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Merge branch 'stable-4.11' of git://git.infradead.org/users/pcmoore/audit
[people/arne_f/kernel.git] / drivers / video / fbdev / tridentfb.c
1 /*
2 * Frame buffer driver for Trident TGUI, Blade and Image series
3 *
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
5 * Copyright 2009 Krzysztof Helt <krzysztof.h1@wp.pl>
6 *
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
13 * code, suggestions
14 * TODO:
15 * timing value tweaking so it looks good on every monitor in every mode
16 */
17
18 #include <linux/module.h>
19 #include <linux/fb.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22 #include <linux/slab.h>
23
24 #include <linux/delay.h>
25 #include <video/vga.h>
26 #include <video/trident.h>
27
28 #include <linux/i2c.h>
29 #include <linux/i2c-algo-bit.h>
30
31 struct tridentfb_par {
32 void __iomem *io_virt; /* iospace virtual memory address */
33 u32 pseudo_pal[16];
34 int chip_id;
35 int flatpanel;
36 void (*init_accel) (struct tridentfb_par *, int, int);
37 void (*wait_engine) (struct tridentfb_par *);
38 void (*fill_rect)
39 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
40 void (*copy_rect)
41 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
42 void (*image_blit)
43 (struct tridentfb_par *par, const char*,
44 u32, u32, u32, u32, u32, u32);
45 unsigned char eng_oper; /* engine operation... */
46 bool ddc_registered;
47 struct i2c_adapter ddc_adapter;
48 struct i2c_algo_bit_data ddc_algo;
49 };
50
51 static struct fb_fix_screeninfo tridentfb_fix = {
52 .id = "Trident",
53 .type = FB_TYPE_PACKED_PIXELS,
54 .ypanstep = 1,
55 .visual = FB_VISUAL_PSEUDOCOLOR,
56 .accel = FB_ACCEL_NONE,
57 };
58
59 /* defaults which are normally overriden by user values */
60
61 /* video mode */
62 static char *mode_option;
63 static int bpp = 8;
64
65 static int noaccel;
66
67 static int center;
68 static int stretch;
69
70 static int fp;
71 static int crt;
72
73 static int memsize;
74 static int memdiff;
75 static int nativex;
76
77 module_param(mode_option, charp, 0);
78 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
79 module_param_named(mode, mode_option, charp, 0);
80 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
81 module_param(bpp, int, 0);
82 module_param(center, int, 0);
83 module_param(stretch, int, 0);
84 module_param(noaccel, int, 0);
85 module_param(memsize, int, 0);
86 module_param(memdiff, int, 0);
87 module_param(nativex, int, 0);
88 module_param(fp, int, 0);
89 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
90 module_param(crt, int, 0);
91 MODULE_PARM_DESC(crt, "Define if CRT is connected");
92
93 static inline int is_oldclock(int id)
94 {
95 return (id == TGUI9440) ||
96 (id == TGUI9660) ||
97 (id == CYBER9320);
98 }
99
100 static inline int is_oldprotect(int id)
101 {
102 return is_oldclock(id) ||
103 (id == PROVIDIA9685) ||
104 (id == CYBER9382) ||
105 (id == CYBER9385);
106 }
107
108 static inline int is_blade(int id)
109 {
110 return (id == BLADE3D) ||
111 (id == CYBERBLADEE4) ||
112 (id == CYBERBLADEi7) ||
113 (id == CYBERBLADEi7D) ||
114 (id == CYBERBLADEi1) ||
115 (id == CYBERBLADEi1D) ||
116 (id == CYBERBLADEAi1) ||
117 (id == CYBERBLADEAi1D);
118 }
119
120 static inline int is_xp(int id)
121 {
122 return (id == CYBERBLADEXPAi1) ||
123 (id == CYBERBLADEXPm8) ||
124 (id == CYBERBLADEXPm16);
125 }
126
127 static inline int is3Dchip(int id)
128 {
129 return is_blade(id) || is_xp(id) ||
130 (id == CYBER9397) || (id == CYBER9397DVD) ||
131 (id == CYBER9520) || (id == CYBER9525DVD) ||
132 (id == IMAGE975) || (id == IMAGE985);
133 }
134
135 static inline int iscyber(int id)
136 {
137 switch (id) {
138 case CYBER9388:
139 case CYBER9382:
140 case CYBER9385:
141 case CYBER9397:
142 case CYBER9397DVD:
143 case CYBER9520:
144 case CYBER9525DVD:
145 case CYBERBLADEE4:
146 case CYBERBLADEi7D:
147 case CYBERBLADEi1:
148 case CYBERBLADEi1D:
149 case CYBERBLADEAi1:
150 case CYBERBLADEAi1D:
151 case CYBERBLADEXPAi1:
152 return 1;
153
154 case CYBER9320:
155 case CYBERBLADEi7: /* VIA MPV4 integrated version */
156 default:
157 /* case CYBERBLDAEXPm8: Strange */
158 /* case CYBERBLDAEXPm16: Strange */
159 return 0;
160 }
161 }
162
163 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
164 {
165 fb_writeb(val, p->io_virt + reg);
166 }
167
168 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
169 {
170 return fb_readb(p->io_virt + reg);
171 }
172
173 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
174 {
175 fb_writel(v, par->io_virt + r);
176 }
177
178 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
179 {
180 return fb_readl(par->io_virt + r);
181 }
182
183 #define DDC_SDA_TGUI BIT(0)
184 #define DDC_SCL_TGUI BIT(1)
185 #define DDC_SCL_DRIVE_TGUI BIT(2)
186 #define DDC_SDA_DRIVE_TGUI BIT(3)
187 #define DDC_MASK_TGUI (DDC_SCL_DRIVE_TGUI | DDC_SDA_DRIVE_TGUI)
188
189 static void tridentfb_ddc_setscl_tgui(void *data, int val)
190 {
191 struct tridentfb_par *par = data;
192 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
193
194 if (val)
195 reg &= ~DDC_SCL_DRIVE_TGUI; /* disable drive - don't drive hi */
196 else
197 reg |= DDC_SCL_DRIVE_TGUI; /* drive low */
198
199 vga_mm_wcrt(par->io_virt, I2C, reg);
200 }
201
202 static void tridentfb_ddc_setsda_tgui(void *data, int val)
203 {
204 struct tridentfb_par *par = data;
205 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
206
207 if (val)
208 reg &= ~DDC_SDA_DRIVE_TGUI; /* disable drive - don't drive hi */
209 else
210 reg |= DDC_SDA_DRIVE_TGUI; /* drive low */
211
212 vga_mm_wcrt(par->io_virt, I2C, reg);
213 }
214
215 static int tridentfb_ddc_getsda_tgui(void *data)
216 {
217 struct tridentfb_par *par = data;
218
219 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_TGUI);
220 }
221
222 #define DDC_SDA_IN BIT(0)
223 #define DDC_SCL_OUT BIT(1)
224 #define DDC_SDA_OUT BIT(3)
225 #define DDC_SCL_IN BIT(6)
226 #define DDC_MASK (DDC_SCL_OUT | DDC_SDA_OUT)
227
228 static void tridentfb_ddc_setscl(void *data, int val)
229 {
230 struct tridentfb_par *par = data;
231 unsigned char reg;
232
233 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
234 if (val)
235 reg |= DDC_SCL_OUT;
236 else
237 reg &= ~DDC_SCL_OUT;
238 vga_mm_wcrt(par->io_virt, I2C, reg);
239 }
240
241 static void tridentfb_ddc_setsda(void *data, int val)
242 {
243 struct tridentfb_par *par = data;
244 unsigned char reg;
245
246 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
247 if (!val)
248 reg |= DDC_SDA_OUT;
249 else
250 reg &= ~DDC_SDA_OUT;
251 vga_mm_wcrt(par->io_virt, I2C, reg);
252 }
253
254 static int tridentfb_ddc_getscl(void *data)
255 {
256 struct tridentfb_par *par = data;
257
258 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SCL_IN);
259 }
260
261 static int tridentfb_ddc_getsda(void *data)
262 {
263 struct tridentfb_par *par = data;
264
265 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_IN);
266 }
267
268 static int tridentfb_setup_ddc_bus(struct fb_info *info)
269 {
270 struct tridentfb_par *par = info->par;
271
272 strlcpy(par->ddc_adapter.name, info->fix.id,
273 sizeof(par->ddc_adapter.name));
274 par->ddc_adapter.owner = THIS_MODULE;
275 par->ddc_adapter.class = I2C_CLASS_DDC;
276 par->ddc_adapter.algo_data = &par->ddc_algo;
277 par->ddc_adapter.dev.parent = info->device;
278 if (is_oldclock(par->chip_id)) { /* not sure if this check is OK */
279 par->ddc_algo.setsda = tridentfb_ddc_setsda_tgui;
280 par->ddc_algo.setscl = tridentfb_ddc_setscl_tgui;
281 par->ddc_algo.getsda = tridentfb_ddc_getsda_tgui;
282 /* no getscl */
283 } else {
284 par->ddc_algo.setsda = tridentfb_ddc_setsda;
285 par->ddc_algo.setscl = tridentfb_ddc_setscl;
286 par->ddc_algo.getsda = tridentfb_ddc_getsda;
287 par->ddc_algo.getscl = tridentfb_ddc_getscl;
288 }
289 par->ddc_algo.udelay = 10;
290 par->ddc_algo.timeout = 20;
291 par->ddc_algo.data = par;
292
293 i2c_set_adapdata(&par->ddc_adapter, par);
294
295 return i2c_bit_add_bus(&par->ddc_adapter);
296 }
297
298 /*
299 * Blade specific acceleration.
300 */
301
302 #define point(x, y) ((y) << 16 | (x))
303
304 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
305 {
306 int v1 = (pitch >> 3) << 20;
307 int tmp = bpp == 24 ? 2 : (bpp >> 4);
308 int v2 = v1 | (tmp << 29);
309
310 writemmr(par, 0x21C0, v2);
311 writemmr(par, 0x21C4, v2);
312 writemmr(par, 0x21B8, v2);
313 writemmr(par, 0x21BC, v2);
314 writemmr(par, 0x21D0, v1);
315 writemmr(par, 0x21D4, v1);
316 writemmr(par, 0x21C8, v1);
317 writemmr(par, 0x21CC, v1);
318 writemmr(par, 0x216C, 0);
319 }
320
321 static void blade_wait_engine(struct tridentfb_par *par)
322 {
323 while (readmmr(par, STATUS) & 0xFA800000)
324 cpu_relax();
325 }
326
327 static void blade_fill_rect(struct tridentfb_par *par,
328 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
329 {
330 writemmr(par, COLOR, c);
331 writemmr(par, ROP, rop ? ROP_X : ROP_S);
332 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
333
334 writemmr(par, DST1, point(x, y));
335 writemmr(par, DST2, point(x + w - 1, y + h - 1));
336 }
337
338 static void blade_image_blit(struct tridentfb_par *par, const char *data,
339 u32 x, u32 y, u32 w, u32 h, u32 c, u32 b)
340 {
341 unsigned size = ((w + 31) >> 5) * h;
342
343 writemmr(par, COLOR, c);
344 writemmr(par, BGCOLOR, b);
345 writemmr(par, CMD, 0xa0000000 | 3 << 19);
346
347 writemmr(par, DST1, point(x, y));
348 writemmr(par, DST2, point(x + w - 1, y + h - 1));
349
350 iowrite32_rep(par->io_virt + 0x10000, data, size);
351 }
352
353 static void blade_copy_rect(struct tridentfb_par *par,
354 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
355 {
356 int direction = 2;
357 u32 s1 = point(x1, y1);
358 u32 s2 = point(x1 + w - 1, y1 + h - 1);
359 u32 d1 = point(x2, y2);
360 u32 d2 = point(x2 + w - 1, y2 + h - 1);
361
362 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
363 direction = 0;
364
365 writemmr(par, ROP, ROP_S);
366 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
367
368 writemmr(par, SRC1, direction ? s2 : s1);
369 writemmr(par, SRC2, direction ? s1 : s2);
370 writemmr(par, DST1, direction ? d2 : d1);
371 writemmr(par, DST2, direction ? d1 : d2);
372 }
373
374 /*
375 * BladeXP specific acceleration functions
376 */
377
378 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
379 {
380 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
381 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
382
383 switch (pitch << (bpp >> 3)) {
384 case 8192:
385 case 512:
386 x |= 0x00;
387 break;
388 case 1024:
389 x |= 0x04;
390 break;
391 case 2048:
392 x |= 0x08;
393 break;
394 case 4096:
395 x |= 0x0C;
396 break;
397 }
398
399 t_outb(par, x, 0x2125);
400
401 par->eng_oper = x | 0x40;
402
403 writemmr(par, 0x2154, v1);
404 writemmr(par, 0x2150, v1);
405 t_outb(par, 3, 0x2126);
406 }
407
408 static void xp_wait_engine(struct tridentfb_par *par)
409 {
410 int count = 0;
411 int timeout = 0;
412
413 while (t_inb(par, STATUS) & 0x80) {
414 count++;
415 if (count == 10000000) {
416 /* Timeout */
417 count = 9990000;
418 timeout++;
419 if (timeout == 8) {
420 /* Reset engine */
421 t_outb(par, 0x00, STATUS);
422 return;
423 }
424 }
425 cpu_relax();
426 }
427 }
428
429 static void xp_fill_rect(struct tridentfb_par *par,
430 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
431 {
432 writemmr(par, 0x2127, ROP_P);
433 writemmr(par, 0x2158, c);
434 writemmr(par, DRAWFL, 0x4000);
435 writemmr(par, OLDDIM, point(h, w));
436 writemmr(par, OLDDST, point(y, x));
437 t_outb(par, 0x01, OLDCMD);
438 t_outb(par, par->eng_oper, 0x2125);
439 }
440
441 static void xp_copy_rect(struct tridentfb_par *par,
442 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
443 {
444 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
445 int direction = 0x0004;
446
447 if ((x1 < x2) && (y1 == y2)) {
448 direction |= 0x0200;
449 x1_tmp = x1 + w - 1;
450 x2_tmp = x2 + w - 1;
451 } else {
452 x1_tmp = x1;
453 x2_tmp = x2;
454 }
455
456 if (y1 < y2) {
457 direction |= 0x0100;
458 y1_tmp = y1 + h - 1;
459 y2_tmp = y2 + h - 1;
460 } else {
461 y1_tmp = y1;
462 y2_tmp = y2;
463 }
464
465 writemmr(par, DRAWFL, direction);
466 t_outb(par, ROP_S, 0x2127);
467 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
468 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
469 writemmr(par, OLDDIM, point(h, w));
470 t_outb(par, 0x01, OLDCMD);
471 }
472
473 /*
474 * Image specific acceleration functions
475 */
476 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
477 {
478 int tmp = bpp == 24 ? 2: (bpp >> 4);
479
480 writemmr(par, 0x2120, 0xF0000000);
481 writemmr(par, 0x2120, 0x40000000 | tmp);
482 writemmr(par, 0x2120, 0x80000000);
483 writemmr(par, 0x2144, 0x00000000);
484 writemmr(par, 0x2148, 0x00000000);
485 writemmr(par, 0x2150, 0x00000000);
486 writemmr(par, 0x2154, 0x00000000);
487 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
488 writemmr(par, 0x216C, 0x00000000);
489 writemmr(par, 0x2170, 0x00000000);
490 writemmr(par, 0x217C, 0x00000000);
491 writemmr(par, 0x2120, 0x10000000);
492 writemmr(par, 0x2130, (2047 << 16) | 2047);
493 }
494
495 static void image_wait_engine(struct tridentfb_par *par)
496 {
497 while (readmmr(par, 0x2164) & 0xF0000000)
498 cpu_relax();
499 }
500
501 static void image_fill_rect(struct tridentfb_par *par,
502 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
503 {
504 writemmr(par, 0x2120, 0x80000000);
505 writemmr(par, 0x2120, 0x90000000 | ROP_S);
506
507 writemmr(par, 0x2144, c);
508
509 writemmr(par, DST1, point(x, y));
510 writemmr(par, DST2, point(x + w - 1, y + h - 1));
511
512 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
513 }
514
515 static void image_copy_rect(struct tridentfb_par *par,
516 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
517 {
518 int direction = 0x4;
519 u32 s1 = point(x1, y1);
520 u32 s2 = point(x1 + w - 1, y1 + h - 1);
521 u32 d1 = point(x2, y2);
522 u32 d2 = point(x2 + w - 1, y2 + h - 1);
523
524 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
525 direction = 0;
526
527 writemmr(par, 0x2120, 0x80000000);
528 writemmr(par, 0x2120, 0x90000000 | ROP_S);
529
530 writemmr(par, SRC1, direction ? s2 : s1);
531 writemmr(par, SRC2, direction ? s1 : s2);
532 writemmr(par, DST1, direction ? d2 : d1);
533 writemmr(par, DST2, direction ? d1 : d2);
534 writemmr(par, 0x2124,
535 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
536 }
537
538 /*
539 * TGUI 9440/96XX acceleration
540 */
541
542 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
543 {
544 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
545
546 /* disable clipping */
547 writemmr(par, 0x2148, 0);
548 writemmr(par, 0x214C, point(4095, 2047));
549
550 switch ((pitch * bpp) / 8) {
551 case 8192:
552 case 512:
553 x |= 0x00;
554 break;
555 case 1024:
556 x |= 0x04;
557 break;
558 case 2048:
559 x |= 0x08;
560 break;
561 case 4096:
562 x |= 0x0C;
563 break;
564 }
565
566 fb_writew(x, par->io_virt + 0x2122);
567 }
568
569 static void tgui_fill_rect(struct tridentfb_par *par,
570 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
571 {
572 t_outb(par, ROP_P, 0x2127);
573 writemmr(par, OLDCLR, c);
574 writemmr(par, DRAWFL, 0x4020);
575 writemmr(par, OLDDIM, point(w - 1, h - 1));
576 writemmr(par, OLDDST, point(x, y));
577 t_outb(par, 1, OLDCMD);
578 }
579
580 static void tgui_copy_rect(struct tridentfb_par *par,
581 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
582 {
583 int flags = 0;
584 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
585
586 if ((x1 < x2) && (y1 == y2)) {
587 flags |= 0x0200;
588 x1_tmp = x1 + w - 1;
589 x2_tmp = x2 + w - 1;
590 } else {
591 x1_tmp = x1;
592 x2_tmp = x2;
593 }
594
595 if (y1 < y2) {
596 flags |= 0x0100;
597 y1_tmp = y1 + h - 1;
598 y2_tmp = y2 + h - 1;
599 } else {
600 y1_tmp = y1;
601 y2_tmp = y2;
602 }
603
604 writemmr(par, DRAWFL, 0x4 | flags);
605 t_outb(par, ROP_S, 0x2127);
606 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
607 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
608 writemmr(par, OLDDIM, point(w - 1, h - 1));
609 t_outb(par, 1, OLDCMD);
610 }
611
612 /*
613 * Accel functions called by the upper layers
614 */
615 static void tridentfb_fillrect(struct fb_info *info,
616 const struct fb_fillrect *fr)
617 {
618 struct tridentfb_par *par = info->par;
619 int col;
620
621 if (info->flags & FBINFO_HWACCEL_DISABLED) {
622 cfb_fillrect(info, fr);
623 return;
624 }
625 if (info->var.bits_per_pixel == 8) {
626 col = fr->color;
627 col |= col << 8;
628 col |= col << 16;
629 } else
630 col = ((u32 *)(info->pseudo_palette))[fr->color];
631
632 par->wait_engine(par);
633 par->fill_rect(par, fr->dx, fr->dy, fr->width,
634 fr->height, col, fr->rop);
635 }
636
637 static void tridentfb_imageblit(struct fb_info *info,
638 const struct fb_image *img)
639 {
640 struct tridentfb_par *par = info->par;
641 int col, bgcol;
642
643 if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) {
644 cfb_imageblit(info, img);
645 return;
646 }
647 if (info->var.bits_per_pixel == 8) {
648 col = img->fg_color;
649 col |= col << 8;
650 col |= col << 16;
651 bgcol = img->bg_color;
652 bgcol |= bgcol << 8;
653 bgcol |= bgcol << 16;
654 } else {
655 col = ((u32 *)(info->pseudo_palette))[img->fg_color];
656 bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color];
657 }
658
659 par->wait_engine(par);
660 if (par->image_blit)
661 par->image_blit(par, img->data, img->dx, img->dy,
662 img->width, img->height, col, bgcol);
663 else
664 cfb_imageblit(info, img);
665 }
666
667 static void tridentfb_copyarea(struct fb_info *info,
668 const struct fb_copyarea *ca)
669 {
670 struct tridentfb_par *par = info->par;
671
672 if (info->flags & FBINFO_HWACCEL_DISABLED) {
673 cfb_copyarea(info, ca);
674 return;
675 }
676 par->wait_engine(par);
677 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
678 ca->width, ca->height);
679 }
680
681 static int tridentfb_sync(struct fb_info *info)
682 {
683 struct tridentfb_par *par = info->par;
684
685 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
686 par->wait_engine(par);
687 return 0;
688 }
689
690 /*
691 * Hardware access functions
692 */
693
694 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
695 {
696 return vga_mm_rcrt(par->io_virt, reg);
697 }
698
699 static inline void write3X4(struct tridentfb_par *par, int reg,
700 unsigned char val)
701 {
702 vga_mm_wcrt(par->io_virt, reg, val);
703 }
704
705 static inline unsigned char read3CE(struct tridentfb_par *par,
706 unsigned char reg)
707 {
708 return vga_mm_rgfx(par->io_virt, reg);
709 }
710
711 static inline void writeAttr(struct tridentfb_par *par, int reg,
712 unsigned char val)
713 {
714 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
715 vga_mm_wattr(par->io_virt, reg, val);
716 }
717
718 static inline void write3CE(struct tridentfb_par *par, int reg,
719 unsigned char val)
720 {
721 vga_mm_wgfx(par->io_virt, reg, val);
722 }
723
724 static void enable_mmio(struct tridentfb_par *par)
725 {
726 /* Goto New Mode */
727 vga_io_rseq(0x0B);
728
729 /* Unprotect registers */
730 vga_io_wseq(NewMode1, 0x80);
731 if (!is_oldprotect(par->chip_id))
732 vga_io_wseq(Protection, 0x92);
733
734 /* Enable MMIO */
735 outb(PCIReg, 0x3D4);
736 outb(inb(0x3D5) | 0x01, 0x3D5);
737 }
738
739 static void disable_mmio(struct tridentfb_par *par)
740 {
741 /* Goto New Mode */
742 vga_mm_rseq(par->io_virt, 0x0B);
743
744 /* Unprotect registers */
745 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
746 if (!is_oldprotect(par->chip_id))
747 vga_mm_wseq(par->io_virt, Protection, 0x92);
748
749 /* Disable MMIO */
750 t_outb(par, PCIReg, 0x3D4);
751 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
752 }
753
754 static inline void crtc_unlock(struct tridentfb_par *par)
755 {
756 write3X4(par, VGA_CRTC_V_SYNC_END,
757 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
758 }
759
760 /* Return flat panel's maximum x resolution */
761 static int get_nativex(struct tridentfb_par *par)
762 {
763 int x, y, tmp;
764
765 if (nativex)
766 return nativex;
767
768 tmp = (read3CE(par, VertStretch) >> 4) & 3;
769
770 switch (tmp) {
771 case 0:
772 x = 1280; y = 1024;
773 break;
774 case 2:
775 x = 1024; y = 768;
776 break;
777 case 3:
778 x = 800; y = 600;
779 break;
780 case 4:
781 x = 1400; y = 1050;
782 break;
783 case 1:
784 default:
785 x = 640; y = 480;
786 break;
787 }
788
789 output("%dx%d flat panel found\n", x, y);
790 return x;
791 }
792
793 /* Set pitch */
794 static inline void set_lwidth(struct tridentfb_par *par, int width)
795 {
796 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
797 /* chips older than TGUI9660 have only 1 width bit in AddColReg */
798 /* touching the other one breaks I2C/DDC */
799 if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320)
800 write3X4(par, AddColReg,
801 (read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4));
802 else
803 write3X4(par, AddColReg,
804 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
805 }
806
807 /* For resolutions smaller than FP resolution stretch */
808 static void screen_stretch(struct tridentfb_par *par)
809 {
810 if (par->chip_id != CYBERBLADEXPAi1)
811 write3CE(par, BiosReg, 0);
812 else
813 write3CE(par, BiosReg, 8);
814 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
815 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
816 }
817
818 /* For resolutions smaller than FP resolution center */
819 static inline void screen_center(struct tridentfb_par *par)
820 {
821 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
822 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
823 }
824
825 /* Address of first shown pixel in display memory */
826 static void set_screen_start(struct tridentfb_par *par, int base)
827 {
828 u8 tmp;
829 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
830 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
831 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
832 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
833 tmp = read3X4(par, CRTHiOrd) & 0xF8;
834 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
835 }
836
837 /* Set dotclock frequency */
838 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
839 {
840 int m, n, k;
841 unsigned long fi, d, di;
842 unsigned char best_m = 0, best_n = 0, best_k = 0;
843 unsigned char hi, lo;
844 unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
845
846 d = 20000;
847 for (k = shift; k >= 0; k--)
848 for (m = 1; m < 32; m++) {
849 n = ((m + 2) << shift) - 8;
850 for (n = (n < 0 ? 0 : n); n < 122; n++) {
851 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
852 di = abs(fi - freq);
853 if (di < d || (di == d && k == best_k)) {
854 d = di;
855 best_n = n;
856 best_m = m;
857 best_k = k;
858 }
859 if (fi > freq)
860 break;
861 }
862 }
863
864 if (is_oldclock(par->chip_id)) {
865 lo = best_n | (best_m << 7);
866 hi = (best_m >> 1) | (best_k << 4);
867 } else {
868 lo = best_n;
869 hi = best_m | (best_k << 6);
870 }
871
872 if (is3Dchip(par->chip_id)) {
873 vga_mm_wseq(par->io_virt, ClockHigh, hi);
874 vga_mm_wseq(par->io_virt, ClockLow, lo);
875 } else {
876 t_outb(par, lo, 0x43C8);
877 t_outb(par, hi, 0x43C9);
878 }
879 debug("VCLK = %X %X\n", hi, lo);
880 }
881
882 /* Set number of lines for flat panels*/
883 static void set_number_of_lines(struct tridentfb_par *par, int lines)
884 {
885 int tmp = read3CE(par, CyberEnhance) & 0x8F;
886 if (lines > 1024)
887 tmp |= 0x50;
888 else if (lines > 768)
889 tmp |= 0x30;
890 else if (lines > 600)
891 tmp |= 0x20;
892 else if (lines > 480)
893 tmp |= 0x10;
894 write3CE(par, CyberEnhance, tmp);
895 }
896
897 /*
898 * If we see that FP is active we assume we have one.
899 * Otherwise we have a CRT display. User can override.
900 */
901 static int is_flatpanel(struct tridentfb_par *par)
902 {
903 if (fp)
904 return 1;
905 if (crt || !iscyber(par->chip_id))
906 return 0;
907 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
908 }
909
910 /* Try detecting the video memory size */
911 static unsigned int get_memsize(struct tridentfb_par *par)
912 {
913 unsigned char tmp, tmp2;
914 unsigned int k;
915
916 /* If memory size provided by user */
917 if (memsize)
918 k = memsize * Kb;
919 else
920 switch (par->chip_id) {
921 case CYBER9525DVD:
922 k = 2560 * Kb;
923 break;
924 default:
925 tmp = read3X4(par, SPR) & 0x0F;
926 switch (tmp) {
927
928 case 0x01:
929 k = 512 * Kb;
930 break;
931 case 0x02:
932 k = 6 * Mb; /* XP */
933 break;
934 case 0x03:
935 k = 1 * Mb;
936 break;
937 case 0x04:
938 k = 8 * Mb;
939 break;
940 case 0x06:
941 k = 10 * Mb; /* XP */
942 break;
943 case 0x07:
944 k = 2 * Mb;
945 break;
946 case 0x08:
947 k = 12 * Mb; /* XP */
948 break;
949 case 0x0A:
950 k = 14 * Mb; /* XP */
951 break;
952 case 0x0C:
953 k = 16 * Mb; /* XP */
954 break;
955 case 0x0E: /* XP */
956
957 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
958 switch (tmp2) {
959 case 0x00:
960 k = 20 * Mb;
961 break;
962 case 0x01:
963 k = 24 * Mb;
964 break;
965 case 0x10:
966 k = 28 * Mb;
967 break;
968 case 0x11:
969 k = 32 * Mb;
970 break;
971 default:
972 k = 1 * Mb;
973 break;
974 }
975 break;
976
977 case 0x0F:
978 k = 4 * Mb;
979 break;
980 default:
981 k = 1 * Mb;
982 break;
983 }
984 }
985
986 k -= memdiff * Kb;
987 output("framebuffer size = %d Kb\n", k / Kb);
988 return k;
989 }
990
991 /* See if we can handle the video mode described in var */
992 static int tridentfb_check_var(struct fb_var_screeninfo *var,
993 struct fb_info *info)
994 {
995 struct tridentfb_par *par = info->par;
996 int bpp = var->bits_per_pixel;
997 int line_length;
998 int ramdac = 230000; /* 230MHz for most 3D chips */
999 debug("enter\n");
1000
1001 /* check color depth */
1002 if (bpp == 24)
1003 bpp = var->bits_per_pixel = 32;
1004 if (bpp != 8 && bpp != 16 && bpp != 32)
1005 return -EINVAL;
1006 if (par->chip_id == TGUI9440 && bpp == 32)
1007 return -EINVAL;
1008 /* check whether resolution fits on panel and in memory */
1009 if (par->flatpanel && nativex && var->xres > nativex)
1010 return -EINVAL;
1011 /* various resolution checks */
1012 var->xres = (var->xres + 7) & ~0x7;
1013 if (var->xres > var->xres_virtual)
1014 var->xres_virtual = var->xres;
1015 if (var->yres > var->yres_virtual)
1016 var->yres_virtual = var->yres;
1017 if (var->xres_virtual > 4095 || var->yres > 2048)
1018 return -EINVAL;
1019 /* prevent from position overflow for acceleration */
1020 if (var->yres_virtual > 0xffff)
1021 return -EINVAL;
1022 line_length = var->xres_virtual * bpp / 8;
1023
1024 if (!is3Dchip(par->chip_id) &&
1025 !(info->flags & FBINFO_HWACCEL_DISABLED)) {
1026 /* acceleration requires line length to be power of 2 */
1027 if (line_length <= 512)
1028 var->xres_virtual = 512 * 8 / bpp;
1029 else if (line_length <= 1024)
1030 var->xres_virtual = 1024 * 8 / bpp;
1031 else if (line_length <= 2048)
1032 var->xres_virtual = 2048 * 8 / bpp;
1033 else if (line_length <= 4096)
1034 var->xres_virtual = 4096 * 8 / bpp;
1035 else if (line_length <= 8192)
1036 var->xres_virtual = 8192 * 8 / bpp;
1037 else
1038 return -EINVAL;
1039
1040 line_length = var->xres_virtual * bpp / 8;
1041 }
1042
1043 /* datasheet specifies how to set panning only up to 4 MB */
1044 if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
1045 var->yres_virtual = ((4 << 20) / line_length) + var->yres;
1046
1047 if (line_length * var->yres_virtual > info->fix.smem_len)
1048 return -EINVAL;
1049
1050 switch (bpp) {
1051 case 8:
1052 var->red.offset = 0;
1053 var->red.length = 8;
1054 var->green = var->red;
1055 var->blue = var->red;
1056 break;
1057 case 16:
1058 var->red.offset = 11;
1059 var->green.offset = 5;
1060 var->blue.offset = 0;
1061 var->red.length = 5;
1062 var->green.length = 6;
1063 var->blue.length = 5;
1064 break;
1065 case 32:
1066 var->red.offset = 16;
1067 var->green.offset = 8;
1068 var->blue.offset = 0;
1069 var->red.length = 8;
1070 var->green.length = 8;
1071 var->blue.length = 8;
1072 break;
1073 default:
1074 return -EINVAL;
1075 }
1076
1077 if (is_xp(par->chip_id))
1078 ramdac = 350000;
1079
1080 switch (par->chip_id) {
1081 case TGUI9440:
1082 ramdac = (bpp >= 16) ? 45000 : 90000;
1083 break;
1084 case CYBER9320:
1085 case TGUI9660:
1086 ramdac = 135000;
1087 break;
1088 case PROVIDIA9685:
1089 case CYBER9388:
1090 case CYBER9382:
1091 case CYBER9385:
1092 ramdac = 170000;
1093 break;
1094 }
1095
1096 /* The clock is doubled for 32 bpp */
1097 if (bpp == 32)
1098 ramdac /= 2;
1099
1100 if (PICOS2KHZ(var->pixclock) > ramdac)
1101 return -EINVAL;
1102
1103 debug("exit\n");
1104
1105 return 0;
1106
1107 }
1108
1109 /* Pan the display */
1110 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
1111 struct fb_info *info)
1112 {
1113 struct tridentfb_par *par = info->par;
1114 unsigned int offset;
1115
1116 debug("enter\n");
1117 offset = (var->xoffset + (var->yoffset * info->var.xres_virtual))
1118 * info->var.bits_per_pixel / 32;
1119 set_screen_start(par, offset);
1120 debug("exit\n");
1121 return 0;
1122 }
1123
1124 static inline void shadowmode_on(struct tridentfb_par *par)
1125 {
1126 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1127 }
1128
1129 static inline void shadowmode_off(struct tridentfb_par *par)
1130 {
1131 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
1132 }
1133
1134 /* Set the hardware to the requested video mode */
1135 static int tridentfb_set_par(struct fb_info *info)
1136 {
1137 struct tridentfb_par *par = info->par;
1138 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
1139 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
1140 struct fb_var_screeninfo *var = &info->var;
1141 int bpp = var->bits_per_pixel;
1142 unsigned char tmp;
1143 unsigned long vclk;
1144
1145 debug("enter\n");
1146 hdispend = var->xres / 8 - 1;
1147 hsyncstart = (var->xres + var->right_margin) / 8;
1148 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
1149 htotal = (var->xres + var->left_margin + var->right_margin +
1150 var->hsync_len) / 8 - 5;
1151 hblankstart = hdispend + 1;
1152 hblankend = htotal + 3;
1153
1154 vdispend = var->yres - 1;
1155 vsyncstart = var->yres + var->lower_margin;
1156 vsyncend = vsyncstart + var->vsync_len;
1157 vtotal = var->upper_margin + vsyncend - 2;
1158 vblankstart = vdispend + 1;
1159 vblankend = vtotal;
1160
1161 if (info->var.vmode & FB_VMODE_INTERLACED) {
1162 vtotal /= 2;
1163 vdispend /= 2;
1164 vsyncstart /= 2;
1165 vsyncend /= 2;
1166 vblankstart /= 2;
1167 vblankend /= 2;
1168 }
1169
1170 enable_mmio(par);
1171 crtc_unlock(par);
1172 write3CE(par, CyberControl, 8);
1173 tmp = 0xEB;
1174 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1175 tmp &= ~0x40;
1176 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1177 tmp &= ~0x80;
1178
1179 if (par->flatpanel && var->xres < nativex) {
1180 /*
1181 * on flat panels with native size larger
1182 * than requested resolution decide whether
1183 * we stretch or center
1184 */
1185 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1186
1187 shadowmode_on(par);
1188
1189 if (center)
1190 screen_center(par);
1191 else if (stretch)
1192 screen_stretch(par);
1193
1194 } else {
1195 t_outb(par, tmp, VGA_MIS_W);
1196 write3CE(par, CyberControl, 8);
1197 }
1198
1199 /* vertical timing values */
1200 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1201 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1202 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1203 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1204 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1205 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1206
1207 /* horizontal timing values */
1208 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1209 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1210 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1211 write3X4(par, VGA_CRTC_H_SYNC_END,
1212 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1213 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1214 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1215
1216 /* higher bits of vertical timing values */
1217 tmp = 0x10;
1218 if (vtotal & 0x100) tmp |= 0x01;
1219 if (vdispend & 0x100) tmp |= 0x02;
1220 if (vsyncstart & 0x100) tmp |= 0x04;
1221 if (vblankstart & 0x100) tmp |= 0x08;
1222
1223 if (vtotal & 0x200) tmp |= 0x20;
1224 if (vdispend & 0x200) tmp |= 0x40;
1225 if (vsyncstart & 0x200) tmp |= 0x80;
1226 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1227
1228 tmp = read3X4(par, CRTHiOrd) & 0x07;
1229 tmp |= 0x08; /* line compare bit 10 */
1230 if (vtotal & 0x400) tmp |= 0x80;
1231 if (vblankstart & 0x400) tmp |= 0x40;
1232 if (vsyncstart & 0x400) tmp |= 0x20;
1233 if (vdispend & 0x400) tmp |= 0x10;
1234 write3X4(par, CRTHiOrd, tmp);
1235
1236 tmp = (htotal >> 8) & 0x01;
1237 tmp |= (hdispend >> 7) & 0x02;
1238 tmp |= (hsyncstart >> 5) & 0x08;
1239 tmp |= (hblankstart >> 4) & 0x10;
1240 write3X4(par, HorizOverflow, tmp);
1241
1242 tmp = 0x40;
1243 if (vblankstart & 0x200) tmp |= 0x20;
1244 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1245 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1246
1247 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1248 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1249 write3X4(par, VGA_CRTC_MODE, 0xC3);
1250
1251 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1252
1253 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1254 /* enable access extended memory */
1255 write3X4(par, CRTCModuleTest, tmp);
1256 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1257 if (info->var.vmode & FB_VMODE_INTERLACED)
1258 tmp |= 0x4;
1259 write3CE(par, MiscIntContReg, tmp);
1260
1261 /* enable GE for text acceleration */
1262 write3X4(par, GraphEngReg, 0x80);
1263
1264 switch (bpp) {
1265 case 8:
1266 tmp = 0x00;
1267 break;
1268 case 16:
1269 tmp = 0x05;
1270 break;
1271 case 24:
1272 tmp = 0x29;
1273 break;
1274 case 32:
1275 tmp = 0x09;
1276 break;
1277 }
1278
1279 write3X4(par, PixelBusReg, tmp);
1280
1281 tmp = read3X4(par, DRAMControl);
1282 if (!is_oldprotect(par->chip_id))
1283 tmp |= 0x10;
1284 if (iscyber(par->chip_id))
1285 tmp |= 0x20;
1286 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1287
1288 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1289 if (!is_xp(par->chip_id))
1290 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1291 /* MMIO & PCI read and write burst enable */
1292 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1293 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1294
1295 vga_mm_wseq(par->io_virt, 0, 3);
1296 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1297 /* enable 4 maps because needed in chain4 mode */
1298 vga_mm_wseq(par->io_virt, 2, 0x0F);
1299 vga_mm_wseq(par->io_virt, 3, 0);
1300 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1301
1302 /* convert from picoseconds to kHz */
1303 vclk = PICOS2KHZ(info->var.pixclock);
1304
1305 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1306 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1307 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1308 tmp |= 8;
1309 vclk *= 2;
1310 }
1311 set_vclk(par, vclk);
1312 write3CE(par, MiscExtFunc, tmp | 0x12);
1313 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1314 write3CE(par, 0x6, 0x05); /* graphics mode */
1315 write3CE(par, 0x7, 0x0F); /* planes? */
1316
1317 /* graphics mode and support 256 color modes */
1318 writeAttr(par, 0x10, 0x41);
1319 writeAttr(par, 0x12, 0x0F); /* planes */
1320 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1321
1322 /* colors */
1323 for (tmp = 0; tmp < 0x10; tmp++)
1324 writeAttr(par, tmp, tmp);
1325 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1326 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1327
1328 switch (bpp) {
1329 case 8:
1330 tmp = 0;
1331 break;
1332 case 16:
1333 tmp = 0x30;
1334 break;
1335 case 24:
1336 case 32:
1337 tmp = 0xD0;
1338 break;
1339 }
1340
1341 t_inb(par, VGA_PEL_IW);
1342 t_inb(par, VGA_PEL_MSK);
1343 t_inb(par, VGA_PEL_MSK);
1344 t_inb(par, VGA_PEL_MSK);
1345 t_inb(par, VGA_PEL_MSK);
1346 t_outb(par, tmp, VGA_PEL_MSK);
1347 t_inb(par, VGA_PEL_IW);
1348
1349 if (par->flatpanel)
1350 set_number_of_lines(par, info->var.yres);
1351 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1352 set_lwidth(par, info->fix.line_length / 8);
1353
1354 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1355 par->init_accel(par, info->var.xres_virtual, bpp);
1356
1357 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1358 info->cmap.len = (bpp == 8) ? 256 : 16;
1359 debug("exit\n");
1360 return 0;
1361 }
1362
1363 /* Set one color register */
1364 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1365 unsigned blue, unsigned transp,
1366 struct fb_info *info)
1367 {
1368 int bpp = info->var.bits_per_pixel;
1369 struct tridentfb_par *par = info->par;
1370
1371 if (regno >= info->cmap.len)
1372 return 1;
1373
1374 if (bpp == 8) {
1375 t_outb(par, 0xFF, VGA_PEL_MSK);
1376 t_outb(par, regno, VGA_PEL_IW);
1377
1378 t_outb(par, red >> 10, VGA_PEL_D);
1379 t_outb(par, green >> 10, VGA_PEL_D);
1380 t_outb(par, blue >> 10, VGA_PEL_D);
1381
1382 } else if (regno < 16) {
1383 if (bpp == 16) { /* RGB 565 */
1384 u32 col;
1385
1386 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1387 ((blue & 0xF800) >> 11);
1388 col |= col << 16;
1389 ((u32 *)(info->pseudo_palette))[regno] = col;
1390 } else if (bpp == 32) /* ARGB 8888 */
1391 ((u32 *)info->pseudo_palette)[regno] =
1392 ((transp & 0xFF00) << 16) |
1393 ((red & 0xFF00) << 8) |
1394 ((green & 0xFF00)) |
1395 ((blue & 0xFF00) >> 8);
1396 }
1397
1398 return 0;
1399 }
1400
1401 /* Try blanking the screen. For flat panels it does nothing */
1402 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1403 {
1404 unsigned char PMCont, DPMSCont;
1405 struct tridentfb_par *par = info->par;
1406
1407 debug("enter\n");
1408 if (par->flatpanel)
1409 return 0;
1410 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1411 PMCont = t_inb(par, 0x83C6) & 0xFC;
1412 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1413 switch (blank_mode) {
1414 case FB_BLANK_UNBLANK:
1415 /* Screen: On, HSync: On, VSync: On */
1416 case FB_BLANK_NORMAL:
1417 /* Screen: Off, HSync: On, VSync: On */
1418 PMCont |= 0x03;
1419 DPMSCont |= 0x00;
1420 break;
1421 case FB_BLANK_HSYNC_SUSPEND:
1422 /* Screen: Off, HSync: Off, VSync: On */
1423 PMCont |= 0x02;
1424 DPMSCont |= 0x01;
1425 break;
1426 case FB_BLANK_VSYNC_SUSPEND:
1427 /* Screen: Off, HSync: On, VSync: Off */
1428 PMCont |= 0x02;
1429 DPMSCont |= 0x02;
1430 break;
1431 case FB_BLANK_POWERDOWN:
1432 /* Screen: Off, HSync: Off, VSync: Off */
1433 PMCont |= 0x00;
1434 DPMSCont |= 0x03;
1435 break;
1436 }
1437
1438 write3CE(par, PowerStatus, DPMSCont);
1439 t_outb(par, 4, 0x83C8);
1440 t_outb(par, PMCont, 0x83C6);
1441
1442 debug("exit\n");
1443
1444 /* let fbcon do a softblank for us */
1445 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1446 }
1447
1448 static struct fb_ops tridentfb_ops = {
1449 .owner = THIS_MODULE,
1450 .fb_setcolreg = tridentfb_setcolreg,
1451 .fb_pan_display = tridentfb_pan_display,
1452 .fb_blank = tridentfb_blank,
1453 .fb_check_var = tridentfb_check_var,
1454 .fb_set_par = tridentfb_set_par,
1455 .fb_fillrect = tridentfb_fillrect,
1456 .fb_copyarea = tridentfb_copyarea,
1457 .fb_imageblit = tridentfb_imageblit,
1458 .fb_sync = tridentfb_sync,
1459 };
1460
1461 static int trident_pci_probe(struct pci_dev *dev,
1462 const struct pci_device_id *id)
1463 {
1464 int err;
1465 unsigned char revision;
1466 struct fb_info *info;
1467 struct tridentfb_par *default_par;
1468 int chip3D;
1469 int chip_id;
1470 bool found = false;
1471
1472 err = pci_enable_device(dev);
1473 if (err)
1474 return err;
1475
1476 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1477 if (!info)
1478 return -ENOMEM;
1479 default_par = info->par;
1480
1481 chip_id = id->device;
1482
1483 /* If PCI id is 0x9660 then further detect chip type */
1484
1485 if (chip_id == TGUI9660) {
1486 revision = vga_io_rseq(RevisionID);
1487
1488 switch (revision) {
1489 case 0x21:
1490 chip_id = PROVIDIA9685;
1491 break;
1492 case 0x22:
1493 case 0x23:
1494 chip_id = CYBER9397;
1495 break;
1496 case 0x2A:
1497 chip_id = CYBER9397DVD;
1498 break;
1499 case 0x30:
1500 case 0x33:
1501 case 0x34:
1502 case 0x35:
1503 case 0x38:
1504 case 0x3A:
1505 case 0xB3:
1506 chip_id = CYBER9385;
1507 break;
1508 case 0x40 ... 0x43:
1509 chip_id = CYBER9382;
1510 break;
1511 case 0x4A:
1512 chip_id = CYBER9388;
1513 break;
1514 default:
1515 break;
1516 }
1517 }
1518
1519 chip3D = is3Dchip(chip_id);
1520
1521 if (is_xp(chip_id)) {
1522 default_par->init_accel = xp_init_accel;
1523 default_par->wait_engine = xp_wait_engine;
1524 default_par->fill_rect = xp_fill_rect;
1525 default_par->copy_rect = xp_copy_rect;
1526 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1527 } else if (is_blade(chip_id)) {
1528 default_par->init_accel = blade_init_accel;
1529 default_par->wait_engine = blade_wait_engine;
1530 default_par->fill_rect = blade_fill_rect;
1531 default_par->copy_rect = blade_copy_rect;
1532 default_par->image_blit = blade_image_blit;
1533 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1534 } else if (chip3D) { /* 3DImage family left */
1535 default_par->init_accel = image_init_accel;
1536 default_par->wait_engine = image_wait_engine;
1537 default_par->fill_rect = image_fill_rect;
1538 default_par->copy_rect = image_copy_rect;
1539 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1540 } else { /* TGUI 9440/96XX family */
1541 default_par->init_accel = tgui_init_accel;
1542 default_par->wait_engine = xp_wait_engine;
1543 default_par->fill_rect = tgui_fill_rect;
1544 default_par->copy_rect = tgui_copy_rect;
1545 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1546 }
1547
1548 default_par->chip_id = chip_id;
1549
1550 /* setup MMIO region */
1551 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1552 tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1553
1554 if (!request_mem_region(tridentfb_fix.mmio_start,
1555 tridentfb_fix.mmio_len, "tridentfb")) {
1556 debug("request_region failed!\n");
1557 framebuffer_release(info);
1558 return -1;
1559 }
1560
1561 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1562 tridentfb_fix.mmio_len);
1563
1564 if (!default_par->io_virt) {
1565 debug("ioremap failed\n");
1566 err = -1;
1567 goto out_unmap1;
1568 }
1569
1570 enable_mmio(default_par);
1571
1572 /* setup framebuffer memory */
1573 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1574 tridentfb_fix.smem_len = get_memsize(default_par);
1575
1576 if (!request_mem_region(tridentfb_fix.smem_start,
1577 tridentfb_fix.smem_len, "tridentfb")) {
1578 debug("request_mem_region failed!\n");
1579 disable_mmio(info->par);
1580 err = -1;
1581 goto out_unmap1;
1582 }
1583
1584 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1585 tridentfb_fix.smem_len);
1586
1587 if (!info->screen_base) {
1588 debug("ioremap failed\n");
1589 err = -1;
1590 goto out_unmap2;
1591 }
1592
1593 default_par->flatpanel = is_flatpanel(default_par);
1594
1595 if (default_par->flatpanel)
1596 nativex = get_nativex(default_par);
1597
1598 info->fix = tridentfb_fix;
1599 info->fbops = &tridentfb_ops;
1600 info->pseudo_palette = default_par->pseudo_pal;
1601
1602 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1603 if (!noaccel && default_par->init_accel) {
1604 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1605 info->flags |= FBINFO_HWACCEL_COPYAREA;
1606 info->flags |= FBINFO_HWACCEL_FILLRECT;
1607 } else
1608 info->flags |= FBINFO_HWACCEL_DISABLED;
1609
1610 if (is_blade(chip_id) && chip_id != BLADE3D)
1611 info->flags |= FBINFO_READS_FAST;
1612
1613 info->pixmap.addr = kmalloc(4096, GFP_KERNEL);
1614 if (!info->pixmap.addr) {
1615 err = -ENOMEM;
1616 goto out_unmap2;
1617 }
1618
1619 info->pixmap.size = 4096;
1620 info->pixmap.buf_align = 4;
1621 info->pixmap.scan_align = 1;
1622 info->pixmap.access_align = 32;
1623 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1624 info->var.bits_per_pixel = 8;
1625
1626 if (default_par->image_blit) {
1627 info->flags |= FBINFO_HWACCEL_IMAGEBLIT;
1628 info->pixmap.scan_align = 4;
1629 }
1630
1631 if (noaccel) {
1632 printk(KERN_DEBUG "disabling acceleration\n");
1633 info->flags |= FBINFO_HWACCEL_DISABLED;
1634 info->pixmap.scan_align = 1;
1635 }
1636
1637 if (tridentfb_setup_ddc_bus(info) == 0) {
1638 u8 *edid = fb_ddc_read(&default_par->ddc_adapter);
1639
1640 default_par->ddc_registered = true;
1641 if (edid) {
1642 fb_edid_to_monspecs(edid, &info->monspecs);
1643 kfree(edid);
1644 if (!info->monspecs.modedb)
1645 dev_err(info->device, "error getting mode database\n");
1646 else {
1647 const struct fb_videomode *m;
1648
1649 fb_videomode_to_modelist(info->monspecs.modedb,
1650 info->monspecs.modedb_len,
1651 &info->modelist);
1652 m = fb_find_best_display(&info->monspecs,
1653 &info->modelist);
1654 if (m) {
1655 fb_videomode_to_var(&info->var, m);
1656 /* fill all other info->var's fields */
1657 if (tridentfb_check_var(&info->var,
1658 info) == 0)
1659 found = true;
1660 }
1661 }
1662 }
1663 }
1664
1665 if (!mode_option && !found)
1666 mode_option = "640x480-8@60";
1667
1668 /* Prepare startup mode */
1669 if (mode_option) {
1670 err = fb_find_mode(&info->var, info, mode_option,
1671 info->monspecs.modedb,
1672 info->monspecs.modedb_len,
1673 NULL, info->var.bits_per_pixel);
1674 if (!err || err == 4) {
1675 err = -EINVAL;
1676 dev_err(info->device, "mode %s not found\n",
1677 mode_option);
1678 fb_destroy_modedb(info->monspecs.modedb);
1679 info->monspecs.modedb = NULL;
1680 goto out_unmap2;
1681 }
1682 }
1683
1684 fb_destroy_modedb(info->monspecs.modedb);
1685 info->monspecs.modedb = NULL;
1686
1687 err = fb_alloc_cmap(&info->cmap, 256, 0);
1688 if (err < 0)
1689 goto out_unmap2;
1690
1691 info->var.activate |= FB_ACTIVATE_NOW;
1692 info->device = &dev->dev;
1693 if (register_framebuffer(info) < 0) {
1694 printk(KERN_ERR "tridentfb: could not register framebuffer\n");
1695 fb_dealloc_cmap(&info->cmap);
1696 err = -EINVAL;
1697 goto out_unmap2;
1698 }
1699 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1700 info->node, info->fix.id, info->var.xres,
1701 info->var.yres, info->var.bits_per_pixel);
1702
1703 pci_set_drvdata(dev, info);
1704 return 0;
1705
1706 out_unmap2:
1707 if (default_par->ddc_registered)
1708 i2c_del_adapter(&default_par->ddc_adapter);
1709 kfree(info->pixmap.addr);
1710 if (info->screen_base)
1711 iounmap(info->screen_base);
1712 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1713 disable_mmio(info->par);
1714 out_unmap1:
1715 if (default_par->io_virt)
1716 iounmap(default_par->io_virt);
1717 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1718 framebuffer_release(info);
1719 return err;
1720 }
1721
1722 static void trident_pci_remove(struct pci_dev *dev)
1723 {
1724 struct fb_info *info = pci_get_drvdata(dev);
1725 struct tridentfb_par *par = info->par;
1726
1727 unregister_framebuffer(info);
1728 if (par->ddc_registered)
1729 i2c_del_adapter(&par->ddc_adapter);
1730 iounmap(par->io_virt);
1731 iounmap(info->screen_base);
1732 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1733 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1734 kfree(info->pixmap.addr);
1735 fb_dealloc_cmap(&info->cmap);
1736 framebuffer_release(info);
1737 }
1738
1739 /* List of boards that we are trying to support */
1740 static struct pci_device_id trident_devices[] = {
1741 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1742 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1743 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1744 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1745 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1746 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1747 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1748 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1749 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1750 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1751 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1752 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1753 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1754 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1755 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1756 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1757 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1758 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1759 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1760 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1761 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1762 {0,}
1763 };
1764
1765 MODULE_DEVICE_TABLE(pci, trident_devices);
1766
1767 static struct pci_driver tridentfb_pci_driver = {
1768 .name = "tridentfb",
1769 .id_table = trident_devices,
1770 .probe = trident_pci_probe,
1771 .remove = trident_pci_remove,
1772 };
1773
1774 /*
1775 * Parse user specified options (`video=trident:')
1776 * example:
1777 * video=trident:800x600,bpp=16,noaccel
1778 */
1779 #ifndef MODULE
1780 static int __init tridentfb_setup(char *options)
1781 {
1782 char *opt;
1783 if (!options || !*options)
1784 return 0;
1785 while ((opt = strsep(&options, ",")) != NULL) {
1786 if (!*opt)
1787 continue;
1788 if (!strncmp(opt, "noaccel", 7))
1789 noaccel = 1;
1790 else if (!strncmp(opt, "fp", 2))
1791 fp = 1;
1792 else if (!strncmp(opt, "crt", 3))
1793 fp = 0;
1794 else if (!strncmp(opt, "bpp=", 4))
1795 bpp = simple_strtoul(opt + 4, NULL, 0);
1796 else if (!strncmp(opt, "center", 6))
1797 center = 1;
1798 else if (!strncmp(opt, "stretch", 7))
1799 stretch = 1;
1800 else if (!strncmp(opt, "memsize=", 8))
1801 memsize = simple_strtoul(opt + 8, NULL, 0);
1802 else if (!strncmp(opt, "memdiff=", 8))
1803 memdiff = simple_strtoul(opt + 8, NULL, 0);
1804 else if (!strncmp(opt, "nativex=", 8))
1805 nativex = simple_strtoul(opt + 8, NULL, 0);
1806 else
1807 mode_option = opt;
1808 }
1809 return 0;
1810 }
1811 #endif
1812
1813 static int __init tridentfb_init(void)
1814 {
1815 #ifndef MODULE
1816 char *option = NULL;
1817
1818 if (fb_get_options("tridentfb", &option))
1819 return -ENODEV;
1820 tridentfb_setup(option);
1821 #endif
1822 return pci_register_driver(&tridentfb_pci_driver);
1823 }
1824
1825 static void __exit tridentfb_exit(void)
1826 {
1827 pci_unregister_driver(&tridentfb_pci_driver);
1828 }
1829
1830 module_init(tridentfb_init);
1831 module_exit(tridentfb_exit);
1832
1833 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1834 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1835 MODULE_LICENSE("GPL");
1836 MODULE_ALIAS("cyblafb");
1837
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