drivers/video/ipu.h

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2010
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   6  *
   7  * Linux IPU driver for MX51:
   8  *
   9  * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #ifndef __ASM_ARCH_IPU_H__
  31 #define __ASM_ARCH_IPU_H__
  32
  33 #include <linux/types.h>
  34
  35 #define IDMA_CHAN_INVALID       0xFF
  36 #define HIGH_RESOLUTION_WIDTH   1024
  37
  38 struct clk {
  39         const char *name;
  40         int id;
  41         /* Source clock this clk depends on */
  42         struct clk *parent;
  43         /* Secondary clock to enable/disable with this clock */
  44         struct clk *secondary;
  45         /* Current clock rate */
  46         unsigned long rate;
  47         /* Reference count of clock enable/disable */
  48         __s8 usecount;
  49         /* Register bit position for clock's enable/disable control. */
  50         u8 enable_shift;
  51         /* Register address for clock's enable/disable control. */
  52         void *enable_reg;
  53         u32 flags;
  54         /*
  55          * Function ptr to recalculate the clock's rate based on parent
  56          * clock's rate
  57          */
  58         void (*recalc) (struct clk *);
  59         /*
  60          * Function ptr to set the clock to a new rate. The rate must match a
  61          * supported rate returned from round_rate. Leave blank if clock is not
  62         * programmable
  63          */
  64         int (*set_rate) (struct clk *, unsigned long);
  65         /*
  66          * Function ptr to round the requested clock rate to the nearest
  67          * supported rate that is less than or equal to the requested rate.
  68          */
  69         unsigned long (*round_rate) (struct clk *, unsigned long);
  70         /*
  71          * Function ptr to enable the clock. Leave blank if clock can not
  72          * be gated.
  73          */
  74         int (*enable) (struct clk *);
  75         /*
  76          * Function ptr to disable the clock. Leave blank if clock can not
  77          * be gated.
  78          */
  79         void (*disable) (struct clk *);
  80         /* Function ptr to set the parent clock of the clock. */
  81         int (*set_parent) (struct clk *, struct clk *);
  82 };
  83
  84 /*
  85  * Enumeration of Synchronous (Memory-less) panel types
  86  */
  87 typedef enum {
  88         IPU_PANEL_SHARP_TFT,
  89         IPU_PANEL_TFT,
  90 } ipu_panel_t;
  91
  92 /*  IPU Pixel format definitions */
  93 #define fourcc(a, b, c, d)\
  94         (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
  95
  96 /*
  97  * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
  98  * the same used by V4L2 API.
  99  */
 100
 101 #define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')
 102 #define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')
 103 #define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')
 104 #define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')
 105
 106 #define IPU_PIX_FMT_RGB332  fourcc('R', 'G', 'B', '1')  /*<  8  RGB-3-3-2    */
 107 #define IPU_PIX_FMT_RGB555  fourcc('R', 'G', 'B', 'O')  /*< 16  RGB-5-5-5    */
 108 #define IPU_PIX_FMT_RGB565  fourcc('R', 'G', 'B', 'P')  /*< 1 6  RGB-5-6-5   */
 109 #define IPU_PIX_FMT_RGB666  fourcc('R', 'G', 'B', '6')  /*< 18  RGB-6-6-6    */
 110 #define IPU_PIX_FMT_BGR666  fourcc('B', 'G', 'R', '6')  /*< 18  BGR-6-6-6    */
 111 #define IPU_PIX_FMT_BGR24   fourcc('B', 'G', 'R', '3')  /*< 24  BGR-8-8-8    */
 112 #define IPU_PIX_FMT_RGB24   fourcc('R', 'G', 'B', '3')  /*< 24  RGB-8-8-8    */
 113 #define IPU_PIX_FMT_BGR32   fourcc('B', 'G', 'R', '4')  /*< 32  BGR-8-8-8-8  */
 114 #define IPU_PIX_FMT_BGRA32  fourcc('B', 'G', 'R', 'A')  /*< 32  BGR-8-8-8-8  */
 115 #define IPU_PIX_FMT_RGB32   fourcc('R', 'G', 'B', '4')  /*< 32  RGB-8-8-8-8  */
 116 #define IPU_PIX_FMT_RGBA32  fourcc('R', 'G', 'B', 'A')  /*< 32  RGB-8-8-8-8  */
 117 #define IPU_PIX_FMT_ABGR32  fourcc('A', 'B', 'G', 'R')  /*< 32  ABGR-8-8-8-8 */
 118
 119 /* YUV Interleaved Formats */
 120 #define IPU_PIX_FMT_YUYV    fourcc('Y', 'U', 'Y', 'V')  /*< 16 YUV 4:2:2 */
 121 #define IPU_PIX_FMT_UYVY    fourcc('U', 'Y', 'V', 'Y')  /*< 16 YUV 4:2:2 */
 122 #define IPU_PIX_FMT_Y41P    fourcc('Y', '4', '1', 'P')  /*< 12 YUV 4:1:1 */
 123 #define IPU_PIX_FMT_YUV444  fourcc('Y', '4', '4', '4')  /*< 24 YUV 4:4:4 */
 124
 125 /* two planes -- one Y, one Cb + Cr interleaved  */
 126 #define IPU_PIX_FMT_NV12    fourcc('N', 'V', '1', '2') /* 12  Y/CbCr 4:2:0  */
 127
 128 #define IPU_PIX_FMT_GREY    fourcc('G', 'R', 'E', 'Y')  /*< 8  Greyscale */
 129 #define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9')  /*< 9  YVU 4:1:0 */
 130 #define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9')  /*< 9  YUV 4:1:0 */
 131 #define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2')  /*< 12 YVU 4:2:0 */
 132 #define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0')  /*< 12 YUV 4:2:0 */
 133 #define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*< 12 YUV 4:2:0 */
 134 #define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6')  /*< 16 YVU 4:2:2 */
 135 #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P')  /*< 16 YUV 4:2:2 */
 136
 137 /*
 138  * IPU Driver channels definitions.
 139  * Note these are different from IDMA channels
 140  */
 141 #define IPU_MAX_CH      32
 142 #define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
 143         ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
 144 #define _MAKE_ALT_CHAN(ch)              (ch | (IPU_MAX_CH << 24))
 145 #define IPU_CHAN_ID(ch)                 (ch >> 24)
 146 #define IPU_CHAN_ALT(ch)                (ch & 0x02000000)
 147 #define IPU_CHAN_ALPHA_IN_DMA(ch)       ((uint32_t) (ch >> 6) & 0x3F)
 148 #define IPU_CHAN_GRAPH_IN_DMA(ch)       ((uint32_t) (ch >> 12) & 0x3F)
 149 #define IPU_CHAN_VIDEO_IN_DMA(ch)       ((uint32_t) (ch >> 18) & 0x3F)
 150 #define IPU_CHAN_OUT_DMA(ch)            ((uint32_t) (ch & 0x3F))
 151 #define NO_DMA 0x3F
 152 #define ALT     1
 153
 154 /*
 155  * Enumeration of IPU logical channels. An IPU logical channel is defined as a
 156  * combination of an input (memory to IPU), output (IPU to memory), and/or
 157  * secondary input IDMA channels and in some cases an Image Converter task.
 158  * Some channels consist of only an input or output.
 159  */
 160 typedef enum {
 161         CHAN_NONE = -1,
 162
 163         MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
 164         MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
 165         MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
 166         MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
 167
 168         MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
 169         MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
 170         MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
 171         MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
 172
 173         DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
 174         DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
 175
 176 } ipu_channel_t;
 177
 178 /*
 179  * Enumeration of types of buffers for a logical channel.
 180  */
 181 typedef enum {
 182         IPU_OUTPUT_BUFFER = 0,  /*< Buffer for output from IPU */
 183         IPU_ALPHA_IN_BUFFER = 1,        /*< Buffer for input to IPU */
 184         IPU_GRAPH_IN_BUFFER = 2,        /*< Buffer for input to IPU */
 185         IPU_VIDEO_IN_BUFFER = 3,        /*< Buffer for input to IPU */
 186         IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
 187         IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
 188 } ipu_buffer_t;
 189
 190 #define IPU_PANEL_SERIAL                1
 191 #define IPU_PANEL_PARALLEL              2
 192
 193 struct ipu_channel {
 194         u8 video_in_dma;
 195         u8 alpha_in_dma;
 196         u8 graph_in_dma;
 197         u8 out_dma;
 198 };
 199
 200 enum ipu_dmfc_type {
 201         DMFC_NORMAL = 0,
 202         DMFC_HIGH_RESOLUTION_DC,
 203         DMFC_HIGH_RESOLUTION_DP,
 204         DMFC_HIGH_RESOLUTION_ONLY_DP,
 205 };
 206
 207
 208 /*
 209  * Union of initialization parameters for a logical channel.
 210  */
 211 typedef union {
 212         struct {
 213                 uint32_t di;
 214                 unsigned char interlaced;
 215         } mem_dc_sync;
 216         struct {
 217                 uint32_t temp;
 218         } mem_sdc_fg;
 219         struct {
 220                 uint32_t di;
 221                 unsigned char interlaced;
 222                 uint32_t in_pixel_fmt;
 223                 uint32_t out_pixel_fmt;
 224                 unsigned char alpha_chan_en;
 225         } mem_dp_bg_sync;
 226         struct {
 227                 uint32_t temp;
 228         } mem_sdc_bg;
 229         struct {
 230                 uint32_t di;
 231                 unsigned char interlaced;
 232                 uint32_t in_pixel_fmt;
 233                 uint32_t out_pixel_fmt;
 234                 unsigned char alpha_chan_en;
 235         } mem_dp_fg_sync;
 236 } ipu_channel_params_t;
 237
 238 /*
 239  * Bitfield of Display Interface signal polarities.
 240  */
 241 typedef struct {
 242         unsigned datamask_en:1;
 243         unsigned ext_clk:1;
 244         unsigned interlaced:1;
 245         unsigned odd_field_first:1;
 246         unsigned clksel_en:1;
 247         unsigned clkidle_en:1;
 248         unsigned data_pol:1;    /* true = inverted */
 249         unsigned clk_pol:1;     /* true = rising edge */
 250         unsigned enable_pol:1;
 251         unsigned Hsync_pol:1;   /* true = active high */
 252         unsigned Vsync_pol:1;
 253 } ipu_di_signal_cfg_t;
 254
 255 typedef enum {
 256         RGB,
 257         YCbCr,
 258         YUV
 259 } ipu_color_space_t;
 260
 261 /* Common IPU API */
 262 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
 263 void ipu_uninit_channel(ipu_channel_t channel);
 264
 265 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
 266                                 uint32_t pixel_fmt,
 267                                 uint16_t width, uint16_t height,
 268                                 uint32_t stride,
 269                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
 270                                 uint32_t u_offset, uint32_t v_offset);
 271
 272 int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
 273                                   uint32_t bufNum, dma_addr_t phyaddr);
 274
 275 int32_t ipu_is_channel_busy(ipu_channel_t channel);
 276 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
 277                 uint32_t bufNum);
 278 int32_t ipu_enable_channel(ipu_channel_t channel);
 279 int32_t ipu_disable_channel(ipu_channel_t channel);
 280
 281 int32_t ipu_init_sync_panel(int disp,
 282                             uint32_t pixel_clk,
 283                             uint16_t width, uint16_t height,
 284                             uint32_t pixel_fmt,
 285                             uint16_t h_start_width, uint16_t h_sync_width,
 286                             uint16_t h_end_width, uint16_t v_start_width,
 287                             uint16_t v_sync_width, uint16_t v_end_width,
 288                             uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
 289
 290 int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
 291                                   uint8_t alpha);
 292 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
 293                                uint32_t colorKey);
 294
 295 uint32_t bytes_per_pixel(uint32_t fmt);
 296
 297 void clk_enable(struct clk *clk);
 298 void clk_disable(struct clk *clk);
 299 u32 clk_get_rate(struct clk *clk);
 300 int clk_set_rate(struct clk *clk, unsigned long rate);
 301 long clk_round_rate(struct clk *clk, unsigned long rate);
 302 int clk_set_parent(struct clk *clk, struct clk *parent);
 303 int clk_get_usecount(struct clk *clk);
 304 struct clk *clk_get_parent(struct clk *clk);
 305
 306 void ipu_dump_registers(void);
 307 int ipu_probe(void);
 308
 309 void ipu_dmfc_init(int dmfc_type, int first);
 310 void ipu_init_dc_mappings(void);
 311 void ipu_dmfc_set_wait4eot(int dma_chan, int width);
 312 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
 313 void ipu_dc_uninit(int dc_chan);
 314 void ipu_dp_dc_enable(ipu_channel_t channel);
 315 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
 316                  uint32_t out_pixel_fmt);
 317 void ipu_dp_uninit(ipu_channel_t channel);
 318 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
 319 ipu_color_space_t format_to_colorspace(uint32_t fmt);
 320
 321 #endif