5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
7 * Linux IPU driver for MX51:
9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/types.h>
17 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/crm_regs.h>
26 extern struct mxc_ccm_reg
*mxc_ccm
;
27 extern u32
*ipu_cpmem_base
;
29 struct ipu_ch_param_word
{
35 struct ipu_ch_param_word word
[2];
38 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
40 #define _param_word(base, w) \
41 (((struct ipu_ch_param *)(base))->word[(w)].data)
43 #define ipu_ch_param_set_field(base, w, bit, size, v) { \
45 int off = (bit) % 32; \
46 _param_word(base, w)[i] |= (v) << off; \
47 if (((bit) + (size) - 1) / 32 > i) { \
48 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
52 #define ipu_ch_param_mod_field(base, w, bit, size, v) { \
54 int off = (bit) % 32; \
55 u32 mask = (1UL << size) - 1; \
56 u32 temp = _param_word(base, w)[i]; \
57 temp &= ~(mask << off); \
58 _param_word(base, w)[i] = temp | (v) << off; \
59 if (((bit) + (size) - 1) / 32 > i) { \
60 temp = _param_word(base, w)[i + 1]; \
61 temp &= ~(mask >> (32 - off)); \
62 _param_word(base, w)[i + 1] = \
63 temp | ((v) >> (off ? (32 - off) : 0)); \
67 #define ipu_ch_param_read_field(base, w, bit, size) ({ \
70 int off = (bit) % 32; \
71 u32 mask = (1UL << size) - 1; \
72 u32 temp1 = _param_word(base, w)[i]; \
73 temp1 = mask & (temp1 >> off); \
74 if (((bit)+(size) - 1) / 32 > i) { \
75 temp2 = _param_word(base, w)[i + 1]; \
76 temp2 &= mask >> (off ? (32 - off) : 0); \
77 temp1 |= temp2 << (off ? (32 - off) : 0); \
82 #define IPU_SW_RST_TOUT_USEC (10000)
84 void clk_enable(struct clk
*clk
)
87 if (clk
->usecount
++ == 0) {
93 void clk_disable(struct clk
*clk
)
96 if (!(--clk
->usecount
)) {
103 int clk_get_usecount(struct clk
*clk
)
108 return clk
->usecount
;
111 u32
clk_get_rate(struct clk
*clk
)
119 struct clk
*clk_get_parent(struct clk
*clk
)
127 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
129 if (clk
&& clk
->set_rate
)
130 clk
->set_rate(clk
, rate
);
134 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
136 if (clk
== NULL
|| !clk
->round_rate
)
139 return clk
->round_rate(clk
, rate
);
142 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
144 clk
->parent
= parent
;
146 return clk
->set_parent(clk
, parent
);
150 static int clk_ipu_enable(struct clk
*clk
)
154 reg
= __raw_readl(clk
->enable_reg
);
155 reg
|= MXC_CCM_CCGR_CG_MASK
<< clk
->enable_shift
;
156 __raw_writel(reg
, clk
->enable_reg
);
158 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
159 /* Handshake with IPU when certain clock rates are changed. */
160 reg
= __raw_readl(&mxc_ccm
->ccdr
);
161 reg
&= ~MXC_CCM_CCDR_IPU_HS_MASK
;
162 __raw_writel(reg
, &mxc_ccm
->ccdr
);
164 /* Handshake with IPU when LPM is entered as its enabled. */
165 reg
= __raw_readl(&mxc_ccm
->clpcr
);
166 reg
&= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS
;
167 __raw_writel(reg
, &mxc_ccm
->clpcr
);
172 static void clk_ipu_disable(struct clk
*clk
)
176 reg
= __raw_readl(clk
->enable_reg
);
177 reg
&= ~(MXC_CCM_CCGR_CG_MASK
<< clk
->enable_shift
);
178 __raw_writel(reg
, clk
->enable_reg
);
180 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
182 * No handshake with IPU whe dividers are changed
183 * as its not enabled.
185 reg
= __raw_readl(&mxc_ccm
->ccdr
);
186 reg
|= MXC_CCM_CCDR_IPU_HS_MASK
;
187 __raw_writel(reg
, &mxc_ccm
->ccdr
);
189 /* No handshake with IPU when LPM is entered as its not enabled. */
190 reg
= __raw_readl(&mxc_ccm
->clpcr
);
191 reg
|= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS
;
192 __raw_writel(reg
, &mxc_ccm
->clpcr
);
197 static struct clk ipu_clk
= {
199 .rate
= CONFIG_IPUV3_CLK
,
200 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
201 .enable_reg
= (u32
*)(CCM_BASE_ADDR
+
202 offsetof(struct mxc_ccm_reg
, CCGR5
)),
203 .enable_shift
= MXC_CCM_CCGR5_IPU_OFFSET
,
205 .enable_reg
= (u32
*)(CCM_BASE_ADDR
+
206 offsetof(struct mxc_ccm_reg
, CCGR3
)),
207 .enable_shift
= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
,
209 .enable
= clk_ipu_enable
,
210 .disable
= clk_ipu_disable
,
214 #if !defined CONFIG_SYS_LDB_CLOCK
215 #define CONFIG_SYS_LDB_CLOCK 65000000
218 static struct clk ldb_clk
= {
220 .rate
= CONFIG_SYS_LDB_CLOCK
,
225 struct clk
*g_ipu_clk
;
226 struct clk
*g_ldb_clk
;
227 unsigned char g_ipu_clk_enabled
;
228 struct clk
*g_di_clk
[2];
229 struct clk
*g_pixel_clk
[2];
230 unsigned char g_dc_di_assignment
[10];
231 uint32_t g_channel_init_mask
;
232 uint32_t g_channel_enable_mask
;
234 static int ipu_dc_use_count
;
235 static int ipu_dp_use_count
;
236 static int ipu_dmfc_use_count
;
237 static int ipu_di_use_count
[2];
240 u32
*ipu_dc_tmpl_reg
;
242 /* Static functions */
244 static inline void ipu_ch_param_set_high_priority(uint32_t ch
)
246 ipu_ch_param_mod_field(ipu_ch_param_addr(ch
), 1, 93, 2, 1);
249 static inline uint32_t channel_2_dma(ipu_channel_t ch
, ipu_buffer_t type
)
251 return ((uint32_t) ch
>> (6 * type
)) & 0x3F;
254 /* Either DP BG or DP FG can be graphic window */
255 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan
)
257 return (dma_chan
== 23 || dma_chan
== 27);
260 static inline int ipu_is_dmfc_chan(uint32_t dma_chan
)
262 return ((dma_chan
>= 23) && (dma_chan
<= 29));
266 static inline void ipu_ch_param_set_buffer(uint32_t ch
, int bufNum
,
269 ipu_ch_param_mod_field(ipu_ch_param_addr(ch
), 1, 29 * bufNum
, 29,
273 #define idma_is_valid(ch) (ch != NO_DMA)
274 #define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
275 #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
277 static void ipu_pixel_clk_recalc(struct clk
*clk
)
280 u64 final_rate
= (unsigned long long)clk
->parent
->rate
* 16;
282 div
= __raw_readl(DI_BS_CLKGEN0(clk
->id
));
283 debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
284 div
, final_rate
, clk
->parent
->rate
);
288 do_div(final_rate
, div
);
289 clk
->rate
= final_rate
;
293 static unsigned long ipu_pixel_clk_round_rate(struct clk
*clk
,
298 u64 parent_rate
= (unsigned long long)clk
->parent
->rate
* 16;
302 * Fractional part is 4 bits,
303 * so simply multiply by 2^4 to get fractional part.
306 remainder
= do_div(div
, rate
);
307 /* Round the divider value */
308 if (remainder
> (rate
/ 2))
310 if (div
< 0x10) /* Min DI disp clock divider is 1 */
315 /* Round up divider if it gets us closer to desired pix clk */
316 if ((div
& 0xC) == 0xC) {
321 final_rate
= parent_rate
;
322 do_div(final_rate
, div
);
327 static int ipu_pixel_clk_set_rate(struct clk
*clk
, unsigned long rate
)
329 u64 div
, parent_rate
;
332 parent_rate
= (unsigned long long)clk
->parent
->rate
* 16;
334 remainder
= do_div(div
, rate
);
335 /* Round the divider value */
336 if (remainder
> (rate
/ 2))
339 /* Round up divider if it gets us closer to desired pix clk */
340 if ((div
& 0xC) == 0xC) {
345 debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32
)div
);
347 __raw_writel(div
, DI_BS_CLKGEN0(clk
->id
));
350 * Setup pixel clock timing
351 * Down time is half of period
353 __raw_writel((div
/ 16) << 16, DI_BS_CLKGEN1(clk
->id
));
355 do_div(parent_rate
, div
);
357 clk
->rate
= parent_rate
;
362 static int ipu_pixel_clk_enable(struct clk
*clk
)
364 u32 disp_gen
= __raw_readl(IPU_DISP_GEN
);
365 disp_gen
|= clk
->id
? DI1_COUNTER_RELEASE
: DI0_COUNTER_RELEASE
;
366 __raw_writel(disp_gen
, IPU_DISP_GEN
);
371 static void ipu_pixel_clk_disable(struct clk
*clk
)
373 u32 disp_gen
= __raw_readl(IPU_DISP_GEN
);
374 disp_gen
&= clk
->id
? ~DI1_COUNTER_RELEASE
: ~DI0_COUNTER_RELEASE
;
375 __raw_writel(disp_gen
, IPU_DISP_GEN
);
379 static int ipu_pixel_clk_set_parent(struct clk
*clk
, struct clk
*parent
)
381 u32 di_gen
= __raw_readl(DI_GENERAL(clk
->id
));
383 if (parent
== g_ipu_clk
)
384 di_gen
&= ~DI_GEN_DI_CLK_EXT
;
385 else if (!IS_ERR(g_di_clk
[clk
->id
]) && parent
== g_ldb_clk
)
386 di_gen
|= DI_GEN_DI_CLK_EXT
;
390 __raw_writel(di_gen
, DI_GENERAL(clk
->id
));
391 ipu_pixel_clk_recalc(clk
);
395 static struct clk pixel_clk
[] = {
399 .recalc
= ipu_pixel_clk_recalc
,
400 .set_rate
= ipu_pixel_clk_set_rate
,
401 .round_rate
= ipu_pixel_clk_round_rate
,
402 .set_parent
= ipu_pixel_clk_set_parent
,
403 .enable
= ipu_pixel_clk_enable
,
404 .disable
= ipu_pixel_clk_disable
,
410 .recalc
= ipu_pixel_clk_recalc
,
411 .set_rate
= ipu_pixel_clk_set_rate
,
412 .round_rate
= ipu_pixel_clk_round_rate
,
413 .set_parent
= ipu_pixel_clk_set_parent
,
414 .enable
= ipu_pixel_clk_enable
,
415 .disable
= ipu_pixel_clk_disable
,
421 * This function resets IPU
423 static void ipu_reset(void)
427 int timeout
= IPU_SW_RST_TOUT_USEC
;
429 reg
= (u32
*)SRC_BASE_ADDR
;
430 value
= __raw_readl(reg
);
431 value
= value
| SW_IPU_RST
;
432 __raw_writel(value
, reg
);
434 while (__raw_readl(reg
) & SW_IPU_RST
) {
437 printf("ipu software reset timeout\n");
444 * This function is called by the driver framework to initialize the IPU
447 * @param dev The device structure for the IPU passed in by the
450 * @return Returns 0 on success or negative error code on error
454 unsigned long ipu_base
;
455 #if defined CONFIG_MX51
458 u32
*reg_hsc_mcd
= (u32
*)MIPI_HSC_BASE_ADDR
;
459 u32
*reg_hsc_mxt_conf
= (u32
*)(MIPI_HSC_BASE_ADDR
+ 0x800);
461 __raw_writel(0xF00, reg_hsc_mcd
);
463 /* CSI mode reserved*/
464 temp
= __raw_readl(reg_hsc_mxt_conf
);
465 __raw_writel(temp
| 0x0FF, reg_hsc_mxt_conf
);
467 temp
= __raw_readl(reg_hsc_mxt_conf
);
468 __raw_writel(temp
| 0x10000, reg_hsc_mxt_conf
);
471 ipu_base
= IPU_CTRL_BASE_ADDR
;
472 ipu_cpmem_base
= (u32
*)(ipu_base
+ IPU_CPMEM_REG_BASE
);
473 ipu_dc_tmpl_reg
= (u32
*)(ipu_base
+ IPU_DC_TMPL_REG_BASE
);
475 g_pixel_clk
[0] = &pixel_clk
[0];
476 g_pixel_clk
[1] = &pixel_clk
[1];
478 g_ipu_clk
= &ipu_clk
;
479 debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk
));
480 g_ldb_clk
= &ldb_clk
;
481 debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk
));
484 clk_set_parent(g_pixel_clk
[0], g_ipu_clk
);
485 clk_set_parent(g_pixel_clk
[1], g_ipu_clk
);
486 clk_enable(g_ipu_clk
);
491 __raw_writel(0x807FFFFF, IPU_MEM_RST
);
492 while (__raw_readl(IPU_MEM_RST
) & 0x80000000)
495 ipu_init_dc_mappings();
497 __raw_writel(0, IPU_INT_CTRL(5));
498 __raw_writel(0, IPU_INT_CTRL(6));
499 __raw_writel(0, IPU_INT_CTRL(9));
500 __raw_writel(0, IPU_INT_CTRL(10));
503 ipu_dmfc_init(DMFC_NORMAL
, 1);
505 /* Set sync refresh channels as high priority */
506 __raw_writel(0x18800000L
, IDMAC_CHA_PRI(0));
508 /* Set MCU_T to divide MCU access window into 2 */
509 __raw_writel(0x00400000L
| (IPU_MCU_T_DEFAULT
<< 18), IPU_DISP_GEN
);
511 clk_disable(g_ipu_clk
);
516 void ipu_dump_registers(void)
518 debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF
));
519 debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF
));
520 debug("IDMAC_CHA_EN1 = \t0x%08X\n",
521 __raw_readl(IDMAC_CHA_EN(0)));
522 debug("IDMAC_CHA_EN2 = \t0x%08X\n",
523 __raw_readl(IDMAC_CHA_EN(32)));
524 debug("IDMAC_CHA_PRI1 = \t0x%08X\n",
525 __raw_readl(IDMAC_CHA_PRI(0)));
526 debug("IDMAC_CHA_PRI2 = \t0x%08X\n",
527 __raw_readl(IDMAC_CHA_PRI(32)));
528 debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
529 __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
530 debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
531 __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
532 debug("DMFC_WR_CHAN = \t0x%08X\n",
533 __raw_readl(DMFC_WR_CHAN
));
534 debug("DMFC_WR_CHAN_DEF = \t0x%08X\n",
535 __raw_readl(DMFC_WR_CHAN_DEF
));
536 debug("DMFC_DP_CHAN = \t0x%08X\n",
537 __raw_readl(DMFC_DP_CHAN
));
538 debug("DMFC_DP_CHAN_DEF = \t0x%08X\n",
539 __raw_readl(DMFC_DP_CHAN_DEF
));
540 debug("DMFC_IC_CTRL = \t0x%08X\n",
541 __raw_readl(DMFC_IC_CTRL
));
542 debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n",
543 __raw_readl(IPU_FS_PROC_FLOW1
));
544 debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n",
545 __raw_readl(IPU_FS_PROC_FLOW2
));
546 debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n",
547 __raw_readl(IPU_FS_PROC_FLOW3
));
548 debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n",
549 __raw_readl(IPU_FS_DISP_FLOW1
));
553 * This function is called to initialize a logical IPU channel.
555 * @param channel Input parameter for the logical channel ID to init.
557 * @param params Input parameter containing union of channel
558 * initialization parameters.
560 * @return Returns 0 on success or negative error code on fail
562 int32_t ipu_init_channel(ipu_channel_t channel
, ipu_channel_params_t
*params
)
567 debug("init channel = %d\n", IPU_CHAN_ID(channel
));
569 if (g_ipu_clk_enabled
== 0) {
570 g_ipu_clk_enabled
= 1;
571 clk_enable(g_ipu_clk
);
575 if (g_channel_init_mask
& (1L << IPU_CHAN_ID(channel
))) {
576 printf("Warning: channel already initialized %d\n",
577 IPU_CHAN_ID(channel
));
580 ipu_conf
= __raw_readl(IPU_CONF
);
584 if (params
->mem_dc_sync
.di
> 1) {
589 g_dc_di_assignment
[1] = params
->mem_dc_sync
.di
;
590 ipu_dc_init(1, params
->mem_dc_sync
.di
,
591 params
->mem_dc_sync
.interlaced
);
592 ipu_di_use_count
[params
->mem_dc_sync
.di
]++;
594 ipu_dmfc_use_count
++;
597 if (params
->mem_dp_bg_sync
.di
> 1) {
602 g_dc_di_assignment
[5] = params
->mem_dp_bg_sync
.di
;
603 ipu_dp_init(channel
, params
->mem_dp_bg_sync
.in_pixel_fmt
,
604 params
->mem_dp_bg_sync
.out_pixel_fmt
);
605 ipu_dc_init(5, params
->mem_dp_bg_sync
.di
,
606 params
->mem_dp_bg_sync
.interlaced
);
607 ipu_di_use_count
[params
->mem_dp_bg_sync
.di
]++;
610 ipu_dmfc_use_count
++;
613 ipu_dp_init(channel
, params
->mem_dp_fg_sync
.in_pixel_fmt
,
614 params
->mem_dp_fg_sync
.out_pixel_fmt
);
618 ipu_dmfc_use_count
++;
621 printf("Missing channel initialization\n");
625 /* Enable IPU sub module */
626 g_channel_init_mask
|= 1L << IPU_CHAN_ID(channel
);
627 if (ipu_dc_use_count
== 1)
628 ipu_conf
|= IPU_CONF_DC_EN
;
629 if (ipu_dp_use_count
== 1)
630 ipu_conf
|= IPU_CONF_DP_EN
;
631 if (ipu_dmfc_use_count
== 1)
632 ipu_conf
|= IPU_CONF_DMFC_EN
;
633 if (ipu_di_use_count
[0] == 1) {
634 ipu_conf
|= IPU_CONF_DI0_EN
;
636 if (ipu_di_use_count
[1] == 1) {
637 ipu_conf
|= IPU_CONF_DI1_EN
;
640 __raw_writel(ipu_conf
, IPU_CONF
);
647 * This function is called to uninitialize a logical IPU channel.
649 * @param channel Input parameter for the logical channel ID to uninit.
651 void ipu_uninit_channel(ipu_channel_t channel
)
654 uint32_t in_dma
, out_dma
= 0;
657 if ((g_channel_init_mask
& (1L << IPU_CHAN_ID(channel
))) == 0) {
658 debug("Channel already uninitialized %d\n",
659 IPU_CHAN_ID(channel
));
664 * Make sure channel is disabled
665 * Get input and output dma channels
667 in_dma
= channel_2_dma(channel
, IPU_OUTPUT_BUFFER
);
668 out_dma
= channel_2_dma(channel
, IPU_VIDEO_IN_BUFFER
);
670 if (idma_is_set(IDMAC_CHA_EN
, in_dma
) ||
671 idma_is_set(IDMAC_CHA_EN
, out_dma
)) {
673 "Channel %d is not disabled, disable first\n",
674 IPU_CHAN_ID(channel
));
678 ipu_conf
= __raw_readl(IPU_CONF
);
680 /* Reset the double buffer */
681 reg
= __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma
));
682 __raw_writel(reg
& ~idma_mask(in_dma
), IPU_CHA_DB_MODE_SEL(in_dma
));
683 reg
= __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma
));
684 __raw_writel(reg
& ~idma_mask(out_dma
), IPU_CHA_DB_MODE_SEL(out_dma
));
689 ipu_di_use_count
[g_dc_di_assignment
[1]]--;
691 ipu_dmfc_use_count
--;
694 ipu_dp_uninit(channel
);
696 ipu_di_use_count
[g_dc_di_assignment
[5]]--;
699 ipu_dmfc_use_count
--;
702 ipu_dp_uninit(channel
);
705 ipu_dmfc_use_count
--;
711 g_channel_init_mask
&= ~(1L << IPU_CHAN_ID(channel
));
713 if (ipu_dc_use_count
== 0)
714 ipu_conf
&= ~IPU_CONF_DC_EN
;
715 if (ipu_dp_use_count
== 0)
716 ipu_conf
&= ~IPU_CONF_DP_EN
;
717 if (ipu_dmfc_use_count
== 0)
718 ipu_conf
&= ~IPU_CONF_DMFC_EN
;
719 if (ipu_di_use_count
[0] == 0) {
720 ipu_conf
&= ~IPU_CONF_DI0_EN
;
722 if (ipu_di_use_count
[1] == 0) {
723 ipu_conf
&= ~IPU_CONF_DI1_EN
;
726 __raw_writel(ipu_conf
, IPU_CONF
);
729 clk_disable(g_ipu_clk
);
730 g_ipu_clk_enabled
= 0;
735 static inline void ipu_ch_param_dump(int ch
)
738 struct ipu_ch_param
*p
= ipu_ch_param_addr(ch
);
739 debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch
,
740 p
->word
[0].data
[0], p
->word
[0].data
[1], p
->word
[0].data
[2],
741 p
->word
[0].data
[3], p
->word
[0].data
[4]);
742 debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch
,
743 p
->word
[1].data
[0], p
->word
[1].data
[1], p
->word
[1].data
[2],
744 p
->word
[1].data
[3], p
->word
[1].data
[4]);
746 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 85, 4));
748 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 0, 107, 3));
750 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 78, 7));
753 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 0, 125, 13));
755 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 0, 138, 12));
757 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 102, 14));
759 debug("Width0 %d+1, ",
760 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 116, 3));
761 debug("Width1 %d+1, ",
762 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 119, 3));
763 debug("Width2 %d+1, ",
764 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 122, 3));
765 debug("Width3 %d+1, ",
766 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 125, 3));
767 debug("Offset0 %d, ",
768 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 128, 5));
769 debug("Offset1 %d, ",
770 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 133, 5));
771 debug("Offset2 %d, ",
772 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 138, 5));
773 debug("Offset3 %d\n",
774 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 143, 5));
778 static inline void ipu_ch_params_set_packing(struct ipu_ch_param
*p
,
779 int red_width
, int red_offset
,
780 int green_width
, int green_offset
,
781 int blue_width
, int blue_offset
,
782 int alpha_width
, int alpha_offset
)
784 /* Setup red width and offset */
785 ipu_ch_param_set_field(p
, 1, 116, 3, red_width
- 1);
786 ipu_ch_param_set_field(p
, 1, 128, 5, red_offset
);
787 /* Setup green width and offset */
788 ipu_ch_param_set_field(p
, 1, 119, 3, green_width
- 1);
789 ipu_ch_param_set_field(p
, 1, 133, 5, green_offset
);
790 /* Setup blue width and offset */
791 ipu_ch_param_set_field(p
, 1, 122, 3, blue_width
- 1);
792 ipu_ch_param_set_field(p
, 1, 138, 5, blue_offset
);
793 /* Setup alpha width and offset */
794 ipu_ch_param_set_field(p
, 1, 125, 3, alpha_width
- 1);
795 ipu_ch_param_set_field(p
, 1, 143, 5, alpha_offset
);
798 static void ipu_ch_param_init(int ch
,
799 uint32_t pixel_fmt
, uint32_t width
,
800 uint32_t height
, uint32_t stride
,
801 uint32_t u
, uint32_t v
,
802 uint32_t uv_stride
, dma_addr_t addr0
,
805 uint32_t u_offset
= 0;
806 uint32_t v_offset
= 0;
807 struct ipu_ch_param params
;
809 memset(¶ms
, 0, sizeof(params
));
811 ipu_ch_param_set_field(¶ms
, 0, 125, 13, width
- 1);
813 if ((ch
== 8) || (ch
== 9) || (ch
== 10)) {
814 ipu_ch_param_set_field(¶ms
, 0, 138, 12, (height
/ 2) - 1);
815 ipu_ch_param_set_field(¶ms
, 1, 102, 14, (stride
* 2) - 1);
817 ipu_ch_param_set_field(¶ms
, 0, 138, 12, height
- 1);
818 ipu_ch_param_set_field(¶ms
, 1, 102, 14, stride
- 1);
821 ipu_ch_param_set_field(¶ms
, 1, 0, 29, addr0
>> 3);
822 ipu_ch_param_set_field(¶ms
, 1, 29, 29, addr1
>> 3);
825 case IPU_PIX_FMT_GENERIC
:
826 /*Represents 8-bit Generic data */
827 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 5); /* bits/pixel */
828 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 6); /* pix format */
829 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 63); /* burst size */
832 case IPU_PIX_FMT_GENERIC_32
:
833 /*Represents 32-bit Generic data */
835 case IPU_PIX_FMT_RGB565
:
836 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 3); /* bits/pixel */
837 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
838 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 15); /* burst size */
840 ipu_ch_params_set_packing(¶ms
, 5, 0, 6, 5, 5, 11, 8, 16);
842 case IPU_PIX_FMT_BGR24
:
843 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 1); /* bits/pixel */
844 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
845 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 19); /* burst size */
847 ipu_ch_params_set_packing(¶ms
, 8, 0, 8, 8, 8, 16, 8, 24);
849 case IPU_PIX_FMT_RGB24
:
850 case IPU_PIX_FMT_YUV444
:
851 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 1); /* bits/pixel */
852 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
853 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 19); /* burst size */
855 ipu_ch_params_set_packing(¶ms
, 8, 16, 8, 8, 8, 0, 8, 24);
857 case IPU_PIX_FMT_BGRA32
:
858 case IPU_PIX_FMT_BGR32
:
859 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 0); /* bits/pixel */
860 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
861 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 15); /* burst size */
863 ipu_ch_params_set_packing(¶ms
, 8, 8, 8, 16, 8, 24, 8, 0);
865 case IPU_PIX_FMT_RGBA32
:
866 case IPU_PIX_FMT_RGB32
:
867 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 0); /* bits/pixel */
868 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
869 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 15); /* burst size */
871 ipu_ch_params_set_packing(¶ms
, 8, 24, 8, 16, 8, 8, 8, 0);
873 case IPU_PIX_FMT_ABGR32
:
874 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 0); /* bits/pixel */
875 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
877 ipu_ch_params_set_packing(¶ms
, 8, 0, 8, 8, 8, 16, 8, 24);
879 case IPU_PIX_FMT_UYVY
:
880 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 3); /* bits/pixel */
881 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 0xA); /* pix format */
882 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 15); /* burst size */
884 case IPU_PIX_FMT_YUYV
:
885 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 3); /* bits/pixel */
886 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 0x8); /* pix format */
887 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 31); /* burst size */
889 case IPU_PIX_FMT_YUV420P2
:
890 case IPU_PIX_FMT_YUV420P
:
891 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 2); /* pix format */
893 if (uv_stride
< stride
/ 2)
894 uv_stride
= stride
/ 2;
896 u_offset
= stride
* height
;
897 v_offset
= u_offset
+ (uv_stride
* height
/ 2);
899 if ((ch
== 8) || (ch
== 9) || (ch
== 10)) {
900 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 15);
901 uv_stride
= uv_stride
*2;
903 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 31);
906 case IPU_PIX_FMT_YVU422P
:
907 /* BPP & pixel format */
908 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 1); /* pix format */
909 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 31); /* burst size */
911 if (uv_stride
< stride
/ 2)
912 uv_stride
= stride
/ 2;
914 v_offset
= (v
== 0) ? stride
* height
: v
;
915 u_offset
= (u
== 0) ? v_offset
+ v_offset
/ 2 : u
;
917 case IPU_PIX_FMT_YUV422P
:
918 /* BPP & pixel format */
919 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 1); /* pix format */
920 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 31); /* burst size */
922 if (uv_stride
< stride
/ 2)
923 uv_stride
= stride
/ 2;
925 u_offset
= (u
== 0) ? stride
* height
: u
;
926 v_offset
= (v
== 0) ? u_offset
+ u_offset
/ 2 : v
;
928 case IPU_PIX_FMT_NV12
:
929 /* BPP & pixel format */
930 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 4); /* pix format */
931 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 31); /* burst size */
933 u_offset
= (u
== 0) ? stride
* height
: u
;
936 puts("mxc ipu: unimplemented pixel format\n");
942 ipu_ch_param_set_field(¶ms
, 1, 128, 14, uv_stride
- 1);
944 /* Get the uv offset from user when need cropping */
950 /* UBO and VBO are 22-bit */
951 if (u_offset
/8 > 0x3fffff)
952 puts("The value of U offset exceeds IPU limitation\n");
953 if (v_offset
/8 > 0x3fffff)
954 puts("The value of V offset exceeds IPU limitation\n");
956 ipu_ch_param_set_field(¶ms
, 0, 46, 22, u_offset
/ 8);
957 ipu_ch_param_set_field(¶ms
, 0, 68, 22, v_offset
/ 8);
959 debug("initializing idma ch %d @ %p\n", ch
, ipu_ch_param_addr(ch
));
960 memcpy(ipu_ch_param_addr(ch
), ¶ms
, sizeof(params
));
964 * This function is called to initialize a buffer for logical IPU channel.
966 * @param channel Input parameter for the logical channel ID.
968 * @param type Input parameter which buffer to initialize.
970 * @param pixel_fmt Input parameter for pixel format of buffer.
971 * Pixel format is a FOURCC ASCII code.
973 * @param width Input parameter for width of buffer in pixels.
975 * @param height Input parameter for height of buffer in pixels.
977 * @param stride Input parameter for stride length of buffer
980 * @param phyaddr_0 Input parameter buffer 0 physical address.
982 * @param phyaddr_1 Input parameter buffer 1 physical address.
983 * Setting this to a value other than NULL enables
984 * double buffering mode.
986 * @param u private u offset for additional cropping,
989 * @param v private v offset for additional cropping,
992 * @return Returns 0 on success or negative error code on fail
994 int32_t ipu_init_channel_buffer(ipu_channel_t channel
, ipu_buffer_t type
,
996 uint16_t width
, uint16_t height
,
998 dma_addr_t phyaddr_0
, dma_addr_t phyaddr_1
,
999 uint32_t u
, uint32_t v
)
1004 dma_chan
= channel_2_dma(channel
, type
);
1005 if (!idma_is_valid(dma_chan
))
1008 if (stride
< width
* bytes_per_pixel(pixel_fmt
))
1009 stride
= width
* bytes_per_pixel(pixel_fmt
);
1013 "Stride not 32-bit aligned, stride = %d\n", stride
);
1016 /* Build parameter memory data for DMA channel */
1017 ipu_ch_param_init(dma_chan
, pixel_fmt
, width
, height
, stride
, u
, v
, 0,
1018 phyaddr_0
, phyaddr_1
);
1020 if (ipu_is_dmfc_chan(dma_chan
)) {
1021 ipu_dmfc_set_wait4eot(dma_chan
, width
);
1024 if (idma_is_set(IDMAC_CHA_PRI
, dma_chan
))
1025 ipu_ch_param_set_high_priority(dma_chan
);
1027 ipu_ch_param_dump(dma_chan
);
1029 reg
= __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan
));
1031 reg
|= idma_mask(dma_chan
);
1033 reg
&= ~idma_mask(dma_chan
);
1034 __raw_writel(reg
, IPU_CHA_DB_MODE_SEL(dma_chan
));
1036 /* Reset to buffer 0 */
1037 __raw_writel(idma_mask(dma_chan
), IPU_CHA_CUR_BUF(dma_chan
));
1043 * This function enables a logical channel.
1045 * @param channel Input parameter for the logical channel ID.
1047 * @return This function returns 0 on success or negative error code on
1050 int32_t ipu_enable_channel(ipu_channel_t channel
)
1056 if (g_channel_enable_mask
& (1L << IPU_CHAN_ID(channel
))) {
1057 printf("Warning: channel already enabled %d\n",
1058 IPU_CHAN_ID(channel
));
1061 /* Get input and output dma channels */
1062 out_dma
= channel_2_dma(channel
, IPU_OUTPUT_BUFFER
);
1063 in_dma
= channel_2_dma(channel
, IPU_VIDEO_IN_BUFFER
);
1065 if (idma_is_valid(in_dma
)) {
1066 reg
= __raw_readl(IDMAC_CHA_EN(in_dma
));
1067 __raw_writel(reg
| idma_mask(in_dma
), IDMAC_CHA_EN(in_dma
));
1069 if (idma_is_valid(out_dma
)) {
1070 reg
= __raw_readl(IDMAC_CHA_EN(out_dma
));
1071 __raw_writel(reg
| idma_mask(out_dma
), IDMAC_CHA_EN(out_dma
));
1074 if ((channel
== MEM_DC_SYNC
) || (channel
== MEM_BG_SYNC
) ||
1075 (channel
== MEM_FG_SYNC
))
1076 ipu_dp_dc_enable(channel
);
1078 g_channel_enable_mask
|= 1L << IPU_CHAN_ID(channel
);
1084 * This function clear buffer ready for a logical channel.
1086 * @param channel Input parameter for the logical channel ID.
1088 * @param type Input parameter which buffer to clear.
1090 * @param bufNum Input parameter for which buffer number clear
1094 void ipu_clear_buffer_ready(ipu_channel_t channel
, ipu_buffer_t type
,
1097 uint32_t dma_ch
= channel_2_dma(channel
, type
);
1099 if (!idma_is_valid(dma_ch
))
1102 __raw_writel(0xF0000000, IPU_GPR
); /* write one to clear */
1104 if (idma_is_set(IPU_CHA_BUF0_RDY
, dma_ch
)) {
1105 __raw_writel(idma_mask(dma_ch
),
1106 IPU_CHA_BUF0_RDY(dma_ch
));
1109 if (idma_is_set(IPU_CHA_BUF1_RDY
, dma_ch
)) {
1110 __raw_writel(idma_mask(dma_ch
),
1111 IPU_CHA_BUF1_RDY(dma_ch
));
1114 __raw_writel(0x0, IPU_GPR
); /* write one to set */
1118 * This function disables a logical channel.
1120 * @param channel Input parameter for the logical channel ID.
1122 * @param wait_for_stop Flag to set whether to wait for channel end
1123 * of frame or return immediately.
1125 * @return This function returns 0 on success or negative error code on
1128 int32_t ipu_disable_channel(ipu_channel_t channel
)
1134 if ((g_channel_enable_mask
& (1L << IPU_CHAN_ID(channel
))) == 0) {
1135 debug("Channel already disabled %d\n",
1136 IPU_CHAN_ID(channel
));
1140 /* Get input and output dma channels */
1141 out_dma
= channel_2_dma(channel
, IPU_OUTPUT_BUFFER
);
1142 in_dma
= channel_2_dma(channel
, IPU_VIDEO_IN_BUFFER
);
1144 if ((idma_is_valid(in_dma
) &&
1145 !idma_is_set(IDMAC_CHA_EN
, in_dma
))
1146 && (idma_is_valid(out_dma
) &&
1147 !idma_is_set(IDMAC_CHA_EN
, out_dma
)))
1150 if ((channel
== MEM_BG_SYNC
) || (channel
== MEM_FG_SYNC
) ||
1151 (channel
== MEM_DC_SYNC
)) {
1152 ipu_dp_dc_disable(channel
, 0);
1155 /* Disable DMA channel(s) */
1156 if (idma_is_valid(in_dma
)) {
1157 reg
= __raw_readl(IDMAC_CHA_EN(in_dma
));
1158 __raw_writel(reg
& ~idma_mask(in_dma
), IDMAC_CHA_EN(in_dma
));
1159 __raw_writel(idma_mask(in_dma
), IPU_CHA_CUR_BUF(in_dma
));
1161 if (idma_is_valid(out_dma
)) {
1162 reg
= __raw_readl(IDMAC_CHA_EN(out_dma
));
1163 __raw_writel(reg
& ~idma_mask(out_dma
), IDMAC_CHA_EN(out_dma
));
1164 __raw_writel(idma_mask(out_dma
), IPU_CHA_CUR_BUF(out_dma
));
1167 g_channel_enable_mask
&= ~(1L << IPU_CHAN_ID(channel
));
1169 /* Set channel buffers NOT to be ready */
1170 if (idma_is_valid(in_dma
)) {
1171 ipu_clear_buffer_ready(channel
, IPU_VIDEO_IN_BUFFER
, 0);
1172 ipu_clear_buffer_ready(channel
, IPU_VIDEO_IN_BUFFER
, 1);
1174 if (idma_is_valid(out_dma
)) {
1175 ipu_clear_buffer_ready(channel
, IPU_OUTPUT_BUFFER
, 0);
1176 ipu_clear_buffer_ready(channel
, IPU_OUTPUT_BUFFER
, 1);
1182 uint32_t bytes_per_pixel(uint32_t fmt
)
1185 case IPU_PIX_FMT_GENERIC
: /*generic data */
1186 case IPU_PIX_FMT_RGB332
:
1187 case IPU_PIX_FMT_YUV420P
:
1188 case IPU_PIX_FMT_YUV422P
:
1191 case IPU_PIX_FMT_RGB565
:
1192 case IPU_PIX_FMT_YUYV
:
1193 case IPU_PIX_FMT_UYVY
:
1196 case IPU_PIX_FMT_BGR24
:
1197 case IPU_PIX_FMT_RGB24
:
1200 case IPU_PIX_FMT_GENERIC_32
: /*generic data */
1201 case IPU_PIX_FMT_BGR32
:
1202 case IPU_PIX_FMT_BGRA32
:
1203 case IPU_PIX_FMT_RGB32
:
1204 case IPU_PIX_FMT_RGBA32
:
1205 case IPU_PIX_FMT_ABGR32
:
1215 ipu_color_space_t
format_to_colorspace(uint32_t fmt
)
1218 case IPU_PIX_FMT_RGB666
:
1219 case IPU_PIX_FMT_RGB565
:
1220 case IPU_PIX_FMT_BGR24
:
1221 case IPU_PIX_FMT_RGB24
:
1222 case IPU_PIX_FMT_BGR32
:
1223 case IPU_PIX_FMT_BGRA32
:
1224 case IPU_PIX_FMT_RGB32
:
1225 case IPU_PIX_FMT_RGBA32
:
1226 case IPU_PIX_FMT_ABGR32
:
1227 case IPU_PIX_FMT_LVDS666
:
1228 case IPU_PIX_FMT_LVDS888
:
1239 /* should be removed when clk framework is availiable */
1240 int ipu_set_ldb_clock(int rate
)
1242 ldb_clk
.rate
= rate
;