drivers/video/ipu_regs.h

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2010
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   6  *
   7  * Linux IPU driver for MX51:
   8  *
   9  * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #ifndef __IPU_REGS_INCLUDED__
  31 #define __IPU_REGS_INCLUDED__
  32
  33 #define IPU_DISP0_BASE          0x00000000
  34 #define IPU_MCU_T_DEFAULT       8
  35 #define IPU_DISP1_BASE          (IPU_MCU_T_DEFAULT << 25)
  36 #define IPU_CM_REG_BASE         0x00000000
  37 #define IPU_STAT_REG_BASE       0x00000200
  38 #define IPU_IDMAC_REG_BASE      0x00008000
  39 #define IPU_ISP_REG_BASE        0x00010000
  40 #define IPU_DP_REG_BASE         0x00018000
  41 #define IPU_IC_REG_BASE         0x00020000
  42 #define IPU_IRT_REG_BASE        0x00028000
  43 #define IPU_CSI0_REG_BASE       0x00030000
  44 #define IPU_CSI1_REG_BASE       0x00038000
  45 #define IPU_DI0_REG_BASE        0x00040000
  46 #define IPU_DI1_REG_BASE        0x00048000
  47 #define IPU_SMFC_REG_BASE       0x00050000
  48 #define IPU_DC_REG_BASE         0x00058000
  49 #define IPU_DMFC_REG_BASE       0x00060000
  50 #define IPU_VDI_REG_BASE        0x00680000
  51 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
  52 #define IPU_CPMEM_REG_BASE      0x01000000
  53 #define IPU_LUT_REG_BASE        0x01020000
  54 #define IPU_SRM_REG_BASE        0x01040000
  55 #define IPU_TPM_REG_BASE        0x01060000
  56 #define IPU_DC_TMPL_REG_BASE    0x01080000
  57 #define IPU_ISP_TBPR_REG_BASE   0x010C0000
  58 #elif defined(CONFIG_MX6)
  59 #define IPU_CPMEM_REG_BASE      0x00100000
  60 #define IPU_LUT_REG_BASE        0x00120000
  61 #define IPU_SRM_REG_BASE        0x00140000
  62 #define IPU_TPM_REG_BASE        0x00160000
  63 #define IPU_DC_TMPL_REG_BASE    0x00180000
  64 #define IPU_ISP_TBPR_REG_BASE   0x001C0000
  65 #endif
  66
  67 #define IPU_CTRL_BASE_ADDR      (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
  68
  69 extern u32 *ipu_dc_tmpl_reg;
  70
  71 #define DC_EVT_NF               0
  72 #define DC_EVT_NL               1
  73 #define DC_EVT_EOF              2
  74 #define DC_EVT_NFIELD           3
  75 #define DC_EVT_EOL              4
  76 #define DC_EVT_EOFIELD          5
  77 #define DC_EVT_NEW_ADDR         6
  78 #define DC_EVT_NEW_CHAN         7
  79 #define DC_EVT_NEW_DATA         8
  80
  81 #define DC_EVT_NEW_ADDR_W_0     0
  82 #define DC_EVT_NEW_ADDR_W_1     1
  83 #define DC_EVT_NEW_CHAN_W_0     2
  84 #define DC_EVT_NEW_CHAN_W_1     3
  85 #define DC_EVT_NEW_DATA_W_0     4
  86 #define DC_EVT_NEW_DATA_W_1     5
  87 #define DC_EVT_NEW_ADDR_R_0     6
  88 #define DC_EVT_NEW_ADDR_R_1     7
  89 #define DC_EVT_NEW_CHAN_R_0     8
  90 #define DC_EVT_NEW_CHAN_R_1     9
  91 #define DC_EVT_NEW_DATA_R_0     10
  92 #define DC_EVT_NEW_DATA_R_1     11
  93
  94 /* Software reset for ipu */
  95 #define SW_IPU_RST      8
  96
  97 enum {
  98         IPU_CONF_DP_EN = 0x00000020,
  99         IPU_CONF_DI0_EN = 0x00000040,
 100         IPU_CONF_DI1_EN = 0x00000080,
 101         IPU_CONF_DMFC_EN = 0x00000400,
 102         IPU_CONF_DC_EN = 0x00000200,
 103
 104         DI0_COUNTER_RELEASE = 0x01000000,
 105         DI1_COUNTER_RELEASE = 0x02000000,
 106
 107         DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
 108         DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
 109
 110         DI_GEN_DI_CLK_EXT = 0x100000,
 111         DI_GEN_POLARITY_1 = 0x00000001,
 112         DI_GEN_POLARITY_2 = 0x00000002,
 113         DI_GEN_POLARITY_3 = 0x00000004,
 114         DI_GEN_POLARITY_4 = 0x00000008,
 115         DI_GEN_POLARITY_5 = 0x00000010,
 116         DI_GEN_POLARITY_6 = 0x00000020,
 117         DI_GEN_POLARITY_7 = 0x00000040,
 118         DI_GEN_POLARITY_8 = 0x00000080,
 119         DI_GEN_POL_CLK = 0x20000,
 120
 121         DI_POL_DRDY_DATA_POLARITY = 0x00000080,
 122         DI_POL_DRDY_POLARITY_15 = 0x00000010,
 123         DI_VSYNC_SEL_OFFSET = 13,
 124
 125         DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
 126         DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
 127         DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
 128         DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
 129         DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
 130         DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
 131
 132         DP_COM_CONF_FG_EN = 0x00000001,
 133         DP_COM_CONF_GWSEL = 0x00000002,
 134         DP_COM_CONF_GWAM = 0x00000004,
 135         DP_COM_CONF_GWCKE = 0x00000008,
 136         DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
 137         DP_COM_CONF_CSC_DEF_OFFSET = 8,
 138         DP_COM_CONF_CSC_DEF_FG = 0x00000300,
 139         DP_COM_CONF_CSC_DEF_BG = 0x00000200,
 140         DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
 141         DP_COM_CONF_GAMMA_EN = 0x00001000,
 142         DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
 143 };
 144
 145 enum di_pins {
 146         DI_PIN11 = 0,
 147         DI_PIN12 = 1,
 148         DI_PIN13 = 2,
 149         DI_PIN14 = 3,
 150         DI_PIN15 = 4,
 151         DI_PIN16 = 5,
 152         DI_PIN17 = 6,
 153         DI_PIN_CS = 7,
 154
 155         DI_PIN_SER_CLK = 0,
 156         DI_PIN_SER_RS = 1,
 157 };
 158
 159 enum di_sync_wave {
 160         DI_SYNC_NONE = -1,
 161         DI_SYNC_CLK = 0,
 162         DI_SYNC_INT_HSYNC = 1,
 163         DI_SYNC_HSYNC = 2,
 164         DI_SYNC_VSYNC = 3,
 165         DI_SYNC_DE = 5,
 166 };
 167
 168 struct ipu_cm {
 169         u32 conf;
 170         u32 sisg_ctrl0;
 171         u32 sisg_ctrl1;
 172         u32 sisg_set[6];
 173         u32 sisg_clear[6];
 174         u32 int_ctrl[15];
 175         u32 sdma_event[10];
 176         u32 srm_pri1;
 177         u32 srm_pri2;
 178         u32 fs_proc_flow[3];
 179         u32 fs_disp_flow[2];
 180         u32 skip;
 181         u32 disp_alt_conf;
 182         u32 disp_gen;
 183         u32 disp_alt[4];
 184         u32 snoop;
 185         u32 mem_rst;
 186         u32 pm;
 187         u32 gpr;
 188         u32 reserved0[26];
 189         u32 ch_db_mode_sel[2];
 190         u32 reserved1[16];
 191         u32 alt_ch_db_mode_sel[2];
 192         u32 reserved2[2];
 193         u32 ch_trb_mode_sel[2];
 194 };
 195
 196 struct ipu_idmac {
 197         u32 conf;
 198         u32 ch_en[2];
 199         u32 sep_alpha;
 200         u32 alt_sep_alpha;
 201         u32 ch_pri[2];
 202         u32 wm_en[2];
 203         u32 lock_en[2];
 204         u32 sub_addr[5];
 205         u32 bndm_en[2];
 206         u32 sc_cord[2];
 207         u32 reserved[45];
 208         u32 ch_busy[2];
 209 };
 210
 211 struct ipu_com_async {
 212         u32 com_conf_async;
 213         u32 graph_wind_ctrl_async;
 214         u32 fg_pos_async;
 215         u32 cur_pos_async;
 216         u32 cur_map_async;
 217         u32 gamma_c_async[8];
 218         u32 gamma_s_async[4];
 219         u32 dp_csca_async[4];
 220         u32 dp_csc_async[2];
 221 };
 222
 223 struct ipu_dp {
 224         u32 com_conf_sync;
 225         u32 graph_wind_ctrl_sync;
 226         u32 fg_pos_sync;
 227         u32 cur_pos_sync;
 228         u32 cur_map_sync;
 229         u32 gamma_c_sync[8];
 230         u32 gamma_s_sync[4];
 231         u32 csca_sync[4];
 232         u32 csc_sync[2];
 233         u32 cur_pos_alt;
 234         struct ipu_com_async async[2];
 235 };
 236
 237 struct ipu_di {
 238         u32 general;
 239         u32 bs_clkgen0;
 240         u32 bs_clkgen1;
 241         u32 sw_gen0[9];
 242         u32 sw_gen1[9];
 243         u32 sync_as;
 244         u32 dw_gen[12];
 245         u32 dw_set[48];
 246         u32 stp_rep[4];
 247         u32 stp_rep9;
 248         u32 ser_conf;
 249         u32 ssc;
 250         u32 pol;
 251         u32 aw0;
 252         u32 aw1;
 253         u32 scr_conf;
 254         u32 stat;
 255 };
 256
 257 struct ipu_stat {
 258         u32 int_stat[15];
 259         u32 cur_buf[2];
 260         u32 alt_cur_buf_0;
 261         u32 alt_cur_buf_1;
 262         u32 srm_stat;
 263         u32 proc_task_stat;
 264         u32 disp_task_stat;
 265         u32 triple_cur_buf[4];
 266         u32 ch_buf0_rdy[2];
 267         u32 ch_buf1_rdy[2];
 268         u32 alt_ch_buf0_rdy[2];
 269         u32 alt_ch_buf1_rdy[2];
 270         u32 ch_buf2_rdy[2];
 271 };
 272
 273 struct ipu_dc_ch {
 274         u32 wr_ch_conf;
 275         u32 wr_ch_addr;
 276         u32 rl[5];
 277 };
 278
 279 struct ipu_dc {
 280         struct ipu_dc_ch dc_ch0_1_2[3];
 281         u32 cmd_ch_conf_3;
 282         u32 cmd_ch_conf_4;
 283         struct ipu_dc_ch dc_ch5_6[2];
 284         struct ipu_dc_ch dc_ch8;
 285         u32 rl6_ch_8;
 286         struct ipu_dc_ch dc_ch9;
 287         u32 rl6_ch_9;
 288         u32 gen;
 289         u32 disp_conf1[4];
 290         u32 disp_conf2[4];
 291         u32 di0_conf[2];
 292         u32 di1_conf[2];
 293         u32 dc_map_ptr[15];
 294         u32 dc_map_val[12];
 295         u32 udge[16];
 296         u32 lla[2];
 297         u32 r_lla[2];
 298         u32 wr_ch_addr_5_alt;
 299         u32 stat;
 300 };
 301
 302 struct ipu_dmfc {
 303         u32 rd_chan;
 304         u32 wr_chan;
 305         u32 wr_chan_def;
 306         u32 dp_chan;
 307         u32 dp_chan_def;
 308         u32 general[2];
 309         u32 ic_ctrl;
 310         u32 wr_chan_alt;
 311         u32 wr_chan_def_alt;
 312         u32 general1_alt;
 313         u32 stat;
 314 };
 315
 316 #define IPU_CM_REG              ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \
 317                                 IPU_CM_REG_BASE))
 318 #define IPU_CONF                (&IPU_CM_REG->conf)
 319 #define IPU_SRM_PRI1            (&IPU_CM_REG->srm_pri1)
 320 #define IPU_SRM_PRI2            (&IPU_CM_REG->srm_pri2)
 321 #define IPU_FS_PROC_FLOW1       (&IPU_CM_REG->fs_proc_flow[0])
 322 #define IPU_FS_PROC_FLOW2       (&IPU_CM_REG->fs_proc_flow[1])
 323 #define IPU_FS_PROC_FLOW3       (&IPU_CM_REG->fs_proc_flow[2])
 324 #define IPU_FS_DISP_FLOW1       (&IPU_CM_REG->fs_disp_flow[0])
 325 #define IPU_DISP_GEN            (&IPU_CM_REG->disp_gen)
 326 #define IPU_MEM_RST             (&IPU_CM_REG->mem_rst)
 327 #define IPU_GPR                 (&IPU_CM_REG->gpr)
 328 #define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])
 329
 330 #define IPU_STAT                ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
 331                                 IPU_STAT_REG_BASE))
 332 #define IPU_CHA_CUR_BUF(ch)     (&IPU_STAT->cur_buf[ch / 32])
 333 #define IPU_CHA_BUF0_RDY(ch)    (&IPU_STAT->ch_buf0_rdy[ch / 32])
 334 #define IPU_CHA_BUF1_RDY(ch)    (&IPU_STAT->ch_buf1_rdy[ch / 32])
 335
 336 #define IPU_INT_CTRL(n)         (&IPU_CM_REG->int_ctrl[(n) - 1])
 337
 338 #define IDMAC_REG               ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \
 339                                 IPU_IDMAC_REG_BASE))
 340 #define IDMAC_CONF              (&IDMAC_REG->conf)
 341 #define IDMAC_CHA_EN(ch)        (&IDMAC_REG->ch_en[ch / 32])
 342 #define IDMAC_CHA_PRI(ch)       (&IDMAC_REG->ch_pri[ch / 32])
 343
 344 #define DI_REG(di)              ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
 345                                 ((di == 1) ? IPU_DI1_REG_BASE : \
 346                                 IPU_DI0_REG_BASE)))
 347 #define DI_GENERAL(di)          (&DI_REG(di)->general)
 348 #define DI_BS_CLKGEN0(di)       (&DI_REG(di)->bs_clkgen0)
 349 #define DI_BS_CLKGEN1(di)       (&DI_REG(di)->bs_clkgen1)
 350
 351 #define DI_SW_GEN0(di, gen)     (&DI_REG(di)->sw_gen0[gen - 1])
 352 #define DI_SW_GEN1(di, gen)     (&DI_REG(di)->sw_gen1[gen - 1])
 353 #define DI_STP_REP(di, gen)     (&DI_REG(di)->stp_rep[(gen - 1) / 2])
 354 #define DI_SYNC_AS_GEN(di)      (&DI_REG(di)->sync_as)
 355 #define DI_DW_GEN(di, gen)      (&DI_REG(di)->dw_gen[gen])
 356 #define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
 357 #define DI_POL(di)              (&DI_REG(di)->pol)
 358 #define DI_SCR_CONF(di)         (&DI_REG(di)->scr_conf)
 359
 360 #define DMFC_REG                ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \
 361                                 IPU_DMFC_REG_BASE))
 362 #define DMFC_WR_CHAN            (&DMFC_REG->wr_chan)
 363 #define DMFC_WR_CHAN_DEF        (&DMFC_REG->wr_chan_def)
 364 #define DMFC_DP_CHAN            (&DMFC_REG->dp_chan)
 365 #define DMFC_DP_CHAN_DEF        (&DMFC_REG->dp_chan_def)
 366 #define DMFC_GENERAL1           (&DMFC_REG->general[0])
 367 #define DMFC_IC_CTRL            (&DMFC_REG->ic_ctrl)
 368
 369
 370 #define DC_REG                  ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \
 371                                 IPU_DC_REG_BASE))
 372 #define DC_MAP_CONF_PTR(n)      (&DC_REG->dc_map_ptr[n / 2])
 373 #define DC_MAP_CONF_VAL(n)      (&DC_REG->dc_map_val[n / 2])
 374
 375
 376 static inline struct ipu_dc_ch *dc_ch_offset(int ch)
 377 {
 378         switch (ch) {
 379         case 0:
 380         case 1:
 381         case 2:
 382                 return &DC_REG->dc_ch0_1_2[ch];
 383         case 5:
 384         case 6:
 385                 return &DC_REG->dc_ch5_6[ch - 5];
 386         case 8:
 387                 return &DC_REG->dc_ch8;
 388         case 9:
 389                 return &DC_REG->dc_ch9;
 390         default:
 391                 printf("%s: invalid channel %d\n", __func__, ch);
 392                 return NULL;
 393         }
 394
 395 }
 396
 397 #define DC_RL_CH(ch, evt)       (&dc_ch_offset(ch)->rl[evt / 2])
 398
 399 #define DC_WR_CH_CONF(ch)       (&dc_ch_offset(ch)->wr_ch_conf)
 400 #define DC_WR_CH_ADDR(ch)       (&dc_ch_offset(ch)->wr_ch_addr)
 401
 402 #define DC_WR_CH_CONF_1         DC_WR_CH_CONF(1)
 403 #define DC_WR_CH_CONF_5         DC_WR_CH_CONF(5)
 404
 405 #define DC_GEN                  (&DC_REG->gen)
 406 #define DC_DISP_CONF2(disp)     (&DC_REG->disp_conf2[disp])
 407 #define DC_STAT                 (&DC_REG->stat)
 408
 409 #define DP_SYNC 0
 410 #define DP_ASYNC0 0x60
 411 #define DP_ASYNC1 0xBC
 412
 413 #define DP_REG                  ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
 414                                 IPU_DP_REG_BASE))
 415 #define DP_COM_CONF()           (&DP_REG->com_conf_sync)
 416 #define DP_GRAPH_WIND_CTRL()    (&DP_REG->graph_wind_ctrl_sync)
 417 #define DP_CSC_A_0()            (&DP_REG->csca_sync[0])
 418 #define DP_CSC_A_1()            (&DP_REG->csca_sync[1])
 419 #define DP_CSC_A_2()            (&DP_REG->csca_sync[2])
 420 #define DP_CSC_A_3()            (&DP_REG->csca_sync[3])
 421
 422 #define DP_CSC_0()              (&DP_REG->csc_sync[0])
 423 #define DP_CSC_1()              (&DP_REG->csc_sync[1])
 424
 425 /* DC template opcodes */
 426 #define WROD(lf)                (0x18 | (lf << 1))
 427
 428 #endif