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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/video/mb862xx.c
3 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
26 * PCI and video mode code was derived from smiLynxEM driver.
34 #include "videomodes.h"
37 #if defined(CONFIG_POST)
43 GraphicDevice mb862xx
;
46 * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
48 #define VIDEO_MEM_SIZE 0x01FC0000
50 #if defined(CONFIG_PCI)
51 #if defined(CONFIG_VIDEO_CORALP)
53 static struct pci_device_id supported
[] = {
54 { PCI_VENDOR_ID_FUJITSU
, PCI_DEVICE_ID_CORAL_P
},
55 { PCI_VENDOR_ID_FUJITSU
, PCI_DEVICE_ID_CORAL_PA
},
59 /* Internal clock frequency divider table, index is mode number */
60 unsigned int fr_div
[] = { 0x00000f00, 0x00000900, 0x00000500 };
64 #if defined(CONFIG_VIDEO_CORALP)
68 #define rd_io(addr) in_be32((volatile unsigned*)(addr))
69 #define wr_io(addr,val) out_be32((volatile unsigned*)(addr), (val))
72 #define HOST_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fc0000 + (off)))
73 #define HOST_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fc0000 + (off)), (val))
74 #define DISP_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fd0000 + (off)))
75 #define DISP_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fd0000 + (off)), (val))
76 #define DE_RD_REG(off) rd_io((pGD->dprBase + (off)))
77 #define DE_WR_REG(off, val) wr_io((pGD->dprBase + (off)), (val))
79 #if defined(CONFIG_VIDEO_CORALP)
80 #define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x8400)), (val))
82 #define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x04a0)), (val))
85 #define L0PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)))
86 #define L0PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)), (val))
87 #define L1PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)))
88 #define L1PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)), (val))
89 #define L2PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)))
90 #define L2PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)), (val))
91 #define L3PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)))
92 #define L3PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)), (val))
94 static void gdc_sw_reset(void)
96 GraphicDevice
*pGD
= (GraphicDevice
*)&mb862xx
;
97 HOST_WR_REG (0x002c, 0x00000001);
103 static void de_wait(void)
105 GraphicDevice
*pGD
= (GraphicDevice
*)&mb862xx
;
108 /* Sync with software writes to framebuffer,
109 try to reset if engine locked */
110 while (DE_RD_REG (0x0400) & 0x00000131)
113 printf ("gdc reset done after drawing engine lock...\n");
118 static void de_wait_slots(int slots
)
120 GraphicDevice
*pGD
= (GraphicDevice
*)&mb862xx
;
123 /* Wait for free fifo slots */
124 while (DE_RD_REG (0x0408) < slots
)
127 printf ("gdc reset done after drawing engine lock...\n");
132 #if !defined(CONFIG_VIDEO_CORALP)
133 static void board_disp_init(void)
135 GraphicDevice
*pGD
= (GraphicDevice
*)&mb862xx
;
136 const gdc_regs
*regs
= board_get_regs ();
138 while (regs
->index
) {
139 DISP_WR_REG (regs
->index
, regs
->value
);
146 * Init drawing engine
148 static void de_init (void)
150 GraphicDevice
*pGD
= (GraphicDevice
*)&mb862xx
;
151 int cf
= (pGD
->gdfBytesPP
== 1) ? 0x0000 : 0x8000;
153 pGD
->dprBase
= pGD
->frameAdrs
+ 0x01ff0000;
155 /* Setup mode and fbbase, xres, fg, bg */
157 DE_WR_FIFO (0xf1010108);
158 DE_WR_FIFO (cf
| 0x0300);
159 DE_WR_REG (0x0440, 0x0000);
160 DE_WR_REG (0x0444, pGD
->winSizeX
);
161 DE_WR_REG (0x0480, 0x0000);
162 DE_WR_REG (0x0484, 0x0000);
164 DE_WR_REG (0x0454, 0x0000);
165 DE_WR_REG (0x0458, pGD
->winSizeX
);
166 DE_WR_REG (0x045c, 0x0000);
167 DE_WR_REG (0x0460, pGD
->winSizeY
);
169 /* Clear framebuffer using drawing engine */
171 DE_WR_FIFO (0x09410000);
172 DE_WR_FIFO (0x00000000);
173 DE_WR_FIFO (pGD
->winSizeY
<<16 | pGD
->winSizeX
);
174 /* sync with SW access to framebuffer */
178 #if defined(CONFIG_VIDEO_CORALP)
179 unsigned int pci_video_init(void)
181 GraphicDevice
*pGD
= (GraphicDevice
*)&mb862xx
;
184 if ((devbusfn
= pci_find_devices(supported
, 0)) < 0)
186 printf ("PCI video controller not found!\n");
191 pci_write_config_dword (devbusfn
, PCI_COMMAND
, (PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
));
192 pci_read_config_dword (devbusfn
, PCI_BASE_ADDRESS_0
, &pGD
->frameAdrs
);
193 pGD
->frameAdrs
= pci_mem_to_phys (devbusfn
, pGD
->frameAdrs
);
195 if (pGD
->frameAdrs
== 0) {
196 printf ("PCI config: failed to get base address\n");
200 pGD
->pciBase
= pGD
->frameAdrs
;
202 /* Setup clocks and memory mode for Coral-P Eval. Board */
203 HOST_WR_REG (0x0038, 0x00090000);
205 HOST_WR_REG (0xfffc, 0x11d7fa13);
207 return pGD
->frameAdrs
;
210 unsigned int card_init (void)
212 GraphicDevice
*pGD
= (GraphicDevice
*)&mb862xx
;
213 unsigned int cf
, videomode
, div
= 0;
214 unsigned long t1
, hsync
, vsync
;
217 struct ctfb_res_modes
*res_mode
;
218 struct ctfb_res_modes var_mode
;
220 memset (pGD
, 0, sizeof (GraphicDevice
));
222 if (!pci_video_init ()) {
230 /* get video mode via environment */
231 if ((penv
= getenv ("videomode")) != NULL
) {
232 /* deceide if it is a string */
233 if (penv
[0] <= '9') {
234 videomode
= (int) simple_strtoul (penv
, NULL
, 16);
241 /* parameter are vesa modes */
243 for (i
= 0; i
< VESA_MODES_COUNT
; i
++) {
244 if (vesa_modes
[i
].vesanr
== videomode
)
247 if (i
== VESA_MODES_COUNT
) {
248 printf ("\tno VESA Mode found, switching to mode 0x%x \n", videomode
);
252 (struct ctfb_res_modes
*) &res_mode_init
[vesa_modes
[i
].resindex
];
253 if (vesa_modes
[i
].resindex
> 2) {
254 printf ("\tUnsupported resolution, switching to default\n");
255 bpp
= vesa_modes
[1].bits_per_pixel
;
258 bpp
= vesa_modes
[i
].bits_per_pixel
;
259 div
= fr_div
[vesa_modes
[i
].resindex
];
262 res_mode
= (struct ctfb_res_modes
*) &var_mode
;
263 bpp
= video_get_params (res_mode
, penv
);
266 /* calculate hsync and vsync freq (info only) */
267 t1
= (res_mode
->left_margin
+ res_mode
->xres
+
268 res_mode
->right_margin
+ res_mode
->hsync_len
) / 8;
270 t1
*= res_mode
->pixclock
;
272 hsync
= 1000000000L / t1
;
273 t1
*= (res_mode
->upper_margin
+ res_mode
->yres
+
274 res_mode
->lower_margin
+ res_mode
->vsync_len
);
276 vsync
= 1000000000L / t1
;
278 /* fill in Graphic device struct */
279 sprintf (pGD
->modeIdent
, "%dx%dx%d %ldkHz %ldHz", res_mode
->xres
,
280 res_mode
->yres
, bpp
, (hsync
/ 1000), (vsync
/ 1000));
281 printf ("\t%s\n", pGD
->modeIdent
);
282 pGD
->winSizeX
= res_mode
->xres
;
283 pGD
->winSizeY
= res_mode
->yres
;
284 pGD
->memSize
= VIDEO_MEM_SIZE
;
288 pGD
->gdfIndex
= GDF__8BIT_INDEX
;
293 pGD
->gdfIndex
= GDF_15BIT_555RGB
;
297 printf ("\t%d bpp configured, but only 8,15 and 16 supported.\n", bpp
);
298 printf ("\tSwitching back to 15bpp\n");
299 pGD
->gdfIndex
= GDF_15BIT_555RGB
;
303 /* Setup dot clock (internal pll, division rate) */
304 DISP_WR_REG (0x0100, div
);
306 cf
= (pGD
->gdfBytesPP
== 1) ? 0x00000000 : 0x80000000;
307 DISP_WR_REG (0x0020, ((pGD
->winSizeX
* pGD
->gdfBytesPP
)/64)<<16 |
310 DISP_WR_REG (0x0024, 0x00000000);
311 DISP_WR_REG (0x0028, 0x00000000);
312 DISP_WR_REG (0x002c, 0x00000000);
313 DISP_WR_REG (0x0110, 0x00000000);
314 DISP_WR_REG (0x0114, 0x00000000);
315 DISP_WR_REG (0x0118, (pGD
->winSizeY
-1)<<16 | pGD
->winSizeX
);
317 /* Display timing init */
318 DISP_WR_REG (0x0004, (pGD
->winSizeX
+res_mode
->left_margin
+res_mode
->right_margin
+res_mode
->hsync_len
-1)<<16);
319 DISP_WR_REG (0x0008, (pGD
->winSizeX
-1) << 16 | (pGD
->winSizeX
-1));
320 DISP_WR_REG (0x000c, (res_mode
->vsync_len
-1)<<24|(res_mode
->hsync_len
-1)<<16|(pGD
->winSizeX
+res_mode
->right_margin
-1));
321 DISP_WR_REG (0x0010, (pGD
->winSizeY
+res_mode
->lower_margin
+res_mode
->upper_margin
+res_mode
->vsync_len
-1)<<16);
322 DISP_WR_REG (0x0014, (pGD
->winSizeY
-1) << 16 | (pGD
->winSizeY
+res_mode
->lower_margin
-1));
323 DISP_WR_REG (0x0018, 0x00000000);
324 DISP_WR_REG (0x001c, pGD
->winSizeY
<< 16 | pGD
->winSizeX
);
325 /* Display enable, L0 layer */
326 DISP_WR_REG (0x0100, 0x80010000 | div
);
328 return pGD
->frameAdrs
;
332 void *video_hw_init (void)
334 GraphicDevice
*pGD
= (GraphicDevice
*)&mb862xx
;
336 printf ("Video: Fujitsu ");
338 memset (pGD
, 0, sizeof (GraphicDevice
));
340 #if defined(CONFIG_VIDEO_CORALP)
341 if (card_init () == 0) {
345 /* Preliminary init of the onboard graphic controller,
346 retrieve base address */
347 if ((pGD
->frameAdrs
= board_video_init ()) == 0) {
348 printf ("Controller not found!\n");
356 #if !defined(CONFIG_VIDEO_CORALP)
360 #if (defined(CONFIG_LWMON5) || \
361 defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
363 board_backlight_switch (1);
370 * Set a RGB color in the LUT
372 void video_set_lut (unsigned int index
, unsigned char r
, unsigned char g
, unsigned char b
)
374 GraphicDevice
*pGD
= (GraphicDevice
*)&mb862xx
;
376 L0PAL_WR_REG (index
, (r
<< 16) | (g
<< 8) | (b
));
380 * Drawing engine Fill and BitBlt screen region
382 void video_hw_rectfill (unsigned int bpp
, unsigned int dst_x
, unsigned int dst_y
,
383 unsigned int dim_x
, unsigned int dim_y
, unsigned int color
)
385 GraphicDevice
*pGD
= (GraphicDevice
*)&mb862xx
;
388 DE_WR_REG (0x0480, color
);
389 DE_WR_FIFO (0x09410000);
390 DE_WR_FIFO ((dst_y
<< 16) | dst_x
);
391 DE_WR_FIFO ((dim_y
<< 16) | dim_x
);
395 void video_hw_bitblt (unsigned int bpp
, unsigned int src_x
, unsigned int src_y
,
396 unsigned int dst_x
, unsigned int dst_y
, unsigned int width
,
399 GraphicDevice
*pGD
= (GraphicDevice
*)&mb862xx
;
400 unsigned int ctrl
= 0x0d000000L
;
402 if (src_x
>= dst_x
&& src_y
>= dst_y
)
404 else if (src_x
>= dst_x
&& src_y
<= dst_y
)
406 else if (src_x
<= dst_x
&& src_y
>= dst_y
)
413 DE_WR_FIFO ((src_y
<< 16) | src_x
);
414 DE_WR_FIFO ((dst_y
<< 16) | dst_x
);
415 DE_WR_FIFO ((height
<< 16) | width
);
416 de_wait (); /* sync */