]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/video/mb86r0xgdc.c
3 * Matthias Weisser <weisserm@arcor.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic
33 #include <asm/arch/hardware.h>
35 #include "videomodes.h"
38 * 4MB (at the end of system RAM)
40 #define VIDEO_MEM_SIZE 0x400000
42 #define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */
47 static GraphicDevice mb86r0x
;
49 static void dsp_init(struct mb86r0x_gdc_dsp
*dsp
, char *modestr
,
52 struct ctfb_res_modes var_mode
;
54 u16 htp
, hdp
, hdb
, hsp
, vtr
, vsp
, vdp
;
56 u32 l2m
, l2em
, l2oa0
, l2da0
, l2oa1
, l2da1
;
57 u16 l2dx
, l2dy
, l2wx
, l2wy
, l2ww
, l2wh
;
62 bpp
= video_get_params(&var_mode
, modestr
);
67 var_mode
.pixclock
= 39721; /* 25MHz */
68 var_mode
.left_margin
= 48;
69 var_mode
.right_margin
= 16;
70 var_mode
.upper_margin
= 33;
71 var_mode
.lower_margin
= 10;
72 var_mode
.hsync_len
= 96;
73 var_mode
.vsync_len
= 2;
79 /* Fill memory with white */
80 for (i
= 0; i
< var_mode
.xres
* var_mode
.yres
/ 2; i
++)
81 *videomem
++ = 0xFFFFFFFF;
83 mb86r0x
.winSizeX
= var_mode
.xres
;
84 mb86r0x
.winSizeY
= var_mode
.yres
;
86 /* LCD base clock is ~ 660MHZ. We do calculations in kHz */
87 div
= 660000 / (1000000000L / var_mode
.pixclock
);
93 dcm1
= (div
- 1) << 8;
95 if (var_mode
.sync
& FB_SYNC_CLK_INV
)
100 htp
= var_mode
.left_margin
+ var_mode
.xres
+
101 var_mode
.hsync_len
+ var_mode
.right_margin
;
104 hsp
= var_mode
.xres
+ var_mode
.right_margin
;
105 hsw
= var_mode
.hsync_len
;
107 vsw
= var_mode
.vsync_len
;
108 vtr
= var_mode
.upper_margin
+ var_mode
.yres
+
109 var_mode
.vsync_len
+ var_mode
.lower_margin
;
110 vsp
= var_mode
.yres
+ var_mode
.lower_margin
;
113 l2m
= ((var_mode
.yres
- 1) << (0)) |
114 (((var_mode
.xres
* 2) / 64) << (16)) |
117 l2em
= (1 << 0) | (1 << 1);
119 l2oa0
= mb86r0x
.frameAdrs
;
120 l2da0
= mb86r0x
.frameAdrs
;
121 l2oa1
= mb86r0x
.frameAdrs
;
122 l2da1
= mb86r0x
.frameAdrs
;
127 l2ww
= var_mode
.xres
;
128 l2wh
= var_mode
.yres
- 1;
130 writel(dcm1
, &dsp
->dcm1
);
131 writel(dcm2
, &dsp
->dcm2
);
132 writel(dcm3
, &dsp
->dcm3
);
134 writew(htp
, &dsp
->htp
);
135 writew(hdp
, &dsp
->hdp
);
136 writew(hdb
, &dsp
->hdb
);
137 writew(hsp
, &dsp
->hsp
);
138 writeb(hsw
, &dsp
->hsw
);
140 writeb(vsw
, &dsp
->vsw
);
141 writew(vtr
, &dsp
->vtr
);
142 writew(vsp
, &dsp
->vsp
);
143 writew(vdp
, &dsp
->vdp
);
145 writel(l2m
, &dsp
->l2m
);
146 writel(l2em
, &dsp
->l2em
);
147 writel(l2oa0
, &dsp
->l2oa0
);
148 writel(l2da0
, &dsp
->l2da0
);
149 writel(l2oa1
, &dsp
->l2oa1
);
150 writel(l2da1
, &dsp
->l2da1
);
151 writew(l2dx
, &dsp
->l2dx
);
152 writew(l2dy
, &dsp
->l2dy
);
153 writew(l2wx
, &dsp
->l2wx
);
154 writew(l2wy
, &dsp
->l2wy
);
155 writew(l2ww
, &dsp
->l2ww
);
156 writew(l2wh
, &dsp
->l2wh
);
158 writel(dcm1
| (1 << 18) | (1 << 31), &dsp
->dcm1
);
161 void *video_hw_init(void)
163 struct mb86r0x_gdc
*gdc
= (struct mb86r0x_gdc
*) MB86R0x_GDC_BASE
;
164 GraphicDevice
*pGD
= &mb86r0x
;
168 memset(pGD
, 0, sizeof(GraphicDevice
));
170 pGD
->gdfIndex
= GDF_15BIT_555RGB
;
172 pGD
->memSize
= VIDEO_MEM_SIZE
;
173 pGD
->frameAdrs
= PHYS_SDRAM
+ PHYS_SDRAM_SIZE
- VIDEO_MEM_SIZE
;
175 vid
= (u32
*)pGD
->frameAdrs
;
177 s
= getenv("videomode");
179 dsp_init(&gdc
->dsp0
, s
, vid
);
181 s
= getenv("videomode1");
183 dsp_init(&gdc
->dsp1
, s
, vid
);