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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/video/mpc8xx_lcd.c
2 * (C) Copyright 2001-2002
3 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /************************************************************************/
26 /************************************************************************/
37 #include <linux/types.h>
38 #include <stdio_dev.h>
39 #if defined(CONFIG_POST)
46 /************************************************************************/
47 /* ** CONFIG STUFF -- should be moved to board config file */
48 /************************************************************************/
49 #ifndef CONFIG_LCD_INFO
50 #define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
53 #if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
54 #undef CONFIG_LCD_LOGO
55 #undef CONFIG_LCD_INFO
58 /*----------------------------------------------------------------------*/
59 #ifdef CONFIG_KYOCERA_KCS057QV1AJ
61 * Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
63 #define LCD_BPP LCD_COLOR4
65 vidinfo_t panel_info
= {
66 640, 480, 132, 99, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
,
67 LCD_BPP
, 1, 0, 1, 0, 5, 0, 0, 0
68 /* wbl, vpw, lcdac, wbf */
70 #endif /* CONFIG_KYOCERA_KCS057QV1AJ */
71 /*----------------------------------------------------------------------*/
73 /*----------------------------------------------------------------------*/
74 #ifdef CONFIG_HITACHI_SP19X001_Z1A
76 * Hitachi SP19X001-. Active, color, single scan.
78 vidinfo_t panel_info
= {
79 640, 480, 154, 116, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
,
80 LCD_COLOR8
, 1, 0, 1, 0, 0, 0, 0, 0
81 /* wbl, vpw, lcdac, wbf */
83 #endif /* CONFIG_HITACHI_SP19X001_Z1A */
84 /*----------------------------------------------------------------------*/
86 /*----------------------------------------------------------------------*/
87 #ifdef CONFIG_NEC_NL6448AC33
89 * NEC NL6448AC33-18. Active, color, single scan.
91 vidinfo_t panel_info
= {
92 640, 480, 132, 99, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_LOW
, CONFIG_SYS_LOW
, CONFIG_SYS_HIGH
,
93 3, 0, 0, 1, 1, 144, 2, 0, 33
94 /* wbl, vpw, lcdac, wbf */
96 #endif /* CONFIG_NEC_NL6448AC33 */
97 /*----------------------------------------------------------------------*/
99 #ifdef CONFIG_NEC_NL6448BC20
101 * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan.
103 vidinfo_t panel_info
= {
104 640, 480, 132, 99, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_LOW
, CONFIG_SYS_LOW
, CONFIG_SYS_HIGH
,
105 3, 0, 0, 1, 1, 144, 2, 0, 33
106 /* wbl, vpw, lcdac, wbf */
108 #endif /* CONFIG_NEC_NL6448BC20 */
109 /*----------------------------------------------------------------------*/
111 #ifdef CONFIG_NEC_NL6448BC33_54
113 * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
115 vidinfo_t panel_info
= {
116 640, 480, 212, 158, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_LOW
, CONFIG_SYS_LOW
, CONFIG_SYS_HIGH
,
117 3, 0, 0, 1, 1, 144, 2, 0, 33
118 /* wbl, vpw, lcdac, wbf */
120 #endif /* CONFIG_NEC_NL6448BC33_54 */
121 /*----------------------------------------------------------------------*/
123 #ifdef CONFIG_SHARP_LQ104V7DS01
125 * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
127 vidinfo_t panel_info
= {
128 640, 480, 132, 99, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_LOW
, CONFIG_SYS_LOW
, CONFIG_SYS_LOW
,
129 3, 0, 0, 1, 1, 25, 1, 0, 33
130 /* wbl, vpw, lcdac, wbf */
132 #endif /* CONFIG_SHARP_LQ104V7DS01 */
133 /*----------------------------------------------------------------------*/
135 #ifdef CONFIG_SHARP_16x9
137 * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am
138 * not sure what it is.......
140 vidinfo_t panel_info
= {
141 320, 240, 0, 0, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
,
142 3, 0, 0, 1, 1, 15, 4, 0, 3
144 #endif /* CONFIG_SHARP_16x9 */
145 /*----------------------------------------------------------------------*/
147 #ifdef CONFIG_SHARP_LQ057Q3DC02
149 * Sharp LQ057Q3DC02 display. Active, color, single scan.
154 vidinfo_t panel_info
= {
155 320, 240, 0, 0, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_LOW
, CONFIG_SYS_LOW
, CONFIG_SYS_HIGH
,
156 3, 0, 0, 1, 1, 15, 4, 0, 3
157 /* wbl, vpw, lcdac, wbf */
159 #define CONFIG_LCD_INFO_BELOW_LOGO
160 #endif /* CONFIG_SHARP_LQ057Q3DC02 */
161 /*----------------------------------------------------------------------*/
163 #ifdef CONFIG_SHARP_LQ64D341
165 * Sharp LQ64D341 display, 640x480. Active, color, single scan.
167 vidinfo_t panel_info
= {
168 640, 480, 0, 0, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_LOW
, CONFIG_SYS_LOW
, CONFIG_SYS_HIGH
,
169 3, 0, 0, 1, 1, 128, 16, 0, 32
170 /* wbl, vpw, lcdac, wbf */
172 #endif /* CONFIG_SHARP_LQ64D341 */
174 #ifdef CONFIG_SHARP_LQ065T9DR51U
176 * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
178 vidinfo_t panel_info
= {
179 400, 240, 143, 79, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
,
180 3, 0, 0, 1, 1, 248, 4, 0, 35
181 /* wbl, vpw, lcdac, wbf */
183 #define CONFIG_LCD_INFO_BELOW_LOGO
184 #endif /* CONFIG_SHARP_LQ065T9DR51U */
186 #ifdef CONFIG_SHARP_LQ084V1DG21
188 * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
190 vidinfo_t panel_info
= {
191 640, 480, 171, 129, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_LOW
, CONFIG_SYS_LOW
, CONFIG_SYS_LOW
,
192 3, 0, 0, 1, 1, 160, 3, 0, 48
193 /* wbl, vpw, lcdac, wbf */
195 #endif /* CONFIG_SHARP_LQ084V1DG21 */
197 /*----------------------------------------------------------------------*/
199 #ifdef CONFIG_HLD1045
201 * HLD1045 display, 640x480. Active, color, single scan.
203 vidinfo_t panel_info
= {
204 640, 480, 0, 0, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_LOW
, CONFIG_SYS_LOW
, CONFIG_SYS_HIGH
,
205 3, 0, 0, 1, 1, 160, 3, 0, 48
206 /* wbl, vpw, lcdac, wbf */
208 #endif /* CONFIG_HLD1045 */
209 /*----------------------------------------------------------------------*/
211 #ifdef CONFIG_PRIMEVIEW_V16C6448AC
213 * Prime View V16C6448AC
215 vidinfo_t panel_info
= {
216 640, 480, 130, 98, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_LOW
, CONFIG_SYS_LOW
, CONFIG_SYS_HIGH
,
217 3, 0, 0, 1, 1, 144, 2, 0, 35
218 /* wbl, vpw, lcdac, wbf */
220 #endif /* CONFIG_PRIMEVIEW_V16C6448AC */
222 /*----------------------------------------------------------------------*/
224 #ifdef CONFIG_OPTREX_BW
226 * Optrex CBL50840-2 NF-FW 99 22 M5
228 * Hitachi LMG6912RPFC-00T
232 * 320x240. Black & white.
234 #define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */
235 /* 1 - 4 grey levels, 2 bpp */
236 /* 2 - 16 grey levels, 4 bpp */
237 vidinfo_t panel_info
= {
238 320, 240, 0, 0, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_LOW
,
239 OPTREX_BPP
, 0, 0, 0, 0, 0, 0, 0, 0, 4
241 #endif /* CONFIG_OPTREX_BW */
243 /*-----------------------------------------------------------------*/
244 #ifdef CONFIG_EDT32F10
246 * Emerging Display Technologies 320x240. Passive, monochrome, single scan.
248 #define LCD_BPP LCD_MONOCHROME
251 vidinfo_t panel_info
= {
252 320, 240, 0, 0, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_HIGH
, CONFIG_SYS_LOW
,
253 LCD_BPP
, 0, 0, 0, 0, 33, 0, 0, 0
256 /*----------------------------------------------------------------------*/
258 void lcd_ctrl_init (void *lcdbase
);
259 void lcd_enable (void);
260 #if LCD_BPP == LCD_COLOR8
261 void lcd_setcolreg (ushort regno
,
262 ushort red
, ushort green
, ushort blue
);
264 #if LCD_BPP == LCD_MONOCHROME
265 void lcd_initcolregs (void);
268 #if defined(CONFIG_RBC823)
269 void lcd_disable (void);
272 /************************************************************************/
274 /************************************************************************/
275 /* ----------------- chipset specific functions ----------------------- */
276 /************************************************************************/
279 * Calculate fb size for VIDEOLFB_ATAG.
281 ulong
calc_fbsize (void)
284 int line_length
= (panel_info
.vl_col
* NBITS (panel_info
.vl_bpix
)) / 8;
286 size
= line_length
* panel_info
.vl_row
;
291 void lcd_ctrl_init (void *lcdbase
)
293 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
294 volatile lcd823_t
*lcdp
= &immr
->im_lcd
;
299 /* Initialize the LCD control register according to the LCD
300 * parameters defined. We do everything here but enable
304 #ifdef CONFIG_RPXLITE
305 /* This is special for RPXlite_DW Software Development Platform **[Sam]** */
306 panel_info
.vl_dp
= CONFIG_SYS_LOW
;
309 lccrtmp
= LCDBIT (LCCR_BNUM_BIT
,
310 (((panel_info
.vl_row
* panel_info
.vl_col
) * (1 << LCD_BPP
)) / 128));
312 lccrtmp
|= LCDBIT (LCCR_CLKP_BIT
, panel_info
.vl_clkp
) |
313 LCDBIT (LCCR_OEP_BIT
, panel_info
.vl_oep
) |
314 LCDBIT (LCCR_HSP_BIT
, panel_info
.vl_hsp
) |
315 LCDBIT (LCCR_VSP_BIT
, panel_info
.vl_vsp
) |
316 LCDBIT (LCCR_DP_BIT
, panel_info
.vl_dp
) |
317 LCDBIT (LCCR_BPIX_BIT
, panel_info
.vl_bpix
) |
318 LCDBIT (LCCR_LBW_BIT
, panel_info
.vl_lbw
) |
319 LCDBIT (LCCR_SPLT_BIT
, panel_info
.vl_splt
) |
320 LCDBIT (LCCR_CLOR_BIT
, panel_info
.vl_clor
) |
321 LCDBIT (LCCR_TFT_BIT
, panel_info
.vl_tft
);
324 lccrtmp
|= ((SIU_LEVEL5
/ 2) << 12);
325 lccrtmp
|= LCCR_EIEN
;
328 lcdp
->lcd_lccr
= lccrtmp
;
329 lcdp
->lcd_lcsr
= 0xFF; /* Clear pending interrupts */
331 /* Initialize LCD controller bus priorities.
334 immr
->im_siu_conf
.sc_sdcr
= (immr
->im_siu_conf
.sc_sdcr
& ~0x0f) | 1; /* RAID = 01, LAID = 00 */
336 immr
->im_siu_conf
.sc_sdcr
&= ~0x0f; /* RAID = LAID = 0 */
338 /* set SHFT/CLOCK division factor 4
339 * This needs to be set based upon display type and processor
340 * speed. The TFT displays run about 20 to 30 MHz.
341 * I was running 64 MHz processor speed.
342 * The value for this divider must be chosen so the result is
343 * an integer of the processor speed (i.e., divide by 3 with
344 * 64 MHz would be bad).
346 immr
->im_clkrst
.car_sccr
&= ~0x1F;
347 immr
->im_clkrst
.car_sccr
|= LCD_DF
; /* was 8 */
349 #endif /* CONFIG_RBC823 */
351 #if defined(CONFIG_RBC823)
352 /* Enable LCD on port D.
354 immr
->im_ioport
.iop_pddat
&= 0x0300;
355 immr
->im_ioport
.iop_pdpar
|= 0x1CFF;
356 immr
->im_ioport
.iop_pddir
|= 0x1CFF;
358 /* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
360 immr
->im_cpm
.cp_pbdat
&= ~0x00005001;
361 immr
->im_cpm
.cp_pbpar
&= ~0x00005001;
362 immr
->im_cpm
.cp_pbdir
|= 0x00005001;
363 #elif !defined(CONFIG_EDT32F10)
364 /* Enable LCD on port D.
366 immr
->im_ioport
.iop_pdpar
|= 0x1FFF;
367 immr
->im_ioport
.iop_pddir
|= 0x1FFF;
369 /* Enable LCD_A/B/C on port B.
371 immr
->im_cpm
.cp_pbpar
|= 0x00005001;
372 immr
->im_cpm
.cp_pbdir
|= 0x00005001;
374 /* Enable LCD on port D.
376 immr
->im_ioport
.iop_pdpar
|= 0x1DFF;
377 immr
->im_ioport
.iop_pdpar
&= ~0x0200;
378 immr
->im_ioport
.iop_pddir
|= 0x1FFF;
379 immr
->im_ioport
.iop_pddat
|= 0x0200;
382 /* Load the physical address of the linear frame buffer
383 * into the LCD controller.
384 * BIG NOTE: This has to be modified to load A and B depending
385 * upon the split mode of the LCD.
387 lcdp
->lcd_lcfaa
= (ulong
)lcdbase
;
388 lcdp
->lcd_lcfba
= (ulong
)lcdbase
;
390 /* MORE HACKS...This must be updated according to 823 manual
391 * for different panels.
392 * Udi Finkelstein - done - see below:
393 * Note: You better not try unsupported combinations such as
394 * 4-bit wide passive dual scan LCD at 4/8 Bit color.
398 (panel_info
.vl_tft
? 8 :
399 (((2 - panel_info
.vl_lbw
) << /* 4 bit=2, 8-bit = 1 */
400 /* use << to mult by: single scan = 1, dual scan = 2 */
401 panel_info
.vl_splt
) *
402 (panel_info
.vl_bpix
| 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
404 lcdp
->lcd_lchcr
= LCHCR_BO
|
405 LCDBIT (LCHCR_AT_BIT
, 4) |
406 LCDBIT (LCHCR_HPC_BIT
, lchcr_hpc_tmp
) |
409 lcdp
->lcd_lcvcr
= LCDBIT (LCVCR_VPW_BIT
, panel_info
.vl_vpw
) |
410 LCDBIT (LCVCR_LCD_AC_BIT
, panel_info
.vl_lcdac
) |
411 LCDBIT (LCVCR_VPC_BIT
, panel_info
.vl_row
) |
416 /*----------------------------------------------------------------------*/
418 #ifdef NOT_USED_SO_FAR
420 lcd_getcolreg (ushort regno
, ushort
*red
, ushort
*green
, ushort
*blue
)
422 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
423 volatile cpm8xx_t
*cp
= &(immr
->im_cpm
);
424 unsigned short colreg
, *cmap_ptr
;
426 cmap_ptr
= (unsigned short *)&cp
->lcd_cmap
[regno
* 2];
429 #ifdef CONFIG_SYS_INVERT_COLORS
433 *red
= (colreg
>> 8) & 0x0F;
434 *green
= (colreg
>> 4) & 0x0F;
435 *blue
= colreg
& 0x0F;
437 #endif /* NOT_USED_SO_FAR */
439 /*----------------------------------------------------------------------*/
441 #if LCD_BPP == LCD_COLOR8
443 lcd_setcolreg (ushort regno
, ushort red
, ushort green
, ushort blue
)
445 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
446 volatile cpm8xx_t
*cp
= &(immr
->im_cpm
);
447 unsigned short colreg
, *cmap_ptr
;
449 cmap_ptr
= (unsigned short *)&cp
->lcd_cmap
[regno
* 2];
451 colreg
= ((red
& 0x0F) << 8) |
452 ((green
& 0x0F) << 4) |
454 #ifdef CONFIG_SYS_INVERT_COLORS
459 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
460 regno
, &(cp
->lcd_cmap
[regno
* 2]),
462 cp
->lcd_cmap
[ regno
* 2 ], cp
->lcd_cmap
[(regno
* 2) + 1]);
464 #endif /* LCD_COLOR8 */
466 /*----------------------------------------------------------------------*/
468 #if LCD_BPP == LCD_MONOCHROME
470 void lcd_initcolregs (void)
472 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
473 volatile cpm8xx_t
*cp
= &(immr
->im_cpm
);
476 for (regno
= 0; regno
< 16; regno
++) {
477 cp
->lcd_cmap
[regno
* 2] = 0;
478 cp
->lcd_cmap
[(regno
* 2) + 1] = regno
& 0x0f;
483 /*----------------------------------------------------------------------*/
485 void lcd_enable (void)
487 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
488 volatile lcd823_t
*lcdp
= &immr
->im_lcd
;
490 /* Enable the LCD panel */
491 #ifndef CONFIG_RBC823
492 immr
->im_siu_conf
.sc_sdcr
|= (1 << (31 - 25)); /* LAM = 1 */
494 lcdp
->lcd_lccr
|= LCCR_PON
;
497 /* Turn on display backlight */
498 immr
->im_cpm
.cp_pbpar
|= 0x00008000;
499 immr
->im_cpm
.cp_pbdir
|= 0x00008000;
500 #elif defined(CONFIG_RBC823)
501 /* Turn on display backlight */
502 immr
->im_cpm
.cp_pbdat
|= 0x00004000;
505 #if defined(CONFIG_LWMON)
506 { uchar c
= pic_read (0x60);
507 #if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
508 /* Enable LCD later in sysmon test, only if temperature is OK */
510 c
|= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */
514 #endif /* CONFIG_LWMON */
516 #if defined(CONFIG_R360MPI)
518 extern void r360_i2c_lcd_write (uchar data0
, uchar data1
);
519 unsigned long bgi
, ctr
;
522 if ((p
= getenv("lcdbgi")) != NULL
) {
523 bgi
= simple_strtoul (p
, 0, 10) & 0xFFF;
528 if ((p
= getenv("lcdctr")) != NULL
) {
529 ctr
= simple_strtoul (p
, 0, 10) & 0xFFF;
534 r360_i2c_lcd_write(0x10, 0x01);
535 r360_i2c_lcd_write(0x20, 0x01);
536 r360_i2c_lcd_write(0x30 | ((bgi
>>8) & 0xF), bgi
& 0xFF);
537 r360_i2c_lcd_write(0x40 | ((ctr
>>8) & 0xF), ctr
& 0xFF);
539 #endif /* CONFIG_R360MPI */
541 udelay(200000); /* wait 200ms */
542 /* Turn VEE_ON first */
543 immr
->im_cpm
.cp_pbdat
|= 0x00000001;
544 udelay(200000); /* wait 200ms */
545 /* Now turn on LCD_ON */
546 immr
->im_cpm
.cp_pbdat
|= 0x00001000;
548 #ifdef CONFIG_RRVISION
549 debug ("PC4->Output(1): enable LVDS\n");
550 debug ("PC5->Output(0): disable PAL clock\n");
551 immr
->im_ioport
.iop_pddir
|= 0x1000;
552 immr
->im_ioport
.iop_pcpar
&= ~(0x0C00);
553 immr
->im_ioport
.iop_pcdir
|= 0x0C00 ;
554 immr
->im_ioport
.iop_pcdat
|= 0x0800 ;
555 immr
->im_ioport
.iop_pcdat
&= ~(0x0400);
556 debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
557 immr
->im_ioport
.iop_pdpar
,
558 immr
->im_ioport
.iop_pddir
,
559 immr
->im_ioport
.iop_pddat
);
560 debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
561 immr
->im_ioport
.iop_pcpar
,
562 immr
->im_ioport
.iop_pcdir
,
563 immr
->im_ioport
.iop_pcdat
);
567 /*----------------------------------------------------------------------*/
569 #if defined (CONFIG_RBC823)
570 void lcd_disable (void)
572 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
573 volatile lcd823_t
*lcdp
= &immr
->im_lcd
;
575 #if defined(CONFIG_LWMON)
576 { uchar c
= pic_read (0x60);
577 c
&= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */
580 #elif defined(CONFIG_R360MPI)
582 extern void r360_i2c_lcd_write (uchar data0
, uchar data1
);
584 r360_i2c_lcd_write(0x10, 0x00);
585 r360_i2c_lcd_write(0x20, 0x00);
586 r360_i2c_lcd_write(0x30, 0x00);
587 r360_i2c_lcd_write(0x40, 0x00);
589 #endif /* CONFIG_LWMON */
590 /* Disable the LCD panel */
591 lcdp
->lcd_lccr
&= ~LCCR_PON
;
593 /* Turn off display backlight, VEE and LCD_ON */
594 immr
->im_cpm
.cp_pbdat
&= ~0x00005001;
596 immr
->im_siu_conf
.sc_sdcr
&= ~(1 << (31 - 25)); /* LAM = 0 */
597 #endif /* CONFIG_RBC823 */
599 #endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */
602 /************************************************************************/
604 #endif /* CONFIG_LCD */