drivers/video/mpc8xx_lcd.c

   1 /*
   2  * (C) Copyright 2001-2002
   3  * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************/
  25 /* ** HEADER FILES                                                      */
  26 /************************************************************************/
  27
  28 /* #define DEBUG */
  29
  30 #include <config.h>
  31 #include <common.h>
  32 #include <command.h>
  33 #include <watchdog.h>
  34 #include <version.h>
  35 #include <stdarg.h>
  36 #include <lcdvideo.h>
  37 #include <linux/types.h>
  38 #include <stdio_dev.h>
  39 #if defined(CONFIG_POST)
  40 #include <post.h>
  41 #endif
  42 #include <lcd.h>
  43
  44 #ifdef CONFIG_LCD
  45
  46 /************************************************************************/
  47 /* ** CONFIG STUFF -- should be moved to board config file              */
  48 /************************************************************************/
  49 #ifndef CONFIG_LCD_INFO
  50 #define CONFIG_LCD_INFO         /* Display Logo, (C) and system info    */
  51 #endif
  52
  53 #if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
  54 #undef CONFIG_LCD_LOGO
  55 #undef CONFIG_LCD_INFO
  56 #endif
  57
  58 /*----------------------------------------------------------------------*/
  59 #ifdef CONFIG_KYOCERA_KCS057QV1AJ
  60 /*
  61  *  Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
  62  */
  63 #define LCD_BPP LCD_COLOR4
  64
  65 vidinfo_t panel_info = {
  66     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
  67     LCD_BPP, 1, 0, 1, 0,  5, 0, 0, 0
  68                 /* wbl, vpw, lcdac, wbf */
  69 };
  70 #endif /* CONFIG_KYOCERA_KCS057QV1AJ */
  71 /*----------------------------------------------------------------------*/
  72
  73 /*----------------------------------------------------------------------*/
  74 #ifdef CONFIG_HITACHI_SP19X001_Z1A
  75 /*
  76  *  Hitachi SP19X001-. Active, color, single scan.
  77  */
  78 vidinfo_t panel_info = {
  79     640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
  80     LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
  81                 /* wbl, vpw, lcdac, wbf */
  82 };
  83 #endif /* CONFIG_HITACHI_SP19X001_Z1A */
  84 /*----------------------------------------------------------------------*/
  85
  86 /*----------------------------------------------------------------------*/
  87 #ifdef CONFIG_NEC_NL6448AC33
  88 /*
  89  *  NEC NL6448AC33-18. Active, color, single scan.
  90  */
  91 vidinfo_t panel_info = {
  92     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
  93     3, 0, 0, 1, 1, 144, 2, 0, 33
  94                 /* wbl, vpw, lcdac, wbf */
  95 };
  96 #endif /* CONFIG_NEC_NL6448AC33 */
  97 /*----------------------------------------------------------------------*/
  98
  99 #ifdef CONFIG_NEC_NL6448BC20
 100 /*
 101  *  NEC NL6448BC20-08.  6.5", 640x480. Active, color, single scan.
 102  */
 103 vidinfo_t panel_info = {
 104     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 105     3, 0, 0, 1, 1, 144, 2, 0, 33
 106                 /* wbl, vpw, lcdac, wbf */
 107 };
 108 #endif /* CONFIG_NEC_NL6448BC20 */
 109 /*----------------------------------------------------------------------*/
 110
 111 #ifdef CONFIG_NEC_NL6448BC33_54
 112 /*
 113  *  NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
 114  */
 115 vidinfo_t panel_info = {
 116     640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 117     3, 0, 0, 1, 1, 144, 2, 0, 33
 118                 /* wbl, vpw, lcdac, wbf */
 119 };
 120 #endif /* CONFIG_NEC_NL6448BC33_54 */
 121 /*----------------------------------------------------------------------*/
 122
 123 #ifdef CONFIG_SHARP_LQ104V7DS01
 124 /*
 125  *  SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
 126  */
 127 vidinfo_t panel_info = {
 128     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
 129     3, 0, 0, 1, 1, 25, 1, 0, 33
 130                 /* wbl, vpw, lcdac, wbf */
 131 };
 132 #endif /* CONFIG_SHARP_LQ104V7DS01 */
 133 /*----------------------------------------------------------------------*/
 134
 135 #ifdef CONFIG_SHARP_16x9
 136 /*
 137  * Sharp 320x240. Active, color, single scan.  It isn't 16x9, and I am
 138  * not sure what it is.......
 139  */
 140 vidinfo_t panel_info = {
 141     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
 142     3, 0, 0, 1, 1, 15, 4, 0, 3
 143 };
 144 #endif /* CONFIG_SHARP_16x9 */
 145 /*----------------------------------------------------------------------*/
 146
 147 #ifdef CONFIG_SHARP_LQ057Q3DC02
 148 /*
 149  * Sharp LQ057Q3DC02 display. Active, color, single scan.
 150  */
 151 #undef LCD_DF
 152 #define LCD_DF 12
 153
 154 vidinfo_t panel_info = {
 155     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 156     3, 0, 0, 1, 1, 15, 4, 0, 3
 157                 /* wbl, vpw, lcdac, wbf */
 158 };
 159 #define CONFIG_LCD_INFO_BELOW_LOGO
 160 #endif /* CONFIG_SHARP_LQ057Q3DC02 */
 161 /*----------------------------------------------------------------------*/
 162
 163 #ifdef CONFIG_SHARP_LQ64D341
 164 /*
 165  * Sharp LQ64D341 display, 640x480. Active, color, single scan.
 166  */
 167 vidinfo_t panel_info = {
 168     640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 169     3, 0, 0, 1, 1, 128, 16, 0, 32
 170                 /* wbl, vpw, lcdac, wbf */
 171 };
 172 #endif /* CONFIG_SHARP_LQ64D341 */
 173
 174 #ifdef CONFIG_SHARP_LQ065T9DR51U
 175 /*
 176  * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
 177  */
 178 vidinfo_t panel_info = {
 179     400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
 180     3, 0, 0, 1, 1, 248, 4, 0, 35
 181                 /* wbl, vpw, lcdac, wbf */
 182 };
 183 #define CONFIG_LCD_INFO_BELOW_LOGO
 184 #endif /* CONFIG_SHARP_LQ065T9DR51U */
 185
 186 #ifdef CONFIG_SHARP_LQ084V1DG21
 187 /*
 188  * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
 189  */
 190 vidinfo_t panel_info = {
 191     640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
 192     3, 0, 0, 1, 1, 160, 3, 0, 48
 193                 /* wbl, vpw, lcdac, wbf */
 194 };
 195 #endif /* CONFIG_SHARP_LQ084V1DG21 */
 196
 197 /*----------------------------------------------------------------------*/
 198
 199 #ifdef CONFIG_HLD1045
 200 /*
 201  * HLD1045 display, 640x480. Active, color, single scan.
 202  */
 203 vidinfo_t panel_info = {
 204     640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 205     3, 0, 0, 1, 1, 160, 3, 0, 48
 206                 /* wbl, vpw, lcdac, wbf */
 207 };
 208 #endif /* CONFIG_HLD1045 */
 209 /*----------------------------------------------------------------------*/
 210
 211 #ifdef CONFIG_PRIMEVIEW_V16C6448AC
 212 /*
 213  * Prime View V16C6448AC
 214  */
 215 vidinfo_t panel_info = {
 216     640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 217     3, 0, 0, 1, 1, 144, 2, 0, 35
 218                 /* wbl, vpw, lcdac, wbf */
 219 };
 220 #endif /* CONFIG_PRIMEVIEW_V16C6448AC */
 221
 222 /*----------------------------------------------------------------------*/
 223
 224 #ifdef CONFIG_OPTREX_BW
 225 /*
 226  * Optrex   CBL50840-2 NF-FW 99 22 M5
 227  * or
 228  * Hitachi  LMG6912RPFC-00T
 229  * or
 230  * Hitachi  SP14Q002
 231  *
 232  * 320x240. Black & white.
 233  */
 234 #define OPTREX_BPP      0       /* 0 - monochrome,     1 bpp */
 235                                 /* 1 -  4 grey levels, 2 bpp */
 236                                 /* 2 - 16 grey levels, 4 bpp */
 237 vidinfo_t panel_info = {
 238     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
 239     OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
 240 };
 241 #endif /* CONFIG_OPTREX_BW */
 242
 243 /*-----------------------------------------------------------------*/
 244 #ifdef CONFIG_EDT32F10
 245 /*
 246  * Emerging Display Technologies 320x240. Passive, monochrome, single scan.
 247  */
 248 #define LCD_BPP         LCD_MONOCHROME
 249 #define LCD_DF          10
 250
 251 vidinfo_t panel_info = {
 252     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
 253     LCD_BPP,  0, 0, 0, 0, 33, 0, 0, 0
 254 };
 255 #endif
 256
 257 /************************************************************************/
 258 /* ----------------- chipset specific functions ----------------------- */
 259 /************************************************************************/
 260
 261 /*
 262  * Calculate fb size for VIDEOLFB_ATAG.
 263  */
 264 ulong calc_fbsize (void)
 265 {
 266         ulong size;
 267         int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 268
 269         size = line_length * panel_info.vl_row;
 270
 271         return size;
 272 }
 273
 274 void lcd_ctrl_init (void *lcdbase)
 275 {
 276         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 277         volatile lcd823_t *lcdp = &immr->im_lcd;
 278
 279         uint lccrtmp;
 280         uint lchcr_hpc_tmp;
 281
 282         /* Initialize the LCD control register according to the LCD
 283          * parameters defined.  We do everything here but enable
 284          * the controller.
 285          */
 286
 287 #ifdef CONFIG_RPXLITE
 288         /* This is special for RPXlite_DW Software Development Platform **[Sam]** */
 289         panel_info.vl_dp = CONFIG_SYS_LOW;
 290 #endif
 291
 292         lccrtmp  = LCDBIT (LCCR_BNUM_BIT,
 293                    (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
 294
 295         lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp)   |
 296                    LCDBIT (LCCR_OEP_BIT,  panel_info.vl_oep)    |
 297                    LCDBIT (LCCR_HSP_BIT,  panel_info.vl_hsp)    |
 298                    LCDBIT (LCCR_VSP_BIT,  panel_info.vl_vsp)    |
 299                    LCDBIT (LCCR_DP_BIT,   panel_info.vl_dp)     |
 300                    LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix)   |
 301                    LCDBIT (LCCR_LBW_BIT,  panel_info.vl_lbw)    |
 302                    LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt)   |
 303                    LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor)   |
 304                    LCDBIT (LCCR_TFT_BIT,  panel_info.vl_tft);
 305
 306 #if 0
 307         lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
 308         lccrtmp |= LCCR_EIEN;
 309 #endif
 310
 311         lcdp->lcd_lccr = lccrtmp;
 312         lcdp->lcd_lcsr = 0xFF;          /* Clear pending interrupts */
 313
 314         /* Initialize LCD controller bus priorities.
 315          */
 316 #ifdef CONFIG_RBC823
 317         immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1;    /* RAID = 01, LAID = 00 */
 318 #else
 319         immr->im_siu_conf.sc_sdcr &= ~0x0f;     /* RAID = LAID = 0 */
 320
 321         /* set SHFT/CLOCK division factor 4
 322          * This needs to be set based upon display type and processor
 323          * speed.  The TFT displays run about 20 to 30 MHz.
 324          * I was running 64 MHz processor speed.
 325          * The value for this divider must be chosen so the result is
 326          * an integer of the processor speed (i.e., divide by 3 with
 327          * 64 MHz would be bad).
 328          */
 329         immr->im_clkrst.car_sccr &= ~0x1F;
 330         immr->im_clkrst.car_sccr |= LCD_DF;     /* was 8 */
 331
 332 #endif /* CONFIG_RBC823 */
 333
 334 #if defined(CONFIG_RBC823)
 335         /* Enable LCD on port D.
 336          */
 337         immr->im_ioport.iop_pddat &= 0x0300;
 338         immr->im_ioport.iop_pdpar |= 0x1CFF;
 339         immr->im_ioport.iop_pddir |= 0x1CFF;
 340
 341         /* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
 342          */
 343         immr->im_cpm.cp_pbdat &= ~0x00005001;
 344         immr->im_cpm.cp_pbpar &= ~0x00005001;
 345         immr->im_cpm.cp_pbdir |=  0x00005001;
 346 #elif !defined(CONFIG_EDT32F10)
 347         /* Enable LCD on port D.
 348          */
 349         immr->im_ioport.iop_pdpar |= 0x1FFF;
 350         immr->im_ioport.iop_pddir |= 0x1FFF;
 351
 352         /* Enable LCD_A/B/C on port B.
 353          */
 354         immr->im_cpm.cp_pbpar |= 0x00005001;
 355         immr->im_cpm.cp_pbdir |= 0x00005001;
 356 #else
 357         /* Enable LCD on port D.
 358          */
 359         immr->im_ioport.iop_pdpar |= 0x1DFF;
 360         immr->im_ioport.iop_pdpar &= ~0x0200;
 361         immr->im_ioport.iop_pddir |= 0x1FFF;
 362         immr->im_ioport.iop_pddat |= 0x0200;
 363 #endif
 364
 365         /* Load the physical address of the linear frame buffer
 366          * into the LCD controller.
 367          * BIG NOTE:  This has to be modified to load A and B depending
 368          * upon the split mode of the LCD.
 369          */
 370         lcdp->lcd_lcfaa = (ulong)lcdbase;
 371         lcdp->lcd_lcfba = (ulong)lcdbase;
 372
 373         /* MORE HACKS...This must be updated according to 823 manual
 374          * for different panels.
 375          * Udi Finkelstein - done - see below:
 376          * Note: You better not try unsupported combinations such as
 377          * 4-bit wide passive dual scan LCD at 4/8 Bit color.
 378          */
 379         lchcr_hpc_tmp =
 380                 (panel_info.vl_col *
 381                  (panel_info.vl_tft ? 8 :
 382                         (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
 383                          /* use << to mult by: single scan = 1, dual scan = 2 */
 384                           panel_info.vl_splt) *
 385                          (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
 386
 387         lcdp->lcd_lchcr = LCHCR_BO |
 388                           LCDBIT (LCHCR_AT_BIT, 4) |
 389                           LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
 390                           panel_info.vl_wbl;
 391
 392         lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
 393                           LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
 394                           LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
 395                           panel_info.vl_wbf;
 396
 397 }
 398
 399 /*----------------------------------------------------------------------*/
 400
 401 #if LCD_BPP == LCD_COLOR8
 402 void
 403 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 404 {
 405         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 406         volatile cpm8xx_t *cp = &(immr->im_cpm);
 407         unsigned short colreg, *cmap_ptr;
 408
 409         cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
 410
 411         colreg = ((red   & 0x0F) << 8) |
 412                  ((green & 0x0F) << 4) |
 413                   (blue  & 0x0F) ;
 414 #ifdef  CONFIG_SYS_INVERT_COLORS
 415         colreg ^= 0x0FFF;
 416 #endif
 417         *cmap_ptr = colreg;
 418
 419         debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
 420                 regno, &(cp->lcd_cmap[regno * 2]),
 421                 red, green, blue,
 422                 cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
 423 }
 424 #endif  /* LCD_COLOR8 */
 425
 426 /*----------------------------------------------------------------------*/
 427
 428 #if LCD_BPP == LCD_MONOCHROME
 429 static
 430 void lcd_initcolregs (void)
 431 {
 432         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 433         volatile cpm8xx_t *cp = &(immr->im_cpm);
 434         ushort regno;
 435
 436         for (regno = 0; regno < 16; regno++) {
 437                 cp->lcd_cmap[regno * 2] = 0;
 438                 cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
 439         }
 440 }
 441 #endif
 442
 443 /*----------------------------------------------------------------------*/
 444
 445 void lcd_enable (void)
 446 {
 447         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 448         volatile lcd823_t *lcdp = &immr->im_lcd;
 449
 450         /* Enable the LCD panel */
 451 #ifndef CONFIG_RBC823
 452         immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25));          /* LAM = 1 */
 453 #endif
 454         lcdp->lcd_lccr |= LCCR_PON;
 455
 456 #ifdef CONFIG_V37
 457         /* Turn on display backlight */
 458         immr->im_cpm.cp_pbpar |= 0x00008000;
 459         immr->im_cpm.cp_pbdir |= 0x00008000;
 460 #elif defined(CONFIG_RBC823)
 461         /* Turn on display backlight */
 462         immr->im_cpm.cp_pbdat |= 0x00004000;
 463 #endif
 464
 465 #if defined(CONFIG_LWMON)
 466     {   uchar c = pic_read (0x60);
 467 #if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
 468         /* Enable LCD later in sysmon test, only if temperature is OK */
 469 #else
 470         c |= 0x07;      /* Power on CCFL, Enable CCFL, Chip Enable LCD */
 471 #endif
 472         pic_write (0x60, c);
 473     }
 474 #endif /* CONFIG_LWMON */
 475
 476 #if defined(CONFIG_R360MPI)
 477     {
 478         extern void r360_i2c_lcd_write (uchar data0, uchar data1);
 479         unsigned long bgi, ctr;
 480         char *p;
 481
 482         if ((p = getenv("lcdbgi")) != NULL) {
 483                 bgi = simple_strtoul (p, 0, 10) & 0xFFF;
 484         } else {
 485                 bgi = 0xFFF;
 486         }
 487
 488         if ((p = getenv("lcdctr")) != NULL) {
 489                 ctr = simple_strtoul (p, 0, 10) & 0xFFF;
 490         } else {
 491                 ctr=0x7FF;
 492         }
 493
 494         r360_i2c_lcd_write(0x10, 0x01);
 495         r360_i2c_lcd_write(0x20, 0x01);
 496         r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
 497         r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
 498     }
 499 #endif /* CONFIG_R360MPI */
 500 #ifdef CONFIG_RBC823
 501         udelay(200000); /* wait 200ms */
 502         /* Turn VEE_ON first */
 503         immr->im_cpm.cp_pbdat |= 0x00000001;
 504         udelay(200000); /* wait 200ms */
 505         /* Now turn on LCD_ON */
 506         immr->im_cpm.cp_pbdat |= 0x00001000;
 507 #endif
 508 #ifdef CONFIG_RRVISION
 509         debug ("PC4->Output(1): enable LVDS\n");
 510         debug ("PC5->Output(0): disable PAL clock\n");
 511         immr->im_ioport.iop_pddir |=  0x1000;
 512         immr->im_ioport.iop_pcpar &= ~(0x0C00);
 513         immr->im_ioport.iop_pcdir |=   0x0C00 ;
 514         immr->im_ioport.iop_pcdat |=   0x0800 ;
 515         immr->im_ioport.iop_pcdat &= ~(0x0400);
 516         debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
 517                immr->im_ioport.iop_pdpar,
 518                immr->im_ioport.iop_pddir,
 519                immr->im_ioport.iop_pddat);
 520         debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
 521                immr->im_ioport.iop_pcpar,
 522                immr->im_ioport.iop_pcdir,
 523                immr->im_ioport.iop_pcdat);
 524 #endif
 525 }
 526
 527 /*----------------------------------------------------------------------*/
 528
 529 #if defined (CONFIG_RBC823)
 530 void lcd_disable (void)
 531 {
 532         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 533         volatile lcd823_t *lcdp = &immr->im_lcd;
 534
 535 #if defined(CONFIG_LWMON)
 536     {   uchar c = pic_read (0x60);
 537         c &= ~0x07;     /* Power off CCFL, Disable CCFL, Chip Disable LCD */
 538         pic_write (0x60, c);
 539     }
 540 #elif defined(CONFIG_R360MPI)
 541     {
 542         extern void r360_i2c_lcd_write (uchar data0, uchar data1);
 543
 544         r360_i2c_lcd_write(0x10, 0x00);
 545         r360_i2c_lcd_write(0x20, 0x00);
 546         r360_i2c_lcd_write(0x30, 0x00);
 547         r360_i2c_lcd_write(0x40, 0x00);
 548     }
 549 #endif /* CONFIG_LWMON */
 550         /* Disable the LCD panel */
 551         lcdp->lcd_lccr &= ~LCCR_PON;
 552 #ifdef CONFIG_RBC823
 553         /* Turn off display backlight, VEE and LCD_ON */
 554         immr->im_cpm.cp_pbdat &= ~0x00005001;
 555 #else
 556         immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */
 557 #endif /* CONFIG_RBC823 */
 558 }
 559 #endif  /* NOT_USED_SO_FAR || CONFIG_RBC823 */
 560
 561
 562 /************************************************************************/
 563
 564 #endif /* CONFIG_LCD */