drivers/video/mpc8xx_lcd.c

   1 /*
   2  * (C) Copyright 2001-2002
   3  * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /************************************************************************/
   9 /* ** HEADER FILES                                                      */
  10 /************************************************************************/
  11
  12 /* #define DEBUG */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <command.h>
  17 #include <watchdog.h>
  18 #include <version.h>
  19 #include <stdarg.h>
  20 #include <lcdvideo.h>
  21 #include <linux/types.h>
  22 #include <stdio_dev.h>
  23 #if defined(CONFIG_POST)
  24 #include <post.h>
  25 #endif
  26 #include <lcd.h>
  27
  28 #ifdef CONFIG_LCD
  29
  30 /************************************************************************/
  31 /* ** CONFIG STUFF -- should be moved to board config file              */
  32 /************************************************************************/
  33 #ifndef CONFIG_LCD_INFO
  34 #define CONFIG_LCD_INFO         /* Display Logo, (C) and system info    */
  35 #endif
  36
  37 #if defined(CONFIG_EDT32F10)
  38 #undef CONFIG_LCD_LOGO
  39 #undef CONFIG_LCD_INFO
  40 #endif
  41
  42 /*----------------------------------------------------------------------*/
  43 #ifdef CONFIG_KYOCERA_KCS057QV1AJ
  44 /*
  45  *  Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
  46  */
  47 #define LCD_BPP LCD_COLOR4
  48
  49 vidinfo_t panel_info = {
  50     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
  51     LCD_BPP, 1, 0, 1, 0,  5, 0, 0, 0
  52                 /* wbl, vpw, lcdac, wbf */
  53 };
  54 #endif /* CONFIG_KYOCERA_KCS057QV1AJ */
  55 /*----------------------------------------------------------------------*/
  56
  57 /*----------------------------------------------------------------------*/
  58 #ifdef CONFIG_HITACHI_SP19X001_Z1A
  59 /*
  60  *  Hitachi SP19X001-. Active, color, single scan.
  61  */
  62 vidinfo_t panel_info = {
  63     640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
  64     LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
  65                 /* wbl, vpw, lcdac, wbf */
  66 };
  67 #endif /* CONFIG_HITACHI_SP19X001_Z1A */
  68 /*----------------------------------------------------------------------*/
  69
  70 /*----------------------------------------------------------------------*/
  71 #ifdef CONFIG_NEC_NL6448AC33
  72 /*
  73  *  NEC NL6448AC33-18. Active, color, single scan.
  74  */
  75 vidinfo_t panel_info = {
  76     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
  77     3, 0, 0, 1, 1, 144, 2, 0, 33
  78                 /* wbl, vpw, lcdac, wbf */
  79 };
  80 #endif /* CONFIG_NEC_NL6448AC33 */
  81 /*----------------------------------------------------------------------*/
  82
  83 #ifdef CONFIG_NEC_NL6448BC20
  84 /*
  85  *  NEC NL6448BC20-08.  6.5", 640x480. Active, color, single scan.
  86  */
  87 vidinfo_t panel_info = {
  88     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
  89     3, 0, 0, 1, 1, 144, 2, 0, 33
  90                 /* wbl, vpw, lcdac, wbf */
  91 };
  92 #endif /* CONFIG_NEC_NL6448BC20 */
  93 /*----------------------------------------------------------------------*/
  94
  95 #ifdef CONFIG_NEC_NL6448BC33_54
  96 /*
  97  *  NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
  98  */
  99 vidinfo_t panel_info = {
 100     640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 101     3, 0, 0, 1, 1, 144, 2, 0, 33
 102                 /* wbl, vpw, lcdac, wbf */
 103 };
 104 #endif /* CONFIG_NEC_NL6448BC33_54 */
 105 /*----------------------------------------------------------------------*/
 106
 107 #ifdef CONFIG_SHARP_LQ104V7DS01
 108 /*
 109  *  SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
 110  */
 111 vidinfo_t panel_info = {
 112     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
 113     3, 0, 0, 1, 1, 25, 1, 0, 33
 114                 /* wbl, vpw, lcdac, wbf */
 115 };
 116 #endif /* CONFIG_SHARP_LQ104V7DS01 */
 117 /*----------------------------------------------------------------------*/
 118
 119 #ifdef CONFIG_SHARP_16x9
 120 /*
 121  * Sharp 320x240. Active, color, single scan.  It isn't 16x9, and I am
 122  * not sure what it is.......
 123  */
 124 vidinfo_t panel_info = {
 125     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
 126     3, 0, 0, 1, 1, 15, 4, 0, 3
 127 };
 128 #endif /* CONFIG_SHARP_16x9 */
 129 /*----------------------------------------------------------------------*/
 130
 131 #ifdef CONFIG_SHARP_LQ057Q3DC02
 132 /*
 133  * Sharp LQ057Q3DC02 display. Active, color, single scan.
 134  */
 135 #undef LCD_DF
 136 #define LCD_DF 12
 137
 138 vidinfo_t panel_info = {
 139     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 140     3, 0, 0, 1, 1, 15, 4, 0, 3
 141                 /* wbl, vpw, lcdac, wbf */
 142 };
 143 #define CONFIG_LCD_INFO_BELOW_LOGO
 144 #endif /* CONFIG_SHARP_LQ057Q3DC02 */
 145 /*----------------------------------------------------------------------*/
 146
 147 #ifdef CONFIG_SHARP_LQ64D341
 148 /*
 149  * Sharp LQ64D341 display, 640x480. Active, color, single scan.
 150  */
 151 vidinfo_t panel_info = {
 152     640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 153     3, 0, 0, 1, 1, 128, 16, 0, 32
 154                 /* wbl, vpw, lcdac, wbf */
 155 };
 156 #endif /* CONFIG_SHARP_LQ64D341 */
 157
 158 #ifdef CONFIG_SHARP_LQ065T9DR51U
 159 /*
 160  * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
 161  */
 162 vidinfo_t panel_info = {
 163     400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
 164     3, 0, 0, 1, 1, 248, 4, 0, 35
 165                 /* wbl, vpw, lcdac, wbf */
 166 };
 167 #define CONFIG_LCD_INFO_BELOW_LOGO
 168 #endif /* CONFIG_SHARP_LQ065T9DR51U */
 169
 170 #ifdef CONFIG_SHARP_LQ084V1DG21
 171 /*
 172  * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
 173  */
 174 vidinfo_t panel_info = {
 175     640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
 176     3, 0, 0, 1, 1, 160, 3, 0, 48
 177                 /* wbl, vpw, lcdac, wbf */
 178 };
 179 #endif /* CONFIG_SHARP_LQ084V1DG21 */
 180
 181 /*----------------------------------------------------------------------*/
 182
 183 #ifdef CONFIG_HLD1045
 184 /*
 185  * HLD1045 display, 640x480. Active, color, single scan.
 186  */
 187 vidinfo_t panel_info = {
 188     640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 189     3, 0, 0, 1, 1, 160, 3, 0, 48
 190                 /* wbl, vpw, lcdac, wbf */
 191 };
 192 #endif /* CONFIG_HLD1045 */
 193 /*----------------------------------------------------------------------*/
 194
 195 #ifdef CONFIG_PRIMEVIEW_V16C6448AC
 196 /*
 197  * Prime View V16C6448AC
 198  */
 199 vidinfo_t panel_info = {
 200     640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 201     3, 0, 0, 1, 1, 144, 2, 0, 35
 202                 /* wbl, vpw, lcdac, wbf */
 203 };
 204 #endif /* CONFIG_PRIMEVIEW_V16C6448AC */
 205
 206 /*----------------------------------------------------------------------*/
 207
 208 #ifdef CONFIG_OPTREX_BW
 209 /*
 210  * Optrex   CBL50840-2 NF-FW 99 22 M5
 211  * or
 212  * Hitachi  LMG6912RPFC-00T
 213  * or
 214  * Hitachi  SP14Q002
 215  *
 216  * 320x240. Black & white.
 217  */
 218 #define OPTREX_BPP      0       /* 0 - monochrome,     1 bpp */
 219                                 /* 1 -  4 grey levels, 2 bpp */
 220                                 /* 2 - 16 grey levels, 4 bpp */
 221 vidinfo_t panel_info = {
 222     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
 223     OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
 224 };
 225 #endif /* CONFIG_OPTREX_BW */
 226
 227 /*-----------------------------------------------------------------*/
 228 #ifdef CONFIG_EDT32F10
 229 /*
 230  * Emerging Display Technologies 320x240. Passive, monochrome, single scan.
 231  */
 232 #define LCD_BPP         LCD_MONOCHROME
 233 #define LCD_DF          10
 234
 235 vidinfo_t panel_info = {
 236     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
 237     LCD_BPP,  0, 0, 0, 0, 33, 0, 0, 0
 238 };
 239 #endif
 240
 241 /************************************************************************/
 242 /* ----------------- chipset specific functions ----------------------- */
 243 /************************************************************************/
 244
 245 /*
 246  * Calculate fb size for VIDEOLFB_ATAG.
 247  */
 248 ulong calc_fbsize (void)
 249 {
 250         ulong size;
 251         int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 252
 253         size = line_length * panel_info.vl_row;
 254
 255         return size;
 256 }
 257
 258 void lcd_ctrl_init (void *lcdbase)
 259 {
 260         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 261         volatile lcd823_t *lcdp = &immr->im_lcd;
 262
 263         uint lccrtmp;
 264         uint lchcr_hpc_tmp;
 265
 266         /* Initialize the LCD control register according to the LCD
 267          * parameters defined.  We do everything here but enable
 268          * the controller.
 269          */
 270
 271         lccrtmp  = LCDBIT (LCCR_BNUM_BIT,
 272                    (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
 273
 274         lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp)   |
 275                    LCDBIT (LCCR_OEP_BIT,  panel_info.vl_oep)    |
 276                    LCDBIT (LCCR_HSP_BIT,  panel_info.vl_hsp)    |
 277                    LCDBIT (LCCR_VSP_BIT,  panel_info.vl_vsp)    |
 278                    LCDBIT (LCCR_DP_BIT,   panel_info.vl_dp)     |
 279                    LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix)   |
 280                    LCDBIT (LCCR_LBW_BIT,  panel_info.vl_lbw)    |
 281                    LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt)   |
 282                    LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor)   |
 283                    LCDBIT (LCCR_TFT_BIT,  panel_info.vl_tft);
 284
 285 #if 0
 286         lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
 287         lccrtmp |= LCCR_EIEN;
 288 #endif
 289
 290         lcdp->lcd_lccr = lccrtmp;
 291         lcdp->lcd_lcsr = 0xFF;          /* Clear pending interrupts */
 292
 293         /* Initialize LCD controller bus priorities.
 294          */
 295         immr->im_siu_conf.sc_sdcr &= ~0x0f;     /* RAID = LAID = 0 */
 296
 297         /* set SHFT/CLOCK division factor 4
 298          * This needs to be set based upon display type and processor
 299          * speed.  The TFT displays run about 20 to 30 MHz.
 300          * I was running 64 MHz processor speed.
 301          * The value for this divider must be chosen so the result is
 302          * an integer of the processor speed (i.e., divide by 3 with
 303          * 64 MHz would be bad).
 304          */
 305         immr->im_clkrst.car_sccr &= ~0x1F;
 306         immr->im_clkrst.car_sccr |= LCD_DF;     /* was 8 */
 307
 308 #if !defined(CONFIG_EDT32F10)
 309         /* Enable LCD on port D.
 310          */
 311         immr->im_ioport.iop_pdpar |= 0x1FFF;
 312         immr->im_ioport.iop_pddir |= 0x1FFF;
 313
 314         /* Enable LCD_A/B/C on port B.
 315          */
 316         immr->im_cpm.cp_pbpar |= 0x00005001;
 317         immr->im_cpm.cp_pbdir |= 0x00005001;
 318 #else
 319         /* Enable LCD on port D.
 320          */
 321         immr->im_ioport.iop_pdpar |= 0x1DFF;
 322         immr->im_ioport.iop_pdpar &= ~0x0200;
 323         immr->im_ioport.iop_pddir |= 0x1FFF;
 324         immr->im_ioport.iop_pddat |= 0x0200;
 325 #endif
 326
 327         /* Load the physical address of the linear frame buffer
 328          * into the LCD controller.
 329          * BIG NOTE:  This has to be modified to load A and B depending
 330          * upon the split mode of the LCD.
 331          */
 332         lcdp->lcd_lcfaa = (ulong)lcdbase;
 333         lcdp->lcd_lcfba = (ulong)lcdbase;
 334
 335         /* MORE HACKS...This must be updated according to 823 manual
 336          * for different panels.
 337          * Udi Finkelstein - done - see below:
 338          * Note: You better not try unsupported combinations such as
 339          * 4-bit wide passive dual scan LCD at 4/8 Bit color.
 340          */
 341         lchcr_hpc_tmp =
 342                 (panel_info.vl_col *
 343                  (panel_info.vl_tft ? 8 :
 344                         (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
 345                          /* use << to mult by: single scan = 1, dual scan = 2 */
 346                           panel_info.vl_splt) *
 347                          (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
 348
 349         lcdp->lcd_lchcr = LCHCR_BO |
 350                           LCDBIT (LCHCR_AT_BIT, 4) |
 351                           LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
 352                           panel_info.vl_wbl;
 353
 354         lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
 355                           LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
 356                           LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
 357                           panel_info.vl_wbf;
 358
 359 }
 360
 361 /*----------------------------------------------------------------------*/
 362
 363 #if LCD_BPP == LCD_COLOR8
 364 void
 365 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 366 {
 367         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 368         volatile cpm8xx_t *cp = &(immr->im_cpm);
 369         unsigned short colreg, *cmap_ptr;
 370
 371         cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
 372
 373         colreg = ((red   & 0x0F) << 8) |
 374                  ((green & 0x0F) << 4) |
 375                   (blue  & 0x0F) ;
 376 #ifdef  CONFIG_SYS_INVERT_COLORS
 377         colreg ^= 0x0FFF;
 378 #endif
 379         *cmap_ptr = colreg;
 380
 381         debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
 382                 regno, &(cp->lcd_cmap[regno * 2]),
 383                 red, green, blue,
 384                 cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
 385 }
 386 #endif  /* LCD_COLOR8 */
 387
 388 /*----------------------------------------------------------------------*/
 389
 390 #if LCD_BPP == LCD_MONOCHROME
 391 static
 392 void lcd_initcolregs (void)
 393 {
 394         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 395         volatile cpm8xx_t *cp = &(immr->im_cpm);
 396         ushort regno;
 397
 398         for (regno = 0; regno < 16; regno++) {
 399                 cp->lcd_cmap[regno * 2] = 0;
 400                 cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
 401         }
 402 }
 403 #endif
 404
 405 /*----------------------------------------------------------------------*/
 406
 407 void lcd_enable (void)
 408 {
 409         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 410         volatile lcd823_t *lcdp = &immr->im_lcd;
 411
 412         /* Enable the LCD panel */
 413         immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25));          /* LAM = 1 */
 414         lcdp->lcd_lccr |= LCCR_PON;
 415
 416 #if defined(CONFIG_LWMON)
 417     {   uchar c = pic_read (0x60);
 418 #if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
 419         /* Enable LCD later in sysmon test, only if temperature is OK */
 420 #else
 421         c |= 0x07;      /* Power on CCFL, Enable CCFL, Chip Enable LCD */
 422 #endif
 423         pic_write (0x60, c);
 424     }
 425 #endif /* CONFIG_LWMON */
 426
 427 #if defined(CONFIG_R360MPI)
 428     {
 429         extern void r360_i2c_lcd_write (uchar data0, uchar data1);
 430         unsigned long bgi, ctr;
 431         char *p;
 432
 433         if ((p = getenv("lcdbgi")) != NULL) {
 434                 bgi = simple_strtoul (p, 0, 10) & 0xFFF;
 435         } else {
 436                 bgi = 0xFFF;
 437         }
 438
 439         if ((p = getenv("lcdctr")) != NULL) {
 440                 ctr = simple_strtoul (p, 0, 10) & 0xFFF;
 441         } else {
 442                 ctr=0x7FF;
 443         }
 444
 445         r360_i2c_lcd_write(0x10, 0x01);
 446         r360_i2c_lcd_write(0x20, 0x01);
 447         r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
 448         r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
 449     }
 450 #endif /* CONFIG_R360MPI */
 451 #ifdef CONFIG_RRVISION
 452         debug ("PC4->Output(1): enable LVDS\n");
 453         debug ("PC5->Output(0): disable PAL clock\n");
 454         immr->im_ioport.iop_pddir |=  0x1000;
 455         immr->im_ioport.iop_pcpar &= ~(0x0C00);
 456         immr->im_ioport.iop_pcdir |=   0x0C00 ;
 457         immr->im_ioport.iop_pcdat |=   0x0800 ;
 458         immr->im_ioport.iop_pcdat &= ~(0x0400);
 459         debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
 460                immr->im_ioport.iop_pdpar,
 461                immr->im_ioport.iop_pddir,
 462                immr->im_ioport.iop_pddat);
 463         debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
 464                immr->im_ioport.iop_pcpar,
 465                immr->im_ioport.iop_pcdir,
 466                immr->im_ioport.iop_pcdat);
 467 #endif
 468 }
 469
 470 /************************************************************************/
 471
 472 #endif /* CONFIG_LCD */