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[thirdparty/u-boot.git] / drivers / video / mvebu_lcd.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Video driver for Marvell Armada XP SoC
4 *
5 * Initialization of LCD interface and setup of SPLASH screen image
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <video.h>
11 #include <asm/cache.h>
12 #include <dm/device_compat.h>
13 #include <linux/mbus.h>
14 #include <asm/io.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/soc.h>
17
18 #define MVEBU_LCD_WIN_CONTROL(w) (0xf000 + ((w) << 4))
19 #define MVEBU_LCD_WIN_BASE(w) (0xf004 + ((w) << 4))
20 #define MVEBU_LCD_WIN_REMAP(w) (0xf00c + ((w) << 4))
21
22 #define MVEBU_LCD_CFG_DMA_START_ADDR_0 0x00cc
23 #define MVEBU_LCD_CFG_DMA_START_ADDR_1 0x00dc
24
25 #define MVEBU_LCD_CFG_GRA_START_ADDR0 0x00f4
26 #define MVEBU_LCD_CFG_GRA_START_ADDR1 0x00f8
27 #define MVEBU_LCD_CFG_GRA_PITCH 0x00fc
28 #define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
29 #define MVEBU_LCD_SPU_GRA_HPXL_VLN 0x0104
30 #define MVEBU_LCD_SPU_GZM_HPXL_VLN 0x0108
31 #define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN 0x010c
32 #define MVEBU_LCD_SPU_HWC_HPXL_VLN 0x0110
33 #define MVEBU_LCD_SPUT_V_H_TOTAL 0x0114
34 #define MVEBU_LCD_SPU_V_H_ACTIVE 0x0118
35 #define MVEBU_LCD_SPU_H_PORCH 0x011c
36 #define MVEBU_LCD_SPU_V_PORCH 0x0120
37 #define MVEBU_LCD_SPU_BLANKCOLOR 0x0124
38 #define MVEBU_LCD_SPU_ALPHA_COLOR1 0x0128
39 #define MVEBU_LCD_SPU_ALPHA_COLOR2 0x012c
40 #define MVEBU_LCD_SPU_COLORKEY_Y 0x0130
41 #define MVEBU_LCD_SPU_COLORKEY_U 0x0134
42 #define MVEBU_LCD_SPU_COLORKEY_V 0x0138
43 #define MVEBU_LCD_CFG_RDREG4F 0x013c
44 #define MVEBU_LCD_SPU_SPI_RXDATA 0x0140
45 #define MVEBU_LCD_SPU_ISA_RXDATA 0x0144
46 #define MVEBU_LCD_SPU_DBG_ISA 0x0148
47
48 #define MVEBU_LCD_SPU_HWC_RDDAT 0x0158
49 #define MVEBU_LCD_SPU_GAMMA_RDDAT 0x015c
50 #define MVEBU_LCD_SPU_PALETTE_RDDAT 0x0160
51 #define MVEBU_LCD_SPU_IOPAD_IN 0x0178
52 #define MVEBU_LCD_FRAME_COUNT 0x017c
53 #define MVEBU_LCD_SPU_DMA_CTRL0 0x0190
54 #define MVEBU_LCD_SPU_DMA_CTRL1 0x0194
55 #define MVEBU_LCD_SPU_SRAM_CTRL 0x0198
56 #define MVEBU_LCD_SPU_SRAM_WRDAT 0x019c
57 #define MVEBU_LCD_SPU_SRAM_PARA0 0x01a0
58 #define MVEBU_LCD_SPU_SRAM_PARA1 0x01a4
59 #define MVEBU_LCD_CFG_SCLK_DIV 0x01a8
60 #define MVEBU_LCD_SPU_CONTRAST 0x01ac
61 #define MVEBU_LCD_SPU_SATURATION 0x01b0
62 #define MVEBU_LCD_SPU_CBSH_HUE 0x01b4
63 #define MVEBU_LCD_SPU_DUMB_CTRL 0x01b8
64 #define MVEBU_LCD_SPU_IOPAD_CONTROL 0x01bc
65 #define MVEBU_LCD_SPU_IRQ_ENA_2 0x01d8
66 #define MVEBU_LCD_SPU_IRQ_ISR_2 0x01dc
67 #define MVEBU_LCD_SPU_IRQ_ENA 0x01c0
68 #define MVEBU_LCD_SPU_IRQ_ISR 0x01c4
69 #define MVEBU_LCD_ADLL_CTRL 0x01c8
70 #define MVEBU_LCD_CLK_DIS 0x01cc
71 #define MVEBU_LCD_VGA_HVSYNC_DELAY 0x01d4
72 #define MVEBU_LCD_CLK_CFG_0 0xf0a0
73 #define MVEBU_LCD_CLK_CFG_1 0xf0a4
74 #define MVEBU_LCD_LVDS_CLK_CFG 0xf0ac
75
76 #define MVEBU_LVDS_PADS_REG (MVEBU_SYSTEM_REG_BASE + 0xf0)
77
78 enum {
79 /* Maximum LCD size we support */
80 LCD_MAX_WIDTH = 640,
81 LCD_MAX_HEIGHT = 480,
82 LCD_MAX_LOG2_BPP = VIDEO_BPP16,
83 };
84
85 struct mvebu_lcd_info {
86 u32 fb_base;
87 int x_res;
88 int y_res;
89 int x_fp;
90 int y_fp;
91 int x_bp;
92 int y_bp;
93 };
94
95 struct mvebu_video_priv {
96 uintptr_t regs;
97 };
98
99 /* Setup Mbus Bridge Windows for LCD */
100 static void mvebu_lcd_conf_mbus_registers(uintptr_t regs)
101 {
102 const struct mbus_dram_target_info *dram;
103 int i;
104
105 dram = mvebu_mbus_dram_info();
106
107 /* Disable windows, set size/base/remap to 0 */
108 for (i = 0; i < 6; i++) {
109 writel(0, regs + MVEBU_LCD_WIN_CONTROL(i));
110 writel(0, regs + MVEBU_LCD_WIN_BASE(i));
111 writel(0, regs + MVEBU_LCD_WIN_REMAP(i));
112 }
113
114 /* Write LCD bridge window registers */
115 for (i = 0; i < dram->num_cs; i++) {
116 const struct mbus_dram_window *cs = dram->cs + i;
117 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
118 (dram->mbus_dram_target_id << 4) | 1,
119 regs + MVEBU_LCD_WIN_CONTROL(i));
120
121 writel(cs->base & 0xffff0000, regs + MVEBU_LCD_WIN_BASE(i));
122 }
123 }
124
125 /* Initialize LCD registers */
126 static void mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info,
127 uintptr_t regs)
128 {
129 /* Local variable for easier handling */
130 int x = lcd_info->x_res;
131 int y = lcd_info->y_res;
132 u32 val;
133
134 /* Setup Mbus Bridge Windows */
135 mvebu_lcd_conf_mbus_registers(regs);
136
137 /*
138 * Set LVDS Pads Control Register
139 * wr 0 182F0 FFE00000
140 */
141 clrbits_le32(MVEBU_LVDS_PADS_REG, 0x1f << 16);
142
143 /*
144 * Set the LCD_CFG_GRA_START_ADDR0/1 Registers
145 * This is supposed to point to the "physical" memory at memory
146 * end (currently 1GB-64MB but also may be 2GB-64MB).
147 * See also the Window 0 settings!
148 */
149 writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR0);
150 writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR1);
151
152 /*
153 * Set the LCD_CFG_GRA_PITCH Register
154 * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting)
155 * Bits 25-16: Backlight divider from 32kHz Clock
156 * (here 16=0x10 for 1kHz)
157 * Bits 15-00: Line Length in Bytes
158 * 240*2 (for RGB1555)=480=0x1E0
159 */
160 writel(0x80100000 + 2 * x, regs + MVEBU_LCD_CFG_GRA_PITCH);
161
162 /*
163 * Set the LCD_SPU_GRA_OVSA_HPXL_VLN Register
164 * Bits 31-16: Vertical start of graphical overlay on screen
165 * Bits 15-00: Horizontal start of graphical overlay on screen
166 */
167 writel(0x00000000, regs + MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN);
168
169 /*
170 * Set the LCD_SPU_GRA_HPXL_VLN Register
171 * Bits 31-16: Vertical size of graphical overlay 320=0x140
172 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
173 * Values before zooming
174 */
175 writel((y << 16) | x, regs + MVEBU_LCD_SPU_GRA_HPXL_VLN);
176
177 /*
178 * Set the LCD_SPU_GZM_HPXL_VLN Register
179 * Bits 31-16: Vertical size of graphical overlay 320=0x140
180 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
181 * Values after zooming
182 */
183 writel((y << 16) | x, regs + MVEBU_LCD_SPU_GZM_HPXL_VLN);
184
185 /*
186 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
187 * Bits 31-16: Vertical position of HW Cursor 320=0x140
188 * Bits 15-00: Horizontal position of HW Cursor 240=0xF0
189 */
190 writel((y << 16) | x, regs + MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN);
191
192 /*
193 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
194 * Bits 31-16: Vertical size of HW Cursor
195 * Bits 15-00: Horizontal size of HW Cursor
196 */
197 writel(0x00000000, regs + MVEBU_LCD_SPU_HWC_HPXL_VLN);
198
199 /*
200 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
201 * Bits 31-16: Screen total vertical lines:
202 * VSYNC = 1
203 * Vertical Front Porch = 2
204 * Vertical Lines = 320
205 * Vertical Back Porch = 2
206 * SUM = 325 = 0x0145
207 * Bits 15-00: Screen total horizontal pixels:
208 * HSYNC = 1
209 * Horizontal Front Porch = 44
210 * Horizontal Lines = 240
211 * Horizontal Back Porch = 2
212 * SUM = 287 = 0x011F
213 * Note: For the display the backporch is between SYNC and
214 * the start of the pixels.
215 * This is not certain for the Marvell (!?)
216 */
217 val = ((y + lcd_info->y_fp + lcd_info->y_bp + 1) << 16) |
218 (x + lcd_info->x_fp + lcd_info->x_bp + 1);
219 writel(val, regs + MVEBU_LCD_SPUT_V_H_TOTAL);
220
221 /*
222 * Set the LCD_SPU_V_H_ACTIVE Register
223 * Bits 31-16: Screen active vertical lines 320=0x140
224 * Bits 15-00: Screen active horizontakl pixels 240=0x00F0
225 */
226 writel((y << 16) | x, regs + MVEBU_LCD_SPU_V_H_ACTIVE);
227
228 /*
229 * Set the LCD_SPU_H_PORCH Register
230 * Bits 31-16: Screen horizontal backporch 44=0x2c
231 * Bits 15-00: Screen horizontal frontporch 2=0x02
232 * Note: The terms "front" and "back" for the Marvell seem to be
233 * exactly opposite to the display.
234 */
235 writel((lcd_info->x_fp << 16) | lcd_info->x_bp,
236 regs + MVEBU_LCD_SPU_H_PORCH);
237
238 /*
239 * Set the LCD_SPU_V_PORCH Register
240 * Bits 31-16: Screen vertical backporch 2=0x02
241 * Bits 15-00: Screen vertical frontporch 2=0x02
242 * Note: The terms "front" and "back" for the Marvell seem to be exactly
243 * opposite to the display.
244 */
245 writel((lcd_info->y_fp << 16) | lcd_info->y_bp,
246 regs + MVEBU_LCD_SPU_V_PORCH);
247
248 /*
249 * Set the LCD_SPU_BLANKCOLOR Register
250 * This should be black = 0
251 * For tests this is magenta=00FF00FF
252 */
253 writel(0x00FF00FF, regs + MVEBU_LCD_SPU_BLANKCOLOR);
254
255 /*
256 * Registers in the range of 0x0128 to 0x012C are colors for the cursor
257 * Registers in the range of 0x0130 to 0x0138 are colors for video
258 * color keying
259 */
260
261 /*
262 * Set the LCD_SPU_RDREG4F Register
263 * Bits 31-12: Reservd
264 * Bit 11: SRAM Wait
265 * Bit 10: Smart display fast TX (must be 1)
266 * Bit 9: DMA Arbitration Video/Graphics overlay: 0=interleaved
267 * Bit 8: FIFO watermark for DMA: 0=disable
268 * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80
269 */
270 writel(0x00000780, regs + MVEBU_LCD_CFG_RDREG4F);
271
272 /*
273 * Set the LCD_SPU_DMACTRL 0 Register
274 * Bit 31: Disable overlay blending 1=disable
275 * Bit 30: Gamma correction enable, 0=disable
276 * Bit 29: Video Contrast/Saturation/Hue Adjust enable, 0=disable
277 * Bit 28: Color palette enable, 0=disable
278 * Bit 27: DMA AXI Arbiter, 1=default
279 * Bit 26: HW Cursor 1-bit mode
280 * Bit 25: HW Cursor or 1- or 2-bit mode
281 * Bit 24: HW Cursor enabled, 0=disable
282 * Bits 23-20: Graphics Memory Color Format: 0x1=RGB1555
283 * Bits 19-16: Video Memory Color Format: 0x1=RGB1555
284 * Bit 15: Memory Toggle between frame 0 and 1: 0=disable
285 * Bit 14: Graphics horizontal scaling enable: 0=disable
286 * Bit 13: Graphics test mode: 0=disable
287 * Bit 12: Graphics SWAP R and B: 0=disable
288 * Bit 11: Graphics SWAP U and V: 0=disable
289 * Bit 10: Graphics SWAP Y and U/V: 0=disable
290 * Bit 09: Graphic YUV to RGB Conversion: 0=disable
291 * Bit 08: Graphic Transfer: 1=enable
292 * Bit 07: Memory Toggle: 0=disable
293 * Bit 06: Video horizontal scaling enable: 0=disable
294 * Bit 05: Video test mode: 0=disable
295 * Bit 04: Video SWAP R and B: 0=disable
296 * Bit 03: Video SWAP U and V: 0=disable
297 * Bit 02: Video SWAP Y and U/V: 0=disable
298 * Bit 01: Video YUV to RGB Conversion: 0=disable
299 * Bit 00: Video Transfer: 0=disable
300 */
301 writel(0x88111100, regs + MVEBU_LCD_SPU_DMA_CTRL0);
302
303 /*
304 * Set the LCD_SPU_DMA_CTRL1 Register
305 * Bit 31: Manual DMA Trigger = 0
306 * Bits 30-28: DMA Trigger Source: 0x2 VSYNC
307 * Bit 28: VSYNC_INV: 0=Rising Edge, 1=Falling Edge
308 * Bits 26-24: Color Key Mode: 0=disable
309 * Bit 23: Fill low bits: 0=fill with zeroes
310 * Bit 22: Reserved
311 * Bit 21: Gated Clock: 0=disable
312 * Bit 20: Power Save enable: 0=disable
313 * Bits 19-18: Reserved
314 * Bits 17-16: Configure Video/Graphic Path: 0x1: Graphic path alpha.
315 * Bits 15-08: Configure Alpha: 0x00.
316 * Bits 07-00: Reserved.
317 */
318 writel(0x20010000, regs + MVEBU_LCD_SPU_DMA_CTRL1);
319
320 /*
321 * Set the LCD_SPU_SRAM_CTRL Register
322 * Reset to default = 0000C000
323 * Bits 15-14: SRAM control: init=0x3, Read=0, Write=2
324 * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb,
325 * 3=palette, 15=cursor
326 */
327 writel(0x0000C000, regs + MVEBU_LCD_SPU_SRAM_CTRL);
328
329 /*
330 * LCD_SPU_SRAM_WRDAT register: 019C
331 * LCD_SPU_SRAM_PARA0 register: 01A0
332 * LCD_SPU_SRAM_PARA1 register: 01A4 - Cursor control/Power settings
333 */
334 writel(0x00000000, regs + MVEBU_LCD_SPU_SRAM_PARA1);
335
336
337 /* Clock settings in the at 01A8 and in the range F0A0 see below */
338
339 /*
340 * Set LCD_SPU_CONTRAST
341 * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0
342 * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0
343 */
344 writel(0x00000000, regs + MVEBU_LCD_SPU_CONTRAST);
345
346 /*
347 * Set LCD_SPU_SATURATION
348 * Bits 31-16: Multiplier signed 4.12 fixed point value
349 * Bits 15-00: Saturation signed 4.12 fixed point value
350 */
351 writel(0x10001000, regs + MVEBU_LCD_SPU_SATURATION);
352
353 /*
354 * Set LCD_SPU_HUE
355 * Bits 31-16: Sine signed 2.14 fixed point value
356 * Bits 15-00: Cosine signed 2.14 fixed point value
357 */
358 writel(0x00000000, regs + MVEBU_LCD_SPU_CBSH_HUE);
359
360 /*
361 * Set LCD_SPU_DUMB_CTRL
362 * Bits 31-28: LCD Type: 3=18 bit RGB | 6=24 bit RGB888
363 * Bits 27-12: Reserved
364 * Bit 11: LCD DMA Pipeline Enable: 1=Enable
365 * Bits 10-09: Reserved
366 * Bit 8: LCD GPIO pin (??)
367 * Bit 7: Reverse RGB
368 * Bit 6: Invert composite blank signal DE/EN (??)
369 * Bit 5: Invert composite sync signal
370 * Bit 4: Invert Pixel Valid Enable DE/EN (??)
371 * Bit 3: Invert VSYNC
372 * Bit 2: Invert HSYNC
373 * Bit 1: Invert Pixel Clock
374 * Bit 0: Enable LCD Panel: 1=Enable
375 * Question: Do we have to disable Smart and Dumb LCD
376 * and separately enable LVDS?
377 */
378 writel(0x6000080F, regs + MVEBU_LCD_SPU_DUMB_CTRL);
379
380 /*
381 * Set LCD_SPU_IOPAD_CTRL
382 * Bits 31-20: Reserved
383 * Bits 19-18: Vertical Interpolation: 0=Disable
384 * Bits 17-16: Reserved
385 * Bit 15: Graphics Vertical Mirror enable: 0=disable
386 * Bit 14: Reserved
387 * Bit 13: Video Vertical Mirror enable: 0=disable
388 * Bit 12: Reserved
389 * Bit 11: Command Vertical Mirror enable: 0=disable
390 * Bit 10: Reserved
391 * Bits 09-08: YUV to RGB Color space conversion: 0 (Not used)
392 * Bits 07-04: AXI Bus Master: 0x4: no crossing of 4k boundary,
393 * 128 Bytes burst
394 * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ??
395 */
396 writel(0x000000C0, regs + MVEBU_LCD_SPU_IOPAD_CONTROL);
397
398 /*
399 * Set SUP_IRQ_ENA_2: Disable all interrupts
400 */
401 writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA_2);
402
403 /*
404 * Set SUP_IRQ_ENA: Disable all interrupts.
405 */
406 writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA);
407
408 /*
409 * Set up ADDL Control Register
410 * Bits 31-29: 0x0 = Fastest Delay Line (default)
411 * 0x3 = Slowest Delay Line (default)
412 * Bit 28: Calibration done status.
413 * Bit 27: Reserved
414 * Bit 26: Set Pixel Clock to ADDL output
415 * Bit 25: Reduce CAL Enable
416 * Bits 24-22: Manual calibration value.
417 * Bit 21: Manual calibration enable.
418 * Bit 20: Restart Auto Cal
419 * Bits 19-16: Calibration Threshold voltage, default= 0x2
420 * Bite 15-14: Reserved
421 * Bits 13-11: Divisor for ADDL Clock: 0x1=/2, 0x3=/8, 0x5=/16
422 * Bit 10: Power Down ADDL module, default = 1!
423 * Bits 09-08: Test point configuration: 0x2=Bias, 0x3=High-z
424 * Bit 07: Reset ADDL
425 * Bit 06: Invert ADLL Clock
426 * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay
427 * Note: ADLL is used for a VGA interface with DAC - not used here
428 */
429 writel(0x00000000, regs + MVEBU_LCD_ADLL_CTRL);
430
431 /*
432 * Set the LCD_CLK_DIS Register:
433 * Bits 3 and 4 must be 1
434 */
435 writel(0x00000018, regs + MVEBU_LCD_CLK_DIS);
436
437 /*
438 * Set the LCD_VGA_HSYNC/VSYNC Delay Register:
439 * Bits 03-00: Sets the delay for the HSYNC and VSYNC signals
440 */
441 writel(0x00000000, regs + MVEBU_LCD_VGA_HVSYNC_DELAY);
442
443 /*
444 * Clock registers
445 * See page 475 in the functional spec.
446 */
447
448 /* Step 1 and 2: Disable the PLL */
449
450 /*
451 * Disable PLL, see "LCD Clock Configuration 1 Register" below
452 */
453 writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1);
454
455 /*
456 * Powerdown, see "LCD Clock Configuration 0 Register" below
457 */
458 writel(0x94000174, regs + MVEBU_LCD_CLK_CFG_0);
459
460 /*
461 * Set the LCD_CFG_SCLK_DIV Register
462 * This is set fix to 0x40000001 for the LVDS output:
463 * Bits 31-30: SCLCK Source: 0=AXIBus, 1=AHBus, 2=PLLDivider0
464 * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001
465 * See page 475 in section 28.5.
466 */
467 writel(0x80000001, regs + MVEBU_LCD_CFG_SCLK_DIV);
468
469 /*
470 * Set the LCD Clock Configuration 0 Register:
471 * Bit 31: Powerdown: 0=Power up
472 * Bits 30-29: Reserved
473 * Bits 28-26: PLL_KDIV: This encodes K
474 * K=16 => 0x5
475 * Bits 25-17: PLL_MDIV: This is M-1:
476 * M=1 => 0x0
477 * Bits 16-13: VCO band: 0x1 for 700-920MHz
478 * Bits 12-04: PLL_NDIV: This is N-1 and corresponds to R1_CTRL!
479 * N=28=0x1C => 0x1B
480 * Bits 03-00: R1_CTRL (for N=28 => 0x4)
481 */
482 writel(0x940021B4, regs + MVEBU_LCD_CLK_CFG_0);
483
484 /*
485 * Set the LCD Clock Configuration 1 Register:
486 * Bits 31-19: Reserved
487 * Bit 18: Select PLL: Core PLL, 1=Dedicated PPL
488 * Bit 17: Clock Output Enable: 0=disable, 1=enable
489 * Bit 16: Select RefClk: 0=RefClk (25MHz), 1=External
490 * Bit 15: Half-Div, Device Clock by DIV+0.5*Half-Dev
491 * Bits 14-13: Reserved
492 * Bits 12-00: PLL Full Divider [Note: Assumed to be the Post-Divider
493 * M' for LVDS=7!]
494 */
495 writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1);
496
497 /*
498 * Set the LVDS Clock Configuration Register:
499 * Bit 31: Clock Gating for the input clock to the LVDS
500 * Bit 30: LVDS Serializer enable: 1=Enabled
501 * Bits 29-11: Reserved
502 * Bit 11-08: LVDS Clock delay: 0x02 (default): by 2 pixel clock/7
503 * Bits 07-02: Reserved
504 * Bit 01: 24bbp Option: 0=Option_1,1=Option2
505 * Bit 00: 1=24bbp Panel: 0=18bpp Panel
506 * Note: Bits 0 and must be verified with the help of the
507 * Interface/display
508 */
509 writel(0xC0000201, regs + MVEBU_LCD_LVDS_CLK_CFG);
510
511 /*
512 * Power up PLL (Clock Config 0)
513 */
514 writel(0x140021B4, regs + MVEBU_LCD_CLK_CFG_0);
515
516 /* wait 10 ms */
517 mdelay(10);
518
519 /*
520 * Enable PLL (Clock Config 1)
521 */
522 writel(0x8FF60007, regs + MVEBU_LCD_CLK_CFG_1);
523 }
524
525 static int mvebu_video_probe(struct udevice *dev)
526 {
527 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
528 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
529 struct mvebu_video_priv *priv = dev_get_priv(dev);
530 struct mvebu_lcd_info lcd_info;
531 struct display_timing timings;
532 u32 fb_start, fb_end;
533 int ret;
534
535 priv->regs = dev_read_addr(dev);
536 if (priv->regs == FDT_ADDR_T_NONE) {
537 dev_err(dev, "failed to get LCD address\n");
538 return -ENXIO;
539 }
540
541 ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings);
542 if (ret) {
543 dev_err(dev, "failed to get any display timings\n");
544 return -EINVAL;
545 }
546
547 /* Use DT timing (resolution) in internal info struct */
548 lcd_info.fb_base = plat->base;
549 lcd_info.x_res = timings.hactive.typ;
550 lcd_info.x_fp = timings.hfront_porch.typ;
551 lcd_info.x_bp = timings.hback_porch.typ;
552 lcd_info.y_res = timings.vactive.typ;
553 lcd_info.y_fp = timings.vfront_porch.typ;
554 lcd_info.y_bp = timings.vback_porch.typ;
555
556 /* Initialize the LCD controller */
557 mvebu_lcd_register_init(&lcd_info, priv->regs);
558
559 /* Enable dcache for the frame buffer */
560 fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
561 fb_end = plat->base + plat->size;
562 fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
563 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
564 DCACHE_WRITEBACK);
565 video_set_flush_dcache(dev, true);
566
567 uc_priv->xsize = lcd_info.x_res;
568 uc_priv->ysize = lcd_info.y_res;
569 uc_priv->bpix = VIDEO_BPP16; /* Uses RGB555 format */
570
571 return 0;
572 }
573
574 static int mvebu_video_bind(struct udevice *dev)
575 {
576 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
577
578 plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
579 (1 << LCD_MAX_LOG2_BPP) / 8;
580
581 return 0;
582 }
583
584 static const struct udevice_id mvebu_video_ids[] = {
585 { .compatible = "marvell,armada-xp-lcd" },
586 { }
587 };
588
589 U_BOOT_DRIVER(mvebu_video) = {
590 .name = "mvebu_video",
591 .id = UCLASS_VIDEO,
592 .of_match = mvebu_video_ids,
593 .bind = mvebu_video_bind,
594 .probe = mvebu_video_probe,
595 .priv_auto_alloc_size = sizeof(struct mvebu_video_priv),
596 };
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