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[people/ms/u-boot.git] / drivers / video / mvebu_lcd.c
1 /*
2 * Video driver for Marvell Armada XP SoC
3 *
4 * Initialization of LCD interface and setup of SPLASH screen image
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <video_fb.h>
11 #include <linux/mbus.h>
12 #include <asm/io.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15
16 #define MVEBU_LCD_WIN_CONTROL(w) (MVEBU_LCD_BASE + 0xf000 + ((w) << 4))
17 #define MVEBU_LCD_WIN_BASE(w) (MVEBU_LCD_BASE + 0xf004 + ((w) << 4))
18 #define MVEBU_LCD_WIN_REMAP(w) (MVEBU_LCD_BASE + 0xf00c + ((w) << 4))
19
20 #define MVEBU_LCD_CFG_DMA_START_ADDR_0 (MVEBU_LCD_BASE + 0x00cc)
21 #define MVEBU_LCD_CFG_DMA_START_ADDR_1 (MVEBU_LCD_BASE + 0x00dc)
22
23 #define MVEBU_LCD_CFG_GRA_START_ADDR0 (MVEBU_LCD_BASE + 0x00f4)
24 #define MVEBU_LCD_CFG_GRA_START_ADDR1 (MVEBU_LCD_BASE + 0x00f8)
25 #define MVEBU_LCD_CFG_GRA_PITCH (MVEBU_LCD_BASE + 0x00fc)
26 #define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x0100)
27 #define MVEBU_LCD_SPU_GRA_HPXL_VLN (MVEBU_LCD_BASE + 0x0104)
28 #define MVEBU_LCD_SPU_GZM_HPXL_VLN (MVEBU_LCD_BASE + 0x0108)
29 #define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x010c)
30 #define MVEBU_LCD_SPU_HWC_HPXL_VLN (MVEBU_LCD_BASE + 0x0110)
31 #define MVEBU_LCD_SPUT_V_H_TOTAL (MVEBU_LCD_BASE + 0x0114)
32 #define MVEBU_LCD_SPU_V_H_ACTIVE (MVEBU_LCD_BASE + 0x0118)
33 #define MVEBU_LCD_SPU_H_PORCH (MVEBU_LCD_BASE + 0x011c)
34 #define MVEBU_LCD_SPU_V_PORCH (MVEBU_LCD_BASE + 0x0120)
35 #define MVEBU_LCD_SPU_BLANKCOLOR (MVEBU_LCD_BASE + 0x0124)
36 #define MVEBU_LCD_SPU_ALPHA_COLOR1 (MVEBU_LCD_BASE + 0x0128)
37 #define MVEBU_LCD_SPU_ALPHA_COLOR2 (MVEBU_LCD_BASE + 0x012c)
38 #define MVEBU_LCD_SPU_COLORKEY_Y (MVEBU_LCD_BASE + 0x0130)
39 #define MVEBU_LCD_SPU_COLORKEY_U (MVEBU_LCD_BASE + 0x0134)
40 #define MVEBU_LCD_SPU_COLORKEY_V (MVEBU_LCD_BASE + 0x0138)
41 #define MVEBU_LCD_CFG_RDREG4F (MVEBU_LCD_BASE + 0x013c)
42 #define MVEBU_LCD_SPU_SPI_RXDATA (MVEBU_LCD_BASE + 0x0140)
43 #define MVEBU_LCD_SPU_ISA_RXDATA (MVEBU_LCD_BASE + 0x0144)
44 #define MVEBU_LCD_SPU_DBG_ISA (MVEBU_LCD_BASE + 0x0148)
45
46 #define MVEBU_LCD_SPU_HWC_RDDAT (MVEBU_LCD_BASE + 0x0158)
47 #define MVEBU_LCD_SPU_GAMMA_RDDAT (MVEBU_LCD_BASE + 0x015c)
48 #define MVEBU_LCD_SPU_PALETTE_RDDAT (MVEBU_LCD_BASE + 0x0160)
49 #define MVEBU_LCD_SPU_IOPAD_IN (MVEBU_LCD_BASE + 0x0178)
50 #define MVEBU_LCD_FRAME_COUNT (MVEBU_LCD_BASE + 0x017c)
51 #define MVEBU_LCD_SPU_DMA_CTRL0 (MVEBU_LCD_BASE + 0x0190)
52 #define MVEBU_LCD_SPU_DMA_CTRL1 (MVEBU_LCD_BASE + 0x0194)
53 #define MVEBU_LCD_SPU_SRAM_CTRL (MVEBU_LCD_BASE + 0x0198)
54 #define MVEBU_LCD_SPU_SRAM_WRDAT (MVEBU_LCD_BASE + 0x019c)
55 #define MVEBU_LCD_SPU_SRAM_PARA0 (MVEBU_LCD_BASE + 0x01a0)
56 #define MVEBU_LCD_SPU_SRAM_PARA1 (MVEBU_LCD_BASE + 0x01a4)
57 #define MVEBU_LCD_CFG_SCLK_DIV (MVEBU_LCD_BASE + 0x01a8)
58 #define MVEBU_LCD_SPU_CONTRAST (MVEBU_LCD_BASE + 0x01ac)
59 #define MVEBU_LCD_SPU_SATURATION (MVEBU_LCD_BASE + 0x01b0)
60 #define MVEBU_LCD_SPU_CBSH_HUE (MVEBU_LCD_BASE + 0x01b4)
61 #define MVEBU_LCD_SPU_DUMB_CTRL (MVEBU_LCD_BASE + 0x01b8)
62 #define MVEBU_LCD_SPU_IOPAD_CONTROL (MVEBU_LCD_BASE + 0x01bc)
63 #define MVEBU_LCD_SPU_IRQ_ENA_2 (MVEBU_LCD_BASE + 0x01d8)
64 #define MVEBU_LCD_SPU_IRQ_ISR_2 (MVEBU_LCD_BASE + 0x01dc)
65 #define MVEBU_LCD_SPU_IRQ_ENA (MVEBU_LCD_BASE + 0x01c0)
66 #define MVEBU_LCD_SPU_IRQ_ISR (MVEBU_LCD_BASE + 0x01c4)
67 #define MVEBU_LCD_ADLL_CTRL (MVEBU_LCD_BASE + 0x01c8)
68 #define MVEBU_LCD_CLK_DIS (MVEBU_LCD_BASE + 0x01cc)
69 #define MVEBU_LCD_VGA_HVSYNC_DELAY (MVEBU_LCD_BASE + 0x01d4)
70 #define MVEBU_LCD_CLK_CFG_0 (MVEBU_LCD_BASE + 0xf0a0)
71 #define MVEBU_LCD_CLK_CFG_1 (MVEBU_LCD_BASE + 0xf0a4)
72 #define MVEBU_LCD_LVDS_CLK_CFG (MVEBU_LCD_BASE + 0xf0ac)
73
74 #define MVEBU_LVDS_PADS_REG (MVEBU_SYSTEM_REG_BASE + 0xf0)
75
76 /* Setup Mbus Bridge Windows for LCD */
77 static void mvebu_lcd_conf_mbus_registers(void)
78 {
79 const struct mbus_dram_target_info *dram;
80 int i;
81
82 dram = mvebu_mbus_dram_info();
83
84 /* Disable windows, set size/base/remap to 0 */
85 for (i = 0; i < 6; i++) {
86 writel(0, MVEBU_LCD_WIN_CONTROL(i));
87 writel(0, MVEBU_LCD_WIN_BASE(i));
88 writel(0, MVEBU_LCD_WIN_REMAP(i));
89 }
90
91 /* Write LCD bridge window registers */
92 for (i = 0; i < dram->num_cs; i++) {
93 const struct mbus_dram_window *cs = dram->cs + i;
94 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
95 (dram->mbus_dram_target_id << 4) | 1,
96 MVEBU_LCD_WIN_CONTROL(i));
97
98 writel(cs->base & 0xffff0000, MVEBU_LCD_WIN_BASE(i));
99 }
100 }
101
102 /* Initialize LCD registers */
103 int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info)
104 {
105 /* Local variable for easier handling */
106 int x = lcd_info->x_res;
107 int y = lcd_info->y_res;
108 u32 val;
109
110 /* Setup Mbus Bridge Windows */
111 mvebu_lcd_conf_mbus_registers();
112
113 /*
114 * Set LVDS Pads Control Register
115 * wr 0 182F0 FFE00000
116 */
117 clrbits_le32(MVEBU_LVDS_PADS_REG, 0x1f << 16);
118
119 /*
120 * Set the LCD_CFG_GRA_START_ADDR0/1 Registers
121 * This is supposed to point to the "physical" memory at memory
122 * end (currently 1GB-64MB but also may be 2GB-64MB).
123 * See also the Window 0 settings!
124 */
125 writel(lcd_info->fb_base, MVEBU_LCD_CFG_GRA_START_ADDR0);
126 writel(lcd_info->fb_base, MVEBU_LCD_CFG_GRA_START_ADDR1);
127
128 /*
129 * Set the LCD_CFG_GRA_PITCH Register
130 * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting)
131 * Bits 25-16: Backlight divider from 32kHz Clock
132 * (here 16=0x10 for 1kHz)
133 * Bits 15-00: Line Length in Bytes
134 * 240*2 (for RGB1555)=480=0x1E0
135 */
136 writel(0x80100000 + 2 * x, MVEBU_LCD_CFG_GRA_PITCH);
137
138 /*
139 * Set the LCD_SPU_GRA_OVSA_HPXL_VLN Register
140 * Bits 31-16: Vertical start of graphical overlay on screen
141 * Bits 15-00: Horizontal start of graphical overlay on screen
142 */
143 writel(0x00000000, MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN);
144
145 /*
146 * Set the LCD_SPU_GRA_HPXL_VLN Register
147 * Bits 31-16: Vertical size of graphical overlay 320=0x140
148 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
149 * Values before zooming
150 */
151 writel((y << 16) | x, MVEBU_LCD_SPU_GRA_HPXL_VLN);
152
153 /*
154 * Set the LCD_SPU_GZM_HPXL_VLN Register
155 * Bits 31-16: Vertical size of graphical overlay 320=0x140
156 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
157 * Values after zooming
158 */
159 writel((y << 16) | x, MVEBU_LCD_SPU_GZM_HPXL_VLN);
160
161 /*
162 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
163 * Bits 31-16: Vertical position of HW Cursor 320=0x140
164 * Bits 15-00: Horizontal position of HW Cursor 240=0xF0
165 */
166 writel((y << 16) | x, MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN);
167
168 /*
169 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
170 * Bits 31-16: Vertical size of HW Cursor
171 * Bits 15-00: Horizontal size of HW Cursor
172 */
173 writel(0x00000000, MVEBU_LCD_SPU_HWC_HPXL_VLN);
174
175 /*
176 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
177 * Bits 31-16: Screen total vertical lines:
178 * VSYNC = 1
179 * Vertical Front Porch = 2
180 * Vertical Lines = 320
181 * Vertical Back Porch = 2
182 * SUM = 325 = 0x0145
183 * Bits 15-00: Screen total horizontal pixels:
184 * HSYNC = 1
185 * Horizontal Front Porch = 44
186 * Horizontal Lines = 240
187 * Horizontal Back Porch = 2
188 * SUM = 287 = 0x011F
189 * Note: For the display the backporch is between SYNC and
190 * the start of the pixels.
191 * This is not certain for the Marvell (!?)
192 */
193 val = ((y + lcd_info->y_fp + lcd_info->y_bp + 1) << 16) |
194 (x + lcd_info->x_fp + lcd_info->x_bp + 1);
195 writel(val, MVEBU_LCD_SPUT_V_H_TOTAL);
196
197 /*
198 * Set the LCD_SPU_V_H_ACTIVE Register
199 * Bits 31-16: Screen active vertical lines 320=0x140
200 * Bits 15-00: Screen active horizontakl pixels 240=0x00F0
201 */
202 writel((y << 16) | x, MVEBU_LCD_SPU_V_H_ACTIVE);
203
204 /*
205 * Set the LCD_SPU_H_PORCH Register
206 * Bits 31-16: Screen horizontal backporch 44=0x2c
207 * Bits 15-00: Screen horizontal frontporch 2=0x02
208 * Note: The terms "front" and "back" for the Marvell seem to be
209 * exactly opposite to the display.
210 */
211 writel((lcd_info->x_fp << 16) | lcd_info->x_bp, MVEBU_LCD_SPU_H_PORCH);
212
213 /*
214 * Set the LCD_SPU_V_PORCH Register
215 * Bits 31-16: Screen vertical backporch 2=0x02
216 * Bits 15-00: Screen vertical frontporch 2=0x02
217 * Note: The terms "front" and "back" for the Marvell seem to be exactly
218 * opposite to the display.
219 */
220 writel((lcd_info->y_fp << 16) | lcd_info->y_bp, MVEBU_LCD_SPU_V_PORCH);
221
222 /*
223 * Set the LCD_SPU_BLANKCOLOR Register
224 * This should be black = 0
225 * For tests this is magenta=00FF00FF
226 */
227 writel(0x00FF00FF, MVEBU_LCD_SPU_BLANKCOLOR);
228
229 /*
230 * Registers in the range of 0x0128 to 0x012C are colors for the cursor
231 * Registers in the range of 0x0130 to 0x0138 are colors for video
232 * color keying
233 */
234
235 /*
236 * Set the LCD_SPU_RDREG4F Register
237 * Bits 31-12: Reservd
238 * Bit 11: SRAM Wait
239 * Bit 10: Smart display fast TX (must be 1)
240 * Bit 9: DMA Arbitration Video/Graphics overlay: 0=interleaved
241 * Bit 8: FIFO watermark for DMA: 0=disable
242 * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80
243 */
244 writel(0x00000780, MVEBU_LCD_CFG_RDREG4F);
245
246 /*
247 * Set the LCD_SPU_DMACTRL 0 Register
248 * Bit 31: Disable overlay blending 1=disable
249 * Bit 30: Gamma correction enable, 0=disable
250 * Bit 29: Video Contrast/Saturation/Hue Adjust enable, 0=disable
251 * Bit 28: Color palette enable, 0=disable
252 * Bit 27: DMA AXI Arbiter, 1=default
253 * Bit 26: HW Cursor 1-bit mode
254 * Bit 25: HW Cursor or 1- or 2-bit mode
255 * Bit 24: HW Cursor enabled, 0=disable
256 * Bits 23-20: Graphics Memory Color Format: 0x1=RGB1555
257 * Bits 19-16: Video Memory Color Format: 0x1=RGB1555
258 * Bit 15: Memory Toggle between frame 0 and 1: 0=disable
259 * Bit 14: Graphics horizontal scaling enable: 0=disable
260 * Bit 13: Graphics test mode: 0=disable
261 * Bit 12: Graphics SWAP R and B: 0=disable
262 * Bit 11: Graphics SWAP U and V: 0=disable
263 * Bit 10: Graphics SWAP Y and U/V: 0=disable
264 * Bit 09: Graphic YUV to RGB Conversion: 0=disable
265 * Bit 08: Graphic Transfer: 1=enable
266 * Bit 07: Memory Toggle: 0=disable
267 * Bit 06: Video horizontal scaling enable: 0=disable
268 * Bit 05: Video test mode: 0=disable
269 * Bit 04: Video SWAP R and B: 0=disable
270 * Bit 03: Video SWAP U and V: 0=disable
271 * Bit 02: Video SWAP Y and U/V: 0=disable
272 * Bit 01: Video YUV to RGB Conversion: 0=disable
273 * Bit 00: Video Transfer: 0=disable
274 */
275 writel(0x88111100, MVEBU_LCD_SPU_DMA_CTRL0);
276
277 /*
278 * Set the LCD_SPU_DMA_CTRL1 Register
279 * Bit 31: Manual DMA Trigger = 0
280 * Bits 30-28: DMA Trigger Source: 0x2 VSYNC
281 * Bit 28: VSYNC_INV: 0=Rising Edge, 1=Falling Edge
282 * Bits 26-24: Color Key Mode: 0=disable
283 * Bit 23: Fill low bits: 0=fill with zeroes
284 * Bit 22: Reserved
285 * Bit 21: Gated Clock: 0=disable
286 * Bit 20: Power Save enable: 0=disable
287 * Bits 19-18: Reserved
288 * Bits 17-16: Configure Video/Graphic Path: 0x1: Graphic path alpha.
289 * Bits 15-08: Configure Alpha: 0x00.
290 * Bits 07-00: Reserved.
291 */
292 writel(0x20010000, MVEBU_LCD_SPU_DMA_CTRL1);
293
294 /*
295 * Set the LCD_SPU_SRAM_CTRL Register
296 * Reset to default = 0000C000
297 * Bits 15-14: SRAM control: init=0x3, Read=0, Write=2
298 * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb,
299 * 3=palette, 15=cursor
300 */
301 writel(0x0000C000, MVEBU_LCD_SPU_SRAM_CTRL);
302
303 /*
304 * LCD_SPU_SRAM_WRDAT register: 019C
305 * LCD_SPU_SRAM_PARA0 register: 01A0
306 * LCD_SPU_SRAM_PARA1 register: 01A4 - Cursor control/Power settings
307 */
308 writel(0x00000000, MVEBU_LCD_SPU_SRAM_PARA1);
309
310
311 /* Clock settings in the at 01A8 and in the range F0A0 see below */
312
313 /*
314 * Set LCD_SPU_CONTRAST
315 * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0
316 * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0
317 */
318 writel(0x00000000, MVEBU_LCD_SPU_CONTRAST);
319
320 /*
321 * Set LCD_SPU_SATURATION
322 * Bits 31-16: Multiplier signed 4.12 fixed point value
323 * Bits 15-00: Saturation signed 4.12 fixed point value
324 */
325 writel(0x10001000, MVEBU_LCD_SPU_SATURATION);
326
327 /*
328 * Set LCD_SPU_HUE
329 * Bits 31-16: Sine signed 2.14 fixed point value
330 * Bits 15-00: Cosine signed 2.14 fixed point value
331 */
332 writel(0x00000000, MVEBU_LCD_SPU_CBSH_HUE);
333
334 /*
335 * Set LCD_SPU_DUMB_CTRL
336 * Bits 31-28: LCD Type: 3=18 bit RGB | 6=24 bit RGB888
337 * Bits 27-12: Reserved
338 * Bit 11: LCD DMA Pipeline Enable: 1=Enable
339 * Bits 10-09: Reserved
340 * Bit 8: LCD GPIO pin (??)
341 * Bit 7: Reverse RGB
342 * Bit 6: Invert composite blank signal DE/EN (??)
343 * Bit 5: Invert composite sync signal
344 * Bit 4: Invert Pixel Valid Enable DE/EN (??)
345 * Bit 3: Invert VSYNC
346 * Bit 2: Invert HSYNC
347 * Bit 1: Invert Pixel Clock
348 * Bit 0: Enable LCD Panel: 1=Enable
349 * Question: Do we have to disable Smart and Dumb LCD
350 * and separately enable LVDS?
351 */
352 writel(0x6000080F, MVEBU_LCD_SPU_DUMB_CTRL);
353
354 /*
355 * Set LCD_SPU_IOPAD_CTRL
356 * Bits 31-20: Reserved
357 * Bits 19-18: Vertical Interpolation: 0=Disable
358 * Bits 17-16: Reserved
359 * Bit 15: Graphics Vertical Mirror enable: 0=disable
360 * Bit 14: Reserved
361 * Bit 13: Video Vertical Mirror enable: 0=disable
362 * Bit 12: Reserved
363 * Bit 11: Command Vertical Mirror enable: 0=disable
364 * Bit 10: Reserved
365 * Bits 09-08: YUV to RGB Color space conversion: 0 (Not used)
366 * Bits 07-04: AXI Bus Master: 0x4: no crossing of 4k boundary,
367 * 128 Bytes burst
368 * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ??
369 */
370 writel(0x000000C0, MVEBU_LCD_SPU_IOPAD_CONTROL);
371
372 /*
373 * Set SUP_IRQ_ENA_2: Disable all interrupts
374 */
375 writel(0x00000000, MVEBU_LCD_SPU_IRQ_ENA_2);
376
377 /*
378 * Set SUP_IRQ_ENA: Disable all interrupts.
379 */
380 writel(0x00000000, MVEBU_LCD_SPU_IRQ_ENA);
381
382 /*
383 * Set up ADDL Control Register
384 * Bits 31-29: 0x0 = Fastest Delay Line (default)
385 * 0x3 = Slowest Delay Line (default)
386 * Bit 28: Calibration done status.
387 * Bit 27: Reserved
388 * Bit 26: Set Pixel Clock to ADDL output
389 * Bit 25: Reduce CAL Enable
390 * Bits 24-22: Manual calibration value.
391 * Bit 21: Manual calibration enable.
392 * Bit 20: Restart Auto Cal
393 * Bits 19-16: Calibration Threshold voltage, default= 0x2
394 * Bite 15-14: Reserved
395 * Bits 13-11: Divisor for ADDL Clock: 0x1=/2, 0x3=/8, 0x5=/16
396 * Bit 10: Power Down ADDL module, default = 1!
397 * Bits 09-08: Test point configuration: 0x2=Bias, 0x3=High-z
398 * Bit 07: Reset ADDL
399 * Bit 06: Invert ADLL Clock
400 * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay
401 * Note: ADLL is used for a VGA interface with DAC - not used here
402 */
403 writel(0x00000000, MVEBU_LCD_ADLL_CTRL);
404
405 /*
406 * Set the LCD_CLK_DIS Register:
407 * Bits 3 and 4 must be 1
408 */
409 writel(0x00000018, MVEBU_LCD_CLK_DIS);
410
411 /*
412 * Set the LCD_VGA_HSYNC/VSYNC Delay Register:
413 * Bits 03-00: Sets the delay for the HSYNC and VSYNC signals
414 */
415 writel(0x00000000, MVEBU_LCD_VGA_HVSYNC_DELAY);
416
417 /*
418 * Clock registers
419 * See page 475 in the functional spec.
420 */
421
422 /* Step 1 and 2: Disable the PLL */
423
424 /*
425 * Disable PLL, see "LCD Clock Configuration 1 Register" below
426 */
427 writel(0x8FF40007, MVEBU_LCD_CLK_CFG_1);
428
429 /*
430 * Powerdown, see "LCD Clock Configuration 0 Register" below
431 */
432 writel(0x94000174, MVEBU_LCD_CLK_CFG_0);
433
434 /*
435 * Set the LCD_CFG_SCLK_DIV Register
436 * This is set fix to 0x40000001 for the LVDS output:
437 * Bits 31-30: SCLCK Source: 0=AXIBus, 1=AHBus, 2=PLLDivider0
438 * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001
439 * See page 475 in section 28.5.
440 */
441 writel(0x80000001, MVEBU_LCD_CFG_SCLK_DIV);
442
443 /*
444 * Set the LCD Clock Configuration 0 Register:
445 * Bit 31: Powerdown: 0=Power up
446 * Bits 30-29: Reserved
447 * Bits 28-26: PLL_KDIV: This encodes K
448 * K=16 => 0x5
449 * Bits 25-17: PLL_MDIV: This is M-1:
450 * M=1 => 0x0
451 * Bits 16-13: VCO band: 0x1 for 700-920MHz
452 * Bits 12-04: PLL_NDIV: This is N-1 and corresponds to R1_CTRL!
453 * N=28=0x1C => 0x1B
454 * Bits 03-00: R1_CTRL (for N=28 => 0x4)
455 */
456 writel(0x940021B4, MVEBU_LCD_CLK_CFG_0);
457
458 /*
459 * Set the LCD Clock Configuration 1 Register:
460 * Bits 31-19: Reserved
461 * Bit 18: Select PLL: Core PLL, 1=Dedicated PPL
462 * Bit 17: Clock Output Enable: 0=disable, 1=enable
463 * Bit 16: Select RefClk: 0=RefClk (25MHz), 1=External
464 * Bit 15: Half-Div, Device Clock by DIV+0.5*Half-Dev
465 * Bits 14-13: Reserved
466 * Bits 12-00: PLL Full Divider [Note: Assumed to be the Post-Divider
467 * M' for LVDS=7!]
468 */
469 writel(0x8FF40007, MVEBU_LCD_CLK_CFG_1);
470
471 /*
472 * Set the LVDS Clock Configuration Register:
473 * Bit 31: Clock Gating for the input clock to the LVDS
474 * Bit 30: LVDS Serializer enable: 1=Enabled
475 * Bits 29-11: Reserved
476 * Bit 11-08: LVDS Clock delay: 0x02 (default): by 2 pixel clock/7
477 * Bits 07-02: Reserved
478 * Bit 01: 24bbp Option: 0=Option_1,1=Option2
479 * Bit 00: 1=24bbp Panel: 0=18bpp Panel
480 * Note: Bits 0 and must be verified with the help of the
481 * Interface/display
482 */
483 writel(0xC0000201, MVEBU_LCD_LVDS_CLK_CFG);
484
485 /*
486 * Power up PLL (Clock Config 0)
487 */
488 writel(0x140021B4, MVEBU_LCD_CLK_CFG_0);
489
490 /* wait 10 ms */
491 mdelay(10);
492
493 /*
494 * Enable PLL (Clock Config 1)
495 */
496 writel(0x8FF60007, MVEBU_LCD_CLK_CFG_1);
497
498 return 0;
499 }
500
501 int __weak board_video_init(void)
502 {
503 return -1;
504 }
505
506 void *video_hw_init(void)
507 {
508 static GraphicDevice mvebufb;
509 GraphicDevice *pGD = &mvebufb;
510 u32 val;
511
512 /*
513 * The board code needs to call mvebu_lcd_register_init()
514 * in its board_video_init() implementation, with the board
515 * specific parameters for its LCD.
516 */
517 if (board_video_init() || !readl(MVEBU_LCD_CFG_GRA_START_ADDR0))
518 return NULL;
519
520 /* Provide the necessary values for the U-Boot video IF */
521 val = readl(MVEBU_LCD_SPU_V_H_ACTIVE);
522 pGD->winSizeY = val >> 16;
523 pGD->winSizeX = val & 0x0000ffff;
524 pGD->gdfBytesPP = 2;
525 pGD->gdfIndex = GDF_15BIT_555RGB;
526 pGD->frameAdrs = readl(MVEBU_LCD_CFG_GRA_START_ADDR0);
527
528 debug("LCD: buffer at 0x%08x resolution %dx%d\n", pGD->frameAdrs,
529 pGD->winSizeX, pGD->winSizeY);
530
531 return pGD;
532 }
"Das U-Boot" Source Tree