drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <linux/fb.h>
  17 #include <video_fb.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 struct sunxi_display {
  22         GraphicDevice graphic_device;
  23         bool enabled;
  24 } sunxi_display;
  25
  26 static int sunxi_hdmi_hpd_detect(void)
  27 {
  28         struct sunxi_ccm_reg * const ccm =
  29                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  30         struct sunxi_hdmi_reg * const hdmi =
  31                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  32
  33         /* Set pll3 to 300MHz */
  34         clock_set_pll3(300000000);
  35
  36         /* Set hdmi parent to pll3 */
  37         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  38                         CCM_HDMI_CTRL_PLL3);
  39
  40         /* Set ahb gating to pass */
  41 #ifdef CONFIG_MACH_SUN6I
  42         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  43 #endif
  44         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  45
  46         /* Clock on */
  47         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  48
  49         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  50         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  51
  52         udelay(1000);
  53
  54         if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  55                 return 1;
  56
  57         /* No need to keep these running */
  58         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
  59         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  60         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  61 #ifdef CONFIG_MACH_SUN6I
  62         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  63 #endif
  64         clock_set_pll3(0);
  65
  66         return 0;
  67 }
  68
  69 /*
  70  * This is the entity that mixes and matches the different layers and inputs.
  71  * Allwinner calls it the back-end, but i like composer better.
  72  */
  73 static void sunxi_composer_init(void)
  74 {
  75         struct sunxi_ccm_reg * const ccm =
  76                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  77         struct sunxi_de_be_reg * const de_be =
  78                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
  79         int i;
  80
  81 #ifdef CONFIG_MACH_SUN6I
  82         /* Reset off */
  83         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
  84 #endif
  85
  86         /* Clocks on */
  87         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
  88         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
  89         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
  90
  91         /* Engine bug, clear registers after reset */
  92         for (i = 0x0800; i < 0x1000; i += 4)
  93                 writel(0, SUNXI_DE_BE0_BASE + i);
  94
  95         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
  96 }
  97
  98 static void sunxi_composer_mode_set(struct fb_videomode *mode,
  99                                     unsigned int address)
 100 {
 101         struct sunxi_de_be_reg * const de_be =
 102                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 103
 104         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 105                &de_be->disp_size);
 106         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 107                &de_be->layer0_size);
 108         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 109         writel(address << 3, &de_be->layer0_addr_low32b);
 110         writel(address >> 29, &de_be->layer0_addr_high4b);
 111         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 112
 113         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 114 }
 115
 116 /*
 117  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 118  */
 119 static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
 120 {
 121         struct sunxi_ccm_reg * const ccm =
 122                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 123         int value, n, m, diff;
 124         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 125         int best_double = 0;
 126
 127         /*
 128          * Find the lowest divider resulting in a matching clock, if there
 129          * is no match, pick the closest lower clock, as monitors tend to
 130          * not sync to higher frequencies.
 131          */
 132         for (m = 15; m > 0; m--) {
 133                 n = (m * dotclock) / 3000;
 134
 135                 if ((n >= 9) && (n <= 127)) {
 136                         value = (3000 * n) / m;
 137                         diff = dotclock - value;
 138                         if (diff < best_diff) {
 139                                 best_diff = diff;
 140                                 best_m = m;
 141                                 best_n = n;
 142                                 best_double = 0;
 143                         }
 144                 }
 145
 146                 /* These are just duplicates */
 147                 if (!(m & 1))
 148                         continue;
 149
 150                 n = (m * dotclock) / 6000;
 151                 if ((n >= 9) && (n <= 127)) {
 152                         value = (6000 * n) / m;
 153                         diff = dotclock - value;
 154                         if (diff < best_diff) {
 155                                 best_diff = diff;
 156                                 best_m = m;
 157                                 best_n = n;
 158                                 best_double = 1;
 159                         }
 160                 }
 161         }
 162
 163         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 164               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 165               best_double + 1, best_n, best_m);
 166
 167         clock_set_pll3(best_n * 3000000);
 168
 169         writel(CCM_LCD_CH1_CTRL_GATE |
 170             (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
 171             CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 172
 173         *clk_div = best_m;
 174         *clk_double = best_double;
 175 }
 176
 177 static void sunxi_lcdc_init(void)
 178 {
 179         struct sunxi_ccm_reg * const ccm =
 180                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 181         struct sunxi_lcdc_reg * const lcdc =
 182                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 183
 184         /* Reset off */
 185 #ifdef CONFIG_MACH_SUN6I
 186         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 187 #else
 188         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 189 #endif
 190
 191         /* Clock on */
 192         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 193
 194         /* Init lcdc */
 195         writel(0, &lcdc->ctrl); /* Disable tcon */
 196         writel(0, &lcdc->int0); /* Disable all interrupts */
 197
 198         /* Disable tcon0 dot clock */
 199         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 200
 201         /* Set all io lines to tristate */
 202         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 203         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 204 }
 205
 206 static void sunxi_lcdc_mode_set(struct fb_videomode *mode,
 207                                 int *clk_div, int *clk_double)
 208 {
 209         struct sunxi_lcdc_reg * const lcdc =
 210                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 211         int bp, total;
 212
 213         /* Use tcon1 */
 214         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 215                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 216
 217         /* Enabled, 0x1e start delay */
 218         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 219                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
 220
 221         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 222                &lcdc->tcon1_timing_source);
 223         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 224                &lcdc->tcon1_timing_scale);
 225         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 226                &lcdc->tcon1_timing_out);
 227
 228         bp = mode->hsync_len + mode->left_margin;
 229         total = mode->xres + mode->right_margin + bp;
 230         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 231                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 232
 233         bp = mode->vsync_len + mode->upper_margin;
 234         total = mode->yres + mode->lower_margin + bp;
 235         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 236                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 237
 238         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 239                &lcdc->tcon1_timing_sync);
 240
 241         sunxi_lcdc_pll_set(mode->pixclock, clk_div, clk_double);
 242 }
 243
 244 #ifdef CONFIG_MACH_SUN6I
 245 static void sunxi_drc_init(void)
 246 {
 247         struct sunxi_ccm_reg * const ccm =
 248                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 249
 250         /* On sun6i the drc must be clocked even when in pass-through mode */
 251         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 252         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 253 }
 254 #endif
 255
 256 static void sunxi_hdmi_mode_set(struct fb_videomode *mode,
 257                                 int clk_div, int clk_double)
 258 {
 259         struct sunxi_hdmi_reg * const hdmi =
 260                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 261         int x, y;
 262
 263         /* Write clear interrupt status bits */
 264         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 265
 266         /* Init various registers, select pll3 as clock source */
 267         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 268         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 269         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 270         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 271         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 272
 273         /* Setup clk div and doubler */
 274         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 275                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 276         if (!clk_double)
 277                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 278
 279         /* Setup timing registers */
 280         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 281                &hdmi->video_size);
 282
 283         x = mode->hsync_len + mode->left_margin;
 284         y = mode->vsync_len + mode->upper_margin;
 285         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 286
 287         x = mode->right_margin;
 288         y = mode->lower_margin;
 289         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 290
 291         x = mode->hsync_len;
 292         y = mode->vsync_len;
 293         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 294
 295         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 296                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 297
 298         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 299                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 300 }
 301
 302 static void sunxi_engines_init(void)
 303 {
 304         sunxi_composer_init();
 305         sunxi_lcdc_init();
 306 #ifdef CONFIG_MACH_SUN6I
 307         sunxi_drc_init();
 308 #endif
 309 }
 310
 311 static void sunxi_mode_set(struct fb_videomode *mode, unsigned int address)
 312 {
 313         struct sunxi_de_be_reg * const de_be =
 314                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 315         struct sunxi_lcdc_reg * const lcdc =
 316                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 317         struct sunxi_hdmi_reg * const hdmi =
 318                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 319         int clk_div, clk_double;
 320         int retries = 3;
 321
 322 retry:
 323         clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 324         clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 325         clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 326
 327         sunxi_composer_mode_set(mode, address);
 328         sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
 329         sunxi_hdmi_mode_set(mode, clk_div, clk_double);
 330
 331         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 332         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 333
 334         udelay(1000000 / mode->refresh + 500);
 335
 336         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 337
 338         udelay(1000000 / mode->refresh + 500);
 339
 340         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 341
 342         udelay(1000000 / mode->refresh + 500);
 343
 344         /*
 345          * Sometimes the display pipeline does not sync up properly, if
 346          * this happens the hdmi fifo underrun or overrun bits are set.
 347          */
 348         if (readl(&hdmi->irq) &
 349             (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) {
 350                 if (retries--)
 351                         goto retry;
 352                 printf("HDMI fifo under or overrun\n");
 353         }
 354 }
 355
 356 void *video_hw_init(void)
 357 {
 358         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 359         /*
 360          * Vesa standard 1024x768@60
 361          * 65.0  1024 1048 1184 1344  768 771 777 806  -hsync -vsync
 362          */
 363         struct fb_videomode mode = {
 364                 .name = "1024x768",
 365                 .refresh = 60,
 366                 .xres = 1024,
 367                 .yres = 768,
 368                 .pixclock = 65000,
 369                 .left_margin = 160,
 370                 .right_margin = 24,
 371                 .upper_margin = 29,
 372                 .lower_margin = 3,
 373                 .hsync_len = 136,
 374                 .vsync_len = 6,
 375                 .sync = 0,
 376                 .vmode = 0,
 377                 .flag = 0,
 378         };
 379         int ret;
 380
 381         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 382
 383         printf("Reserved %dkB of RAM for Framebuffer.\n",
 384                CONFIG_SUNXI_FB_SIZE >> 10);
 385         gd->fb_base = gd->ram_top;
 386
 387         ret = sunxi_hdmi_hpd_detect();
 388         if (!ret)
 389                 return NULL;
 390
 391         printf("HDMI connected.\n");
 392         sunxi_display.enabled = true;
 393
 394         printf("Setting up a %s console.\n", mode.name);
 395         sunxi_engines_init();
 396         sunxi_mode_set(&mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
 397
 398         /*
 399          * These are the only members of this structure that are used. All the
 400          * others are driver specific. There is nothing to decribe pitch or
 401          * stride, but we are lucky with our hw.
 402          */
 403         graphic_device->frameAdrs = gd->fb_base;
 404         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
 405         graphic_device->gdfBytesPP = 4;
 406         graphic_device->winSizeX = mode.xres;
 407         graphic_device->winSizeY = mode.yres;
 408
 409         return graphic_device;
 410 }