drivers/watchdog/imx2_wdt.c

   1 /*
   2  * Watchdog driver for IMX2 and later processors
   3  *
   4  *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
   5  *  Copyright (C) 2014 Freescale Semiconductor, Inc.
   6  *
   7  * some parts adapted by similar drivers from Darius Augulis and Vladimir
   8  * Zapolskiy, additional improvements by Wim Van Sebroeck.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
  15  *
  16  *                      MX1:            MX2+:
  17  *                      ----            -----
  18  * Registers:           32-bit          16-bit
  19  * Stopable timer:      Yes             No
  20  * Need to enable clk:  No              Yes
  21  * Halt on suspend:     Manual          Can be automatic
  22  */
  23
  24 #include <linux/clk.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/moduleparam.h>
  32 #include <linux/of_address.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regmap.h>
  35 #include <linux/watchdog.h>
  36
  37 #define DRIVER_NAME "imx2-wdt"
  38
  39 #define IMX2_WDT_WCR            0x00            /* Control Register */
  40 #define IMX2_WDT_WCR_WT         (0xFF << 8)     /* -> Watchdog Timeout Field */
  41 #define IMX2_WDT_WCR_WDA        BIT(5)          /* -> External Reset WDOG_B */
  42 #define IMX2_WDT_WCR_SRS        BIT(4)          /* -> Software Reset Signal */
  43 #define IMX2_WDT_WCR_WRE        BIT(3)          /* -> WDOG Reset Enable */
  44 #define IMX2_WDT_WCR_WDE        BIT(2)          /* -> Watchdog Enable */
  45 #define IMX2_WDT_WCR_WDZST      BIT(0)          /* -> Watchdog timer Suspend */
  46
  47 #define IMX2_WDT_WSR            0x02            /* Service Register */
  48 #define IMX2_WDT_SEQ1           0x5555          /* -> service sequence 1 */
  49 #define IMX2_WDT_SEQ2           0xAAAA          /* -> service sequence 2 */
  50
  51 #define IMX2_WDT_WRSR           0x04            /* Reset Status Register */
  52 #define IMX2_WDT_WRSR_TOUT      BIT(1)          /* -> Reset due to Timeout */
  53
  54 #define IMX2_WDT_WICR           0x06            /* Interrupt Control Register */
  55 #define IMX2_WDT_WICR_WIE       BIT(15)         /* -> Interrupt Enable */
  56 #define IMX2_WDT_WICR_WTIS      BIT(14)         /* -> Interrupt Status */
  57 #define IMX2_WDT_WICR_WICT      0xFF            /* -> Interrupt Count Timeout */
  58
  59 #define IMX2_WDT_WMCR           0x08            /* Misc Register */
  60
  61 #define IMX2_WDT_MAX_TIME       128U
  62 #define IMX2_WDT_DEFAULT_TIME   60              /* in seconds */
  63
  64 #define WDOG_SEC_TO_COUNT(s)    ((s * 2 - 1) << 8)
  65
  66 struct imx2_wdt_device {
  67         struct clk *clk;
  68         struct regmap *regmap;
  69         struct watchdog_device wdog;
  70         bool ext_reset;
  71 };
  72
  73 static bool nowayout = WATCHDOG_NOWAYOUT;
  74 module_param(nowayout, bool, 0);
  75 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  76                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  77
  78
  79 static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
  80 module_param(timeout, uint, 0);
  81 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
  82                                 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
  83
  84 static const struct watchdog_info imx2_wdt_info = {
  85         .identity = "imx2+ watchdog",
  86         .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
  87 };
  88
  89 static const struct watchdog_info imx2_wdt_pretimeout_info = {
  90         .identity = "imx2+ watchdog",
  91         .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
  92                    WDIOF_PRETIMEOUT,
  93 };
  94
  95 static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
  96                             void *data)
  97 {
  98         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  99         unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
 100
 101         /* Use internal reset or external - not both */
 102         if (wdev->ext_reset)
 103                 wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
 104         else
 105                 wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
 106
 107         /* Assert SRS signal */
 108         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
 109         /*
 110          * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
 111          * written twice), we add another two writes to ensure there must be at
 112          * least two writes happen in the same one 32kHz clock period.  We save
 113          * the target check here, since the writes shouldn't be a huge burden
 114          * for other platforms.
 115          */
 116         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
 117         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
 118
 119         /* wait for reset to assert... */
 120         mdelay(500);
 121
 122         return 0;
 123 }
 124
 125 static inline void imx2_wdt_setup(struct watchdog_device *wdog)
 126 {
 127         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 128         u32 val;
 129
 130         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 131
 132         /* Suspend timer in low power mode, write once-only */
 133         val |= IMX2_WDT_WCR_WDZST;
 134         /* Strip the old watchdog Time-Out value */
 135         val &= ~IMX2_WDT_WCR_WT;
 136         /* Generate internal chip-level reset if WDOG times out */
 137         if (!wdev->ext_reset)
 138                 val &= ~IMX2_WDT_WCR_WRE;
 139         /* Or if external-reset assert WDOG_B reset only on time-out */
 140         else
 141                 val |= IMX2_WDT_WCR_WRE;
 142         /* Keep Watchdog Disabled */
 143         val &= ~IMX2_WDT_WCR_WDE;
 144         /* Set the watchdog's Time-Out value */
 145         val |= WDOG_SEC_TO_COUNT(wdog->timeout);
 146
 147         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 148
 149         /* enable the watchdog */
 150         val |= IMX2_WDT_WCR_WDE;
 151         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 152 }
 153
 154 static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
 155 {
 156         u32 val;
 157
 158         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 159
 160         return val & IMX2_WDT_WCR_WDE;
 161 }
 162
 163 static int imx2_wdt_ping(struct watchdog_device *wdog)
 164 {
 165         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 166
 167         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
 168         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
 169         return 0;
 170 }
 171
 172 static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
 173                                    unsigned int new_timeout)
 174 {
 175         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 176
 177         regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
 178                            WDOG_SEC_TO_COUNT(new_timeout));
 179 }
 180
 181 static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
 182                                 unsigned int new_timeout)
 183 {
 184         unsigned int actual;
 185
 186         actual = min(new_timeout, IMX2_WDT_MAX_TIME);
 187         __imx2_wdt_set_timeout(wdog, actual);
 188         wdog->timeout = new_timeout;
 189         return 0;
 190 }
 191
 192 static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
 193                                    unsigned int new_pretimeout)
 194 {
 195         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 196
 197         if (new_pretimeout >= IMX2_WDT_MAX_TIME)
 198                 return -EINVAL;
 199
 200         wdog->pretimeout = new_pretimeout;
 201
 202         regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
 203                            IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
 204                            IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
 205         return 0;
 206 }
 207
 208 static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
 209 {
 210         struct watchdog_device *wdog = wdog_arg;
 211         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 212
 213         regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
 214                           IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
 215
 216         watchdog_notify_pretimeout(wdog);
 217
 218         return IRQ_HANDLED;
 219 }
 220
 221 static int imx2_wdt_start(struct watchdog_device *wdog)
 222 {
 223         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 224
 225         if (imx2_wdt_is_running(wdev))
 226                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 227         else
 228                 imx2_wdt_setup(wdog);
 229
 230         set_bit(WDOG_HW_RUNNING, &wdog->status);
 231
 232         return imx2_wdt_ping(wdog);
 233 }
 234
 235 static const struct watchdog_ops imx2_wdt_ops = {
 236         .owner = THIS_MODULE,
 237         .start = imx2_wdt_start,
 238         .ping = imx2_wdt_ping,
 239         .set_timeout = imx2_wdt_set_timeout,
 240         .set_pretimeout = imx2_wdt_set_pretimeout,
 241         .restart = imx2_wdt_restart,
 242 };
 243
 244 static const struct regmap_config imx2_wdt_regmap_config = {
 245         .reg_bits = 16,
 246         .reg_stride = 2,
 247         .val_bits = 16,
 248         .max_register = 0x8,
 249 };
 250
 251 static int __init imx2_wdt_probe(struct platform_device *pdev)
 252 {
 253         struct imx2_wdt_device *wdev;
 254         struct watchdog_device *wdog;
 255         struct resource *res;
 256         void __iomem *base;
 257         int ret;
 258         u32 val;
 259
 260         wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
 261         if (!wdev)
 262                 return -ENOMEM;
 263
 264         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 265         base = devm_ioremap_resource(&pdev->dev, res);
 266         if (IS_ERR(base))
 267                 return PTR_ERR(base);
 268
 269         wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
 270                                                  &imx2_wdt_regmap_config);
 271         if (IS_ERR(wdev->regmap)) {
 272                 dev_err(&pdev->dev, "regmap init failed\n");
 273                 return PTR_ERR(wdev->regmap);
 274         }
 275
 276         wdev->clk = devm_clk_get(&pdev->dev, NULL);
 277         if (IS_ERR(wdev->clk)) {
 278                 dev_err(&pdev->dev, "can't get Watchdog clock\n");
 279                 return PTR_ERR(wdev->clk);
 280         }
 281
 282         wdog                    = &wdev->wdog;
 283         wdog->info              = &imx2_wdt_info;
 284         wdog->ops               = &imx2_wdt_ops;
 285         wdog->min_timeout       = 1;
 286         wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
 287         wdog->parent            = &pdev->dev;
 288
 289         ret = platform_get_irq(pdev, 0);
 290         if (ret > 0)
 291                 if (!devm_request_irq(&pdev->dev, ret, imx2_wdt_isr, 0,
 292                                       dev_name(&pdev->dev), wdog))
 293                         wdog->info = &imx2_wdt_pretimeout_info;
 294
 295         ret = clk_prepare_enable(wdev->clk);
 296         if (ret)
 297                 return ret;
 298
 299         regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
 300         wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
 301
 302         wdev->ext_reset = of_property_read_bool(pdev->dev.of_node,
 303                                                 "fsl,ext-reset-output");
 304         wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
 305         if (wdog->timeout != timeout)
 306                 dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
 307                          timeout, wdog->timeout);
 308
 309         platform_set_drvdata(pdev, wdog);
 310         watchdog_set_drvdata(wdog, wdev);
 311         watchdog_set_nowayout(wdog, nowayout);
 312         watchdog_set_restart_priority(wdog, 128);
 313         watchdog_init_timeout(wdog, timeout, &pdev->dev);
 314
 315         if (imx2_wdt_is_running(wdev)) {
 316                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 317                 set_bit(WDOG_HW_RUNNING, &wdog->status);
 318         }
 319
 320         /*
 321          * Disable the watchdog power down counter at boot. Otherwise the power
 322          * down counter will pull down the #WDOG interrupt line for one clock
 323          * cycle.
 324          */
 325         regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
 326
 327         ret = watchdog_register_device(wdog);
 328         if (ret) {
 329                 dev_err(&pdev->dev, "cannot register watchdog device\n");
 330                 goto disable_clk;
 331         }
 332
 333         dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
 334                  wdog->timeout, nowayout);
 335
 336         return 0;
 337
 338 disable_clk:
 339         clk_disable_unprepare(wdev->clk);
 340         return ret;
 341 }
 342
 343 static int __exit imx2_wdt_remove(struct platform_device *pdev)
 344 {
 345         struct watchdog_device *wdog = platform_get_drvdata(pdev);
 346         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 347
 348         watchdog_unregister_device(wdog);
 349
 350         if (imx2_wdt_is_running(wdev)) {
 351                 imx2_wdt_ping(wdog);
 352                 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
 353         }
 354         return 0;
 355 }
 356
 357 static void imx2_wdt_shutdown(struct platform_device *pdev)
 358 {
 359         struct watchdog_device *wdog = platform_get_drvdata(pdev);
 360         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 361
 362         if (imx2_wdt_is_running(wdev)) {
 363                 /*
 364                  * We are running, configure max timeout before reboot
 365                  * will take place.
 366                  */
 367                 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 368                 imx2_wdt_ping(wdog);
 369                 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
 370         }
 371 }
 372
 373 #ifdef CONFIG_PM_SLEEP
 374 /* Disable watchdog if it is active or non-active but still running */
 375 static int imx2_wdt_suspend(struct device *dev)
 376 {
 377         struct watchdog_device *wdog = dev_get_drvdata(dev);
 378         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 379
 380         /* The watchdog IP block is running */
 381         if (imx2_wdt_is_running(wdev)) {
 382                 /*
 383                  * Don't update wdog->timeout, we'll restore the current value
 384                  * during resume.
 385                  */
 386                 __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 387                 imx2_wdt_ping(wdog);
 388         }
 389
 390         clk_disable_unprepare(wdev->clk);
 391
 392         return 0;
 393 }
 394
 395 /* Enable watchdog and configure it if necessary */
 396 static int imx2_wdt_resume(struct device *dev)
 397 {
 398         struct watchdog_device *wdog = dev_get_drvdata(dev);
 399         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 400         int ret;
 401
 402         ret = clk_prepare_enable(wdev->clk);
 403         if (ret)
 404                 return ret;
 405
 406         if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
 407                 /*
 408                  * If the watchdog is still active and resumes
 409                  * from deep sleep state, need to restart the
 410                  * watchdog again.
 411                  */
 412                 imx2_wdt_setup(wdog);
 413         }
 414         if (imx2_wdt_is_running(wdev)) {
 415                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 416                 imx2_wdt_ping(wdog);
 417         }
 418
 419         return 0;
 420 }
 421 #endif
 422
 423 static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
 424                          imx2_wdt_resume);
 425
 426 static const struct of_device_id imx2_wdt_dt_ids[] = {
 427         { .compatible = "fsl,imx21-wdt", },
 428         { /* sentinel */ }
 429 };
 430 MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
 431
 432 static struct platform_driver imx2_wdt_driver = {
 433         .remove         = __exit_p(imx2_wdt_remove),
 434         .shutdown       = imx2_wdt_shutdown,
 435         .driver         = {
 436                 .name   = DRIVER_NAME,
 437                 .pm     = &imx2_wdt_pm_ops,
 438                 .of_match_table = imx2_wdt_dt_ids,
 439         },
 440 };
 441
 442 module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
 443
 444 MODULE_AUTHOR("Wolfram Sang");
 445 MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
 446 MODULE_LICENSE("GPL v2");
 447 MODULE_ALIAS("platform:" DRIVER_NAME);