2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
12 * MX7ULP WDOG Register Map
23 #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
24 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
27 #define REFRESH_WORD0 0xA602 /* 1st refresh word */
28 #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
30 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
31 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
33 #define WDGCS1_WDGE (1<<7)
34 #define WDGCS1_WDGUPDATE (1<<5)
36 #define WDGCS2_FLG (1<<6)
38 #define WDG_BUS_CLK (0x0)
39 #define WDG_LPO_CLK (0x1)
40 #define WDG_32KHZ_CLK (0x2)
41 #define WDG_EXT_CLK (0x3)
43 DECLARE_GLOBAL_DATA_PTR
;
45 void hw_watchdog_set_timeout(u16 val
)
47 /* setting timeout value */
48 struct wdog_regs
*wdog
= (struct wdog_regs
*)WDOG_BASE_ADDR
;
50 writel(val
, &wdog
->toval
);
53 void hw_watchdog_reset(void)
55 struct wdog_regs
*wdog
= (struct wdog_regs
*)WDOG_BASE_ADDR
;
57 writel(REFRESH_WORD0
, &wdog
->cnt
);
58 writel(REFRESH_WORD1
, &wdog
->cnt
);
61 void hw_watchdog_init(void)
64 struct wdog_regs
*wdog
= (struct wdog_regs
*)WDOG_BASE_ADDR
;
66 writel(UNLOCK_WORD0
, &wdog
->cnt
);
67 writel(UNLOCK_WORD1
, &wdog
->cnt
);
69 val
= readb(&wdog
->cs2
);
71 writeb(val
, &wdog
->cs2
);
73 hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS
);
74 writel(0, &wdog
->win
);
76 writeb(WDG_LPO_CLK
, &wdog
->cs2
);/* setting 1-kHz clock source */
77 writeb((WDGCS1_WDGE
| WDGCS1_WDGUPDATE
), &wdog
->cs1
);/* enable counter running */
82 void reset_cpu(ulong addr
)
84 struct wdog_regs
*wdog
= (struct wdog_regs
*)WDOG_BASE_ADDR
;
86 writel(UNLOCK_WORD0
, &wdog
->cnt
);
87 writel(UNLOCK_WORD1
, &wdog
->cnt
);
89 hw_watchdog_set_timeout(5); /* 5ms timeout */
90 writel(0, &wdog
->win
);
92 writeb(WDG_LPO_CLK
, &wdog
->cs2
);/* setting 1-kHz clock source */
93 writeb(WDGCS1_WDGE
, &wdog
->cs1
);/* enable counter running */