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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/watchdog/xilinx_tb_wdt.c
2 * Copyright (c) 2011-2013 Xilinx Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/microblaze_intc.h>
10 #include <asm/processor.h>
13 #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */
14 #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */
15 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/
16 #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */
18 struct watchdog_regs
{
24 static struct watchdog_regs
*watchdog_base
=
25 (struct watchdog_regs
*)CONFIG_WATCHDOG_BASEADDR
;
27 void hw_watchdog_reset(void)
31 /* Read the current contents of TCSR0 */
32 reg
= readl(&watchdog_base
->twcsr0
);
34 /* Clear the watchdog WDS bit */
35 if (reg
& (XWT_CSR0_EWDT1_MASK
| XWT_CSRX_EWDT2_MASK
))
36 writel(reg
| XWT_CSR0_WDS_MASK
, &watchdog_base
->twcsr0
);
39 void hw_watchdog_disable(void)
43 /* Read the current contents of TCSR0 */
44 reg
= readl(&watchdog_base
->twcsr0
);
46 writel(reg
& ~XWT_CSR0_EWDT1_MASK
, &watchdog_base
->twcsr0
);
47 writel(~XWT_CSRX_EWDT2_MASK
, &watchdog_base
->twcsr1
);
49 puts("Watchdog disabled!\n");
52 static void hw_watchdog_isr(void *arg
)
57 void hw_watchdog_init(void)
61 writel((XWT_CSR0_WRS_MASK
| XWT_CSR0_WDS_MASK
| XWT_CSR0_EWDT1_MASK
),
62 &watchdog_base
->twcsr0
);
63 writel(XWT_CSRX_EWDT2_MASK
, &watchdog_base
->twcsr1
);
65 ret
= install_interrupt_handler(CONFIG_WATCHDOG_IRQ
,
66 hw_watchdog_isr
, NULL
);
68 puts("Watchdog IRQ registration failed.");