4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
23 #include "qemu/cutils.h"
25 #include "exec/exec-all.h"
26 #include "exec/target_page.h"
28 #include "hw/qdev-core.h"
29 #include "hw/qdev-properties.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #include "hw/boards.h"
32 #include "hw/xen/xen.h"
34 #include "sysemu/kvm.h"
35 #include "sysemu/sysemu.h"
36 #include "sysemu/tcg.h"
37 #include "qemu/timer.h"
38 #include "qemu/config-file.h"
39 #include "qemu/error-report.h"
40 #include "qemu/qemu-print.h"
41 #if defined(CONFIG_USER_ONLY)
43 #else /* !CONFIG_USER_ONLY */
45 #include "exec/memory.h"
46 #include "exec/ioport.h"
47 #include "sysemu/dma.h"
48 #include "sysemu/numa.h"
49 #include "sysemu/hw_accel.h"
50 #include "exec/address-spaces.h"
51 #include "sysemu/xen-mapcache.h"
52 #include "trace-root.h"
54 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
55 #include <linux/falloc.h>
59 #include "qemu/rcu_queue.h"
60 #include "qemu/main-loop.h"
61 #include "translate-all.h"
62 #include "sysemu/replay.h"
64 #include "exec/memory-internal.h"
65 #include "exec/ram_addr.h"
68 #include "migration/vmstate.h"
70 #include "qemu/range.h"
72 #include "qemu/mmap-alloc.h"
75 #include "monitor/monitor.h"
77 //#define DEBUG_SUBPAGE
79 #if !defined(CONFIG_USER_ONLY)
80 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
81 * are protected by the ramlist lock.
83 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
85 static MemoryRegion
*system_memory
;
86 static MemoryRegion
*system_io
;
88 AddressSpace address_space_io
;
89 AddressSpace address_space_memory
;
91 MemoryRegion io_mem_rom
, io_mem_notdirty
;
92 static MemoryRegion io_mem_unassigned
;
95 #ifdef TARGET_PAGE_BITS_VARY
97 bool target_page_bits_decided
;
100 CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
102 /* current CPU in the current thread. It is only valid inside
104 __thread CPUState
*current_cpu
;
105 /* 0 = Do not count executed instructions.
106 1 = Precise instruction counting.
107 2 = Adaptive rate instruction counting. */
110 uintptr_t qemu_host_page_size
;
111 intptr_t qemu_host_page_mask
;
113 bool set_preferred_target_page_bits(int bits
)
115 /* The target page size is the lowest common denominator for all
116 * the CPUs in the system, so we can only make it smaller, never
117 * larger. And we can't make it smaller once we've committed to
120 #ifdef TARGET_PAGE_BITS_VARY
121 assert(bits
>= TARGET_PAGE_BITS_MIN
);
122 if (target_page_bits
== 0 || target_page_bits
> bits
) {
123 if (target_page_bits_decided
) {
126 target_page_bits
= bits
;
132 #if !defined(CONFIG_USER_ONLY)
134 static void finalize_target_page_bits(void)
136 #ifdef TARGET_PAGE_BITS_VARY
137 if (target_page_bits
== 0) {
138 target_page_bits
= TARGET_PAGE_BITS_MIN
;
140 target_page_bits_decided
= true;
144 typedef struct PhysPageEntry PhysPageEntry
;
146 struct PhysPageEntry
{
147 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
149 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
153 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
155 /* Size of the L2 (and L3, etc) page tables. */
156 #define ADDR_SPACE_BITS 64
159 #define P_L2_SIZE (1 << P_L2_BITS)
161 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
163 typedef PhysPageEntry Node
[P_L2_SIZE
];
165 typedef struct PhysPageMap
{
168 unsigned sections_nb
;
169 unsigned sections_nb_alloc
;
171 unsigned nodes_nb_alloc
;
173 MemoryRegionSection
*sections
;
176 struct AddressSpaceDispatch
{
177 MemoryRegionSection
*mru_section
;
178 /* This is a multi-level map on the physical address space.
179 * The bottom level has pointers to MemoryRegionSections.
181 PhysPageEntry phys_map
;
185 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
186 typedef struct subpage_t
{
190 uint16_t sub_section
[];
193 #define PHYS_SECTION_UNASSIGNED 0
194 #define PHYS_SECTION_NOTDIRTY 1
195 #define PHYS_SECTION_ROM 2
196 #define PHYS_SECTION_WATCH 3
198 static void io_mem_init(void);
199 static void memory_map_init(void);
200 static void tcg_commit(MemoryListener
*listener
);
202 static MemoryRegion io_mem_watch
;
205 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
206 * @cpu: the CPU whose AddressSpace this is
207 * @as: the AddressSpace itself
208 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
209 * @tcg_as_listener: listener for tracking changes to the AddressSpace
211 struct CPUAddressSpace
{
214 struct AddressSpaceDispatch
*memory_dispatch
;
215 MemoryListener tcg_as_listener
;
218 struct DirtyBitmapSnapshot
{
221 unsigned long dirty
[];
226 #if !defined(CONFIG_USER_ONLY)
228 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
230 static unsigned alloc_hint
= 16;
231 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
232 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, alloc_hint
);
233 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, map
->nodes_nb
+ nodes
);
234 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
235 alloc_hint
= map
->nodes_nb_alloc
;
239 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
246 ret
= map
->nodes_nb
++;
248 assert(ret
!= PHYS_MAP_NODE_NIL
);
249 assert(ret
!= map
->nodes_nb_alloc
);
251 e
.skip
= leaf
? 0 : 1;
252 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
253 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
254 memcpy(&p
[i
], &e
, sizeof(e
));
259 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
260 hwaddr
*index
, hwaddr
*nb
, uint16_t leaf
,
264 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
266 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
267 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
269 p
= map
->nodes
[lp
->ptr
];
270 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
272 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
273 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
279 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
285 static void phys_page_set(AddressSpaceDispatch
*d
,
286 hwaddr index
, hwaddr nb
,
289 /* Wildly overreserve - it doesn't matter much. */
290 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
292 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
295 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
296 * and update our entry so we can skip it and go directly to the destination.
298 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
300 unsigned valid_ptr
= P_L2_SIZE
;
305 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
310 for (i
= 0; i
< P_L2_SIZE
; i
++) {
311 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
318 phys_page_compact(&p
[i
], nodes
);
322 /* We can only compress if there's only one child. */
327 assert(valid_ptr
< P_L2_SIZE
);
329 /* Don't compress if it won't fit in the # of bits we have. */
330 if (lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 3)) {
334 lp
->ptr
= p
[valid_ptr
].ptr
;
335 if (!p
[valid_ptr
].skip
) {
336 /* If our only child is a leaf, make this a leaf. */
337 /* By design, we should have made this node a leaf to begin with so we
338 * should never reach here.
339 * But since it's so simple to handle this, let's do it just in case we
344 lp
->skip
+= p
[valid_ptr
].skip
;
348 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
350 if (d
->phys_map
.skip
) {
351 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
355 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
358 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
359 * the section must cover the entire address space.
361 return int128_gethi(section
->size
) ||
362 range_covers_byte(section
->offset_within_address_space
,
363 int128_getlo(section
->size
), addr
);
366 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
368 PhysPageEntry lp
= d
->phys_map
, *p
;
369 Node
*nodes
= d
->map
.nodes
;
370 MemoryRegionSection
*sections
= d
->map
.sections
;
371 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
374 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
375 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
376 return §ions
[PHYS_SECTION_UNASSIGNED
];
379 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
382 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
383 return §ions
[lp
.ptr
];
385 return §ions
[PHYS_SECTION_UNASSIGNED
];
389 /* Called from RCU critical section */
390 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
392 bool resolve_subpage
)
394 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
397 if (!section
|| section
== &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] ||
398 !section_covers_addr(section
, addr
)) {
399 section
= phys_page_find(d
, addr
);
400 atomic_set(&d
->mru_section
, section
);
402 if (resolve_subpage
&& section
->mr
->subpage
) {
403 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
404 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
409 /* Called from RCU critical section */
410 static MemoryRegionSection
*
411 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
412 hwaddr
*plen
, bool resolve_subpage
)
414 MemoryRegionSection
*section
;
418 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
419 /* Compute offset within MemoryRegionSection */
420 addr
-= section
->offset_within_address_space
;
422 /* Compute offset within MemoryRegion */
423 *xlat
= addr
+ section
->offset_within_region
;
427 /* MMIO registers can be expected to perform full-width accesses based only
428 * on their address, without considering adjacent registers that could
429 * decode to completely different MemoryRegions. When such registers
430 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
431 * regions overlap wildly. For this reason we cannot clamp the accesses
434 * If the length is small (as is the case for address_space_ldl/stl),
435 * everything works fine. If the incoming length is large, however,
436 * the caller really has to do the clamping through memory_access_size.
438 if (memory_region_is_ram(mr
)) {
439 diff
= int128_sub(section
->size
, int128_make64(addr
));
440 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
446 * address_space_translate_iommu - translate an address through an IOMMU
447 * memory region and then through the target address space.
449 * @iommu_mr: the IOMMU memory region that we start the translation from
450 * @addr: the address to be translated through the MMU
451 * @xlat: the translated address offset within the destination memory region.
452 * It cannot be %NULL.
453 * @plen_out: valid read/write length of the translated address. It
455 * @page_mask_out: page mask for the translated address. This
456 * should only be meaningful for IOMMU translated
457 * addresses, since there may be huge pages that this bit
458 * would tell. It can be %NULL if we don't care about it.
459 * @is_write: whether the translation operation is for write
460 * @is_mmio: whether this can be MMIO, set true if it can
461 * @target_as: the address space targeted by the IOMMU
462 * @attrs: transaction attributes
464 * This function is called from RCU critical section. It is the common
465 * part of flatview_do_translate and address_space_translate_cached.
467 static MemoryRegionSection
address_space_translate_iommu(IOMMUMemoryRegion
*iommu_mr
,
470 hwaddr
*page_mask_out
,
473 AddressSpace
**target_as
,
476 MemoryRegionSection
*section
;
477 hwaddr page_mask
= (hwaddr
)-1;
481 IOMMUMemoryRegionClass
*imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
485 if (imrc
->attrs_to_index
) {
486 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
489 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
490 IOMMU_WO
: IOMMU_RO
, iommu_idx
);
492 if (!(iotlb
.perm
& (1 << is_write
))) {
496 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
497 | (addr
& iotlb
.addr_mask
));
498 page_mask
&= iotlb
.addr_mask
;
499 *plen_out
= MIN(*plen_out
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
500 *target_as
= iotlb
.target_as
;
502 section
= address_space_translate_internal(
503 address_space_to_dispatch(iotlb
.target_as
), addr
, xlat
,
506 iommu_mr
= memory_region_get_iommu(section
->mr
);
507 } while (unlikely(iommu_mr
));
510 *page_mask_out
= page_mask
;
515 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
519 * flatview_do_translate - translate an address in FlatView
521 * @fv: the flat view that we want to translate on
522 * @addr: the address to be translated in above address space
523 * @xlat: the translated address offset within memory region. It
525 * @plen_out: valid read/write length of the translated address. It
526 * can be @NULL when we don't care about it.
527 * @page_mask_out: page mask for the translated address. This
528 * should only be meaningful for IOMMU translated
529 * addresses, since there may be huge pages that this bit
530 * would tell. It can be @NULL if we don't care about it.
531 * @is_write: whether the translation operation is for write
532 * @is_mmio: whether this can be MMIO, set true if it can
533 * @target_as: the address space targeted by the IOMMU
534 * @attrs: memory transaction attributes
536 * This function is called from RCU critical section
538 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
542 hwaddr
*page_mask_out
,
545 AddressSpace
**target_as
,
548 MemoryRegionSection
*section
;
549 IOMMUMemoryRegion
*iommu_mr
;
550 hwaddr plen
= (hwaddr
)(-1);
556 section
= address_space_translate_internal(
557 flatview_to_dispatch(fv
), addr
, xlat
,
560 iommu_mr
= memory_region_get_iommu(section
->mr
);
561 if (unlikely(iommu_mr
)) {
562 return address_space_translate_iommu(iommu_mr
, xlat
,
563 plen_out
, page_mask_out
,
568 /* Not behind an IOMMU, use default page size. */
569 *page_mask_out
= ~TARGET_PAGE_MASK
;
575 /* Called from RCU critical section */
576 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
577 bool is_write
, MemTxAttrs attrs
)
579 MemoryRegionSection section
;
580 hwaddr xlat
, page_mask
;
583 * This can never be MMIO, and we don't really care about plen,
586 section
= flatview_do_translate(address_space_to_flatview(as
), addr
, &xlat
,
587 NULL
, &page_mask
, is_write
, false, &as
,
590 /* Illegal translation */
591 if (section
.mr
== &io_mem_unassigned
) {
595 /* Convert memory region offset into address space offset */
596 xlat
+= section
.offset_within_address_space
-
597 section
.offset_within_region
;
599 return (IOMMUTLBEntry
) {
601 .iova
= addr
& ~page_mask
,
602 .translated_addr
= xlat
& ~page_mask
,
603 .addr_mask
= page_mask
,
604 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
609 return (IOMMUTLBEntry
) {0};
612 /* Called from RCU critical section */
613 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
614 hwaddr
*plen
, bool is_write
,
618 MemoryRegionSection section
;
619 AddressSpace
*as
= NULL
;
621 /* This can be MMIO, so setup MMIO bit. */
622 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, NULL
,
623 is_write
, true, &as
, attrs
);
626 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
627 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
628 *plen
= MIN(page
, *plen
);
634 typedef struct TCGIOMMUNotifier
{
642 static void tcg_iommu_unmap_notify(IOMMUNotifier
*n
, IOMMUTLBEntry
*iotlb
)
644 TCGIOMMUNotifier
*notifier
= container_of(n
, TCGIOMMUNotifier
, n
);
646 if (!notifier
->active
) {
649 tlb_flush(notifier
->cpu
);
650 notifier
->active
= false;
651 /* We leave the notifier struct on the list to avoid reallocating it later.
652 * Generally the number of IOMMUs a CPU deals with will be small.
653 * In any case we can't unregister the iommu notifier from a notify
658 static void tcg_register_iommu_notifier(CPUState
*cpu
,
659 IOMMUMemoryRegion
*iommu_mr
,
662 /* Make sure this CPU has an IOMMU notifier registered for this
663 * IOMMU/IOMMU index combination, so that we can flush its TLB
664 * when the IOMMU tells us the mappings we've cached have changed.
666 MemoryRegion
*mr
= MEMORY_REGION(iommu_mr
);
667 TCGIOMMUNotifier
*notifier
;
670 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
671 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
672 if (notifier
->mr
== mr
&& notifier
->iommu_idx
== iommu_idx
) {
676 if (i
== cpu
->iommu_notifiers
->len
) {
677 /* Not found, add a new entry at the end of the array */
678 cpu
->iommu_notifiers
= g_array_set_size(cpu
->iommu_notifiers
, i
+ 1);
679 notifier
= g_new0(TCGIOMMUNotifier
, 1);
680 g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
) = notifier
;
683 notifier
->iommu_idx
= iommu_idx
;
685 /* Rather than trying to register interest in the specific part
686 * of the iommu's address space that we've accessed and then
687 * expand it later as subsequent accesses touch more of it, we
688 * just register interest in the whole thing, on the assumption
689 * that iommu reconfiguration will be rare.
691 iommu_notifier_init(¬ifier
->n
,
692 tcg_iommu_unmap_notify
,
693 IOMMU_NOTIFIER_UNMAP
,
697 memory_region_register_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
700 if (!notifier
->active
) {
701 notifier
->active
= true;
705 static void tcg_iommu_free_notifier_list(CPUState
*cpu
)
707 /* Destroy the CPU's notifier list */
709 TCGIOMMUNotifier
*notifier
;
711 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
712 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
713 memory_region_unregister_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
716 g_array_free(cpu
->iommu_notifiers
, true);
719 /* Called from RCU critical section */
720 MemoryRegionSection
*
721 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
722 hwaddr
*xlat
, hwaddr
*plen
,
723 MemTxAttrs attrs
, int *prot
)
725 MemoryRegionSection
*section
;
726 IOMMUMemoryRegion
*iommu_mr
;
727 IOMMUMemoryRegionClass
*imrc
;
730 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
733 section
= address_space_translate_internal(d
, addr
, &addr
, plen
, false);
735 iommu_mr
= memory_region_get_iommu(section
->mr
);
740 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
742 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
743 tcg_register_iommu_notifier(cpu
, iommu_mr
, iommu_idx
);
744 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
745 * doesn't short-cut its translation table walk.
747 iotlb
= imrc
->translate(iommu_mr
, addr
, IOMMU_NONE
, iommu_idx
);
748 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
749 | (addr
& iotlb
.addr_mask
));
750 /* Update the caller's prot bits to remove permissions the IOMMU
751 * is giving us a failure response for. If we get down to no
752 * permissions left at all we can give up now.
754 if (!(iotlb
.perm
& IOMMU_RO
)) {
755 *prot
&= ~(PAGE_READ
| PAGE_EXEC
);
757 if (!(iotlb
.perm
& IOMMU_WO
)) {
758 *prot
&= ~PAGE_WRITE
;
765 d
= flatview_to_dispatch(address_space_to_flatview(iotlb
.target_as
));
768 assert(!memory_region_is_iommu(section
->mr
));
773 return &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
];
777 #if !defined(CONFIG_USER_ONLY)
779 static int cpu_common_post_load(void *opaque
, int version_id
)
781 CPUState
*cpu
= opaque
;
783 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
784 version_id is increased. */
785 cpu
->interrupt_request
&= ~0x01;
788 /* loadvm has just updated the content of RAM, bypassing the
789 * usual mechanisms that ensure we flush TBs for writes to
790 * memory we've translated code from. So we must flush all TBs,
791 * which will now be stale.
798 static int cpu_common_pre_load(void *opaque
)
800 CPUState
*cpu
= opaque
;
802 cpu
->exception_index
= -1;
807 static bool cpu_common_exception_index_needed(void *opaque
)
809 CPUState
*cpu
= opaque
;
811 return tcg_enabled() && cpu
->exception_index
!= -1;
814 static const VMStateDescription vmstate_cpu_common_exception_index
= {
815 .name
= "cpu_common/exception_index",
817 .minimum_version_id
= 1,
818 .needed
= cpu_common_exception_index_needed
,
819 .fields
= (VMStateField
[]) {
820 VMSTATE_INT32(exception_index
, CPUState
),
821 VMSTATE_END_OF_LIST()
825 static bool cpu_common_crash_occurred_needed(void *opaque
)
827 CPUState
*cpu
= opaque
;
829 return cpu
->crash_occurred
;
832 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
833 .name
= "cpu_common/crash_occurred",
835 .minimum_version_id
= 1,
836 .needed
= cpu_common_crash_occurred_needed
,
837 .fields
= (VMStateField
[]) {
838 VMSTATE_BOOL(crash_occurred
, CPUState
),
839 VMSTATE_END_OF_LIST()
843 const VMStateDescription vmstate_cpu_common
= {
844 .name
= "cpu_common",
846 .minimum_version_id
= 1,
847 .pre_load
= cpu_common_pre_load
,
848 .post_load
= cpu_common_post_load
,
849 .fields
= (VMStateField
[]) {
850 VMSTATE_UINT32(halted
, CPUState
),
851 VMSTATE_UINT32(interrupt_request
, CPUState
),
852 VMSTATE_END_OF_LIST()
854 .subsections
= (const VMStateDescription
*[]) {
855 &vmstate_cpu_common_exception_index
,
856 &vmstate_cpu_common_crash_occurred
,
863 CPUState
*qemu_get_cpu(int index
)
868 if (cpu
->cpu_index
== index
) {
876 #if !defined(CONFIG_USER_ONLY)
877 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
878 const char *prefix
, MemoryRegion
*mr
)
880 CPUAddressSpace
*newas
;
881 AddressSpace
*as
= g_new0(AddressSpace
, 1);
885 as_name
= g_strdup_printf("%s-%d", prefix
, cpu
->cpu_index
);
886 address_space_init(as
, mr
, as_name
);
889 /* Target code should have set num_ases before calling us */
890 assert(asidx
< cpu
->num_ases
);
893 /* address space 0 gets the convenience alias */
897 /* KVM cannot currently support multiple address spaces. */
898 assert(asidx
== 0 || !kvm_enabled());
900 if (!cpu
->cpu_ases
) {
901 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
904 newas
= &cpu
->cpu_ases
[asidx
];
908 newas
->tcg_as_listener
.commit
= tcg_commit
;
909 memory_listener_register(&newas
->tcg_as_listener
, as
);
913 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
915 /* Return the AddressSpace corresponding to the specified index */
916 return cpu
->cpu_ases
[asidx
].as
;
920 void cpu_exec_unrealizefn(CPUState
*cpu
)
922 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
924 cpu_list_remove(cpu
);
926 if (cc
->vmsd
!= NULL
) {
927 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
929 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
930 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
932 #ifndef CONFIG_USER_ONLY
933 tcg_iommu_free_notifier_list(cpu
);
937 Property cpu_common_props
[] = {
938 #ifndef CONFIG_USER_ONLY
939 /* Create a memory property for softmmu CPU object,
940 * so users can wire up its memory. (This can't go in qom/cpu.c
941 * because that file is compiled only once for both user-mode
942 * and system builds.) The default if no link is set up is to use
943 * the system address space.
945 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
948 DEFINE_PROP_END_OF_LIST(),
951 void cpu_exec_initfn(CPUState
*cpu
)
956 #ifndef CONFIG_USER_ONLY
957 cpu
->thread_id
= qemu_get_thread_id();
958 cpu
->memory
= system_memory
;
959 object_ref(OBJECT(cpu
->memory
));
963 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
965 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
966 static bool tcg_target_initialized
;
970 if (tcg_enabled() && !tcg_target_initialized
) {
971 tcg_target_initialized
= true;
972 cc
->tcg_initialize();
976 #ifndef CONFIG_USER_ONLY
977 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
978 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
980 if (cc
->vmsd
!= NULL
) {
981 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
984 cpu
->iommu_notifiers
= g_array_new(false, true, sizeof(TCGIOMMUNotifier
*));
988 const char *parse_cpu_option(const char *cpu_option
)
992 gchar
**model_pieces
;
993 const char *cpu_type
;
995 model_pieces
= g_strsplit(cpu_option
, ",", 2);
996 if (!model_pieces
[0]) {
997 error_report("-cpu option cannot be empty");
1001 oc
= cpu_class_by_name(CPU_RESOLVING_TYPE
, model_pieces
[0]);
1003 error_report("unable to find CPU model '%s'", model_pieces
[0]);
1004 g_strfreev(model_pieces
);
1008 cpu_type
= object_class_get_name(oc
);
1010 cc
->parse_features(cpu_type
, model_pieces
[1], &error_fatal
);
1011 g_strfreev(model_pieces
);
1015 #if defined(CONFIG_USER_ONLY)
1016 void tb_invalidate_phys_addr(target_ulong addr
)
1019 tb_invalidate_phys_page_range(addr
, addr
+ 1, 0);
1023 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1025 tb_invalidate_phys_addr(pc
);
1028 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
)
1030 ram_addr_t ram_addr
;
1034 if (!tcg_enabled()) {
1039 mr
= address_space_translate(as
, addr
, &addr
, &l
, false, attrs
);
1040 if (!(memory_region_is_ram(mr
)
1041 || memory_region_is_romd(mr
))) {
1045 ram_addr
= memory_region_get_ram_addr(mr
) + addr
;
1046 tb_invalidate_phys_page_range(ram_addr
, ram_addr
+ 1, 0);
1050 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1053 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
1054 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
1056 /* Locks grabbed by tb_invalidate_phys_addr */
1057 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
1058 phys
| (pc
& ~TARGET_PAGE_MASK
), attrs
);
1063 #if defined(CONFIG_USER_ONLY)
1064 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1069 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1075 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1079 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1080 int flags
, CPUWatchpoint
**watchpoint
)
1085 /* Add a watchpoint. */
1086 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1087 int flags
, CPUWatchpoint
**watchpoint
)
1091 /* forbid ranges which are empty or run off the end of the address space */
1092 if (len
== 0 || (addr
+ len
- 1) < addr
) {
1093 error_report("tried to set invalid watchpoint at %"
1094 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
1097 wp
= g_malloc(sizeof(*wp
));
1103 /* keep all GDB-injected watchpoints in front */
1104 if (flags
& BP_GDB
) {
1105 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
1107 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
1110 tlb_flush_page(cpu
, addr
);
1117 /* Remove a specific watchpoint. */
1118 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1123 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1124 if (addr
== wp
->vaddr
&& len
== wp
->len
1125 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
1126 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1133 /* Remove a specific watchpoint by reference. */
1134 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1136 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
1138 tlb_flush_page(cpu
, watchpoint
->vaddr
);
1143 /* Remove all matching watchpoints. */
1144 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1146 CPUWatchpoint
*wp
, *next
;
1148 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
1149 if (wp
->flags
& mask
) {
1150 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1155 /* Return true if this watchpoint address matches the specified
1156 * access (ie the address range covered by the watchpoint overlaps
1157 * partially or completely with the address range covered by the
1160 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint
*wp
,
1164 /* We know the lengths are non-zero, but a little caution is
1165 * required to avoid errors in the case where the range ends
1166 * exactly at the top of the address space and so addr + len
1167 * wraps round to zero.
1169 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
1170 vaddr addrend
= addr
+ len
- 1;
1172 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
1177 /* Add a breakpoint. */
1178 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1179 CPUBreakpoint
**breakpoint
)
1183 bp
= g_malloc(sizeof(*bp
));
1188 /* keep all GDB-injected breakpoints in front */
1189 if (flags
& BP_GDB
) {
1190 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
1192 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
1195 breakpoint_invalidate(cpu
, pc
);
1203 /* Remove a specific breakpoint. */
1204 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
1208 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1209 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
1210 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1217 /* Remove a specific breakpoint by reference. */
1218 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
1220 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
1222 breakpoint_invalidate(cpu
, breakpoint
->pc
);
1227 /* Remove all matching breakpoints. */
1228 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
1230 CPUBreakpoint
*bp
, *next
;
1232 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
1233 if (bp
->flags
& mask
) {
1234 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1239 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1240 CPU loop after each instruction */
1241 void cpu_single_step(CPUState
*cpu
, int enabled
)
1243 if (cpu
->singlestep_enabled
!= enabled
) {
1244 cpu
->singlestep_enabled
= enabled
;
1245 if (kvm_enabled()) {
1246 kvm_update_guest_debug(cpu
, 0);
1248 /* must flush all the translated code to avoid inconsistencies */
1249 /* XXX: only flush what is necessary */
1255 void cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1262 fprintf(stderr
, "qemu: fatal: ");
1263 vfprintf(stderr
, fmt
, ap
);
1264 fprintf(stderr
, "\n");
1265 cpu_dump_state(cpu
, stderr
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1266 if (qemu_log_separate()) {
1268 qemu_log("qemu: fatal: ");
1269 qemu_log_vprintf(fmt
, ap2
);
1271 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1279 #if defined(CONFIG_USER_ONLY)
1281 struct sigaction act
;
1282 sigfillset(&act
.sa_mask
);
1283 act
.sa_handler
= SIG_DFL
;
1285 sigaction(SIGABRT
, &act
, NULL
);
1291 #if !defined(CONFIG_USER_ONLY)
1292 /* Called from RCU critical section */
1293 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1297 block
= atomic_rcu_read(&ram_list
.mru_block
);
1298 if (block
&& addr
- block
->offset
< block
->max_length
) {
1301 RAMBLOCK_FOREACH(block
) {
1302 if (addr
- block
->offset
< block
->max_length
) {
1307 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1311 /* It is safe to write mru_block outside the iothread lock. This
1316 * xxx removed from list
1320 * call_rcu(reclaim_ramblock, xxx);
1323 * atomic_rcu_set is not needed here. The block was already published
1324 * when it was placed into the list. Here we're just making an extra
1325 * copy of the pointer.
1327 ram_list
.mru_block
= block
;
1331 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1338 assert(tcg_enabled());
1339 end
= TARGET_PAGE_ALIGN(start
+ length
);
1340 start
&= TARGET_PAGE_MASK
;
1343 block
= qemu_get_ram_block(start
);
1344 assert(block
== qemu_get_ram_block(end
- 1));
1345 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1347 tlb_reset_dirty(cpu
, start1
, length
);
1352 /* Note: start and end must be within the same ram block. */
1353 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1357 DirtyMemoryBlocks
*blocks
;
1358 unsigned long end
, page
;
1365 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1366 page
= start
>> TARGET_PAGE_BITS
;
1370 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1372 while (page
< end
) {
1373 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1374 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1375 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1377 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1384 if (dirty
&& tcg_enabled()) {
1385 tlb_reset_dirty_range_all(start
, length
);
1391 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1392 (ram_addr_t start
, ram_addr_t length
, unsigned client
)
1394 DirtyMemoryBlocks
*blocks
;
1395 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1396 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1397 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1398 DirtyBitmapSnapshot
*snap
;
1399 unsigned long page
, end
, dest
;
1401 snap
= g_malloc0(sizeof(*snap
) +
1402 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1403 snap
->start
= first
;
1406 page
= first
>> TARGET_PAGE_BITS
;
1407 end
= last
>> TARGET_PAGE_BITS
;
1412 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1414 while (page
< end
) {
1415 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1416 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1417 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1419 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1420 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1421 offset
>>= BITS_PER_LEVEL
;
1423 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1424 blocks
->blocks
[idx
] + offset
,
1427 dest
+= num
>> BITS_PER_LEVEL
;
1432 if (tcg_enabled()) {
1433 tlb_reset_dirty_range_all(start
, length
);
1439 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1443 unsigned long page
, end
;
1445 assert(start
>= snap
->start
);
1446 assert(start
+ length
<= snap
->end
);
1448 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1449 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1451 while (page
< end
) {
1452 if (test_bit(page
, snap
->dirty
)) {
1460 /* Called from RCU critical section */
1461 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1462 MemoryRegionSection
*section
,
1464 hwaddr paddr
, hwaddr xlat
,
1466 target_ulong
*address
)
1471 if (memory_region_is_ram(section
->mr
)) {
1473 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1474 if (!section
->readonly
) {
1475 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1477 iotlb
|= PHYS_SECTION_ROM
;
1480 AddressSpaceDispatch
*d
;
1482 d
= flatview_to_dispatch(section
->fv
);
1483 iotlb
= section
- d
->map
.sections
;
1487 /* Make accesses to pages with watchpoints go via the
1488 watchpoint trap routines. */
1489 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1490 if (cpu_watchpoint_address_matches(wp
, vaddr
, TARGET_PAGE_SIZE
)) {
1491 /* Avoid trapping reads of pages with a write breakpoint. */
1492 if ((prot
& PAGE_WRITE
) || (wp
->flags
& BP_MEM_READ
)) {
1493 iotlb
= PHYS_SECTION_WATCH
+ paddr
;
1494 *address
|= TLB_MMIO
;
1502 #endif /* defined(CONFIG_USER_ONLY) */
1504 #if !defined(CONFIG_USER_ONLY)
1506 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1508 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1510 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
, bool shared
) =
1511 qemu_anon_ram_alloc
;
1514 * Set a custom physical guest memory alloator.
1515 * Accelerators with unusual needs may need this. Hopefully, we can
1516 * get rid of it eventually.
1518 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
, bool shared
))
1520 phys_mem_alloc
= alloc
;
1523 static uint16_t phys_section_add(PhysPageMap
*map
,
1524 MemoryRegionSection
*section
)
1526 /* The physical section number is ORed with a page-aligned
1527 * pointer to produce the iotlb entries. Thus it should
1528 * never overflow into the page-aligned value.
1530 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1532 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1533 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1534 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1535 map
->sections_nb_alloc
);
1537 map
->sections
[map
->sections_nb
] = *section
;
1538 memory_region_ref(section
->mr
);
1539 return map
->sections_nb
++;
1542 static void phys_section_destroy(MemoryRegion
*mr
)
1544 bool have_sub_page
= mr
->subpage
;
1546 memory_region_unref(mr
);
1548 if (have_sub_page
) {
1549 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1550 object_unref(OBJECT(&subpage
->iomem
));
1555 static void phys_sections_free(PhysPageMap
*map
)
1557 while (map
->sections_nb
> 0) {
1558 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1559 phys_section_destroy(section
->mr
);
1561 g_free(map
->sections
);
1565 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1567 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1569 hwaddr base
= section
->offset_within_address_space
1571 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1572 MemoryRegionSection subsection
= {
1573 .offset_within_address_space
= base
,
1574 .size
= int128_make64(TARGET_PAGE_SIZE
),
1578 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1580 if (!(existing
->mr
->subpage
)) {
1581 subpage
= subpage_init(fv
, base
);
1583 subsection
.mr
= &subpage
->iomem
;
1584 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1585 phys_section_add(&d
->map
, &subsection
));
1587 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1589 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1590 end
= start
+ int128_get64(section
->size
) - 1;
1591 subpage_register(subpage
, start
, end
,
1592 phys_section_add(&d
->map
, section
));
1596 static void register_multipage(FlatView
*fv
,
1597 MemoryRegionSection
*section
)
1599 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1600 hwaddr start_addr
= section
->offset_within_address_space
;
1601 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1602 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1606 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1610 * The range in *section* may look like this:
1614 * where s stands for subpage and P for page.
1616 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1618 MemoryRegionSection remain
= *section
;
1619 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1621 /* register first subpage */
1622 if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1623 uint64_t left
= TARGET_PAGE_ALIGN(remain
.offset_within_address_space
)
1624 - remain
.offset_within_address_space
;
1626 MemoryRegionSection now
= remain
;
1627 now
.size
= int128_min(int128_make64(left
), now
.size
);
1628 register_subpage(fv
, &now
);
1629 if (int128_eq(remain
.size
, now
.size
)) {
1632 remain
.size
= int128_sub(remain
.size
, now
.size
);
1633 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1634 remain
.offset_within_region
+= int128_get64(now
.size
);
1637 /* register whole pages */
1638 if (int128_ge(remain
.size
, page_size
)) {
1639 MemoryRegionSection now
= remain
;
1640 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1641 register_multipage(fv
, &now
);
1642 if (int128_eq(remain
.size
, now
.size
)) {
1645 remain
.size
= int128_sub(remain
.size
, now
.size
);
1646 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1647 remain
.offset_within_region
+= int128_get64(now
.size
);
1650 /* register last subpage */
1651 register_subpage(fv
, &remain
);
1654 void qemu_flush_coalesced_mmio_buffer(void)
1657 kvm_flush_coalesced_mmio_buffer();
1660 void qemu_mutex_lock_ramlist(void)
1662 qemu_mutex_lock(&ram_list
.mutex
);
1665 void qemu_mutex_unlock_ramlist(void)
1667 qemu_mutex_unlock(&ram_list
.mutex
);
1670 void ram_block_dump(Monitor
*mon
)
1676 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1677 "Block Name", "PSize", "Offset", "Used", "Total");
1678 RAMBLOCK_FOREACH(block
) {
1679 psize
= size_to_str(block
->page_size
);
1680 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1681 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1682 (uint64_t)block
->offset
,
1683 (uint64_t)block
->used_length
,
1684 (uint64_t)block
->max_length
);
1692 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1693 * may or may not name the same files / on the same filesystem now as
1694 * when we actually open and map them. Iterate over the file
1695 * descriptors instead, and use qemu_fd_getpagesize().
1697 static int find_min_backend_pagesize(Object
*obj
, void *opaque
)
1699 long *hpsize_min
= opaque
;
1701 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1702 HostMemoryBackend
*backend
= MEMORY_BACKEND(obj
);
1703 long hpsize
= host_memory_backend_pagesize(backend
);
1705 if (host_memory_backend_is_mapped(backend
) && (hpsize
< *hpsize_min
)) {
1706 *hpsize_min
= hpsize
;
1713 static int find_max_backend_pagesize(Object
*obj
, void *opaque
)
1715 long *hpsize_max
= opaque
;
1717 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1718 HostMemoryBackend
*backend
= MEMORY_BACKEND(obj
);
1719 long hpsize
= host_memory_backend_pagesize(backend
);
1721 if (host_memory_backend_is_mapped(backend
) && (hpsize
> *hpsize_max
)) {
1722 *hpsize_max
= hpsize
;
1730 * TODO: We assume right now that all mapped host memory backends are
1731 * used as RAM, however some might be used for different purposes.
1733 long qemu_minrampagesize(void)
1735 long hpsize
= LONG_MAX
;
1736 long mainrampagesize
;
1737 Object
*memdev_root
;
1739 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1741 /* it's possible we have memory-backend objects with
1742 * hugepage-backed RAM. these may get mapped into system
1743 * address space via -numa parameters or memory hotplug
1744 * hooks. we want to take these into account, but we
1745 * also want to make sure these supported hugepage
1746 * sizes are applicable across the entire range of memory
1747 * we may boot from, so we take the min across all
1748 * backends, and assume normal pages in cases where a
1749 * backend isn't backed by hugepages.
1751 memdev_root
= object_resolve_path("/objects", NULL
);
1753 object_child_foreach(memdev_root
, find_min_backend_pagesize
, &hpsize
);
1755 if (hpsize
== LONG_MAX
) {
1756 /* No additional memory regions found ==> Report main RAM page size */
1757 return mainrampagesize
;
1760 /* If NUMA is disabled or the NUMA nodes are not backed with a
1761 * memory-backend, then there is at least one node using "normal" RAM,
1762 * so if its page size is smaller we have got to report that size instead.
1764 if (hpsize
> mainrampagesize
&&
1765 (nb_numa_nodes
== 0 || numa_info
[0].node_memdev
== NULL
)) {
1768 error_report("Huge page support disabled (n/a for main memory).");
1771 return mainrampagesize
;
1777 long qemu_maxrampagesize(void)
1779 long pagesize
= qemu_mempath_getpagesize(mem_path
);
1780 Object
*memdev_root
= object_resolve_path("/objects", NULL
);
1783 object_child_foreach(memdev_root
, find_max_backend_pagesize
,
1789 long qemu_minrampagesize(void)
1791 return getpagesize();
1793 long qemu_maxrampagesize(void)
1795 return getpagesize();
1800 static int64_t get_file_size(int fd
)
1802 int64_t size
= lseek(fd
, 0, SEEK_END
);
1809 static int file_ram_open(const char *path
,
1810 const char *region_name
,
1815 char *sanitized_name
;
1821 fd
= open(path
, O_RDWR
);
1823 /* @path names an existing file, use it */
1826 if (errno
== ENOENT
) {
1827 /* @path names a file that doesn't exist, create it */
1828 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1833 } else if (errno
== EISDIR
) {
1834 /* @path names a directory, create a file there */
1835 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1836 sanitized_name
= g_strdup(region_name
);
1837 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1843 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1845 g_free(sanitized_name
);
1847 fd
= mkstemp(filename
);
1855 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1856 error_setg_errno(errp
, errno
,
1857 "can't open backing store %s for guest RAM",
1862 * Try again on EINTR and EEXIST. The latter happens when
1863 * something else creates the file between our two open().
1870 static void *file_ram_alloc(RAMBlock
*block
,
1878 block
->page_size
= qemu_fd_getpagesize(fd
);
1879 if (block
->mr
->align
% block
->page_size
) {
1880 error_setg(errp
, "alignment 0x%" PRIx64
1881 " must be multiples of page size 0x%zx",
1882 block
->mr
->align
, block
->page_size
);
1884 } else if (block
->mr
->align
&& !is_power_of_2(block
->mr
->align
)) {
1885 error_setg(errp
, "alignment 0x%" PRIx64
1886 " must be a power of two", block
->mr
->align
);
1889 block
->mr
->align
= MAX(block
->page_size
, block
->mr
->align
);
1890 #if defined(__s390x__)
1891 if (kvm_enabled()) {
1892 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1896 if (memory
< block
->page_size
) {
1897 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1898 "or larger than page size 0x%zx",
1899 memory
, block
->page_size
);
1903 memory
= ROUND_UP(memory
, block
->page_size
);
1906 * ftruncate is not supported by hugetlbfs in older
1907 * hosts, so don't bother bailing out on errors.
1908 * If anything goes wrong with it under other filesystems,
1911 * Do not truncate the non-empty backend file to avoid corrupting
1912 * the existing data in the file. Disabling shrinking is not
1913 * enough. For example, the current vNVDIMM implementation stores
1914 * the guest NVDIMM labels at the end of the backend file. If the
1915 * backend file is later extended, QEMU will not be able to find
1916 * those labels. Therefore, extending the non-empty backend file
1917 * is disabled as well.
1919 if (truncate
&& ftruncate(fd
, memory
)) {
1920 perror("ftruncate");
1923 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1924 block
->flags
& RAM_SHARED
, block
->flags
& RAM_PMEM
);
1925 if (area
== MAP_FAILED
) {
1926 error_setg_errno(errp
, errno
,
1927 "unable to map backing store for guest RAM");
1932 os_mem_prealloc(fd
, area
, memory
, smp_cpus
, errp
);
1933 if (errp
&& *errp
) {
1934 qemu_ram_munmap(fd
, area
, memory
);
1944 /* Allocate space within the ram_addr_t space that governs the
1946 * Called with the ramlist lock held.
1948 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1950 RAMBlock
*block
, *next_block
;
1951 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1953 assert(size
!= 0); /* it would hand out same offset multiple times */
1955 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1959 RAMBLOCK_FOREACH(block
) {
1960 ram_addr_t candidate
, next
= RAM_ADDR_MAX
;
1962 /* Align blocks to start on a 'long' in the bitmap
1963 * which makes the bitmap sync'ing take the fast path.
1965 candidate
= block
->offset
+ block
->max_length
;
1966 candidate
= ROUND_UP(candidate
, BITS_PER_LONG
<< TARGET_PAGE_BITS
);
1968 /* Search for the closest following block
1971 RAMBLOCK_FOREACH(next_block
) {
1972 if (next_block
->offset
>= candidate
) {
1973 next
= MIN(next
, next_block
->offset
);
1977 /* If it fits remember our place and remember the size
1978 * of gap, but keep going so that we might find a smaller
1979 * gap to fill so avoiding fragmentation.
1981 if (next
- candidate
>= size
&& next
- candidate
< mingap
) {
1983 mingap
= next
- candidate
;
1986 trace_find_ram_offset_loop(size
, candidate
, offset
, next
, mingap
);
1989 if (offset
== RAM_ADDR_MAX
) {
1990 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
1995 trace_find_ram_offset(size
, offset
);
2000 static unsigned long last_ram_page(void)
2003 ram_addr_t last
= 0;
2006 RAMBLOCK_FOREACH(block
) {
2007 last
= MAX(last
, block
->offset
+ block
->max_length
);
2010 return last
>> TARGET_PAGE_BITS
;
2013 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
2017 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
2018 if (!machine_dump_guest_core(current_machine
)) {
2019 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
2021 perror("qemu_madvise");
2022 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
2023 "but dump_guest_core=off specified\n");
2028 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
2033 void *qemu_ram_get_host_addr(RAMBlock
*rb
)
2038 ram_addr_t
qemu_ram_get_offset(RAMBlock
*rb
)
2043 ram_addr_t
qemu_ram_get_used_length(RAMBlock
*rb
)
2045 return rb
->used_length
;
2048 bool qemu_ram_is_shared(RAMBlock
*rb
)
2050 return rb
->flags
& RAM_SHARED
;
2053 /* Note: Only set at the start of postcopy */
2054 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
)
2056 return rb
->flags
& RAM_UF_ZEROPAGE
;
2059 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
)
2061 rb
->flags
|= RAM_UF_ZEROPAGE
;
2064 bool qemu_ram_is_migratable(RAMBlock
*rb
)
2066 return rb
->flags
& RAM_MIGRATABLE
;
2069 void qemu_ram_set_migratable(RAMBlock
*rb
)
2071 rb
->flags
|= RAM_MIGRATABLE
;
2074 void qemu_ram_unset_migratable(RAMBlock
*rb
)
2076 rb
->flags
&= ~RAM_MIGRATABLE
;
2079 /* Called with iothread lock held. */
2080 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
2085 assert(!new_block
->idstr
[0]);
2088 char *id
= qdev_get_dev_path(dev
);
2090 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
2094 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
2097 RAMBLOCK_FOREACH(block
) {
2098 if (block
!= new_block
&&
2099 !strcmp(block
->idstr
, new_block
->idstr
)) {
2100 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
2108 /* Called with iothread lock held. */
2109 void qemu_ram_unset_idstr(RAMBlock
*block
)
2111 /* FIXME: arch_init.c assumes that this is not called throughout
2112 * migration. Ignore the problem since hot-unplug during migration
2113 * does not work anyway.
2116 memset(block
->idstr
, 0, sizeof(block
->idstr
));
2120 size_t qemu_ram_pagesize(RAMBlock
*rb
)
2122 return rb
->page_size
;
2125 /* Returns the largest size of page in use */
2126 size_t qemu_ram_pagesize_largest(void)
2131 RAMBLOCK_FOREACH(block
) {
2132 largest
= MAX(largest
, qemu_ram_pagesize(block
));
2138 static int memory_try_enable_merging(void *addr
, size_t len
)
2140 if (!machine_mem_merge(current_machine
)) {
2141 /* disabled by the user */
2145 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
2148 /* Only legal before guest might have detected the memory size: e.g. on
2149 * incoming migration, or right after reset.
2151 * As memory core doesn't know how is memory accessed, it is up to
2152 * resize callback to update device state and/or add assertions to detect
2153 * misuse, if necessary.
2155 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
2159 newsize
= HOST_PAGE_ALIGN(newsize
);
2161 if (block
->used_length
== newsize
) {
2165 if (!(block
->flags
& RAM_RESIZEABLE
)) {
2166 error_setg_errno(errp
, EINVAL
,
2167 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2168 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
2169 newsize
, block
->used_length
);
2173 if (block
->max_length
< newsize
) {
2174 error_setg_errno(errp
, EINVAL
,
2175 "Length too large: %s: 0x" RAM_ADDR_FMT
2176 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
2177 newsize
, block
->max_length
);
2181 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
2182 block
->used_length
= newsize
;
2183 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
2185 memory_region_set_size(block
->mr
, newsize
);
2186 if (block
->resized
) {
2187 block
->resized(block
->idstr
, newsize
, block
->host
);
2192 /* Called with ram_list.mutex held */
2193 static void dirty_memory_extend(ram_addr_t old_ram_size
,
2194 ram_addr_t new_ram_size
)
2196 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
2197 DIRTY_MEMORY_BLOCK_SIZE
);
2198 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
2199 DIRTY_MEMORY_BLOCK_SIZE
);
2202 /* Only need to extend if block count increased */
2203 if (new_num_blocks
<= old_num_blocks
) {
2207 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
2208 DirtyMemoryBlocks
*old_blocks
;
2209 DirtyMemoryBlocks
*new_blocks
;
2212 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
2213 new_blocks
= g_malloc(sizeof(*new_blocks
) +
2214 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
2216 if (old_num_blocks
) {
2217 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
2218 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
2221 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
2222 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
2225 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
2228 g_free_rcu(old_blocks
, rcu
);
2233 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
, bool shared
)
2236 RAMBlock
*last_block
= NULL
;
2237 ram_addr_t old_ram_size
, new_ram_size
;
2240 old_ram_size
= last_ram_page();
2242 qemu_mutex_lock_ramlist();
2243 new_block
->offset
= find_ram_offset(new_block
->max_length
);
2245 if (!new_block
->host
) {
2246 if (xen_enabled()) {
2247 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
2248 new_block
->mr
, &err
);
2250 error_propagate(errp
, err
);
2251 qemu_mutex_unlock_ramlist();
2255 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
2256 &new_block
->mr
->align
, shared
);
2257 if (!new_block
->host
) {
2258 error_setg_errno(errp
, errno
,
2259 "cannot set up guest memory '%s'",
2260 memory_region_name(new_block
->mr
));
2261 qemu_mutex_unlock_ramlist();
2264 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
2268 new_ram_size
= MAX(old_ram_size
,
2269 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
2270 if (new_ram_size
> old_ram_size
) {
2271 dirty_memory_extend(old_ram_size
, new_ram_size
);
2273 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2274 * QLIST (which has an RCU-friendly variant) does not have insertion at
2275 * tail, so save the last element in last_block.
2277 RAMBLOCK_FOREACH(block
) {
2279 if (block
->max_length
< new_block
->max_length
) {
2284 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
2285 } else if (last_block
) {
2286 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
2287 } else { /* list is empty */
2288 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
2290 ram_list
.mru_block
= NULL
;
2292 /* Write list before version */
2295 qemu_mutex_unlock_ramlist();
2297 cpu_physical_memory_set_dirty_range(new_block
->offset
,
2298 new_block
->used_length
,
2301 if (new_block
->host
) {
2302 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
2303 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
2304 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2305 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
2306 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
2311 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
2312 uint32_t ram_flags
, int fd
,
2315 RAMBlock
*new_block
;
2316 Error
*local_err
= NULL
;
2319 /* Just support these ram flags by now. */
2320 assert((ram_flags
& ~(RAM_SHARED
| RAM_PMEM
)) == 0);
2322 if (xen_enabled()) {
2323 error_setg(errp
, "-mem-path not supported with Xen");
2327 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2329 "host lacks kvm mmu notifiers, -mem-path unsupported");
2333 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
2335 * file_ram_alloc() needs to allocate just like
2336 * phys_mem_alloc, but we haven't bothered to provide
2340 "-mem-path not supported with this accelerator");
2344 size
= HOST_PAGE_ALIGN(size
);
2345 file_size
= get_file_size(fd
);
2346 if (file_size
> 0 && file_size
< size
) {
2347 error_setg(errp
, "backing store %s size 0x%" PRIx64
2348 " does not match 'size' option 0x" RAM_ADDR_FMT
,
2349 mem_path
, file_size
, size
);
2353 new_block
= g_malloc0(sizeof(*new_block
));
2355 new_block
->used_length
= size
;
2356 new_block
->max_length
= size
;
2357 new_block
->flags
= ram_flags
;
2358 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
2359 if (!new_block
->host
) {
2364 ram_block_add(new_block
, &local_err
, ram_flags
& RAM_SHARED
);
2367 error_propagate(errp
, local_err
);
2375 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2376 uint32_t ram_flags
, const char *mem_path
,
2383 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2388 block
= qemu_ram_alloc_from_fd(size
, mr
, ram_flags
, fd
, errp
);
2402 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2403 void (*resized
)(const char*,
2406 void *host
, bool resizeable
, bool share
,
2407 MemoryRegion
*mr
, Error
**errp
)
2409 RAMBlock
*new_block
;
2410 Error
*local_err
= NULL
;
2412 size
= HOST_PAGE_ALIGN(size
);
2413 max_size
= HOST_PAGE_ALIGN(max_size
);
2414 new_block
= g_malloc0(sizeof(*new_block
));
2416 new_block
->resized
= resized
;
2417 new_block
->used_length
= size
;
2418 new_block
->max_length
= max_size
;
2419 assert(max_size
>= size
);
2421 new_block
->page_size
= getpagesize();
2422 new_block
->host
= host
;
2424 new_block
->flags
|= RAM_PREALLOC
;
2427 new_block
->flags
|= RAM_RESIZEABLE
;
2429 ram_block_add(new_block
, &local_err
, share
);
2432 error_propagate(errp
, local_err
);
2438 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2439 MemoryRegion
*mr
, Error
**errp
)
2441 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false,
2445 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, bool share
,
2446 MemoryRegion
*mr
, Error
**errp
)
2448 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false,
2452 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2453 void (*resized
)(const char*,
2456 MemoryRegion
*mr
, Error
**errp
)
2458 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true,
2462 static void reclaim_ramblock(RAMBlock
*block
)
2464 if (block
->flags
& RAM_PREALLOC
) {
2466 } else if (xen_enabled()) {
2467 xen_invalidate_map_cache_entry(block
->host
);
2469 } else if (block
->fd
>= 0) {
2470 qemu_ram_munmap(block
->fd
, block
->host
, block
->max_length
);
2474 qemu_anon_ram_free(block
->host
, block
->max_length
);
2479 void qemu_ram_free(RAMBlock
*block
)
2486 ram_block_notify_remove(block
->host
, block
->max_length
);
2489 qemu_mutex_lock_ramlist();
2490 QLIST_REMOVE_RCU(block
, next
);
2491 ram_list
.mru_block
= NULL
;
2492 /* Write list before version */
2495 call_rcu(block
, reclaim_ramblock
, rcu
);
2496 qemu_mutex_unlock_ramlist();
2500 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2507 RAMBLOCK_FOREACH(block
) {
2508 offset
= addr
- block
->offset
;
2509 if (offset
< block
->max_length
) {
2510 vaddr
= ramblock_ptr(block
, offset
);
2511 if (block
->flags
& RAM_PREALLOC
) {
2513 } else if (xen_enabled()) {
2517 if (block
->fd
>= 0) {
2518 flags
|= (block
->flags
& RAM_SHARED
?
2519 MAP_SHARED
: MAP_PRIVATE
);
2520 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2521 flags
, block
->fd
, offset
);
2524 * Remap needs to match alloc. Accelerators that
2525 * set phys_mem_alloc never remap. If they did,
2526 * we'd need a remap hook here.
2528 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2530 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2531 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2534 if (area
!= vaddr
) {
2535 error_report("Could not remap addr: "
2536 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"",
2540 memory_try_enable_merging(vaddr
, length
);
2541 qemu_ram_setup_dump(vaddr
, length
);
2546 #endif /* !_WIN32 */
2548 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2549 * This should not be used for general purpose DMA. Use address_space_map
2550 * or address_space_rw instead. For local memory (e.g. video ram) that the
2551 * device owns, use memory_region_get_ram_ptr.
2553 * Called within RCU critical section.
2555 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2557 RAMBlock
*block
= ram_block
;
2559 if (block
== NULL
) {
2560 block
= qemu_get_ram_block(addr
);
2561 addr
-= block
->offset
;
2564 if (xen_enabled() && block
->host
== NULL
) {
2565 /* We need to check if the requested address is in the RAM
2566 * because we don't want to map the entire memory in QEMU.
2567 * In that case just map until the end of the page.
2569 if (block
->offset
== 0) {
2570 return xen_map_cache(addr
, 0, 0, false);
2573 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2575 return ramblock_ptr(block
, addr
);
2578 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2579 * but takes a size argument.
2581 * Called within RCU critical section.
2583 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2584 hwaddr
*size
, bool lock
)
2586 RAMBlock
*block
= ram_block
;
2591 if (block
== NULL
) {
2592 block
= qemu_get_ram_block(addr
);
2593 addr
-= block
->offset
;
2595 *size
= MIN(*size
, block
->max_length
- addr
);
2597 if (xen_enabled() && block
->host
== NULL
) {
2598 /* We need to check if the requested address is in the RAM
2599 * because we don't want to map the entire memory in QEMU.
2600 * In that case just map the requested area.
2602 if (block
->offset
== 0) {
2603 return xen_map_cache(addr
, *size
, lock
, lock
);
2606 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2609 return ramblock_ptr(block
, addr
);
2612 /* Return the offset of a hostpointer within a ramblock */
2613 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
)
2615 ram_addr_t res
= (uint8_t *)host
- (uint8_t *)rb
->host
;
2616 assert((uintptr_t)host
>= (uintptr_t)rb
->host
);
2617 assert(res
< rb
->max_length
);
2623 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2626 * ptr: Host pointer to look up
2627 * round_offset: If true round the result offset down to a page boundary
2628 * *ram_addr: set to result ram_addr
2629 * *offset: set to result offset within the RAMBlock
2631 * Returns: RAMBlock (or NULL if not found)
2633 * By the time this function returns, the returned pointer is not protected
2634 * by RCU anymore. If the caller is not within an RCU critical section and
2635 * does not hold the iothread lock, it must have other means of protecting the
2636 * pointer, such as a reference to the region that includes the incoming
2639 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2643 uint8_t *host
= ptr
;
2645 if (xen_enabled()) {
2646 ram_addr_t ram_addr
;
2648 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2649 block
= qemu_get_ram_block(ram_addr
);
2651 *offset
= ram_addr
- block
->offset
;
2658 block
= atomic_rcu_read(&ram_list
.mru_block
);
2659 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2663 RAMBLOCK_FOREACH(block
) {
2664 /* This case append when the block is not mapped. */
2665 if (block
->host
== NULL
) {
2668 if (host
- block
->host
< block
->max_length
) {
2677 *offset
= (host
- block
->host
);
2679 *offset
&= TARGET_PAGE_MASK
;
2686 * Finds the named RAMBlock
2688 * name: The name of RAMBlock to find
2690 * Returns: RAMBlock (or NULL if not found)
2692 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2696 RAMBLOCK_FOREACH(block
) {
2697 if (!strcmp(name
, block
->idstr
)) {
2705 /* Some of the softmmu routines need to translate from a host pointer
2706 (typically a TLB entry) back to a ram offset. */
2707 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2712 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2714 return RAM_ADDR_INVALID
;
2717 return block
->offset
+ offset
;
2720 /* Called within RCU critical section. */
2721 void memory_notdirty_write_prepare(NotDirtyInfo
*ndi
,
2724 ram_addr_t ram_addr
,
2728 ndi
->ram_addr
= ram_addr
;
2729 ndi
->mem_vaddr
= mem_vaddr
;
2733 assert(tcg_enabled());
2734 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2735 ndi
->pages
= page_collection_lock(ram_addr
, ram_addr
+ size
);
2736 tb_invalidate_phys_page_fast(ndi
->pages
, ram_addr
, size
);
2740 /* Called within RCU critical section. */
2741 void memory_notdirty_write_complete(NotDirtyInfo
*ndi
)
2744 assert(tcg_enabled());
2745 page_collection_unlock(ndi
->pages
);
2749 /* Set both VGA and migration bits for simplicity and to remove
2750 * the notdirty callback faster.
2752 cpu_physical_memory_set_dirty_range(ndi
->ram_addr
, ndi
->size
,
2753 DIRTY_CLIENTS_NOCODE
);
2754 /* we remove the notdirty callback only if the code has been
2756 if (!cpu_physical_memory_is_clean(ndi
->ram_addr
)) {
2757 tlb_set_dirty(ndi
->cpu
, ndi
->mem_vaddr
);
2761 /* Called within RCU critical section. */
2762 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2763 uint64_t val
, unsigned size
)
2767 memory_notdirty_write_prepare(&ndi
, current_cpu
, current_cpu
->mem_io_vaddr
,
2770 stn_p(qemu_map_ram_ptr(NULL
, ram_addr
), size
, val
);
2771 memory_notdirty_write_complete(&ndi
);
2774 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2775 unsigned size
, bool is_write
,
2781 static const MemoryRegionOps notdirty_mem_ops
= {
2782 .write
= notdirty_mem_write
,
2783 .valid
.accepts
= notdirty_mem_accepts
,
2784 .endianness
= DEVICE_NATIVE_ENDIAN
,
2786 .min_access_size
= 1,
2787 .max_access_size
= 8,
2791 .min_access_size
= 1,
2792 .max_access_size
= 8,
2797 /* Generate a debug exception if a watchpoint has been hit. */
2798 static void check_watchpoint(int offset
, int len
, MemTxAttrs attrs
, int flags
)
2800 CPUState
*cpu
= current_cpu
;
2801 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2805 assert(tcg_enabled());
2806 if (cpu
->watchpoint_hit
) {
2807 /* We re-entered the check after replacing the TB. Now raise
2808 * the debug interrupt so that is will trigger after the
2809 * current instruction. */
2810 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2813 vaddr
= (cpu
->mem_io_vaddr
& TARGET_PAGE_MASK
) + offset
;
2814 vaddr
= cc
->adjust_watchpoint_address(cpu
, vaddr
, len
);
2815 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2816 if (cpu_watchpoint_address_matches(wp
, vaddr
, len
)
2817 && (wp
->flags
& flags
)) {
2818 if (flags
== BP_MEM_READ
) {
2819 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2821 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2823 wp
->hitaddr
= vaddr
;
2824 wp
->hitattrs
= attrs
;
2825 if (!cpu
->watchpoint_hit
) {
2826 if (wp
->flags
& BP_CPU
&&
2827 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2828 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2831 cpu
->watchpoint_hit
= wp
;
2834 tb_check_watchpoint(cpu
);
2835 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2836 cpu
->exception_index
= EXCP_DEBUG
;
2840 /* Force execution of one insn next time. */
2841 cpu
->cflags_next_tb
= 1 | curr_cflags();
2843 cpu_loop_exit_noexc(cpu
);
2847 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2852 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2853 so these check for a hit then pass through to the normal out-of-line
2855 static MemTxResult
watch_mem_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
2856 unsigned size
, MemTxAttrs attrs
)
2860 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2861 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2863 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_READ
);
2866 data
= address_space_ldub(as
, addr
, attrs
, &res
);
2869 data
= address_space_lduw(as
, addr
, attrs
, &res
);
2872 data
= address_space_ldl(as
, addr
, attrs
, &res
);
2875 data
= address_space_ldq(as
, addr
, attrs
, &res
);
2883 static MemTxResult
watch_mem_write(void *opaque
, hwaddr addr
,
2884 uint64_t val
, unsigned size
,
2888 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2889 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2891 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_WRITE
);
2894 address_space_stb(as
, addr
, val
, attrs
, &res
);
2897 address_space_stw(as
, addr
, val
, attrs
, &res
);
2900 address_space_stl(as
, addr
, val
, attrs
, &res
);
2903 address_space_stq(as
, addr
, val
, attrs
, &res
);
2910 static const MemoryRegionOps watch_mem_ops
= {
2911 .read_with_attrs
= watch_mem_read
,
2912 .write_with_attrs
= watch_mem_write
,
2913 .endianness
= DEVICE_NATIVE_ENDIAN
,
2915 .min_access_size
= 1,
2916 .max_access_size
= 8,
2920 .min_access_size
= 1,
2921 .max_access_size
= 8,
2926 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
2927 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
);
2928 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2929 const uint8_t *buf
, hwaddr len
);
2930 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
2931 bool is_write
, MemTxAttrs attrs
);
2933 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2934 unsigned len
, MemTxAttrs attrs
)
2936 subpage_t
*subpage
= opaque
;
2940 #if defined(DEBUG_SUBPAGE)
2941 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2942 subpage
, len
, addr
);
2944 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2948 *data
= ldn_p(buf
, len
);
2952 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2953 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2955 subpage_t
*subpage
= opaque
;
2958 #if defined(DEBUG_SUBPAGE)
2959 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2960 " value %"PRIx64
"\n",
2961 __func__
, subpage
, len
, addr
, value
);
2963 stn_p(buf
, len
, value
);
2964 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2967 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2968 unsigned len
, bool is_write
,
2971 subpage_t
*subpage
= opaque
;
2972 #if defined(DEBUG_SUBPAGE)
2973 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2974 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2977 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2978 len
, is_write
, attrs
);
2981 static const MemoryRegionOps subpage_ops
= {
2982 .read_with_attrs
= subpage_read
,
2983 .write_with_attrs
= subpage_write
,
2984 .impl
.min_access_size
= 1,
2985 .impl
.max_access_size
= 8,
2986 .valid
.min_access_size
= 1,
2987 .valid
.max_access_size
= 8,
2988 .valid
.accepts
= subpage_accepts
,
2989 .endianness
= DEVICE_NATIVE_ENDIAN
,
2992 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
2997 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
2999 idx
= SUBPAGE_IDX(start
);
3000 eidx
= SUBPAGE_IDX(end
);
3001 #if defined(DEBUG_SUBPAGE)
3002 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
3003 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
3005 for (; idx
<= eidx
; idx
++) {
3006 mmio
->sub_section
[idx
] = section
;
3012 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
3016 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
3019 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
3020 NULL
, TARGET_PAGE_SIZE
);
3021 mmio
->iomem
.subpage
= true;
3022 #if defined(DEBUG_SUBPAGE)
3023 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
3024 mmio
, base
, TARGET_PAGE_SIZE
);
3026 subpage_register(mmio
, 0, TARGET_PAGE_SIZE
-1, PHYS_SECTION_UNASSIGNED
);
3031 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
3034 MemoryRegionSection section
= {
3037 .offset_within_address_space
= 0,
3038 .offset_within_region
= 0,
3039 .size
= int128_2_64(),
3042 return phys_section_add(map
, §ion
);
3045 static void readonly_mem_write(void *opaque
, hwaddr addr
,
3046 uint64_t val
, unsigned size
)
3048 /* Ignore any write to ROM. */
3051 static bool readonly_mem_accepts(void *opaque
, hwaddr addr
,
3052 unsigned size
, bool is_write
,
3058 /* This will only be used for writes, because reads are special cased
3059 * to directly access the underlying host ram.
3061 static const MemoryRegionOps readonly_mem_ops
= {
3062 .write
= readonly_mem_write
,
3063 .valid
.accepts
= readonly_mem_accepts
,
3064 .endianness
= DEVICE_NATIVE_ENDIAN
,
3066 .min_access_size
= 1,
3067 .max_access_size
= 8,
3071 .min_access_size
= 1,
3072 .max_access_size
= 8,
3077 MemoryRegionSection
*iotlb_to_section(CPUState
*cpu
,
3078 hwaddr index
, MemTxAttrs attrs
)
3080 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3081 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
3082 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
3083 MemoryRegionSection
*sections
= d
->map
.sections
;
3085 return §ions
[index
& ~TARGET_PAGE_MASK
];
3088 static void io_mem_init(void)
3090 memory_region_init_io(&io_mem_rom
, NULL
, &readonly_mem_ops
,
3091 NULL
, NULL
, UINT64_MAX
);
3092 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
3095 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3096 * which can be called without the iothread mutex.
3098 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
3100 memory_region_clear_global_locking(&io_mem_notdirty
);
3102 memory_region_init_io(&io_mem_watch
, NULL
, &watch_mem_ops
, NULL
,
3106 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
3108 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
3111 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
3112 assert(n
== PHYS_SECTION_UNASSIGNED
);
3113 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
3114 assert(n
== PHYS_SECTION_NOTDIRTY
);
3115 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
3116 assert(n
== PHYS_SECTION_ROM
);
3117 n
= dummy_section(&d
->map
, fv
, &io_mem_watch
);
3118 assert(n
== PHYS_SECTION_WATCH
);
3120 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
3125 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
3127 phys_sections_free(&d
->map
);
3131 static void tcg_commit(MemoryListener
*listener
)
3133 CPUAddressSpace
*cpuas
;
3134 AddressSpaceDispatch
*d
;
3136 assert(tcg_enabled());
3137 /* since each CPU stores ram addresses in its TLB cache, we must
3138 reset the modified entries */
3139 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3140 cpu_reloading_memory_map();
3141 /* The CPU and TLB are protected by the iothread lock.
3142 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3143 * may have split the RCU critical section.
3145 d
= address_space_to_dispatch(cpuas
->as
);
3146 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
3147 tlb_flush(cpuas
->cpu
);
3150 static void memory_map_init(void)
3152 system_memory
= g_malloc(sizeof(*system_memory
));
3154 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
3155 address_space_init(&address_space_memory
, system_memory
, "memory");
3157 system_io
= g_malloc(sizeof(*system_io
));
3158 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
3160 address_space_init(&address_space_io
, system_io
, "I/O");
3163 MemoryRegion
*get_system_memory(void)
3165 return system_memory
;
3168 MemoryRegion
*get_system_io(void)
3173 #endif /* !defined(CONFIG_USER_ONLY) */
3175 /* physical memory access (slow version, mainly for debug) */
3176 #if defined(CONFIG_USER_ONLY)
3177 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3178 uint8_t *buf
, target_ulong len
, int is_write
)
3181 target_ulong l
, page
;
3185 page
= addr
& TARGET_PAGE_MASK
;
3186 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3189 flags
= page_get_flags(page
);
3190 if (!(flags
& PAGE_VALID
))
3193 if (!(flags
& PAGE_WRITE
))
3195 /* XXX: this code should not depend on lock_user */
3196 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
3199 unlock_user(p
, addr
, l
);
3201 if (!(flags
& PAGE_READ
))
3203 /* XXX: this code should not depend on lock_user */
3204 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
3207 unlock_user(p
, addr
, 0);
3218 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
3221 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
3222 addr
+= memory_region_get_ram_addr(mr
);
3224 /* No early return if dirty_log_mask is or becomes 0, because
3225 * cpu_physical_memory_set_dirty_range will still call
3226 * xen_modified_memory.
3228 if (dirty_log_mask
) {
3230 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
3232 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
3233 assert(tcg_enabled());
3234 tb_invalidate_phys_range(addr
, addr
+ length
);
3235 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
3237 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
3240 void memory_region_flush_rom_device(MemoryRegion
*mr
, hwaddr addr
, hwaddr size
)
3243 * In principle this function would work on other memory region types too,
3244 * but the ROM device use case is the only one where this operation is
3245 * necessary. Other memory regions should use the
3246 * address_space_read/write() APIs.
3248 assert(memory_region_is_romd(mr
));
3250 invalidate_and_set_dirty(mr
, addr
, size
);
3253 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
3255 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
3257 /* Regions are assumed to support 1-4 byte accesses unless
3258 otherwise specified. */
3259 if (access_size_max
== 0) {
3260 access_size_max
= 4;
3263 /* Bound the maximum access by the alignment of the address. */
3264 if (!mr
->ops
->impl
.unaligned
) {
3265 unsigned align_size_max
= addr
& -addr
;
3266 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
3267 access_size_max
= align_size_max
;
3271 /* Don't attempt accesses larger than the maximum. */
3272 if (l
> access_size_max
) {
3273 l
= access_size_max
;
3280 static bool prepare_mmio_access(MemoryRegion
*mr
)
3282 bool unlocked
= !qemu_mutex_iothread_locked();
3283 bool release_lock
= false;
3285 if (unlocked
&& mr
->global_locking
) {
3286 qemu_mutex_lock_iothread();
3288 release_lock
= true;
3290 if (mr
->flush_coalesced_mmio
) {
3292 qemu_mutex_lock_iothread();
3294 qemu_flush_coalesced_mmio_buffer();
3296 qemu_mutex_unlock_iothread();
3300 return release_lock
;
3303 /* Called within RCU critical section. */
3304 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
3307 hwaddr len
, hwaddr addr1
,
3308 hwaddr l
, MemoryRegion
*mr
)
3312 MemTxResult result
= MEMTX_OK
;
3313 bool release_lock
= false;
3316 if (!memory_access_is_direct(mr
, true)) {
3317 release_lock
|= prepare_mmio_access(mr
);
3318 l
= memory_access_size(mr
, l
, addr1
);
3319 /* XXX: could force current_cpu to NULL to avoid
3321 val
= ldn_p(buf
, l
);
3322 result
|= memory_region_dispatch_write(mr
, addr1
, val
, l
, attrs
);
3325 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3326 memcpy(ptr
, buf
, l
);
3327 invalidate_and_set_dirty(mr
, addr1
, l
);
3331 qemu_mutex_unlock_iothread();
3332 release_lock
= false;
3344 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3350 /* Called from RCU critical section. */
3351 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3352 const uint8_t *buf
, hwaddr len
)
3357 MemTxResult result
= MEMTX_OK
;
3360 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3361 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
3367 /* Called within RCU critical section. */
3368 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
3369 MemTxAttrs attrs
, uint8_t *buf
,
3370 hwaddr len
, hwaddr addr1
, hwaddr l
,
3375 MemTxResult result
= MEMTX_OK
;
3376 bool release_lock
= false;
3379 if (!memory_access_is_direct(mr
, false)) {
3381 release_lock
|= prepare_mmio_access(mr
);
3382 l
= memory_access_size(mr
, l
, addr1
);
3383 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, l
, attrs
);
3387 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3388 memcpy(buf
, ptr
, l
);
3392 qemu_mutex_unlock_iothread();
3393 release_lock
= false;
3405 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3411 /* Called from RCU critical section. */
3412 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
3413 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3420 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3421 return flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3425 MemTxResult
address_space_read_full(AddressSpace
*as
, hwaddr addr
,
3426 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3428 MemTxResult result
= MEMTX_OK
;
3433 fv
= address_space_to_flatview(as
);
3434 result
= flatview_read(fv
, addr
, attrs
, buf
, len
);
3441 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
3443 const uint8_t *buf
, hwaddr len
)
3445 MemTxResult result
= MEMTX_OK
;
3450 fv
= address_space_to_flatview(as
);
3451 result
= flatview_write(fv
, addr
, attrs
, buf
, len
);
3458 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
,
3459 uint8_t *buf
, hwaddr len
, bool is_write
)
3462 return address_space_write(as
, addr
, attrs
, buf
, len
);
3464 return address_space_read_full(as
, addr
, attrs
, buf
, len
);
3468 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3469 hwaddr len
, int is_write
)
3471 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3472 buf
, len
, is_write
);
3475 enum write_rom_type
{
3480 static inline MemTxResult
address_space_write_rom_internal(AddressSpace
*as
,
3485 enum write_rom_type type
)
3495 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true, attrs
);
3497 if (!(memory_region_is_ram(mr
) ||
3498 memory_region_is_romd(mr
))) {
3499 l
= memory_access_size(mr
, l
, addr1
);
3502 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3505 memcpy(ptr
, buf
, l
);
3506 invalidate_and_set_dirty(mr
, addr1
, l
);
3509 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3521 /* used for ROM loading : can write in RAM and ROM */
3522 MemTxResult
address_space_write_rom(AddressSpace
*as
, hwaddr addr
,
3524 const uint8_t *buf
, hwaddr len
)
3526 return address_space_write_rom_internal(as
, addr
, attrs
,
3527 buf
, len
, WRITE_DATA
);
3530 void cpu_flush_icache_range(hwaddr start
, hwaddr len
)
3533 * This function should do the same thing as an icache flush that was
3534 * triggered from within the guest. For TCG we are always cache coherent,
3535 * so there is no need to flush anything. For KVM / Xen we need to flush
3536 * the host's instruction cache at least.
3538 if (tcg_enabled()) {
3542 address_space_write_rom_internal(&address_space_memory
,
3543 start
, MEMTXATTRS_UNSPECIFIED
,
3544 NULL
, len
, FLUSH_CACHE
);
3555 static BounceBuffer bounce
;
3557 typedef struct MapClient
{
3559 QLIST_ENTRY(MapClient
) link
;
3562 QemuMutex map_client_list_lock
;
3563 static QLIST_HEAD(, MapClient
) map_client_list
3564 = QLIST_HEAD_INITIALIZER(map_client_list
);
3566 static void cpu_unregister_map_client_do(MapClient
*client
)
3568 QLIST_REMOVE(client
, link
);
3572 static void cpu_notify_map_clients_locked(void)
3576 while (!QLIST_EMPTY(&map_client_list
)) {
3577 client
= QLIST_FIRST(&map_client_list
);
3578 qemu_bh_schedule(client
->bh
);
3579 cpu_unregister_map_client_do(client
);
3583 void cpu_register_map_client(QEMUBH
*bh
)
3585 MapClient
*client
= g_malloc(sizeof(*client
));
3587 qemu_mutex_lock(&map_client_list_lock
);
3589 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3590 if (!atomic_read(&bounce
.in_use
)) {
3591 cpu_notify_map_clients_locked();
3593 qemu_mutex_unlock(&map_client_list_lock
);
3596 void cpu_exec_init_all(void)
3598 qemu_mutex_init(&ram_list
.mutex
);
3599 /* The data structures we set up here depend on knowing the page size,
3600 * so no more changes can be made after this point.
3601 * In an ideal world, nothing we did before we had finished the
3602 * machine setup would care about the target page size, and we could
3603 * do this much later, rather than requiring board models to state
3604 * up front what their requirements are.
3606 finalize_target_page_bits();
3609 qemu_mutex_init(&map_client_list_lock
);
3612 void cpu_unregister_map_client(QEMUBH
*bh
)
3616 qemu_mutex_lock(&map_client_list_lock
);
3617 QLIST_FOREACH(client
, &map_client_list
, link
) {
3618 if (client
->bh
== bh
) {
3619 cpu_unregister_map_client_do(client
);
3623 qemu_mutex_unlock(&map_client_list_lock
);
3626 static void cpu_notify_map_clients(void)
3628 qemu_mutex_lock(&map_client_list_lock
);
3629 cpu_notify_map_clients_locked();
3630 qemu_mutex_unlock(&map_client_list_lock
);
3633 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
3634 bool is_write
, MemTxAttrs attrs
)
3641 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3642 if (!memory_access_is_direct(mr
, is_write
)) {
3643 l
= memory_access_size(mr
, l
, addr
);
3644 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
, attrs
)) {
3655 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3656 hwaddr len
, bool is_write
,
3663 fv
= address_space_to_flatview(as
);
3664 result
= flatview_access_valid(fv
, addr
, len
, is_write
, attrs
);
3670 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3672 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3673 bool is_write
, MemTxAttrs attrs
)
3677 MemoryRegion
*this_mr
;
3683 if (target_len
== 0) {
3688 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3689 &len
, is_write
, attrs
);
3690 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3696 /* Map a physical memory region into a host virtual address.
3697 * May map a subset of the requested range, given by and returned in *plen.
3698 * May return NULL if resources needed to perform the mapping are exhausted.
3699 * Use only for reads OR writes - not for read-modify-write operations.
3700 * Use cpu_register_map_client() to know when retrying the map operation is
3701 * likely to succeed.
3703 void *address_space_map(AddressSpace
*as
,
3721 fv
= address_space_to_flatview(as
);
3722 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3724 if (!memory_access_is_direct(mr
, is_write
)) {
3725 if (atomic_xchg(&bounce
.in_use
, true)) {
3729 /* Avoid unbounded allocations */
3730 l
= MIN(l
, TARGET_PAGE_SIZE
);
3731 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3735 memory_region_ref(mr
);
3738 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3744 return bounce
.buffer
;
3748 memory_region_ref(mr
);
3749 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3750 l
, is_write
, attrs
);
3751 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3757 /* Unmaps a memory region previously mapped by address_space_map().
3758 * Will also mark the memory as dirty if is_write == 1. access_len gives
3759 * the amount of memory that was actually read or written by the caller.
3761 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3762 int is_write
, hwaddr access_len
)
3764 if (buffer
!= bounce
.buffer
) {
3768 mr
= memory_region_from_host(buffer
, &addr1
);
3771 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3773 if (xen_enabled()) {
3774 xen_invalidate_map_cache_entry(buffer
);
3776 memory_region_unref(mr
);
3780 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3781 bounce
.buffer
, access_len
);
3783 qemu_vfree(bounce
.buffer
);
3784 bounce
.buffer
= NULL
;
3785 memory_region_unref(bounce
.mr
);
3786 atomic_mb_set(&bounce
.in_use
, false);
3787 cpu_notify_map_clients();
3790 void *cpu_physical_memory_map(hwaddr addr
,
3794 return address_space_map(&address_space_memory
, addr
, plen
, is_write
,
3795 MEMTXATTRS_UNSPECIFIED
);
3798 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3799 int is_write
, hwaddr access_len
)
3801 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3804 #define ARG1_DECL AddressSpace *as
3807 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3808 #define RCU_READ_LOCK(...) rcu_read_lock()
3809 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3810 #include "memory_ldst.inc.c"
3812 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3818 AddressSpaceDispatch
*d
;
3825 cache
->fv
= address_space_get_flatview(as
);
3826 d
= flatview_to_dispatch(cache
->fv
);
3827 cache
->mrs
= *address_space_translate_internal(d
, addr
, &cache
->xlat
, &l
, true);
3830 memory_region_ref(mr
);
3831 if (memory_access_is_direct(mr
, is_write
)) {
3832 /* We don't care about the memory attributes here as we're only
3833 * doing this if we found actual RAM, which behaves the same
3834 * regardless of attributes; so UNSPECIFIED is fine.
3836 l
= flatview_extend_translation(cache
->fv
, addr
, len
, mr
,
3837 cache
->xlat
, l
, is_write
,
3838 MEMTXATTRS_UNSPECIFIED
);
3839 cache
->ptr
= qemu_ram_ptr_length(mr
->ram_block
, cache
->xlat
, &l
, true);
3845 cache
->is_write
= is_write
;
3849 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3853 assert(cache
->is_write
);
3854 if (likely(cache
->ptr
)) {
3855 invalidate_and_set_dirty(cache
->mrs
.mr
, addr
+ cache
->xlat
, access_len
);
3859 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3861 if (!cache
->mrs
.mr
) {
3865 if (xen_enabled()) {
3866 xen_invalidate_map_cache_entry(cache
->ptr
);
3868 memory_region_unref(cache
->mrs
.mr
);
3869 flatview_unref(cache
->fv
);
3870 cache
->mrs
.mr
= NULL
;
3874 /* Called from RCU critical section. This function has the same
3875 * semantics as address_space_translate, but it only works on a
3876 * predefined range of a MemoryRegion that was mapped with
3877 * address_space_cache_init.
3879 static inline MemoryRegion
*address_space_translate_cached(
3880 MemoryRegionCache
*cache
, hwaddr addr
, hwaddr
*xlat
,
3881 hwaddr
*plen
, bool is_write
, MemTxAttrs attrs
)
3883 MemoryRegionSection section
;
3885 IOMMUMemoryRegion
*iommu_mr
;
3886 AddressSpace
*target_as
;
3888 assert(!cache
->ptr
);
3889 *xlat
= addr
+ cache
->xlat
;
3892 iommu_mr
= memory_region_get_iommu(mr
);
3898 section
= address_space_translate_iommu(iommu_mr
, xlat
, plen
,
3899 NULL
, is_write
, true,
3904 /* Called from RCU critical section. address_space_read_cached uses this
3905 * out of line function when the target is an MMIO or IOMMU region.
3908 address_space_read_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3909 void *buf
, hwaddr len
)
3915 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, false,
3916 MEMTXATTRS_UNSPECIFIED
);
3917 flatview_read_continue(cache
->fv
,
3918 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3922 /* Called from RCU critical section. address_space_write_cached uses this
3923 * out of line function when the target is an MMIO or IOMMU region.
3926 address_space_write_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3927 const void *buf
, hwaddr len
)
3933 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, true,
3934 MEMTXATTRS_UNSPECIFIED
);
3935 flatview_write_continue(cache
->fv
,
3936 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3940 #define ARG1_DECL MemoryRegionCache *cache
3942 #define SUFFIX _cached_slow
3943 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3944 #define RCU_READ_LOCK() ((void)0)
3945 #define RCU_READ_UNLOCK() ((void)0)
3946 #include "memory_ldst.inc.c"
3948 /* virtual memory access for debug (includes writing to ROM) */
3949 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3950 uint8_t *buf
, target_ulong len
, int is_write
)
3953 target_ulong l
, page
;
3955 cpu_synchronize_state(cpu
);
3960 page
= addr
& TARGET_PAGE_MASK
;
3961 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
3962 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3963 /* if no physical page mapped, return an error */
3964 if (phys_addr
== -1)
3966 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3969 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
3971 address_space_write_rom(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3974 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3985 * Allows code that needs to deal with migration bitmaps etc to still be built
3986 * target independent.
3988 size_t qemu_target_page_size(void)
3990 return TARGET_PAGE_SIZE
;
3993 int qemu_target_page_bits(void)
3995 return TARGET_PAGE_BITS
;
3998 int qemu_target_page_bits_min(void)
4000 return TARGET_PAGE_BITS_MIN
;
4004 bool target_words_bigendian(void)
4006 #if defined(TARGET_WORDS_BIGENDIAN)
4013 #ifndef CONFIG_USER_ONLY
4014 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
4021 mr
= address_space_translate(&address_space_memory
,
4022 phys_addr
, &phys_addr
, &l
, false,
4023 MEMTXATTRS_UNSPECIFIED
);
4025 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
4030 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
4036 RAMBLOCK_FOREACH(block
) {
4037 ret
= func(block
, opaque
);
4047 * Unmap pages of memory from start to start+length such that
4048 * they a) read as 0, b) Trigger whatever fault mechanism
4049 * the OS provides for postcopy.
4050 * The pages must be unmapped by the end of the function.
4051 * Returns: 0 on success, none-0 on failure
4054 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
4058 uint8_t *host_startaddr
= rb
->host
+ start
;
4060 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
4061 error_report("ram_block_discard_range: Unaligned start address: %p",
4066 if ((start
+ length
) <= rb
->used_length
) {
4067 bool need_madvise
, need_fallocate
;
4068 uint8_t *host_endaddr
= host_startaddr
+ length
;
4069 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
4070 error_report("ram_block_discard_range: Unaligned end address: %p",
4075 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
4077 /* The logic here is messy;
4078 * madvise DONTNEED fails for hugepages
4079 * fallocate works on hugepages and shmem
4081 need_madvise
= (rb
->page_size
== qemu_host_page_size
);
4082 need_fallocate
= rb
->fd
!= -1;
4083 if (need_fallocate
) {
4084 /* For a file, this causes the area of the file to be zero'd
4085 * if read, and for hugetlbfs also causes it to be unmapped
4086 * so a userfault will trigger.
4088 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4089 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
4093 error_report("ram_block_discard_range: Failed to fallocate "
4094 "%s:%" PRIx64
" +%zx (%d)",
4095 rb
->idstr
, start
, length
, ret
);
4100 error_report("ram_block_discard_range: fallocate not available/file"
4101 "%s:%" PRIx64
" +%zx (%d)",
4102 rb
->idstr
, start
, length
, ret
);
4107 /* For normal RAM this causes it to be unmapped,
4108 * for shared memory it causes the local mapping to disappear
4109 * and to fall back on the file contents (which we just
4110 * fallocate'd away).
4112 #if defined(CONFIG_MADVISE)
4113 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
4116 error_report("ram_block_discard_range: Failed to discard range "
4117 "%s:%" PRIx64
" +%zx (%d)",
4118 rb
->idstr
, start
, length
, ret
);
4123 error_report("ram_block_discard_range: MADVISE not available"
4124 "%s:%" PRIx64
" +%zx (%d)",
4125 rb
->idstr
, start
, length
, ret
);
4129 trace_ram_block_discard_range(rb
->idstr
, host_startaddr
, length
,
4130 need_madvise
, need_fallocate
, ret
);
4132 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4133 "/%zx/" RAM_ADDR_FMT
")",
4134 rb
->idstr
, start
, length
, rb
->used_length
);
4141 bool ramblock_is_pmem(RAMBlock
*rb
)
4143 return rb
->flags
& RAM_PMEM
;
4148 void page_size_init(void)
4150 /* NOTE: we can always suppose that qemu_host_page_size >=
4152 if (qemu_host_page_size
== 0) {
4153 qemu_host_page_size
= qemu_real_host_page_size
;
4155 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
4156 qemu_host_page_size
= TARGET_PAGE_SIZE
;
4158 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
4161 #if !defined(CONFIG_USER_ONLY)
4163 static void mtree_print_phys_entries(int start
, int end
, int skip
, int ptr
)
4165 if (start
== end
- 1) {
4166 qemu_printf("\t%3d ", start
);
4168 qemu_printf("\t%3d..%-3d ", start
, end
- 1);
4170 qemu_printf(" skip=%d ", skip
);
4171 if (ptr
== PHYS_MAP_NODE_NIL
) {
4172 qemu_printf(" ptr=NIL");
4174 qemu_printf(" ptr=#%d", ptr
);
4176 qemu_printf(" ptr=[%d]", ptr
);
4181 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4182 int128_sub((size), int128_one())) : 0)
4184 void mtree_print_dispatch(AddressSpaceDispatch
*d
, MemoryRegion
*root
)
4188 qemu_printf(" Dispatch\n");
4189 qemu_printf(" Physical sections\n");
4191 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
4192 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
4193 const char *names
[] = { " [unassigned]", " [not dirty]",
4194 " [ROM]", " [watch]" };
4196 qemu_printf(" #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
4199 s
->offset_within_address_space
,
4200 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
4201 s
->mr
->name
? s
->mr
->name
: "(noname)",
4202 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
4203 s
->mr
== root
? " [ROOT]" : "",
4204 s
== d
->mru_section
? " [MRU]" : "",
4205 s
->mr
->is_iommu
? " [iommu]" : "");
4208 qemu_printf(" alias=%s", s
->mr
->alias
->name
?
4209 s
->mr
->alias
->name
: "noname");
4214 qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4215 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
4216 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
4219 Node
*n
= d
->map
.nodes
+ i
;
4221 qemu_printf(" [%d]\n", i
);
4223 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
4224 PhysPageEntry
*pe
= *n
+ j
;
4226 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
4230 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);
4236 if (jprev
!= ARRAY_SIZE(*n
)) {
4237 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);