1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Number of littlenums required to hold an extended precision number. */
242 #define MAX_LITTLENUMS 6
244 /* Return value for certain parsers when the parsing fails; those parsers
245 return the information of the parsed result, e.g. register number, on
247 #define PARSE_FAIL -1
249 /* This is an invalid condition code that means no conditional field is
251 #define COND_ALWAYS 0x10
255 const char *template;
261 const char *template;
268 bfd_reloc_code_real_type reloc
;
271 /* Macros to define the register types and masks for the purpose
274 #undef AARCH64_REG_TYPES
275 #define AARCH64_REG_TYPES \
276 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
277 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
278 BASIC_REG_TYPE(SP_32) /* wsp */ \
279 BASIC_REG_TYPE(SP_64) /* sp */ \
280 BASIC_REG_TYPE(Z_32) /* wzr */ \
281 BASIC_REG_TYPE(Z_64) /* xzr */ \
282 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
283 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
284 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
285 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
286 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
287 BASIC_REG_TYPE(VN) /* v[0-31] */ \
288 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
289 BASIC_REG_TYPE(PN) /* p[0-15] */ \
290 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
291 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
292 /* Typecheck: same, plus SVE registers. */ \
293 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
295 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
296 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
298 /* Typecheck: same, plus SVE registers. */ \
299 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
300 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
302 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
303 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
305 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
306 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
307 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
308 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
309 /* Typecheck: any [BHSDQ]P FP. */ \
310 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
311 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
312 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
313 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
314 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
315 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
316 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
317 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
318 be used for SVE instructions, since Zn and Pn are valid symbols \
319 in other contexts. */ \
320 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
321 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
322 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
323 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
324 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
325 | REG_TYPE(ZN) | REG_TYPE(PN)) \
326 /* Any integer register; used for error messages only. */ \
327 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
328 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
329 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
330 /* Pseudo type to mark the end of the enumerator sequence. */ \
333 #undef BASIC_REG_TYPE
334 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
335 #undef MULTI_REG_TYPE
336 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
338 /* Register type enumerators. */
339 typedef enum aarch64_reg_type_
341 /* A list of REG_TYPE_*. */
345 #undef BASIC_REG_TYPE
346 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
348 #define REG_TYPE(T) (1 << REG_TYPE_##T)
349 #undef MULTI_REG_TYPE
350 #define MULTI_REG_TYPE(T,V) V,
352 /* Structure for a hash table entry for a register. */
356 unsigned char number
;
357 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
358 unsigned char builtin
;
361 /* Values indexed by aarch64_reg_type to assist the type checking. */
362 static const unsigned reg_type_masks
[] =
367 #undef BASIC_REG_TYPE
369 #undef MULTI_REG_TYPE
370 #undef AARCH64_REG_TYPES
372 /* Diagnostics used when we don't get a register of the expected type.
373 Note: this has to synchronized with aarch64_reg_type definitions
376 get_reg_expected_msg (aarch64_reg_type reg_type
)
383 msg
= N_("integer 32-bit register expected");
386 msg
= N_("integer 64-bit register expected");
389 msg
= N_("integer register expected");
391 case REG_TYPE_R64_SP
:
392 msg
= N_("64-bit integer or SP register expected");
394 case REG_TYPE_SVE_BASE
:
395 msg
= N_("base register expected");
398 msg
= N_("integer or zero register expected");
400 case REG_TYPE_SVE_OFFSET
:
401 msg
= N_("offset register expected");
404 msg
= N_("integer or SP register expected");
406 case REG_TYPE_R_Z_SP
:
407 msg
= N_("integer, zero or SP register expected");
410 msg
= N_("8-bit SIMD scalar register expected");
413 msg
= N_("16-bit SIMD scalar or floating-point half precision "
414 "register expected");
417 msg
= N_("32-bit SIMD scalar or floating-point single precision "
418 "register expected");
421 msg
= N_("64-bit SIMD scalar or floating-point double precision "
422 "register expected");
425 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
426 "register expected");
428 case REG_TYPE_R_Z_BHSDQ_V
:
429 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
430 msg
= N_("register expected");
432 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
433 msg
= N_("SIMD scalar or floating-point register expected");
435 case REG_TYPE_VN
: /* any V reg */
436 msg
= N_("vector register expected");
439 msg
= N_("SVE vector register expected");
442 msg
= N_("SVE predicate register expected");
445 as_fatal (_("invalid register type %d"), reg_type
);
450 /* Some well known registers that we refer to directly elsewhere. */
453 /* Instructions take 4 bytes in the object file. */
456 static struct hash_control
*aarch64_ops_hsh
;
457 static struct hash_control
*aarch64_cond_hsh
;
458 static struct hash_control
*aarch64_shift_hsh
;
459 static struct hash_control
*aarch64_sys_regs_hsh
;
460 static struct hash_control
*aarch64_pstatefield_hsh
;
461 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
462 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
463 static struct hash_control
*aarch64_sys_regs_at_hsh
;
464 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
465 static struct hash_control
*aarch64_sys_regs_sr_hsh
;
466 static struct hash_control
*aarch64_reg_hsh
;
467 static struct hash_control
*aarch64_barrier_opt_hsh
;
468 static struct hash_control
*aarch64_nzcv_hsh
;
469 static struct hash_control
*aarch64_pldop_hsh
;
470 static struct hash_control
*aarch64_hint_opt_hsh
;
472 /* Stuff needed to resolve the label ambiguity
481 static symbolS
*last_label_seen
;
483 /* Literal pool structure. Held on a per-section
484 and per-sub-section basis. */
486 #define MAX_LITERAL_POOL_SIZE 1024
487 typedef struct literal_expression
490 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
491 LITTLENUM_TYPE
* bignum
;
492 } literal_expression
;
494 typedef struct literal_pool
496 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
497 unsigned int next_free_entry
;
503 struct literal_pool
*next
;
506 /* Pointer to a linked list of literal pools. */
507 static literal_pool
*list_of_pools
= NULL
;
511 /* This array holds the chars that always start a comment. If the
512 pre-processor is disabled, these aren't very useful. */
513 const char comment_chars
[] = "";
515 /* This array holds the chars that only start a comment at the beginning of
516 a line. If the line seems to have the form '# 123 filename'
517 .line and .file directives will appear in the pre-processed output. */
518 /* Note that input_file.c hand checks for '#' at the beginning of the
519 first line of the input file. This is because the compiler outputs
520 #NO_APP at the beginning of its output. */
521 /* Also note that comments like this one will always work. */
522 const char line_comment_chars
[] = "#";
524 const char line_separator_chars
[] = ";";
526 /* Chars that can be used to separate mant
527 from exp in floating point numbers. */
528 const char EXP_CHARS
[] = "eE";
530 /* Chars that mean this number is a floating point constant. */
534 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
536 /* Prefix character that indicates the start of an immediate value. */
537 #define is_immediate_prefix(C) ((C) == '#')
539 /* Separator character handling. */
541 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
543 static inline bfd_boolean
544 skip_past_char (char **str
, char c
)
555 #define skip_past_comma(str) skip_past_char (str, ',')
557 /* Arithmetic expressions (possibly involving symbols). */
559 static bfd_boolean in_my_get_expression_p
= FALSE
;
561 /* Third argument to my_get_expression. */
562 #define GE_NO_PREFIX 0
563 #define GE_OPT_PREFIX 1
565 /* Return TRUE if the string pointed by *STR is successfully parsed
566 as an valid expression; *EP will be filled with the information of
567 such an expression. Otherwise return FALSE. */
570 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
575 int prefix_present_p
= 0;
582 if (is_immediate_prefix (**str
))
585 prefix_present_p
= 1;
592 memset (ep
, 0, sizeof (expressionS
));
594 save_in
= input_line_pointer
;
595 input_line_pointer
= *str
;
596 in_my_get_expression_p
= TRUE
;
597 seg
= expression (ep
);
598 in_my_get_expression_p
= FALSE
;
600 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
602 /* We found a bad expression in md_operand(). */
603 *str
= input_line_pointer
;
604 input_line_pointer
= save_in
;
605 if (prefix_present_p
&& ! error_p ())
606 set_fatal_syntax_error (_("bad expression"));
608 set_first_syntax_error (_("bad expression"));
613 if (seg
!= absolute_section
614 && seg
!= text_section
615 && seg
!= data_section
616 && seg
!= bss_section
&& seg
!= undefined_section
)
618 set_syntax_error (_("bad segment"));
619 *str
= input_line_pointer
;
620 input_line_pointer
= save_in
;
627 *str
= input_line_pointer
;
628 input_line_pointer
= save_in
;
632 /* Turn a string in input_line_pointer into a floating point constant
633 of type TYPE, and store the appropriate bytes in *LITP. The number
634 of LITTLENUMS emitted is stored in *SIZEP. An error message is
635 returned, or NULL on OK. */
638 md_atof (int type
, char *litP
, int *sizeP
)
640 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
643 /* We handle all bad expressions here, so that we can report the faulty
644 instruction in the error message. */
646 md_operand (expressionS
* exp
)
648 if (in_my_get_expression_p
)
649 exp
->X_op
= O_illegal
;
652 /* Immediate values. */
654 /* Errors may be set multiple times during parsing or bit encoding
655 (particularly in the Neon bits), but usually the earliest error which is set
656 will be the most meaningful. Avoid overwriting it with later (cascading)
657 errors by calling this function. */
660 first_error (const char *error
)
663 set_syntax_error (error
);
666 /* Similar to first_error, but this function accepts formatted error
669 first_error_fmt (const char *format
, ...)
674 /* N.B. this single buffer will not cause error messages for different
675 instructions to pollute each other; this is because at the end of
676 processing of each assembly line, error message if any will be
677 collected by as_bad. */
678 static char buffer
[size
];
682 int ret ATTRIBUTE_UNUSED
;
683 va_start (args
, format
);
684 ret
= vsnprintf (buffer
, size
, format
, args
);
685 know (ret
<= size
- 1 && ret
>= 0);
687 set_syntax_error (buffer
);
691 /* Register parsing. */
693 /* Generic register parser which is called by other specialized
695 CCP points to what should be the beginning of a register name.
696 If it is indeed a valid register name, advance CCP over it and
697 return the reg_entry structure; otherwise return NULL.
698 It does not issue diagnostics. */
701 parse_reg (char **ccp
)
707 #ifdef REGISTER_PREFIX
708 if (*start
!= REGISTER_PREFIX
)
714 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
719 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
721 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
730 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
733 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
735 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
738 /* Try to parse a base or offset register. Allow SVE base and offset
739 registers if REG_TYPE includes SVE registers. Return the register
740 entry on success, setting *QUALIFIER to the register qualifier.
741 Return null otherwise.
743 Note that this function does not issue any diagnostics. */
745 static const reg_entry
*
746 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
747 aarch64_opnd_qualifier_t
*qualifier
)
750 const reg_entry
*reg
= parse_reg (&str
);
760 *qualifier
= AARCH64_OPND_QLF_W
;
766 *qualifier
= AARCH64_OPND_QLF_X
;
770 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
773 switch (TOLOWER (str
[1]))
776 *qualifier
= AARCH64_OPND_QLF_S_S
;
779 *qualifier
= AARCH64_OPND_QLF_S_D
;
796 /* Try to parse a base or offset register. Return the register entry
797 on success, setting *QUALIFIER to the register qualifier. Return null
800 Note that this function does not issue any diagnostics. */
802 static const reg_entry
*
803 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
805 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
808 /* Parse the qualifier of a vector register or vector element of type
809 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
810 succeeds; otherwise return FALSE.
812 Accept only one occurrence of:
813 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
816 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
817 struct vector_type_el
*parsed_type
, char **str
)
821 unsigned element_size
;
822 enum vector_el_type type
;
825 gas_assert (*ptr
== '.');
828 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
833 width
= strtoul (ptr
, &ptr
, 10);
834 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
836 first_error_fmt (_("bad size %d in vector width specifier"), width
);
841 switch (TOLOWER (*ptr
))
860 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
869 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
871 first_error (_("missing element size"));
874 if (width
!= 0 && width
* element_size
!= 64
875 && width
* element_size
!= 128
876 && !(width
== 2 && element_size
== 16)
877 && !(width
== 4 && element_size
== 8))
880 ("invalid element size %d and vector size combination %c"),
886 parsed_type
->type
= type
;
887 parsed_type
->width
= width
;
894 /* *STR contains an SVE zero/merge predication suffix. Parse it into
895 *PARSED_TYPE and point *STR at the end of the suffix. */
898 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
903 gas_assert (*ptr
== '/');
905 switch (TOLOWER (*ptr
))
908 parsed_type
->type
= NT_zero
;
911 parsed_type
->type
= NT_merge
;
914 if (*ptr
!= '\0' && *ptr
!= ',')
915 first_error_fmt (_("unexpected character `%c' in predication type"),
918 first_error (_("missing predication type"));
921 parsed_type
->width
= 0;
926 /* Parse a register of the type TYPE.
928 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
929 name or the parsed register is not of TYPE.
931 Otherwise return the register number, and optionally fill in the actual
932 type of the register in *RTYPE when multiple alternatives were given, and
933 return the register shape and element index information in *TYPEINFO.
935 IN_REG_LIST should be set with TRUE if the caller is parsing a register
939 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
940 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
943 const reg_entry
*reg
= parse_reg (&str
);
944 struct vector_type_el atype
;
945 struct vector_type_el parsetype
;
946 bfd_boolean is_typed_vecreg
= FALSE
;
949 atype
.type
= NT_invtype
;
957 set_default_error ();
961 if (! aarch64_check_reg_type (reg
, type
))
963 DEBUG_TRACE ("reg type check failed");
964 set_default_error ();
969 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
970 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
974 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
979 if (!parse_predication_for_operand (&parsetype
, &str
))
983 /* Register if of the form Vn.[bhsdq]. */
984 is_typed_vecreg
= TRUE
;
986 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
988 /* The width is always variable; we don't allow an integer width
990 gas_assert (parsetype
.width
== 0);
991 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
993 else if (parsetype
.width
== 0)
994 /* Expect index. In the new scheme we cannot have
995 Vn.[bhsdq] represent a scalar. Therefore any
996 Vn.[bhsdq] should have an index following it.
997 Except in reglists of course. */
998 atype
.defined
|= NTA_HASINDEX
;
1000 atype
.defined
|= NTA_HASTYPE
;
1002 atype
.type
= parsetype
.type
;
1003 atype
.width
= parsetype
.width
;
1006 if (skip_past_char (&str
, '['))
1010 /* Reject Sn[index] syntax. */
1011 if (!is_typed_vecreg
)
1013 first_error (_("this type of register can't be indexed"));
1019 first_error (_("index not allowed inside register list"));
1023 atype
.defined
|= NTA_HASINDEX
;
1025 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1027 if (exp
.X_op
!= O_constant
)
1029 first_error (_("constant expression required"));
1033 if (! skip_past_char (&str
, ']'))
1036 atype
.index
= exp
.X_add_number
;
1038 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1040 /* Indexed vector register expected. */
1041 first_error (_("indexed vector register expected"));
1045 /* A vector reg Vn should be typed or indexed. */
1046 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1048 first_error (_("invalid use of vector register"));
1064 Return the register number on success; return PARSE_FAIL otherwise.
1066 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1067 the register (e.g. NEON double or quad reg when either has been requested).
1069 If this is a NEON vector register with additional type information, fill
1070 in the struct pointed to by VECTYPE (if non-NULL).
1072 This parser does not handle register list. */
1075 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1076 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1078 struct vector_type_el atype
;
1080 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1081 /*in_reg_list= */ FALSE
);
1083 if (reg
== PARSE_FAIL
)
1094 static inline bfd_boolean
1095 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1099 && e1
.defined
== e2
.defined
1100 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1103 /* This function parses a list of vector registers of type TYPE.
1104 On success, it returns the parsed register list information in the
1105 following encoded format:
1107 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1108 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1110 The information of the register shape and/or index is returned in
1113 It returns PARSE_FAIL if the register list is invalid.
1115 The list contains one to four registers.
1116 Each register can be one of:
1119 All <T> should be identical.
1120 All <index> should be identical.
1121 There are restrictions on <Vt> numbers which are checked later
1122 (by reg_list_valid_p). */
1125 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1126 struct vector_type_el
*vectype
)
1130 struct vector_type_el typeinfo
, typeinfo_first
;
1135 bfd_boolean error
= FALSE
;
1136 bfd_boolean expect_index
= FALSE
;
1140 set_syntax_error (_("expecting {"));
1146 typeinfo_first
.defined
= 0;
1147 typeinfo_first
.type
= NT_invtype
;
1148 typeinfo_first
.width
= -1;
1149 typeinfo_first
.index
= 0;
1158 str
++; /* skip over '-' */
1161 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1162 /*in_reg_list= */ TRUE
);
1163 if (val
== PARSE_FAIL
)
1165 set_first_syntax_error (_("invalid vector register in list"));
1169 /* reject [bhsd]n */
1170 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1172 set_first_syntax_error (_("invalid scalar register in list"));
1177 if (typeinfo
.defined
& NTA_HASINDEX
)
1178 expect_index
= TRUE
;
1182 if (val
< val_range
)
1184 set_first_syntax_error
1185 (_("invalid range in vector register list"));
1194 typeinfo_first
= typeinfo
;
1195 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1197 set_first_syntax_error
1198 (_("type mismatch in vector register list"));
1203 for (i
= val_range
; i
<= val
; i
++)
1205 ret_val
|= i
<< (5 * nb_regs
);
1210 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1212 skip_whitespace (str
);
1215 set_first_syntax_error (_("end of vector register list not found"));
1220 skip_whitespace (str
);
1224 if (skip_past_char (&str
, '['))
1228 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1229 if (exp
.X_op
!= O_constant
)
1231 set_first_syntax_error (_("constant expression required."));
1234 if (! skip_past_char (&str
, ']'))
1237 typeinfo_first
.index
= exp
.X_add_number
;
1241 set_first_syntax_error (_("expected index"));
1248 set_first_syntax_error (_("too many registers in vector register list"));
1251 else if (nb_regs
== 0)
1253 set_first_syntax_error (_("empty vector register list"));
1259 *vectype
= typeinfo_first
;
1261 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1264 /* Directives: register aliases. */
1267 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1272 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1275 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1278 /* Only warn about a redefinition if it's not defined as the
1280 else if (new->number
!= number
|| new->type
!= type
)
1281 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1286 name
= xstrdup (str
);
1287 new = XNEW (reg_entry
);
1290 new->number
= number
;
1292 new->builtin
= FALSE
;
1294 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1300 /* Look for the .req directive. This is of the form:
1302 new_register_name .req existing_register_name
1304 If we find one, or if it looks sufficiently like one that we want to
1305 handle any error here, return TRUE. Otherwise return FALSE. */
1308 create_register_alias (char *newname
, char *p
)
1310 const reg_entry
*old
;
1311 char *oldname
, *nbuf
;
1314 /* The input scrubber ensures that whitespace after the mnemonic is
1315 collapsed to single spaces. */
1317 if (strncmp (oldname
, " .req ", 6) != 0)
1321 if (*oldname
== '\0')
1324 old
= hash_find (aarch64_reg_hsh
, oldname
);
1327 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1331 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1332 the desired alias name, and p points to its end. If not, then
1333 the desired alias name is in the global original_case_string. */
1334 #ifdef TC_CASE_SENSITIVE
1337 newname
= original_case_string
;
1338 nlen
= strlen (newname
);
1341 nbuf
= xmemdup0 (newname
, nlen
);
1343 /* Create aliases under the new name as stated; an all-lowercase
1344 version of the new name; and an all-uppercase version of the new
1346 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1348 for (p
= nbuf
; *p
; p
++)
1351 if (strncmp (nbuf
, newname
, nlen
))
1353 /* If this attempt to create an additional alias fails, do not bother
1354 trying to create the all-lower case alias. We will fail and issue
1355 a second, duplicate error message. This situation arises when the
1356 programmer does something like:
1359 The second .req creates the "Foo" alias but then fails to create
1360 the artificial FOO alias because it has already been created by the
1362 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1369 for (p
= nbuf
; *p
; p
++)
1372 if (strncmp (nbuf
, newname
, nlen
))
1373 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1380 /* Should never be called, as .req goes between the alias and the
1381 register name, not at the beginning of the line. */
1383 s_req (int a ATTRIBUTE_UNUSED
)
1385 as_bad (_("invalid syntax for .req directive"));
1388 /* The .unreq directive deletes an alias which was previously defined
1389 by .req. For example:
1395 s_unreq (int a ATTRIBUTE_UNUSED
)
1400 name
= input_line_pointer
;
1402 while (*input_line_pointer
!= 0
1403 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1404 ++input_line_pointer
;
1406 saved_char
= *input_line_pointer
;
1407 *input_line_pointer
= 0;
1410 as_bad (_("invalid syntax for .unreq directive"));
1413 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1416 as_bad (_("unknown register alias '%s'"), name
);
1417 else if (reg
->builtin
)
1418 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1425 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1426 free ((char *) reg
->name
);
1429 /* Also locate the all upper case and all lower case versions.
1430 Do not complain if we cannot find one or the other as it
1431 was probably deleted above. */
1433 nbuf
= strdup (name
);
1434 for (p
= nbuf
; *p
; p
++)
1436 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1439 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1440 free ((char *) reg
->name
);
1444 for (p
= nbuf
; *p
; p
++)
1446 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1449 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1450 free ((char *) reg
->name
);
1458 *input_line_pointer
= saved_char
;
1459 demand_empty_rest_of_line ();
1462 /* Directives: Instruction set selection. */
1465 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1466 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1467 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1468 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1470 /* Create a new mapping symbol for the transition to STATE. */
1473 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1476 const char *symname
;
1483 type
= BSF_NO_FLAGS
;
1487 type
= BSF_NO_FLAGS
;
1493 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1494 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1496 /* Save the mapping symbols for future reference. Also check that
1497 we do not place two mapping symbols at the same offset within a
1498 frag. We'll handle overlap between frags in
1499 check_mapping_symbols.
1501 If .fill or other data filling directive generates zero sized data,
1502 the mapping symbol for the following code will have the same value
1503 as the one generated for the data filling directive. In this case,
1504 we replace the old symbol with the new one at the same address. */
1507 if (frag
->tc_frag_data
.first_map
!= NULL
)
1509 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1510 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1513 frag
->tc_frag_data
.first_map
= symbolP
;
1515 if (frag
->tc_frag_data
.last_map
!= NULL
)
1517 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1518 S_GET_VALUE (symbolP
));
1519 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1520 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1523 frag
->tc_frag_data
.last_map
= symbolP
;
1526 /* We must sometimes convert a region marked as code to data during
1527 code alignment, if an odd number of bytes have to be padded. The
1528 code mapping symbol is pushed to an aligned address. */
1531 insert_data_mapping_symbol (enum mstate state
,
1532 valueT value
, fragS
* frag
, offsetT bytes
)
1534 /* If there was already a mapping symbol, remove it. */
1535 if (frag
->tc_frag_data
.last_map
!= NULL
1536 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1537 frag
->fr_address
+ value
)
1539 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1543 know (frag
->tc_frag_data
.first_map
== symp
);
1544 frag
->tc_frag_data
.first_map
= NULL
;
1546 frag
->tc_frag_data
.last_map
= NULL
;
1547 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1550 make_mapping_symbol (MAP_DATA
, value
, frag
);
1551 make_mapping_symbol (state
, value
+ bytes
, frag
);
1554 static void mapping_state_2 (enum mstate state
, int max_chars
);
1556 /* Set the mapping state to STATE. Only call this when about to
1557 emit some STATE bytes to the file. */
1560 mapping_state (enum mstate state
)
1562 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1564 if (state
== MAP_INSN
)
1565 /* AArch64 instructions require 4-byte alignment. When emitting
1566 instructions into any section, record the appropriate section
1568 record_alignment (now_seg
, 2);
1570 if (mapstate
== state
)
1571 /* The mapping symbol has already been emitted.
1572 There is nothing else to do. */
1575 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1576 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1577 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1578 evaluated later in the next else. */
1580 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1582 /* Only add the symbol if the offset is > 0:
1583 if we're at the first frag, check it's size > 0;
1584 if we're not at the first frag, then for sure
1585 the offset is > 0. */
1586 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1587 const int add_symbol
= (frag_now
!= frag_first
)
1588 || (frag_now_fix () > 0);
1591 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1595 mapping_state_2 (state
, 0);
1598 /* Same as mapping_state, but MAX_CHARS bytes have already been
1599 allocated. Put the mapping symbol that far back. */
1602 mapping_state_2 (enum mstate state
, int max_chars
)
1604 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1606 if (!SEG_NORMAL (now_seg
))
1609 if (mapstate
== state
)
1610 /* The mapping symbol has already been emitted.
1611 There is nothing else to do. */
1614 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1615 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1618 #define mapping_state(x) /* nothing */
1619 #define mapping_state_2(x, y) /* nothing */
1622 /* Directives: sectioning and alignment. */
1625 s_bss (int ignore ATTRIBUTE_UNUSED
)
1627 /* We don't support putting frags in the BSS segment, we fake it by
1628 marking in_bss, then looking at s_skip for clues. */
1629 subseg_set (bss_section
, 0);
1630 demand_empty_rest_of_line ();
1631 mapping_state (MAP_DATA
);
1635 s_even (int ignore ATTRIBUTE_UNUSED
)
1637 /* Never make frag if expect extra pass. */
1639 frag_align (1, 0, 0);
1641 record_alignment (now_seg
, 1);
1643 demand_empty_rest_of_line ();
1646 /* Directives: Literal pools. */
1648 static literal_pool
*
1649 find_literal_pool (int size
)
1653 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1655 if (pool
->section
== now_seg
1656 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1663 static literal_pool
*
1664 find_or_make_literal_pool (int size
)
1666 /* Next literal pool ID number. */
1667 static unsigned int latest_pool_num
= 1;
1670 pool
= find_literal_pool (size
);
1674 /* Create a new pool. */
1675 pool
= XNEW (literal_pool
);
1679 /* Currently we always put the literal pool in the current text
1680 section. If we were generating "small" model code where we
1681 knew that all code and initialised data was within 1MB then
1682 we could output literals to mergeable, read-only data
1685 pool
->next_free_entry
= 0;
1686 pool
->section
= now_seg
;
1687 pool
->sub_section
= now_subseg
;
1689 pool
->next
= list_of_pools
;
1690 pool
->symbol
= NULL
;
1692 /* Add it to the list. */
1693 list_of_pools
= pool
;
1696 /* New pools, and emptied pools, will have a NULL symbol. */
1697 if (pool
->symbol
== NULL
)
1699 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1700 (valueT
) 0, &zero_address_frag
);
1701 pool
->id
= latest_pool_num
++;
1708 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1709 Return TRUE on success, otherwise return FALSE. */
1711 add_to_lit_pool (expressionS
*exp
, int size
)
1716 pool
= find_or_make_literal_pool (size
);
1718 /* Check if this literal value is already in the pool. */
1719 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1721 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1723 if ((litexp
->X_op
== exp
->X_op
)
1724 && (exp
->X_op
== O_constant
)
1725 && (litexp
->X_add_number
== exp
->X_add_number
)
1726 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1729 if ((litexp
->X_op
== exp
->X_op
)
1730 && (exp
->X_op
== O_symbol
)
1731 && (litexp
->X_add_number
== exp
->X_add_number
)
1732 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1733 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1737 /* Do we need to create a new entry? */
1738 if (entry
== pool
->next_free_entry
)
1740 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1742 set_syntax_error (_("literal pool overflow"));
1746 pool
->literals
[entry
].exp
= *exp
;
1747 pool
->next_free_entry
+= 1;
1748 if (exp
->X_op
== O_big
)
1750 /* PR 16688: Bignums are held in a single global array. We must
1751 copy and preserve that value now, before it is overwritten. */
1752 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1754 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1755 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1758 pool
->literals
[entry
].bignum
= NULL
;
1761 exp
->X_op
= O_symbol
;
1762 exp
->X_add_number
= ((int) entry
) * size
;
1763 exp
->X_add_symbol
= pool
->symbol
;
1768 /* Can't use symbol_new here, so have to create a symbol and then at
1769 a later date assign it a value. That's what these functions do. */
1772 symbol_locate (symbolS
* symbolP
,
1773 const char *name
,/* It is copied, the caller can modify. */
1774 segT segment
, /* Segment identifier (SEG_<something>). */
1775 valueT valu
, /* Symbol value. */
1776 fragS
* frag
) /* Associated fragment. */
1779 char *preserved_copy_of_name
;
1781 name_length
= strlen (name
) + 1; /* +1 for \0. */
1782 obstack_grow (¬es
, name
, name_length
);
1783 preserved_copy_of_name
= obstack_finish (¬es
);
1785 #ifdef tc_canonicalize_symbol_name
1786 preserved_copy_of_name
=
1787 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1790 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1792 S_SET_SEGMENT (symbolP
, segment
);
1793 S_SET_VALUE (symbolP
, valu
);
1794 symbol_clear_list_pointers (symbolP
);
1796 symbol_set_frag (symbolP
, frag
);
1798 /* Link to end of symbol chain. */
1800 extern int symbol_table_frozen
;
1802 if (symbol_table_frozen
)
1806 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1808 obj_symbol_new_hook (symbolP
);
1810 #ifdef tc_symbol_new_hook
1811 tc_symbol_new_hook (symbolP
);
1815 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1816 #endif /* DEBUG_SYMS */
1821 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1828 for (align
= 2; align
<= 4; align
++)
1830 int size
= 1 << align
;
1832 pool
= find_literal_pool (size
);
1833 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1836 /* Align pool as you have word accesses.
1837 Only make a frag if we have to. */
1839 frag_align (align
, 0, 0);
1841 mapping_state (MAP_DATA
);
1843 record_alignment (now_seg
, align
);
1845 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1847 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1848 (valueT
) frag_now_fix (), frag_now
);
1849 symbol_table_insert (pool
->symbol
);
1851 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1853 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1855 if (exp
->X_op
== O_big
)
1857 /* PR 16688: Restore the global bignum value. */
1858 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1859 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1860 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1863 /* First output the expression in the instruction to the pool. */
1864 emit_expr (exp
, size
); /* .word|.xword */
1866 if (exp
->X_op
== O_big
)
1868 free (pool
->literals
[entry
].bignum
);
1869 pool
->literals
[entry
].bignum
= NULL
;
1873 /* Mark the pool as empty. */
1874 pool
->next_free_entry
= 0;
1875 pool
->symbol
= NULL
;
1880 /* Forward declarations for functions below, in the MD interface
1882 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1883 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1885 /* Directives: Data. */
1886 /* N.B. the support for relocation suffix in this directive needs to be
1887 implemented properly. */
1890 s_aarch64_elf_cons (int nbytes
)
1894 #ifdef md_flush_pending_output
1895 md_flush_pending_output ();
1898 if (is_it_end_of_statement ())
1900 demand_empty_rest_of_line ();
1904 #ifdef md_cons_align
1905 md_cons_align (nbytes
);
1908 mapping_state (MAP_DATA
);
1911 struct reloc_table_entry
*reloc
;
1915 if (exp
.X_op
!= O_symbol
)
1916 emit_expr (&exp
, (unsigned int) nbytes
);
1919 skip_past_char (&input_line_pointer
, '#');
1920 if (skip_past_char (&input_line_pointer
, ':'))
1922 reloc
= find_reloc_table_entry (&input_line_pointer
);
1924 as_bad (_("unrecognized relocation suffix"));
1926 as_bad (_("unimplemented relocation suffix"));
1927 ignore_rest_of_line ();
1931 emit_expr (&exp
, (unsigned int) nbytes
);
1934 while (*input_line_pointer
++ == ',');
1936 /* Put terminator back into stream. */
1937 input_line_pointer
--;
1938 demand_empty_rest_of_line ();
1941 #endif /* OBJ_ELF */
1943 /* Output a 32-bit word, but mark as an instruction. */
1946 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1950 #ifdef md_flush_pending_output
1951 md_flush_pending_output ();
1954 if (is_it_end_of_statement ())
1956 demand_empty_rest_of_line ();
1960 /* Sections are assumed to start aligned. In executable section, there is no
1961 MAP_DATA symbol pending. So we only align the address during
1962 MAP_DATA --> MAP_INSN transition.
1963 For other sections, this is not guaranteed. */
1964 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1965 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1966 frag_align_code (2, 0);
1969 mapping_state (MAP_INSN
);
1975 if (exp
.X_op
!= O_constant
)
1977 as_bad (_("constant expression required"));
1978 ignore_rest_of_line ();
1982 if (target_big_endian
)
1984 unsigned int val
= exp
.X_add_number
;
1985 exp
.X_add_number
= SWAP_32 (val
);
1987 emit_expr (&exp
, 4);
1989 while (*input_line_pointer
++ == ',');
1991 /* Put terminator back into stream. */
1992 input_line_pointer
--;
1993 demand_empty_rest_of_line ();
1997 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2000 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2006 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2007 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2009 demand_empty_rest_of_line ();
2012 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2015 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2019 /* Since we're just labelling the code, there's no need to define a
2022 /* Make sure there is enough room in this frag for the following
2023 blr. This trick only works if the blr follows immediately after
2024 the .tlsdesc directive. */
2026 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2027 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2029 demand_empty_rest_of_line ();
2032 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2035 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2041 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2042 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2044 demand_empty_rest_of_line ();
2046 #endif /* OBJ_ELF */
2048 static void s_aarch64_arch (int);
2049 static void s_aarch64_cpu (int);
2050 static void s_aarch64_arch_extension (int);
2052 /* This table describes all the machine specific pseudo-ops the assembler
2053 has to support. The fields are:
2054 pseudo-op name without dot
2055 function to call to execute this pseudo-op
2056 Integer arg to pass to the function. */
2058 const pseudo_typeS md_pseudo_table
[] = {
2059 /* Never called because '.req' does not start a line. */
2061 {"unreq", s_unreq
, 0},
2063 {"even", s_even
, 0},
2064 {"ltorg", s_ltorg
, 0},
2065 {"pool", s_ltorg
, 0},
2066 {"cpu", s_aarch64_cpu
, 0},
2067 {"arch", s_aarch64_arch
, 0},
2068 {"arch_extension", s_aarch64_arch_extension
, 0},
2069 {"inst", s_aarch64_inst
, 0},
2071 {"tlsdescadd", s_tlsdescadd
, 0},
2072 {"tlsdesccall", s_tlsdesccall
, 0},
2073 {"tlsdescldr", s_tlsdescldr
, 0},
2074 {"word", s_aarch64_elf_cons
, 4},
2075 {"long", s_aarch64_elf_cons
, 4},
2076 {"xword", s_aarch64_elf_cons
, 8},
2077 {"dword", s_aarch64_elf_cons
, 8},
2083 /* Check whether STR points to a register name followed by a comma or the
2084 end of line; REG_TYPE indicates which register types are checked
2085 against. Return TRUE if STR is such a register name; otherwise return
2086 FALSE. The function does not intend to produce any diagnostics, but since
2087 the register parser aarch64_reg_parse, which is called by this function,
2088 does produce diagnostics, we call clear_error to clear any diagnostics
2089 that may be generated by aarch64_reg_parse.
2090 Also, the function returns FALSE directly if there is any user error
2091 present at the function entry. This prevents the existing diagnostics
2092 state from being spoiled.
2093 The function currently serves parse_constant_immediate and
2094 parse_big_immediate only. */
2096 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2100 /* Prevent the diagnostics state from being spoiled. */
2104 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2106 /* Clear the parsing error that may be set by the reg parser. */
2109 if (reg
== PARSE_FAIL
)
2112 skip_whitespace (str
);
2113 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2119 /* Parser functions used exclusively in instruction operands. */
2121 /* Parse an immediate expression which may not be constant.
2123 To prevent the expression parser from pushing a register name
2124 into the symbol table as an undefined symbol, firstly a check is
2125 done to find out whether STR is a register of type REG_TYPE followed
2126 by a comma or the end of line. Return FALSE if STR is such a string. */
2129 parse_immediate_expression (char **str
, expressionS
*exp
,
2130 aarch64_reg_type reg_type
)
2132 if (reg_name_p (*str
, reg_type
))
2134 set_recoverable_error (_("immediate operand required"));
2138 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2140 if (exp
->X_op
== O_absent
)
2142 set_fatal_syntax_error (_("missing immediate expression"));
2149 /* Constant immediate-value read function for use in insn parsing.
2150 STR points to the beginning of the immediate (with the optional
2151 leading #); *VAL receives the value. REG_TYPE says which register
2152 names should be treated as registers rather than as symbolic immediates.
2154 Return TRUE on success; otherwise return FALSE. */
2157 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2161 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2164 if (exp
.X_op
!= O_constant
)
2166 set_syntax_error (_("constant expression required"));
2170 *val
= exp
.X_add_number
;
2175 encode_imm_float_bits (uint32_t imm
)
2177 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2178 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2181 /* Return TRUE if the single-precision floating-point value encoded in IMM
2182 can be expressed in the AArch64 8-bit signed floating-point format with
2183 3-bit exponent and normalized 4 bits of precision; in other words, the
2184 floating-point value must be expressable as
2185 (+/-) n / 16 * power (2, r)
2186 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2189 aarch64_imm_float_p (uint32_t imm
)
2191 /* If a single-precision floating-point value has the following bit
2192 pattern, it can be expressed in the AArch64 8-bit floating-point
2195 3 32222222 2221111111111
2196 1 09876543 21098765432109876543210
2197 n Eeeeeexx xxxx0000000000000000000
2199 where n, e and each x are either 0 or 1 independently, with
2204 /* Prepare the pattern for 'Eeeeee'. */
2205 if (((imm
>> 30) & 0x1) == 0)
2206 pattern
= 0x3e000000;
2208 pattern
= 0x40000000;
2210 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2211 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2214 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2215 as an IEEE float without any loss of precision. Store the value in
2219 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2221 /* If a double-precision floating-point value has the following bit
2222 pattern, it can be expressed in a float:
2224 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2225 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2226 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2228 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2229 if Eeee_eeee != 1111_1111
2231 where n, e, s and S are either 0 or 1 independently and where ~ is the
2235 uint32_t high32
= imm
>> 32;
2236 uint32_t low32
= imm
;
2238 /* Lower 29 bits need to be 0s. */
2239 if ((imm
& 0x1fffffff) != 0)
2242 /* Prepare the pattern for 'Eeeeeeeee'. */
2243 if (((high32
>> 30) & 0x1) == 0)
2244 pattern
= 0x38000000;
2246 pattern
= 0x40000000;
2249 if ((high32
& 0x78000000) != pattern
)
2252 /* Check Eeee_eeee != 1111_1111. */
2253 if ((high32
& 0x7ff00000) == 0x47f00000)
2256 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2257 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2258 | (low32
>> 29)); /* 3 S bits. */
2262 /* Return true if we should treat OPERAND as a double-precision
2263 floating-point operand rather than a single-precision one. */
2265 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2267 /* Check for unsuffixed SVE registers, which are allowed
2268 for LDR and STR but not in instructions that require an
2269 immediate. We get better error messages if we arbitrarily
2270 pick one size, parse the immediate normally, and then
2271 report the match failure in the normal way. */
2272 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2273 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2276 /* Parse a floating-point immediate. Return TRUE on success and return the
2277 value in *IMMED in the format of IEEE754 single-precision encoding.
2278 *CCP points to the start of the string; DP_P is TRUE when the immediate
2279 is expected to be in double-precision (N.B. this only matters when
2280 hexadecimal representation is involved). REG_TYPE says which register
2281 names should be treated as registers rather than as symbolic immediates.
2283 This routine accepts any IEEE float; it is up to the callers to reject
2287 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2288 aarch64_reg_type reg_type
)
2292 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2294 unsigned fpword
= 0;
2295 bfd_boolean hex_p
= FALSE
;
2297 skip_past_char (&str
, '#');
2300 skip_whitespace (fpnum
);
2302 if (strncmp (fpnum
, "0x", 2) == 0)
2304 /* Support the hexadecimal representation of the IEEE754 encoding.
2305 Double-precision is expected when DP_P is TRUE, otherwise the
2306 representation should be in single-precision. */
2307 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2312 if (!can_convert_double_to_float (val
, &fpword
))
2315 else if ((uint64_t) val
> 0xffffffff)
2322 else if (reg_name_p (str
, reg_type
))
2324 set_recoverable_error (_("immediate operand required"));
2332 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2335 /* Our FP word must be 32 bits (single-precision FP). */
2336 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2338 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2348 set_fatal_syntax_error (_("invalid floating-point constant"));
2352 /* Less-generic immediate-value read function with the possibility of loading
2353 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2356 To prevent the expression parser from pushing a register name into the
2357 symbol table as an undefined symbol, a check is firstly done to find
2358 out whether STR is a register of type REG_TYPE followed by a comma or
2359 the end of line. Return FALSE if STR is such a register. */
2362 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2366 if (reg_name_p (ptr
, reg_type
))
2368 set_syntax_error (_("immediate operand required"));
2372 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2374 if (inst
.reloc
.exp
.X_op
== O_constant
)
2375 *imm
= inst
.reloc
.exp
.X_add_number
;
2382 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2383 if NEED_LIBOPCODES is non-zero, the fixup will need
2384 assistance from the libopcodes. */
2387 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2388 const aarch64_opnd_info
*operand
,
2389 int need_libopcodes_p
)
2391 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2392 reloc
->opnd
= operand
->type
;
2393 if (need_libopcodes_p
)
2394 reloc
->need_libopcodes_p
= 1;
2397 /* Return TRUE if the instruction needs to be fixed up later internally by
2398 the GAS; otherwise return FALSE. */
2400 static inline bfd_boolean
2401 aarch64_gas_internal_fixup_p (void)
2403 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2406 /* Assign the immediate value to the relevant field in *OPERAND if
2407 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2408 needs an internal fixup in a later stage.
2409 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2410 IMM.VALUE that may get assigned with the constant. */
2412 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2413 aarch64_opnd_info
*operand
,
2415 int need_libopcodes_p
,
2418 if (reloc
->exp
.X_op
== O_constant
)
2421 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2423 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2424 reloc
->type
= BFD_RELOC_UNUSED
;
2428 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2429 /* Tell libopcodes to ignore this operand or not. This is helpful
2430 when one of the operands needs to be fixed up later but we need
2431 libopcodes to check the other operands. */
2432 operand
->skip
= skip_p
;
2436 /* Relocation modifiers. Each entry in the table contains the textual
2437 name for the relocation which may be placed before a symbol used as
2438 a load/store offset, or add immediate. It must be surrounded by a
2439 leading and trailing colon, for example:
2441 ldr x0, [x1, #:rello:varsym]
2442 add x0, x1, #:rello:varsym */
2444 struct reloc_table_entry
2448 bfd_reloc_code_real_type adr_type
;
2449 bfd_reloc_code_real_type adrp_type
;
2450 bfd_reloc_code_real_type movw_type
;
2451 bfd_reloc_code_real_type add_type
;
2452 bfd_reloc_code_real_type ldst_type
;
2453 bfd_reloc_code_real_type ld_literal_type
;
2456 static struct reloc_table_entry reloc_table
[] = {
2457 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2462 BFD_RELOC_AARCH64_ADD_LO12
,
2463 BFD_RELOC_AARCH64_LDST_LO12
,
2466 /* Higher 21 bits of pc-relative page offset: ADRP */
2469 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2475 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2478 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2484 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2488 BFD_RELOC_AARCH64_MOVW_G0
,
2493 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2497 BFD_RELOC_AARCH64_MOVW_G0_S
,
2502 /* Less significant bits 0-15 of address/value: MOVK, no check */
2506 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2511 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2515 BFD_RELOC_AARCH64_MOVW_G1
,
2520 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2524 BFD_RELOC_AARCH64_MOVW_G1_S
,
2529 /* Less significant bits 16-31 of address/value: MOVK, no check */
2533 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2538 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2542 BFD_RELOC_AARCH64_MOVW_G2
,
2547 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2551 BFD_RELOC_AARCH64_MOVW_G2_S
,
2556 /* Less significant bits 32-47 of address/value: MOVK, no check */
2560 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2565 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2569 BFD_RELOC_AARCH64_MOVW_G3
,
2574 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2578 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2583 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2587 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2592 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2596 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2601 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2605 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2610 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2614 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2619 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2623 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2628 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2632 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2637 /* Get to the page containing GOT entry for a symbol. */
2640 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2644 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2646 /* 12 bit offset into the page containing GOT entry for that symbol. */
2652 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2655 /* 0-15 bits of address/value: MOVk, no check. */
2659 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2664 /* Most significant bits 16-31 of address/value: MOVZ. */
2668 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2673 /* 15 bit offset into the page containing GOT entry for that symbol. */
2679 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2682 /* Get to the page containing GOT TLS entry for a symbol */
2683 {"gottprel_g0_nc", 0,
2686 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2691 /* Get to the page containing GOT TLS entry for a symbol */
2695 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2700 /* Get to the page containing GOT TLS entry for a symbol */
2702 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2703 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2709 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2714 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2718 /* Lower 16 bits address/value: MOVk. */
2722 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2727 /* Most significant bits 16-31 of address/value: MOVZ. */
2731 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2736 /* Get to the page containing GOT TLS entry for a symbol */
2738 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2739 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2743 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2745 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2750 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2751 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2754 /* Get to the page containing GOT TLS entry for a symbol.
2755 The same as GD, we allocate two consecutive GOT slots
2756 for module index and module offset, the only difference
2757 with GD is the module offset should be initialized to
2758 zero without any outstanding runtime relocation. */
2760 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2761 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2767 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2768 {"tlsldm_lo12_nc", 0,
2772 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2776 /* 12 bit offset into the module TLS base address. */
2781 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2782 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2785 /* Same as dtprel_lo12, no overflow check. */
2786 {"dtprel_lo12_nc", 0,
2790 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2791 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2794 /* bits[23:12] of offset to the module TLS base address. */
2799 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2803 /* bits[15:0] of offset to the module TLS base address. */
2807 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2812 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2816 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2821 /* bits[31:16] of offset to the module TLS base address. */
2825 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2830 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2834 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2839 /* bits[47:32] of offset to the module TLS base address. */
2843 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2848 /* Lower 16 bit offset into GOT entry for a symbol */
2849 {"tlsdesc_off_g0_nc", 0,
2852 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2857 /* Higher 16 bit offset into GOT entry for a symbol */
2858 {"tlsdesc_off_g1", 0,
2861 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2866 /* Get to the page containing GOT TLS entry for a symbol */
2869 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2873 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2875 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2876 {"gottprel_lo12", 0,
2881 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2884 /* Get tp offset for a symbol. */
2889 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2893 /* Get tp offset for a symbol. */
2898 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2899 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2902 /* Get tp offset for a symbol. */
2907 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2911 /* Get tp offset for a symbol. */
2912 {"tprel_lo12_nc", 0,
2916 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2917 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2920 /* Most significant bits 32-47 of address/value: MOVZ. */
2924 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2929 /* Most significant bits 16-31 of address/value: MOVZ. */
2933 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2938 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2942 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2947 /* Most significant bits 0-15 of address/value: MOVZ. */
2951 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2956 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2960 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2965 /* 15bit offset from got entry to base address of GOT table. */
2971 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2974 /* 14bit offset from got entry to base address of GOT table. */
2980 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2984 /* Given the address of a pointer pointing to the textual name of a
2985 relocation as may appear in assembler source, attempt to find its
2986 details in reloc_table. The pointer will be updated to the character
2987 after the trailing colon. On failure, NULL will be returned;
2988 otherwise return the reloc_table_entry. */
2990 static struct reloc_table_entry
*
2991 find_reloc_table_entry (char **str
)
2994 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2996 int length
= strlen (reloc_table
[i
].name
);
2998 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2999 && (*str
)[length
] == ':')
3001 *str
+= (length
+ 1);
3002 return &reloc_table
[i
];
3009 /* Mode argument to parse_shift and parser_shifter_operand. */
3010 enum parse_shift_mode
3012 SHIFTED_NONE
, /* no shifter allowed */
3013 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3015 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3017 SHIFTED_LSL
, /* bare "lsl #n" */
3018 SHIFTED_MUL
, /* bare "mul #n" */
3019 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3020 SHIFTED_MUL_VL
, /* "mul vl" */
3021 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3024 /* Parse a <shift> operator on an AArch64 data processing instruction.
3025 Return TRUE on success; otherwise return FALSE. */
3027 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3029 const struct aarch64_name_value_pair
*shift_op
;
3030 enum aarch64_modifier_kind kind
;
3036 for (p
= *str
; ISALPHA (*p
); p
++)
3041 set_syntax_error (_("shift expression expected"));
3045 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3047 if (shift_op
== NULL
)
3049 set_syntax_error (_("shift operator expected"));
3053 kind
= aarch64_get_operand_modifier (shift_op
);
3055 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3057 set_syntax_error (_("invalid use of 'MSL'"));
3061 if (kind
== AARCH64_MOD_MUL
3062 && mode
!= SHIFTED_MUL
3063 && mode
!= SHIFTED_MUL_VL
)
3065 set_syntax_error (_("invalid use of 'MUL'"));
3071 case SHIFTED_LOGIC_IMM
:
3072 if (aarch64_extend_operator_p (kind
))
3074 set_syntax_error (_("extending shift is not permitted"));
3079 case SHIFTED_ARITH_IMM
:
3080 if (kind
== AARCH64_MOD_ROR
)
3082 set_syntax_error (_("'ROR' shift is not permitted"));
3088 if (kind
!= AARCH64_MOD_LSL
)
3090 set_syntax_error (_("only 'LSL' shift is permitted"));
3096 if (kind
!= AARCH64_MOD_MUL
)
3098 set_syntax_error (_("only 'MUL' is permitted"));
3103 case SHIFTED_MUL_VL
:
3104 /* "MUL VL" consists of two separate tokens. Require the first
3105 token to be "MUL" and look for a following "VL". */
3106 if (kind
== AARCH64_MOD_MUL
)
3108 skip_whitespace (p
);
3109 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3112 kind
= AARCH64_MOD_MUL_VL
;
3116 set_syntax_error (_("only 'MUL VL' is permitted"));
3119 case SHIFTED_REG_OFFSET
:
3120 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3121 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3123 set_fatal_syntax_error
3124 (_("invalid shift for the register offset addressing mode"));
3129 case SHIFTED_LSL_MSL
:
3130 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3132 set_syntax_error (_("invalid shift operator"));
3141 /* Whitespace can appear here if the next thing is a bare digit. */
3142 skip_whitespace (p
);
3144 /* Parse shift amount. */
3146 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3147 exp
.X_op
= O_absent
;
3150 if (is_immediate_prefix (*p
))
3155 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3157 if (kind
== AARCH64_MOD_MUL_VL
)
3158 /* For consistency, give MUL VL the same shift amount as an implicit
3160 operand
->shifter
.amount
= 1;
3161 else if (exp
.X_op
== O_absent
)
3163 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3165 set_syntax_error (_("missing shift amount"));
3168 operand
->shifter
.amount
= 0;
3170 else if (exp
.X_op
!= O_constant
)
3172 set_syntax_error (_("constant shift amount required"));
3175 /* For parsing purposes, MUL #n has no inherent range. The range
3176 depends on the operand and will be checked by operand-specific
3178 else if (kind
!= AARCH64_MOD_MUL
3179 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3181 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3186 operand
->shifter
.amount
= exp
.X_add_number
;
3187 operand
->shifter
.amount_present
= 1;
3190 operand
->shifter
.operator_present
= 1;
3191 operand
->shifter
.kind
= kind
;
3197 /* Parse a <shifter_operand> for a data processing instruction:
3200 #<immediate>, LSL #imm
3202 Validation of immediate operands is deferred to md_apply_fix.
3204 Return TRUE on success; otherwise return FALSE. */
3207 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3208 enum parse_shift_mode mode
)
3212 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3217 /* Accept an immediate expression. */
3218 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3221 /* Accept optional LSL for arithmetic immediate values. */
3222 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3223 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3226 /* Not accept any shifter for logical immediate values. */
3227 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3228 && parse_shift (&p
, operand
, mode
))
3230 set_syntax_error (_("unexpected shift operator"));
3238 /* Parse a <shifter_operand> for a data processing instruction:
3243 #<immediate>, LSL #imm
3245 where <shift> is handled by parse_shift above, and the last two
3246 cases are handled by the function above.
3248 Validation of immediate operands is deferred to md_apply_fix.
3250 Return TRUE on success; otherwise return FALSE. */
3253 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3254 enum parse_shift_mode mode
)
3256 const reg_entry
*reg
;
3257 aarch64_opnd_qualifier_t qualifier
;
3258 enum aarch64_operand_class opd_class
3259 = aarch64_get_operand_class (operand
->type
);
3261 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3264 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3266 set_syntax_error (_("unexpected register in the immediate operand"));
3270 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3272 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3276 operand
->reg
.regno
= reg
->number
;
3277 operand
->qualifier
= qualifier
;
3279 /* Accept optional shift operation on register. */
3280 if (! skip_past_comma (str
))
3283 if (! parse_shift (str
, operand
, mode
))
3288 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3291 (_("integer register expected in the extended/shifted operand "
3296 /* We have a shifted immediate variable. */
3297 return parse_shifter_operand_imm (str
, operand
, mode
);
3300 /* Return TRUE on success; return FALSE otherwise. */
3303 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3304 enum parse_shift_mode mode
)
3308 /* Determine if we have the sequence of characters #: or just :
3309 coming next. If we do, then we check for a :rello: relocation
3310 modifier. If we don't, punt the whole lot to
3311 parse_shifter_operand. */
3313 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3315 struct reloc_table_entry
*entry
;
3323 /* Try to parse a relocation. Anything else is an error. */
3324 if (!(entry
= find_reloc_table_entry (str
)))
3326 set_syntax_error (_("unknown relocation modifier"));
3330 if (entry
->add_type
== 0)
3333 (_("this relocation modifier is not allowed on this instruction"));
3337 /* Save str before we decompose it. */
3340 /* Next, we parse the expression. */
3341 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3344 /* Record the relocation type (use the ADD variant here). */
3345 inst
.reloc
.type
= entry
->add_type
;
3346 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3348 /* If str is empty, we've reached the end, stop here. */
3352 /* Otherwise, we have a shifted reloc modifier, so rewind to
3353 recover the variable name and continue parsing for the shifter. */
3355 return parse_shifter_operand_imm (str
, operand
, mode
);
3358 return parse_shifter_operand (str
, operand
, mode
);
3361 /* Parse all forms of an address expression. Information is written
3362 to *OPERAND and/or inst.reloc.
3364 The A64 instruction set has the following addressing modes:
3367 [base] // in SIMD ld/st structure
3368 [base{,#0}] // in ld/st exclusive
3370 [base,Xm{,LSL #imm}]
3371 [base,Xm,SXTX {#imm}]
3372 [base,Wm,(S|U)XTW {#imm}]
3377 [base],Xm // in SIMD ld/st structure
3378 PC-relative (literal)
3382 [base,Zm.D{,LSL #imm}]
3383 [base,Zm.S,(S|U)XTW {#imm}]
3384 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3387 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3388 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3389 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3391 (As a convenience, the notation "=immediate" is permitted in conjunction
3392 with the pc-relative literal load instructions to automatically place an
3393 immediate value or symbolic address in a nearby literal pool and generate
3394 a hidden label which references it.)
3396 Upon a successful parsing, the address structure in *OPERAND will be
3397 filled in the following way:
3399 .base_regno = <base>
3400 .offset.is_reg // 1 if the offset is a register
3402 .offset.regno = <Rm>
3404 For different addressing modes defined in the A64 ISA:
3407 .pcrel=0; .preind=1; .postind=0; .writeback=0
3409 .pcrel=0; .preind=1; .postind=0; .writeback=1
3411 .pcrel=0; .preind=0; .postind=1; .writeback=1
3412 PC-relative (literal)
3413 .pcrel=1; .preind=1; .postind=0; .writeback=0
3415 The shift/extension information, if any, will be stored in .shifter.
3416 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3417 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3418 corresponding register.
3420 BASE_TYPE says which types of base register should be accepted and
3421 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3422 is the type of shifter that is allowed for immediate offsets,
3423 or SHIFTED_NONE if none.
3425 In all other respects, it is the caller's responsibility to check
3426 for addressing modes not supported by the instruction, and to set
3430 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3431 aarch64_opnd_qualifier_t
*base_qualifier
,
3432 aarch64_opnd_qualifier_t
*offset_qualifier
,
3433 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3434 enum parse_shift_mode imm_shift_mode
)
3437 const reg_entry
*reg
;
3438 expressionS
*exp
= &inst
.reloc
.exp
;
3440 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3441 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3442 if (! skip_past_char (&p
, '['))
3444 /* =immediate or label. */
3445 operand
->addr
.pcrel
= 1;
3446 operand
->addr
.preind
= 1;
3448 /* #:<reloc_op>:<symbol> */
3449 skip_past_char (&p
, '#');
3450 if (skip_past_char (&p
, ':'))
3452 bfd_reloc_code_real_type ty
;
3453 struct reloc_table_entry
*entry
;
3455 /* Try to parse a relocation modifier. Anything else is
3457 entry
= find_reloc_table_entry (&p
);
3460 set_syntax_error (_("unknown relocation modifier"));
3464 switch (operand
->type
)
3466 case AARCH64_OPND_ADDR_PCREL21
:
3468 ty
= entry
->adr_type
;
3472 ty
= entry
->ld_literal_type
;
3479 (_("this relocation modifier is not allowed on this "
3485 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3487 set_syntax_error (_("invalid relocation expression"));
3491 /* #:<reloc_op>:<expr> */
3492 /* Record the relocation type. */
3493 inst
.reloc
.type
= ty
;
3494 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3499 if (skip_past_char (&p
, '='))
3500 /* =immediate; need to generate the literal in the literal pool. */
3501 inst
.gen_lit_pool
= 1;
3503 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3505 set_syntax_error (_("invalid address"));
3516 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3517 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3519 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3522 operand
->addr
.base_regno
= reg
->number
;
3525 if (skip_past_comma (&p
))
3528 operand
->addr
.preind
= 1;
3530 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3533 if (!aarch64_check_reg_type (reg
, offset_type
))
3535 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3540 operand
->addr
.offset
.regno
= reg
->number
;
3541 operand
->addr
.offset
.is_reg
= 1;
3542 /* Shifted index. */
3543 if (skip_past_comma (&p
))
3546 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3547 /* Use the diagnostics set in parse_shift, so not set new
3548 error message here. */
3552 [base,Xm{,LSL #imm}]
3553 [base,Xm,SXTX {#imm}]
3554 [base,Wm,(S|U)XTW {#imm}] */
3555 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3556 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3557 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3559 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3561 set_syntax_error (_("invalid use of 32-bit register offset"));
3564 if (aarch64_get_qualifier_esize (*base_qualifier
)
3565 != aarch64_get_qualifier_esize (*offset_qualifier
))
3567 set_syntax_error (_("offset has different size from base"));
3571 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3573 set_syntax_error (_("invalid use of 64-bit register offset"));
3579 /* [Xn,#:<reloc_op>:<symbol> */
3580 skip_past_char (&p
, '#');
3581 if (skip_past_char (&p
, ':'))
3583 struct reloc_table_entry
*entry
;
3585 /* Try to parse a relocation modifier. Anything else is
3587 if (!(entry
= find_reloc_table_entry (&p
)))
3589 set_syntax_error (_("unknown relocation modifier"));
3593 if (entry
->ldst_type
== 0)
3596 (_("this relocation modifier is not allowed on this "
3601 /* [Xn,#:<reloc_op>: */
3602 /* We now have the group relocation table entry corresponding to
3603 the name in the assembler source. Next, we parse the
3605 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3607 set_syntax_error (_("invalid relocation expression"));
3611 /* [Xn,#:<reloc_op>:<expr> */
3612 /* Record the load/store relocation type. */
3613 inst
.reloc
.type
= entry
->ldst_type
;
3614 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3618 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3620 set_syntax_error (_("invalid expression in the address"));
3624 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3625 /* [Xn,<expr>,<shifter> */
3626 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3632 if (! skip_past_char (&p
, ']'))
3634 set_syntax_error (_("']' expected"));
3638 if (skip_past_char (&p
, '!'))
3640 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3642 set_syntax_error (_("register offset not allowed in pre-indexed "
3643 "addressing mode"));
3647 operand
->addr
.writeback
= 1;
3649 else if (skip_past_comma (&p
))
3652 operand
->addr
.postind
= 1;
3653 operand
->addr
.writeback
= 1;
3655 if (operand
->addr
.preind
)
3657 set_syntax_error (_("cannot combine pre- and post-indexing"));
3661 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3665 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3667 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3671 operand
->addr
.offset
.regno
= reg
->number
;
3672 operand
->addr
.offset
.is_reg
= 1;
3674 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3677 set_syntax_error (_("invalid expression in the address"));
3682 /* If at this point neither .preind nor .postind is set, we have a
3683 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3684 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3686 if (operand
->addr
.writeback
)
3689 set_syntax_error (_("missing offset in the pre-indexed address"));
3693 operand
->addr
.preind
= 1;
3694 inst
.reloc
.exp
.X_op
= O_constant
;
3695 inst
.reloc
.exp
.X_add_number
= 0;
3702 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3705 parse_address (char **str
, aarch64_opnd_info
*operand
)
3707 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3708 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3709 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3712 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3713 The arguments have the same meaning as for parse_address_main.
3714 Return TRUE on success. */
3716 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3717 aarch64_opnd_qualifier_t
*base_qualifier
,
3718 aarch64_opnd_qualifier_t
*offset_qualifier
)
3720 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3721 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3725 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3726 Return TRUE on success; otherwise return FALSE. */
3728 parse_half (char **str
, int *internal_fixup_p
)
3732 skip_past_char (&p
, '#');
3734 gas_assert (internal_fixup_p
);
3735 *internal_fixup_p
= 0;
3739 struct reloc_table_entry
*entry
;
3741 /* Try to parse a relocation. Anything else is an error. */
3743 if (!(entry
= find_reloc_table_entry (&p
)))
3745 set_syntax_error (_("unknown relocation modifier"));
3749 if (entry
->movw_type
== 0)
3752 (_("this relocation modifier is not allowed on this instruction"));
3756 inst
.reloc
.type
= entry
->movw_type
;
3759 *internal_fixup_p
= 1;
3761 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3768 /* Parse an operand for an ADRP instruction:
3770 Return TRUE on success; otherwise return FALSE. */
3773 parse_adrp (char **str
)
3780 struct reloc_table_entry
*entry
;
3782 /* Try to parse a relocation. Anything else is an error. */
3784 if (!(entry
= find_reloc_table_entry (&p
)))
3786 set_syntax_error (_("unknown relocation modifier"));
3790 if (entry
->adrp_type
== 0)
3793 (_("this relocation modifier is not allowed on this instruction"));
3797 inst
.reloc
.type
= entry
->adrp_type
;
3800 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3802 inst
.reloc
.pc_rel
= 1;
3804 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3811 /* Miscellaneous. */
3813 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3814 of SIZE tokens in which index I gives the token for field value I,
3815 or is null if field value I is invalid. REG_TYPE says which register
3816 names should be treated as registers rather than as symbolic immediates.
3818 Return true on success, moving *STR past the operand and storing the
3819 field value in *VAL. */
3822 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3823 size_t size
, aarch64_reg_type reg_type
)
3829 /* Match C-like tokens. */
3831 while (ISALNUM (*q
))
3834 for (i
= 0; i
< size
; ++i
)
3836 && strncasecmp (array
[i
], p
, q
- p
) == 0
3837 && array
[i
][q
- p
] == 0)
3844 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3847 if (exp
.X_op
== O_constant
3848 && (uint64_t) exp
.X_add_number
< size
)
3850 *val
= exp
.X_add_number
;
3855 /* Use the default error for this operand. */
3859 /* Parse an option for a preload instruction. Returns the encoding for the
3860 option, or PARSE_FAIL. */
3863 parse_pldop (char **str
)
3866 const struct aarch64_name_value_pair
*o
;
3869 while (ISALNUM (*q
))
3872 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3880 /* Parse an option for a barrier instruction. Returns the encoding for the
3881 option, or PARSE_FAIL. */
3884 parse_barrier (char **str
)
3887 const asm_barrier_opt
*o
;
3890 while (ISALPHA (*q
))
3893 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3901 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3902 return 0 if successful. Otherwise return PARSE_FAIL. */
3905 parse_barrier_psb (char **str
,
3906 const struct aarch64_name_value_pair
** hint_opt
)
3909 const struct aarch64_name_value_pair
*o
;
3912 while (ISALPHA (*q
))
3915 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3918 set_fatal_syntax_error
3919 ( _("unknown or missing option to PSB"));
3923 if (o
->value
!= 0x11)
3925 /* PSB only accepts option name 'CSYNC'. */
3927 (_("the specified option is not accepted for PSB"));
3936 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3937 Returns the encoding for the option, or PARSE_FAIL.
3939 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3940 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3942 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3943 field, otherwise as a system register.
3947 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3948 int imple_defined_p
, int pstatefield_p
,
3953 const aarch64_sys_reg
*o
;
3957 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3959 *p
++ = TOLOWER (*q
);
3961 /* Assert that BUF be large enough. */
3962 gas_assert (p
- buf
== q
- *str
);
3964 o
= hash_find (sys_regs
, buf
);
3967 if (!imple_defined_p
)
3971 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3972 unsigned int op0
, op1
, cn
, cm
, op2
;
3974 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3977 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3979 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3986 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3987 as_bad (_("selected processor does not support PSTATE field "
3989 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3990 as_bad (_("selected processor does not support system register "
3992 if (aarch64_sys_reg_deprecated_p (o
))
3993 as_warn (_("system register name '%s' is deprecated and may be "
3994 "removed in a future release"), buf
);
4004 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4005 for the option, or NULL. */
4007 static const aarch64_sys_ins_reg
*
4008 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
4012 const aarch64_sys_ins_reg
*o
;
4015 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4017 *p
++ = TOLOWER (*q
);
4020 o
= hash_find (sys_ins_regs
, buf
);
4024 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
4025 as_bad (_("selected processor does not support system register "
4032 #define po_char_or_fail(chr) do { \
4033 if (! skip_past_char (&str, chr)) \
4037 #define po_reg_or_fail(regtype) do { \
4038 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4039 if (val == PARSE_FAIL) \
4041 set_default_error (); \
4046 #define po_int_reg_or_fail(reg_type) do { \
4047 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4048 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4050 set_default_error (); \
4053 info->reg.regno = reg->number; \
4054 info->qualifier = qualifier; \
4057 #define po_imm_nc_or_fail() do { \
4058 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4062 #define po_imm_or_fail(min, max) do { \
4063 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4065 if (val < min || val > max) \
4067 set_fatal_syntax_error (_("immediate value out of range "\
4068 #min " to "#max)); \
4073 #define po_enum_or_fail(array) do { \
4074 if (!parse_enum_string (&str, &val, array, \
4075 ARRAY_SIZE (array), imm_reg_type)) \
4079 #define po_misc_or_fail(expr) do { \
4084 /* encode the 12-bit imm field of Add/sub immediate */
4085 static inline uint32_t
4086 encode_addsub_imm (uint32_t imm
)
4091 /* encode the shift amount field of Add/sub immediate */
4092 static inline uint32_t
4093 encode_addsub_imm_shift_amount (uint32_t cnt
)
4099 /* encode the imm field of Adr instruction */
4100 static inline uint32_t
4101 encode_adr_imm (uint32_t imm
)
4103 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4104 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4107 /* encode the immediate field of Move wide immediate */
4108 static inline uint32_t
4109 encode_movw_imm (uint32_t imm
)
4114 /* encode the 26-bit offset of unconditional branch */
4115 static inline uint32_t
4116 encode_branch_ofs_26 (uint32_t ofs
)
4118 return ofs
& ((1 << 26) - 1);
4121 /* encode the 19-bit offset of conditional branch and compare & branch */
4122 static inline uint32_t
4123 encode_cond_branch_ofs_19 (uint32_t ofs
)
4125 return (ofs
& ((1 << 19) - 1)) << 5;
4128 /* encode the 19-bit offset of ld literal */
4129 static inline uint32_t
4130 encode_ld_lit_ofs_19 (uint32_t ofs
)
4132 return (ofs
& ((1 << 19) - 1)) << 5;
4135 /* Encode the 14-bit offset of test & branch. */
4136 static inline uint32_t
4137 encode_tst_branch_ofs_14 (uint32_t ofs
)
4139 return (ofs
& ((1 << 14) - 1)) << 5;
4142 /* Encode the 16-bit imm field of svc/hvc/smc. */
4143 static inline uint32_t
4144 encode_svc_imm (uint32_t imm
)
4149 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4150 static inline uint32_t
4151 reencode_addsub_switch_add_sub (uint32_t opcode
)
4153 return opcode
^ (1 << 30);
4156 static inline uint32_t
4157 reencode_movzn_to_movz (uint32_t opcode
)
4159 return opcode
| (1 << 30);
4162 static inline uint32_t
4163 reencode_movzn_to_movn (uint32_t opcode
)
4165 return opcode
& ~(1 << 30);
4168 /* Overall per-instruction processing. */
4170 /* We need to be able to fix up arbitrary expressions in some statements.
4171 This is so that we can handle symbols that are an arbitrary distance from
4172 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4173 which returns part of an address in a form which will be valid for
4174 a data instruction. We do this by pushing the expression into a symbol
4175 in the expr_section, and creating a fix for that. */
4178 fix_new_aarch64 (fragS
* frag
,
4180 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4190 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4194 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4201 /* Diagnostics on operands errors. */
4203 /* By default, output verbose error message.
4204 Disable the verbose error message by -mno-verbose-error. */
4205 static int verbose_error_p
= 1;
4207 #ifdef DEBUG_AARCH64
4208 /* N.B. this is only for the purpose of debugging. */
4209 const char* operand_mismatch_kind_names
[] =
4212 "AARCH64_OPDE_RECOVERABLE",
4213 "AARCH64_OPDE_SYNTAX_ERROR",
4214 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4215 "AARCH64_OPDE_INVALID_VARIANT",
4216 "AARCH64_OPDE_OUT_OF_RANGE",
4217 "AARCH64_OPDE_UNALIGNED",
4218 "AARCH64_OPDE_REG_LIST",
4219 "AARCH64_OPDE_OTHER_ERROR",
4221 #endif /* DEBUG_AARCH64 */
4223 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4225 When multiple errors of different kinds are found in the same assembly
4226 line, only the error of the highest severity will be picked up for
4227 issuing the diagnostics. */
4229 static inline bfd_boolean
4230 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4231 enum aarch64_operand_error_kind rhs
)
4233 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4234 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4235 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4236 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4237 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4238 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4239 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4240 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4244 /* Helper routine to get the mnemonic name from the assembly instruction
4245 line; should only be called for the diagnosis purpose, as there is
4246 string copy operation involved, which may affect the runtime
4247 performance if used in elsewhere. */
4250 get_mnemonic_name (const char *str
)
4252 static char mnemonic
[32];
4255 /* Get the first 15 bytes and assume that the full name is included. */
4256 strncpy (mnemonic
, str
, 31);
4257 mnemonic
[31] = '\0';
4259 /* Scan up to the end of the mnemonic, which must end in white space,
4260 '.', or end of string. */
4261 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4266 /* Append '...' to the truncated long name. */
4267 if (ptr
- mnemonic
== 31)
4268 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4274 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4276 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4277 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4280 /* Data structures storing one user error in the assembly code related to
4283 struct operand_error_record
4285 const aarch64_opcode
*opcode
;
4286 aarch64_operand_error detail
;
4287 struct operand_error_record
*next
;
4290 typedef struct operand_error_record operand_error_record
;
4292 struct operand_errors
4294 operand_error_record
*head
;
4295 operand_error_record
*tail
;
4298 typedef struct operand_errors operand_errors
;
4300 /* Top-level data structure reporting user errors for the current line of
4302 The way md_assemble works is that all opcodes sharing the same mnemonic
4303 name are iterated to find a match to the assembly line. In this data
4304 structure, each of the such opcodes will have one operand_error_record
4305 allocated and inserted. In other words, excessive errors related with
4306 a single opcode are disregarded. */
4307 operand_errors operand_error_report
;
4309 /* Free record nodes. */
4310 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4312 /* Initialize the data structure that stores the operand mismatch
4313 information on assembling one line of the assembly code. */
4315 init_operand_error_report (void)
4317 if (operand_error_report
.head
!= NULL
)
4319 gas_assert (operand_error_report
.tail
!= NULL
);
4320 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4321 free_opnd_error_record_nodes
= operand_error_report
.head
;
4322 operand_error_report
.head
= NULL
;
4323 operand_error_report
.tail
= NULL
;
4326 gas_assert (operand_error_report
.tail
== NULL
);
4329 /* Return TRUE if some operand error has been recorded during the
4330 parsing of the current assembly line using the opcode *OPCODE;
4331 otherwise return FALSE. */
4332 static inline bfd_boolean
4333 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4335 operand_error_record
*record
= operand_error_report
.head
;
4336 return record
&& record
->opcode
== opcode
;
4339 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4340 OPCODE field is initialized with OPCODE.
4341 N.B. only one record for each opcode, i.e. the maximum of one error is
4342 recorded for each instruction template. */
4345 add_operand_error_record (const operand_error_record
* new_record
)
4347 const aarch64_opcode
*opcode
= new_record
->opcode
;
4348 operand_error_record
* record
= operand_error_report
.head
;
4350 /* The record may have been created for this opcode. If not, we need
4352 if (! opcode_has_operand_error_p (opcode
))
4354 /* Get one empty record. */
4355 if (free_opnd_error_record_nodes
== NULL
)
4357 record
= XNEW (operand_error_record
);
4361 record
= free_opnd_error_record_nodes
;
4362 free_opnd_error_record_nodes
= record
->next
;
4364 record
->opcode
= opcode
;
4365 /* Insert at the head. */
4366 record
->next
= operand_error_report
.head
;
4367 operand_error_report
.head
= record
;
4368 if (operand_error_report
.tail
== NULL
)
4369 operand_error_report
.tail
= record
;
4371 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4372 && record
->detail
.index
<= new_record
->detail
.index
4373 && operand_error_higher_severity_p (record
->detail
.kind
,
4374 new_record
->detail
.kind
))
4376 /* In the case of multiple errors found on operands related with a
4377 single opcode, only record the error of the leftmost operand and
4378 only if the error is of higher severity. */
4379 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4380 " the existing error %s on operand %d",
4381 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4382 new_record
->detail
.index
,
4383 operand_mismatch_kind_names
[record
->detail
.kind
],
4384 record
->detail
.index
);
4388 record
->detail
= new_record
->detail
;
4392 record_operand_error_info (const aarch64_opcode
*opcode
,
4393 aarch64_operand_error
*error_info
)
4395 operand_error_record record
;
4396 record
.opcode
= opcode
;
4397 record
.detail
= *error_info
;
4398 add_operand_error_record (&record
);
4401 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4402 error message *ERROR, for operand IDX (count from 0). */
4405 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4406 enum aarch64_operand_error_kind kind
,
4409 aarch64_operand_error info
;
4410 memset(&info
, 0, sizeof (info
));
4414 info
.non_fatal
= FALSE
;
4415 record_operand_error_info (opcode
, &info
);
4419 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4420 enum aarch64_operand_error_kind kind
,
4421 const char* error
, const int *extra_data
)
4423 aarch64_operand_error info
;
4427 info
.data
[0] = extra_data
[0];
4428 info
.data
[1] = extra_data
[1];
4429 info
.data
[2] = extra_data
[2];
4430 info
.non_fatal
= FALSE
;
4431 record_operand_error_info (opcode
, &info
);
4435 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4436 const char* error
, int lower_bound
,
4439 int data
[3] = {lower_bound
, upper_bound
, 0};
4440 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4444 /* Remove the operand error record for *OPCODE. */
4445 static void ATTRIBUTE_UNUSED
4446 remove_operand_error_record (const aarch64_opcode
*opcode
)
4448 if (opcode_has_operand_error_p (opcode
))
4450 operand_error_record
* record
= operand_error_report
.head
;
4451 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4452 operand_error_report
.head
= record
->next
;
4453 record
->next
= free_opnd_error_record_nodes
;
4454 free_opnd_error_record_nodes
= record
;
4455 if (operand_error_report
.head
== NULL
)
4457 gas_assert (operand_error_report
.tail
== record
);
4458 operand_error_report
.tail
= NULL
;
4463 /* Given the instruction in *INSTR, return the index of the best matched
4464 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4466 Return -1 if there is no qualifier sequence; return the first match
4467 if there is multiple matches found. */
4470 find_best_match (const aarch64_inst
*instr
,
4471 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4473 int i
, num_opnds
, max_num_matched
, idx
;
4475 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4478 DEBUG_TRACE ("no operand");
4482 max_num_matched
= 0;
4485 /* For each pattern. */
4486 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4489 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4491 /* Most opcodes has much fewer patterns in the list. */
4492 if (empty_qualifier_sequence_p (qualifiers
))
4494 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4498 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4499 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4502 if (num_matched
> max_num_matched
)
4504 max_num_matched
= num_matched
;
4509 DEBUG_TRACE ("return with %d", idx
);
4513 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4514 corresponding operands in *INSTR. */
4517 assign_qualifier_sequence (aarch64_inst
*instr
,
4518 const aarch64_opnd_qualifier_t
*qualifiers
)
4521 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4522 gas_assert (num_opnds
);
4523 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4524 instr
->operands
[i
].qualifier
= *qualifiers
;
4527 /* Print operands for the diagnosis purpose. */
4530 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4531 const aarch64_opnd_info
*opnds
)
4535 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4539 /* We regard the opcode operand info more, however we also look into
4540 the inst->operands to support the disassembling of the optional
4542 The two operand code should be the same in all cases, apart from
4543 when the operand can be optional. */
4544 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4545 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4548 /* Generate the operand string in STR. */
4549 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4554 strcat (buf
, i
== 0 ? " " : ", ");
4556 /* Append the operand string. */
4561 /* Send to stderr a string as information. */
4564 output_info (const char *format
, ...)
4570 file
= as_where (&line
);
4574 fprintf (stderr
, "%s:%u: ", file
, line
);
4576 fprintf (stderr
, "%s: ", file
);
4578 fprintf (stderr
, _("Info: "));
4579 va_start (args
, format
);
4580 vfprintf (stderr
, format
, args
);
4582 (void) putc ('\n', stderr
);
4585 /* Output one operand error record. */
4588 output_operand_error_record (const operand_error_record
*record
, char *str
)
4590 const aarch64_operand_error
*detail
= &record
->detail
;
4591 int idx
= detail
->index
;
4592 const aarch64_opcode
*opcode
= record
->opcode
;
4593 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4594 : AARCH64_OPND_NIL
);
4596 typedef void (*handler_t
)(const char *format
, ...);
4597 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4599 switch (detail
->kind
)
4601 case AARCH64_OPDE_NIL
:
4604 case AARCH64_OPDE_SYNTAX_ERROR
:
4605 case AARCH64_OPDE_RECOVERABLE
:
4606 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4607 case AARCH64_OPDE_OTHER_ERROR
:
4608 /* Use the prepared error message if there is, otherwise use the
4609 operand description string to describe the error. */
4610 if (detail
->error
!= NULL
)
4613 handler (_("%s -- `%s'"), detail
->error
, str
);
4615 handler (_("%s at operand %d -- `%s'"),
4616 detail
->error
, idx
+ 1, str
);
4620 gas_assert (idx
>= 0);
4621 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4622 aarch64_get_operand_desc (opd_code
), str
);
4626 case AARCH64_OPDE_INVALID_VARIANT
:
4627 handler (_("operand mismatch -- `%s'"), str
);
4628 if (verbose_error_p
)
4630 /* We will try to correct the erroneous instruction and also provide
4631 more information e.g. all other valid variants.
4633 The string representation of the corrected instruction and other
4634 valid variants are generated by
4636 1) obtaining the intermediate representation of the erroneous
4638 2) manipulating the IR, e.g. replacing the operand qualifier;
4639 3) printing out the instruction by calling the printer functions
4640 shared with the disassembler.
4642 The limitation of this method is that the exact input assembly
4643 line cannot be accurately reproduced in some cases, for example an
4644 optional operand present in the actual assembly line will be
4645 omitted in the output; likewise for the optional syntax rules,
4646 e.g. the # before the immediate. Another limitation is that the
4647 assembly symbols and relocation operations in the assembly line
4648 currently cannot be printed out in the error report. Last but not
4649 least, when there is other error(s) co-exist with this error, the
4650 'corrected' instruction may be still incorrect, e.g. given
4651 'ldnp h0,h1,[x0,#6]!'
4652 this diagnosis will provide the version:
4653 'ldnp s0,s1,[x0,#6]!'
4654 which is still not right. */
4655 size_t len
= strlen (get_mnemonic_name (str
));
4659 aarch64_inst
*inst_base
= &inst
.base
;
4660 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4663 reset_aarch64_instruction (&inst
);
4664 inst_base
->opcode
= opcode
;
4666 /* Reset the error report so that there is no side effect on the
4667 following operand parsing. */
4668 init_operand_error_report ();
4671 result
= parse_operands (str
+ len
, opcode
)
4672 && programmer_friendly_fixup (&inst
);
4673 gas_assert (result
);
4674 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4675 NULL
, NULL
, insn_sequence
);
4676 gas_assert (!result
);
4678 /* Find the most matched qualifier sequence. */
4679 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4680 gas_assert (qlf_idx
> -1);
4682 /* Assign the qualifiers. */
4683 assign_qualifier_sequence (inst_base
,
4684 opcode
->qualifiers_list
[qlf_idx
]);
4686 /* Print the hint. */
4687 output_info (_(" did you mean this?"));
4688 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4689 print_operands (buf
, opcode
, inst_base
->operands
);
4690 output_info (_(" %s"), buf
);
4692 /* Print out other variant(s) if there is any. */
4694 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4695 output_info (_(" other valid variant(s):"));
4697 /* For each pattern. */
4698 qualifiers_list
= opcode
->qualifiers_list
;
4699 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4701 /* Most opcodes has much fewer patterns in the list.
4702 First NIL qualifier indicates the end in the list. */
4703 if (empty_qualifier_sequence_p (*qualifiers_list
))
4708 /* Mnemonics name. */
4709 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4711 /* Assign the qualifiers. */
4712 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4714 /* Print instruction. */
4715 print_operands (buf
, opcode
, inst_base
->operands
);
4717 output_info (_(" %s"), buf
);
4723 case AARCH64_OPDE_UNTIED_OPERAND
:
4724 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4725 detail
->index
+ 1, str
);
4728 case AARCH64_OPDE_OUT_OF_RANGE
:
4729 if (detail
->data
[0] != detail
->data
[1])
4730 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4731 detail
->error
? detail
->error
: _("immediate value"),
4732 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4734 handler (_("%s must be %d at operand %d -- `%s'"),
4735 detail
->error
? detail
->error
: _("immediate value"),
4736 detail
->data
[0], idx
+ 1, str
);
4739 case AARCH64_OPDE_REG_LIST
:
4740 if (detail
->data
[0] == 1)
4741 handler (_("invalid number of registers in the list; "
4742 "only 1 register is expected at operand %d -- `%s'"),
4745 handler (_("invalid number of registers in the list; "
4746 "%d registers are expected at operand %d -- `%s'"),
4747 detail
->data
[0], idx
+ 1, str
);
4750 case AARCH64_OPDE_UNALIGNED
:
4751 handler (_("immediate value must be a multiple of "
4752 "%d at operand %d -- `%s'"),
4753 detail
->data
[0], idx
+ 1, str
);
4762 /* Process and output the error message about the operand mismatching.
4764 When this function is called, the operand error information had
4765 been collected for an assembly line and there will be multiple
4766 errors in the case of multiple instruction templates; output the
4767 error message that most closely describes the problem.
4769 The errors to be printed can be filtered on printing all errors
4770 or only non-fatal errors. This distinction has to be made because
4771 the error buffer may already be filled with fatal errors we don't want to
4772 print due to the different instruction templates. */
4775 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4777 int largest_error_pos
;
4778 const char *msg
= NULL
;
4779 enum aarch64_operand_error_kind kind
;
4780 operand_error_record
*curr
;
4781 operand_error_record
*head
= operand_error_report
.head
;
4782 operand_error_record
*record
= NULL
;
4784 /* No error to report. */
4788 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4790 /* Only one error. */
4791 if (head
== operand_error_report
.tail
)
4793 /* If the only error is a non-fatal one and we don't want to print it,
4795 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4797 DEBUG_TRACE ("single opcode entry with error kind: %s",
4798 operand_mismatch_kind_names
[head
->detail
.kind
]);
4799 output_operand_error_record (head
, str
);
4804 /* Find the error kind of the highest severity. */
4805 DEBUG_TRACE ("multiple opcode entries with error kind");
4806 kind
= AARCH64_OPDE_NIL
;
4807 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4809 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4810 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4811 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4812 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4813 kind
= curr
->detail
.kind
;
4816 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
4818 /* Pick up one of errors of KIND to report. */
4819 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4820 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4822 /* If we don't want to print non-fatal errors then don't consider them
4824 if (curr
->detail
.kind
!= kind
4825 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
4827 /* If there are multiple errors, pick up the one with the highest
4828 mismatching operand index. In the case of multiple errors with
4829 the equally highest operand index, pick up the first one or the
4830 first one with non-NULL error message. */
4831 if (curr
->detail
.index
> largest_error_pos
4832 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4833 && curr
->detail
.error
!= NULL
))
4835 largest_error_pos
= curr
->detail
.index
;
4837 msg
= record
->detail
.error
;
4841 /* The way errors are collected in the back-end is a bit non-intuitive. But
4842 essentially, because each operand template is tried recursively you may
4843 always have errors collected from the previous tried OPND. These are
4844 usually skipped if there is one successful match. However now with the
4845 non-fatal errors we have to ignore those previously collected hard errors
4846 when we're only interested in printing the non-fatal ones. This condition
4847 prevents us from printing errors that are not appropriate, since we did
4848 match a condition, but it also has warnings that it wants to print. */
4849 if (non_fatal_only
&& !record
)
4852 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4853 DEBUG_TRACE ("Pick up error kind %s to report",
4854 operand_mismatch_kind_names
[record
->detail
.kind
]);
4857 output_operand_error_record (record
, str
);
4860 /* Write an AARCH64 instruction to buf - always little-endian. */
4862 put_aarch64_insn (char *buf
, uint32_t insn
)
4864 unsigned char *where
= (unsigned char *) buf
;
4866 where
[1] = insn
>> 8;
4867 where
[2] = insn
>> 16;
4868 where
[3] = insn
>> 24;
4872 get_aarch64_insn (char *buf
)
4874 unsigned char *where
= (unsigned char *) buf
;
4876 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4881 output_inst (struct aarch64_inst
*new_inst
)
4885 to
= frag_more (INSN_SIZE
);
4887 frag_now
->tc_frag_data
.recorded
= 1;
4889 put_aarch64_insn (to
, inst
.base
.value
);
4891 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4893 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4894 INSN_SIZE
, &inst
.reloc
.exp
,
4897 DEBUG_TRACE ("Prepared relocation fix up");
4898 /* Don't check the addend value against the instruction size,
4899 that's the job of our code in md_apply_fix(). */
4900 fixp
->fx_no_overflow
= 1;
4901 if (new_inst
!= NULL
)
4902 fixp
->tc_fix_data
.inst
= new_inst
;
4903 if (aarch64_gas_internal_fixup_p ())
4905 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4906 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4907 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4911 dwarf2_emit_insn (INSN_SIZE
);
4914 /* Link together opcodes of the same name. */
4918 aarch64_opcode
*opcode
;
4919 struct templates
*next
;
4922 typedef struct templates templates
;
4925 lookup_mnemonic (const char *start
, int len
)
4927 templates
*templ
= NULL
;
4929 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4933 /* Subroutine of md_assemble, responsible for looking up the primary
4934 opcode from the mnemonic the user wrote. STR points to the
4935 beginning of the mnemonic. */
4938 opcode_lookup (char **str
)
4940 char *end
, *base
, *dot
;
4941 const aarch64_cond
*cond
;
4945 /* Scan up to the end of the mnemonic, which must end in white space,
4946 '.', or end of string. */
4948 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4949 if (*end
== '.' && !dot
)
4952 if (end
== base
|| dot
== base
)
4955 inst
.cond
= COND_ALWAYS
;
4957 /* Handle a possible condition. */
4960 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
4963 inst
.cond
= cond
->value
;
4979 if (inst
.cond
== COND_ALWAYS
)
4981 /* Look for unaffixed mnemonic. */
4982 return lookup_mnemonic (base
, len
);
4986 /* append ".c" to mnemonic if conditional */
4987 memcpy (condname
, base
, len
);
4988 memcpy (condname
+ len
, ".c", 2);
4991 return lookup_mnemonic (base
, len
);
4997 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4998 to a corresponding operand qualifier. */
5000 static inline aarch64_opnd_qualifier_t
5001 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5003 /* Element size in bytes indexed by vector_el_type. */
5004 const unsigned char ele_size
[5]
5006 const unsigned int ele_base
[5] =
5008 AARCH64_OPND_QLF_V_4B
,
5009 AARCH64_OPND_QLF_V_2H
,
5010 AARCH64_OPND_QLF_V_2S
,
5011 AARCH64_OPND_QLF_V_1D
,
5012 AARCH64_OPND_QLF_V_1Q
5015 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5016 goto vectype_conversion_fail
;
5018 if (vectype
->type
== NT_zero
)
5019 return AARCH64_OPND_QLF_P_Z
;
5020 if (vectype
->type
== NT_merge
)
5021 return AARCH64_OPND_QLF_P_M
;
5023 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5025 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5027 /* Special case S_4B. */
5028 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5029 return AARCH64_OPND_QLF_S_4B
;
5031 /* Vector element register. */
5032 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5036 /* Vector register. */
5037 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5040 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5041 goto vectype_conversion_fail
;
5043 /* The conversion is by calculating the offset from the base operand
5044 qualifier for the vector type. The operand qualifiers are regular
5045 enough that the offset can established by shifting the vector width by
5046 a vector-type dependent amount. */
5048 if (vectype
->type
== NT_b
)
5050 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5052 else if (vectype
->type
>= NT_d
)
5057 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5058 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5059 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5063 vectype_conversion_fail
:
5064 first_error (_("bad vector arrangement type"));
5065 return AARCH64_OPND_QLF_NIL
;
5068 /* Process an optional operand that is found omitted from the assembly line.
5069 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5070 instruction's opcode entry while IDX is the index of this omitted operand.
5074 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5075 int idx
, aarch64_opnd_info
*operand
)
5077 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5078 gas_assert (optional_operand_p (opcode
, idx
));
5079 gas_assert (!operand
->present
);
5083 case AARCH64_OPND_Rd
:
5084 case AARCH64_OPND_Rn
:
5085 case AARCH64_OPND_Rm
:
5086 case AARCH64_OPND_Rt
:
5087 case AARCH64_OPND_Rt2
:
5088 case AARCH64_OPND_Rs
:
5089 case AARCH64_OPND_Ra
:
5090 case AARCH64_OPND_Rt_SYS
:
5091 case AARCH64_OPND_Rd_SP
:
5092 case AARCH64_OPND_Rn_SP
:
5093 case AARCH64_OPND_Rm_SP
:
5094 case AARCH64_OPND_Fd
:
5095 case AARCH64_OPND_Fn
:
5096 case AARCH64_OPND_Fm
:
5097 case AARCH64_OPND_Fa
:
5098 case AARCH64_OPND_Ft
:
5099 case AARCH64_OPND_Ft2
:
5100 case AARCH64_OPND_Sd
:
5101 case AARCH64_OPND_Sn
:
5102 case AARCH64_OPND_Sm
:
5103 case AARCH64_OPND_Va
:
5104 case AARCH64_OPND_Vd
:
5105 case AARCH64_OPND_Vn
:
5106 case AARCH64_OPND_Vm
:
5107 case AARCH64_OPND_VdD1
:
5108 case AARCH64_OPND_VnD1
:
5109 operand
->reg
.regno
= default_value
;
5112 case AARCH64_OPND_Ed
:
5113 case AARCH64_OPND_En
:
5114 case AARCH64_OPND_Em
:
5115 case AARCH64_OPND_Em16
:
5116 case AARCH64_OPND_SM3_IMM2
:
5117 operand
->reglane
.regno
= default_value
;
5120 case AARCH64_OPND_IDX
:
5121 case AARCH64_OPND_BIT_NUM
:
5122 case AARCH64_OPND_IMMR
:
5123 case AARCH64_OPND_IMMS
:
5124 case AARCH64_OPND_SHLL_IMM
:
5125 case AARCH64_OPND_IMM_VLSL
:
5126 case AARCH64_OPND_IMM_VLSR
:
5127 case AARCH64_OPND_CCMP_IMM
:
5128 case AARCH64_OPND_FBITS
:
5129 case AARCH64_OPND_UIMM4
:
5130 case AARCH64_OPND_UIMM3_OP1
:
5131 case AARCH64_OPND_UIMM3_OP2
:
5132 case AARCH64_OPND_IMM
:
5133 case AARCH64_OPND_IMM_2
:
5134 case AARCH64_OPND_WIDTH
:
5135 case AARCH64_OPND_UIMM7
:
5136 case AARCH64_OPND_NZCV
:
5137 case AARCH64_OPND_SVE_PATTERN
:
5138 case AARCH64_OPND_SVE_PRFOP
:
5139 operand
->imm
.value
= default_value
;
5142 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5143 operand
->imm
.value
= default_value
;
5144 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5145 operand
->shifter
.amount
= 1;
5148 case AARCH64_OPND_EXCEPTION
:
5149 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5152 case AARCH64_OPND_BARRIER_ISB
:
5153 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5160 /* Process the relocation type for move wide instructions.
5161 Return TRUE on success; otherwise return FALSE. */
5164 process_movw_reloc_info (void)
5169 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5171 if (inst
.base
.opcode
->op
== OP_MOVK
)
5172 switch (inst
.reloc
.type
)
5174 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5175 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5176 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5177 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5178 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5179 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5180 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5181 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5182 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5183 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5184 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5186 (_("the specified relocation type is not allowed for MOVK"));
5192 switch (inst
.reloc
.type
)
5194 case BFD_RELOC_AARCH64_MOVW_G0
:
5195 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5196 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5197 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5198 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5199 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5200 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5201 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5202 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5203 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5204 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5205 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5206 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5209 case BFD_RELOC_AARCH64_MOVW_G1
:
5210 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5211 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5212 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5213 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5214 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5215 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5216 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5217 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5218 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5219 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5220 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5221 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5224 case BFD_RELOC_AARCH64_MOVW_G2
:
5225 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5226 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5227 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5228 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5229 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5230 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5233 set_fatal_syntax_error
5234 (_("the specified relocation type is not allowed for 32-bit "
5240 case BFD_RELOC_AARCH64_MOVW_G3
:
5241 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5244 set_fatal_syntax_error
5245 (_("the specified relocation type is not allowed for 32-bit "
5252 /* More cases should be added when more MOVW-related relocation types
5253 are supported in GAS. */
5254 gas_assert (aarch64_gas_internal_fixup_p ());
5255 /* The shift amount should have already been set by the parser. */
5258 inst
.base
.operands
[1].shifter
.amount
= shift
;
5262 /* A primitive log calculator. */
5264 static inline unsigned int
5265 get_logsz (unsigned int size
)
5267 const unsigned char ls
[16] =
5268 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5274 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5275 return ls
[size
- 1];
5278 /* Determine and return the real reloc type code for an instruction
5279 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5281 static inline bfd_reloc_code_real_type
5282 ldst_lo12_determine_real_reloc_type (void)
5285 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5286 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5288 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5290 BFD_RELOC_AARCH64_LDST8_LO12
,
5291 BFD_RELOC_AARCH64_LDST16_LO12
,
5292 BFD_RELOC_AARCH64_LDST32_LO12
,
5293 BFD_RELOC_AARCH64_LDST64_LO12
,
5294 BFD_RELOC_AARCH64_LDST128_LO12
5297 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5298 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5299 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5300 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5301 BFD_RELOC_AARCH64_NONE
5304 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5305 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5306 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5307 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5308 BFD_RELOC_AARCH64_NONE
5311 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5312 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5313 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5314 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5315 BFD_RELOC_AARCH64_NONE
5318 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5319 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5320 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5321 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5322 BFD_RELOC_AARCH64_NONE
5326 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5327 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5329 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5331 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5333 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5334 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5336 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5338 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5340 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5342 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5343 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5344 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5345 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5346 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5347 gas_assert (logsz
<= 3);
5349 gas_assert (logsz
<= 4);
5351 /* In reloc.c, these pseudo relocation types should be defined in similar
5352 order as above reloc_ldst_lo12 array. Because the array index calculation
5353 below relies on this. */
5354 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5357 /* Check whether a register list REGINFO is valid. The registers must be
5358 numbered in increasing order (modulo 32), in increments of one or two.
5360 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5363 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5366 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5368 uint32_t i
, nb_regs
, prev_regno
, incr
;
5370 nb_regs
= 1 + (reginfo
& 0x3);
5372 prev_regno
= reginfo
& 0x1f;
5373 incr
= accept_alternate
? 2 : 1;
5375 for (i
= 1; i
< nb_regs
; ++i
)
5377 uint32_t curr_regno
;
5379 curr_regno
= reginfo
& 0x1f;
5380 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5382 prev_regno
= curr_regno
;
5388 /* Generic instruction operand parser. This does no encoding and no
5389 semantic validation; it merely squirrels values away in the inst
5390 structure. Returns TRUE or FALSE depending on whether the
5391 specified grammar matched. */
5394 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5397 char *backtrack_pos
= 0;
5398 const enum aarch64_opnd
*operands
= opcode
->operands
;
5399 aarch64_reg_type imm_reg_type
;
5402 skip_whitespace (str
);
5404 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5405 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5407 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5409 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5412 const reg_entry
*reg
;
5413 int comma_skipped_p
= 0;
5414 aarch64_reg_type rtype
;
5415 struct vector_type_el vectype
;
5416 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5417 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5418 aarch64_reg_type reg_type
;
5420 DEBUG_TRACE ("parse operand %d", i
);
5422 /* Assign the operand code. */
5423 info
->type
= operands
[i
];
5425 if (optional_operand_p (opcode
, i
))
5427 /* Remember where we are in case we need to backtrack. */
5428 gas_assert (!backtrack_pos
);
5429 backtrack_pos
= str
;
5432 /* Expect comma between operands; the backtrack mechanism will take
5433 care of cases of omitted optional operand. */
5434 if (i
> 0 && ! skip_past_char (&str
, ','))
5436 set_syntax_error (_("comma expected between operands"));
5440 comma_skipped_p
= 1;
5442 switch (operands
[i
])
5444 case AARCH64_OPND_Rd
:
5445 case AARCH64_OPND_Rn
:
5446 case AARCH64_OPND_Rm
:
5447 case AARCH64_OPND_Rt
:
5448 case AARCH64_OPND_Rt2
:
5449 case AARCH64_OPND_Rs
:
5450 case AARCH64_OPND_Ra
:
5451 case AARCH64_OPND_Rt_SYS
:
5452 case AARCH64_OPND_PAIRREG
:
5453 case AARCH64_OPND_SVE_Rm
:
5454 po_int_reg_or_fail (REG_TYPE_R_Z
);
5457 case AARCH64_OPND_Rd_SP
:
5458 case AARCH64_OPND_Rn_SP
:
5459 case AARCH64_OPND_SVE_Rn_SP
:
5460 case AARCH64_OPND_Rm_SP
:
5461 po_int_reg_or_fail (REG_TYPE_R_SP
);
5464 case AARCH64_OPND_Rm_EXT
:
5465 case AARCH64_OPND_Rm_SFT
:
5466 po_misc_or_fail (parse_shifter_operand
5467 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5469 : SHIFTED_LOGIC_IMM
)));
5470 if (!info
->shifter
.operator_present
)
5472 /* Default to LSL if not present. Libopcodes prefers shifter
5473 kind to be explicit. */
5474 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5475 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5476 /* For Rm_EXT, libopcodes will carry out further check on whether
5477 or not stack pointer is used in the instruction (Recall that
5478 "the extend operator is not optional unless at least one of
5479 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5483 case AARCH64_OPND_Fd
:
5484 case AARCH64_OPND_Fn
:
5485 case AARCH64_OPND_Fm
:
5486 case AARCH64_OPND_Fa
:
5487 case AARCH64_OPND_Ft
:
5488 case AARCH64_OPND_Ft2
:
5489 case AARCH64_OPND_Sd
:
5490 case AARCH64_OPND_Sn
:
5491 case AARCH64_OPND_Sm
:
5492 case AARCH64_OPND_SVE_VZn
:
5493 case AARCH64_OPND_SVE_Vd
:
5494 case AARCH64_OPND_SVE_Vm
:
5495 case AARCH64_OPND_SVE_Vn
:
5496 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5497 if (val
== PARSE_FAIL
)
5499 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5502 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5504 info
->reg
.regno
= val
;
5505 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5508 case AARCH64_OPND_SVE_Pd
:
5509 case AARCH64_OPND_SVE_Pg3
:
5510 case AARCH64_OPND_SVE_Pg4_5
:
5511 case AARCH64_OPND_SVE_Pg4_10
:
5512 case AARCH64_OPND_SVE_Pg4_16
:
5513 case AARCH64_OPND_SVE_Pm
:
5514 case AARCH64_OPND_SVE_Pn
:
5515 case AARCH64_OPND_SVE_Pt
:
5516 reg_type
= REG_TYPE_PN
;
5519 case AARCH64_OPND_SVE_Za_5
:
5520 case AARCH64_OPND_SVE_Za_16
:
5521 case AARCH64_OPND_SVE_Zd
:
5522 case AARCH64_OPND_SVE_Zm_5
:
5523 case AARCH64_OPND_SVE_Zm_16
:
5524 case AARCH64_OPND_SVE_Zn
:
5525 case AARCH64_OPND_SVE_Zt
:
5526 reg_type
= REG_TYPE_ZN
;
5529 case AARCH64_OPND_Va
:
5530 case AARCH64_OPND_Vd
:
5531 case AARCH64_OPND_Vn
:
5532 case AARCH64_OPND_Vm
:
5533 reg_type
= REG_TYPE_VN
;
5535 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5536 if (val
== PARSE_FAIL
)
5538 first_error (_(get_reg_expected_msg (reg_type
)));
5541 if (vectype
.defined
& NTA_HASINDEX
)
5544 info
->reg
.regno
= val
;
5545 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5546 && vectype
.type
== NT_invtype
)
5547 /* Unqualified Pn and Zn registers are allowed in certain
5548 contexts. Rely on F_STRICT qualifier checking to catch
5550 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5553 info
->qualifier
= vectype_to_qualifier (&vectype
);
5554 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5559 case AARCH64_OPND_VdD1
:
5560 case AARCH64_OPND_VnD1
:
5561 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5562 if (val
== PARSE_FAIL
)
5564 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5567 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5569 set_fatal_syntax_error
5570 (_("the top half of a 128-bit FP/SIMD register is expected"));
5573 info
->reg
.regno
= val
;
5574 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5575 here; it is correct for the purpose of encoding/decoding since
5576 only the register number is explicitly encoded in the related
5577 instructions, although this appears a bit hacky. */
5578 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5581 case AARCH64_OPND_SVE_Zm3_INDEX
:
5582 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5583 case AARCH64_OPND_SVE_Zm4_INDEX
:
5584 case AARCH64_OPND_SVE_Zn_INDEX
:
5585 reg_type
= REG_TYPE_ZN
;
5586 goto vector_reg_index
;
5588 case AARCH64_OPND_Ed
:
5589 case AARCH64_OPND_En
:
5590 case AARCH64_OPND_Em
:
5591 case AARCH64_OPND_Em16
:
5592 case AARCH64_OPND_SM3_IMM2
:
5593 reg_type
= REG_TYPE_VN
;
5595 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5596 if (val
== PARSE_FAIL
)
5598 first_error (_(get_reg_expected_msg (reg_type
)));
5601 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5604 info
->reglane
.regno
= val
;
5605 info
->reglane
.index
= vectype
.index
;
5606 info
->qualifier
= vectype_to_qualifier (&vectype
);
5607 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5611 case AARCH64_OPND_SVE_ZnxN
:
5612 case AARCH64_OPND_SVE_ZtxN
:
5613 reg_type
= REG_TYPE_ZN
;
5614 goto vector_reg_list
;
5616 case AARCH64_OPND_LVn
:
5617 case AARCH64_OPND_LVt
:
5618 case AARCH64_OPND_LVt_AL
:
5619 case AARCH64_OPND_LEt
:
5620 reg_type
= REG_TYPE_VN
;
5622 if (reg_type
== REG_TYPE_ZN
5623 && get_opcode_dependent_value (opcode
) == 1
5626 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5627 if (val
== PARSE_FAIL
)
5629 first_error (_(get_reg_expected_msg (reg_type
)));
5632 info
->reglist
.first_regno
= val
;
5633 info
->reglist
.num_regs
= 1;
5637 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5638 if (val
== PARSE_FAIL
)
5640 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5642 set_fatal_syntax_error (_("invalid register list"));
5645 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5646 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5648 if (operands
[i
] == AARCH64_OPND_LEt
)
5650 if (!(vectype
.defined
& NTA_HASINDEX
))
5652 info
->reglist
.has_index
= 1;
5653 info
->reglist
.index
= vectype
.index
;
5657 if (vectype
.defined
& NTA_HASINDEX
)
5659 if (!(vectype
.defined
& NTA_HASTYPE
))
5661 if (reg_type
== REG_TYPE_ZN
)
5662 set_fatal_syntax_error (_("missing type suffix"));
5666 info
->qualifier
= vectype_to_qualifier (&vectype
);
5667 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5671 case AARCH64_OPND_CRn
:
5672 case AARCH64_OPND_CRm
:
5674 char prefix
= *(str
++);
5675 if (prefix
!= 'c' && prefix
!= 'C')
5678 po_imm_nc_or_fail ();
5681 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5684 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5685 info
->imm
.value
= val
;
5689 case AARCH64_OPND_SHLL_IMM
:
5690 case AARCH64_OPND_IMM_VLSR
:
5691 po_imm_or_fail (1, 64);
5692 info
->imm
.value
= val
;
5695 case AARCH64_OPND_CCMP_IMM
:
5696 case AARCH64_OPND_SIMM5
:
5697 case AARCH64_OPND_FBITS
:
5698 case AARCH64_OPND_UIMM4
:
5699 case AARCH64_OPND_UIMM3_OP1
:
5700 case AARCH64_OPND_UIMM3_OP2
:
5701 case AARCH64_OPND_IMM_VLSL
:
5702 case AARCH64_OPND_IMM
:
5703 case AARCH64_OPND_IMM_2
:
5704 case AARCH64_OPND_WIDTH
:
5705 case AARCH64_OPND_SVE_INV_LIMM
:
5706 case AARCH64_OPND_SVE_LIMM
:
5707 case AARCH64_OPND_SVE_LIMM_MOV
:
5708 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5709 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5710 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5711 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5712 case AARCH64_OPND_SVE_SIMM5
:
5713 case AARCH64_OPND_SVE_SIMM5B
:
5714 case AARCH64_OPND_SVE_SIMM6
:
5715 case AARCH64_OPND_SVE_SIMM8
:
5716 case AARCH64_OPND_SVE_UIMM3
:
5717 case AARCH64_OPND_SVE_UIMM7
:
5718 case AARCH64_OPND_SVE_UIMM8
:
5719 case AARCH64_OPND_SVE_UIMM8_53
:
5720 case AARCH64_OPND_IMM_ROT1
:
5721 case AARCH64_OPND_IMM_ROT2
:
5722 case AARCH64_OPND_IMM_ROT3
:
5723 case AARCH64_OPND_SVE_IMM_ROT1
:
5724 case AARCH64_OPND_SVE_IMM_ROT2
:
5725 po_imm_nc_or_fail ();
5726 info
->imm
.value
= val
;
5729 case AARCH64_OPND_SVE_AIMM
:
5730 case AARCH64_OPND_SVE_ASIMM
:
5731 po_imm_nc_or_fail ();
5732 info
->imm
.value
= val
;
5733 skip_whitespace (str
);
5734 if (skip_past_comma (&str
))
5735 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5737 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5740 case AARCH64_OPND_SVE_PATTERN
:
5741 po_enum_or_fail (aarch64_sve_pattern_array
);
5742 info
->imm
.value
= val
;
5745 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5746 po_enum_or_fail (aarch64_sve_pattern_array
);
5747 info
->imm
.value
= val
;
5748 if (skip_past_comma (&str
)
5749 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5751 if (!info
->shifter
.operator_present
)
5753 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5754 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5755 info
->shifter
.amount
= 1;
5759 case AARCH64_OPND_SVE_PRFOP
:
5760 po_enum_or_fail (aarch64_sve_prfop_array
);
5761 info
->imm
.value
= val
;
5764 case AARCH64_OPND_UIMM7
:
5765 po_imm_or_fail (0, 127);
5766 info
->imm
.value
= val
;
5769 case AARCH64_OPND_IDX
:
5770 case AARCH64_OPND_MASK
:
5771 case AARCH64_OPND_BIT_NUM
:
5772 case AARCH64_OPND_IMMR
:
5773 case AARCH64_OPND_IMMS
:
5774 po_imm_or_fail (0, 63);
5775 info
->imm
.value
= val
;
5778 case AARCH64_OPND_IMM0
:
5779 po_imm_nc_or_fail ();
5782 set_fatal_syntax_error (_("immediate zero expected"));
5785 info
->imm
.value
= 0;
5788 case AARCH64_OPND_FPIMM0
:
5791 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5792 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5793 it is probably not worth the effort to support it. */
5794 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5797 || !(res2
= parse_constant_immediate (&str
, &val
,
5800 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5802 info
->imm
.value
= 0;
5803 info
->imm
.is_fp
= 1;
5806 set_fatal_syntax_error (_("immediate zero expected"));
5810 case AARCH64_OPND_IMM_MOV
:
5813 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5814 reg_name_p (str
, REG_TYPE_VN
))
5817 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5819 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5820 later. fix_mov_imm_insn will try to determine a machine
5821 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5822 message if the immediate cannot be moved by a single
5824 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5825 inst
.base
.operands
[i
].skip
= 1;
5829 case AARCH64_OPND_SIMD_IMM
:
5830 case AARCH64_OPND_SIMD_IMM_SFT
:
5831 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5833 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5835 /* need_libopcodes_p */ 1,
5838 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5839 shift, we don't check it here; we leave the checking to
5840 the libopcodes (operand_general_constraint_met_p). By
5841 doing this, we achieve better diagnostics. */
5842 if (skip_past_comma (&str
)
5843 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5845 if (!info
->shifter
.operator_present
5846 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5848 /* Default to LSL if not present. Libopcodes prefers shifter
5849 kind to be explicit. */
5850 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5851 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5855 case AARCH64_OPND_FPIMM
:
5856 case AARCH64_OPND_SIMD_FPIMM
:
5857 case AARCH64_OPND_SVE_FPIMM8
:
5862 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5863 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5864 || !aarch64_imm_float_p (qfloat
))
5867 set_fatal_syntax_error (_("invalid floating-point"
5871 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5872 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5876 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5877 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5878 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5883 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5884 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5887 set_fatal_syntax_error (_("invalid floating-point"
5891 inst
.base
.operands
[i
].imm
.value
= qfloat
;
5892 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5896 case AARCH64_OPND_LIMM
:
5897 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5898 SHIFTED_LOGIC_IMM
));
5899 if (info
->shifter
.operator_present
)
5901 set_fatal_syntax_error
5902 (_("shift not allowed for bitmask immediate"));
5905 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5907 /* need_libopcodes_p */ 1,
5911 case AARCH64_OPND_AIMM
:
5912 if (opcode
->op
== OP_ADD
)
5913 /* ADD may have relocation types. */
5914 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5915 SHIFTED_ARITH_IMM
));
5917 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5918 SHIFTED_ARITH_IMM
));
5919 switch (inst
.reloc
.type
)
5921 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5922 info
->shifter
.amount
= 12;
5924 case BFD_RELOC_UNUSED
:
5925 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5926 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5927 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5928 inst
.reloc
.pc_rel
= 0;
5933 info
->imm
.value
= 0;
5934 if (!info
->shifter
.operator_present
)
5936 /* Default to LSL if not present. Libopcodes prefers shifter
5937 kind to be explicit. */
5938 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5939 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5943 case AARCH64_OPND_HALF
:
5945 /* #<imm16> or relocation. */
5946 int internal_fixup_p
;
5947 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5948 if (internal_fixup_p
)
5949 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5950 skip_whitespace (str
);
5951 if (skip_past_comma (&str
))
5953 /* {, LSL #<shift>} */
5954 if (! aarch64_gas_internal_fixup_p ())
5956 set_fatal_syntax_error (_("can't mix relocation modifier "
5957 "with explicit shift"));
5960 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5963 inst
.base
.operands
[i
].shifter
.amount
= 0;
5964 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5965 inst
.base
.operands
[i
].imm
.value
= 0;
5966 if (! process_movw_reloc_info ())
5971 case AARCH64_OPND_EXCEPTION
:
5972 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
5974 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5976 /* need_libopcodes_p */ 0,
5980 case AARCH64_OPND_NZCV
:
5982 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5986 info
->imm
.value
= nzcv
->value
;
5989 po_imm_or_fail (0, 15);
5990 info
->imm
.value
= val
;
5994 case AARCH64_OPND_COND
:
5995 case AARCH64_OPND_COND1
:
6000 while (ISALPHA (*str
));
6001 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6002 if (info
->cond
== NULL
)
6004 set_syntax_error (_("invalid condition"));
6007 else if (operands
[i
] == AARCH64_OPND_COND1
6008 && (info
->cond
->value
& 0xe) == 0xe)
6010 /* Do not allow AL or NV. */
6011 set_default_error ();
6017 case AARCH64_OPND_ADDR_ADRP
:
6018 po_misc_or_fail (parse_adrp (&str
));
6019 /* Clear the value as operand needs to be relocated. */
6020 info
->imm
.value
= 0;
6023 case AARCH64_OPND_ADDR_PCREL14
:
6024 case AARCH64_OPND_ADDR_PCREL19
:
6025 case AARCH64_OPND_ADDR_PCREL21
:
6026 case AARCH64_OPND_ADDR_PCREL26
:
6027 po_misc_or_fail (parse_address (&str
, info
));
6028 if (!info
->addr
.pcrel
)
6030 set_syntax_error (_("invalid pc-relative address"));
6033 if (inst
.gen_lit_pool
6034 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6036 /* Only permit "=value" in the literal load instructions.
6037 The literal will be generated by programmer_friendly_fixup. */
6038 set_syntax_error (_("invalid use of \"=immediate\""));
6041 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6043 set_syntax_error (_("unrecognized relocation suffix"));
6046 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6048 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6049 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6053 info
->imm
.value
= 0;
6054 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6055 switch (opcode
->iclass
)
6059 /* e.g. CBZ or B.COND */
6060 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6061 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6065 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6066 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6070 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6072 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6073 : BFD_RELOC_AARCH64_JUMP26
;
6076 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6077 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6080 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6081 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6087 inst
.reloc
.pc_rel
= 1;
6091 case AARCH64_OPND_ADDR_SIMPLE
:
6092 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6094 /* [<Xn|SP>{, #<simm>}] */
6096 /* First use the normal address-parsing routines, to get
6097 the usual syntax errors. */
6098 po_misc_or_fail (parse_address (&str
, info
));
6099 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6100 || !info
->addr
.preind
|| info
->addr
.postind
6101 || info
->addr
.writeback
)
6103 set_syntax_error (_("invalid addressing mode"));
6107 /* Then retry, matching the specific syntax of these addresses. */
6109 po_char_or_fail ('[');
6110 po_reg_or_fail (REG_TYPE_R64_SP
);
6111 /* Accept optional ", #0". */
6112 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6113 && skip_past_char (&str
, ','))
6115 skip_past_char (&str
, '#');
6116 if (! skip_past_char (&str
, '0'))
6118 set_fatal_syntax_error
6119 (_("the optional immediate offset can only be 0"));
6123 po_char_or_fail (']');
6127 case AARCH64_OPND_ADDR_REGOFF
:
6128 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6129 po_misc_or_fail (parse_address (&str
, info
));
6131 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6132 || !info
->addr
.preind
|| info
->addr
.postind
6133 || info
->addr
.writeback
)
6135 set_syntax_error (_("invalid addressing mode"));
6138 if (!info
->shifter
.operator_present
)
6140 /* Default to LSL if not present. Libopcodes prefers shifter
6141 kind to be explicit. */
6142 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6143 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6145 /* Qualifier to be deduced by libopcodes. */
6148 case AARCH64_OPND_ADDR_SIMM7
:
6149 po_misc_or_fail (parse_address (&str
, info
));
6150 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6151 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6153 set_syntax_error (_("invalid addressing mode"));
6156 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6158 set_syntax_error (_("relocation not allowed"));
6161 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6163 /* need_libopcodes_p */ 1,
6167 case AARCH64_OPND_ADDR_SIMM9
:
6168 case AARCH64_OPND_ADDR_SIMM9_2
:
6169 po_misc_or_fail (parse_address (&str
, info
));
6170 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6171 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6172 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6173 && info
->addr
.writeback
))
6175 set_syntax_error (_("invalid addressing mode"));
6178 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6180 set_syntax_error (_("relocation not allowed"));
6183 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6185 /* need_libopcodes_p */ 1,
6189 case AARCH64_OPND_ADDR_SIMM10
:
6190 case AARCH64_OPND_ADDR_OFFSET
:
6191 po_misc_or_fail (parse_address (&str
, info
));
6192 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6193 || !info
->addr
.preind
|| info
->addr
.postind
)
6195 set_syntax_error (_("invalid addressing mode"));
6198 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6200 set_syntax_error (_("relocation not allowed"));
6203 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6205 /* need_libopcodes_p */ 1,
6209 case AARCH64_OPND_ADDR_UIMM12
:
6210 po_misc_or_fail (parse_address (&str
, info
));
6211 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6212 || !info
->addr
.preind
|| info
->addr
.writeback
)
6214 set_syntax_error (_("invalid addressing mode"));
6217 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6218 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6219 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6221 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6223 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6225 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6227 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6228 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6229 /* Leave qualifier to be determined by libopcodes. */
6232 case AARCH64_OPND_SIMD_ADDR_POST
:
6233 /* [<Xn|SP>], <Xm|#<amount>> */
6234 po_misc_or_fail (parse_address (&str
, info
));
6235 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6237 set_syntax_error (_("invalid addressing mode"));
6240 if (!info
->addr
.offset
.is_reg
)
6242 if (inst
.reloc
.exp
.X_op
== O_constant
)
6243 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6246 set_fatal_syntax_error
6247 (_("writeback value must be an immediate constant"));
6254 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6255 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6256 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6257 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6258 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6259 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6260 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6261 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6262 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6263 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6264 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6265 /* [X<n>{, #imm, MUL VL}]
6267 but recognizing SVE registers. */
6268 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6269 &offset_qualifier
));
6270 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6272 set_syntax_error (_("invalid addressing mode"));
6276 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6277 || !info
->addr
.preind
|| info
->addr
.writeback
)
6279 set_syntax_error (_("invalid addressing mode"));
6282 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6283 || inst
.reloc
.exp
.X_op
!= O_constant
)
6285 /* Make sure this has priority over
6286 "invalid addressing mode". */
6287 set_fatal_syntax_error (_("constant offset required"));
6290 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6293 case AARCH64_OPND_SVE_ADDR_R
:
6294 /* [<Xn|SP>{, <R><m>}]
6295 but recognizing SVE registers. */
6296 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6297 &offset_qualifier
));
6298 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6300 offset_qualifier
= AARCH64_OPND_QLF_X
;
6301 info
->addr
.offset
.is_reg
= 1;
6302 info
->addr
.offset
.regno
= 31;
6304 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6305 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6307 set_syntax_error (_("invalid addressing mode"));
6312 case AARCH64_OPND_SVE_ADDR_RR
:
6313 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6314 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6315 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6316 case AARCH64_OPND_SVE_ADDR_RX
:
6317 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6318 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6319 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6320 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6321 but recognizing SVE registers. */
6322 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6323 &offset_qualifier
));
6324 if (base_qualifier
!= AARCH64_OPND_QLF_X
6325 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6327 set_syntax_error (_("invalid addressing mode"));
6332 case AARCH64_OPND_SVE_ADDR_RZ
:
6333 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6334 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6335 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6336 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6337 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6338 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6339 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6340 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6341 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6342 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6343 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6344 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6345 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6346 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6347 &offset_qualifier
));
6348 if (base_qualifier
!= AARCH64_OPND_QLF_X
6349 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6350 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6352 set_syntax_error (_("invalid addressing mode"));
6355 info
->qualifier
= offset_qualifier
;
6358 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6359 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6360 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6361 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6362 /* [Z<n>.<T>{, #imm}] */
6363 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6364 &offset_qualifier
));
6365 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6366 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6368 set_syntax_error (_("invalid addressing mode"));
6371 info
->qualifier
= base_qualifier
;
6374 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6375 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6376 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6377 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6378 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6382 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6384 here since we get better error messages by leaving it to
6385 the qualifier checking routines. */
6386 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6387 &offset_qualifier
));
6388 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6389 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6390 || offset_qualifier
!= base_qualifier
)
6392 set_syntax_error (_("invalid addressing mode"));
6395 info
->qualifier
= base_qualifier
;
6398 case AARCH64_OPND_SYSREG
:
6400 uint32_t sysreg_flags
;
6401 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6402 &sysreg_flags
)) == PARSE_FAIL
)
6404 set_syntax_error (_("unknown or missing system register name"));
6407 inst
.base
.operands
[i
].sysreg
.value
= val
;
6408 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6412 case AARCH64_OPND_PSTATEFIELD
:
6413 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6416 set_syntax_error (_("unknown or missing PSTATE field name"));
6419 inst
.base
.operands
[i
].pstatefield
= val
;
6422 case AARCH64_OPND_SYSREG_IC
:
6423 inst
.base
.operands
[i
].sysins_op
=
6424 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6427 case AARCH64_OPND_SYSREG_DC
:
6428 inst
.base
.operands
[i
].sysins_op
=
6429 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6432 case AARCH64_OPND_SYSREG_AT
:
6433 inst
.base
.operands
[i
].sysins_op
=
6434 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6437 case AARCH64_OPND_SYSREG_SR
:
6438 inst
.base
.operands
[i
].sysins_op
=
6439 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6442 case AARCH64_OPND_SYSREG_TLBI
:
6443 inst
.base
.operands
[i
].sysins_op
=
6444 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6446 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6448 set_fatal_syntax_error ( _("unknown or missing operation name"));
6453 case AARCH64_OPND_BARRIER
:
6454 case AARCH64_OPND_BARRIER_ISB
:
6455 val
= parse_barrier (&str
);
6456 if (val
!= PARSE_FAIL
6457 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6459 /* ISB only accepts options name 'sy'. */
6461 (_("the specified option is not accepted in ISB"));
6462 /* Turn off backtrack as this optional operand is present. */
6466 /* This is an extension to accept a 0..15 immediate. */
6467 if (val
== PARSE_FAIL
)
6468 po_imm_or_fail (0, 15);
6469 info
->barrier
= aarch64_barrier_options
+ val
;
6472 case AARCH64_OPND_PRFOP
:
6473 val
= parse_pldop (&str
);
6474 /* This is an extension to accept a 0..31 immediate. */
6475 if (val
== PARSE_FAIL
)
6476 po_imm_or_fail (0, 31);
6477 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6480 case AARCH64_OPND_BARRIER_PSB
:
6481 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6482 if (val
== PARSE_FAIL
)
6487 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6490 /* If we get here, this operand was successfully parsed. */
6491 inst
.base
.operands
[i
].present
= 1;
6495 /* The parse routine should already have set the error, but in case
6496 not, set a default one here. */
6498 set_default_error ();
6500 if (! backtrack_pos
)
6501 goto parse_operands_return
;
6504 /* We reach here because this operand is marked as optional, and
6505 either no operand was supplied or the operand was supplied but it
6506 was syntactically incorrect. In the latter case we report an
6507 error. In the former case we perform a few more checks before
6508 dropping through to the code to insert the default operand. */
6510 char *tmp
= backtrack_pos
;
6511 char endchar
= END_OF_INSN
;
6513 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6515 skip_past_char (&tmp
, ',');
6517 if (*tmp
!= endchar
)
6518 /* The user has supplied an operand in the wrong format. */
6519 goto parse_operands_return
;
6521 /* Make sure there is not a comma before the optional operand.
6522 For example the fifth operand of 'sys' is optional:
6524 sys #0,c0,c0,#0, <--- wrong
6525 sys #0,c0,c0,#0 <--- correct. */
6526 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6528 set_fatal_syntax_error
6529 (_("unexpected comma before the omitted optional operand"));
6530 goto parse_operands_return
;
6534 /* Reaching here means we are dealing with an optional operand that is
6535 omitted from the assembly line. */
6536 gas_assert (optional_operand_p (opcode
, i
));
6538 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6540 /* Try again, skipping the optional operand at backtrack_pos. */
6541 str
= backtrack_pos
;
6544 /* Clear any error record after the omitted optional operand has been
6545 successfully handled. */
6549 /* Check if we have parsed all the operands. */
6550 if (*str
!= '\0' && ! error_p ())
6552 /* Set I to the index of the last present operand; this is
6553 for the purpose of diagnostics. */
6554 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6556 set_fatal_syntax_error
6557 (_("unexpected characters following instruction"));
6560 parse_operands_return
:
6564 DEBUG_TRACE ("parsing FAIL: %s - %s",
6565 operand_mismatch_kind_names
[get_error_kind ()],
6566 get_error_message ());
6567 /* Record the operand error properly; this is useful when there
6568 are multiple instruction templates for a mnemonic name, so that
6569 later on, we can select the error that most closely describes
6571 record_operand_error (opcode
, i
, get_error_kind (),
6572 get_error_message ());
6577 DEBUG_TRACE ("parsing SUCCESS");
6582 /* It does some fix-up to provide some programmer friendly feature while
6583 keeping the libopcodes happy, i.e. libopcodes only accepts
6584 the preferred architectural syntax.
6585 Return FALSE if there is any failure; otherwise return TRUE. */
6588 programmer_friendly_fixup (aarch64_instruction
*instr
)
6590 aarch64_inst
*base
= &instr
->base
;
6591 const aarch64_opcode
*opcode
= base
->opcode
;
6592 enum aarch64_op op
= opcode
->op
;
6593 aarch64_opnd_info
*operands
= base
->operands
;
6595 DEBUG_TRACE ("enter");
6597 switch (opcode
->iclass
)
6600 /* TBNZ Xn|Wn, #uimm6, label
6601 Test and Branch Not Zero: conditionally jumps to label if bit number
6602 uimm6 in register Xn is not zero. The bit number implies the width of
6603 the register, which may be written and should be disassembled as Wn if
6604 uimm is less than 32. */
6605 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6607 if (operands
[1].imm
.value
>= 32)
6609 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6613 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6617 /* LDR Wt, label | =value
6618 As a convenience assemblers will typically permit the notation
6619 "=value" in conjunction with the pc-relative literal load instructions
6620 to automatically place an immediate value or symbolic address in a
6621 nearby literal pool and generate a hidden label which references it.
6622 ISREG has been set to 0 in the case of =value. */
6623 if (instr
->gen_lit_pool
6624 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6626 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6627 if (op
== OP_LDRSW_LIT
)
6629 if (instr
->reloc
.exp
.X_op
!= O_constant
6630 && instr
->reloc
.exp
.X_op
!= O_big
6631 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6633 record_operand_error (opcode
, 1,
6634 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6635 _("constant expression expected"));
6638 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6640 record_operand_error (opcode
, 1,
6641 AARCH64_OPDE_OTHER_ERROR
,
6642 _("literal pool insertion failed"));
6650 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6651 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6652 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6653 A programmer-friendly assembler should accept a destination Xd in
6654 place of Wd, however that is not the preferred form for disassembly.
6656 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6657 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6658 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6659 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6664 /* In the 64-bit form, the final register operand is written as Wm
6665 for all but the (possibly omitted) UXTX/LSL and SXTX
6667 As a programmer-friendly assembler, we accept e.g.
6668 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6669 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6670 int idx
= aarch64_operand_index (opcode
->operands
,
6671 AARCH64_OPND_Rm_EXT
);
6672 gas_assert (idx
== 1 || idx
== 2);
6673 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6674 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6675 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6676 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6677 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6678 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6686 DEBUG_TRACE ("exit with SUCCESS");
6690 /* Check for loads and stores that will cause unpredictable behavior. */
6693 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6695 aarch64_inst
*base
= &instr
->base
;
6696 const aarch64_opcode
*opcode
= base
->opcode
;
6697 const aarch64_opnd_info
*opnds
= base
->operands
;
6698 switch (opcode
->iclass
)
6705 /* Loading/storing the base register is unpredictable if writeback. */
6706 if ((aarch64_get_operand_class (opnds
[0].type
)
6707 == AARCH64_OPND_CLASS_INT_REG
)
6708 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6709 && opnds
[1].addr
.base_regno
!= REG_SP
6710 && opnds
[1].addr
.writeback
)
6711 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6714 case ldstnapair_offs
:
6715 case ldstpair_indexed
:
6716 /* Loading/storing the base register is unpredictable if writeback. */
6717 if ((aarch64_get_operand_class (opnds
[0].type
)
6718 == AARCH64_OPND_CLASS_INT_REG
)
6719 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6720 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6721 && opnds
[2].addr
.base_regno
!= REG_SP
6722 && opnds
[2].addr
.writeback
)
6723 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6724 /* Load operations must load different registers. */
6725 if ((opcode
->opcode
& (1 << 22))
6726 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6727 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6731 /* It is unpredictable if the destination and status registers are the
6733 if ((aarch64_get_operand_class (opnds
[0].type
)
6734 == AARCH64_OPND_CLASS_INT_REG
)
6735 && (aarch64_get_operand_class (opnds
[1].type
)
6736 == AARCH64_OPND_CLASS_INT_REG
)
6737 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
6738 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
6739 as_warn (_("unpredictable: identical transfer and status registers"
6751 force_automatic_sequence_close (void)
6753 if (now_instr_sequence
.instr
)
6755 as_warn (_("previous `%s' sequence has not been closed"),
6756 now_instr_sequence
.instr
->opcode
->name
);
6757 init_insn_sequence (NULL
, &now_instr_sequence
);
6761 /* A wrapper function to interface with libopcodes on encoding and
6762 record the error message if there is any.
6764 Return TRUE on success; otherwise return FALSE. */
6767 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6770 aarch64_operand_error error_info
;
6771 memset (&error_info
, '\0', sizeof (error_info
));
6772 error_info
.kind
= AARCH64_OPDE_NIL
;
6773 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
6774 && !error_info
.non_fatal
)
6777 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6778 record_operand_error_info (opcode
, &error_info
);
6779 return error_info
.non_fatal
;
6782 #ifdef DEBUG_AARCH64
6784 dump_opcode_operands (const aarch64_opcode
*opcode
)
6787 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6789 aarch64_verbose ("\t\t opnd%d: %s", i
,
6790 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6791 ? aarch64_get_operand_name (opcode
->operands
[i
])
6792 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6796 #endif /* DEBUG_AARCH64 */
6798 /* This is the guts of the machine-dependent assembler. STR points to a
6799 machine dependent instruction. This function is supposed to emit
6800 the frags/bytes it assembles to. */
6803 md_assemble (char *str
)
6806 templates
*template;
6807 aarch64_opcode
*opcode
;
6808 aarch64_inst
*inst_base
;
6809 unsigned saved_cond
;
6811 /* Align the previous label if needed. */
6812 if (last_label_seen
!= NULL
)
6814 symbol_set_frag (last_label_seen
, frag_now
);
6815 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6816 S_SET_SEGMENT (last_label_seen
, now_seg
);
6819 /* Update the current insn_sequence from the segment. */
6820 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
6822 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6824 DEBUG_TRACE ("\n\n");
6825 DEBUG_TRACE ("==============================");
6826 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6828 template = opcode_lookup (&p
);
6831 /* It wasn't an instruction, but it might be a register alias of
6832 the form alias .req reg directive. */
6833 if (!create_register_alias (str
, p
))
6834 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6839 skip_whitespace (p
);
6842 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6843 get_mnemonic_name (str
), str
);
6847 init_operand_error_report ();
6849 /* Sections are assumed to start aligned. In executable section, there is no
6850 MAP_DATA symbol pending. So we only align the address during
6851 MAP_DATA --> MAP_INSN transition.
6852 For other sections, this is not guaranteed. */
6853 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6854 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6855 frag_align_code (2, 0);
6857 saved_cond
= inst
.cond
;
6858 reset_aarch64_instruction (&inst
);
6859 inst
.cond
= saved_cond
;
6861 /* Iterate through all opcode entries with the same mnemonic name. */
6864 opcode
= template->opcode
;
6866 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6867 #ifdef DEBUG_AARCH64
6869 dump_opcode_operands (opcode
);
6870 #endif /* DEBUG_AARCH64 */
6872 mapping_state (MAP_INSN
);
6874 inst_base
= &inst
.base
;
6875 inst_base
->opcode
= opcode
;
6877 /* Truly conditionally executed instructions, e.g. b.cond. */
6878 if (opcode
->flags
& F_COND
)
6880 gas_assert (inst
.cond
!= COND_ALWAYS
);
6881 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6882 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6884 else if (inst
.cond
!= COND_ALWAYS
)
6886 /* It shouldn't arrive here, where the assembly looks like a
6887 conditional instruction but the found opcode is unconditional. */
6892 if (parse_operands (p
, opcode
)
6893 && programmer_friendly_fixup (&inst
)
6894 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6896 /* Check that this instruction is supported for this CPU. */
6897 if (!opcode
->avariant
6898 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6900 as_bad (_("selected processor does not support `%s'"), str
);
6904 warn_unpredictable_ldst (&inst
, str
);
6906 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6907 || !inst
.reloc
.need_libopcodes_p
)
6911 /* If there is relocation generated for the instruction,
6912 store the instruction information for the future fix-up. */
6913 struct aarch64_inst
*copy
;
6914 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6915 copy
= XNEW (struct aarch64_inst
);
6916 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6920 /* Issue non-fatal messages if any. */
6921 output_operand_error_report (str
, TRUE
);
6925 template = template->next
;
6926 if (template != NULL
)
6928 reset_aarch64_instruction (&inst
);
6929 inst
.cond
= saved_cond
;
6932 while (template != NULL
);
6934 /* Issue the error messages if any. */
6935 output_operand_error_report (str
, FALSE
);
6938 /* Various frobbings of labels and their addresses. */
6941 aarch64_start_line_hook (void)
6943 last_label_seen
= NULL
;
6947 aarch64_frob_label (symbolS
* sym
)
6949 last_label_seen
= sym
;
6951 dwarf2_emit_label (sym
);
6955 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
6957 /* Check to see if we have a block to close. */
6958 force_automatic_sequence_close ();
6962 aarch64_data_in_code (void)
6964 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6966 *input_line_pointer
= '/';
6967 input_line_pointer
+= 5;
6968 *input_line_pointer
= 0;
6976 aarch64_canonicalize_symbol_name (char *name
)
6980 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6981 *(name
+ len
- 5) = 0;
6986 /* Table of all register names defined by default. The user can
6987 define additional names with .req. Note that all register names
6988 should appear in both upper and lowercase variants. Some registers
6989 also have mixed-case names. */
6991 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6992 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
6993 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6994 #define REGSET16(p,t) \
6995 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6996 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6997 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6998 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
6999 #define REGSET31(p,t) \
7001 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7002 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7003 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7004 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7005 #define REGSET(p,t) \
7006 REGSET31(p,t), REGNUM(p,31,t)
7008 /* These go into aarch64_reg_hsh hash-table. */
7009 static const reg_entry reg_names
[] = {
7010 /* Integer registers. */
7011 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7012 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7014 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7015 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7016 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7017 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7018 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7019 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7021 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7022 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7024 /* Floating-point single precision registers. */
7025 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7027 /* Floating-point double precision registers. */
7028 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7030 /* Floating-point half precision registers. */
7031 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7033 /* Floating-point byte precision registers. */
7034 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7036 /* Floating-point quad precision registers. */
7037 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7039 /* FP/SIMD registers. */
7040 REGSET (v
, VN
), REGSET (V
, VN
),
7042 /* SVE vector registers. */
7043 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7045 /* SVE predicate registers. */
7046 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7064 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7065 static const asm_nzcv nzcv_names
[] = {
7066 {"nzcv", B (n
, z
, c
, v
)},
7067 {"nzcV", B (n
, z
, c
, V
)},
7068 {"nzCv", B (n
, z
, C
, v
)},
7069 {"nzCV", B (n
, z
, C
, V
)},
7070 {"nZcv", B (n
, Z
, c
, v
)},
7071 {"nZcV", B (n
, Z
, c
, V
)},
7072 {"nZCv", B (n
, Z
, C
, v
)},
7073 {"nZCV", B (n
, Z
, C
, V
)},
7074 {"Nzcv", B (N
, z
, c
, v
)},
7075 {"NzcV", B (N
, z
, c
, V
)},
7076 {"NzCv", B (N
, z
, C
, v
)},
7077 {"NzCV", B (N
, z
, C
, V
)},
7078 {"NZcv", B (N
, Z
, c
, v
)},
7079 {"NZcV", B (N
, Z
, c
, V
)},
7080 {"NZCv", B (N
, Z
, C
, v
)},
7081 {"NZCV", B (N
, Z
, C
, V
)}
7094 /* MD interface: bits in the object file. */
7096 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7097 for use in the a.out file, and stores them in the array pointed to by buf.
7098 This knows about the endian-ness of the target machine and does
7099 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7100 2 (short) and 4 (long) Floating numbers are put out as a series of
7101 LITTLENUMS (shorts, here at least). */
7104 md_number_to_chars (char *buf
, valueT val
, int n
)
7106 if (target_big_endian
)
7107 number_to_chars_bigendian (buf
, val
, n
);
7109 number_to_chars_littleendian (buf
, val
, n
);
7112 /* MD interface: Sections. */
7114 /* Estimate the size of a frag before relaxing. Assume everything fits in
7118 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7124 /* Round up a section size to the appropriate boundary. */
7127 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7132 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7133 of an rs_align_code fragment.
7135 Here we fill the frag with the appropriate info for padding the
7136 output stream. The resulting frag will consist of a fixed (fr_fix)
7137 and of a repeating (fr_var) part.
7139 The fixed content is always emitted before the repeating content and
7140 these two parts are used as follows in constructing the output:
7141 - the fixed part will be used to align to a valid instruction word
7142 boundary, in case that we start at a misaligned address; as no
7143 executable instruction can live at the misaligned location, we
7144 simply fill with zeros;
7145 - the variable part will be used to cover the remaining padding and
7146 we fill using the AArch64 NOP instruction.
7148 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7149 enough storage space for up to 3 bytes for padding the back to a valid
7150 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7153 aarch64_handle_align (fragS
* fragP
)
7155 /* NOP = d503201f */
7156 /* AArch64 instructions are always little-endian. */
7157 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7159 int bytes
, fix
, noop_size
;
7162 if (fragP
->fr_type
!= rs_align_code
)
7165 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7166 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7169 gas_assert (fragP
->tc_frag_data
.recorded
);
7172 noop_size
= sizeof (aarch64_noop
);
7174 fix
= bytes
& (noop_size
- 1);
7178 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7182 fragP
->fr_fix
+= fix
;
7186 memcpy (p
, aarch64_noop
, noop_size
);
7187 fragP
->fr_var
= noop_size
;
7190 /* Perform target specific initialisation of a frag.
7191 Note - despite the name this initialisation is not done when the frag
7192 is created, but only when its type is assigned. A frag can be created
7193 and used a long time before its type is set, so beware of assuming that
7194 this initialisation is performed first. */
7198 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7199 int max_chars ATTRIBUTE_UNUSED
)
7203 #else /* OBJ_ELF is defined. */
7205 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7207 /* Record a mapping symbol for alignment frags. We will delete this
7208 later if the alignment ends up empty. */
7209 if (!fragP
->tc_frag_data
.recorded
)
7210 fragP
->tc_frag_data
.recorded
= 1;
7212 /* PR 21809: Do not set a mapping state for debug sections
7213 - it just confuses other tools. */
7214 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
7217 switch (fragP
->fr_type
)
7221 mapping_state_2 (MAP_DATA
, max_chars
);
7224 /* PR 20364: We can get alignment frags in code sections,
7225 so do not just assume that we should use the MAP_DATA state. */
7226 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7229 mapping_state_2 (MAP_INSN
, max_chars
);
7236 /* Initialize the DWARF-2 unwind information for this procedure. */
7239 tc_aarch64_frame_initial_instructions (void)
7241 cfi_add_CFA_def_cfa (REG_SP
, 0);
7243 #endif /* OBJ_ELF */
7245 /* Convert REGNAME to a DWARF-2 register number. */
7248 tc_aarch64_regname_to_dw2regnum (char *regname
)
7250 const reg_entry
*reg
= parse_reg (®name
);
7256 case REG_TYPE_SP_32
:
7257 case REG_TYPE_SP_64
:
7267 return reg
->number
+ 64;
7275 /* Implement DWARF2_ADDR_SIZE. */
7278 aarch64_dwarf2_addr_size (void)
7280 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7284 return bfd_arch_bits_per_address (stdoutput
) / 8;
7287 /* MD interface: Symbol and relocation handling. */
7289 /* Return the address within the segment that a PC-relative fixup is
7290 relative to. For AArch64 PC-relative fixups applied to instructions
7291 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7294 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7296 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7298 /* If this is pc-relative and we are going to emit a relocation
7299 then we just want to put out any pipeline compensation that the linker
7300 will need. Otherwise we want to use the calculated base. */
7302 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7303 || aarch64_force_relocation (fixP
)))
7306 /* AArch64 should be consistent for all pc-relative relocations. */
7307 return base
+ AARCH64_PCREL_OFFSET
;
7310 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7311 Otherwise we have no need to default values of symbols. */
7314 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7317 if (name
[0] == '_' && name
[1] == 'G'
7318 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7322 if (symbol_find (name
))
7323 as_bad (_("GOT already in the symbol table"));
7325 GOT_symbol
= symbol_new (name
, undefined_section
,
7326 (valueT
) 0, &zero_address_frag
);
7336 /* Return non-zero if the indicated VALUE has overflowed the maximum
7337 range expressible by a unsigned number with the indicated number of
7341 unsigned_overflow (valueT value
, unsigned bits
)
7344 if (bits
>= sizeof (valueT
) * 8)
7346 lim
= (valueT
) 1 << bits
;
7347 return (value
>= lim
);
7351 /* Return non-zero if the indicated VALUE has overflowed the maximum
7352 range expressible by an signed number with the indicated number of
7356 signed_overflow (offsetT value
, unsigned bits
)
7359 if (bits
>= sizeof (offsetT
) * 8)
7361 lim
= (offsetT
) 1 << (bits
- 1);
7362 return (value
< -lim
|| value
>= lim
);
7365 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7366 unsigned immediate offset load/store instruction, try to encode it as
7367 an unscaled, 9-bit, signed immediate offset load/store instruction.
7368 Return TRUE if it is successful; otherwise return FALSE.
7370 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7371 in response to the standard LDR/STR mnemonics when the immediate offset is
7372 unambiguous, i.e. when it is negative or unaligned. */
7375 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7378 enum aarch64_op new_op
;
7379 const aarch64_opcode
*new_opcode
;
7381 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7383 switch (instr
->opcode
->op
)
7385 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7386 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7387 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7388 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7389 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7390 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7391 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7392 case OP_STR_POS
: new_op
= OP_STUR
; break;
7393 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7394 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7395 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7396 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7397 default: new_op
= OP_NIL
; break;
7400 if (new_op
== OP_NIL
)
7403 new_opcode
= aarch64_get_opcode (new_op
);
7404 gas_assert (new_opcode
!= NULL
);
7406 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7407 instr
->opcode
->op
, new_opcode
->op
);
7409 aarch64_replace_opcode (instr
, new_opcode
);
7411 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7412 qualifier matching may fail because the out-of-date qualifier will
7413 prevent the operand being updated with a new and correct qualifier. */
7414 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7415 AARCH64_OPND_ADDR_SIMM9
);
7416 gas_assert (idx
== 1);
7417 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7419 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7421 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7428 /* Called by fix_insn to fix a MOV immediate alias instruction.
7430 Operand for a generic move immediate instruction, which is an alias
7431 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7432 a 32-bit/64-bit immediate value into general register. An assembler error
7433 shall result if the immediate cannot be created by a single one of these
7434 instructions. If there is a choice, then to ensure reversability an
7435 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7438 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7440 const aarch64_opcode
*opcode
;
7442 /* Need to check if the destination is SP/ZR. The check has to be done
7443 before any aarch64_replace_opcode. */
7444 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7445 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7447 instr
->operands
[1].imm
.value
= value
;
7448 instr
->operands
[1].skip
= 0;
7452 /* Try the MOVZ alias. */
7453 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7454 aarch64_replace_opcode (instr
, opcode
);
7455 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7456 &instr
->value
, NULL
, NULL
, insn_sequence
))
7458 put_aarch64_insn (buf
, instr
->value
);
7461 /* Try the MOVK alias. */
7462 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7463 aarch64_replace_opcode (instr
, opcode
);
7464 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7465 &instr
->value
, NULL
, NULL
, insn_sequence
))
7467 put_aarch64_insn (buf
, instr
->value
);
7472 if (try_mov_bitmask_p
)
7474 /* Try the ORR alias. */
7475 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7476 aarch64_replace_opcode (instr
, opcode
);
7477 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7478 &instr
->value
, NULL
, NULL
, insn_sequence
))
7480 put_aarch64_insn (buf
, instr
->value
);
7485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7486 _("immediate cannot be moved by a single instruction"));
7489 /* An instruction operand which is immediate related may have symbol used
7490 in the assembly, e.g.
7493 .set u32, 0x00ffff00
7495 At the time when the assembly instruction is parsed, a referenced symbol,
7496 like 'u32' in the above example may not have been seen; a fixS is created
7497 in such a case and is handled here after symbols have been resolved.
7498 Instruction is fixed up with VALUE using the information in *FIXP plus
7499 extra information in FLAGS.
7501 This function is called by md_apply_fix to fix up instructions that need
7502 a fix-up described above but does not involve any linker-time relocation. */
7505 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7509 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7510 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7511 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7515 /* Now the instruction is about to be fixed-up, so the operand that
7516 was previously marked as 'ignored' needs to be unmarked in order
7517 to get the encoding done properly. */
7518 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7519 new_inst
->operands
[idx
].skip
= 0;
7522 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7526 case AARCH64_OPND_EXCEPTION
:
7527 if (unsigned_overflow (value
, 16))
7528 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7529 _("immediate out of range"));
7530 insn
= get_aarch64_insn (buf
);
7531 insn
|= encode_svc_imm (value
);
7532 put_aarch64_insn (buf
, insn
);
7535 case AARCH64_OPND_AIMM
:
7536 /* ADD or SUB with immediate.
7537 NOTE this assumes we come here with a add/sub shifted reg encoding
7538 3 322|2222|2 2 2 21111 111111
7539 1 098|7654|3 2 1 09876 543210 98765 43210
7540 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7541 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7542 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7543 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7545 3 322|2222|2 2 221111111111
7546 1 098|7654|3 2 109876543210 98765 43210
7547 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7548 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7549 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7550 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7551 Fields sf Rn Rd are already set. */
7552 insn
= get_aarch64_insn (buf
);
7556 insn
= reencode_addsub_switch_add_sub (insn
);
7560 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7561 && unsigned_overflow (value
, 12))
7563 /* Try to shift the value by 12 to make it fit. */
7564 if (((value
>> 12) << 12) == value
7565 && ! unsigned_overflow (value
, 12 + 12))
7568 insn
|= encode_addsub_imm_shift_amount (1);
7572 if (unsigned_overflow (value
, 12))
7573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7574 _("immediate out of range"));
7576 insn
|= encode_addsub_imm (value
);
7578 put_aarch64_insn (buf
, insn
);
7581 case AARCH64_OPND_SIMD_IMM
:
7582 case AARCH64_OPND_SIMD_IMM_SFT
:
7583 case AARCH64_OPND_LIMM
:
7584 /* Bit mask immediate. */
7585 gas_assert (new_inst
!= NULL
);
7586 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7587 new_inst
->operands
[idx
].imm
.value
= value
;
7588 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7589 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7590 put_aarch64_insn (buf
, new_inst
->value
);
7592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7593 _("invalid immediate"));
7596 case AARCH64_OPND_HALF
:
7597 /* 16-bit unsigned immediate. */
7598 if (unsigned_overflow (value
, 16))
7599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7600 _("immediate out of range"));
7601 insn
= get_aarch64_insn (buf
);
7602 insn
|= encode_movw_imm (value
& 0xffff);
7603 put_aarch64_insn (buf
, insn
);
7606 case AARCH64_OPND_IMM_MOV
:
7607 /* Operand for a generic move immediate instruction, which is
7608 an alias instruction that generates a single MOVZ, MOVN or ORR
7609 instruction to loads a 32-bit/64-bit immediate value into general
7610 register. An assembler error shall result if the immediate cannot be
7611 created by a single one of these instructions. If there is a choice,
7612 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7613 and MOVZ or MOVN to ORR. */
7614 gas_assert (new_inst
!= NULL
);
7615 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7618 case AARCH64_OPND_ADDR_SIMM7
:
7619 case AARCH64_OPND_ADDR_SIMM9
:
7620 case AARCH64_OPND_ADDR_SIMM9_2
:
7621 case AARCH64_OPND_ADDR_SIMM10
:
7622 case AARCH64_OPND_ADDR_UIMM12
:
7623 /* Immediate offset in an address. */
7624 insn
= get_aarch64_insn (buf
);
7626 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7627 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7628 || new_inst
->opcode
->operands
[2] == opnd
);
7630 /* Get the index of the address operand. */
7631 if (new_inst
->opcode
->operands
[1] == opnd
)
7632 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7635 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7638 /* Update the resolved offset value. */
7639 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7641 /* Encode/fix-up. */
7642 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7643 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7645 put_aarch64_insn (buf
, new_inst
->value
);
7648 else if (new_inst
->opcode
->iclass
== ldst_pos
7649 && try_to_encode_as_unscaled_ldst (new_inst
))
7651 put_aarch64_insn (buf
, new_inst
->value
);
7655 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7656 _("immediate offset out of range"));
7661 as_fatal (_("unhandled operand code %d"), opnd
);
7665 /* Apply a fixup (fixP) to segment data, once it has been determined
7666 by our caller that we have all the info we need to fix it up.
7668 Parameter valP is the pointer to the value of the bits. */
7671 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7673 offsetT value
= *valP
;
7675 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7677 unsigned flags
= fixP
->fx_addnumber
;
7679 DEBUG_TRACE ("\n\n");
7680 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7681 DEBUG_TRACE ("Enter md_apply_fix");
7683 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7685 /* Note whether this will delete the relocation. */
7687 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7690 /* Process the relocations. */
7691 switch (fixP
->fx_r_type
)
7693 case BFD_RELOC_NONE
:
7694 /* This will need to go in the object file. */
7699 case BFD_RELOC_8_PCREL
:
7700 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7701 md_number_to_chars (buf
, value
, 1);
7705 case BFD_RELOC_16_PCREL
:
7706 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7707 md_number_to_chars (buf
, value
, 2);
7711 case BFD_RELOC_32_PCREL
:
7712 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7713 md_number_to_chars (buf
, value
, 4);
7717 case BFD_RELOC_64_PCREL
:
7718 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7719 md_number_to_chars (buf
, value
, 8);
7722 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7723 /* We claim that these fixups have been processed here, even if
7724 in fact we generate an error because we do not have a reloc
7725 for them, so tc_gen_reloc() will reject them. */
7727 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7730 _("undefined symbol %s used as an immediate value"),
7731 S_GET_NAME (fixP
->fx_addsy
));
7732 goto apply_fix_return
;
7734 fix_insn (fixP
, flags
, value
);
7737 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7738 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7742 _("pc-relative load offset not word aligned"));
7743 if (signed_overflow (value
, 21))
7744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7745 _("pc-relative load offset out of range"));
7746 insn
= get_aarch64_insn (buf
);
7747 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7748 put_aarch64_insn (buf
, insn
);
7752 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7753 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7755 if (signed_overflow (value
, 21))
7756 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7757 _("pc-relative address offset out of range"));
7758 insn
= get_aarch64_insn (buf
);
7759 insn
|= encode_adr_imm (value
);
7760 put_aarch64_insn (buf
, insn
);
7764 case BFD_RELOC_AARCH64_BRANCH19
:
7765 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7769 _("conditional branch target not word aligned"));
7770 if (signed_overflow (value
, 21))
7771 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7772 _("conditional branch out of range"));
7773 insn
= get_aarch64_insn (buf
);
7774 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7775 put_aarch64_insn (buf
, insn
);
7779 case BFD_RELOC_AARCH64_TSTBR14
:
7780 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7783 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7784 _("conditional branch target not word aligned"));
7785 if (signed_overflow (value
, 16))
7786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7787 _("conditional branch out of range"));
7788 insn
= get_aarch64_insn (buf
);
7789 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7790 put_aarch64_insn (buf
, insn
);
7794 case BFD_RELOC_AARCH64_CALL26
:
7795 case BFD_RELOC_AARCH64_JUMP26
:
7796 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7800 _("branch target not word aligned"));
7801 if (signed_overflow (value
, 28))
7802 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7803 _("branch out of range"));
7804 insn
= get_aarch64_insn (buf
);
7805 insn
|= encode_branch_ofs_26 (value
>> 2);
7806 put_aarch64_insn (buf
, insn
);
7810 case BFD_RELOC_AARCH64_MOVW_G0
:
7811 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7812 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7813 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7814 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7815 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
7818 case BFD_RELOC_AARCH64_MOVW_G1
:
7819 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7820 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7821 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7822 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7823 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
7826 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7828 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7829 /* Should always be exported to object file, see
7830 aarch64_force_relocation(). */
7831 gas_assert (!fixP
->fx_done
);
7832 gas_assert (seg
->use_rela_p
);
7834 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7836 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7837 /* Should always be exported to object file, see
7838 aarch64_force_relocation(). */
7839 gas_assert (!fixP
->fx_done
);
7840 gas_assert (seg
->use_rela_p
);
7842 case BFD_RELOC_AARCH64_MOVW_G2
:
7843 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7844 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7845 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7846 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
7849 case BFD_RELOC_AARCH64_MOVW_G3
:
7850 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
7853 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7855 insn
= get_aarch64_insn (buf
);
7859 /* REL signed addend must fit in 16 bits */
7860 if (signed_overflow (value
, 16))
7861 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7862 _("offset out of range"));
7866 /* Check for overflow and scale. */
7867 switch (fixP
->fx_r_type
)
7869 case BFD_RELOC_AARCH64_MOVW_G0
:
7870 case BFD_RELOC_AARCH64_MOVW_G1
:
7871 case BFD_RELOC_AARCH64_MOVW_G2
:
7872 case BFD_RELOC_AARCH64_MOVW_G3
:
7873 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7874 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7875 if (unsigned_overflow (value
, scale
+ 16))
7876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7877 _("unsigned value out of range"));
7879 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7880 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7881 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7882 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7883 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7884 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7885 /* NOTE: We can only come here with movz or movn. */
7886 if (signed_overflow (value
, scale
+ 16))
7887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7888 _("signed value out of range"));
7891 /* Force use of MOVN. */
7893 insn
= reencode_movzn_to_movn (insn
);
7897 /* Force use of MOVZ. */
7898 insn
= reencode_movzn_to_movz (insn
);
7902 /* Unchecked relocations. */
7908 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7909 insn
|= encode_movw_imm (value
& 0xffff);
7911 put_aarch64_insn (buf
, insn
);
7915 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7916 fixP
->fx_r_type
= (ilp32_p
7917 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7918 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7919 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7920 /* Should always be exported to object file, see
7921 aarch64_force_relocation(). */
7922 gas_assert (!fixP
->fx_done
);
7923 gas_assert (seg
->use_rela_p
);
7926 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7927 fixP
->fx_r_type
= (ilp32_p
7928 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7929 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
7930 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7931 /* Should always be exported to object file, see
7932 aarch64_force_relocation(). */
7933 gas_assert (!fixP
->fx_done
);
7934 gas_assert (seg
->use_rela_p
);
7937 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
7938 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7939 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7940 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7941 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
7942 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7943 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7944 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7945 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7946 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7947 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7948 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7949 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7950 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7951 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7952 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7953 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7954 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7955 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7956 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7957 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7958 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7959 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7960 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7961 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7962 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7963 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7964 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7965 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7966 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7967 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7968 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7969 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7970 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7971 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7972 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7973 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
7974 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
7975 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
7976 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
7977 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
7978 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
7979 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
7980 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
7981 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7982 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7983 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7984 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7985 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7986 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7987 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7988 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7989 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7990 /* Should always be exported to object file, see
7991 aarch64_force_relocation(). */
7992 gas_assert (!fixP
->fx_done
);
7993 gas_assert (seg
->use_rela_p
);
7996 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7997 /* Should always be exported to object file, see
7998 aarch64_force_relocation(). */
7999 fixP
->fx_r_type
= (ilp32_p
8000 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8001 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8002 gas_assert (!fixP
->fx_done
);
8003 gas_assert (seg
->use_rela_p
);
8006 case BFD_RELOC_AARCH64_ADD_LO12
:
8007 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8008 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8009 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8010 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8011 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8012 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8013 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8014 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8015 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8016 case BFD_RELOC_AARCH64_LDST128_LO12
:
8017 case BFD_RELOC_AARCH64_LDST16_LO12
:
8018 case BFD_RELOC_AARCH64_LDST32_LO12
:
8019 case BFD_RELOC_AARCH64_LDST64_LO12
:
8020 case BFD_RELOC_AARCH64_LDST8_LO12
:
8021 /* Should always be exported to object file, see
8022 aarch64_force_relocation(). */
8023 gas_assert (!fixP
->fx_done
);
8024 gas_assert (seg
->use_rela_p
);
8027 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8028 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8029 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8032 case BFD_RELOC_UNUSED
:
8033 /* An error will already have been reported. */
8037 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8038 _("unexpected %s fixup"),
8039 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8044 /* Free the allocated the struct aarch64_inst.
8045 N.B. currently there are very limited number of fix-up types actually use
8046 this field, so the impact on the performance should be minimal . */
8047 if (fixP
->tc_fix_data
.inst
!= NULL
)
8048 free (fixP
->tc_fix_data
.inst
);
8053 /* Translate internal representation of relocation info to BFD target
8057 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8060 bfd_reloc_code_real_type code
;
8062 reloc
= XNEW (arelent
);
8064 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8065 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8066 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8070 if (section
->use_rela_p
)
8071 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8073 fixp
->fx_offset
= reloc
->address
;
8075 reloc
->addend
= fixp
->fx_offset
;
8077 code
= fixp
->fx_r_type
;
8082 code
= BFD_RELOC_16_PCREL
;
8087 code
= BFD_RELOC_32_PCREL
;
8092 code
= BFD_RELOC_64_PCREL
;
8099 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8100 if (reloc
->howto
== NULL
)
8102 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8104 ("cannot represent %s relocation in this object file format"),
8105 bfd_get_reloc_code_name (code
));
8112 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8115 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8117 bfd_reloc_code_real_type type
;
8121 FIXME: @@ Should look at CPU word size. */
8128 type
= BFD_RELOC_16
;
8131 type
= BFD_RELOC_32
;
8134 type
= BFD_RELOC_64
;
8137 as_bad (_("cannot do %u-byte relocation"), size
);
8138 type
= BFD_RELOC_UNUSED
;
8142 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8146 aarch64_force_relocation (struct fix
*fixp
)
8148 switch (fixp
->fx_r_type
)
8150 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8151 /* Perform these "immediate" internal relocations
8152 even if the symbol is extern or weak. */
8155 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8156 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8157 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8158 /* Pseudo relocs that need to be fixed up according to
8162 case BFD_RELOC_AARCH64_ADD_LO12
:
8163 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8164 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8165 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8166 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8167 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8168 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8169 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8170 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8171 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8172 case BFD_RELOC_AARCH64_LDST128_LO12
:
8173 case BFD_RELOC_AARCH64_LDST16_LO12
:
8174 case BFD_RELOC_AARCH64_LDST32_LO12
:
8175 case BFD_RELOC_AARCH64_LDST64_LO12
:
8176 case BFD_RELOC_AARCH64_LDST8_LO12
:
8177 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8178 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8179 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8180 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8181 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8182 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8183 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8184 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8185 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8186 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8187 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8188 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8189 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8190 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8191 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8192 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8193 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8194 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8195 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8196 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8197 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8198 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8199 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8200 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8201 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8202 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8203 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8204 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8205 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8206 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8207 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8208 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8209 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8210 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8211 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8212 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8213 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8214 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8215 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8216 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8217 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8218 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8219 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8220 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8221 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8222 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8223 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8224 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8225 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8226 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8227 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8228 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8229 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8230 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8231 /* Always leave these relocations for the linker. */
8238 return generic_force_reloc (fixp
);
8243 /* Implement md_after_parse_args. This is the earliest time we need to decide
8244 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8247 aarch64_after_parse_args (void)
8249 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8252 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8253 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8254 aarch64_abi
= AARCH64_ABI_ILP32
;
8256 aarch64_abi
= AARCH64_ABI_LP64
;
8260 elf64_aarch64_target_format (void)
8262 if (strcmp (TARGET_OS
, "cloudabi") == 0)
8264 /* FIXME: What to do for ilp32_p ? */
8265 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
8267 if (target_big_endian
)
8268 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8270 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8274 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8276 elf_frob_symbol (symp
, puntp
);
8280 /* MD interface: Finalization. */
8282 /* A good place to do this, although this was probably not intended
8283 for this kind of use. We need to dump the literal pool before
8284 references are made to a null symbol pointer. */
8287 aarch64_cleanup (void)
8291 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8293 /* Put it at the end of the relevant section. */
8294 subseg_set (pool
->section
, pool
->sub_section
);
8300 /* Remove any excess mapping symbols generated for alignment frags in
8301 SEC. We may have created a mapping symbol before a zero byte
8302 alignment; remove it if there's a mapping symbol after the
8305 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8306 void *dummy ATTRIBUTE_UNUSED
)
8308 segment_info_type
*seginfo
= seg_info (sec
);
8311 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8314 for (fragp
= seginfo
->frchainP
->frch_root
;
8315 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8317 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8318 fragS
*next
= fragp
->fr_next
;
8320 /* Variable-sized frags have been converted to fixed size by
8321 this point. But if this was variable-sized to start with,
8322 there will be a fixed-size frag after it. So don't handle
8324 if (sym
== NULL
|| next
== NULL
)
8327 if (S_GET_VALUE (sym
) < next
->fr_address
)
8328 /* Not at the end of this frag. */
8330 know (S_GET_VALUE (sym
) == next
->fr_address
);
8334 if (next
->tc_frag_data
.first_map
!= NULL
)
8336 /* Next frag starts with a mapping symbol. Discard this
8338 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8342 if (next
->fr_next
== NULL
)
8344 /* This mapping symbol is at the end of the section. Discard
8346 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8347 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8351 /* As long as we have empty frags without any mapping symbols,
8353 /* If the next frag is non-empty and does not start with a
8354 mapping symbol, then this mapping symbol is required. */
8355 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8358 next
= next
->fr_next
;
8360 while (next
!= NULL
);
8365 /* Adjust the symbol table. */
8368 aarch64_adjust_symtab (void)
8371 /* Remove any overlapping mapping symbols generated by alignment frags. */
8372 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8373 /* Now do generic ELF adjustments. */
8374 elf_adjust_symtab ();
8379 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8381 const char *hash_err
;
8383 hash_err
= hash_insert (table
, key
, value
);
8385 printf ("Internal Error: Can't hash %s\n", key
);
8389 fill_instruction_hash_table (void)
8391 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8393 while (opcode
->name
!= NULL
)
8395 templates
*templ
, *new_templ
;
8396 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8398 new_templ
= XNEW (templates
);
8399 new_templ
->opcode
= opcode
;
8400 new_templ
->next
= NULL
;
8403 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8406 new_templ
->next
= templ
->next
;
8407 templ
->next
= new_templ
;
8414 convert_to_upper (char *dst
, const char *src
, size_t num
)
8417 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8418 *dst
= TOUPPER (*src
);
8422 /* Assume STR point to a lower-case string, allocate, convert and return
8423 the corresponding upper-case string. */
8424 static inline const char*
8425 get_upper_str (const char *str
)
8428 size_t len
= strlen (str
);
8429 ret
= XNEWVEC (char, len
+ 1);
8430 convert_to_upper (ret
, str
, len
);
8434 /* MD interface: Initialization. */
8442 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8443 || (aarch64_cond_hsh
= hash_new ()) == NULL
8444 || (aarch64_shift_hsh
= hash_new ()) == NULL
8445 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8446 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8447 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8448 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8449 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8450 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8451 || (aarch64_sys_regs_sr_hsh
= hash_new ()) == NULL
8452 || (aarch64_reg_hsh
= hash_new ()) == NULL
8453 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8454 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8455 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8456 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8457 as_fatal (_("virtual memory exhausted"));
8459 fill_instruction_hash_table ();
8461 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8462 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8463 (void *) (aarch64_sys_regs
+ i
));
8465 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8466 checked_hash_insert (aarch64_pstatefield_hsh
,
8467 aarch64_pstatefields
[i
].name
,
8468 (void *) (aarch64_pstatefields
+ i
));
8470 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8471 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8472 aarch64_sys_regs_ic
[i
].name
,
8473 (void *) (aarch64_sys_regs_ic
+ i
));
8475 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8476 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8477 aarch64_sys_regs_dc
[i
].name
,
8478 (void *) (aarch64_sys_regs_dc
+ i
));
8480 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8481 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8482 aarch64_sys_regs_at
[i
].name
,
8483 (void *) (aarch64_sys_regs_at
+ i
));
8485 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8486 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8487 aarch64_sys_regs_tlbi
[i
].name
,
8488 (void *) (aarch64_sys_regs_tlbi
+ i
));
8490 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8491 checked_hash_insert (aarch64_sys_regs_sr_hsh
,
8492 aarch64_sys_regs_sr
[i
].name
,
8493 (void *) (aarch64_sys_regs_sr
+ i
));
8495 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8496 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8497 (void *) (reg_names
+ i
));
8499 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8500 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8501 (void *) (nzcv_names
+ i
));
8503 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8505 const char *name
= aarch64_operand_modifiers
[i
].name
;
8506 checked_hash_insert (aarch64_shift_hsh
, name
,
8507 (void *) (aarch64_operand_modifiers
+ i
));
8508 /* Also hash the name in the upper case. */
8509 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8510 (void *) (aarch64_operand_modifiers
+ i
));
8513 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8516 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8517 the same condition code. */
8518 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8520 const char *name
= aarch64_conds
[i
].names
[j
];
8523 checked_hash_insert (aarch64_cond_hsh
, name
,
8524 (void *) (aarch64_conds
+ i
));
8525 /* Also hash the name in the upper case. */
8526 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8527 (void *) (aarch64_conds
+ i
));
8531 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8533 const char *name
= aarch64_barrier_options
[i
].name
;
8534 /* Skip xx00 - the unallocated values of option. */
8537 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8538 (void *) (aarch64_barrier_options
+ i
));
8539 /* Also hash the name in the upper case. */
8540 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8541 (void *) (aarch64_barrier_options
+ i
));
8544 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8546 const char* name
= aarch64_prfops
[i
].name
;
8547 /* Skip the unallocated hint encodings. */
8550 checked_hash_insert (aarch64_pldop_hsh
, name
,
8551 (void *) (aarch64_prfops
+ i
));
8552 /* Also hash the name in the upper case. */
8553 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8554 (void *) (aarch64_prfops
+ i
));
8557 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8559 const char* name
= aarch64_hint_options
[i
].name
;
8561 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8562 (void *) (aarch64_hint_options
+ i
));
8563 /* Also hash the name in the upper case. */
8564 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8565 (void *) (aarch64_hint_options
+ i
));
8568 /* Set the cpu variant based on the command-line options. */
8570 mcpu_cpu_opt
= march_cpu_opt
;
8573 mcpu_cpu_opt
= &cpu_default
;
8575 cpu_variant
= *mcpu_cpu_opt
;
8577 /* Record the CPU type. */
8578 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8580 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8583 /* Command line processing. */
8585 const char *md_shortopts
= "m:";
8587 #ifdef AARCH64_BI_ENDIAN
8588 #define OPTION_EB (OPTION_MD_BASE + 0)
8589 #define OPTION_EL (OPTION_MD_BASE + 1)
8591 #if TARGET_BYTES_BIG_ENDIAN
8592 #define OPTION_EB (OPTION_MD_BASE + 0)
8594 #define OPTION_EL (OPTION_MD_BASE + 1)
8598 struct option md_longopts
[] = {
8600 {"EB", no_argument
, NULL
, OPTION_EB
},
8603 {"EL", no_argument
, NULL
, OPTION_EL
},
8605 {NULL
, no_argument
, NULL
, 0}
8608 size_t md_longopts_size
= sizeof (md_longopts
);
8610 struct aarch64_option_table
8612 const char *option
; /* Option name to match. */
8613 const char *help
; /* Help information. */
8614 int *var
; /* Variable to change. */
8615 int value
; /* What to change it to. */
8616 char *deprecated
; /* If non-null, print this message. */
8619 static struct aarch64_option_table aarch64_opts
[] = {
8620 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8621 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8623 #ifdef DEBUG_AARCH64
8624 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8625 #endif /* DEBUG_AARCH64 */
8626 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8628 {"mno-verbose-error", N_("do not output verbose error messages"),
8629 &verbose_error_p
, 0, NULL
},
8630 {NULL
, NULL
, NULL
, 0, NULL
}
8633 struct aarch64_cpu_option_table
8636 const aarch64_feature_set value
;
8637 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8639 const char *canonical_name
;
8642 /* This list should, at a minimum, contain all the cpu names
8643 recognized by GCC. */
8644 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8645 {"all", AARCH64_ANY
, NULL
},
8646 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8647 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8648 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8649 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8650 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8651 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8652 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8653 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8654 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8655 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8656 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8657 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8659 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8660 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8662 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8663 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8665 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8666 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8667 "Samsung Exynos M1"},
8668 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8669 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8670 | AARCH64_FEATURE_RDMA
),
8672 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8673 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8674 | AARCH64_FEATURE_RDMA
),
8675 "Qualcomm QDF24XX"},
8676 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8677 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8678 "Qualcomm Saphira"},
8679 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8680 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8682 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8683 AARCH64_FEATURE_CRYPTO
),
8685 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8686 in earlier releases and is superseded by 'xgene1' in all
8688 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8689 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8690 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8691 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8692 {"generic", AARCH64_ARCH_V8
, NULL
},
8694 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8697 struct aarch64_arch_option_table
8700 const aarch64_feature_set value
;
8703 /* This list should, at a minimum, contain all the architecture names
8704 recognized by GCC. */
8705 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8706 {"all", AARCH64_ANY
},
8707 {"armv8-a", AARCH64_ARCH_V8
},
8708 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8709 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8710 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8711 {"armv8.4-a", AARCH64_ARCH_V8_4
},
8712 {"armv8.5-a", AARCH64_ARCH_V8_5
},
8713 {NULL
, AARCH64_ARCH_NONE
}
8716 /* ISA extensions. */
8717 struct aarch64_option_cpu_value_table
8720 const aarch64_feature_set value
;
8721 const aarch64_feature_set require
; /* Feature dependencies. */
8724 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8725 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8727 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
8728 | AARCH64_FEATURE_AES
8729 | AARCH64_FEATURE_SHA2
, 0),
8730 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8731 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8733 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8735 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8736 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8737 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8739 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8741 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8743 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8744 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8745 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8746 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8747 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
8748 AARCH64_FEATURE (AARCH64_FEATURE_FP
8749 | AARCH64_FEATURE_F16
, 0)},
8750 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8752 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8753 AARCH64_FEATURE (AARCH64_FEATURE_F16
8754 | AARCH64_FEATURE_SIMD
8755 | AARCH64_FEATURE_COMPNUM
, 0)},
8756 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
8757 AARCH64_FEATURE (AARCH64_FEATURE_F16
8758 | AARCH64_FEATURE_SIMD
, 0)},
8759 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
8761 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
8763 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
8765 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
8767 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
8769 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
8771 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
8773 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
8774 | AARCH64_FEATURE_SHA3
, 0),
8776 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
8778 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8781 struct aarch64_long_option_table
8783 const char *option
; /* Substring to match. */
8784 const char *help
; /* Help information. */
8785 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8786 char *deprecated
; /* If non-null, print this message. */
8789 /* Transitive closure of features depending on set. */
8790 static aarch64_feature_set
8791 aarch64_feature_disable_set (aarch64_feature_set set
)
8793 const struct aarch64_option_cpu_value_table
*opt
;
8794 aarch64_feature_set prev
= 0;
8796 while (prev
!= set
) {
8798 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8799 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8800 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8805 /* Transitive closure of dependencies of set. */
8806 static aarch64_feature_set
8807 aarch64_feature_enable_set (aarch64_feature_set set
)
8809 const struct aarch64_option_cpu_value_table
*opt
;
8810 aarch64_feature_set prev
= 0;
8812 while (prev
!= set
) {
8814 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8815 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8816 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
8822 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
8823 bfd_boolean ext_only
)
8825 /* We insist on extensions being added before being removed. We achieve
8826 this by using the ADDING_VALUE variable to indicate whether we are
8827 adding an extension (1) or removing it (0) and only allowing it to
8828 change in the order -1 -> 1 -> 0. */
8829 int adding_value
= -1;
8830 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
8832 /* Copy the feature set, so that we can modify it. */
8836 while (str
!= NULL
&& *str
!= 0)
8838 const struct aarch64_option_cpu_value_table
*opt
;
8839 const char *ext
= NULL
;
8846 as_bad (_("invalid architectural extension"));
8850 ext
= strchr (++str
, '+');
8856 optlen
= strlen (str
);
8858 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
8860 if (adding_value
!= 0)
8865 else if (optlen
> 0)
8867 if (adding_value
== -1)
8869 else if (adding_value
!= 1)
8871 as_bad (_("must specify extensions to add before specifying "
8872 "those to remove"));
8879 as_bad (_("missing architectural extension"));
8883 gas_assert (adding_value
!= -1);
8885 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8886 if (strncmp (opt
->name
, str
, optlen
) == 0)
8888 aarch64_feature_set set
;
8890 /* Add or remove the extension. */
8893 set
= aarch64_feature_enable_set (opt
->value
);
8894 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
8898 set
= aarch64_feature_disable_set (opt
->value
);
8899 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
8904 if (opt
->name
== NULL
)
8906 as_bad (_("unknown architectural extension `%s'"), str
);
8917 aarch64_parse_cpu (const char *str
)
8919 const struct aarch64_cpu_option_table
*opt
;
8920 const char *ext
= strchr (str
, '+');
8926 optlen
= strlen (str
);
8930 as_bad (_("missing cpu name `%s'"), str
);
8934 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
8935 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8937 mcpu_cpu_opt
= &opt
->value
;
8939 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
8944 as_bad (_("unknown cpu `%s'"), str
);
8949 aarch64_parse_arch (const char *str
)
8951 const struct aarch64_arch_option_table
*opt
;
8952 const char *ext
= strchr (str
, '+');
8958 optlen
= strlen (str
);
8962 as_bad (_("missing architecture name `%s'"), str
);
8966 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
8967 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8969 march_cpu_opt
= &opt
->value
;
8971 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
8976 as_bad (_("unknown architecture `%s'\n"), str
);
8981 struct aarch64_option_abi_value_table
8984 enum aarch64_abi_type value
;
8987 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
8988 {"ilp32", AARCH64_ABI_ILP32
},
8989 {"lp64", AARCH64_ABI_LP64
},
8993 aarch64_parse_abi (const char *str
)
8999 as_bad (_("missing abi name `%s'"), str
);
9003 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9004 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9006 aarch64_abi
= aarch64_abis
[i
].value
;
9010 as_bad (_("unknown abi `%s'\n"), str
);
9014 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9016 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9017 aarch64_parse_abi
, NULL
},
9018 #endif /* OBJ_ELF */
9019 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9020 aarch64_parse_cpu
, NULL
},
9021 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9022 aarch64_parse_arch
, NULL
},
9023 {NULL
, NULL
, 0, NULL
}
9027 md_parse_option (int c
, const char *arg
)
9029 struct aarch64_option_table
*opt
;
9030 struct aarch64_long_option_table
*lopt
;
9036 target_big_endian
= 1;
9042 target_big_endian
= 0;
9047 /* Listing option. Just ignore these, we don't support additional
9052 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9054 if (c
== opt
->option
[0]
9055 && ((arg
== NULL
&& opt
->option
[1] == 0)
9056 || streq (arg
, opt
->option
+ 1)))
9058 /* If the option is deprecated, tell the user. */
9059 if (opt
->deprecated
!= NULL
)
9060 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9061 arg
? arg
: "", _(opt
->deprecated
));
9063 if (opt
->var
!= NULL
)
9064 *opt
->var
= opt
->value
;
9070 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9072 /* These options are expected to have an argument. */
9073 if (c
== lopt
->option
[0]
9075 && strncmp (arg
, lopt
->option
+ 1,
9076 strlen (lopt
->option
+ 1)) == 0)
9078 /* If the option is deprecated, tell the user. */
9079 if (lopt
->deprecated
!= NULL
)
9080 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9081 _(lopt
->deprecated
));
9083 /* Call the sup-option parser. */
9084 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9095 md_show_usage (FILE * fp
)
9097 struct aarch64_option_table
*opt
;
9098 struct aarch64_long_option_table
*lopt
;
9100 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9102 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9103 if (opt
->help
!= NULL
)
9104 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9106 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9107 if (lopt
->help
!= NULL
)
9108 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9112 -EB assemble code for a big-endian cpu\n"));
9117 -EL assemble code for a little-endian cpu\n"));
9121 /* Parse a .cpu directive. */
9124 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9126 const struct aarch64_cpu_option_table
*opt
;
9132 name
= input_line_pointer
;
9133 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9134 input_line_pointer
++;
9135 saved_char
= *input_line_pointer
;
9136 *input_line_pointer
= 0;
9138 ext
= strchr (name
, '+');
9141 optlen
= ext
- name
;
9143 optlen
= strlen (name
);
9145 /* Skip the first "all" entry. */
9146 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9147 if (strlen (opt
->name
) == optlen
9148 && strncmp (name
, opt
->name
, optlen
) == 0)
9150 mcpu_cpu_opt
= &opt
->value
;
9152 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9155 cpu_variant
= *mcpu_cpu_opt
;
9157 *input_line_pointer
= saved_char
;
9158 demand_empty_rest_of_line ();
9161 as_bad (_("unknown cpu `%s'"), name
);
9162 *input_line_pointer
= saved_char
;
9163 ignore_rest_of_line ();
9167 /* Parse a .arch directive. */
9170 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9172 const struct aarch64_arch_option_table
*opt
;
9178 name
= input_line_pointer
;
9179 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9180 input_line_pointer
++;
9181 saved_char
= *input_line_pointer
;
9182 *input_line_pointer
= 0;
9184 ext
= strchr (name
, '+');
9187 optlen
= ext
- name
;
9189 optlen
= strlen (name
);
9191 /* Skip the first "all" entry. */
9192 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9193 if (strlen (opt
->name
) == optlen
9194 && strncmp (name
, opt
->name
, optlen
) == 0)
9196 mcpu_cpu_opt
= &opt
->value
;
9198 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9201 cpu_variant
= *mcpu_cpu_opt
;
9203 *input_line_pointer
= saved_char
;
9204 demand_empty_rest_of_line ();
9208 as_bad (_("unknown architecture `%s'\n"), name
);
9209 *input_line_pointer
= saved_char
;
9210 ignore_rest_of_line ();
9213 /* Parse a .arch_extension directive. */
9216 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9219 char *ext
= input_line_pointer
;;
9221 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9222 input_line_pointer
++;
9223 saved_char
= *input_line_pointer
;
9224 *input_line_pointer
= 0;
9226 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9229 cpu_variant
= *mcpu_cpu_opt
;
9231 *input_line_pointer
= saved_char
;
9232 demand_empty_rest_of_line ();
9235 /* Copy symbol information. */
9238 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9240 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);