1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
102 'templates' is for grouping together 'template' structures for opcodes
103 of the same name. This is only used for storing the insns in the grand
104 ole hash table of insns.
105 The templates themselves start at START and range up to (but not including)
110 const insn_template
*start
;
111 const insn_template
*end
;
115 /* 386 operand encoding bytes: see 386 book for details of this. */
118 unsigned int regmem
; /* codes register or memory operand */
119 unsigned int reg
; /* codes register operand (or extended opcode) */
120 unsigned int mode
; /* how to interpret regmem & reg */
124 /* x86-64 extension prefix. */
125 typedef int rex_byte
;
127 /* 386 opcode byte to code indirect addressing. */
136 /* x86 arch names, types and features */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 enum processor_type type
; /* arch type */
142 i386_cpu_flags flags
; /* cpu feature flags */
143 unsigned int skip
; /* show_arch should skip this. */
147 /* Used to turn off indicated flags. */
150 const char *name
; /* arch name */
151 unsigned int len
; /* arch string length */
152 i386_cpu_flags flags
; /* cpu feature flags */
156 static void update_code_flag (int, int);
157 static void set_code_flag (int);
158 static void set_16bit_gcc_code_flag (int);
159 static void set_intel_syntax (int);
160 static void set_intel_mnemonic (int);
161 static void set_allow_index_reg (int);
162 static void set_check (int);
163 static void set_cpu_arch (int);
165 static void pe_directive_secrel (int);
167 static void signed_cons (int);
168 static char *output_invalid (int c
);
169 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
171 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
173 static int i386_att_operand (char *);
174 static int i386_intel_operand (char *, int);
175 static int i386_intel_simplify (expressionS
*);
176 static int i386_intel_parse_name (const char *, expressionS
*);
177 static const reg_entry
*parse_register (char *, char **);
178 static char *parse_insn (char *, char *);
179 static char *parse_operands (char *, const char *);
180 static void swap_operands (void);
181 static void swap_2_operands (int, int);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Has MMX register operands. */
354 bfd_boolean has_regmmx
;
356 /* Has XMM register operands. */
357 bfd_boolean has_regxmm
;
359 /* Has YMM register operands. */
360 bfd_boolean has_regymm
;
362 /* Has ZMM register operands. */
363 bfd_boolean has_regzmm
;
365 /* RM and SIB are the modrm byte and the sib byte where the
366 addressing modes of this insn are encoded. */
373 /* Masking attributes. */
374 struct Mask_Operation
*mask
;
376 /* Rounding control and SAE attributes. */
377 struct RC_Operation
*rounding
;
379 /* Broadcasting attributes. */
380 struct Broadcast_Operation
*broadcast
;
382 /* Compressed disp8*N attribute. */
383 unsigned int memshift
;
385 /* Prefer load or store in encoding. */
388 dir_encoding_default
= 0,
394 /* Prefer 8bit or 32bit displacement in encoding. */
397 disp_encoding_default
= 0,
402 /* Prefer the REX byte in encoding. */
403 bfd_boolean rex_encoding
;
405 /* Disable instruction size optimization. */
406 bfd_boolean no_optimize
;
408 /* How to encode vector instructions. */
411 vex_encoding_default
= 0,
418 const char *rep_prefix
;
421 const char *hle_prefix
;
423 /* Have BND prefix. */
424 const char *bnd_prefix
;
426 /* Have NOTRACK prefix. */
427 const char *notrack_prefix
;
430 enum i386_error error
;
433 typedef struct _i386_insn i386_insn
;
435 /* Link RC type with corresponding string, that'll be looked for in
444 static const struct RC_name RC_NamesTable
[] =
446 { rne
, STRING_COMMA_LEN ("rn-sae") },
447 { rd
, STRING_COMMA_LEN ("rd-sae") },
448 { ru
, STRING_COMMA_LEN ("ru-sae") },
449 { rz
, STRING_COMMA_LEN ("rz-sae") },
450 { saeonly
, STRING_COMMA_LEN ("sae") },
453 /* List of chars besides those in app.c:symbol_chars that can start an
454 operand. Used to prevent the scrubber eating vital white-space. */
455 const char extra_symbol_chars
[] = "*%-([{}"
464 #if (defined (TE_I386AIX) \
465 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
466 && !defined (TE_GNU) \
467 && !defined (TE_LINUX) \
468 && !defined (TE_NACL) \
469 && !defined (TE_FreeBSD) \
470 && !defined (TE_DragonFly) \
471 && !defined (TE_NetBSD)))
472 /* This array holds the chars that always start a comment. If the
473 pre-processor is disabled, these aren't very useful. The option
474 --divide will remove '/' from this list. */
475 const char *i386_comment_chars
= "#/";
476 #define SVR4_COMMENT_CHARS 1
477 #define PREFIX_SEPARATOR '\\'
480 const char *i386_comment_chars
= "#";
481 #define PREFIX_SEPARATOR '/'
484 /* This array holds the chars that only start a comment at the beginning of
485 a line. If the line seems to have the form '# 123 filename'
486 .line and .file directives will appear in the pre-processed output.
487 Note that input_file.c hand checks for '#' at the beginning of the
488 first line of the input file. This is because the compiler outputs
489 #NO_APP at the beginning of its output.
490 Also note that comments started like this one will always work if
491 '/' isn't otherwise defined. */
492 const char line_comment_chars
[] = "#/";
494 const char line_separator_chars
[] = ";";
496 /* Chars that can be used to separate mant from exp in floating point
498 const char EXP_CHARS
[] = "eE";
500 /* Chars that mean this number is a floating point constant
503 const char FLT_CHARS
[] = "fFdDxX";
505 /* Tables for lexical analysis. */
506 static char mnemonic_chars
[256];
507 static char register_chars
[256];
508 static char operand_chars
[256];
509 static char identifier_chars
[256];
510 static char digit_chars
[256];
512 /* Lexical macros. */
513 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
514 #define is_operand_char(x) (operand_chars[(unsigned char) x])
515 #define is_register_char(x) (register_chars[(unsigned char) x])
516 #define is_space_char(x) ((x) == ' ')
517 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
518 #define is_digit_char(x) (digit_chars[(unsigned char) x])
520 /* All non-digit non-letter characters that may occur in an operand. */
521 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
523 /* md_assemble() always leaves the strings it's passed unaltered. To
524 effect this we maintain a stack of saved characters that we've smashed
525 with '\0's (indicating end of strings for various sub-fields of the
526 assembler instruction). */
527 static char save_stack
[32];
528 static char *save_stack_p
;
529 #define END_STRING_AND_SAVE(s) \
530 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
531 #define RESTORE_END_STRING(s) \
532 do { *(s) = *--save_stack_p; } while (0)
534 /* The instruction we're assembling. */
537 /* Possible templates for current insn. */
538 static const templates
*current_templates
;
540 /* Per instruction expressionS buffers: max displacements & immediates. */
541 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
542 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
544 /* Current operand we are working on. */
545 static int this_operand
= -1;
547 /* We support four different modes. FLAG_CODE variable is used to distinguish
555 static enum flag_code flag_code
;
556 static unsigned int object_64bit
;
557 static unsigned int disallow_64bit_reloc
;
558 static int use_rela_relocations
= 0;
560 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
564 /* The ELF ABI to use. */
572 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
575 #if defined (TE_PE) || defined (TE_PEP)
576 /* Use big object file format. */
577 static int use_big_obj
= 0;
580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
581 /* 1 if generating code for a shared library. */
582 static int shared
= 0;
585 /* 1 for intel syntax,
587 static int intel_syntax
= 0;
589 /* 1 for Intel64 ISA,
593 /* 1 for intel mnemonic,
594 0 if att mnemonic. */
595 static int intel_mnemonic
= !SYSV386_COMPAT
;
597 /* 1 if pseudo registers are permitted. */
598 static int allow_pseudo_reg
= 0;
600 /* 1 if register prefix % not required. */
601 static int allow_naked_reg
= 0;
603 /* 1 if the assembler should add BND prefix for all control-transferring
604 instructions supporting it, even if this prefix wasn't specified
606 static int add_bnd_prefix
= 0;
608 /* 1 if pseudo index register, eiz/riz, is allowed . */
609 static int allow_index_reg
= 0;
611 /* 1 if the assembler should ignore LOCK prefix, even if it was
612 specified explicitly. */
613 static int omit_lock_prefix
= 0;
615 /* 1 if the assembler should encode lfence, mfence, and sfence as
616 "lock addl $0, (%{re}sp)". */
617 static int avoid_fence
= 0;
619 /* 1 if the assembler should generate relax relocations. */
621 static int generate_relax_relocations
622 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
624 static enum check_kind
630 sse_check
, operand_check
= check_warning
;
633 1. Clear the REX_W bit with register operand if possible.
634 2. Above plus use 128bit vector instruction to clear the full vector
637 static int optimize
= 0;
640 1. Clear the REX_W bit with register operand if possible.
641 2. Above plus use 128bit vector instruction to clear the full vector
643 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
646 static int optimize_for_space
= 0;
648 /* Register prefix used for error message. */
649 static const char *register_prefix
= "%";
651 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
652 leave, push, and pop instructions so that gcc has the same stack
653 frame as in 32 bit mode. */
654 static char stackop_size
= '\0';
656 /* Non-zero to optimize code alignment. */
657 int optimize_align_code
= 1;
659 /* Non-zero to quieten some warnings. */
660 static int quiet_warnings
= 0;
663 static const char *cpu_arch_name
= NULL
;
664 static char *cpu_sub_arch_name
= NULL
;
666 /* CPU feature flags. */
667 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
669 /* If we have selected a cpu we are generating instructions for. */
670 static int cpu_arch_tune_set
= 0;
672 /* Cpu we are generating instructions for. */
673 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
675 /* CPU feature flags of cpu we are generating instructions for. */
676 static i386_cpu_flags cpu_arch_tune_flags
;
678 /* CPU instruction set architecture used. */
679 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of instruction set architecture used. */
682 i386_cpu_flags cpu_arch_isa_flags
;
684 /* If set, conditional jumps are not automatically promoted to handle
685 larger than a byte offset. */
686 static unsigned int no_cond_jump_promotion
= 0;
688 /* Encode SSE instructions with VEX prefix. */
689 static unsigned int sse2avx
;
691 /* Encode scalar AVX instructions with specific vector length. */
698 /* Encode VEX WIG instructions with specific vex.w. */
705 /* Encode scalar EVEX LIG instructions with specific vector length. */
713 /* Encode EVEX WIG instructions with specific evex.w. */
720 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
721 static enum rc_type evexrcig
= rne
;
723 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
724 static symbolS
*GOT_symbol
;
726 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
727 unsigned int x86_dwarf2_return_column
;
729 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
730 int x86_cie_data_alignment
;
732 /* Interface to relax_segment.
733 There are 3 major relax states for 386 jump insns because the
734 different types of jumps add different sizes to frags when we're
735 figuring out what sort of jump to choose to reach a given label. */
738 #define UNCOND_JUMP 0
740 #define COND_JUMP86 2
745 #define SMALL16 (SMALL | CODE16)
747 #define BIG16 (BIG | CODE16)
751 #define INLINE __inline__
757 #define ENCODE_RELAX_STATE(type, size) \
758 ((relax_substateT) (((type) << 2) | (size)))
759 #define TYPE_FROM_RELAX_STATE(s) \
761 #define DISP_SIZE_FROM_RELAX_STATE(s) \
762 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
764 /* This table is used by relax_frag to promote short jumps to long
765 ones where necessary. SMALL (short) jumps may be promoted to BIG
766 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
767 don't allow a short jump in a 32 bit code segment to be promoted to
768 a 16 bit offset jump because it's slower (requires data size
769 prefix), and doesn't work, unless the destination is in the bottom
770 64k of the code segment (The top 16 bits of eip are zeroed). */
772 const relax_typeS md_relax_table
[] =
775 1) most positive reach of this state,
776 2) most negative reach of this state,
777 3) how many bytes this mode will have in the variable part of the frag
778 4) which index into the table to try if we can't fit into this one. */
780 /* UNCOND_JUMP states. */
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
783 /* dword jmp adds 4 bytes to frag:
784 0 extra opcode bytes, 4 displacement bytes. */
786 /* word jmp adds 2 byte2 to frag:
787 0 extra opcode bytes, 2 displacement bytes. */
790 /* COND_JUMP states. */
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
792 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
793 /* dword conditionals adds 5 bytes to frag:
794 1 extra opcode byte, 4 displacement bytes. */
796 /* word conditionals add 3 bytes to frag:
797 1 extra opcode byte, 2 displacement bytes. */
800 /* COND_JUMP86 states. */
801 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
802 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
803 /* dword conditionals adds 5 bytes to frag:
804 1 extra opcode byte, 4 displacement bytes. */
806 /* word conditionals add 4 bytes to frag:
807 1 displacement byte and a 3 byte long branch insn. */
811 static const arch_entry cpu_arch
[] =
813 /* Do not replace the first two entries - i386_target_format()
814 relies on them being there in this order. */
815 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
816 CPU_GENERIC32_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
818 CPU_GENERIC64_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
821 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
823 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
827 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
829 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
831 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
833 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
835 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
836 CPU_PENTIUMPRO_FLAGS
, 0 },
837 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
841 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
843 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
845 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
846 CPU_NOCONA_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
849 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
851 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
852 CPU_CORE2_FLAGS
, 1 },
853 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
854 CPU_CORE2_FLAGS
, 0 },
855 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
856 CPU_COREI7_FLAGS
, 0 },
857 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
859 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
861 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
862 CPU_IAMCU_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
865 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
867 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
868 CPU_ATHLON_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
871 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
873 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
875 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
876 CPU_AMDFAM10_FLAGS
, 0 },
877 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
878 CPU_BDVER1_FLAGS
, 0 },
879 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
880 CPU_BDVER2_FLAGS
, 0 },
881 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
882 CPU_BDVER3_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
884 CPU_BDVER4_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
886 CPU_ZNVER1_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
888 CPU_ZNVER2_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
890 CPU_BTVER1_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
892 CPU_BTVER2_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
914 CPU_SSSE3_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4_1_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
918 CPU_SSE4_2_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
920 CPU_SSE4_2_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
926 CPU_AVX512F_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
928 CPU_AVX512CD_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
930 CPU_AVX512ER_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512PF_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512DQ_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512BW_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512VL_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
942 CPU_VMFUNC_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
946 CPU_XSAVE_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
948 CPU_XSAVEOPT_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
950 CPU_XSAVEC_FLAGS
, 0 },
951 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVES_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
956 CPU_PCLMUL_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
958 CPU_PCLMUL_FLAGS
, 1 },
959 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
960 CPU_FSGSBASE_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
962 CPU_RDRND_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
976 CPU_MOVBE_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
982 CPU_LZCNT_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
988 CPU_INVPCID_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
990 CPU_CLFLUSH_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
994 CPU_SYSCALL_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
996 CPU_RDTSCP_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
998 CPU_3DNOW_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1000 CPU_3DNOWA_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1002 CPU_PADLOCK_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1004 CPU_SVME_FLAGS
, 1 },
1005 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1006 CPU_SVME_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1011 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1018 CPU_RDSEED_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1020 CPU_PRFCHW_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1022 CPU_SMAP_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1028 CPU_CLFLUSHOPT_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1030 CPU_PREFETCHWT1_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1034 CPU_CLWB_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1036 CPU_AVX512IFMA_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1038 CPU_AVX512VBMI_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1040 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_VBMI2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_VNNI_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_BITALG_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1052 CPU_CLZERO_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1054 CPU_MWAITX_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1056 CPU_OSPKE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1058 CPU_RDPID_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1060 CPU_PTWRITE_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1063 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1064 CPU_SHSTK_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1066 CPU_GFNI_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1068 CPU_VAES_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1070 CPU_VPCLMULQDQ_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1072 CPU_WBNOINVD_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1074 CPU_PCONFIG_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1076 CPU_WAITPKG_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1078 CPU_CLDEMOTE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1080 CPU_MOVDIRI_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1082 CPU_MOVDIR64B_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1084 CPU_AVX512_BF16_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1086 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1089 static const noarch_entry cpu_noarch
[] =
1091 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1092 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1093 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1094 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1095 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1096 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1097 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1098 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1099 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1100 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1101 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1102 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1103 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1104 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1105 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1106 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1107 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1108 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1109 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1122 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1123 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1124 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1125 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1126 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1127 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1131 /* Like s_lcomm_internal in gas/read.c but the alignment string
1132 is allowed to be optional. */
1135 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1142 && *input_line_pointer
== ',')
1144 align
= parse_align (needs_align
- 1);
1146 if (align
== (addressT
) -1)
1161 bss_alloc (symbolP
, size
, align
);
1166 pe_lcomm (int needs_align
)
1168 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1172 const pseudo_typeS md_pseudo_table
[] =
1174 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1175 {"align", s_align_bytes
, 0},
1177 {"align", s_align_ptwo
, 0},
1179 {"arch", set_cpu_arch
, 0},
1183 {"lcomm", pe_lcomm
, 1},
1185 {"ffloat", float_cons
, 'f'},
1186 {"dfloat", float_cons
, 'd'},
1187 {"tfloat", float_cons
, 'x'},
1189 {"slong", signed_cons
, 4},
1190 {"noopt", s_ignore
, 0},
1191 {"optim", s_ignore
, 0},
1192 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1193 {"code16", set_code_flag
, CODE_16BIT
},
1194 {"code32", set_code_flag
, CODE_32BIT
},
1196 {"code64", set_code_flag
, CODE_64BIT
},
1198 {"intel_syntax", set_intel_syntax
, 1},
1199 {"att_syntax", set_intel_syntax
, 0},
1200 {"intel_mnemonic", set_intel_mnemonic
, 1},
1201 {"att_mnemonic", set_intel_mnemonic
, 0},
1202 {"allow_index_reg", set_allow_index_reg
, 1},
1203 {"disallow_index_reg", set_allow_index_reg
, 0},
1204 {"sse_check", set_check
, 0},
1205 {"operand_check", set_check
, 1},
1206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1207 {"largecomm", handle_large_common
, 0},
1209 {"file", dwarf2_directive_file
, 0},
1210 {"loc", dwarf2_directive_loc
, 0},
1211 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1214 {"secrel32", pe_directive_secrel
, 0},
1219 /* For interface with expression (). */
1220 extern char *input_line_pointer
;
1222 /* Hash table for instruction mnemonic lookup. */
1223 static struct hash_control
*op_hash
;
1225 /* Hash table for register lookup. */
1226 static struct hash_control
*reg_hash
;
1228 /* Various efficient no-op patterns for aligning code labels.
1229 Note: Don't try to assemble the instructions in the comments.
1230 0L and 0w are not legal. */
1231 static const unsigned char f32_1
[] =
1233 static const unsigned char f32_2
[] =
1234 {0x66,0x90}; /* xchg %ax,%ax */
1235 static const unsigned char f32_3
[] =
1236 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1237 static const unsigned char f32_4
[] =
1238 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1239 static const unsigned char f32_6
[] =
1240 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1241 static const unsigned char f32_7
[] =
1242 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1243 static const unsigned char f16_3
[] =
1244 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1245 static const unsigned char f16_4
[] =
1246 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1247 static const unsigned char jump_disp8
[] =
1248 {0xeb}; /* jmp disp8 */
1249 static const unsigned char jump32_disp32
[] =
1250 {0xe9}; /* jmp disp32 */
1251 static const unsigned char jump16_disp32
[] =
1252 {0x66,0xe9}; /* jmp disp32 */
1253 /* 32-bit NOPs patterns. */
1254 static const unsigned char *const f32_patt
[] = {
1255 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1257 /* 16-bit NOPs patterns. */
1258 static const unsigned char *const f16_patt
[] = {
1259 f32_1
, f32_2
, f16_3
, f16_4
1261 /* nopl (%[re]ax) */
1262 static const unsigned char alt_3
[] =
1264 /* nopl 0(%[re]ax) */
1265 static const unsigned char alt_4
[] =
1266 {0x0f,0x1f,0x40,0x00};
1267 /* nopl 0(%[re]ax,%[re]ax,1) */
1268 static const unsigned char alt_5
[] =
1269 {0x0f,0x1f,0x44,0x00,0x00};
1270 /* nopw 0(%[re]ax,%[re]ax,1) */
1271 static const unsigned char alt_6
[] =
1272 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1273 /* nopl 0L(%[re]ax) */
1274 static const unsigned char alt_7
[] =
1275 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1276 /* nopl 0L(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_8
[] =
1278 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1279 /* nopw 0L(%[re]ax,%[re]ax,1) */
1280 static const unsigned char alt_9
[] =
1281 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1282 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1283 static const unsigned char alt_10
[] =
1284 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1285 /* data16 nopw %cs:0L(%eax,%eax,1) */
1286 static const unsigned char alt_11
[] =
1287 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1288 /* 32-bit and 64-bit NOPs patterns. */
1289 static const unsigned char *const alt_patt
[] = {
1290 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1291 alt_9
, alt_10
, alt_11
1294 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1295 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1298 i386_output_nops (char *where
, const unsigned char *const *patt
,
1299 int count
, int max_single_nop_size
)
1302 /* Place the longer NOP first. */
1305 const unsigned char *nops
;
1307 if (max_single_nop_size
< 1)
1309 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1310 max_single_nop_size
);
1314 nops
= patt
[max_single_nop_size
- 1];
1316 /* Use the smaller one if the requsted one isn't available. */
1319 max_single_nop_size
--;
1320 nops
= patt
[max_single_nop_size
- 1];
1323 last
= count
% max_single_nop_size
;
1326 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1327 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1331 nops
= patt
[last
- 1];
1334 /* Use the smaller one plus one-byte NOP if the needed one
1337 nops
= patt
[last
- 1];
1338 memcpy (where
+ offset
, nops
, last
);
1339 where
[offset
+ last
] = *patt
[0];
1342 memcpy (where
+ offset
, nops
, last
);
1347 fits_in_imm7 (offsetT num
)
1349 return (num
& 0x7f) == num
;
1353 fits_in_imm31 (offsetT num
)
1355 return (num
& 0x7fffffff) == num
;
1358 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1359 single NOP instruction LIMIT. */
1362 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1364 const unsigned char *const *patt
= NULL
;
1365 int max_single_nop_size
;
1366 /* Maximum number of NOPs before switching to jump over NOPs. */
1367 int max_number_of_nops
;
1369 switch (fragP
->fr_type
)
1378 /* We need to decide which NOP sequence to use for 32bit and
1379 64bit. When -mtune= is used:
1381 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1382 PROCESSOR_GENERIC32, f32_patt will be used.
1383 2. For the rest, alt_patt will be used.
1385 When -mtune= isn't used, alt_patt will be used if
1386 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1389 When -march= or .arch is used, we can't use anything beyond
1390 cpu_arch_isa_flags. */
1392 if (flag_code
== CODE_16BIT
)
1395 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1396 /* Limit number of NOPs to 2 in 16-bit mode. */
1397 max_number_of_nops
= 2;
1401 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1403 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1404 switch (cpu_arch_tune
)
1406 case PROCESSOR_UNKNOWN
:
1407 /* We use cpu_arch_isa_flags to check if we SHOULD
1408 optimize with nops. */
1409 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1414 case PROCESSOR_PENTIUM4
:
1415 case PROCESSOR_NOCONA
:
1416 case PROCESSOR_CORE
:
1417 case PROCESSOR_CORE2
:
1418 case PROCESSOR_COREI7
:
1419 case PROCESSOR_L1OM
:
1420 case PROCESSOR_K1OM
:
1421 case PROCESSOR_GENERIC64
:
1423 case PROCESSOR_ATHLON
:
1425 case PROCESSOR_AMDFAM10
:
1427 case PROCESSOR_ZNVER
:
1431 case PROCESSOR_I386
:
1432 case PROCESSOR_I486
:
1433 case PROCESSOR_PENTIUM
:
1434 case PROCESSOR_PENTIUMPRO
:
1435 case PROCESSOR_IAMCU
:
1436 case PROCESSOR_GENERIC32
:
1443 switch (fragP
->tc_frag_data
.tune
)
1445 case PROCESSOR_UNKNOWN
:
1446 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1447 PROCESSOR_UNKNOWN. */
1451 case PROCESSOR_I386
:
1452 case PROCESSOR_I486
:
1453 case PROCESSOR_PENTIUM
:
1454 case PROCESSOR_IAMCU
:
1456 case PROCESSOR_ATHLON
:
1458 case PROCESSOR_AMDFAM10
:
1460 case PROCESSOR_ZNVER
:
1462 case PROCESSOR_GENERIC32
:
1463 /* We use cpu_arch_isa_flags to check if we CAN optimize
1465 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1470 case PROCESSOR_PENTIUMPRO
:
1471 case PROCESSOR_PENTIUM4
:
1472 case PROCESSOR_NOCONA
:
1473 case PROCESSOR_CORE
:
1474 case PROCESSOR_CORE2
:
1475 case PROCESSOR_COREI7
:
1476 case PROCESSOR_L1OM
:
1477 case PROCESSOR_K1OM
:
1478 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1483 case PROCESSOR_GENERIC64
:
1489 if (patt
== f32_patt
)
1491 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1492 /* Limit number of NOPs to 2 for older processors. */
1493 max_number_of_nops
= 2;
1497 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1498 /* Limit number of NOPs to 7 for newer processors. */
1499 max_number_of_nops
= 7;
1504 limit
= max_single_nop_size
;
1506 if (fragP
->fr_type
== rs_fill_nop
)
1508 /* Output NOPs for .nop directive. */
1509 if (limit
> max_single_nop_size
)
1511 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1512 _("invalid single nop size: %d "
1513 "(expect within [0, %d])"),
1514 limit
, max_single_nop_size
);
1519 fragP
->fr_var
= count
;
1521 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1523 /* Generate jump over NOPs. */
1524 offsetT disp
= count
- 2;
1525 if (fits_in_imm7 (disp
))
1527 /* Use "jmp disp8" if possible. */
1529 where
[0] = jump_disp8
[0];
1535 unsigned int size_of_jump
;
1537 if (flag_code
== CODE_16BIT
)
1539 where
[0] = jump16_disp32
[0];
1540 where
[1] = jump16_disp32
[1];
1545 where
[0] = jump32_disp32
[0];
1549 count
-= size_of_jump
+ 4;
1550 if (!fits_in_imm31 (count
))
1552 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1553 _("jump over nop padding out of range"));
1557 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1558 where
+= size_of_jump
+ 4;
1562 /* Generate multiple NOPs. */
1563 i386_output_nops (where
, patt
, count
, limit
);
1567 operand_type_all_zero (const union i386_operand_type
*x
)
1569 switch (ARRAY_SIZE(x
->array
))
1580 return !x
->array
[0];
1587 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1589 switch (ARRAY_SIZE(x
->array
))
1607 operand_type_equal (const union i386_operand_type
*x
,
1608 const union i386_operand_type
*y
)
1610 switch (ARRAY_SIZE(x
->array
))
1613 if (x
->array
[2] != y
->array
[2])
1617 if (x
->array
[1] != y
->array
[1])
1621 return x
->array
[0] == y
->array
[0];
1629 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1631 switch (ARRAY_SIZE(x
->array
))
1646 return !x
->array
[0];
1653 cpu_flags_equal (const union i386_cpu_flags
*x
,
1654 const union i386_cpu_flags
*y
)
1656 switch (ARRAY_SIZE(x
->array
))
1659 if (x
->array
[3] != y
->array
[3])
1663 if (x
->array
[2] != y
->array
[2])
1667 if (x
->array
[1] != y
->array
[1])
1671 return x
->array
[0] == y
->array
[0];
1679 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1681 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1682 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1685 static INLINE i386_cpu_flags
1686 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1688 switch (ARRAY_SIZE (x
.array
))
1691 x
.array
[3] &= y
.array
[3];
1694 x
.array
[2] &= y
.array
[2];
1697 x
.array
[1] &= y
.array
[1];
1700 x
.array
[0] &= y
.array
[0];
1708 static INLINE i386_cpu_flags
1709 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1711 switch (ARRAY_SIZE (x
.array
))
1714 x
.array
[3] |= y
.array
[3];
1717 x
.array
[2] |= y
.array
[2];
1720 x
.array
[1] |= y
.array
[1];
1723 x
.array
[0] |= y
.array
[0];
1731 static INLINE i386_cpu_flags
1732 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1734 switch (ARRAY_SIZE (x
.array
))
1737 x
.array
[3] &= ~y
.array
[3];
1740 x
.array
[2] &= ~y
.array
[2];
1743 x
.array
[1] &= ~y
.array
[1];
1746 x
.array
[0] &= ~y
.array
[0];
1754 #define CPU_FLAGS_ARCH_MATCH 0x1
1755 #define CPU_FLAGS_64BIT_MATCH 0x2
1757 #define CPU_FLAGS_PERFECT_MATCH \
1758 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1760 /* Return CPU flags match bits. */
1763 cpu_flags_match (const insn_template
*t
)
1765 i386_cpu_flags x
= t
->cpu_flags
;
1766 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1768 x
.bitfield
.cpu64
= 0;
1769 x
.bitfield
.cpuno64
= 0;
1771 if (cpu_flags_all_zero (&x
))
1773 /* This instruction is available on all archs. */
1774 match
|= CPU_FLAGS_ARCH_MATCH
;
1778 /* This instruction is available only on some archs. */
1779 i386_cpu_flags cpu
= cpu_arch_flags
;
1781 /* AVX512VL is no standalone feature - match it and then strip it. */
1782 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1784 x
.bitfield
.cpuavx512vl
= 0;
1786 cpu
= cpu_flags_and (x
, cpu
);
1787 if (!cpu_flags_all_zero (&cpu
))
1789 if (x
.bitfield
.cpuavx
)
1791 /* We need to check a few extra flags with AVX. */
1792 if (cpu
.bitfield
.cpuavx
1793 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1794 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1795 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1796 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1797 match
|= CPU_FLAGS_ARCH_MATCH
;
1799 else if (x
.bitfield
.cpuavx512f
)
1801 /* We need to check a few extra flags with AVX512F. */
1802 if (cpu
.bitfield
.cpuavx512f
1803 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1804 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1805 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1806 match
|= CPU_FLAGS_ARCH_MATCH
;
1809 match
|= CPU_FLAGS_ARCH_MATCH
;
1815 static INLINE i386_operand_type
1816 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1818 switch (ARRAY_SIZE (x
.array
))
1821 x
.array
[2] &= y
.array
[2];
1824 x
.array
[1] &= y
.array
[1];
1827 x
.array
[0] &= y
.array
[0];
1835 static INLINE i386_operand_type
1836 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1838 switch (ARRAY_SIZE (x
.array
))
1841 x
.array
[2] &= ~y
.array
[2];
1844 x
.array
[1] &= ~y
.array
[1];
1847 x
.array
[0] &= ~y
.array
[0];
1855 static INLINE i386_operand_type
1856 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1858 switch (ARRAY_SIZE (x
.array
))
1861 x
.array
[2] |= y
.array
[2];
1864 x
.array
[1] |= y
.array
[1];
1867 x
.array
[0] |= y
.array
[0];
1875 static INLINE i386_operand_type
1876 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1878 switch (ARRAY_SIZE (x
.array
))
1881 x
.array
[2] ^= y
.array
[2];
1884 x
.array
[1] ^= y
.array
[1];
1887 x
.array
[0] ^= y
.array
[0];
1895 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1896 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1897 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1898 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1899 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1900 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1901 static const i386_operand_type anydisp
1902 = OPERAND_TYPE_ANYDISP
;
1903 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1904 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1905 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1906 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1907 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1908 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1909 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1910 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1911 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1912 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1913 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1914 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1925 operand_type_check (i386_operand_type t
, enum operand_type c
)
1930 return t
.bitfield
.reg
;
1933 return (t
.bitfield
.imm8
1937 || t
.bitfield
.imm32s
1938 || t
.bitfield
.imm64
);
1941 return (t
.bitfield
.disp8
1942 || t
.bitfield
.disp16
1943 || t
.bitfield
.disp32
1944 || t
.bitfield
.disp32s
1945 || t
.bitfield
.disp64
);
1948 return (t
.bitfield
.disp8
1949 || t
.bitfield
.disp16
1950 || t
.bitfield
.disp32
1951 || t
.bitfield
.disp32s
1952 || t
.bitfield
.disp64
1953 || t
.bitfield
.baseindex
);
1962 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1963 between operand GIVEN and opeand WANTED for instruction template T. */
1966 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1969 return !((i
.types
[given
].bitfield
.byte
1970 && !t
->operand_types
[wanted
].bitfield
.byte
)
1971 || (i
.types
[given
].bitfield
.word
1972 && !t
->operand_types
[wanted
].bitfield
.word
)
1973 || (i
.types
[given
].bitfield
.dword
1974 && !t
->operand_types
[wanted
].bitfield
.dword
)
1975 || (i
.types
[given
].bitfield
.qword
1976 && !t
->operand_types
[wanted
].bitfield
.qword
)
1977 || (i
.types
[given
].bitfield
.tbyte
1978 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1981 /* Return 1 if there is no conflict in SIMD register between operand
1982 GIVEN and opeand WANTED for instruction template T. */
1985 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1988 return !((i
.types
[given
].bitfield
.xmmword
1989 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1990 || (i
.types
[given
].bitfield
.ymmword
1991 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1992 || (i
.types
[given
].bitfield
.zmmword
1993 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1996 /* Return 1 if there is no conflict in any size between operand GIVEN
1997 and opeand WANTED for instruction template T. */
2000 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2003 return (match_operand_size (t
, wanted
, given
)
2004 && !((i
.types
[given
].bitfield
.unspecified
2006 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2007 || (i
.types
[given
].bitfield
.fword
2008 && !t
->operand_types
[wanted
].bitfield
.fword
)
2009 /* For scalar opcode templates to allow register and memory
2010 operands at the same time, some special casing is needed
2011 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2012 down-conversion vpmov*. */
2013 || ((t
->operand_types
[wanted
].bitfield
.regsimd
2014 && !t
->opcode_modifier
.broadcast
2015 && (t
->operand_types
[wanted
].bitfield
.byte
2016 || t
->operand_types
[wanted
].bitfield
.word
2017 || t
->operand_types
[wanted
].bitfield
.dword
2018 || t
->operand_types
[wanted
].bitfield
.qword
))
2019 ? (i
.types
[given
].bitfield
.xmmword
2020 || i
.types
[given
].bitfield
.ymmword
2021 || i
.types
[given
].bitfield
.zmmword
)
2022 : !match_simd_size(t
, wanted
, given
))));
2025 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2026 operands for instruction template T, and it has MATCH_REVERSE set if there
2027 is no size conflict on any operands for the template with operands reversed
2028 (and the template allows for reversing in the first place). */
2030 #define MATCH_STRAIGHT 1
2031 #define MATCH_REVERSE 2
2033 static INLINE
unsigned int
2034 operand_size_match (const insn_template
*t
)
2036 unsigned int j
, match
= MATCH_STRAIGHT
;
2038 /* Don't check jump instructions. */
2039 if (t
->opcode_modifier
.jump
2040 || t
->opcode_modifier
.jumpbyte
2041 || t
->opcode_modifier
.jumpdword
2042 || t
->opcode_modifier
.jumpintersegment
)
2045 /* Check memory and accumulator operand size. */
2046 for (j
= 0; j
< i
.operands
; j
++)
2048 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2049 && t
->operand_types
[j
].bitfield
.anysize
)
2052 if (t
->operand_types
[j
].bitfield
.reg
2053 && !match_operand_size (t
, j
, j
))
2059 if (t
->operand_types
[j
].bitfield
.regsimd
2060 && !match_simd_size (t
, j
, j
))
2066 if (t
->operand_types
[j
].bitfield
.acc
2067 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2073 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2080 if (!t
->opcode_modifier
.d
)
2084 i
.error
= operand_size_mismatch
;
2088 /* Check reverse. */
2089 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2091 for (j
= 0; j
< i
.operands
; j
++)
2093 unsigned int given
= i
.operands
- j
- 1;
2095 if (t
->operand_types
[j
].bitfield
.reg
2096 && !match_operand_size (t
, j
, given
))
2099 if (t
->operand_types
[j
].bitfield
.regsimd
2100 && !match_simd_size (t
, j
, given
))
2103 if (t
->operand_types
[j
].bitfield
.acc
2104 && (!match_operand_size (t
, j
, given
)
2105 || !match_simd_size (t
, j
, given
)))
2108 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2112 return match
| MATCH_REVERSE
;
2116 operand_type_match (i386_operand_type overlap
,
2117 i386_operand_type given
)
2119 i386_operand_type temp
= overlap
;
2121 temp
.bitfield
.jumpabsolute
= 0;
2122 temp
.bitfield
.unspecified
= 0;
2123 temp
.bitfield
.byte
= 0;
2124 temp
.bitfield
.word
= 0;
2125 temp
.bitfield
.dword
= 0;
2126 temp
.bitfield
.fword
= 0;
2127 temp
.bitfield
.qword
= 0;
2128 temp
.bitfield
.tbyte
= 0;
2129 temp
.bitfield
.xmmword
= 0;
2130 temp
.bitfield
.ymmword
= 0;
2131 temp
.bitfield
.zmmword
= 0;
2132 if (operand_type_all_zero (&temp
))
2135 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2136 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2140 i
.error
= operand_type_mismatch
;
2144 /* If given types g0 and g1 are registers they must be of the same type
2145 unless the expected operand type register overlap is null.
2146 Memory operand size of certain SIMD instructions is also being checked
2150 operand_type_register_match (i386_operand_type g0
,
2151 i386_operand_type t0
,
2152 i386_operand_type g1
,
2153 i386_operand_type t1
)
2155 if (!g0
.bitfield
.reg
2156 && !g0
.bitfield
.regsimd
2157 && (!operand_type_check (g0
, anymem
)
2158 || g0
.bitfield
.unspecified
2159 || !t0
.bitfield
.regsimd
))
2162 if (!g1
.bitfield
.reg
2163 && !g1
.bitfield
.regsimd
2164 && (!operand_type_check (g1
, anymem
)
2165 || g1
.bitfield
.unspecified
2166 || !t1
.bitfield
.regsimd
))
2169 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2170 && g0
.bitfield
.word
== g1
.bitfield
.word
2171 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2172 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2173 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2174 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2175 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2178 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2179 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2180 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2181 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2182 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2183 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2184 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2187 i
.error
= register_type_mismatch
;
2192 static INLINE
unsigned int
2193 register_number (const reg_entry
*r
)
2195 unsigned int nr
= r
->reg_num
;
2197 if (r
->reg_flags
& RegRex
)
2200 if (r
->reg_flags
& RegVRex
)
2206 static INLINE
unsigned int
2207 mode_from_disp_size (i386_operand_type t
)
2209 if (t
.bitfield
.disp8
)
2211 else if (t
.bitfield
.disp16
2212 || t
.bitfield
.disp32
2213 || t
.bitfield
.disp32s
)
2220 fits_in_signed_byte (addressT num
)
2222 return num
+ 0x80 <= 0xff;
2226 fits_in_unsigned_byte (addressT num
)
2232 fits_in_unsigned_word (addressT num
)
2234 return num
<= 0xffff;
2238 fits_in_signed_word (addressT num
)
2240 return num
+ 0x8000 <= 0xffff;
2244 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2249 return num
+ 0x80000000 <= 0xffffffff;
2251 } /* fits_in_signed_long() */
2254 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2259 return num
<= 0xffffffff;
2261 } /* fits_in_unsigned_long() */
2264 fits_in_disp8 (offsetT num
)
2266 int shift
= i
.memshift
;
2272 mask
= (1 << shift
) - 1;
2274 /* Return 0 if NUM isn't properly aligned. */
2278 /* Check if NUM will fit in 8bit after shift. */
2279 return fits_in_signed_byte (num
>> shift
);
2283 fits_in_imm4 (offsetT num
)
2285 return (num
& 0xf) == num
;
2288 static i386_operand_type
2289 smallest_imm_type (offsetT num
)
2291 i386_operand_type t
;
2293 operand_type_set (&t
, 0);
2294 t
.bitfield
.imm64
= 1;
2296 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2298 /* This code is disabled on the 486 because all the Imm1 forms
2299 in the opcode table are slower on the i486. They're the
2300 versions with the implicitly specified single-position
2301 displacement, which has another syntax if you really want to
2303 t
.bitfield
.imm1
= 1;
2304 t
.bitfield
.imm8
= 1;
2305 t
.bitfield
.imm8s
= 1;
2306 t
.bitfield
.imm16
= 1;
2307 t
.bitfield
.imm32
= 1;
2308 t
.bitfield
.imm32s
= 1;
2310 else if (fits_in_signed_byte (num
))
2312 t
.bitfield
.imm8
= 1;
2313 t
.bitfield
.imm8s
= 1;
2314 t
.bitfield
.imm16
= 1;
2315 t
.bitfield
.imm32
= 1;
2316 t
.bitfield
.imm32s
= 1;
2318 else if (fits_in_unsigned_byte (num
))
2320 t
.bitfield
.imm8
= 1;
2321 t
.bitfield
.imm16
= 1;
2322 t
.bitfield
.imm32
= 1;
2323 t
.bitfield
.imm32s
= 1;
2325 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2327 t
.bitfield
.imm16
= 1;
2328 t
.bitfield
.imm32
= 1;
2329 t
.bitfield
.imm32s
= 1;
2331 else if (fits_in_signed_long (num
))
2333 t
.bitfield
.imm32
= 1;
2334 t
.bitfield
.imm32s
= 1;
2336 else if (fits_in_unsigned_long (num
))
2337 t
.bitfield
.imm32
= 1;
2343 offset_in_range (offsetT val
, int size
)
2349 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2350 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2351 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2353 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2359 /* If BFD64, sign extend val for 32bit address mode. */
2360 if (flag_code
!= CODE_64BIT
2361 || i
.prefix
[ADDR_PREFIX
])
2362 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2363 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2366 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2368 char buf1
[40], buf2
[40];
2370 sprint_value (buf1
, val
);
2371 sprint_value (buf2
, val
& mask
);
2372 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2387 a. PREFIX_EXIST if attempting to add a prefix where one from the
2388 same class already exists.
2389 b. PREFIX_LOCK if lock prefix is added.
2390 c. PREFIX_REP if rep/repne prefix is added.
2391 d. PREFIX_DS if ds prefix is added.
2392 e. PREFIX_OTHER if other prefix is added.
2395 static enum PREFIX_GROUP
2396 add_prefix (unsigned int prefix
)
2398 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2401 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2402 && flag_code
== CODE_64BIT
)
2404 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2405 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2406 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2407 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2418 case DS_PREFIX_OPCODE
:
2421 case CS_PREFIX_OPCODE
:
2422 case ES_PREFIX_OPCODE
:
2423 case FS_PREFIX_OPCODE
:
2424 case GS_PREFIX_OPCODE
:
2425 case SS_PREFIX_OPCODE
:
2429 case REPNE_PREFIX_OPCODE
:
2430 case REPE_PREFIX_OPCODE
:
2435 case LOCK_PREFIX_OPCODE
:
2444 case ADDR_PREFIX_OPCODE
:
2448 case DATA_PREFIX_OPCODE
:
2452 if (i
.prefix
[q
] != 0)
2460 i
.prefix
[q
] |= prefix
;
2463 as_bad (_("same type of prefix used twice"));
2469 update_code_flag (int value
, int check
)
2471 PRINTF_LIKE ((*as_error
));
2473 flag_code
= (enum flag_code
) value
;
2474 if (flag_code
== CODE_64BIT
)
2476 cpu_arch_flags
.bitfield
.cpu64
= 1;
2477 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2481 cpu_arch_flags
.bitfield
.cpu64
= 0;
2482 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2484 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2487 as_error
= as_fatal
;
2490 (*as_error
) (_("64bit mode not supported on `%s'."),
2491 cpu_arch_name
? cpu_arch_name
: default_arch
);
2493 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2496 as_error
= as_fatal
;
2499 (*as_error
) (_("32bit mode not supported on `%s'."),
2500 cpu_arch_name
? cpu_arch_name
: default_arch
);
2502 stackop_size
= '\0';
2506 set_code_flag (int value
)
2508 update_code_flag (value
, 0);
2512 set_16bit_gcc_code_flag (int new_code_flag
)
2514 flag_code
= (enum flag_code
) new_code_flag
;
2515 if (flag_code
!= CODE_16BIT
)
2517 cpu_arch_flags
.bitfield
.cpu64
= 0;
2518 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2519 stackop_size
= LONG_MNEM_SUFFIX
;
2523 set_intel_syntax (int syntax_flag
)
2525 /* Find out if register prefixing is specified. */
2526 int ask_naked_reg
= 0;
2529 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2532 int e
= get_symbol_name (&string
);
2534 if (strcmp (string
, "prefix") == 0)
2536 else if (strcmp (string
, "noprefix") == 0)
2539 as_bad (_("bad argument to syntax directive."));
2540 (void) restore_line_pointer (e
);
2542 demand_empty_rest_of_line ();
2544 intel_syntax
= syntax_flag
;
2546 if (ask_naked_reg
== 0)
2547 allow_naked_reg
= (intel_syntax
2548 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2550 allow_naked_reg
= (ask_naked_reg
< 0);
2552 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2554 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2555 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2556 register_prefix
= allow_naked_reg
? "" : "%";
2560 set_intel_mnemonic (int mnemonic_flag
)
2562 intel_mnemonic
= mnemonic_flag
;
2566 set_allow_index_reg (int flag
)
2568 allow_index_reg
= flag
;
2572 set_check (int what
)
2574 enum check_kind
*kind
;
2579 kind
= &operand_check
;
2590 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2593 int e
= get_symbol_name (&string
);
2595 if (strcmp (string
, "none") == 0)
2597 else if (strcmp (string
, "warning") == 0)
2598 *kind
= check_warning
;
2599 else if (strcmp (string
, "error") == 0)
2600 *kind
= check_error
;
2602 as_bad (_("bad argument to %s_check directive."), str
);
2603 (void) restore_line_pointer (e
);
2606 as_bad (_("missing argument for %s_check directive"), str
);
2608 demand_empty_rest_of_line ();
2612 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2613 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2615 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2616 static const char *arch
;
2618 /* Intel LIOM is only supported on ELF. */
2624 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2625 use default_arch. */
2626 arch
= cpu_arch_name
;
2628 arch
= default_arch
;
2631 /* If we are targeting Intel MCU, we must enable it. */
2632 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2633 || new_flag
.bitfield
.cpuiamcu
)
2636 /* If we are targeting Intel L1OM, we must enable it. */
2637 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2638 || new_flag
.bitfield
.cpul1om
)
2641 /* If we are targeting Intel K1OM, we must enable it. */
2642 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2643 || new_flag
.bitfield
.cpuk1om
)
2646 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2651 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2655 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2658 int e
= get_symbol_name (&string
);
2660 i386_cpu_flags flags
;
2662 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2664 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2666 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2670 cpu_arch_name
= cpu_arch
[j
].name
;
2671 cpu_sub_arch_name
= NULL
;
2672 cpu_arch_flags
= cpu_arch
[j
].flags
;
2673 if (flag_code
== CODE_64BIT
)
2675 cpu_arch_flags
.bitfield
.cpu64
= 1;
2676 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2680 cpu_arch_flags
.bitfield
.cpu64
= 0;
2681 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2683 cpu_arch_isa
= cpu_arch
[j
].type
;
2684 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2685 if (!cpu_arch_tune_set
)
2687 cpu_arch_tune
= cpu_arch_isa
;
2688 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2693 flags
= cpu_flags_or (cpu_arch_flags
,
2696 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2698 if (cpu_sub_arch_name
)
2700 char *name
= cpu_sub_arch_name
;
2701 cpu_sub_arch_name
= concat (name
,
2703 (const char *) NULL
);
2707 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2708 cpu_arch_flags
= flags
;
2709 cpu_arch_isa_flags
= flags
;
2713 = cpu_flags_or (cpu_arch_isa_flags
,
2715 (void) restore_line_pointer (e
);
2716 demand_empty_rest_of_line ();
2721 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2723 /* Disable an ISA extension. */
2724 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2725 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2727 flags
= cpu_flags_and_not (cpu_arch_flags
,
2728 cpu_noarch
[j
].flags
);
2729 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2731 if (cpu_sub_arch_name
)
2733 char *name
= cpu_sub_arch_name
;
2734 cpu_sub_arch_name
= concat (name
, string
,
2735 (const char *) NULL
);
2739 cpu_sub_arch_name
= xstrdup (string
);
2740 cpu_arch_flags
= flags
;
2741 cpu_arch_isa_flags
= flags
;
2743 (void) restore_line_pointer (e
);
2744 demand_empty_rest_of_line ();
2748 j
= ARRAY_SIZE (cpu_arch
);
2751 if (j
>= ARRAY_SIZE (cpu_arch
))
2752 as_bad (_("no such architecture: `%s'"), string
);
2754 *input_line_pointer
= e
;
2757 as_bad (_("missing cpu architecture"));
2759 no_cond_jump_promotion
= 0;
2760 if (*input_line_pointer
== ','
2761 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2766 ++input_line_pointer
;
2767 e
= get_symbol_name (&string
);
2769 if (strcmp (string
, "nojumps") == 0)
2770 no_cond_jump_promotion
= 1;
2771 else if (strcmp (string
, "jumps") == 0)
2774 as_bad (_("no such architecture modifier: `%s'"), string
);
2776 (void) restore_line_pointer (e
);
2779 demand_empty_rest_of_line ();
2782 enum bfd_architecture
2785 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2787 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2788 || flag_code
!= CODE_64BIT
)
2789 as_fatal (_("Intel L1OM is 64bit ELF only"));
2790 return bfd_arch_l1om
;
2792 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2794 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2795 || flag_code
!= CODE_64BIT
)
2796 as_fatal (_("Intel K1OM is 64bit ELF only"));
2797 return bfd_arch_k1om
;
2799 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2801 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2802 || flag_code
== CODE_64BIT
)
2803 as_fatal (_("Intel MCU is 32bit ELF only"));
2804 return bfd_arch_iamcu
;
2807 return bfd_arch_i386
;
2813 if (!strncmp (default_arch
, "x86_64", 6))
2815 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2817 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2818 || default_arch
[6] != '\0')
2819 as_fatal (_("Intel L1OM is 64bit ELF only"));
2820 return bfd_mach_l1om
;
2822 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2824 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2825 || default_arch
[6] != '\0')
2826 as_fatal (_("Intel K1OM is 64bit ELF only"));
2827 return bfd_mach_k1om
;
2829 else if (default_arch
[6] == '\0')
2830 return bfd_mach_x86_64
;
2832 return bfd_mach_x64_32
;
2834 else if (!strcmp (default_arch
, "i386")
2835 || !strcmp (default_arch
, "iamcu"))
2837 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2839 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2840 as_fatal (_("Intel MCU is 32bit ELF only"));
2841 return bfd_mach_i386_iamcu
;
2844 return bfd_mach_i386_i386
;
2847 as_fatal (_("unknown architecture"));
2853 const char *hash_err
;
2855 /* Support pseudo prefixes like {disp32}. */
2856 lex_type
['{'] = LEX_BEGIN_NAME
;
2858 /* Initialize op_hash hash table. */
2859 op_hash
= hash_new ();
2862 const insn_template
*optab
;
2863 templates
*core_optab
;
2865 /* Setup for loop. */
2867 core_optab
= XNEW (templates
);
2868 core_optab
->start
= optab
;
2873 if (optab
->name
== NULL
2874 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2876 /* different name --> ship out current template list;
2877 add to hash table; & begin anew. */
2878 core_optab
->end
= optab
;
2879 hash_err
= hash_insert (op_hash
,
2881 (void *) core_optab
);
2884 as_fatal (_("can't hash %s: %s"),
2888 if (optab
->name
== NULL
)
2890 core_optab
= XNEW (templates
);
2891 core_optab
->start
= optab
;
2896 /* Initialize reg_hash hash table. */
2897 reg_hash
= hash_new ();
2899 const reg_entry
*regtab
;
2900 unsigned int regtab_size
= i386_regtab_size
;
2902 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2904 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2906 as_fatal (_("can't hash %s: %s"),
2912 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2917 for (c
= 0; c
< 256; c
++)
2922 mnemonic_chars
[c
] = c
;
2923 register_chars
[c
] = c
;
2924 operand_chars
[c
] = c
;
2926 else if (ISLOWER (c
))
2928 mnemonic_chars
[c
] = c
;
2929 register_chars
[c
] = c
;
2930 operand_chars
[c
] = c
;
2932 else if (ISUPPER (c
))
2934 mnemonic_chars
[c
] = TOLOWER (c
);
2935 register_chars
[c
] = mnemonic_chars
[c
];
2936 operand_chars
[c
] = c
;
2938 else if (c
== '{' || c
== '}')
2940 mnemonic_chars
[c
] = c
;
2941 operand_chars
[c
] = c
;
2944 if (ISALPHA (c
) || ISDIGIT (c
))
2945 identifier_chars
[c
] = c
;
2948 identifier_chars
[c
] = c
;
2949 operand_chars
[c
] = c
;
2954 identifier_chars
['@'] = '@';
2957 identifier_chars
['?'] = '?';
2958 operand_chars
['?'] = '?';
2960 digit_chars
['-'] = '-';
2961 mnemonic_chars
['_'] = '_';
2962 mnemonic_chars
['-'] = '-';
2963 mnemonic_chars
['.'] = '.';
2964 identifier_chars
['_'] = '_';
2965 identifier_chars
['.'] = '.';
2967 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2968 operand_chars
[(unsigned char) *p
] = *p
;
2971 if (flag_code
== CODE_64BIT
)
2973 #if defined (OBJ_COFF) && defined (TE_PE)
2974 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2977 x86_dwarf2_return_column
= 16;
2979 x86_cie_data_alignment
= -8;
2983 x86_dwarf2_return_column
= 8;
2984 x86_cie_data_alignment
= -4;
2989 i386_print_statistics (FILE *file
)
2991 hash_print_statistics (file
, "i386 opcode", op_hash
);
2992 hash_print_statistics (file
, "i386 register", reg_hash
);
2997 /* Debugging routines for md_assemble. */
2998 static void pte (insn_template
*);
2999 static void pt (i386_operand_type
);
3000 static void pe (expressionS
*);
3001 static void ps (symbolS
*);
3004 pi (char *line
, i386_insn
*x
)
3008 fprintf (stdout
, "%s: template ", line
);
3010 fprintf (stdout
, " address: base %s index %s scale %x\n",
3011 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3012 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3013 x
->log2_scale_factor
);
3014 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3015 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3016 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3017 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3018 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3019 (x
->rex
& REX_W
) != 0,
3020 (x
->rex
& REX_R
) != 0,
3021 (x
->rex
& REX_X
) != 0,
3022 (x
->rex
& REX_B
) != 0);
3023 for (j
= 0; j
< x
->operands
; j
++)
3025 fprintf (stdout
, " #%d: ", j
+ 1);
3027 fprintf (stdout
, "\n");
3028 if (x
->types
[j
].bitfield
.reg
3029 || x
->types
[j
].bitfield
.regmmx
3030 || x
->types
[j
].bitfield
.regsimd
3031 || x
->types
[j
].bitfield
.sreg2
3032 || x
->types
[j
].bitfield
.sreg3
3033 || x
->types
[j
].bitfield
.control
3034 || x
->types
[j
].bitfield
.debug
3035 || x
->types
[j
].bitfield
.test
)
3036 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3037 if (operand_type_check (x
->types
[j
], imm
))
3039 if (operand_type_check (x
->types
[j
], disp
))
3040 pe (x
->op
[j
].disps
);
3045 pte (insn_template
*t
)
3048 fprintf (stdout
, " %d operands ", t
->operands
);
3049 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3050 if (t
->extension_opcode
!= None
)
3051 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3052 if (t
->opcode_modifier
.d
)
3053 fprintf (stdout
, "D");
3054 if (t
->opcode_modifier
.w
)
3055 fprintf (stdout
, "W");
3056 fprintf (stdout
, "\n");
3057 for (j
= 0; j
< t
->operands
; j
++)
3059 fprintf (stdout
, " #%d type ", j
+ 1);
3060 pt (t
->operand_types
[j
]);
3061 fprintf (stdout
, "\n");
3068 fprintf (stdout
, " operation %d\n", e
->X_op
);
3069 fprintf (stdout
, " add_number %ld (%lx)\n",
3070 (long) e
->X_add_number
, (long) e
->X_add_number
);
3071 if (e
->X_add_symbol
)
3073 fprintf (stdout
, " add_symbol ");
3074 ps (e
->X_add_symbol
);
3075 fprintf (stdout
, "\n");
3079 fprintf (stdout
, " op_symbol ");
3080 ps (e
->X_op_symbol
);
3081 fprintf (stdout
, "\n");
3088 fprintf (stdout
, "%s type %s%s",
3090 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3091 segment_name (S_GET_SEGMENT (s
)));
3094 static struct type_name
3096 i386_operand_type mask
;
3099 const type_names
[] =
3101 { OPERAND_TYPE_REG8
, "r8" },
3102 { OPERAND_TYPE_REG16
, "r16" },
3103 { OPERAND_TYPE_REG32
, "r32" },
3104 { OPERAND_TYPE_REG64
, "r64" },
3105 { OPERAND_TYPE_IMM8
, "i8" },
3106 { OPERAND_TYPE_IMM8
, "i8s" },
3107 { OPERAND_TYPE_IMM16
, "i16" },
3108 { OPERAND_TYPE_IMM32
, "i32" },
3109 { OPERAND_TYPE_IMM32S
, "i32s" },
3110 { OPERAND_TYPE_IMM64
, "i64" },
3111 { OPERAND_TYPE_IMM1
, "i1" },
3112 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3113 { OPERAND_TYPE_DISP8
, "d8" },
3114 { OPERAND_TYPE_DISP16
, "d16" },
3115 { OPERAND_TYPE_DISP32
, "d32" },
3116 { OPERAND_TYPE_DISP32S
, "d32s" },
3117 { OPERAND_TYPE_DISP64
, "d64" },
3118 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3119 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3120 { OPERAND_TYPE_CONTROL
, "control reg" },
3121 { OPERAND_TYPE_TEST
, "test reg" },
3122 { OPERAND_TYPE_DEBUG
, "debug reg" },
3123 { OPERAND_TYPE_FLOATREG
, "FReg" },
3124 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3125 { OPERAND_TYPE_SREG2
, "SReg2" },
3126 { OPERAND_TYPE_SREG3
, "SReg3" },
3127 { OPERAND_TYPE_ACC
, "Acc" },
3128 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3129 { OPERAND_TYPE_REGMMX
, "rMMX" },
3130 { OPERAND_TYPE_REGXMM
, "rXMM" },
3131 { OPERAND_TYPE_REGYMM
, "rYMM" },
3132 { OPERAND_TYPE_REGZMM
, "rZMM" },
3133 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3134 { OPERAND_TYPE_ESSEG
, "es" },
3138 pt (i386_operand_type t
)
3141 i386_operand_type a
;
3143 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3145 a
= operand_type_and (t
, type_names
[j
].mask
);
3146 if (!operand_type_all_zero (&a
))
3147 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3152 #endif /* DEBUG386 */
3154 static bfd_reloc_code_real_type
3155 reloc (unsigned int size
,
3158 bfd_reloc_code_real_type other
)
3160 if (other
!= NO_RELOC
)
3162 reloc_howto_type
*rel
;
3167 case BFD_RELOC_X86_64_GOT32
:
3168 return BFD_RELOC_X86_64_GOT64
;
3170 case BFD_RELOC_X86_64_GOTPLT64
:
3171 return BFD_RELOC_X86_64_GOTPLT64
;
3173 case BFD_RELOC_X86_64_PLTOFF64
:
3174 return BFD_RELOC_X86_64_PLTOFF64
;
3176 case BFD_RELOC_X86_64_GOTPC32
:
3177 other
= BFD_RELOC_X86_64_GOTPC64
;
3179 case BFD_RELOC_X86_64_GOTPCREL
:
3180 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3182 case BFD_RELOC_X86_64_TPOFF32
:
3183 other
= BFD_RELOC_X86_64_TPOFF64
;
3185 case BFD_RELOC_X86_64_DTPOFF32
:
3186 other
= BFD_RELOC_X86_64_DTPOFF64
;
3192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3193 if (other
== BFD_RELOC_SIZE32
)
3196 other
= BFD_RELOC_SIZE64
;
3199 as_bad (_("there are no pc-relative size relocations"));
3205 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3206 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3209 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3211 as_bad (_("unknown relocation (%u)"), other
);
3212 else if (size
!= bfd_get_reloc_size (rel
))
3213 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3214 bfd_get_reloc_size (rel
),
3216 else if (pcrel
&& !rel
->pc_relative
)
3217 as_bad (_("non-pc-relative relocation for pc-relative field"));
3218 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3220 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3222 as_bad (_("relocated field and relocation type differ in signedness"));
3231 as_bad (_("there are no unsigned pc-relative relocations"));
3234 case 1: return BFD_RELOC_8_PCREL
;
3235 case 2: return BFD_RELOC_16_PCREL
;
3236 case 4: return BFD_RELOC_32_PCREL
;
3237 case 8: return BFD_RELOC_64_PCREL
;
3239 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3246 case 4: return BFD_RELOC_X86_64_32S
;
3251 case 1: return BFD_RELOC_8
;
3252 case 2: return BFD_RELOC_16
;
3253 case 4: return BFD_RELOC_32
;
3254 case 8: return BFD_RELOC_64
;
3256 as_bad (_("cannot do %s %u byte relocation"),
3257 sign
> 0 ? "signed" : "unsigned", size
);
3263 /* Here we decide which fixups can be adjusted to make them relative to
3264 the beginning of the section instead of the symbol. Basically we need
3265 to make sure that the dynamic relocations are done correctly, so in
3266 some cases we force the original symbol to be used. */
3269 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3271 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3275 /* Don't adjust pc-relative references to merge sections in 64-bit
3277 if (use_rela_relocations
3278 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3282 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3283 and changed later by validate_fix. */
3284 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3285 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3288 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3289 for size relocations. */
3290 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3291 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3292 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3293 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3294 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3295 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3296 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3297 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3298 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3299 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3300 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3301 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3302 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3303 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3304 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3305 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3306 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3307 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3308 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3309 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3310 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3311 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3312 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3313 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3314 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3315 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3316 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3317 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3318 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3319 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3320 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3321 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3322 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3329 intel_float_operand (const char *mnemonic
)
3331 /* Note that the value returned is meaningful only for opcodes with (memory)
3332 operands, hence the code here is free to improperly handle opcodes that
3333 have no operands (for better performance and smaller code). */
3335 if (mnemonic
[0] != 'f')
3336 return 0; /* non-math */
3338 switch (mnemonic
[1])
3340 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3341 the fs segment override prefix not currently handled because no
3342 call path can make opcodes without operands get here */
3344 return 2 /* integer op */;
3346 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3347 return 3; /* fldcw/fldenv */
3350 if (mnemonic
[2] != 'o' /* fnop */)
3351 return 3; /* non-waiting control op */
3354 if (mnemonic
[2] == 's')
3355 return 3; /* frstor/frstpm */
3358 if (mnemonic
[2] == 'a')
3359 return 3; /* fsave */
3360 if (mnemonic
[2] == 't')
3362 switch (mnemonic
[3])
3364 case 'c': /* fstcw */
3365 case 'd': /* fstdw */
3366 case 'e': /* fstenv */
3367 case 's': /* fsts[gw] */
3373 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3374 return 0; /* fxsave/fxrstor are not really math ops */
3381 /* Build the VEX prefix. */
3384 build_vex_prefix (const insn_template
*t
)
3386 unsigned int register_specifier
;
3387 unsigned int implied_prefix
;
3388 unsigned int vector_length
;
3391 /* Check register specifier. */
3392 if (i
.vex
.register_specifier
)
3394 register_specifier
=
3395 ~register_number (i
.vex
.register_specifier
) & 0xf;
3396 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3399 register_specifier
= 0xf;
3401 /* Use 2-byte VEX prefix by swapping destination and source operand
3402 if there are more than 1 register operand. */
3403 if (i
.reg_operands
> 1
3404 && i
.vec_encoding
!= vex_encoding_vex3
3405 && i
.dir_encoding
== dir_encoding_default
3406 && i
.operands
== i
.reg_operands
3407 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3408 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3409 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3412 unsigned int xchg
= i
.operands
- 1;
3413 union i386_op temp_op
;
3414 i386_operand_type temp_type
;
3416 temp_type
= i
.types
[xchg
];
3417 i
.types
[xchg
] = i
.types
[0];
3418 i
.types
[0] = temp_type
;
3419 temp_op
= i
.op
[xchg
];
3420 i
.op
[xchg
] = i
.op
[0];
3423 gas_assert (i
.rm
.mode
== 3);
3427 i
.rm
.regmem
= i
.rm
.reg
;
3430 if (i
.tm
.opcode_modifier
.d
)
3431 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3432 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3433 else /* Use the next insn. */
3437 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3438 vector_length
= avxscalar
;
3439 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3445 /* Determine vector length from the last multi-length vector
3448 for (op
= t
->operands
; op
--;)
3449 if (t
->operand_types
[op
].bitfield
.xmmword
3450 && t
->operand_types
[op
].bitfield
.ymmword
3451 && i
.types
[op
].bitfield
.ymmword
)
3458 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3463 case DATA_PREFIX_OPCODE
:
3466 case REPE_PREFIX_OPCODE
:
3469 case REPNE_PREFIX_OPCODE
:
3476 /* Check the REX.W bit and VEXW. */
3477 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3478 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3479 else if (i
.tm
.opcode_modifier
.vexw
)
3480 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3482 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3484 /* Use 2-byte VEX prefix if possible. */
3486 && i
.vec_encoding
!= vex_encoding_vex3
3487 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3488 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3490 /* 2-byte VEX prefix. */
3494 i
.vex
.bytes
[0] = 0xc5;
3496 /* Check the REX.R bit. */
3497 r
= (i
.rex
& REX_R
) ? 0 : 1;
3498 i
.vex
.bytes
[1] = (r
<< 7
3499 | register_specifier
<< 3
3500 | vector_length
<< 2
3505 /* 3-byte VEX prefix. */
3510 switch (i
.tm
.opcode_modifier
.vexopcode
)
3514 i
.vex
.bytes
[0] = 0xc4;
3518 i
.vex
.bytes
[0] = 0xc4;
3522 i
.vex
.bytes
[0] = 0xc4;
3526 i
.vex
.bytes
[0] = 0x8f;
3530 i
.vex
.bytes
[0] = 0x8f;
3534 i
.vex
.bytes
[0] = 0x8f;
3540 /* The high 3 bits of the second VEX byte are 1's compliment
3541 of RXB bits from REX. */
3542 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3544 i
.vex
.bytes
[2] = (w
<< 7
3545 | register_specifier
<< 3
3546 | vector_length
<< 2
3551 static INLINE bfd_boolean
3552 is_evex_encoding (const insn_template
*t
)
3554 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3555 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3556 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3559 static INLINE bfd_boolean
3560 is_any_vex_encoding (const insn_template
*t
)
3562 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3563 || is_evex_encoding (t
);
3566 /* Build the EVEX prefix. */
3569 build_evex_prefix (void)
3571 unsigned int register_specifier
;
3572 unsigned int implied_prefix
;
3574 rex_byte vrex_used
= 0;
3576 /* Check register specifier. */
3577 if (i
.vex
.register_specifier
)
3579 gas_assert ((i
.vrex
& REX_X
) == 0);
3581 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3582 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3583 register_specifier
+= 8;
3584 /* The upper 16 registers are encoded in the fourth byte of the
3586 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3587 i
.vex
.bytes
[3] = 0x8;
3588 register_specifier
= ~register_specifier
& 0xf;
3592 register_specifier
= 0xf;
3594 /* Encode upper 16 vector index register in the fourth byte of
3596 if (!(i
.vrex
& REX_X
))
3597 i
.vex
.bytes
[3] = 0x8;
3602 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3607 case DATA_PREFIX_OPCODE
:
3610 case REPE_PREFIX_OPCODE
:
3613 case REPNE_PREFIX_OPCODE
:
3620 /* 4 byte EVEX prefix. */
3622 i
.vex
.bytes
[0] = 0x62;
3625 switch (i
.tm
.opcode_modifier
.vexopcode
)
3641 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3643 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3645 /* The fifth bit of the second EVEX byte is 1's compliment of the
3646 REX_R bit in VREX. */
3647 if (!(i
.vrex
& REX_R
))
3648 i
.vex
.bytes
[1] |= 0x10;
3652 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3654 /* When all operands are registers, the REX_X bit in REX is not
3655 used. We reuse it to encode the upper 16 registers, which is
3656 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3657 as 1's compliment. */
3658 if ((i
.vrex
& REX_B
))
3661 i
.vex
.bytes
[1] &= ~0x40;
3665 /* EVEX instructions shouldn't need the REX prefix. */
3666 i
.vrex
&= ~vrex_used
;
3667 gas_assert (i
.vrex
== 0);
3669 /* Check the REX.W bit and VEXW. */
3670 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3671 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3672 else if (i
.tm
.opcode_modifier
.vexw
)
3673 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3675 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3677 /* Encode the U bit. */
3678 implied_prefix
|= 0x4;
3680 /* The third byte of the EVEX prefix. */
3681 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3683 /* The fourth byte of the EVEX prefix. */
3684 /* The zeroing-masking bit. */
3685 if (i
.mask
&& i
.mask
->zeroing
)
3686 i
.vex
.bytes
[3] |= 0x80;
3688 /* Don't always set the broadcast bit if there is no RC. */
3691 /* Encode the vector length. */
3692 unsigned int vec_length
;
3694 if (!i
.tm
.opcode_modifier
.evex
3695 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3699 /* Determine vector length from the last multi-length vector
3702 for (op
= i
.operands
; op
--;)
3703 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3704 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3705 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3707 if (i
.types
[op
].bitfield
.zmmword
)
3709 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3712 else if (i
.types
[op
].bitfield
.ymmword
)
3714 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3717 else if (i
.types
[op
].bitfield
.xmmword
)
3719 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3722 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3724 switch (i
.broadcast
->bytes
)
3727 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3730 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3733 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3742 if (op
>= MAX_OPERANDS
)
3746 switch (i
.tm
.opcode_modifier
.evex
)
3748 case EVEXLIG
: /* LL' is ignored */
3749 vec_length
= evexlig
<< 5;
3752 vec_length
= 0 << 5;
3755 vec_length
= 1 << 5;
3758 vec_length
= 2 << 5;
3764 i
.vex
.bytes
[3] |= vec_length
;
3765 /* Encode the broadcast bit. */
3767 i
.vex
.bytes
[3] |= 0x10;
3771 if (i
.rounding
->type
!= saeonly
)
3772 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3774 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3777 if (i
.mask
&& i
.mask
->mask
)
3778 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3782 process_immext (void)
3786 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3789 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3790 with an opcode suffix which is coded in the same place as an
3791 8-bit immediate field would be.
3792 Here we check those operands and remove them afterwards. */
3795 for (x
= 0; x
< i
.operands
; x
++)
3796 if (register_number (i
.op
[x
].regs
) != x
)
3797 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3798 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3804 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3806 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3807 suffix which is coded in the same place as an 8-bit immediate
3809 Here we check those operands and remove them afterwards. */
3812 if (i
.operands
!= 3)
3815 for (x
= 0; x
< 2; x
++)
3816 if (register_number (i
.op
[x
].regs
) != x
)
3817 goto bad_register_operand
;
3819 /* Check for third operand for mwaitx/monitorx insn. */
3820 if (register_number (i
.op
[x
].regs
)
3821 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3823 bad_register_operand
:
3824 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3825 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3832 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3833 which is coded in the same place as an 8-bit immediate field
3834 would be. Here we fake an 8-bit immediate operand from the
3835 opcode suffix stored in tm.extension_opcode.
3837 AVX instructions also use this encoding, for some of
3838 3 argument instructions. */
3840 gas_assert (i
.imm_operands
<= 1
3842 || (is_any_vex_encoding (&i
.tm
)
3843 && i
.operands
<= 4)));
3845 exp
= &im_expressions
[i
.imm_operands
++];
3846 i
.op
[i
.operands
].imms
= exp
;
3847 i
.types
[i
.operands
] = imm8
;
3849 exp
->X_op
= O_constant
;
3850 exp
->X_add_number
= i
.tm
.extension_opcode
;
3851 i
.tm
.extension_opcode
= None
;
3858 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3863 as_bad (_("invalid instruction `%s' after `%s'"),
3864 i
.tm
.name
, i
.hle_prefix
);
3867 if (i
.prefix
[LOCK_PREFIX
])
3869 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3873 case HLEPrefixRelease
:
3874 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3876 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3880 if (i
.mem_operands
== 0
3881 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3883 as_bad (_("memory destination needed for instruction `%s'"
3884 " after `xrelease'"), i
.tm
.name
);
3891 /* Try the shortest encoding by shortening operand size. */
3894 optimize_encoding (void)
3898 if (optimize_for_space
3899 && i
.reg_operands
== 1
3900 && i
.imm_operands
== 1
3901 && !i
.types
[1].bitfield
.byte
3902 && i
.op
[0].imms
->X_op
== O_constant
3903 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3904 && ((i
.tm
.base_opcode
== 0xa8
3905 && i
.tm
.extension_opcode
== None
)
3906 || (i
.tm
.base_opcode
== 0xf6
3907 && i
.tm
.extension_opcode
== 0x0)))
3910 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3912 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3913 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3915 i
.types
[1].bitfield
.byte
= 1;
3916 /* Ignore the suffix. */
3918 if (base_regnum
>= 4
3919 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3921 /* Handle SP, BP, SI and DI registers. */
3922 if (i
.types
[1].bitfield
.word
)
3924 else if (i
.types
[1].bitfield
.dword
)
3932 else if (flag_code
== CODE_64BIT
3933 && ((i
.types
[1].bitfield
.qword
3934 && i
.reg_operands
== 1
3935 && i
.imm_operands
== 1
3936 && i
.op
[0].imms
->X_op
== O_constant
3937 && ((i
.tm
.base_opcode
== 0xb0
3938 && i
.tm
.extension_opcode
== None
3939 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3940 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3941 && (((i
.tm
.base_opcode
== 0x24
3942 || i
.tm
.base_opcode
== 0xa8)
3943 && i
.tm
.extension_opcode
== None
)
3944 || (i
.tm
.base_opcode
== 0x80
3945 && i
.tm
.extension_opcode
== 0x4)
3946 || ((i
.tm
.base_opcode
== 0xf6
3947 || i
.tm
.base_opcode
== 0xc6)
3948 && i
.tm
.extension_opcode
== 0x0)))))
3949 || (i
.types
[0].bitfield
.qword
3950 && ((i
.reg_operands
== 2
3951 && i
.op
[0].regs
== i
.op
[1].regs
3952 && ((i
.tm
.base_opcode
== 0x30
3953 || i
.tm
.base_opcode
== 0x28)
3954 && i
.tm
.extension_opcode
== None
))
3955 || (i
.reg_operands
== 1
3957 && i
.tm
.base_opcode
== 0x30
3958 && i
.tm
.extension_opcode
== None
)))))
3961 andq $imm31, %r64 -> andl $imm31, %r32
3962 testq $imm31, %r64 -> testl $imm31, %r32
3963 xorq %r64, %r64 -> xorl %r32, %r32
3964 subq %r64, %r64 -> subl %r32, %r32
3965 movq $imm31, %r64 -> movl $imm31, %r32
3966 movq $imm32, %r64 -> movl $imm32, %r32
3968 i
.tm
.opcode_modifier
.norex64
= 1;
3969 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3972 movq $imm31, %r64 -> movl $imm31, %r32
3973 movq $imm32, %r64 -> movl $imm32, %r32
3975 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3976 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3977 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3978 i
.types
[0].bitfield
.imm32
= 1;
3979 i
.types
[0].bitfield
.imm32s
= 0;
3980 i
.types
[0].bitfield
.imm64
= 0;
3981 i
.types
[1].bitfield
.dword
= 1;
3982 i
.types
[1].bitfield
.qword
= 0;
3983 if (i
.tm
.base_opcode
== 0xc6)
3986 movq $imm31, %r64 -> movl $imm31, %r32
3988 i
.tm
.base_opcode
= 0xb0;
3989 i
.tm
.extension_opcode
= None
;
3990 i
.tm
.opcode_modifier
.shortform
= 1;
3991 i
.tm
.opcode_modifier
.modrm
= 0;
3995 else if (i
.reg_operands
== 3
3996 && i
.op
[0].regs
== i
.op
[1].regs
3997 && !i
.types
[2].bitfield
.xmmword
3998 && (i
.tm
.opcode_modifier
.vex
3999 || ((!i
.mask
|| i
.mask
->zeroing
)
4001 && is_evex_encoding (&i
.tm
)
4002 && (i
.vec_encoding
!= vex_encoding_evex
4003 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4004 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4005 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4006 && i
.types
[2].bitfield
.ymmword
))))
4007 && ((i
.tm
.base_opcode
== 0x55
4008 || i
.tm
.base_opcode
== 0x6655
4009 || i
.tm
.base_opcode
== 0x66df
4010 || i
.tm
.base_opcode
== 0x57
4011 || i
.tm
.base_opcode
== 0x6657
4012 || i
.tm
.base_opcode
== 0x66ef
4013 || i
.tm
.base_opcode
== 0x66f8
4014 || i
.tm
.base_opcode
== 0x66f9
4015 || i
.tm
.base_opcode
== 0x66fa
4016 || i
.tm
.base_opcode
== 0x66fb
4017 || i
.tm
.base_opcode
== 0x42
4018 || i
.tm
.base_opcode
== 0x6642
4019 || i
.tm
.base_opcode
== 0x47
4020 || i
.tm
.base_opcode
== 0x6647)
4021 && i
.tm
.extension_opcode
== None
))
4024 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4026 EVEX VOP %zmmM, %zmmM, %zmmN
4027 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4028 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4029 EVEX VOP %ymmM, %ymmM, %ymmN
4030 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4031 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4032 VEX VOP %ymmM, %ymmM, %ymmN
4033 -> VEX VOP %xmmM, %xmmM, %xmmN
4034 VOP, one of vpandn and vpxor:
4035 VEX VOP %ymmM, %ymmM, %ymmN
4036 -> VEX VOP %xmmM, %xmmM, %xmmN
4037 VOP, one of vpandnd and vpandnq:
4038 EVEX VOP %zmmM, %zmmM, %zmmN
4039 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4040 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4041 EVEX VOP %ymmM, %ymmM, %ymmN
4042 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4043 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4044 VOP, one of vpxord and vpxorq:
4045 EVEX VOP %zmmM, %zmmM, %zmmN
4046 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4047 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4048 EVEX VOP %ymmM, %ymmM, %ymmN
4049 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4050 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4051 VOP, one of kxord and kxorq:
4052 VEX VOP %kM, %kM, %kN
4053 -> VEX kxorw %kM, %kM, %kN
4054 VOP, one of kandnd and kandnq:
4055 VEX VOP %kM, %kM, %kN
4056 -> VEX kandnw %kM, %kM, %kN
4058 if (is_evex_encoding (&i
.tm
))
4060 if (i
.vec_encoding
!= vex_encoding_evex
)
4062 i
.tm
.opcode_modifier
.vex
= VEX128
;
4063 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4064 i
.tm
.opcode_modifier
.evex
= 0;
4066 else if (optimize
> 1)
4067 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4071 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4073 i
.tm
.base_opcode
&= 0xff;
4074 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4077 i
.tm
.opcode_modifier
.vex
= VEX128
;
4079 if (i
.tm
.opcode_modifier
.vex
)
4080 for (j
= 0; j
< 3; j
++)
4082 i
.types
[j
].bitfield
.xmmword
= 1;
4083 i
.types
[j
].bitfield
.ymmword
= 0;
4086 else if (i
.vec_encoding
!= vex_encoding_evex
4087 && !i
.types
[0].bitfield
.zmmword
4088 && !i
.types
[1].bitfield
.zmmword
4090 && is_evex_encoding (&i
.tm
)
4091 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4092 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4093 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4094 && i
.tm
.extension_opcode
== None
)
4097 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4098 vmovdqu32 and vmovdqu64:
4099 EVEX VOP %xmmM, %xmmN
4100 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4101 EVEX VOP %ymmM, %ymmN
4102 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4104 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4106 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4108 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4110 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4112 for (j
= 0; j
< 2; j
++)
4113 if (operand_type_check (i
.types
[j
], disp
)
4114 && i
.op
[j
].disps
->X_op
== O_constant
)
4116 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4117 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4118 bytes, we choose EVEX Disp8 over VEX Disp32. */
4119 int evex_disp8
, vex_disp8
;
4120 unsigned int memshift
= i
.memshift
;
4121 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4123 evex_disp8
= fits_in_disp8 (n
);
4125 vex_disp8
= fits_in_disp8 (n
);
4126 if (evex_disp8
!= vex_disp8
)
4128 i
.memshift
= memshift
;
4132 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4135 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4136 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4137 i
.tm
.opcode_modifier
.vex
4138 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4139 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4140 i
.tm
.opcode_modifier
.evex
= 0;
4141 i
.tm
.opcode_modifier
.masking
= 0;
4142 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4144 for (j
= 0; j
< 2; j
++)
4145 if (operand_type_check (i
.types
[j
], disp
)
4146 && i
.op
[j
].disps
->X_op
== O_constant
)
4148 i
.types
[j
].bitfield
.disp8
4149 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4155 /* This is the guts of the machine-dependent assembler. LINE points to a
4156 machine dependent instruction. This function is supposed to emit
4157 the frags/bytes it assembles to. */
4160 md_assemble (char *line
)
4163 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4164 const insn_template
*t
;
4166 /* Initialize globals. */
4167 memset (&i
, '\0', sizeof (i
));
4168 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4169 i
.reloc
[j
] = NO_RELOC
;
4170 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4171 memset (im_expressions
, '\0', sizeof (im_expressions
));
4172 save_stack_p
= save_stack
;
4174 /* First parse an instruction mnemonic & call i386_operand for the operands.
4175 We assume that the scrubber has arranged it so that line[0] is the valid
4176 start of a (possibly prefixed) mnemonic. */
4178 line
= parse_insn (line
, mnemonic
);
4181 mnem_suffix
= i
.suffix
;
4183 line
= parse_operands (line
, mnemonic
);
4185 xfree (i
.memop1_string
);
4186 i
.memop1_string
= NULL
;
4190 /* Now we've parsed the mnemonic into a set of templates, and have the
4191 operands at hand. */
4193 /* All intel opcodes have reversed operands except for "bound" and
4194 "enter". We also don't reverse intersegment "jmp" and "call"
4195 instructions with 2 immediate operands so that the immediate segment
4196 precedes the offset, as it does when in AT&T mode. */
4199 && (strcmp (mnemonic
, "bound") != 0)
4200 && (strcmp (mnemonic
, "invlpga") != 0)
4201 && !(operand_type_check (i
.types
[0], imm
)
4202 && operand_type_check (i
.types
[1], imm
)))
4205 /* The order of the immediates should be reversed
4206 for 2 immediates extrq and insertq instructions */
4207 if (i
.imm_operands
== 2
4208 && (strcmp (mnemonic
, "extrq") == 0
4209 || strcmp (mnemonic
, "insertq") == 0))
4210 swap_2_operands (0, 1);
4215 /* Don't optimize displacement for movabs since it only takes 64bit
4218 && i
.disp_encoding
!= disp_encoding_32bit
4219 && (flag_code
!= CODE_64BIT
4220 || strcmp (mnemonic
, "movabs") != 0))
4223 /* Next, we find a template that matches the given insn,
4224 making sure the overlap of the given operands types is consistent
4225 with the template operand types. */
4227 if (!(t
= match_template (mnem_suffix
)))
4230 if (sse_check
!= check_none
4231 && !i
.tm
.opcode_modifier
.noavx
4232 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4233 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4234 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4235 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4236 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4237 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4238 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4239 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4240 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4241 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4243 (sse_check
== check_warning
4245 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4248 /* Zap movzx and movsx suffix. The suffix has been set from
4249 "word ptr" or "byte ptr" on the source operand in Intel syntax
4250 or extracted from mnemonic in AT&T syntax. But we'll use
4251 the destination register to choose the suffix for encoding. */
4252 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4254 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4255 there is no suffix, the default will be byte extension. */
4256 if (i
.reg_operands
!= 2
4259 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4264 if (i
.tm
.opcode_modifier
.fwait
)
4265 if (!add_prefix (FWAIT_OPCODE
))
4268 /* Check if REP prefix is OK. */
4269 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4271 as_bad (_("invalid instruction `%s' after `%s'"),
4272 i
.tm
.name
, i
.rep_prefix
);
4276 /* Check for lock without a lockable instruction. Destination operand
4277 must be memory unless it is xchg (0x86). */
4278 if (i
.prefix
[LOCK_PREFIX
]
4279 && (!i
.tm
.opcode_modifier
.islockable
4280 || i
.mem_operands
== 0
4281 || (i
.tm
.base_opcode
!= 0x86
4282 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4284 as_bad (_("expecting lockable instruction after `lock'"));
4288 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4289 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4291 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4295 /* Check if HLE prefix is OK. */
4296 if (i
.hle_prefix
&& !check_hle ())
4299 /* Check BND prefix. */
4300 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4301 as_bad (_("expecting valid branch instruction after `bnd'"));
4303 /* Check NOTRACK prefix. */
4304 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4305 as_bad (_("expecting indirect branch instruction after `notrack'"));
4307 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4309 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4310 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4311 else if (flag_code
!= CODE_16BIT
4312 ? i
.prefix
[ADDR_PREFIX
]
4313 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4314 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4317 /* Insert BND prefix. */
4318 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4320 if (!i
.prefix
[BND_PREFIX
])
4321 add_prefix (BND_PREFIX_OPCODE
);
4322 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4324 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4325 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4329 /* Check string instruction segment overrides. */
4330 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4332 if (!check_string ())
4334 i
.disp_operands
= 0;
4337 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4338 optimize_encoding ();
4340 if (!process_suffix ())
4343 /* Update operand types. */
4344 for (j
= 0; j
< i
.operands
; j
++)
4345 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4347 /* Make still unresolved immediate matches conform to size of immediate
4348 given in i.suffix. */
4349 if (!finalize_imm ())
4352 if (i
.types
[0].bitfield
.imm1
)
4353 i
.imm_operands
= 0; /* kludge for shift insns. */
4355 /* We only need to check those implicit registers for instructions
4356 with 3 operands or less. */
4357 if (i
.operands
<= 3)
4358 for (j
= 0; j
< i
.operands
; j
++)
4359 if (i
.types
[j
].bitfield
.inoutportreg
4360 || i
.types
[j
].bitfield
.shiftcount
4361 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4364 /* ImmExt should be processed after SSE2AVX. */
4365 if (!i
.tm
.opcode_modifier
.sse2avx
4366 && i
.tm
.opcode_modifier
.immext
)
4369 /* For insns with operands there are more diddles to do to the opcode. */
4372 if (!process_operands ())
4375 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4377 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4378 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4381 if (is_any_vex_encoding (&i
.tm
))
4383 if (flag_code
== CODE_16BIT
)
4385 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4390 if (i
.tm
.opcode_modifier
.vex
)
4391 build_vex_prefix (t
);
4393 build_evex_prefix ();
4396 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4397 instructions may define INT_OPCODE as well, so avoid this corner
4398 case for those instructions that use MODRM. */
4399 if (i
.tm
.base_opcode
== INT_OPCODE
4400 && !i
.tm
.opcode_modifier
.modrm
4401 && i
.op
[0].imms
->X_add_number
== 3)
4403 i
.tm
.base_opcode
= INT3_OPCODE
;
4407 if ((i
.tm
.opcode_modifier
.jump
4408 || i
.tm
.opcode_modifier
.jumpbyte
4409 || i
.tm
.opcode_modifier
.jumpdword
)
4410 && i
.op
[0].disps
->X_op
== O_constant
)
4412 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4413 the absolute address given by the constant. Since ix86 jumps and
4414 calls are pc relative, we need to generate a reloc. */
4415 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4416 i
.op
[0].disps
->X_op
= O_symbol
;
4419 if (i
.tm
.opcode_modifier
.rex64
)
4422 /* For 8 bit registers we need an empty rex prefix. Also if the
4423 instruction already has a prefix, we need to convert old
4424 registers to new ones. */
4426 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4427 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4428 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4429 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4430 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4431 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4436 i
.rex
|= REX_OPCODE
;
4437 for (x
= 0; x
< 2; x
++)
4439 /* Look for 8 bit operand that uses old registers. */
4440 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4441 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4443 /* In case it is "hi" register, give up. */
4444 if (i
.op
[x
].regs
->reg_num
> 3)
4445 as_bad (_("can't encode register '%s%s' in an "
4446 "instruction requiring REX prefix."),
4447 register_prefix
, i
.op
[x
].regs
->reg_name
);
4449 /* Otherwise it is equivalent to the extended register.
4450 Since the encoding doesn't change this is merely
4451 cosmetic cleanup for debug output. */
4453 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4458 if (i
.rex
== 0 && i
.rex_encoding
)
4460 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4461 that uses legacy register. If it is "hi" register, don't add
4462 the REX_OPCODE byte. */
4464 for (x
= 0; x
< 2; x
++)
4465 if (i
.types
[x
].bitfield
.reg
4466 && i
.types
[x
].bitfield
.byte
4467 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4468 && i
.op
[x
].regs
->reg_num
> 3)
4470 i
.rex_encoding
= FALSE
;
4479 add_prefix (REX_OPCODE
| i
.rex
);
4481 /* We are ready to output the insn. */
4486 parse_insn (char *line
, char *mnemonic
)
4489 char *token_start
= l
;
4492 const insn_template
*t
;
4498 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4503 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4505 as_bad (_("no such instruction: `%s'"), token_start
);
4510 if (!is_space_char (*l
)
4511 && *l
!= END_OF_INSN
4513 || (*l
!= PREFIX_SEPARATOR
4516 as_bad (_("invalid character %s in mnemonic"),
4517 output_invalid (*l
));
4520 if (token_start
== l
)
4522 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4523 as_bad (_("expecting prefix; got nothing"));
4525 as_bad (_("expecting mnemonic; got nothing"));
4529 /* Look up instruction (or prefix) via hash table. */
4530 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4532 if (*l
!= END_OF_INSN
4533 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4534 && current_templates
4535 && current_templates
->start
->opcode_modifier
.isprefix
)
4537 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4539 as_bad ((flag_code
!= CODE_64BIT
4540 ? _("`%s' is only supported in 64-bit mode")
4541 : _("`%s' is not supported in 64-bit mode")),
4542 current_templates
->start
->name
);
4545 /* If we are in 16-bit mode, do not allow addr16 or data16.
4546 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4547 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4548 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4549 && flag_code
!= CODE_64BIT
4550 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4551 ^ (flag_code
== CODE_16BIT
)))
4553 as_bad (_("redundant %s prefix"),
4554 current_templates
->start
->name
);
4557 if (current_templates
->start
->opcode_length
== 0)
4559 /* Handle pseudo prefixes. */
4560 switch (current_templates
->start
->base_opcode
)
4564 i
.disp_encoding
= disp_encoding_8bit
;
4568 i
.disp_encoding
= disp_encoding_32bit
;
4572 i
.dir_encoding
= dir_encoding_load
;
4576 i
.dir_encoding
= dir_encoding_store
;
4580 i
.vec_encoding
= vex_encoding_vex2
;
4584 i
.vec_encoding
= vex_encoding_vex3
;
4588 i
.vec_encoding
= vex_encoding_evex
;
4592 i
.rex_encoding
= TRUE
;
4596 i
.no_optimize
= TRUE
;
4604 /* Add prefix, checking for repeated prefixes. */
4605 switch (add_prefix (current_templates
->start
->base_opcode
))
4610 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4611 i
.notrack_prefix
= current_templates
->start
->name
;
4614 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4615 i
.hle_prefix
= current_templates
->start
->name
;
4616 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4617 i
.bnd_prefix
= current_templates
->start
->name
;
4619 i
.rep_prefix
= current_templates
->start
->name
;
4625 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4632 if (!current_templates
)
4634 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4635 Check if we should swap operand or force 32bit displacement in
4637 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4638 i
.dir_encoding
= dir_encoding_swap
;
4639 else if (mnem_p
- 3 == dot_p
4642 i
.disp_encoding
= disp_encoding_8bit
;
4643 else if (mnem_p
- 4 == dot_p
4647 i
.disp_encoding
= disp_encoding_32bit
;
4652 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4655 if (!current_templates
)
4658 if (mnem_p
> mnemonic
)
4660 /* See if we can get a match by trimming off a suffix. */
4663 case WORD_MNEM_SUFFIX
:
4664 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4665 i
.suffix
= SHORT_MNEM_SUFFIX
;
4668 case BYTE_MNEM_SUFFIX
:
4669 case QWORD_MNEM_SUFFIX
:
4670 i
.suffix
= mnem_p
[-1];
4672 current_templates
= (const templates
*) hash_find (op_hash
,
4675 case SHORT_MNEM_SUFFIX
:
4676 case LONG_MNEM_SUFFIX
:
4679 i
.suffix
= mnem_p
[-1];
4681 current_templates
= (const templates
*) hash_find (op_hash
,
4690 if (intel_float_operand (mnemonic
) == 1)
4691 i
.suffix
= SHORT_MNEM_SUFFIX
;
4693 i
.suffix
= LONG_MNEM_SUFFIX
;
4695 current_templates
= (const templates
*) hash_find (op_hash
,
4702 if (!current_templates
)
4704 as_bad (_("no such instruction: `%s'"), token_start
);
4709 if (current_templates
->start
->opcode_modifier
.jump
4710 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4712 /* Check for a branch hint. We allow ",pt" and ",pn" for
4713 predict taken and predict not taken respectively.
4714 I'm not sure that branch hints actually do anything on loop
4715 and jcxz insns (JumpByte) for current Pentium4 chips. They
4716 may work in the future and it doesn't hurt to accept them
4718 if (l
[0] == ',' && l
[1] == 'p')
4722 if (!add_prefix (DS_PREFIX_OPCODE
))
4726 else if (l
[2] == 'n')
4728 if (!add_prefix (CS_PREFIX_OPCODE
))
4734 /* Any other comma loses. */
4737 as_bad (_("invalid character %s in mnemonic"),
4738 output_invalid (*l
));
4742 /* Check if instruction is supported on specified architecture. */
4744 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4746 supported
|= cpu_flags_match (t
);
4747 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4749 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4750 as_warn (_("use .code16 to ensure correct addressing mode"));
4756 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4757 as_bad (flag_code
== CODE_64BIT
4758 ? _("`%s' is not supported in 64-bit mode")
4759 : _("`%s' is only supported in 64-bit mode"),
4760 current_templates
->start
->name
);
4762 as_bad (_("`%s' is not supported on `%s%s'"),
4763 current_templates
->start
->name
,
4764 cpu_arch_name
? cpu_arch_name
: default_arch
,
4765 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4771 parse_operands (char *l
, const char *mnemonic
)
4775 /* 1 if operand is pending after ','. */
4776 unsigned int expecting_operand
= 0;
4778 /* Non-zero if operand parens not balanced. */
4779 unsigned int paren_not_balanced
;
4781 while (*l
!= END_OF_INSN
)
4783 /* Skip optional white space before operand. */
4784 if (is_space_char (*l
))
4786 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4788 as_bad (_("invalid character %s before operand %d"),
4789 output_invalid (*l
),
4793 token_start
= l
; /* After white space. */
4794 paren_not_balanced
= 0;
4795 while (paren_not_balanced
|| *l
!= ',')
4797 if (*l
== END_OF_INSN
)
4799 if (paren_not_balanced
)
4802 as_bad (_("unbalanced parenthesis in operand %d."),
4805 as_bad (_("unbalanced brackets in operand %d."),
4810 break; /* we are done */
4812 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4814 as_bad (_("invalid character %s in operand %d"),
4815 output_invalid (*l
),
4822 ++paren_not_balanced
;
4824 --paren_not_balanced
;
4829 ++paren_not_balanced
;
4831 --paren_not_balanced
;
4835 if (l
!= token_start
)
4836 { /* Yes, we've read in another operand. */
4837 unsigned int operand_ok
;
4838 this_operand
= i
.operands
++;
4839 if (i
.operands
> MAX_OPERANDS
)
4841 as_bad (_("spurious operands; (%d operands/instruction max)"),
4845 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4846 /* Now parse operand adding info to 'i' as we go along. */
4847 END_STRING_AND_SAVE (l
);
4849 if (i
.mem_operands
> 1)
4851 as_bad (_("too many memory references for `%s'"),
4858 i386_intel_operand (token_start
,
4859 intel_float_operand (mnemonic
));
4861 operand_ok
= i386_att_operand (token_start
);
4863 RESTORE_END_STRING (l
);
4869 if (expecting_operand
)
4871 expecting_operand_after_comma
:
4872 as_bad (_("expecting operand after ','; got nothing"));
4877 as_bad (_("expecting operand before ','; got nothing"));
4882 /* Now *l must be either ',' or END_OF_INSN. */
4885 if (*++l
== END_OF_INSN
)
4887 /* Just skip it, if it's \n complain. */
4888 goto expecting_operand_after_comma
;
4890 expecting_operand
= 1;
4897 swap_2_operands (int xchg1
, int xchg2
)
4899 union i386_op temp_op
;
4900 i386_operand_type temp_type
;
4901 unsigned int temp_flags
;
4902 enum bfd_reloc_code_real temp_reloc
;
4904 temp_type
= i
.types
[xchg2
];
4905 i
.types
[xchg2
] = i
.types
[xchg1
];
4906 i
.types
[xchg1
] = temp_type
;
4908 temp_flags
= i
.flags
[xchg2
];
4909 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4910 i
.flags
[xchg1
] = temp_flags
;
4912 temp_op
= i
.op
[xchg2
];
4913 i
.op
[xchg2
] = i
.op
[xchg1
];
4914 i
.op
[xchg1
] = temp_op
;
4916 temp_reloc
= i
.reloc
[xchg2
];
4917 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4918 i
.reloc
[xchg1
] = temp_reloc
;
4922 if (i
.mask
->operand
== xchg1
)
4923 i
.mask
->operand
= xchg2
;
4924 else if (i
.mask
->operand
== xchg2
)
4925 i
.mask
->operand
= xchg1
;
4929 if (i
.broadcast
->operand
== xchg1
)
4930 i
.broadcast
->operand
= xchg2
;
4931 else if (i
.broadcast
->operand
== xchg2
)
4932 i
.broadcast
->operand
= xchg1
;
4936 if (i
.rounding
->operand
== xchg1
)
4937 i
.rounding
->operand
= xchg2
;
4938 else if (i
.rounding
->operand
== xchg2
)
4939 i
.rounding
->operand
= xchg1
;
4944 swap_operands (void)
4950 swap_2_operands (1, i
.operands
- 2);
4954 swap_2_operands (0, i
.operands
- 1);
4960 if (i
.mem_operands
== 2)
4962 const seg_entry
*temp_seg
;
4963 temp_seg
= i
.seg
[0];
4964 i
.seg
[0] = i
.seg
[1];
4965 i
.seg
[1] = temp_seg
;
4969 /* Try to ensure constant immediates are represented in the smallest
4974 char guess_suffix
= 0;
4978 guess_suffix
= i
.suffix
;
4979 else if (i
.reg_operands
)
4981 /* Figure out a suffix from the last register operand specified.
4982 We can't do this properly yet, ie. excluding InOutPortReg,
4983 but the following works for instructions with immediates.
4984 In any case, we can't set i.suffix yet. */
4985 for (op
= i
.operands
; --op
>= 0;)
4986 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4988 guess_suffix
= BYTE_MNEM_SUFFIX
;
4991 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4993 guess_suffix
= WORD_MNEM_SUFFIX
;
4996 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4998 guess_suffix
= LONG_MNEM_SUFFIX
;
5001 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
5003 guess_suffix
= QWORD_MNEM_SUFFIX
;
5007 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5008 guess_suffix
= WORD_MNEM_SUFFIX
;
5010 for (op
= i
.operands
; --op
>= 0;)
5011 if (operand_type_check (i
.types
[op
], imm
))
5013 switch (i
.op
[op
].imms
->X_op
)
5016 /* If a suffix is given, this operand may be shortened. */
5017 switch (guess_suffix
)
5019 case LONG_MNEM_SUFFIX
:
5020 i
.types
[op
].bitfield
.imm32
= 1;
5021 i
.types
[op
].bitfield
.imm64
= 1;
5023 case WORD_MNEM_SUFFIX
:
5024 i
.types
[op
].bitfield
.imm16
= 1;
5025 i
.types
[op
].bitfield
.imm32
= 1;
5026 i
.types
[op
].bitfield
.imm32s
= 1;
5027 i
.types
[op
].bitfield
.imm64
= 1;
5029 case BYTE_MNEM_SUFFIX
:
5030 i
.types
[op
].bitfield
.imm8
= 1;
5031 i
.types
[op
].bitfield
.imm8s
= 1;
5032 i
.types
[op
].bitfield
.imm16
= 1;
5033 i
.types
[op
].bitfield
.imm32
= 1;
5034 i
.types
[op
].bitfield
.imm32s
= 1;
5035 i
.types
[op
].bitfield
.imm64
= 1;
5039 /* If this operand is at most 16 bits, convert it
5040 to a signed 16 bit number before trying to see
5041 whether it will fit in an even smaller size.
5042 This allows a 16-bit operand such as $0xffe0 to
5043 be recognised as within Imm8S range. */
5044 if ((i
.types
[op
].bitfield
.imm16
)
5045 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5047 i
.op
[op
].imms
->X_add_number
=
5048 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5051 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5052 if ((i
.types
[op
].bitfield
.imm32
)
5053 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5056 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5057 ^ ((offsetT
) 1 << 31))
5058 - ((offsetT
) 1 << 31));
5062 = operand_type_or (i
.types
[op
],
5063 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5065 /* We must avoid matching of Imm32 templates when 64bit
5066 only immediate is available. */
5067 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5068 i
.types
[op
].bitfield
.imm32
= 0;
5075 /* Symbols and expressions. */
5077 /* Convert symbolic operand to proper sizes for matching, but don't
5078 prevent matching a set of insns that only supports sizes other
5079 than those matching the insn suffix. */
5081 i386_operand_type mask
, allowed
;
5082 const insn_template
*t
;
5084 operand_type_set (&mask
, 0);
5085 operand_type_set (&allowed
, 0);
5087 for (t
= current_templates
->start
;
5088 t
< current_templates
->end
;
5090 allowed
= operand_type_or (allowed
,
5091 t
->operand_types
[op
]);
5092 switch (guess_suffix
)
5094 case QWORD_MNEM_SUFFIX
:
5095 mask
.bitfield
.imm64
= 1;
5096 mask
.bitfield
.imm32s
= 1;
5098 case LONG_MNEM_SUFFIX
:
5099 mask
.bitfield
.imm32
= 1;
5101 case WORD_MNEM_SUFFIX
:
5102 mask
.bitfield
.imm16
= 1;
5104 case BYTE_MNEM_SUFFIX
:
5105 mask
.bitfield
.imm8
= 1;
5110 allowed
= operand_type_and (mask
, allowed
);
5111 if (!operand_type_all_zero (&allowed
))
5112 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5119 /* Try to use the smallest displacement type too. */
5121 optimize_disp (void)
5125 for (op
= i
.operands
; --op
>= 0;)
5126 if (operand_type_check (i
.types
[op
], disp
))
5128 if (i
.op
[op
].disps
->X_op
== O_constant
)
5130 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5132 if (i
.types
[op
].bitfield
.disp16
5133 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5135 /* If this operand is at most 16 bits, convert
5136 to a signed 16 bit number and don't use 64bit
5138 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5139 i
.types
[op
].bitfield
.disp64
= 0;
5142 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5143 if (i
.types
[op
].bitfield
.disp32
5144 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5146 /* If this operand is at most 32 bits, convert
5147 to a signed 32 bit number and don't use 64bit
5149 op_disp
&= (((offsetT
) 2 << 31) - 1);
5150 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5151 i
.types
[op
].bitfield
.disp64
= 0;
5154 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5156 i
.types
[op
].bitfield
.disp8
= 0;
5157 i
.types
[op
].bitfield
.disp16
= 0;
5158 i
.types
[op
].bitfield
.disp32
= 0;
5159 i
.types
[op
].bitfield
.disp32s
= 0;
5160 i
.types
[op
].bitfield
.disp64
= 0;
5164 else if (flag_code
== CODE_64BIT
)
5166 if (fits_in_signed_long (op_disp
))
5168 i
.types
[op
].bitfield
.disp64
= 0;
5169 i
.types
[op
].bitfield
.disp32s
= 1;
5171 if (i
.prefix
[ADDR_PREFIX
]
5172 && fits_in_unsigned_long (op_disp
))
5173 i
.types
[op
].bitfield
.disp32
= 1;
5175 if ((i
.types
[op
].bitfield
.disp32
5176 || i
.types
[op
].bitfield
.disp32s
5177 || i
.types
[op
].bitfield
.disp16
)
5178 && fits_in_disp8 (op_disp
))
5179 i
.types
[op
].bitfield
.disp8
= 1;
5181 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5182 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5184 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5185 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5186 i
.types
[op
].bitfield
.disp8
= 0;
5187 i
.types
[op
].bitfield
.disp16
= 0;
5188 i
.types
[op
].bitfield
.disp32
= 0;
5189 i
.types
[op
].bitfield
.disp32s
= 0;
5190 i
.types
[op
].bitfield
.disp64
= 0;
5193 /* We only support 64bit displacement on constants. */
5194 i
.types
[op
].bitfield
.disp64
= 0;
5198 /* Return 1 if there is a match in broadcast bytes between operand
5199 GIVEN and instruction template T. */
5202 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5204 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5205 && i
.types
[given
].bitfield
.byte
)
5206 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5207 && i
.types
[given
].bitfield
.word
)
5208 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5209 && i
.types
[given
].bitfield
.dword
)
5210 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5211 && i
.types
[given
].bitfield
.qword
));
5214 /* Check if operands are valid for the instruction. */
5217 check_VecOperands (const insn_template
*t
)
5221 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5223 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5224 any one operand are implicity requiring AVX512VL support if the actual
5225 operand size is YMMword or XMMword. Since this function runs after
5226 template matching, there's no need to check for YMMword/XMMword in
5228 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5229 if (!cpu_flags_all_zero (&cpu
)
5230 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5231 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5233 for (op
= 0; op
< t
->operands
; ++op
)
5235 if (t
->operand_types
[op
].bitfield
.zmmword
5236 && (i
.types
[op
].bitfield
.ymmword
5237 || i
.types
[op
].bitfield
.xmmword
))
5239 i
.error
= unsupported
;
5245 /* Without VSIB byte, we can't have a vector register for index. */
5246 if (!t
->opcode_modifier
.vecsib
5248 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5249 || i
.index_reg
->reg_type
.bitfield
.ymmword
5250 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5252 i
.error
= unsupported_vector_index_register
;
5256 /* Check if default mask is allowed. */
5257 if (t
->opcode_modifier
.nodefmask
5258 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5260 i
.error
= no_default_mask
;
5264 /* For VSIB byte, we need a vector register for index, and all vector
5265 registers must be distinct. */
5266 if (t
->opcode_modifier
.vecsib
)
5269 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5270 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5271 || (t
->opcode_modifier
.vecsib
== VecSIB256
5272 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5273 || (t
->opcode_modifier
.vecsib
== VecSIB512
5274 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5276 i
.error
= invalid_vsib_address
;
5280 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5281 if (i
.reg_operands
== 2 && !i
.mask
)
5283 gas_assert (i
.types
[0].bitfield
.regsimd
);
5284 gas_assert (i
.types
[0].bitfield
.xmmword
5285 || i
.types
[0].bitfield
.ymmword
);
5286 gas_assert (i
.types
[2].bitfield
.regsimd
);
5287 gas_assert (i
.types
[2].bitfield
.xmmword
5288 || i
.types
[2].bitfield
.ymmword
);
5289 if (operand_check
== check_none
)
5291 if (register_number (i
.op
[0].regs
)
5292 != register_number (i
.index_reg
)
5293 && register_number (i
.op
[2].regs
)
5294 != register_number (i
.index_reg
)
5295 && register_number (i
.op
[0].regs
)
5296 != register_number (i
.op
[2].regs
))
5298 if (operand_check
== check_error
)
5300 i
.error
= invalid_vector_register_set
;
5303 as_warn (_("mask, index, and destination registers should be distinct"));
5305 else if (i
.reg_operands
== 1 && i
.mask
)
5307 if (i
.types
[1].bitfield
.regsimd
5308 && (i
.types
[1].bitfield
.xmmword
5309 || i
.types
[1].bitfield
.ymmword
5310 || i
.types
[1].bitfield
.zmmword
)
5311 && (register_number (i
.op
[1].regs
)
5312 == register_number (i
.index_reg
)))
5314 if (operand_check
== check_error
)
5316 i
.error
= invalid_vector_register_set
;
5319 if (operand_check
!= check_none
)
5320 as_warn (_("index and destination registers should be distinct"));
5325 /* Check if broadcast is supported by the instruction and is applied
5326 to the memory operand. */
5329 i386_operand_type type
, overlap
;
5331 /* Check if specified broadcast is supported in this instruction,
5332 and its broadcast bytes match the memory operand. */
5333 op
= i
.broadcast
->operand
;
5334 if (!t
->opcode_modifier
.broadcast
5335 || !(i
.flags
[op
] & Operand_Mem
)
5336 || (!i
.types
[op
].bitfield
.unspecified
5337 && !match_broadcast_size (t
, op
)))
5340 i
.error
= unsupported_broadcast
;
5344 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5345 * i
.broadcast
->type
);
5346 operand_type_set (&type
, 0);
5347 switch (i
.broadcast
->bytes
)
5350 type
.bitfield
.word
= 1;
5353 type
.bitfield
.dword
= 1;
5356 type
.bitfield
.qword
= 1;
5359 type
.bitfield
.xmmword
= 1;
5362 type
.bitfield
.ymmword
= 1;
5365 type
.bitfield
.zmmword
= 1;
5371 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5372 if (operand_type_all_zero (&overlap
))
5375 if (t
->opcode_modifier
.checkregsize
)
5379 type
.bitfield
.baseindex
= 1;
5380 for (j
= 0; j
< i
.operands
; ++j
)
5383 && !operand_type_register_match(i
.types
[j
],
5384 t
->operand_types
[j
],
5386 t
->operand_types
[op
]))
5391 /* If broadcast is supported in this instruction, we need to check if
5392 operand of one-element size isn't specified without broadcast. */
5393 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5395 /* Find memory operand. */
5396 for (op
= 0; op
< i
.operands
; op
++)
5397 if (operand_type_check (i
.types
[op
], anymem
))
5399 gas_assert (op
< i
.operands
);
5400 /* Check size of the memory operand. */
5401 if (match_broadcast_size (t
, op
))
5403 i
.error
= broadcast_needed
;
5408 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5410 /* Check if requested masking is supported. */
5413 switch (t
->opcode_modifier
.masking
)
5417 case MERGING_MASKING
:
5418 if (i
.mask
->zeroing
)
5421 i
.error
= unsupported_masking
;
5425 case DYNAMIC_MASKING
:
5426 /* Memory destinations allow only merging masking. */
5427 if (i
.mask
->zeroing
&& i
.mem_operands
)
5429 /* Find memory operand. */
5430 for (op
= 0; op
< i
.operands
; op
++)
5431 if (i
.flags
[op
] & Operand_Mem
)
5433 gas_assert (op
< i
.operands
);
5434 if (op
== i
.operands
- 1)
5436 i
.error
= unsupported_masking
;
5446 /* Check if masking is applied to dest operand. */
5447 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5449 i
.error
= mask_not_on_destination
;
5456 if ((i
.rounding
->type
!= saeonly
5457 && !t
->opcode_modifier
.staticrounding
)
5458 || (i
.rounding
->type
== saeonly
5459 && (t
->opcode_modifier
.staticrounding
5460 || !t
->opcode_modifier
.sae
)))
5462 i
.error
= unsupported_rc_sae
;
5465 /* If the instruction has several immediate operands and one of
5466 them is rounding, the rounding operand should be the last
5467 immediate operand. */
5468 if (i
.imm_operands
> 1
5469 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5471 i
.error
= rc_sae_operand_not_last_imm
;
5476 /* Check vector Disp8 operand. */
5477 if (t
->opcode_modifier
.disp8memshift
5478 && i
.disp_encoding
!= disp_encoding_32bit
)
5481 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5482 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5483 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5486 const i386_operand_type
*type
= NULL
;
5489 for (op
= 0; op
< i
.operands
; op
++)
5490 if (operand_type_check (i
.types
[op
], anymem
))
5492 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5493 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5494 else if (t
->operand_types
[op
].bitfield
.xmmword
5495 + t
->operand_types
[op
].bitfield
.ymmword
5496 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5497 type
= &t
->operand_types
[op
];
5498 else if (!i
.types
[op
].bitfield
.unspecified
)
5499 type
= &i
.types
[op
];
5501 else if (i
.types
[op
].bitfield
.regsimd
5502 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5504 if (i
.types
[op
].bitfield
.zmmword
)
5506 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5508 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5514 if (type
->bitfield
.zmmword
)
5516 else if (type
->bitfield
.ymmword
)
5518 else if (type
->bitfield
.xmmword
)
5522 /* For the check in fits_in_disp8(). */
5523 if (i
.memshift
== 0)
5527 for (op
= 0; op
< i
.operands
; op
++)
5528 if (operand_type_check (i
.types
[op
], disp
)
5529 && i
.op
[op
].disps
->X_op
== O_constant
)
5531 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5533 i
.types
[op
].bitfield
.disp8
= 1;
5536 i
.types
[op
].bitfield
.disp8
= 0;
5545 /* Check if operands are valid for the instruction. Update VEX
5549 VEX_check_operands (const insn_template
*t
)
5551 if (i
.vec_encoding
== vex_encoding_evex
)
5553 /* This instruction must be encoded with EVEX prefix. */
5554 if (!is_evex_encoding (t
))
5556 i
.error
= unsupported
;
5562 if (!t
->opcode_modifier
.vex
)
5564 /* This instruction template doesn't have VEX prefix. */
5565 if (i
.vec_encoding
!= vex_encoding_default
)
5567 i
.error
= unsupported
;
5573 /* Only check VEX_Imm4, which must be the first operand. */
5574 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5576 if (i
.op
[0].imms
->X_op
!= O_constant
5577 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5583 /* Turn off Imm8 so that update_imm won't complain. */
5584 i
.types
[0] = vec_imm4
;
5590 static const insn_template
*
5591 match_template (char mnem_suffix
)
5593 /* Points to template once we've found it. */
5594 const insn_template
*t
;
5595 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5596 i386_operand_type overlap4
;
5597 unsigned int found_reverse_match
;
5598 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5599 i386_operand_type operand_types
[MAX_OPERANDS
];
5600 int addr_prefix_disp
;
5602 unsigned int found_cpu_match
, size_match
;
5603 unsigned int check_register
;
5604 enum i386_error specific_error
= 0;
5606 #if MAX_OPERANDS != 5
5607 # error "MAX_OPERANDS must be 5."
5610 found_reverse_match
= 0;
5611 addr_prefix_disp
= -1;
5613 memset (&suffix_check
, 0, sizeof (suffix_check
));
5614 if (intel_syntax
&& i
.broadcast
)
5616 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5617 suffix_check
.no_bsuf
= 1;
5618 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5619 suffix_check
.no_wsuf
= 1;
5620 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5621 suffix_check
.no_ssuf
= 1;
5622 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5623 suffix_check
.no_lsuf
= 1;
5624 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5625 suffix_check
.no_qsuf
= 1;
5626 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5627 suffix_check
.no_ldsuf
= 1;
5629 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5632 switch (mnem_suffix
)
5634 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5635 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5636 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5637 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5638 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5642 /* Must have right number of operands. */
5643 i
.error
= number_of_operands_mismatch
;
5645 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5647 addr_prefix_disp
= -1;
5648 found_reverse_match
= 0;
5650 if (i
.operands
!= t
->operands
)
5653 /* Check processor support. */
5654 i
.error
= unsupported
;
5655 found_cpu_match
= (cpu_flags_match (t
)
5656 == CPU_FLAGS_PERFECT_MATCH
);
5657 if (!found_cpu_match
)
5660 /* Check AT&T mnemonic. */
5661 i
.error
= unsupported_with_intel_mnemonic
;
5662 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5665 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5666 i
.error
= unsupported_syntax
;
5667 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5668 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5669 || (intel64
&& t
->opcode_modifier
.amd64
)
5670 || (!intel64
&& t
->opcode_modifier
.intel64
))
5673 /* Check the suffix, except for some instructions in intel mode. */
5674 i
.error
= invalid_instruction_suffix
;
5675 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5676 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5677 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5678 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5679 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5680 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5681 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5683 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5684 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5685 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5686 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5687 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5688 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5689 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5692 size_match
= operand_size_match (t
);
5696 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5697 operand_types
[j
] = t
->operand_types
[j
];
5699 /* In general, don't allow 64-bit operands in 32-bit mode. */
5700 if (i
.suffix
== QWORD_MNEM_SUFFIX
5701 && flag_code
!= CODE_64BIT
5703 ? (!t
->opcode_modifier
.ignoresize
5704 && !t
->opcode_modifier
.broadcast
5705 && !intel_float_operand (t
->name
))
5706 : intel_float_operand (t
->name
) != 2)
5707 && ((!operand_types
[0].bitfield
.regmmx
5708 && !operand_types
[0].bitfield
.regsimd
)
5709 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5710 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5711 && (t
->base_opcode
!= 0x0fc7
5712 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5715 /* In general, don't allow 32-bit operands on pre-386. */
5716 else if (i
.suffix
== LONG_MNEM_SUFFIX
5717 && !cpu_arch_flags
.bitfield
.cpui386
5719 ? (!t
->opcode_modifier
.ignoresize
5720 && !intel_float_operand (t
->name
))
5721 : intel_float_operand (t
->name
) != 2)
5722 && ((!operand_types
[0].bitfield
.regmmx
5723 && !operand_types
[0].bitfield
.regsimd
)
5724 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5725 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5728 /* Do not verify operands when there are none. */
5732 /* We've found a match; break out of loop. */
5736 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5737 into Disp32/Disp16/Disp32 operand. */
5738 if (i
.prefix
[ADDR_PREFIX
] != 0)
5740 /* There should be only one Disp operand. */
5744 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5746 if (operand_types
[j
].bitfield
.disp16
)
5748 addr_prefix_disp
= j
;
5749 operand_types
[j
].bitfield
.disp32
= 1;
5750 operand_types
[j
].bitfield
.disp16
= 0;
5756 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5758 if (operand_types
[j
].bitfield
.disp32
)
5760 addr_prefix_disp
= j
;
5761 operand_types
[j
].bitfield
.disp32
= 0;
5762 operand_types
[j
].bitfield
.disp16
= 1;
5768 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5770 if (operand_types
[j
].bitfield
.disp64
)
5772 addr_prefix_disp
= j
;
5773 operand_types
[j
].bitfield
.disp64
= 0;
5774 operand_types
[j
].bitfield
.disp32
= 1;
5782 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5783 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5786 /* We check register size if needed. */
5787 if (t
->opcode_modifier
.checkregsize
)
5789 check_register
= (1 << t
->operands
) - 1;
5791 check_register
&= ~(1 << i
.broadcast
->operand
);
5796 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5797 switch (t
->operands
)
5800 if (!operand_type_match (overlap0
, i
.types
[0]))
5804 /* xchg %eax, %eax is a special case. It is an alias for nop
5805 only in 32bit mode and we can use opcode 0x90. In 64bit
5806 mode, we can't use 0x90 for xchg %eax, %eax since it should
5807 zero-extend %eax to %rax. */
5808 if (flag_code
== CODE_64BIT
5809 && t
->base_opcode
== 0x90
5810 && operand_type_equal (&i
.types
[0], &acc32
)
5811 && operand_type_equal (&i
.types
[1], &acc32
))
5813 /* xrelease mov %eax, <disp> is another special case. It must not
5814 match the accumulator-only encoding of mov. */
5815 if (flag_code
!= CODE_64BIT
5817 && t
->base_opcode
== 0xa0
5818 && i
.types
[0].bitfield
.acc
5819 && operand_type_check (i
.types
[1], anymem
))
5824 if (!(size_match
& MATCH_STRAIGHT
))
5826 /* Reverse direction of operands if swapping is possible in the first
5827 place (operands need to be symmetric) and
5828 - the load form is requested, and the template is a store form,
5829 - the store form is requested, and the template is a load form,
5830 - the non-default (swapped) form is requested. */
5831 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5832 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5833 && !operand_type_all_zero (&overlap1
))
5834 switch (i
.dir_encoding
)
5836 case dir_encoding_load
:
5837 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5838 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5842 case dir_encoding_store
:
5843 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5844 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5848 case dir_encoding_swap
:
5851 case dir_encoding_default
:
5854 /* If we want store form, we skip the current load. */
5855 if ((i
.dir_encoding
== dir_encoding_store
5856 || i
.dir_encoding
== dir_encoding_swap
)
5857 && i
.mem_operands
== 0
5858 && t
->opcode_modifier
.load
)
5863 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5864 if (!operand_type_match (overlap0
, i
.types
[0])
5865 || !operand_type_match (overlap1
, i
.types
[1])
5866 || ((check_register
& 3) == 3
5867 && !operand_type_register_match (i
.types
[0],
5872 /* Check if other direction is valid ... */
5873 if (!t
->opcode_modifier
.d
)
5877 if (!(size_match
& MATCH_REVERSE
))
5879 /* Try reversing direction of operands. */
5880 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5881 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5882 if (!operand_type_match (overlap0
, i
.types
[0])
5883 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5885 && !operand_type_register_match (i
.types
[0],
5886 operand_types
[i
.operands
- 1],
5887 i
.types
[i
.operands
- 1],
5890 /* Does not match either direction. */
5893 /* found_reverse_match holds which of D or FloatR
5895 if (!t
->opcode_modifier
.d
)
5896 found_reverse_match
= 0;
5897 else if (operand_types
[0].bitfield
.tbyte
)
5898 found_reverse_match
= Opcode_FloatD
;
5899 else if (operand_types
[0].bitfield
.xmmword
5900 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5901 || operand_types
[0].bitfield
.regmmx
5902 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5903 || is_any_vex_encoding(t
))
5904 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5905 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5907 found_reverse_match
= Opcode_D
;
5908 if (t
->opcode_modifier
.floatr
)
5909 found_reverse_match
|= Opcode_FloatR
;
5913 /* Found a forward 2 operand match here. */
5914 switch (t
->operands
)
5917 overlap4
= operand_type_and (i
.types
[4],
5921 overlap3
= operand_type_and (i
.types
[3],
5925 overlap2
= operand_type_and (i
.types
[2],
5930 switch (t
->operands
)
5933 if (!operand_type_match (overlap4
, i
.types
[4])
5934 || !operand_type_register_match (i
.types
[3],
5941 if (!operand_type_match (overlap3
, i
.types
[3])
5942 || ((check_register
& 0xa) == 0xa
5943 && !operand_type_register_match (i
.types
[1],
5947 || ((check_register
& 0xc) == 0xc
5948 && !operand_type_register_match (i
.types
[2],
5955 /* Here we make use of the fact that there are no
5956 reverse match 3 operand instructions. */
5957 if (!operand_type_match (overlap2
, i
.types
[2])
5958 || ((check_register
& 5) == 5
5959 && !operand_type_register_match (i
.types
[0],
5963 || ((check_register
& 6) == 6
5964 && !operand_type_register_match (i
.types
[1],
5972 /* Found either forward/reverse 2, 3 or 4 operand match here:
5973 slip through to break. */
5975 if (!found_cpu_match
)
5978 /* Check if vector and VEX operands are valid. */
5979 if (check_VecOperands (t
) || VEX_check_operands (t
))
5981 specific_error
= i
.error
;
5985 /* We've found a match; break out of loop. */
5989 if (t
== current_templates
->end
)
5991 /* We found no match. */
5992 const char *err_msg
;
5993 switch (specific_error
? specific_error
: i
.error
)
5997 case operand_size_mismatch
:
5998 err_msg
= _("operand size mismatch");
6000 case operand_type_mismatch
:
6001 err_msg
= _("operand type mismatch");
6003 case register_type_mismatch
:
6004 err_msg
= _("register type mismatch");
6006 case number_of_operands_mismatch
:
6007 err_msg
= _("number of operands mismatch");
6009 case invalid_instruction_suffix
:
6010 err_msg
= _("invalid instruction suffix");
6013 err_msg
= _("constant doesn't fit in 4 bits");
6015 case unsupported_with_intel_mnemonic
:
6016 err_msg
= _("unsupported with Intel mnemonic");
6018 case unsupported_syntax
:
6019 err_msg
= _("unsupported syntax");
6022 as_bad (_("unsupported instruction `%s'"),
6023 current_templates
->start
->name
);
6025 case invalid_vsib_address
:
6026 err_msg
= _("invalid VSIB address");
6028 case invalid_vector_register_set
:
6029 err_msg
= _("mask, index, and destination registers must be distinct");
6031 case unsupported_vector_index_register
:
6032 err_msg
= _("unsupported vector index register");
6034 case unsupported_broadcast
:
6035 err_msg
= _("unsupported broadcast");
6037 case broadcast_needed
:
6038 err_msg
= _("broadcast is needed for operand of such type");
6040 case unsupported_masking
:
6041 err_msg
= _("unsupported masking");
6043 case mask_not_on_destination
:
6044 err_msg
= _("mask not on destination operand");
6046 case no_default_mask
:
6047 err_msg
= _("default mask isn't allowed");
6049 case unsupported_rc_sae
:
6050 err_msg
= _("unsupported static rounding/sae");
6052 case rc_sae_operand_not_last_imm
:
6054 err_msg
= _("RC/SAE operand must precede immediate operands");
6056 err_msg
= _("RC/SAE operand must follow immediate operands");
6058 case invalid_register_operand
:
6059 err_msg
= _("invalid register operand");
6062 as_bad (_("%s for `%s'"), err_msg
,
6063 current_templates
->start
->name
);
6067 if (!quiet_warnings
)
6070 && (i
.types
[0].bitfield
.jumpabsolute
6071 != operand_types
[0].bitfield
.jumpabsolute
))
6073 as_warn (_("indirect %s without `*'"), t
->name
);
6076 if (t
->opcode_modifier
.isprefix
6077 && t
->opcode_modifier
.ignoresize
)
6079 /* Warn them that a data or address size prefix doesn't
6080 affect assembly of the next line of code. */
6081 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6085 /* Copy the template we found. */
6088 if (addr_prefix_disp
!= -1)
6089 i
.tm
.operand_types
[addr_prefix_disp
]
6090 = operand_types
[addr_prefix_disp
];
6092 if (found_reverse_match
)
6094 /* If we found a reverse match we must alter the opcode
6095 direction bit. found_reverse_match holds bits to change
6096 (different for int & float insns). */
6098 i
.tm
.base_opcode
^= found_reverse_match
;
6100 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6101 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6110 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6111 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6113 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6115 as_bad (_("`%s' operand %d must use `%ses' segment"),
6121 /* There's only ever one segment override allowed per instruction.
6122 This instruction possibly has a legal segment override on the
6123 second operand, so copy the segment to where non-string
6124 instructions store it, allowing common code. */
6125 i
.seg
[0] = i
.seg
[1];
6127 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6129 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6131 as_bad (_("`%s' operand %d must use `%ses' segment"),
6142 process_suffix (void)
6144 /* If matched instruction specifies an explicit instruction mnemonic
6146 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6147 i
.suffix
= WORD_MNEM_SUFFIX
;
6148 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6149 i
.suffix
= LONG_MNEM_SUFFIX
;
6150 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6151 i
.suffix
= QWORD_MNEM_SUFFIX
;
6152 else if (i
.reg_operands
)
6154 /* If there's no instruction mnemonic suffix we try to invent one
6155 based on register operands. */
6158 /* We take i.suffix from the last register operand specified,
6159 Destination register type is more significant than source
6160 register type. crc32 in SSE4.2 prefers source register
6162 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6164 if (i
.types
[0].bitfield
.byte
)
6165 i
.suffix
= BYTE_MNEM_SUFFIX
;
6166 else if (i
.types
[0].bitfield
.word
)
6167 i
.suffix
= WORD_MNEM_SUFFIX
;
6168 else if (i
.types
[0].bitfield
.dword
)
6169 i
.suffix
= LONG_MNEM_SUFFIX
;
6170 else if (i
.types
[0].bitfield
.qword
)
6171 i
.suffix
= QWORD_MNEM_SUFFIX
;
6178 if (i
.tm
.base_opcode
== 0xf20f38f0)
6180 /* We have to know the operand size for crc32. */
6181 as_bad (_("ambiguous memory operand size for `%s`"),
6186 for (op
= i
.operands
; --op
>= 0;)
6187 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6188 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6190 if (!i
.types
[op
].bitfield
.reg
)
6192 if (i
.types
[op
].bitfield
.byte
)
6193 i
.suffix
= BYTE_MNEM_SUFFIX
;
6194 else if (i
.types
[op
].bitfield
.word
)
6195 i
.suffix
= WORD_MNEM_SUFFIX
;
6196 else if (i
.types
[op
].bitfield
.dword
)
6197 i
.suffix
= LONG_MNEM_SUFFIX
;
6198 else if (i
.types
[op
].bitfield
.qword
)
6199 i
.suffix
= QWORD_MNEM_SUFFIX
;
6206 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6209 && i
.tm
.opcode_modifier
.ignoresize
6210 && i
.tm
.opcode_modifier
.no_bsuf
)
6212 else if (!check_byte_reg ())
6215 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6218 && i
.tm
.opcode_modifier
.ignoresize
6219 && i
.tm
.opcode_modifier
.no_lsuf
6220 && !i
.tm
.opcode_modifier
.todword
6221 && !i
.tm
.opcode_modifier
.toqword
)
6223 else if (!check_long_reg ())
6226 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6229 && i
.tm
.opcode_modifier
.ignoresize
6230 && i
.tm
.opcode_modifier
.no_qsuf
6231 && !i
.tm
.opcode_modifier
.todword
6232 && !i
.tm
.opcode_modifier
.toqword
)
6234 else if (!check_qword_reg ())
6237 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6240 && i
.tm
.opcode_modifier
.ignoresize
6241 && i
.tm
.opcode_modifier
.no_wsuf
)
6243 else if (!check_word_reg ())
6246 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6247 /* Do nothing if the instruction is going to ignore the prefix. */
6252 else if (i
.tm
.opcode_modifier
.defaultsize
6254 /* exclude fldenv/frstor/fsave/fstenv */
6255 && i
.tm
.opcode_modifier
.no_ssuf
)
6257 if (stackop_size
== LONG_MNEM_SUFFIX
6258 && i
.tm
.base_opcode
== 0xcf)
6260 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6261 .code16gcc directive to support 16-bit mode with
6262 32-bit address. For IRET without a suffix, generate
6263 16-bit IRET (opcode 0xcf) to return from an interrupt
6265 i
.suffix
= WORD_MNEM_SUFFIX
;
6266 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6269 i
.suffix
= stackop_size
;
6271 else if (intel_syntax
6273 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6274 || i
.tm
.opcode_modifier
.jumpbyte
6275 || i
.tm
.opcode_modifier
.jumpintersegment
6276 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6277 && i
.tm
.extension_opcode
<= 3)))
6282 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6284 i
.suffix
= QWORD_MNEM_SUFFIX
;
6289 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6290 i
.suffix
= LONG_MNEM_SUFFIX
;
6293 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6294 i
.suffix
= WORD_MNEM_SUFFIX
;
6303 if (i
.tm
.opcode_modifier
.w
)
6305 as_bad (_("no instruction mnemonic suffix given and "
6306 "no register operands; can't size instruction"));
6312 unsigned int suffixes
;
6314 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6315 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6317 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6319 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6321 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6323 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6326 /* There are more than suffix matches. */
6327 if (i
.tm
.opcode_modifier
.w
6328 || ((suffixes
& (suffixes
- 1))
6329 && !i
.tm
.opcode_modifier
.defaultsize
6330 && !i
.tm
.opcode_modifier
.ignoresize
))
6332 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6338 /* Change the opcode based on the operand size given by i.suffix. */
6341 /* Size floating point instruction. */
6342 case LONG_MNEM_SUFFIX
:
6343 if (i
.tm
.opcode_modifier
.floatmf
)
6345 i
.tm
.base_opcode
^= 4;
6349 case WORD_MNEM_SUFFIX
:
6350 case QWORD_MNEM_SUFFIX
:
6351 /* It's not a byte, select word/dword operation. */
6352 if (i
.tm
.opcode_modifier
.w
)
6354 if (i
.tm
.opcode_modifier
.shortform
)
6355 i
.tm
.base_opcode
|= 8;
6357 i
.tm
.base_opcode
|= 1;
6360 case SHORT_MNEM_SUFFIX
:
6361 /* Now select between word & dword operations via the operand
6362 size prefix, except for instructions that will ignore this
6364 if (i
.reg_operands
> 0
6365 && i
.types
[0].bitfield
.reg
6366 && i
.tm
.opcode_modifier
.addrprefixopreg
6367 && (i
.tm
.opcode_modifier
.immext
6368 || i
.operands
== 1))
6370 /* The address size override prefix changes the size of the
6372 if ((flag_code
== CODE_32BIT
6373 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6374 || (flag_code
!= CODE_32BIT
6375 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6376 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6379 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6380 && !i
.tm
.opcode_modifier
.ignoresize
6381 && !i
.tm
.opcode_modifier
.floatmf
6382 && !i
.tm
.opcode_modifier
.vex
6383 && !i
.tm
.opcode_modifier
.vexopcode
6384 && !is_evex_encoding (&i
.tm
)
6385 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6386 || (flag_code
== CODE_64BIT
6387 && i
.tm
.opcode_modifier
.jumpbyte
)))
6389 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6391 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6392 prefix
= ADDR_PREFIX_OPCODE
;
6394 if (!add_prefix (prefix
))
6398 /* Set mode64 for an operand. */
6399 if (i
.suffix
== QWORD_MNEM_SUFFIX
6400 && flag_code
== CODE_64BIT
6401 && !i
.tm
.opcode_modifier
.norex64
6402 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6404 && ! (i
.operands
== 2
6405 && i
.tm
.base_opcode
== 0x90
6406 && i
.tm
.extension_opcode
== None
6407 && operand_type_equal (&i
.types
[0], &acc64
)
6408 && operand_type_equal (&i
.types
[1], &acc64
)))
6414 if (i
.reg_operands
!= 0
6416 && i
.tm
.opcode_modifier
.addrprefixopreg
6417 && !i
.tm
.opcode_modifier
.immext
)
6419 /* Check invalid register operand when the address size override
6420 prefix changes the size of register operands. */
6422 enum { need_word
, need_dword
, need_qword
} need
;
6424 if (flag_code
== CODE_32BIT
)
6425 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6428 if (i
.prefix
[ADDR_PREFIX
])
6431 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6434 for (op
= 0; op
< i
.operands
; op
++)
6435 if (i
.types
[op
].bitfield
.reg
6436 && ((need
== need_word
6437 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6438 || (need
== need_dword
6439 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6440 || (need
== need_qword
6441 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6443 as_bad (_("invalid register operand size for `%s'"),
6453 check_byte_reg (void)
6457 for (op
= i
.operands
; --op
>= 0;)
6459 /* Skip non-register operands. */
6460 if (!i
.types
[op
].bitfield
.reg
)
6463 /* If this is an eight bit register, it's OK. If it's the 16 or
6464 32 bit version of an eight bit register, we will just use the
6465 low portion, and that's OK too. */
6466 if (i
.types
[op
].bitfield
.byte
)
6469 /* I/O port address operands are OK too. */
6470 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6473 /* crc32 doesn't generate this warning. */
6474 if (i
.tm
.base_opcode
== 0xf20f38f0)
6477 if ((i
.types
[op
].bitfield
.word
6478 || i
.types
[op
].bitfield
.dword
6479 || i
.types
[op
].bitfield
.qword
)
6480 && i
.op
[op
].regs
->reg_num
< 4
6481 /* Prohibit these changes in 64bit mode, since the lowering
6482 would be more complicated. */
6483 && flag_code
!= CODE_64BIT
)
6485 #if REGISTER_WARNINGS
6486 if (!quiet_warnings
)
6487 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6489 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6490 ? REGNAM_AL
- REGNAM_AX
6491 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6493 i
.op
[op
].regs
->reg_name
,
6498 /* Any other register is bad. */
6499 if (i
.types
[op
].bitfield
.reg
6500 || i
.types
[op
].bitfield
.regmmx
6501 || i
.types
[op
].bitfield
.regsimd
6502 || i
.types
[op
].bitfield
.sreg2
6503 || i
.types
[op
].bitfield
.sreg3
6504 || i
.types
[op
].bitfield
.control
6505 || i
.types
[op
].bitfield
.debug
6506 || i
.types
[op
].bitfield
.test
)
6508 as_bad (_("`%s%s' not allowed with `%s%c'"),
6510 i
.op
[op
].regs
->reg_name
,
6520 check_long_reg (void)
6524 for (op
= i
.operands
; --op
>= 0;)
6525 /* Skip non-register operands. */
6526 if (!i
.types
[op
].bitfield
.reg
)
6528 /* Reject eight bit registers, except where the template requires
6529 them. (eg. movzb) */
6530 else if (i
.types
[op
].bitfield
.byte
6531 && (i
.tm
.operand_types
[op
].bitfield
.reg
6532 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6533 && (i
.tm
.operand_types
[op
].bitfield
.word
6534 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6536 as_bad (_("`%s%s' not allowed with `%s%c'"),
6538 i
.op
[op
].regs
->reg_name
,
6543 /* Warn if the e prefix on a general reg is missing. */
6544 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6545 && i
.types
[op
].bitfield
.word
6546 && (i
.tm
.operand_types
[op
].bitfield
.reg
6547 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6548 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6550 /* Prohibit these changes in the 64bit mode, since the
6551 lowering is more complicated. */
6552 if (flag_code
== CODE_64BIT
)
6554 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6555 register_prefix
, i
.op
[op
].regs
->reg_name
,
6559 #if REGISTER_WARNINGS
6560 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6562 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6563 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6566 /* Warn if the r prefix on a general reg is present. */
6567 else if (i
.types
[op
].bitfield
.qword
6568 && (i
.tm
.operand_types
[op
].bitfield
.reg
6569 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6570 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6573 && i
.tm
.opcode_modifier
.toqword
6574 && !i
.types
[0].bitfield
.regsimd
)
6576 /* Convert to QWORD. We want REX byte. */
6577 i
.suffix
= QWORD_MNEM_SUFFIX
;
6581 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6582 register_prefix
, i
.op
[op
].regs
->reg_name
,
6591 check_qword_reg (void)
6595 for (op
= i
.operands
; --op
>= 0; )
6596 /* Skip non-register operands. */
6597 if (!i
.types
[op
].bitfield
.reg
)
6599 /* Reject eight bit registers, except where the template requires
6600 them. (eg. movzb) */
6601 else if (i
.types
[op
].bitfield
.byte
6602 && (i
.tm
.operand_types
[op
].bitfield
.reg
6603 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6604 && (i
.tm
.operand_types
[op
].bitfield
.word
6605 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6607 as_bad (_("`%s%s' not allowed with `%s%c'"),
6609 i
.op
[op
].regs
->reg_name
,
6614 /* Warn if the r prefix on a general reg is missing. */
6615 else if ((i
.types
[op
].bitfield
.word
6616 || i
.types
[op
].bitfield
.dword
)
6617 && (i
.tm
.operand_types
[op
].bitfield
.reg
6618 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6619 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6621 /* Prohibit these changes in the 64bit mode, since the
6622 lowering is more complicated. */
6624 && i
.tm
.opcode_modifier
.todword
6625 && !i
.types
[0].bitfield
.regsimd
)
6627 /* Convert to DWORD. We don't want REX byte. */
6628 i
.suffix
= LONG_MNEM_SUFFIX
;
6632 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6633 register_prefix
, i
.op
[op
].regs
->reg_name
,
6642 check_word_reg (void)
6645 for (op
= i
.operands
; --op
>= 0;)
6646 /* Skip non-register operands. */
6647 if (!i
.types
[op
].bitfield
.reg
)
6649 /* Reject eight bit registers, except where the template requires
6650 them. (eg. movzb) */
6651 else if (i
.types
[op
].bitfield
.byte
6652 && (i
.tm
.operand_types
[op
].bitfield
.reg
6653 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6654 && (i
.tm
.operand_types
[op
].bitfield
.word
6655 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6657 as_bad (_("`%s%s' not allowed with `%s%c'"),
6659 i
.op
[op
].regs
->reg_name
,
6664 /* Warn if the e or r prefix on a general reg is present. */
6665 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6666 && (i
.types
[op
].bitfield
.dword
6667 || i
.types
[op
].bitfield
.qword
)
6668 && (i
.tm
.operand_types
[op
].bitfield
.reg
6669 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6670 && i
.tm
.operand_types
[op
].bitfield
.word
)
6672 /* Prohibit these changes in the 64bit mode, since the
6673 lowering is more complicated. */
6674 if (flag_code
== CODE_64BIT
)
6676 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6677 register_prefix
, i
.op
[op
].regs
->reg_name
,
6681 #if REGISTER_WARNINGS
6682 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6684 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6685 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6692 update_imm (unsigned int j
)
6694 i386_operand_type overlap
= i
.types
[j
];
6695 if ((overlap
.bitfield
.imm8
6696 || overlap
.bitfield
.imm8s
6697 || overlap
.bitfield
.imm16
6698 || overlap
.bitfield
.imm32
6699 || overlap
.bitfield
.imm32s
6700 || overlap
.bitfield
.imm64
)
6701 && !operand_type_equal (&overlap
, &imm8
)
6702 && !operand_type_equal (&overlap
, &imm8s
)
6703 && !operand_type_equal (&overlap
, &imm16
)
6704 && !operand_type_equal (&overlap
, &imm32
)
6705 && !operand_type_equal (&overlap
, &imm32s
)
6706 && !operand_type_equal (&overlap
, &imm64
))
6710 i386_operand_type temp
;
6712 operand_type_set (&temp
, 0);
6713 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6715 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6716 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6718 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6719 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6720 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6722 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6723 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6726 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6729 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6730 || operand_type_equal (&overlap
, &imm16_32
)
6731 || operand_type_equal (&overlap
, &imm16_32s
))
6733 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6738 if (!operand_type_equal (&overlap
, &imm8
)
6739 && !operand_type_equal (&overlap
, &imm8s
)
6740 && !operand_type_equal (&overlap
, &imm16
)
6741 && !operand_type_equal (&overlap
, &imm32
)
6742 && !operand_type_equal (&overlap
, &imm32s
)
6743 && !operand_type_equal (&overlap
, &imm64
))
6745 as_bad (_("no instruction mnemonic suffix given; "
6746 "can't determine immediate size"));
6750 i
.types
[j
] = overlap
;
6760 /* Update the first 2 immediate operands. */
6761 n
= i
.operands
> 2 ? 2 : i
.operands
;
6764 for (j
= 0; j
< n
; j
++)
6765 if (update_imm (j
) == 0)
6768 /* The 3rd operand can't be immediate operand. */
6769 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6776 process_operands (void)
6778 /* Default segment register this instruction will use for memory
6779 accesses. 0 means unknown. This is only for optimizing out
6780 unnecessary segment overrides. */
6781 const seg_entry
*default_seg
= 0;
6783 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6785 unsigned int dupl
= i
.operands
;
6786 unsigned int dest
= dupl
- 1;
6789 /* The destination must be an xmm register. */
6790 gas_assert (i
.reg_operands
6791 && MAX_OPERANDS
> dupl
6792 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6794 if (i
.tm
.operand_types
[0].bitfield
.acc
6795 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6797 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6799 /* Keep xmm0 for instructions with VEX prefix and 3
6801 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6802 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6807 /* We remove the first xmm0 and keep the number of
6808 operands unchanged, which in fact duplicates the
6810 for (j
= 1; j
< i
.operands
; j
++)
6812 i
.op
[j
- 1] = i
.op
[j
];
6813 i
.types
[j
- 1] = i
.types
[j
];
6814 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6818 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6820 gas_assert ((MAX_OPERANDS
- 1) > dupl
6821 && (i
.tm
.opcode_modifier
.vexsources
6824 /* Add the implicit xmm0 for instructions with VEX prefix
6826 for (j
= i
.operands
; j
> 0; j
--)
6828 i
.op
[j
] = i
.op
[j
- 1];
6829 i
.types
[j
] = i
.types
[j
- 1];
6830 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6833 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6834 i
.types
[0] = regxmm
;
6835 i
.tm
.operand_types
[0] = regxmm
;
6838 i
.reg_operands
+= 2;
6843 i
.op
[dupl
] = i
.op
[dest
];
6844 i
.types
[dupl
] = i
.types
[dest
];
6845 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6854 i
.op
[dupl
] = i
.op
[dest
];
6855 i
.types
[dupl
] = i
.types
[dest
];
6856 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6859 if (i
.tm
.opcode_modifier
.immext
)
6862 else if (i
.tm
.operand_types
[0].bitfield
.acc
6863 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6867 for (j
= 1; j
< i
.operands
; j
++)
6869 i
.op
[j
- 1] = i
.op
[j
];
6870 i
.types
[j
- 1] = i
.types
[j
];
6872 /* We need to adjust fields in i.tm since they are used by
6873 build_modrm_byte. */
6874 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6881 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6883 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6885 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6886 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6887 regnum
= register_number (i
.op
[1].regs
);
6888 first_reg_in_group
= regnum
& ~3;
6889 last_reg_in_group
= first_reg_in_group
+ 3;
6890 if (regnum
!= first_reg_in_group
)
6891 as_warn (_("source register `%s%s' implicitly denotes"
6892 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6893 register_prefix
, i
.op
[1].regs
->reg_name
,
6894 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6895 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6898 else if (i
.tm
.opcode_modifier
.regkludge
)
6900 /* The imul $imm, %reg instruction is converted into
6901 imul $imm, %reg, %reg, and the clr %reg instruction
6902 is converted into xor %reg, %reg. */
6904 unsigned int first_reg_op
;
6906 if (operand_type_check (i
.types
[0], reg
))
6910 /* Pretend we saw the extra register operand. */
6911 gas_assert (i
.reg_operands
== 1
6912 && i
.op
[first_reg_op
+ 1].regs
== 0);
6913 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6914 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6919 if (i
.tm
.opcode_modifier
.shortform
)
6921 if (i
.types
[0].bitfield
.sreg2
6922 || i
.types
[0].bitfield
.sreg3
)
6924 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6925 && i
.op
[0].regs
->reg_num
== 1)
6927 as_bad (_("you can't `pop %scs'"), register_prefix
);
6930 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6931 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6936 /* The register or float register operand is in operand
6940 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6941 || operand_type_check (i
.types
[0], reg
))
6945 /* Register goes in low 3 bits of opcode. */
6946 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6947 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6949 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6951 /* Warn about some common errors, but press on regardless.
6952 The first case can be generated by gcc (<= 2.8.1). */
6953 if (i
.operands
== 2)
6955 /* Reversed arguments on faddp, fsubp, etc. */
6956 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6957 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6958 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6962 /* Extraneous `l' suffix on fp insn. */
6963 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6964 register_prefix
, i
.op
[0].regs
->reg_name
);
6969 else if (i
.tm
.opcode_modifier
.modrm
)
6971 /* The opcode is completed (modulo i.tm.extension_opcode which
6972 must be put into the modrm byte). Now, we make the modrm and
6973 index base bytes based on all the info we've collected. */
6975 default_seg
= build_modrm_byte ();
6977 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6981 else if (i
.tm
.opcode_modifier
.isstring
)
6983 /* For the string instructions that allow a segment override
6984 on one of their operands, the default segment is ds. */
6988 if (i
.tm
.base_opcode
== 0x8d /* lea */
6991 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6993 /* If a segment was explicitly specified, and the specified segment
6994 is not the default, use an opcode prefix to select it. If we
6995 never figured out what the default segment is, then default_seg
6996 will be zero at this point, and the specified segment prefix will
6998 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7000 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7006 static const seg_entry
*
7007 build_modrm_byte (void)
7009 const seg_entry
*default_seg
= 0;
7010 unsigned int source
, dest
;
7013 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7016 unsigned int nds
, reg_slot
;
7019 dest
= i
.operands
- 1;
7022 /* There are 2 kinds of instructions:
7023 1. 5 operands: 4 register operands or 3 register operands
7024 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
7025 VexW0 or VexW1. The destination must be either XMM, YMM or
7027 2. 4 operands: 4 register operands or 3 register operands
7028 plus 1 memory operand, with VexXDS. */
7029 gas_assert ((i
.reg_operands
== 4
7030 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7031 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7032 && i
.tm
.opcode_modifier
.vexw
7033 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
7035 /* If VexW1 is set, the first non-immediate operand is the source and
7036 the second non-immediate one is encoded in the immediate operand. */
7037 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7039 source
= i
.imm_operands
;
7040 reg_slot
= i
.imm_operands
+ 1;
7044 source
= i
.imm_operands
+ 1;
7045 reg_slot
= i
.imm_operands
;
7048 if (i
.imm_operands
== 0)
7050 /* When there is no immediate operand, generate an 8bit
7051 immediate operand to encode the first operand. */
7052 exp
= &im_expressions
[i
.imm_operands
++];
7053 i
.op
[i
.operands
].imms
= exp
;
7054 i
.types
[i
.operands
] = imm8
;
7057 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7058 exp
->X_op
= O_constant
;
7059 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7060 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7064 unsigned int imm_slot
;
7066 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
7068 if (i
.tm
.opcode_modifier
.immext
)
7070 /* When ImmExt is set, the immediate byte is the last
7072 imm_slot
= i
.operands
- 1;
7080 /* Turn on Imm8 so that output_imm will generate it. */
7081 i
.types
[imm_slot
].bitfield
.imm8
= 1;
7084 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7085 i
.op
[imm_slot
].imms
->X_add_number
7086 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7087 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7090 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7091 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7096 /* i.reg_operands MUST be the number of real register operands;
7097 implicit registers do not count. If there are 3 register
7098 operands, it must be a instruction with VexNDS. For a
7099 instruction with VexNDD, the destination register is encoded
7100 in VEX prefix. If there are 4 register operands, it must be
7101 a instruction with VEX prefix and 3 sources. */
7102 if (i
.mem_operands
== 0
7103 && ((i
.reg_operands
== 2
7104 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7105 || (i
.reg_operands
== 3
7106 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7107 || (i
.reg_operands
== 4 && vex_3_sources
)))
7115 /* When there are 3 operands, one of them may be immediate,
7116 which may be the first or the last operand. Otherwise,
7117 the first operand must be shift count register (cl) or it
7118 is an instruction with VexNDS. */
7119 gas_assert (i
.imm_operands
== 1
7120 || (i
.imm_operands
== 0
7121 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7122 || i
.types
[0].bitfield
.shiftcount
)));
7123 if (operand_type_check (i
.types
[0], imm
)
7124 || i
.types
[0].bitfield
.shiftcount
)
7130 /* When there are 4 operands, the first two must be 8bit
7131 immediate operands. The source operand will be the 3rd
7134 For instructions with VexNDS, if the first operand
7135 an imm8, the source operand is the 2nd one. If the last
7136 operand is imm8, the source operand is the first one. */
7137 gas_assert ((i
.imm_operands
== 2
7138 && i
.types
[0].bitfield
.imm8
7139 && i
.types
[1].bitfield
.imm8
)
7140 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7141 && i
.imm_operands
== 1
7142 && (i
.types
[0].bitfield
.imm8
7143 || i
.types
[i
.operands
- 1].bitfield
.imm8
7145 if (i
.imm_operands
== 2)
7149 if (i
.types
[0].bitfield
.imm8
)
7156 if (is_evex_encoding (&i
.tm
))
7158 /* For EVEX instructions, when there are 5 operands, the
7159 first one must be immediate operand. If the second one
7160 is immediate operand, the source operand is the 3th
7161 one. If the last one is immediate operand, the source
7162 operand is the 2nd one. */
7163 gas_assert (i
.imm_operands
== 2
7164 && i
.tm
.opcode_modifier
.sae
7165 && operand_type_check (i
.types
[0], imm
));
7166 if (operand_type_check (i
.types
[1], imm
))
7168 else if (operand_type_check (i
.types
[4], imm
))
7182 /* RC/SAE operand could be between DEST and SRC. That happens
7183 when one operand is GPR and the other one is XMM/YMM/ZMM
7185 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7188 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7190 /* For instructions with VexNDS, the register-only source
7191 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7192 register. It is encoded in VEX prefix. We need to
7193 clear RegMem bit before calling operand_type_equal. */
7195 i386_operand_type op
;
7198 /* Check register-only source operand when two source
7199 operands are swapped. */
7200 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7201 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7209 op
= i
.tm
.operand_types
[vvvv
];
7210 op
.bitfield
.regmem
= 0;
7211 if ((dest
+ 1) >= i
.operands
7212 || ((!op
.bitfield
.reg
7213 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7214 && !op
.bitfield
.regsimd
7215 && !operand_type_equal (&op
, ®mask
)))
7217 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7223 /* One of the register operands will be encoded in the i.tm.reg
7224 field, the other in the combined i.tm.mode and i.tm.regmem
7225 fields. If no form of this instruction supports a memory
7226 destination operand, then we assume the source operand may
7227 sometimes be a memory operand and so we need to store the
7228 destination in the i.rm.reg field. */
7229 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7230 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7232 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7233 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7234 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7235 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7236 i
.has_regmmx
= TRUE
;
7237 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7238 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7240 if (i
.types
[dest
].bitfield
.zmmword
7241 || i
.types
[source
].bitfield
.zmmword
)
7242 i
.has_regzmm
= TRUE
;
7243 else if (i
.types
[dest
].bitfield
.ymmword
7244 || i
.types
[source
].bitfield
.ymmword
)
7245 i
.has_regymm
= TRUE
;
7247 i
.has_regxmm
= TRUE
;
7249 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7251 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7253 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7255 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7260 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7261 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7262 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7264 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7266 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7268 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7271 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7273 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7276 add_prefix (LOCK_PREFIX_OPCODE
);
7280 { /* If it's not 2 reg operands... */
7285 unsigned int fake_zero_displacement
= 0;
7288 for (op
= 0; op
< i
.operands
; op
++)
7289 if (operand_type_check (i
.types
[op
], anymem
))
7291 gas_assert (op
< i
.operands
);
7293 if (i
.tm
.opcode_modifier
.vecsib
)
7295 if (i
.index_reg
->reg_num
== RegIZ
)
7298 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7301 i
.sib
.base
= NO_BASE_REGISTER
;
7302 i
.sib
.scale
= i
.log2_scale_factor
;
7303 i
.types
[op
].bitfield
.disp8
= 0;
7304 i
.types
[op
].bitfield
.disp16
= 0;
7305 i
.types
[op
].bitfield
.disp64
= 0;
7306 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7308 /* Must be 32 bit */
7309 i
.types
[op
].bitfield
.disp32
= 1;
7310 i
.types
[op
].bitfield
.disp32s
= 0;
7314 i
.types
[op
].bitfield
.disp32
= 0;
7315 i
.types
[op
].bitfield
.disp32s
= 1;
7318 i
.sib
.index
= i
.index_reg
->reg_num
;
7319 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7321 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7327 if (i
.base_reg
== 0)
7330 if (!i
.disp_operands
)
7331 fake_zero_displacement
= 1;
7332 if (i
.index_reg
== 0)
7334 i386_operand_type newdisp
;
7336 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7337 /* Operand is just <disp> */
7338 if (flag_code
== CODE_64BIT
)
7340 /* 64bit mode overwrites the 32bit absolute
7341 addressing by RIP relative addressing and
7342 absolute addressing is encoded by one of the
7343 redundant SIB forms. */
7344 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7345 i
.sib
.base
= NO_BASE_REGISTER
;
7346 i
.sib
.index
= NO_INDEX_REGISTER
;
7347 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7349 else if ((flag_code
== CODE_16BIT
)
7350 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7352 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7357 i
.rm
.regmem
= NO_BASE_REGISTER
;
7360 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7361 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7363 else if (!i
.tm
.opcode_modifier
.vecsib
)
7365 /* !i.base_reg && i.index_reg */
7366 if (i
.index_reg
->reg_num
== RegIZ
)
7367 i
.sib
.index
= NO_INDEX_REGISTER
;
7369 i
.sib
.index
= i
.index_reg
->reg_num
;
7370 i
.sib
.base
= NO_BASE_REGISTER
;
7371 i
.sib
.scale
= i
.log2_scale_factor
;
7372 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7373 i
.types
[op
].bitfield
.disp8
= 0;
7374 i
.types
[op
].bitfield
.disp16
= 0;
7375 i
.types
[op
].bitfield
.disp64
= 0;
7376 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7378 /* Must be 32 bit */
7379 i
.types
[op
].bitfield
.disp32
= 1;
7380 i
.types
[op
].bitfield
.disp32s
= 0;
7384 i
.types
[op
].bitfield
.disp32
= 0;
7385 i
.types
[op
].bitfield
.disp32s
= 1;
7387 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7391 /* RIP addressing for 64bit mode. */
7392 else if (i
.base_reg
->reg_num
== RegIP
)
7394 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7395 i
.rm
.regmem
= NO_BASE_REGISTER
;
7396 i
.types
[op
].bitfield
.disp8
= 0;
7397 i
.types
[op
].bitfield
.disp16
= 0;
7398 i
.types
[op
].bitfield
.disp32
= 0;
7399 i
.types
[op
].bitfield
.disp32s
= 1;
7400 i
.types
[op
].bitfield
.disp64
= 0;
7401 i
.flags
[op
] |= Operand_PCrel
;
7402 if (! i
.disp_operands
)
7403 fake_zero_displacement
= 1;
7405 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7407 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7408 switch (i
.base_reg
->reg_num
)
7411 if (i
.index_reg
== 0)
7413 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7414 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7418 if (i
.index_reg
== 0)
7421 if (operand_type_check (i
.types
[op
], disp
) == 0)
7423 /* fake (%bp) into 0(%bp) */
7424 i
.types
[op
].bitfield
.disp8
= 1;
7425 fake_zero_displacement
= 1;
7428 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7429 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7431 default: /* (%si) -> 4 or (%di) -> 5 */
7432 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7434 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7436 else /* i.base_reg and 32/64 bit mode */
7438 if (flag_code
== CODE_64BIT
7439 && operand_type_check (i
.types
[op
], disp
))
7441 i
.types
[op
].bitfield
.disp16
= 0;
7442 i
.types
[op
].bitfield
.disp64
= 0;
7443 if (i
.prefix
[ADDR_PREFIX
] == 0)
7445 i
.types
[op
].bitfield
.disp32
= 0;
7446 i
.types
[op
].bitfield
.disp32s
= 1;
7450 i
.types
[op
].bitfield
.disp32
= 1;
7451 i
.types
[op
].bitfield
.disp32s
= 0;
7455 if (!i
.tm
.opcode_modifier
.vecsib
)
7456 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7457 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7459 i
.sib
.base
= i
.base_reg
->reg_num
;
7460 /* x86-64 ignores REX prefix bit here to avoid decoder
7462 if (!(i
.base_reg
->reg_flags
& RegRex
)
7463 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7464 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7466 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7468 fake_zero_displacement
= 1;
7469 i
.types
[op
].bitfield
.disp8
= 1;
7471 i
.sib
.scale
= i
.log2_scale_factor
;
7472 if (i
.index_reg
== 0)
7474 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7475 /* <disp>(%esp) becomes two byte modrm with no index
7476 register. We've already stored the code for esp
7477 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7478 Any base register besides %esp will not use the
7479 extra modrm byte. */
7480 i
.sib
.index
= NO_INDEX_REGISTER
;
7482 else if (!i
.tm
.opcode_modifier
.vecsib
)
7484 if (i
.index_reg
->reg_num
== RegIZ
)
7485 i
.sib
.index
= NO_INDEX_REGISTER
;
7487 i
.sib
.index
= i
.index_reg
->reg_num
;
7488 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7489 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7494 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7495 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7499 if (!fake_zero_displacement
7503 fake_zero_displacement
= 1;
7504 if (i
.disp_encoding
== disp_encoding_8bit
)
7505 i
.types
[op
].bitfield
.disp8
= 1;
7507 i
.types
[op
].bitfield
.disp32
= 1;
7509 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7513 if (fake_zero_displacement
)
7515 /* Fakes a zero displacement assuming that i.types[op]
7516 holds the correct displacement size. */
7519 gas_assert (i
.op
[op
].disps
== 0);
7520 exp
= &disp_expressions
[i
.disp_operands
++];
7521 i
.op
[op
].disps
= exp
;
7522 exp
->X_op
= O_constant
;
7523 exp
->X_add_number
= 0;
7524 exp
->X_add_symbol
= (symbolS
*) 0;
7525 exp
->X_op_symbol
= (symbolS
*) 0;
7533 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7535 if (operand_type_check (i
.types
[0], imm
))
7536 i
.vex
.register_specifier
= NULL
;
7539 /* VEX.vvvv encodes one of the sources when the first
7540 operand is not an immediate. */
7541 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7542 i
.vex
.register_specifier
= i
.op
[0].regs
;
7544 i
.vex
.register_specifier
= i
.op
[1].regs
;
7547 /* Destination is a XMM register encoded in the ModRM.reg
7549 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7550 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7553 /* ModRM.rm and VEX.B encodes the other source. */
7554 if (!i
.mem_operands
)
7558 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7559 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7561 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7563 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7567 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7569 i
.vex
.register_specifier
= i
.op
[2].regs
;
7570 if (!i
.mem_operands
)
7573 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7574 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7578 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7579 (if any) based on i.tm.extension_opcode. Again, we must be
7580 careful to make sure that segment/control/debug/test/MMX
7581 registers are coded into the i.rm.reg field. */
7582 else if (i
.reg_operands
)
7585 unsigned int vex_reg
= ~0;
7587 for (op
= 0; op
< i
.operands
; op
++)
7589 if (i
.types
[op
].bitfield
.reg
7590 || i
.types
[op
].bitfield
.regbnd
7591 || i
.types
[op
].bitfield
.regmask
7592 || i
.types
[op
].bitfield
.sreg2
7593 || i
.types
[op
].bitfield
.sreg3
7594 || i
.types
[op
].bitfield
.control
7595 || i
.types
[op
].bitfield
.debug
7596 || i
.types
[op
].bitfield
.test
)
7598 if (i
.types
[op
].bitfield
.regsimd
)
7600 if (i
.types
[op
].bitfield
.zmmword
)
7601 i
.has_regzmm
= TRUE
;
7602 else if (i
.types
[op
].bitfield
.ymmword
)
7603 i
.has_regymm
= TRUE
;
7605 i
.has_regxmm
= TRUE
;
7608 if (i
.types
[op
].bitfield
.regmmx
)
7610 i
.has_regmmx
= TRUE
;
7617 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7619 /* For instructions with VexNDS, the register-only
7620 source operand is encoded in VEX prefix. */
7621 gas_assert (mem
!= (unsigned int) ~0);
7626 gas_assert (op
< i
.operands
);
7630 /* Check register-only source operand when two source
7631 operands are swapped. */
7632 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7633 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7637 gas_assert (mem
== (vex_reg
+ 1)
7638 && op
< i
.operands
);
7643 gas_assert (vex_reg
< i
.operands
);
7647 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7649 /* For instructions with VexNDD, the register destination
7650 is encoded in VEX prefix. */
7651 if (i
.mem_operands
== 0)
7653 /* There is no memory operand. */
7654 gas_assert ((op
+ 2) == i
.operands
);
7659 /* There are only 2 non-immediate operands. */
7660 gas_assert (op
< i
.imm_operands
+ 2
7661 && i
.operands
== i
.imm_operands
+ 2);
7662 vex_reg
= i
.imm_operands
+ 1;
7666 gas_assert (op
< i
.operands
);
7668 if (vex_reg
!= (unsigned int) ~0)
7670 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7672 if ((!type
->bitfield
.reg
7673 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7674 && !type
->bitfield
.regsimd
7675 && !operand_type_equal (type
, ®mask
))
7678 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7681 /* Don't set OP operand twice. */
7684 /* If there is an extension opcode to put here, the
7685 register number must be put into the regmem field. */
7686 if (i
.tm
.extension_opcode
!= None
)
7688 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7689 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7691 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7696 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7697 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7699 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7704 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7705 must set it to 3 to indicate this is a register operand
7706 in the regmem field. */
7707 if (!i
.mem_operands
)
7711 /* Fill in i.rm.reg field with extension opcode (if any). */
7712 if (i
.tm
.extension_opcode
!= None
)
7713 i
.rm
.reg
= i
.tm
.extension_opcode
;
7719 output_branch (void)
7725 relax_substateT subtype
;
7729 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7730 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7733 if (i
.prefix
[DATA_PREFIX
] != 0)
7739 /* Pentium4 branch hints. */
7740 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7741 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7746 if (i
.prefix
[REX_PREFIX
] != 0)
7752 /* BND prefixed jump. */
7753 if (i
.prefix
[BND_PREFIX
] != 0)
7755 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7759 if (i
.prefixes
!= 0 && !intel_syntax
)
7760 as_warn (_("skipping prefixes on this instruction"));
7762 /* It's always a symbol; End frag & setup for relax.
7763 Make sure there is enough room in this frag for the largest
7764 instruction we may generate in md_convert_frag. This is 2
7765 bytes for the opcode and room for the prefix and largest
7767 frag_grow (prefix
+ 2 + 4);
7768 /* Prefix and 1 opcode byte go in fr_fix. */
7769 p
= frag_more (prefix
+ 1);
7770 if (i
.prefix
[DATA_PREFIX
] != 0)
7771 *p
++ = DATA_PREFIX_OPCODE
;
7772 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7773 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7774 *p
++ = i
.prefix
[SEG_PREFIX
];
7775 if (i
.prefix
[REX_PREFIX
] != 0)
7776 *p
++ = i
.prefix
[REX_PREFIX
];
7777 *p
= i
.tm
.base_opcode
;
7779 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7780 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7781 else if (cpu_arch_flags
.bitfield
.cpui386
)
7782 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7784 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7787 sym
= i
.op
[0].disps
->X_add_symbol
;
7788 off
= i
.op
[0].disps
->X_add_number
;
7790 if (i
.op
[0].disps
->X_op
!= O_constant
7791 && i
.op
[0].disps
->X_op
!= O_symbol
)
7793 /* Handle complex expressions. */
7794 sym
= make_expr_symbol (i
.op
[0].disps
);
7798 /* 1 possible extra opcode + 4 byte displacement go in var part.
7799 Pass reloc in fr_var. */
7800 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7803 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7804 /* Return TRUE iff PLT32 relocation should be used for branching to
7808 need_plt32_p (symbolS
*s
)
7810 /* PLT32 relocation is ELF only. */
7815 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7816 krtld support it. */
7820 /* Since there is no need to prepare for PLT branch on x86-64, we
7821 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7822 be used as a marker for 32-bit PC-relative branches. */
7826 /* Weak or undefined symbol need PLT32 relocation. */
7827 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7830 /* Non-global symbol doesn't need PLT32 relocation. */
7831 if (! S_IS_EXTERNAL (s
))
7834 /* Other global symbols need PLT32 relocation. NB: Symbol with
7835 non-default visibilities are treated as normal global symbol
7836 so that PLT32 relocation can be used as a marker for 32-bit
7837 PC-relative branches. It is useful for linker relaxation. */
7848 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7850 if (i
.tm
.opcode_modifier
.jumpbyte
)
7852 /* This is a loop or jecxz type instruction. */
7854 if (i
.prefix
[ADDR_PREFIX
] != 0)
7856 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7859 /* Pentium4 branch hints. */
7860 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7861 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7863 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7872 if (flag_code
== CODE_16BIT
)
7875 if (i
.prefix
[DATA_PREFIX
] != 0)
7877 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7887 if (i
.prefix
[REX_PREFIX
] != 0)
7889 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7893 /* BND prefixed jump. */
7894 if (i
.prefix
[BND_PREFIX
] != 0)
7896 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7900 if (i
.prefixes
!= 0 && !intel_syntax
)
7901 as_warn (_("skipping prefixes on this instruction"));
7903 p
= frag_more (i
.tm
.opcode_length
+ size
);
7904 switch (i
.tm
.opcode_length
)
7907 *p
++ = i
.tm
.base_opcode
>> 8;
7910 *p
++ = i
.tm
.base_opcode
;
7916 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7918 && jump_reloc
== NO_RELOC
7919 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7920 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7923 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7925 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7926 i
.op
[0].disps
, 1, jump_reloc
);
7928 /* All jumps handled here are signed, but don't use a signed limit
7929 check for 32 and 16 bit jumps as we want to allow wrap around at
7930 4G and 64k respectively. */
7932 fixP
->fx_signed
= 1;
7936 output_interseg_jump (void)
7944 if (flag_code
== CODE_16BIT
)
7948 if (i
.prefix
[DATA_PREFIX
] != 0)
7954 if (i
.prefix
[REX_PREFIX
] != 0)
7964 if (i
.prefixes
!= 0 && !intel_syntax
)
7965 as_warn (_("skipping prefixes on this instruction"));
7967 /* 1 opcode; 2 segment; offset */
7968 p
= frag_more (prefix
+ 1 + 2 + size
);
7970 if (i
.prefix
[DATA_PREFIX
] != 0)
7971 *p
++ = DATA_PREFIX_OPCODE
;
7973 if (i
.prefix
[REX_PREFIX
] != 0)
7974 *p
++ = i
.prefix
[REX_PREFIX
];
7976 *p
++ = i
.tm
.base_opcode
;
7977 if (i
.op
[1].imms
->X_op
== O_constant
)
7979 offsetT n
= i
.op
[1].imms
->X_add_number
;
7982 && !fits_in_unsigned_word (n
)
7983 && !fits_in_signed_word (n
))
7985 as_bad (_("16-bit jump out of range"));
7988 md_number_to_chars (p
, n
, size
);
7991 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7992 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7993 if (i
.op
[0].imms
->X_op
!= O_constant
)
7994 as_bad (_("can't handle non absolute segment in `%s'"),
7996 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7999 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8004 asection
*seg
= now_seg
;
8005 subsegT subseg
= now_subseg
;
8007 unsigned int alignment
, align_size_1
;
8008 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8009 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8010 unsigned int padding
;
8012 if (!IS_ELF
|| !x86_used_note
)
8015 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8017 /* The .note.gnu.property section layout:
8019 Field Length Contents
8022 n_descsz 4 The note descriptor size
8023 n_type 4 NT_GNU_PROPERTY_TYPE_0
8025 n_desc n_descsz The program property array
8029 /* Create the .note.gnu.property section. */
8030 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8031 bfd_set_section_flags (stdoutput
, sec
,
8038 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8049 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
8050 elf_section_type (sec
) = SHT_NOTE
;
8052 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8054 isa_1_descsz_raw
= 4 + 4 + 4;
8055 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8056 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8058 feature_2_descsz_raw
= isa_1_descsz
;
8059 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8061 feature_2_descsz_raw
+= 4 + 4 + 4;
8062 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8063 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8066 descsz
= feature_2_descsz
;
8067 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8068 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8070 /* Write n_namsz. */
8071 md_number_to_chars (p
, (valueT
) 4, 4);
8073 /* Write n_descsz. */
8074 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8077 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8080 memcpy (p
+ 4 * 3, "GNU", 4);
8082 /* Write 4-byte type. */
8083 md_number_to_chars (p
+ 4 * 4,
8084 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8086 /* Write 4-byte data size. */
8087 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8089 /* Write 4-byte data. */
8090 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8092 /* Zero out paddings. */
8093 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8095 memset (p
+ 4 * 7, 0, padding
);
8097 /* Write 4-byte type. */
8098 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8099 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8101 /* Write 4-byte data size. */
8102 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8104 /* Write 4-byte data. */
8105 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8106 (valueT
) x86_feature_2_used
, 4);
8108 /* Zero out paddings. */
8109 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8111 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8113 /* We probably can't restore the current segment, for there likely
8116 subseg_set (seg
, subseg
);
8123 fragS
*insn_start_frag
;
8124 offsetT insn_start_off
;
8126 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8127 if (IS_ELF
&& x86_used_note
)
8129 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8130 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8131 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8132 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8133 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8134 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8135 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8136 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8137 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8138 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8139 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8140 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8141 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8142 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8143 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8144 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8145 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8146 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8147 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8148 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8149 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8150 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8151 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8152 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8153 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8154 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8155 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8156 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8157 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8158 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8159 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8160 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8161 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8162 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8163 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8164 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8165 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8166 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8167 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8168 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8169 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8170 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8171 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8172 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8173 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8174 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8175 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8176 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8177 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8178 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8180 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8181 || i
.tm
.cpu_flags
.bitfield
.cpu287
8182 || i
.tm
.cpu_flags
.bitfield
.cpu387
8183 || i
.tm
.cpu_flags
.bitfield
.cpu687
8184 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8185 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8186 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8187 Xfence instructions. */
8188 if (i
.tm
.base_opcode
!= 0xf18
8189 && i
.tm
.base_opcode
!= 0xf0d
8190 && i
.tm
.base_opcode
!= 0xfae
8192 || i
.tm
.cpu_flags
.bitfield
.cpummx
8193 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8194 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8195 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8197 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8199 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8201 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8202 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8203 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8204 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8205 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8206 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8207 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8208 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8209 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8213 /* Tie dwarf2 debug info to the address at the start of the insn.
8214 We can't do this after the insn has been output as the current
8215 frag may have been closed off. eg. by frag_var. */
8216 dwarf2_emit_insn (0);
8218 insn_start_frag
= frag_now
;
8219 insn_start_off
= frag_now_fix ();
8222 if (i
.tm
.opcode_modifier
.jump
)
8224 else if (i
.tm
.opcode_modifier
.jumpbyte
8225 || i
.tm
.opcode_modifier
.jumpdword
)
8227 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8228 output_interseg_jump ();
8231 /* Output normal instructions here. */
8235 unsigned int prefix
;
8238 && i
.tm
.base_opcode
== 0xfae
8240 && i
.imm_operands
== 1
8241 && (i
.op
[0].imms
->X_add_number
== 0xe8
8242 || i
.op
[0].imms
->X_add_number
== 0xf0
8243 || i
.op
[0].imms
->X_add_number
== 0xf8))
8245 /* Encode lfence, mfence, and sfence as
8246 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8247 offsetT val
= 0x240483f0ULL
;
8249 md_number_to_chars (p
, val
, 5);
8253 /* Some processors fail on LOCK prefix. This options makes
8254 assembler ignore LOCK prefix and serves as a workaround. */
8255 if (omit_lock_prefix
)
8257 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8259 i
.prefix
[LOCK_PREFIX
] = 0;
8262 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8263 don't need the explicit prefix. */
8264 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8266 switch (i
.tm
.opcode_length
)
8269 if (i
.tm
.base_opcode
& 0xff000000)
8271 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8272 add_prefix (prefix
);
8276 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8278 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8279 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8280 || prefix
!= REPE_PREFIX_OPCODE
8281 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8282 add_prefix (prefix
);
8288 /* Check for pseudo prefixes. */
8289 as_bad_where (insn_start_frag
->fr_file
,
8290 insn_start_frag
->fr_line
,
8291 _("pseudo prefix without instruction"));
8297 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8298 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8299 R_X86_64_GOTTPOFF relocation so that linker can safely
8300 perform IE->LE optimization. */
8301 if (x86_elf_abi
== X86_64_X32_ABI
8303 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8304 && i
.prefix
[REX_PREFIX
] == 0)
8305 add_prefix (REX_OPCODE
);
8308 /* The prefix bytes. */
8309 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8311 FRAG_APPEND_1_CHAR (*q
);
8315 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8320 /* REX byte is encoded in VEX prefix. */
8324 FRAG_APPEND_1_CHAR (*q
);
8327 /* There should be no other prefixes for instructions
8332 /* For EVEX instructions i.vrex should become 0 after
8333 build_evex_prefix. For VEX instructions upper 16 registers
8334 aren't available, so VREX should be 0. */
8337 /* Now the VEX prefix. */
8338 p
= frag_more (i
.vex
.length
);
8339 for (j
= 0; j
< i
.vex
.length
; j
++)
8340 p
[j
] = i
.vex
.bytes
[j
];
8343 /* Now the opcode; be careful about word order here! */
8344 if (i
.tm
.opcode_length
== 1)
8346 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8350 switch (i
.tm
.opcode_length
)
8354 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8355 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8359 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8369 /* Put out high byte first: can't use md_number_to_chars! */
8370 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8371 *p
= i
.tm
.base_opcode
& 0xff;
8374 /* Now the modrm byte and sib byte (if present). */
8375 if (i
.tm
.opcode_modifier
.modrm
)
8377 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8380 /* If i.rm.regmem == ESP (4)
8381 && i.rm.mode != (Register mode)
8383 ==> need second modrm byte. */
8384 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8386 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8387 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8389 | i
.sib
.scale
<< 6));
8392 if (i
.disp_operands
)
8393 output_disp (insn_start_frag
, insn_start_off
);
8396 output_imm (insn_start_frag
, insn_start_off
);
8402 pi ("" /*line*/, &i
);
8404 #endif /* DEBUG386 */
8407 /* Return the size of the displacement operand N. */
8410 disp_size (unsigned int n
)
8414 if (i
.types
[n
].bitfield
.disp64
)
8416 else if (i
.types
[n
].bitfield
.disp8
)
8418 else if (i
.types
[n
].bitfield
.disp16
)
8423 /* Return the size of the immediate operand N. */
8426 imm_size (unsigned int n
)
8429 if (i
.types
[n
].bitfield
.imm64
)
8431 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8433 else if (i
.types
[n
].bitfield
.imm16
)
8439 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8444 for (n
= 0; n
< i
.operands
; n
++)
8446 if (operand_type_check (i
.types
[n
], disp
))
8448 if (i
.op
[n
].disps
->X_op
== O_constant
)
8450 int size
= disp_size (n
);
8451 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8453 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8455 p
= frag_more (size
);
8456 md_number_to_chars (p
, val
, size
);
8460 enum bfd_reloc_code_real reloc_type
;
8461 int size
= disp_size (n
);
8462 int sign
= i
.types
[n
].bitfield
.disp32s
;
8463 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8466 /* We can't have 8 bit displacement here. */
8467 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8469 /* The PC relative address is computed relative
8470 to the instruction boundary, so in case immediate
8471 fields follows, we need to adjust the value. */
8472 if (pcrel
&& i
.imm_operands
)
8477 for (n1
= 0; n1
< i
.operands
; n1
++)
8478 if (operand_type_check (i
.types
[n1
], imm
))
8480 /* Only one immediate is allowed for PC
8481 relative address. */
8482 gas_assert (sz
== 0);
8484 i
.op
[n
].disps
->X_add_number
-= sz
;
8486 /* We should find the immediate. */
8487 gas_assert (sz
!= 0);
8490 p
= frag_more (size
);
8491 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8493 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8494 && (((reloc_type
== BFD_RELOC_32
8495 || reloc_type
== BFD_RELOC_X86_64_32S
8496 || (reloc_type
== BFD_RELOC_64
8498 && (i
.op
[n
].disps
->X_op
== O_symbol
8499 || (i
.op
[n
].disps
->X_op
== O_add
8500 && ((symbol_get_value_expression
8501 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8503 || reloc_type
== BFD_RELOC_32_PCREL
))
8507 if (insn_start_frag
== frag_now
)
8508 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8513 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8514 for (fr
= insn_start_frag
->fr_next
;
8515 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8517 add
+= p
- frag_now
->fr_literal
;
8522 reloc_type
= BFD_RELOC_386_GOTPC
;
8523 i
.op
[n
].imms
->X_add_number
+= add
;
8525 else if (reloc_type
== BFD_RELOC_64
)
8526 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8528 /* Don't do the adjustment for x86-64, as there
8529 the pcrel addressing is relative to the _next_
8530 insn, and that is taken care of in other code. */
8531 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8533 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8534 size
, i
.op
[n
].disps
, pcrel
,
8536 /* Check for "call/jmp *mem", "mov mem, %reg",
8537 "test %reg, mem" and "binop mem, %reg" where binop
8538 is one of adc, add, and, cmp, or, sbb, sub, xor
8539 instructions without data prefix. Always generate
8540 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8541 if (i
.prefix
[DATA_PREFIX
] == 0
8542 && (generate_relax_relocations
8545 && i
.rm
.regmem
== 5))
8547 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8548 && ((i
.operands
== 1
8549 && i
.tm
.base_opcode
== 0xff
8550 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8552 && (i
.tm
.base_opcode
== 0x8b
8553 || i
.tm
.base_opcode
== 0x85
8554 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8558 fixP
->fx_tcbit
= i
.rex
!= 0;
8560 && (i
.base_reg
->reg_num
== RegIP
))
8561 fixP
->fx_tcbit2
= 1;
8564 fixP
->fx_tcbit2
= 1;
8572 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8577 for (n
= 0; n
< i
.operands
; n
++)
8579 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8580 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8583 if (operand_type_check (i
.types
[n
], imm
))
8585 if (i
.op
[n
].imms
->X_op
== O_constant
)
8587 int size
= imm_size (n
);
8590 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8592 p
= frag_more (size
);
8593 md_number_to_chars (p
, val
, size
);
8597 /* Not absolute_section.
8598 Need a 32-bit fixup (don't support 8bit
8599 non-absolute imms). Try to support other
8601 enum bfd_reloc_code_real reloc_type
;
8602 int size
= imm_size (n
);
8605 if (i
.types
[n
].bitfield
.imm32s
8606 && (i
.suffix
== QWORD_MNEM_SUFFIX
8607 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8612 p
= frag_more (size
);
8613 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8615 /* This is tough to explain. We end up with this one if we
8616 * have operands that look like
8617 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8618 * obtain the absolute address of the GOT, and it is strongly
8619 * preferable from a performance point of view to avoid using
8620 * a runtime relocation for this. The actual sequence of
8621 * instructions often look something like:
8626 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8628 * The call and pop essentially return the absolute address
8629 * of the label .L66 and store it in %ebx. The linker itself
8630 * will ultimately change the first operand of the addl so
8631 * that %ebx points to the GOT, but to keep things simple, the
8632 * .o file must have this operand set so that it generates not
8633 * the absolute address of .L66, but the absolute address of
8634 * itself. This allows the linker itself simply treat a GOTPC
8635 * relocation as asking for a pcrel offset to the GOT to be
8636 * added in, and the addend of the relocation is stored in the
8637 * operand field for the instruction itself.
8639 * Our job here is to fix the operand so that it would add
8640 * the correct offset so that %ebx would point to itself. The
8641 * thing that is tricky is that .-.L66 will point to the
8642 * beginning of the instruction, so we need to further modify
8643 * the operand so that it will point to itself. There are
8644 * other cases where you have something like:
8646 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8648 * and here no correction would be required. Internally in
8649 * the assembler we treat operands of this form as not being
8650 * pcrel since the '.' is explicitly mentioned, and I wonder
8651 * whether it would simplify matters to do it this way. Who
8652 * knows. In earlier versions of the PIC patches, the
8653 * pcrel_adjust field was used to store the correction, but
8654 * since the expression is not pcrel, I felt it would be
8655 * confusing to do it this way. */
8657 if ((reloc_type
== BFD_RELOC_32
8658 || reloc_type
== BFD_RELOC_X86_64_32S
8659 || reloc_type
== BFD_RELOC_64
)
8661 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8662 && (i
.op
[n
].imms
->X_op
== O_symbol
8663 || (i
.op
[n
].imms
->X_op
== O_add
8664 && ((symbol_get_value_expression
8665 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8670 if (insn_start_frag
== frag_now
)
8671 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8676 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8677 for (fr
= insn_start_frag
->fr_next
;
8678 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8680 add
+= p
- frag_now
->fr_literal
;
8684 reloc_type
= BFD_RELOC_386_GOTPC
;
8686 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8688 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8689 i
.op
[n
].imms
->X_add_number
+= add
;
8691 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8692 i
.op
[n
].imms
, 0, reloc_type
);
8698 /* x86_cons_fix_new is called via the expression parsing code when a
8699 reloc is needed. We use this hook to get the correct .got reloc. */
8700 static int cons_sign
= -1;
8703 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8704 expressionS
*exp
, bfd_reloc_code_real_type r
)
8706 r
= reloc (len
, 0, cons_sign
, r
);
8709 if (exp
->X_op
== O_secrel
)
8711 exp
->X_op
= O_symbol
;
8712 r
= BFD_RELOC_32_SECREL
;
8716 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8719 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8720 purpose of the `.dc.a' internal pseudo-op. */
8723 x86_address_bytes (void)
8725 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8727 return stdoutput
->arch_info
->bits_per_address
/ 8;
8730 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8732 # define lex_got(reloc, adjust, types) NULL
8734 /* Parse operands of the form
8735 <symbol>@GOTOFF+<nnn>
8736 and similar .plt or .got references.
8738 If we find one, set up the correct relocation in RELOC and copy the
8739 input string, minus the `@GOTOFF' into a malloc'd buffer for
8740 parsing by the calling routine. Return this buffer, and if ADJUST
8741 is non-null set it to the length of the string we removed from the
8742 input line. Otherwise return NULL. */
8744 lex_got (enum bfd_reloc_code_real
*rel
,
8746 i386_operand_type
*types
)
8748 /* Some of the relocations depend on the size of what field is to
8749 be relocated. But in our callers i386_immediate and i386_displacement
8750 we don't yet know the operand size (this will be set by insn
8751 matching). Hence we record the word32 relocation here,
8752 and adjust the reloc according to the real size in reloc(). */
8753 static const struct {
8756 const enum bfd_reloc_code_real rel
[2];
8757 const i386_operand_type types64
;
8759 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8760 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8762 OPERAND_TYPE_IMM32_64
},
8764 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8765 BFD_RELOC_X86_64_PLTOFF64
},
8766 OPERAND_TYPE_IMM64
},
8767 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8768 BFD_RELOC_X86_64_PLT32
},
8769 OPERAND_TYPE_IMM32_32S_DISP32
},
8770 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8771 BFD_RELOC_X86_64_GOTPLT64
},
8772 OPERAND_TYPE_IMM64_DISP64
},
8773 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8774 BFD_RELOC_X86_64_GOTOFF64
},
8775 OPERAND_TYPE_IMM64_DISP64
},
8776 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8777 BFD_RELOC_X86_64_GOTPCREL
},
8778 OPERAND_TYPE_IMM32_32S_DISP32
},
8779 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8780 BFD_RELOC_X86_64_TLSGD
},
8781 OPERAND_TYPE_IMM32_32S_DISP32
},
8782 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8783 _dummy_first_bfd_reloc_code_real
},
8784 OPERAND_TYPE_NONE
},
8785 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8786 BFD_RELOC_X86_64_TLSLD
},
8787 OPERAND_TYPE_IMM32_32S_DISP32
},
8788 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8789 BFD_RELOC_X86_64_GOTTPOFF
},
8790 OPERAND_TYPE_IMM32_32S_DISP32
},
8791 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8792 BFD_RELOC_X86_64_TPOFF32
},
8793 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8794 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8795 _dummy_first_bfd_reloc_code_real
},
8796 OPERAND_TYPE_NONE
},
8797 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8798 BFD_RELOC_X86_64_DTPOFF32
},
8799 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8800 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8801 _dummy_first_bfd_reloc_code_real
},
8802 OPERAND_TYPE_NONE
},
8803 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8804 _dummy_first_bfd_reloc_code_real
},
8805 OPERAND_TYPE_NONE
},
8806 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8807 BFD_RELOC_X86_64_GOT32
},
8808 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8809 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8810 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8811 OPERAND_TYPE_IMM32_32S_DISP32
},
8812 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8813 BFD_RELOC_X86_64_TLSDESC_CALL
},
8814 OPERAND_TYPE_IMM32_32S_DISP32
},
8819 #if defined (OBJ_MAYBE_ELF)
8824 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8825 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8828 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8830 int len
= gotrel
[j
].len
;
8831 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8833 if (gotrel
[j
].rel
[object_64bit
] != 0)
8836 char *tmpbuf
, *past_reloc
;
8838 *rel
= gotrel
[j
].rel
[object_64bit
];
8842 if (flag_code
!= CODE_64BIT
)
8844 types
->bitfield
.imm32
= 1;
8845 types
->bitfield
.disp32
= 1;
8848 *types
= gotrel
[j
].types64
;
8851 if (j
!= 0 && GOT_symbol
== NULL
)
8852 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8854 /* The length of the first part of our input line. */
8855 first
= cp
- input_line_pointer
;
8857 /* The second part goes from after the reloc token until
8858 (and including) an end_of_line char or comma. */
8859 past_reloc
= cp
+ 1 + len
;
8861 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8863 second
= cp
+ 1 - past_reloc
;
8865 /* Allocate and copy string. The trailing NUL shouldn't
8866 be necessary, but be safe. */
8867 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8868 memcpy (tmpbuf
, input_line_pointer
, first
);
8869 if (second
!= 0 && *past_reloc
!= ' ')
8870 /* Replace the relocation token with ' ', so that
8871 errors like foo@GOTOFF1 will be detected. */
8872 tmpbuf
[first
++] = ' ';
8874 /* Increment length by 1 if the relocation token is
8879 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8880 tmpbuf
[first
+ second
] = '\0';
8884 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8885 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8890 /* Might be a symbol version string. Don't as_bad here. */
8899 /* Parse operands of the form
8900 <symbol>@SECREL32+<nnn>
8902 If we find one, set up the correct relocation in RELOC and copy the
8903 input string, minus the `@SECREL32' into a malloc'd buffer for
8904 parsing by the calling routine. Return this buffer, and if ADJUST
8905 is non-null set it to the length of the string we removed from the
8906 input line. Otherwise return NULL.
8908 This function is copied from the ELF version above adjusted for PE targets. */
8911 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8912 int *adjust ATTRIBUTE_UNUSED
,
8913 i386_operand_type
*types
)
8919 const enum bfd_reloc_code_real rel
[2];
8920 const i386_operand_type types64
;
8924 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8925 BFD_RELOC_32_SECREL
},
8926 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8932 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8933 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8936 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8938 int len
= gotrel
[j
].len
;
8940 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8942 if (gotrel
[j
].rel
[object_64bit
] != 0)
8945 char *tmpbuf
, *past_reloc
;
8947 *rel
= gotrel
[j
].rel
[object_64bit
];
8953 if (flag_code
!= CODE_64BIT
)
8955 types
->bitfield
.imm32
= 1;
8956 types
->bitfield
.disp32
= 1;
8959 *types
= gotrel
[j
].types64
;
8962 /* The length of the first part of our input line. */
8963 first
= cp
- input_line_pointer
;
8965 /* The second part goes from after the reloc token until
8966 (and including) an end_of_line char or comma. */
8967 past_reloc
= cp
+ 1 + len
;
8969 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8971 second
= cp
+ 1 - past_reloc
;
8973 /* Allocate and copy string. The trailing NUL shouldn't
8974 be necessary, but be safe. */
8975 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8976 memcpy (tmpbuf
, input_line_pointer
, first
);
8977 if (second
!= 0 && *past_reloc
!= ' ')
8978 /* Replace the relocation token with ' ', so that
8979 errors like foo@SECLREL321 will be detected. */
8980 tmpbuf
[first
++] = ' ';
8981 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8982 tmpbuf
[first
+ second
] = '\0';
8986 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8987 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8992 /* Might be a symbol version string. Don't as_bad here. */
8998 bfd_reloc_code_real_type
8999 x86_cons (expressionS
*exp
, int size
)
9001 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9003 intel_syntax
= -intel_syntax
;
9006 if (size
== 4 || (object_64bit
&& size
== 8))
9008 /* Handle @GOTOFF and the like in an expression. */
9010 char *gotfree_input_line
;
9013 save
= input_line_pointer
;
9014 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9015 if (gotfree_input_line
)
9016 input_line_pointer
= gotfree_input_line
;
9020 if (gotfree_input_line
)
9022 /* expression () has merrily parsed up to the end of line,
9023 or a comma - in the wrong buffer. Transfer how far
9024 input_line_pointer has moved to the right buffer. */
9025 input_line_pointer
= (save
9026 + (input_line_pointer
- gotfree_input_line
)
9028 free (gotfree_input_line
);
9029 if (exp
->X_op
== O_constant
9030 || exp
->X_op
== O_absent
9031 || exp
->X_op
== O_illegal
9032 || exp
->X_op
== O_register
9033 || exp
->X_op
== O_big
)
9035 char c
= *input_line_pointer
;
9036 *input_line_pointer
= 0;
9037 as_bad (_("missing or invalid expression `%s'"), save
);
9038 *input_line_pointer
= c
;
9040 else if ((got_reloc
== BFD_RELOC_386_PLT32
9041 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9042 && exp
->X_op
!= O_symbol
)
9044 char c
= *input_line_pointer
;
9045 *input_line_pointer
= 0;
9046 as_bad (_("invalid PLT expression `%s'"), save
);
9047 *input_line_pointer
= c
;
9054 intel_syntax
= -intel_syntax
;
9057 i386_intel_simplify (exp
);
9063 signed_cons (int size
)
9065 if (flag_code
== CODE_64BIT
)
9073 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9080 if (exp
.X_op
== O_symbol
)
9081 exp
.X_op
= O_secrel
;
9083 emit_expr (&exp
, 4);
9085 while (*input_line_pointer
++ == ',');
9087 input_line_pointer
--;
9088 demand_empty_rest_of_line ();
9092 /* Handle Vector operations. */
9095 check_VecOperations (char *op_string
, char *op_end
)
9097 const reg_entry
*mask
;
9102 && (op_end
== NULL
|| op_string
< op_end
))
9105 if (*op_string
== '{')
9109 /* Check broadcasts. */
9110 if (strncmp (op_string
, "1to", 3) == 0)
9115 goto duplicated_vec_op
;
9118 if (*op_string
== '8')
9120 else if (*op_string
== '4')
9122 else if (*op_string
== '2')
9124 else if (*op_string
== '1'
9125 && *(op_string
+1) == '6')
9132 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9137 broadcast_op
.type
= bcst_type
;
9138 broadcast_op
.operand
= this_operand
;
9139 broadcast_op
.bytes
= 0;
9140 i
.broadcast
= &broadcast_op
;
9142 /* Check masking operation. */
9143 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9145 /* k0 can't be used for write mask. */
9146 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9148 as_bad (_("`%s%s' can't be used for write mask"),
9149 register_prefix
, mask
->reg_name
);
9155 mask_op
.mask
= mask
;
9156 mask_op
.zeroing
= 0;
9157 mask_op
.operand
= this_operand
;
9163 goto duplicated_vec_op
;
9165 i
.mask
->mask
= mask
;
9167 /* Only "{z}" is allowed here. No need to check
9168 zeroing mask explicitly. */
9169 if (i
.mask
->operand
!= this_operand
)
9171 as_bad (_("invalid write mask `%s'"), saved
);
9178 /* Check zeroing-flag for masking operation. */
9179 else if (*op_string
== 'z')
9183 mask_op
.mask
= NULL
;
9184 mask_op
.zeroing
= 1;
9185 mask_op
.operand
= this_operand
;
9190 if (i
.mask
->zeroing
)
9193 as_bad (_("duplicated `%s'"), saved
);
9197 i
.mask
->zeroing
= 1;
9199 /* Only "{%k}" is allowed here. No need to check mask
9200 register explicitly. */
9201 if (i
.mask
->operand
!= this_operand
)
9203 as_bad (_("invalid zeroing-masking `%s'"),
9212 goto unknown_vec_op
;
9214 if (*op_string
!= '}')
9216 as_bad (_("missing `}' in `%s'"), saved
);
9221 /* Strip whitespace since the addition of pseudo prefixes
9222 changed how the scrubber treats '{'. */
9223 if (is_space_char (*op_string
))
9229 /* We don't know this one. */
9230 as_bad (_("unknown vector operation: `%s'"), saved
);
9234 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9236 as_bad (_("zeroing-masking only allowed with write mask"));
9244 i386_immediate (char *imm_start
)
9246 char *save_input_line_pointer
;
9247 char *gotfree_input_line
;
9250 i386_operand_type types
;
9252 operand_type_set (&types
, ~0);
9254 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9256 as_bad (_("at most %d immediate operands are allowed"),
9257 MAX_IMMEDIATE_OPERANDS
);
9261 exp
= &im_expressions
[i
.imm_operands
++];
9262 i
.op
[this_operand
].imms
= exp
;
9264 if (is_space_char (*imm_start
))
9267 save_input_line_pointer
= input_line_pointer
;
9268 input_line_pointer
= imm_start
;
9270 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9271 if (gotfree_input_line
)
9272 input_line_pointer
= gotfree_input_line
;
9274 exp_seg
= expression (exp
);
9278 /* Handle vector operations. */
9279 if (*input_line_pointer
== '{')
9281 input_line_pointer
= check_VecOperations (input_line_pointer
,
9283 if (input_line_pointer
== NULL
)
9287 if (*input_line_pointer
)
9288 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9290 input_line_pointer
= save_input_line_pointer
;
9291 if (gotfree_input_line
)
9293 free (gotfree_input_line
);
9295 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9296 exp
->X_op
= O_illegal
;
9299 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9303 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9304 i386_operand_type types
, const char *imm_start
)
9306 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9309 as_bad (_("missing or invalid immediate expression `%s'"),
9313 else if (exp
->X_op
== O_constant
)
9315 /* Size it properly later. */
9316 i
.types
[this_operand
].bitfield
.imm64
= 1;
9317 /* If not 64bit, sign extend val. */
9318 if (flag_code
!= CODE_64BIT
9319 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9321 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9323 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9324 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9325 && exp_seg
!= absolute_section
9326 && exp_seg
!= text_section
9327 && exp_seg
!= data_section
9328 && exp_seg
!= bss_section
9329 && exp_seg
!= undefined_section
9330 && !bfd_is_com_section (exp_seg
))
9332 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9336 else if (!intel_syntax
&& exp_seg
== reg_section
)
9339 as_bad (_("illegal immediate register operand %s"), imm_start
);
9344 /* This is an address. The size of the address will be
9345 determined later, depending on destination register,
9346 suffix, or the default for the section. */
9347 i
.types
[this_operand
].bitfield
.imm8
= 1;
9348 i
.types
[this_operand
].bitfield
.imm16
= 1;
9349 i
.types
[this_operand
].bitfield
.imm32
= 1;
9350 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9351 i
.types
[this_operand
].bitfield
.imm64
= 1;
9352 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9360 i386_scale (char *scale
)
9363 char *save
= input_line_pointer
;
9365 input_line_pointer
= scale
;
9366 val
= get_absolute_expression ();
9371 i
.log2_scale_factor
= 0;
9374 i
.log2_scale_factor
= 1;
9377 i
.log2_scale_factor
= 2;
9380 i
.log2_scale_factor
= 3;
9384 char sep
= *input_line_pointer
;
9386 *input_line_pointer
= '\0';
9387 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9389 *input_line_pointer
= sep
;
9390 input_line_pointer
= save
;
9394 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9396 as_warn (_("scale factor of %d without an index register"),
9397 1 << i
.log2_scale_factor
);
9398 i
.log2_scale_factor
= 0;
9400 scale
= input_line_pointer
;
9401 input_line_pointer
= save
;
9406 i386_displacement (char *disp_start
, char *disp_end
)
9410 char *save_input_line_pointer
;
9411 char *gotfree_input_line
;
9413 i386_operand_type bigdisp
, types
= anydisp
;
9416 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9418 as_bad (_("at most %d displacement operands are allowed"),
9419 MAX_MEMORY_OPERANDS
);
9423 operand_type_set (&bigdisp
, 0);
9424 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9425 || (!current_templates
->start
->opcode_modifier
.jump
9426 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9428 bigdisp
.bitfield
.disp32
= 1;
9429 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9430 if (flag_code
== CODE_64BIT
)
9434 bigdisp
.bitfield
.disp32s
= 1;
9435 bigdisp
.bitfield
.disp64
= 1;
9438 else if ((flag_code
== CODE_16BIT
) ^ override
)
9440 bigdisp
.bitfield
.disp32
= 0;
9441 bigdisp
.bitfield
.disp16
= 1;
9446 /* For PC-relative branches, the width of the displacement
9447 is dependent upon data size, not address size. */
9448 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9449 if (flag_code
== CODE_64BIT
)
9451 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9452 bigdisp
.bitfield
.disp16
= 1;
9455 bigdisp
.bitfield
.disp32
= 1;
9456 bigdisp
.bitfield
.disp32s
= 1;
9462 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9464 : LONG_MNEM_SUFFIX
));
9465 bigdisp
.bitfield
.disp32
= 1;
9466 if ((flag_code
== CODE_16BIT
) ^ override
)
9468 bigdisp
.bitfield
.disp32
= 0;
9469 bigdisp
.bitfield
.disp16
= 1;
9473 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9476 exp
= &disp_expressions
[i
.disp_operands
];
9477 i
.op
[this_operand
].disps
= exp
;
9479 save_input_line_pointer
= input_line_pointer
;
9480 input_line_pointer
= disp_start
;
9481 END_STRING_AND_SAVE (disp_end
);
9483 #ifndef GCC_ASM_O_HACK
9484 #define GCC_ASM_O_HACK 0
9487 END_STRING_AND_SAVE (disp_end
+ 1);
9488 if (i
.types
[this_operand
].bitfield
.baseIndex
9489 && displacement_string_end
[-1] == '+')
9491 /* This hack is to avoid a warning when using the "o"
9492 constraint within gcc asm statements.
9495 #define _set_tssldt_desc(n,addr,limit,type) \
9496 __asm__ __volatile__ ( \
9498 "movw %w1,2+%0\n\t" \
9500 "movb %b1,4+%0\n\t" \
9501 "movb %4,5+%0\n\t" \
9502 "movb $0,6+%0\n\t" \
9503 "movb %h1,7+%0\n\t" \
9505 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9507 This works great except that the output assembler ends
9508 up looking a bit weird if it turns out that there is
9509 no offset. You end up producing code that looks like:
9522 So here we provide the missing zero. */
9524 *displacement_string_end
= '0';
9527 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9528 if (gotfree_input_line
)
9529 input_line_pointer
= gotfree_input_line
;
9531 exp_seg
= expression (exp
);
9534 if (*input_line_pointer
)
9535 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9537 RESTORE_END_STRING (disp_end
+ 1);
9539 input_line_pointer
= save_input_line_pointer
;
9540 if (gotfree_input_line
)
9542 free (gotfree_input_line
);
9544 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9545 exp
->X_op
= O_illegal
;
9548 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9550 RESTORE_END_STRING (disp_end
);
9556 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9557 i386_operand_type types
, const char *disp_start
)
9559 i386_operand_type bigdisp
;
9562 /* We do this to make sure that the section symbol is in
9563 the symbol table. We will ultimately change the relocation
9564 to be relative to the beginning of the section. */
9565 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9566 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9567 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9569 if (exp
->X_op
!= O_symbol
)
9572 if (S_IS_LOCAL (exp
->X_add_symbol
)
9573 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9574 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9575 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9576 exp
->X_op
= O_subtract
;
9577 exp
->X_op_symbol
= GOT_symbol
;
9578 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9579 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9580 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9581 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9583 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9586 else if (exp
->X_op
== O_absent
9587 || exp
->X_op
== O_illegal
9588 || exp
->X_op
== O_big
)
9591 as_bad (_("missing or invalid displacement expression `%s'"),
9596 else if (flag_code
== CODE_64BIT
9597 && !i
.prefix
[ADDR_PREFIX
]
9598 && exp
->X_op
== O_constant
)
9600 /* Since displacement is signed extended to 64bit, don't allow
9601 disp32 and turn off disp32s if they are out of range. */
9602 i
.types
[this_operand
].bitfield
.disp32
= 0;
9603 if (!fits_in_signed_long (exp
->X_add_number
))
9605 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9606 if (i
.types
[this_operand
].bitfield
.baseindex
)
9608 as_bad (_("0x%lx out range of signed 32bit displacement"),
9609 (long) exp
->X_add_number
);
9615 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9616 else if (exp
->X_op
!= O_constant
9617 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9618 && exp_seg
!= absolute_section
9619 && exp_seg
!= text_section
9620 && exp_seg
!= data_section
9621 && exp_seg
!= bss_section
9622 && exp_seg
!= undefined_section
9623 && !bfd_is_com_section (exp_seg
))
9625 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9630 /* Check if this is a displacement only operand. */
9631 bigdisp
= i
.types
[this_operand
];
9632 bigdisp
.bitfield
.disp8
= 0;
9633 bigdisp
.bitfield
.disp16
= 0;
9634 bigdisp
.bitfield
.disp32
= 0;
9635 bigdisp
.bitfield
.disp32s
= 0;
9636 bigdisp
.bitfield
.disp64
= 0;
9637 if (operand_type_all_zero (&bigdisp
))
9638 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9644 /* Return the active addressing mode, taking address override and
9645 registers forming the address into consideration. Update the
9646 address override prefix if necessary. */
9648 static enum flag_code
9649 i386_addressing_mode (void)
9651 enum flag_code addr_mode
;
9653 if (i
.prefix
[ADDR_PREFIX
])
9654 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9657 addr_mode
= flag_code
;
9659 #if INFER_ADDR_PREFIX
9660 if (i
.mem_operands
== 0)
9662 /* Infer address prefix from the first memory operand. */
9663 const reg_entry
*addr_reg
= i
.base_reg
;
9665 if (addr_reg
== NULL
)
9666 addr_reg
= i
.index_reg
;
9670 if (addr_reg
->reg_type
.bitfield
.dword
)
9671 addr_mode
= CODE_32BIT
;
9672 else if (flag_code
!= CODE_64BIT
9673 && addr_reg
->reg_type
.bitfield
.word
)
9674 addr_mode
= CODE_16BIT
;
9676 if (addr_mode
!= flag_code
)
9678 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9680 /* Change the size of any displacement too. At most one
9681 of Disp16 or Disp32 is set.
9682 FIXME. There doesn't seem to be any real need for
9683 separate Disp16 and Disp32 flags. The same goes for
9684 Imm16 and Imm32. Removing them would probably clean
9685 up the code quite a lot. */
9686 if (flag_code
!= CODE_64BIT
9687 && (i
.types
[this_operand
].bitfield
.disp16
9688 || i
.types
[this_operand
].bitfield
.disp32
))
9689 i
.types
[this_operand
]
9690 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9700 /* Make sure the memory operand we've been dealt is valid.
9701 Return 1 on success, 0 on a failure. */
9704 i386_index_check (const char *operand_string
)
9706 const char *kind
= "base/index";
9707 enum flag_code addr_mode
= i386_addressing_mode ();
9709 if (current_templates
->start
->opcode_modifier
.isstring
9710 && !current_templates
->start
->opcode_modifier
.immext
9711 && (current_templates
->end
[-1].opcode_modifier
.isstring
9714 /* Memory operands of string insns are special in that they only allow
9715 a single register (rDI, rSI, or rBX) as their memory address. */
9716 const reg_entry
*expected_reg
;
9717 static const char *di_si
[][2] =
9723 static const char *bx
[] = { "ebx", "bx", "rbx" };
9725 kind
= "string address";
9727 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9729 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9731 if (!type
.bitfield
.baseindex
9732 || ((!i
.mem_operands
!= !intel_syntax
)
9733 && current_templates
->end
[-1].operand_types
[1]
9734 .bitfield
.baseindex
))
9735 type
= current_templates
->end
[-1].operand_types
[1];
9736 expected_reg
= hash_find (reg_hash
,
9737 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9741 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9743 if (i
.base_reg
!= expected_reg
9745 || operand_type_check (i
.types
[this_operand
], disp
))
9747 /* The second memory operand must have the same size as
9751 && !((addr_mode
== CODE_64BIT
9752 && i
.base_reg
->reg_type
.bitfield
.qword
)
9753 || (addr_mode
== CODE_32BIT
9754 ? i
.base_reg
->reg_type
.bitfield
.dword
9755 : i
.base_reg
->reg_type
.bitfield
.word
)))
9758 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9760 intel_syntax
? '[' : '(',
9762 expected_reg
->reg_name
,
9763 intel_syntax
? ']' : ')');
9770 as_bad (_("`%s' is not a valid %s expression"),
9771 operand_string
, kind
);
9776 if (addr_mode
!= CODE_16BIT
)
9778 /* 32-bit/64-bit checks. */
9780 && ((addr_mode
== CODE_64BIT
9781 ? !i
.base_reg
->reg_type
.bitfield
.qword
9782 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9783 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9784 || i
.base_reg
->reg_num
== RegIZ
))
9786 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9787 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9788 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9789 && ((addr_mode
== CODE_64BIT
9790 ? !i
.index_reg
->reg_type
.bitfield
.qword
9791 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9792 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9795 /* bndmk, bndldx, and bndstx have special restrictions. */
9796 if (current_templates
->start
->base_opcode
== 0xf30f1b
9797 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9799 /* They cannot use RIP-relative addressing. */
9800 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9802 as_bad (_("`%s' cannot be used here"), operand_string
);
9806 /* bndldx and bndstx ignore their scale factor. */
9807 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9808 && i
.log2_scale_factor
)
9809 as_warn (_("register scaling is being ignored here"));
9814 /* 16-bit checks. */
9816 && (!i
.base_reg
->reg_type
.bitfield
.word
9817 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9819 && (!i
.index_reg
->reg_type
.bitfield
.word
9820 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9822 && i
.base_reg
->reg_num
< 6
9823 && i
.index_reg
->reg_num
>= 6
9824 && i
.log2_scale_factor
== 0))))
9831 /* Handle vector immediates. */
9834 RC_SAE_immediate (const char *imm_start
)
9836 unsigned int match_found
, j
;
9837 const char *pstr
= imm_start
;
9845 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9847 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9851 rc_op
.type
= RC_NamesTable
[j
].type
;
9852 rc_op
.operand
= this_operand
;
9853 i
.rounding
= &rc_op
;
9857 as_bad (_("duplicated `%s'"), imm_start
);
9860 pstr
+= RC_NamesTable
[j
].len
;
9870 as_bad (_("Missing '}': '%s'"), imm_start
);
9873 /* RC/SAE immediate string should contain nothing more. */;
9876 as_bad (_("Junk after '}': '%s'"), imm_start
);
9880 exp
= &im_expressions
[i
.imm_operands
++];
9881 i
.op
[this_operand
].imms
= exp
;
9883 exp
->X_op
= O_constant
;
9884 exp
->X_add_number
= 0;
9885 exp
->X_add_symbol
= (symbolS
*) 0;
9886 exp
->X_op_symbol
= (symbolS
*) 0;
9888 i
.types
[this_operand
].bitfield
.imm8
= 1;
9892 /* Only string instructions can have a second memory operand, so
9893 reduce current_templates to just those if it contains any. */
9895 maybe_adjust_templates (void)
9897 const insn_template
*t
;
9899 gas_assert (i
.mem_operands
== 1);
9901 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9902 if (t
->opcode_modifier
.isstring
)
9905 if (t
< current_templates
->end
)
9907 static templates aux_templates
;
9908 bfd_boolean recheck
;
9910 aux_templates
.start
= t
;
9911 for (; t
< current_templates
->end
; ++t
)
9912 if (!t
->opcode_modifier
.isstring
)
9914 aux_templates
.end
= t
;
9916 /* Determine whether to re-check the first memory operand. */
9917 recheck
= (aux_templates
.start
!= current_templates
->start
9918 || t
!= current_templates
->end
);
9920 current_templates
= &aux_templates
;
9925 if (i
.memop1_string
!= NULL
9926 && i386_index_check (i
.memop1_string
) == 0)
9935 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9939 i386_att_operand (char *operand_string
)
9943 char *op_string
= operand_string
;
9945 if (is_space_char (*op_string
))
9948 /* We check for an absolute prefix (differentiating,
9949 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9950 if (*op_string
== ABSOLUTE_PREFIX
)
9953 if (is_space_char (*op_string
))
9955 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9958 /* Check if operand is a register. */
9959 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9961 i386_operand_type temp
;
9963 /* Check for a segment override by searching for ':' after a
9964 segment register. */
9966 if (is_space_char (*op_string
))
9968 if (*op_string
== ':'
9969 && (r
->reg_type
.bitfield
.sreg2
9970 || r
->reg_type
.bitfield
.sreg3
))
9975 i
.seg
[i
.mem_operands
] = &es
;
9978 i
.seg
[i
.mem_operands
] = &cs
;
9981 i
.seg
[i
.mem_operands
] = &ss
;
9984 i
.seg
[i
.mem_operands
] = &ds
;
9987 i
.seg
[i
.mem_operands
] = &fs
;
9990 i
.seg
[i
.mem_operands
] = &gs
;
9994 /* Skip the ':' and whitespace. */
9996 if (is_space_char (*op_string
))
9999 if (!is_digit_char (*op_string
)
10000 && !is_identifier_char (*op_string
)
10001 && *op_string
!= '('
10002 && *op_string
!= ABSOLUTE_PREFIX
)
10004 as_bad (_("bad memory operand `%s'"), op_string
);
10007 /* Handle case of %es:*foo. */
10008 if (*op_string
== ABSOLUTE_PREFIX
)
10011 if (is_space_char (*op_string
))
10013 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10015 goto do_memory_reference
;
10018 /* Handle vector operations. */
10019 if (*op_string
== '{')
10021 op_string
= check_VecOperations (op_string
, NULL
);
10022 if (op_string
== NULL
)
10028 as_bad (_("junk `%s' after register"), op_string
);
10031 temp
= r
->reg_type
;
10032 temp
.bitfield
.baseindex
= 0;
10033 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10035 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10036 i
.op
[this_operand
].regs
= r
;
10039 else if (*op_string
== REGISTER_PREFIX
)
10041 as_bad (_("bad register name `%s'"), op_string
);
10044 else if (*op_string
== IMMEDIATE_PREFIX
)
10047 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10049 as_bad (_("immediate operand illegal with absolute jump"));
10052 if (!i386_immediate (op_string
))
10055 else if (RC_SAE_immediate (operand_string
))
10057 /* If it is a RC or SAE immediate, do nothing. */
10060 else if (is_digit_char (*op_string
)
10061 || is_identifier_char (*op_string
)
10062 || *op_string
== '"'
10063 || *op_string
== '(')
10065 /* This is a memory reference of some sort. */
10068 /* Start and end of displacement string expression (if found). */
10069 char *displacement_string_start
;
10070 char *displacement_string_end
;
10073 do_memory_reference
:
10074 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10076 if ((i
.mem_operands
== 1
10077 && !current_templates
->start
->opcode_modifier
.isstring
)
10078 || i
.mem_operands
== 2)
10080 as_bad (_("too many memory references for `%s'"),
10081 current_templates
->start
->name
);
10085 /* Check for base index form. We detect the base index form by
10086 looking for an ')' at the end of the operand, searching
10087 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10089 base_string
= op_string
+ strlen (op_string
);
10091 /* Handle vector operations. */
10092 vop_start
= strchr (op_string
, '{');
10093 if (vop_start
&& vop_start
< base_string
)
10095 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10097 base_string
= vop_start
;
10101 if (is_space_char (*base_string
))
10104 /* If we only have a displacement, set-up for it to be parsed later. */
10105 displacement_string_start
= op_string
;
10106 displacement_string_end
= base_string
+ 1;
10108 if (*base_string
== ')')
10111 unsigned int parens_balanced
= 1;
10112 /* We've already checked that the number of left & right ()'s are
10113 equal, so this loop will not be infinite. */
10117 if (*base_string
== ')')
10119 if (*base_string
== '(')
10122 while (parens_balanced
);
10124 temp_string
= base_string
;
10126 /* Skip past '(' and whitespace. */
10128 if (is_space_char (*base_string
))
10131 if (*base_string
== ','
10132 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10135 displacement_string_end
= temp_string
;
10137 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10141 base_string
= end_op
;
10142 if (is_space_char (*base_string
))
10146 /* There may be an index reg or scale factor here. */
10147 if (*base_string
== ',')
10150 if (is_space_char (*base_string
))
10153 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10156 base_string
= end_op
;
10157 if (is_space_char (*base_string
))
10159 if (*base_string
== ',')
10162 if (is_space_char (*base_string
))
10165 else if (*base_string
!= ')')
10167 as_bad (_("expecting `,' or `)' "
10168 "after index register in `%s'"),
10173 else if (*base_string
== REGISTER_PREFIX
)
10175 end_op
= strchr (base_string
, ',');
10178 as_bad (_("bad register name `%s'"), base_string
);
10182 /* Check for scale factor. */
10183 if (*base_string
!= ')')
10185 char *end_scale
= i386_scale (base_string
);
10190 base_string
= end_scale
;
10191 if (is_space_char (*base_string
))
10193 if (*base_string
!= ')')
10195 as_bad (_("expecting `)' "
10196 "after scale factor in `%s'"),
10201 else if (!i
.index_reg
)
10203 as_bad (_("expecting index register or scale factor "
10204 "after `,'; got '%c'"),
10209 else if (*base_string
!= ')')
10211 as_bad (_("expecting `,' or `)' "
10212 "after base register in `%s'"),
10217 else if (*base_string
== REGISTER_PREFIX
)
10219 end_op
= strchr (base_string
, ',');
10222 as_bad (_("bad register name `%s'"), base_string
);
10227 /* If there's an expression beginning the operand, parse it,
10228 assuming displacement_string_start and
10229 displacement_string_end are meaningful. */
10230 if (displacement_string_start
!= displacement_string_end
)
10232 if (!i386_displacement (displacement_string_start
,
10233 displacement_string_end
))
10237 /* Special case for (%dx) while doing input/output op. */
10239 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10240 && i
.index_reg
== 0
10241 && i
.log2_scale_factor
== 0
10242 && i
.seg
[i
.mem_operands
] == 0
10243 && !operand_type_check (i
.types
[this_operand
], disp
))
10245 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10249 if (i386_index_check (operand_string
) == 0)
10251 i
.flags
[this_operand
] |= Operand_Mem
;
10252 if (i
.mem_operands
== 0)
10253 i
.memop1_string
= xstrdup (operand_string
);
10258 /* It's not a memory operand; argh! */
10259 as_bad (_("invalid char %s beginning operand %d `%s'"),
10260 output_invalid (*op_string
),
10265 return 1; /* Normal return. */
10268 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10269 that an rs_machine_dependent frag may reach. */
10272 i386_frag_max_var (fragS
*frag
)
10274 /* The only relaxable frags are for jumps.
10275 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10276 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10277 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10280 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10282 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10284 /* STT_GNU_IFUNC symbol must go through PLT. */
10285 if ((symbol_get_bfdsym (fr_symbol
)->flags
10286 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10289 if (!S_IS_EXTERNAL (fr_symbol
))
10290 /* Symbol may be weak or local. */
10291 return !S_IS_WEAK (fr_symbol
);
10293 /* Global symbols with non-default visibility can't be preempted. */
10294 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10297 if (fr_var
!= NO_RELOC
)
10298 switch ((enum bfd_reloc_code_real
) fr_var
)
10300 case BFD_RELOC_386_PLT32
:
10301 case BFD_RELOC_X86_64_PLT32
:
10302 /* Symbol with PLT relocation may be preempted. */
10308 /* Global symbols with default visibility in a shared library may be
10309 preempted by another definition. */
10314 /* md_estimate_size_before_relax()
10316 Called just before relax() for rs_machine_dependent frags. The x86
10317 assembler uses these frags to handle variable size jump
10320 Any symbol that is now undefined will not become defined.
10321 Return the correct fr_subtype in the frag.
10322 Return the initial "guess for variable size of frag" to caller.
10323 The guess is actually the growth beyond the fixed part. Whatever
10324 we do to grow the fixed or variable part contributes to our
10328 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10330 /* We've already got fragP->fr_subtype right; all we have to do is
10331 check for un-relaxable symbols. On an ELF system, we can't relax
10332 an externally visible symbol, because it may be overridden by a
10334 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10335 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10337 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10340 #if defined (OBJ_COFF) && defined (TE_PE)
10341 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10342 && S_IS_WEAK (fragP
->fr_symbol
))
10346 /* Symbol is undefined in this segment, or we need to keep a
10347 reloc so that weak symbols can be overridden. */
10348 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10349 enum bfd_reloc_code_real reloc_type
;
10350 unsigned char *opcode
;
10353 if (fragP
->fr_var
!= NO_RELOC
)
10354 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10355 else if (size
== 2)
10356 reloc_type
= BFD_RELOC_16_PCREL
;
10357 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10358 else if (need_plt32_p (fragP
->fr_symbol
))
10359 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10362 reloc_type
= BFD_RELOC_32_PCREL
;
10364 old_fr_fix
= fragP
->fr_fix
;
10365 opcode
= (unsigned char *) fragP
->fr_opcode
;
10367 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10370 /* Make jmp (0xeb) a (d)word displacement jump. */
10372 fragP
->fr_fix
+= size
;
10373 fix_new (fragP
, old_fr_fix
, size
,
10375 fragP
->fr_offset
, 1,
10381 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10383 /* Negate the condition, and branch past an
10384 unconditional jump. */
10387 /* Insert an unconditional jump. */
10389 /* We added two extra opcode bytes, and have a two byte
10391 fragP
->fr_fix
+= 2 + 2;
10392 fix_new (fragP
, old_fr_fix
+ 2, 2,
10394 fragP
->fr_offset
, 1,
10398 /* Fall through. */
10401 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10405 fragP
->fr_fix
+= 1;
10406 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10408 fragP
->fr_offset
, 1,
10409 BFD_RELOC_8_PCREL
);
10410 fixP
->fx_signed
= 1;
10414 /* This changes the byte-displacement jump 0x7N
10415 to the (d)word-displacement jump 0x0f,0x8N. */
10416 opcode
[1] = opcode
[0] + 0x10;
10417 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10418 /* We've added an opcode byte. */
10419 fragP
->fr_fix
+= 1 + size
;
10420 fix_new (fragP
, old_fr_fix
+ 1, size
,
10422 fragP
->fr_offset
, 1,
10427 BAD_CASE (fragP
->fr_subtype
);
10431 return fragP
->fr_fix
- old_fr_fix
;
10434 /* Guess size depending on current relax state. Initially the relax
10435 state will correspond to a short jump and we return 1, because
10436 the variable part of the frag (the branch offset) is one byte
10437 long. However, we can relax a section more than once and in that
10438 case we must either set fr_subtype back to the unrelaxed state,
10439 or return the value for the appropriate branch. */
10440 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10443 /* Called after relax() is finished.
10445 In: Address of frag.
10446 fr_type == rs_machine_dependent.
10447 fr_subtype is what the address relaxed to.
10449 Out: Any fixSs and constants are set up.
10450 Caller will turn frag into a ".space 0". */
10453 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10456 unsigned char *opcode
;
10457 unsigned char *where_to_put_displacement
= NULL
;
10458 offsetT target_address
;
10459 offsetT opcode_address
;
10460 unsigned int extension
= 0;
10461 offsetT displacement_from_opcode_start
;
10463 opcode
= (unsigned char *) fragP
->fr_opcode
;
10465 /* Address we want to reach in file space. */
10466 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10468 /* Address opcode resides at in file space. */
10469 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10471 /* Displacement from opcode start to fill into instruction. */
10472 displacement_from_opcode_start
= target_address
- opcode_address
;
10474 if ((fragP
->fr_subtype
& BIG
) == 0)
10476 /* Don't have to change opcode. */
10477 extension
= 1; /* 1 opcode + 1 displacement */
10478 where_to_put_displacement
= &opcode
[1];
10482 if (no_cond_jump_promotion
10483 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10484 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10485 _("long jump required"));
10487 switch (fragP
->fr_subtype
)
10489 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10490 extension
= 4; /* 1 opcode + 4 displacement */
10492 where_to_put_displacement
= &opcode
[1];
10495 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10496 extension
= 2; /* 1 opcode + 2 displacement */
10498 where_to_put_displacement
= &opcode
[1];
10501 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10502 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10503 extension
= 5; /* 2 opcode + 4 displacement */
10504 opcode
[1] = opcode
[0] + 0x10;
10505 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10506 where_to_put_displacement
= &opcode
[2];
10509 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10510 extension
= 3; /* 2 opcode + 2 displacement */
10511 opcode
[1] = opcode
[0] + 0x10;
10512 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10513 where_to_put_displacement
= &opcode
[2];
10516 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10521 where_to_put_displacement
= &opcode
[3];
10525 BAD_CASE (fragP
->fr_subtype
);
10530 /* If size if less then four we are sure that the operand fits,
10531 but if it's 4, then it could be that the displacement is larger
10533 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10535 && ((addressT
) (displacement_from_opcode_start
- extension
10536 + ((addressT
) 1 << 31))
10537 > (((addressT
) 2 << 31) - 1)))
10539 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10540 _("jump target out of range"));
10541 /* Make us emit 0. */
10542 displacement_from_opcode_start
= extension
;
10544 /* Now put displacement after opcode. */
10545 md_number_to_chars ((char *) where_to_put_displacement
,
10546 (valueT
) (displacement_from_opcode_start
- extension
),
10547 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10548 fragP
->fr_fix
+= extension
;
10551 /* Apply a fixup (fixP) to segment data, once it has been determined
10552 by our caller that we have all the info we need to fix it up.
10554 Parameter valP is the pointer to the value of the bits.
10556 On the 386, immediates, displacements, and data pointers are all in
10557 the same (little-endian) format, so we don't need to care about which
10558 we are handling. */
10561 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10563 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10564 valueT value
= *valP
;
10566 #if !defined (TE_Mach)
10567 if (fixP
->fx_pcrel
)
10569 switch (fixP
->fx_r_type
)
10575 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10578 case BFD_RELOC_X86_64_32S
:
10579 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10582 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10585 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10590 if (fixP
->fx_addsy
!= NULL
10591 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10592 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10593 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10594 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10595 && !use_rela_relocations
)
10597 /* This is a hack. There should be a better way to handle this.
10598 This covers for the fact that bfd_install_relocation will
10599 subtract the current location (for partial_inplace, PC relative
10600 relocations); see more below. */
10604 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10607 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10609 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10612 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10614 if ((sym_seg
== seg
10615 || (symbol_section_p (fixP
->fx_addsy
)
10616 && sym_seg
!= absolute_section
))
10617 && !generic_force_reloc (fixP
))
10619 /* Yes, we add the values in twice. This is because
10620 bfd_install_relocation subtracts them out again. I think
10621 bfd_install_relocation is broken, but I don't dare change
10623 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10627 #if defined (OBJ_COFF) && defined (TE_PE)
10628 /* For some reason, the PE format does not store a
10629 section address offset for a PC relative symbol. */
10630 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10631 || S_IS_WEAK (fixP
->fx_addsy
))
10632 value
+= md_pcrel_from (fixP
);
10635 #if defined (OBJ_COFF) && defined (TE_PE)
10636 if (fixP
->fx_addsy
!= NULL
10637 && S_IS_WEAK (fixP
->fx_addsy
)
10638 /* PR 16858: Do not modify weak function references. */
10639 && ! fixP
->fx_pcrel
)
10641 #if !defined (TE_PEP)
10642 /* For x86 PE weak function symbols are neither PC-relative
10643 nor do they set S_IS_FUNCTION. So the only reliable way
10644 to detect them is to check the flags of their containing
10646 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10647 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10651 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10655 /* Fix a few things - the dynamic linker expects certain values here,
10656 and we must not disappoint it. */
10657 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10658 if (IS_ELF
&& fixP
->fx_addsy
)
10659 switch (fixP
->fx_r_type
)
10661 case BFD_RELOC_386_PLT32
:
10662 case BFD_RELOC_X86_64_PLT32
:
10663 /* Make the jump instruction point to the address of the operand.
10664 At runtime we merely add the offset to the actual PLT entry.
10665 NB: Subtract the offset size only for jump instructions. */
10666 if (fixP
->fx_pcrel
)
10670 case BFD_RELOC_386_TLS_GD
:
10671 case BFD_RELOC_386_TLS_LDM
:
10672 case BFD_RELOC_386_TLS_IE_32
:
10673 case BFD_RELOC_386_TLS_IE
:
10674 case BFD_RELOC_386_TLS_GOTIE
:
10675 case BFD_RELOC_386_TLS_GOTDESC
:
10676 case BFD_RELOC_X86_64_TLSGD
:
10677 case BFD_RELOC_X86_64_TLSLD
:
10678 case BFD_RELOC_X86_64_GOTTPOFF
:
10679 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10680 value
= 0; /* Fully resolved at runtime. No addend. */
10682 case BFD_RELOC_386_TLS_LE
:
10683 case BFD_RELOC_386_TLS_LDO_32
:
10684 case BFD_RELOC_386_TLS_LE_32
:
10685 case BFD_RELOC_X86_64_DTPOFF32
:
10686 case BFD_RELOC_X86_64_DTPOFF64
:
10687 case BFD_RELOC_X86_64_TPOFF32
:
10688 case BFD_RELOC_X86_64_TPOFF64
:
10689 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10692 case BFD_RELOC_386_TLS_DESC_CALL
:
10693 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10694 value
= 0; /* Fully resolved at runtime. No addend. */
10695 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10699 case BFD_RELOC_VTABLE_INHERIT
:
10700 case BFD_RELOC_VTABLE_ENTRY
:
10707 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10709 #endif /* !defined (TE_Mach) */
10711 /* Are we finished with this relocation now? */
10712 if (fixP
->fx_addsy
== NULL
)
10714 #if defined (OBJ_COFF) && defined (TE_PE)
10715 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10718 /* Remember value for tc_gen_reloc. */
10719 fixP
->fx_addnumber
= value
;
10720 /* Clear out the frag for now. */
10724 else if (use_rela_relocations
)
10726 fixP
->fx_no_overflow
= 1;
10727 /* Remember value for tc_gen_reloc. */
10728 fixP
->fx_addnumber
= value
;
10732 md_number_to_chars (p
, value
, fixP
->fx_size
);
10736 md_atof (int type
, char *litP
, int *sizeP
)
10738 /* This outputs the LITTLENUMs in REVERSE order;
10739 in accord with the bigendian 386. */
10740 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10743 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10746 output_invalid (int c
)
10749 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10752 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10753 "(0x%x)", (unsigned char) c
);
10754 return output_invalid_buf
;
10757 /* REG_STRING starts *before* REGISTER_PREFIX. */
10759 static const reg_entry
*
10760 parse_real_register (char *reg_string
, char **end_op
)
10762 char *s
= reg_string
;
10764 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10765 const reg_entry
*r
;
10767 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10768 if (*s
== REGISTER_PREFIX
)
10771 if (is_space_char (*s
))
10774 p
= reg_name_given
;
10775 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10777 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10778 return (const reg_entry
*) NULL
;
10782 /* For naked regs, make sure that we are not dealing with an identifier.
10783 This prevents confusing an identifier like `eax_var' with register
10785 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10786 return (const reg_entry
*) NULL
;
10790 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10792 /* Handle floating point regs, allowing spaces in the (i) part. */
10793 if (r
== i386_regtab
/* %st is first entry of table */)
10795 if (!cpu_arch_flags
.bitfield
.cpu8087
10796 && !cpu_arch_flags
.bitfield
.cpu287
10797 && !cpu_arch_flags
.bitfield
.cpu387
)
10798 return (const reg_entry
*) NULL
;
10800 if (is_space_char (*s
))
10805 if (is_space_char (*s
))
10807 if (*s
>= '0' && *s
<= '7')
10809 int fpr
= *s
- '0';
10811 if (is_space_char (*s
))
10816 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10821 /* We have "%st(" then garbage. */
10822 return (const reg_entry
*) NULL
;
10826 if (r
== NULL
|| allow_pseudo_reg
)
10829 if (operand_type_all_zero (&r
->reg_type
))
10830 return (const reg_entry
*) NULL
;
10832 if ((r
->reg_type
.bitfield
.dword
10833 || r
->reg_type
.bitfield
.sreg3
10834 || r
->reg_type
.bitfield
.control
10835 || r
->reg_type
.bitfield
.debug
10836 || r
->reg_type
.bitfield
.test
)
10837 && !cpu_arch_flags
.bitfield
.cpui386
)
10838 return (const reg_entry
*) NULL
;
10840 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10841 return (const reg_entry
*) NULL
;
10843 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10845 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10846 return (const reg_entry
*) NULL
;
10848 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10850 if (r
->reg_type
.bitfield
.ymmword
)
10851 return (const reg_entry
*) NULL
;
10853 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10854 return (const reg_entry
*) NULL
;
10858 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10859 return (const reg_entry
*) NULL
;
10861 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10862 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10863 return (const reg_entry
*) NULL
;
10865 /* Upper 16 vector registers are only available with VREX in 64bit
10866 mode, and require EVEX encoding. */
10867 if (r
->reg_flags
& RegVRex
)
10869 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10870 || flag_code
!= CODE_64BIT
)
10871 return (const reg_entry
*) NULL
;
10873 i
.vec_encoding
= vex_encoding_evex
;
10876 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10877 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10878 && flag_code
!= CODE_64BIT
)
10879 return (const reg_entry
*) NULL
;
10881 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10882 return (const reg_entry
*) NULL
;
10887 /* REG_STRING starts *before* REGISTER_PREFIX. */
10889 static const reg_entry
*
10890 parse_register (char *reg_string
, char **end_op
)
10892 const reg_entry
*r
;
10894 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10895 r
= parse_real_register (reg_string
, end_op
);
10900 char *save
= input_line_pointer
;
10904 input_line_pointer
= reg_string
;
10905 c
= get_symbol_name (®_string
);
10906 symbolP
= symbol_find (reg_string
);
10907 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10909 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10911 know (e
->X_op
== O_register
);
10912 know (e
->X_add_number
>= 0
10913 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10914 r
= i386_regtab
+ e
->X_add_number
;
10915 if ((r
->reg_flags
& RegVRex
))
10916 i
.vec_encoding
= vex_encoding_evex
;
10917 *end_op
= input_line_pointer
;
10919 *input_line_pointer
= c
;
10920 input_line_pointer
= save
;
10926 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10928 const reg_entry
*r
;
10929 char *end
= input_line_pointer
;
10932 r
= parse_register (name
, &input_line_pointer
);
10933 if (r
&& end
<= input_line_pointer
)
10935 *nextcharP
= *input_line_pointer
;
10936 *input_line_pointer
= 0;
10937 e
->X_op
= O_register
;
10938 e
->X_add_number
= r
- i386_regtab
;
10941 input_line_pointer
= end
;
10943 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10947 md_operand (expressionS
*e
)
10950 const reg_entry
*r
;
10952 switch (*input_line_pointer
)
10954 case REGISTER_PREFIX
:
10955 r
= parse_real_register (input_line_pointer
, &end
);
10958 e
->X_op
= O_register
;
10959 e
->X_add_number
= r
- i386_regtab
;
10960 input_line_pointer
= end
;
10965 gas_assert (intel_syntax
);
10966 end
= input_line_pointer
++;
10968 if (*input_line_pointer
== ']')
10970 ++input_line_pointer
;
10971 e
->X_op_symbol
= make_expr_symbol (e
);
10972 e
->X_add_symbol
= NULL
;
10973 e
->X_add_number
= 0;
10978 e
->X_op
= O_absent
;
10979 input_line_pointer
= end
;
10986 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10987 const char *md_shortopts
= "kVQ:sqnO::";
10989 const char *md_shortopts
= "qnO::";
10992 #define OPTION_32 (OPTION_MD_BASE + 0)
10993 #define OPTION_64 (OPTION_MD_BASE + 1)
10994 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10995 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10996 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10997 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10998 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10999 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11000 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11001 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11002 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11003 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11004 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11005 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11006 #define OPTION_X32 (OPTION_MD_BASE + 14)
11007 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11008 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11009 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11010 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11011 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11012 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11013 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11014 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11015 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11016 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11017 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11018 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11020 struct option md_longopts
[] =
11022 {"32", no_argument
, NULL
, OPTION_32
},
11023 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11024 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11025 {"64", no_argument
, NULL
, OPTION_64
},
11027 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11028 {"x32", no_argument
, NULL
, OPTION_X32
},
11029 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11030 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11032 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11033 {"march", required_argument
, NULL
, OPTION_MARCH
},
11034 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11035 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11036 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11037 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11038 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11039 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11040 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11041 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11042 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11043 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11044 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11045 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11046 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11047 # if defined (TE_PE) || defined (TE_PEP)
11048 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11050 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11051 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11052 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11053 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11054 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11055 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11056 {NULL
, no_argument
, NULL
, 0}
11058 size_t md_longopts_size
= sizeof (md_longopts
);
11061 md_parse_option (int c
, const char *arg
)
11064 char *arch
, *next
, *saved
;
11069 optimize_align_code
= 0;
11073 quiet_warnings
= 1;
11076 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11077 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11078 should be emitted or not. FIXME: Not implemented. */
11082 /* -V: SVR4 argument to print version ID. */
11084 print_version_id ();
11087 /* -k: Ignore for FreeBSD compatibility. */
11092 /* -s: On i386 Solaris, this tells the native assembler to use
11093 .stab instead of .stab.excl. We always use .stab anyhow. */
11096 case OPTION_MSHARED
:
11100 case OPTION_X86_USED_NOTE
:
11101 if (strcasecmp (arg
, "yes") == 0)
11103 else if (strcasecmp (arg
, "no") == 0)
11106 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11111 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11112 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11115 const char **list
, **l
;
11117 list
= bfd_target_list ();
11118 for (l
= list
; *l
!= NULL
; l
++)
11119 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11120 || strcmp (*l
, "coff-x86-64") == 0
11121 || strcmp (*l
, "pe-x86-64") == 0
11122 || strcmp (*l
, "pei-x86-64") == 0
11123 || strcmp (*l
, "mach-o-x86-64") == 0)
11125 default_arch
= "x86_64";
11129 as_fatal (_("no compiled in support for x86_64"));
11135 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11139 const char **list
, **l
;
11141 list
= bfd_target_list ();
11142 for (l
= list
; *l
!= NULL
; l
++)
11143 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11145 default_arch
= "x86_64:32";
11149 as_fatal (_("no compiled in support for 32bit x86_64"));
11153 as_fatal (_("32bit x86_64 is only supported for ELF"));
11158 default_arch
= "i386";
11161 case OPTION_DIVIDE
:
11162 #ifdef SVR4_COMMENT_CHARS
11167 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11169 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11173 i386_comment_chars
= n
;
11179 saved
= xstrdup (arg
);
11181 /* Allow -march=+nosse. */
11187 as_fatal (_("invalid -march= option: `%s'"), arg
);
11188 next
= strchr (arch
, '+');
11191 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11193 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11196 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11199 cpu_arch_name
= cpu_arch
[j
].name
;
11200 cpu_sub_arch_name
= NULL
;
11201 cpu_arch_flags
= cpu_arch
[j
].flags
;
11202 cpu_arch_isa
= cpu_arch
[j
].type
;
11203 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11204 if (!cpu_arch_tune_set
)
11206 cpu_arch_tune
= cpu_arch_isa
;
11207 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11211 else if (*cpu_arch
[j
].name
== '.'
11212 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11214 /* ISA extension. */
11215 i386_cpu_flags flags
;
11217 flags
= cpu_flags_or (cpu_arch_flags
,
11218 cpu_arch
[j
].flags
);
11220 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11222 if (cpu_sub_arch_name
)
11224 char *name
= cpu_sub_arch_name
;
11225 cpu_sub_arch_name
= concat (name
,
11227 (const char *) NULL
);
11231 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11232 cpu_arch_flags
= flags
;
11233 cpu_arch_isa_flags
= flags
;
11237 = cpu_flags_or (cpu_arch_isa_flags
,
11238 cpu_arch
[j
].flags
);
11243 if (j
>= ARRAY_SIZE (cpu_arch
))
11245 /* Disable an ISA extension. */
11246 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11247 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11249 i386_cpu_flags flags
;
11251 flags
= cpu_flags_and_not (cpu_arch_flags
,
11252 cpu_noarch
[j
].flags
);
11253 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11255 if (cpu_sub_arch_name
)
11257 char *name
= cpu_sub_arch_name
;
11258 cpu_sub_arch_name
= concat (arch
,
11259 (const char *) NULL
);
11263 cpu_sub_arch_name
= xstrdup (arch
);
11264 cpu_arch_flags
= flags
;
11265 cpu_arch_isa_flags
= flags
;
11270 if (j
>= ARRAY_SIZE (cpu_noarch
))
11271 j
= ARRAY_SIZE (cpu_arch
);
11274 if (j
>= ARRAY_SIZE (cpu_arch
))
11275 as_fatal (_("invalid -march= option: `%s'"), arg
);
11279 while (next
!= NULL
);
11285 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11286 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11288 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11290 cpu_arch_tune_set
= 1;
11291 cpu_arch_tune
= cpu_arch
[j
].type
;
11292 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11296 if (j
>= ARRAY_SIZE (cpu_arch
))
11297 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11300 case OPTION_MMNEMONIC
:
11301 if (strcasecmp (arg
, "att") == 0)
11302 intel_mnemonic
= 0;
11303 else if (strcasecmp (arg
, "intel") == 0)
11304 intel_mnemonic
= 1;
11306 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11309 case OPTION_MSYNTAX
:
11310 if (strcasecmp (arg
, "att") == 0)
11312 else if (strcasecmp (arg
, "intel") == 0)
11315 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11318 case OPTION_MINDEX_REG
:
11319 allow_index_reg
= 1;
11322 case OPTION_MNAKED_REG
:
11323 allow_naked_reg
= 1;
11326 case OPTION_MSSE2AVX
:
11330 case OPTION_MSSE_CHECK
:
11331 if (strcasecmp (arg
, "error") == 0)
11332 sse_check
= check_error
;
11333 else if (strcasecmp (arg
, "warning") == 0)
11334 sse_check
= check_warning
;
11335 else if (strcasecmp (arg
, "none") == 0)
11336 sse_check
= check_none
;
11338 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11341 case OPTION_MOPERAND_CHECK
:
11342 if (strcasecmp (arg
, "error") == 0)
11343 operand_check
= check_error
;
11344 else if (strcasecmp (arg
, "warning") == 0)
11345 operand_check
= check_warning
;
11346 else if (strcasecmp (arg
, "none") == 0)
11347 operand_check
= check_none
;
11349 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11352 case OPTION_MAVXSCALAR
:
11353 if (strcasecmp (arg
, "128") == 0)
11354 avxscalar
= vex128
;
11355 else if (strcasecmp (arg
, "256") == 0)
11356 avxscalar
= vex256
;
11358 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11361 case OPTION_MVEXWIG
:
11362 if (strcmp (arg
, "0") == 0)
11364 else if (strcmp (arg
, "1") == 0)
11367 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11370 case OPTION_MADD_BND_PREFIX
:
11371 add_bnd_prefix
= 1;
11374 case OPTION_MEVEXLIG
:
11375 if (strcmp (arg
, "128") == 0)
11376 evexlig
= evexl128
;
11377 else if (strcmp (arg
, "256") == 0)
11378 evexlig
= evexl256
;
11379 else if (strcmp (arg
, "512") == 0)
11380 evexlig
= evexl512
;
11382 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11385 case OPTION_MEVEXRCIG
:
11386 if (strcmp (arg
, "rne") == 0)
11388 else if (strcmp (arg
, "rd") == 0)
11390 else if (strcmp (arg
, "ru") == 0)
11392 else if (strcmp (arg
, "rz") == 0)
11395 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11398 case OPTION_MEVEXWIG
:
11399 if (strcmp (arg
, "0") == 0)
11401 else if (strcmp (arg
, "1") == 0)
11404 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11407 # if defined (TE_PE) || defined (TE_PEP)
11408 case OPTION_MBIG_OBJ
:
11413 case OPTION_MOMIT_LOCK_PREFIX
:
11414 if (strcasecmp (arg
, "yes") == 0)
11415 omit_lock_prefix
= 1;
11416 else if (strcasecmp (arg
, "no") == 0)
11417 omit_lock_prefix
= 0;
11419 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11422 case OPTION_MFENCE_AS_LOCK_ADD
:
11423 if (strcasecmp (arg
, "yes") == 0)
11425 else if (strcasecmp (arg
, "no") == 0)
11428 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11431 case OPTION_MRELAX_RELOCATIONS
:
11432 if (strcasecmp (arg
, "yes") == 0)
11433 generate_relax_relocations
= 1;
11434 else if (strcasecmp (arg
, "no") == 0)
11435 generate_relax_relocations
= 0;
11437 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11440 case OPTION_MAMD64
:
11444 case OPTION_MINTEL64
:
11452 /* Turn off -Os. */
11453 optimize_for_space
= 0;
11455 else if (*arg
== 's')
11457 optimize_for_space
= 1;
11458 /* Turn on all encoding optimizations. */
11459 optimize
= INT_MAX
;
11463 optimize
= atoi (arg
);
11464 /* Turn off -Os. */
11465 optimize_for_space
= 0;
11475 #define MESSAGE_TEMPLATE \
11479 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11480 int *left_p
, const char *name
, int len
)
11482 int size
= sizeof (MESSAGE_TEMPLATE
);
11483 int left
= *left_p
;
11485 /* Reserve 2 spaces for ", " or ",\0" */
11488 /* Check if there is any room. */
11496 p
= mempcpy (p
, name
, len
);
11500 /* Output the current message now and start a new one. */
11503 fprintf (stream
, "%s\n", message
);
11505 left
= size
- (start
- message
) - len
- 2;
11507 gas_assert (left
>= 0);
11509 p
= mempcpy (p
, name
, len
);
11517 show_arch (FILE *stream
, int ext
, int check
)
11519 static char message
[] = MESSAGE_TEMPLATE
;
11520 char *start
= message
+ 27;
11522 int size
= sizeof (MESSAGE_TEMPLATE
);
11529 left
= size
- (start
- message
);
11530 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11532 /* Should it be skipped? */
11533 if (cpu_arch
[j
].skip
)
11536 name
= cpu_arch
[j
].name
;
11537 len
= cpu_arch
[j
].len
;
11540 /* It is an extension. Skip if we aren't asked to show it. */
11551 /* It is an processor. Skip if we show only extension. */
11554 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11556 /* It is an impossible processor - skip. */
11560 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11563 /* Display disabled extensions. */
11565 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11567 name
= cpu_noarch
[j
].name
;
11568 len
= cpu_noarch
[j
].len
;
11569 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11574 fprintf (stream
, "%s\n", message
);
11578 md_show_usage (FILE *stream
)
11580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11581 fprintf (stream
, _("\
11583 -V print assembler version number\n\
11586 fprintf (stream
, _("\
11587 -n Do not optimize code alignment\n\
11588 -q quieten some warnings\n"));
11589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11590 fprintf (stream
, _("\
11593 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11594 || defined (TE_PE) || defined (TE_PEP))
11595 fprintf (stream
, _("\
11596 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11598 #ifdef SVR4_COMMENT_CHARS
11599 fprintf (stream
, _("\
11600 --divide do not treat `/' as a comment character\n"));
11602 fprintf (stream
, _("\
11603 --divide ignored\n"));
11605 fprintf (stream
, _("\
11606 -march=CPU[,+EXTENSION...]\n\
11607 generate code for CPU and EXTENSION, CPU is one of:\n"));
11608 show_arch (stream
, 0, 1);
11609 fprintf (stream
, _("\
11610 EXTENSION is combination of:\n"));
11611 show_arch (stream
, 1, 0);
11612 fprintf (stream
, _("\
11613 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11614 show_arch (stream
, 0, 0);
11615 fprintf (stream
, _("\
11616 -msse2avx encode SSE instructions with VEX prefix\n"));
11617 fprintf (stream
, _("\
11618 -msse-check=[none|error|warning] (default: warning)\n\
11619 check SSE instructions\n"));
11620 fprintf (stream
, _("\
11621 -moperand-check=[none|error|warning] (default: warning)\n\
11622 check operand combinations for validity\n"));
11623 fprintf (stream
, _("\
11624 -mavxscalar=[128|256] (default: 128)\n\
11625 encode scalar AVX instructions with specific vector\n\
11627 fprintf (stream
, _("\
11628 -mvexwig=[0|1] (default: 0)\n\
11629 encode VEX instructions with specific VEX.W value\n\
11630 for VEX.W bit ignored instructions\n"));
11631 fprintf (stream
, _("\
11632 -mevexlig=[128|256|512] (default: 128)\n\
11633 encode scalar EVEX instructions with specific vector\n\
11635 fprintf (stream
, _("\
11636 -mevexwig=[0|1] (default: 0)\n\
11637 encode EVEX instructions with specific EVEX.W value\n\
11638 for EVEX.W bit ignored instructions\n"));
11639 fprintf (stream
, _("\
11640 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11641 encode EVEX instructions with specific EVEX.RC value\n\
11642 for SAE-only ignored instructions\n"));
11643 fprintf (stream
, _("\
11644 -mmnemonic=[att|intel] "));
11645 if (SYSV386_COMPAT
)
11646 fprintf (stream
, _("(default: att)\n"));
11648 fprintf (stream
, _("(default: intel)\n"));
11649 fprintf (stream
, _("\
11650 use AT&T/Intel mnemonic\n"));
11651 fprintf (stream
, _("\
11652 -msyntax=[att|intel] (default: att)\n\
11653 use AT&T/Intel syntax\n"));
11654 fprintf (stream
, _("\
11655 -mindex-reg support pseudo index registers\n"));
11656 fprintf (stream
, _("\
11657 -mnaked-reg don't require `%%' prefix for registers\n"));
11658 fprintf (stream
, _("\
11659 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11660 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11661 fprintf (stream
, _("\
11662 -mshared disable branch optimization for shared code\n"));
11663 fprintf (stream
, _("\
11664 -mx86-used-note=[no|yes] "));
11665 if (DEFAULT_X86_USED_NOTE
)
11666 fprintf (stream
, _("(default: yes)\n"));
11668 fprintf (stream
, _("(default: no)\n"));
11669 fprintf (stream
, _("\
11670 generate x86 used ISA and feature properties\n"));
11672 #if defined (TE_PE) || defined (TE_PEP)
11673 fprintf (stream
, _("\
11674 -mbig-obj generate big object files\n"));
11676 fprintf (stream
, _("\
11677 -momit-lock-prefix=[no|yes] (default: no)\n\
11678 strip all lock prefixes\n"));
11679 fprintf (stream
, _("\
11680 -mfence-as-lock-add=[no|yes] (default: no)\n\
11681 encode lfence, mfence and sfence as\n\
11682 lock addl $0x0, (%%{re}sp)\n"));
11683 fprintf (stream
, _("\
11684 -mrelax-relocations=[no|yes] "));
11685 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11686 fprintf (stream
, _("(default: yes)\n"));
11688 fprintf (stream
, _("(default: no)\n"));
11689 fprintf (stream
, _("\
11690 generate relax relocations\n"));
11691 fprintf (stream
, _("\
11692 -mamd64 accept only AMD64 ISA [default]\n"));
11693 fprintf (stream
, _("\
11694 -mintel64 accept only Intel64 ISA\n"));
11697 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11698 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11699 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11701 /* Pick the target format to use. */
11704 i386_target_format (void)
11706 if (!strncmp (default_arch
, "x86_64", 6))
11708 update_code_flag (CODE_64BIT
, 1);
11709 if (default_arch
[6] == '\0')
11710 x86_elf_abi
= X86_64_ABI
;
11712 x86_elf_abi
= X86_64_X32_ABI
;
11714 else if (!strcmp (default_arch
, "i386"))
11715 update_code_flag (CODE_32BIT
, 1);
11716 else if (!strcmp (default_arch
, "iamcu"))
11718 update_code_flag (CODE_32BIT
, 1);
11719 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11721 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11722 cpu_arch_name
= "iamcu";
11723 cpu_sub_arch_name
= NULL
;
11724 cpu_arch_flags
= iamcu_flags
;
11725 cpu_arch_isa
= PROCESSOR_IAMCU
;
11726 cpu_arch_isa_flags
= iamcu_flags
;
11727 if (!cpu_arch_tune_set
)
11729 cpu_arch_tune
= cpu_arch_isa
;
11730 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11733 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11734 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11738 as_fatal (_("unknown architecture"));
11740 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11741 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11742 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11743 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11745 switch (OUTPUT_FLAVOR
)
11747 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11748 case bfd_target_aout_flavour
:
11749 return AOUT_TARGET_FORMAT
;
11751 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11752 # if defined (TE_PE) || defined (TE_PEP)
11753 case bfd_target_coff_flavour
:
11754 if (flag_code
== CODE_64BIT
)
11755 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11758 # elif defined (TE_GO32)
11759 case bfd_target_coff_flavour
:
11760 return "coff-go32";
11762 case bfd_target_coff_flavour
:
11763 return "coff-i386";
11766 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11767 case bfd_target_elf_flavour
:
11769 const char *format
;
11771 switch (x86_elf_abi
)
11774 format
= ELF_TARGET_FORMAT
;
11777 use_rela_relocations
= 1;
11779 format
= ELF_TARGET_FORMAT64
;
11781 case X86_64_X32_ABI
:
11782 use_rela_relocations
= 1;
11784 disallow_64bit_reloc
= 1;
11785 format
= ELF_TARGET_FORMAT32
;
11788 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11790 if (x86_elf_abi
!= X86_64_ABI
)
11791 as_fatal (_("Intel L1OM is 64bit only"));
11792 return ELF_TARGET_L1OM_FORMAT
;
11794 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11796 if (x86_elf_abi
!= X86_64_ABI
)
11797 as_fatal (_("Intel K1OM is 64bit only"));
11798 return ELF_TARGET_K1OM_FORMAT
;
11800 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11802 if (x86_elf_abi
!= I386_ABI
)
11803 as_fatal (_("Intel MCU is 32bit only"));
11804 return ELF_TARGET_IAMCU_FORMAT
;
11810 #if defined (OBJ_MACH_O)
11811 case bfd_target_mach_o_flavour
:
11812 if (flag_code
== CODE_64BIT
)
11814 use_rela_relocations
= 1;
11816 return "mach-o-x86-64";
11819 return "mach-o-i386";
11827 #endif /* OBJ_MAYBE_ more than one */
11830 md_undefined_symbol (char *name
)
11832 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11833 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11834 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11835 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11839 if (symbol_find (name
))
11840 as_bad (_("GOT already in symbol table"));
11841 GOT_symbol
= symbol_new (name
, undefined_section
,
11842 (valueT
) 0, &zero_address_frag
);
11849 /* Round up a section size to the appropriate boundary. */
11852 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11854 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11855 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11857 /* For a.out, force the section size to be aligned. If we don't do
11858 this, BFD will align it for us, but it will not write out the
11859 final bytes of the section. This may be a bug in BFD, but it is
11860 easier to fix it here since that is how the other a.out targets
11864 align
= bfd_get_section_alignment (stdoutput
, segment
);
11865 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11872 /* On the i386, PC-relative offsets are relative to the start of the
11873 next instruction. That is, the address of the offset, plus its
11874 size, since the offset is always the last part of the insn. */
11877 md_pcrel_from (fixS
*fixP
)
11879 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11885 s_bss (int ignore ATTRIBUTE_UNUSED
)
11889 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11891 obj_elf_section_change_hook ();
11893 temp
= get_absolute_expression ();
11894 subseg_set (bss_section
, (subsegT
) temp
);
11895 demand_empty_rest_of_line ();
11901 i386_validate_fix (fixS
*fixp
)
11903 if (fixp
->fx_subsy
)
11905 if (fixp
->fx_subsy
== GOT_symbol
)
11907 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11911 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11912 if (fixp
->fx_tcbit2
)
11913 fixp
->fx_r_type
= (fixp
->fx_tcbit
11914 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11915 : BFD_RELOC_X86_64_GOTPCRELX
);
11918 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11923 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11925 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11927 fixp
->fx_subsy
= 0;
11930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11931 else if (!object_64bit
)
11933 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11934 && fixp
->fx_tcbit2
)
11935 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11941 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11944 bfd_reloc_code_real_type code
;
11946 switch (fixp
->fx_r_type
)
11948 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11949 case BFD_RELOC_SIZE32
:
11950 case BFD_RELOC_SIZE64
:
11951 if (S_IS_DEFINED (fixp
->fx_addsy
)
11952 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11954 /* Resolve size relocation against local symbol to size of
11955 the symbol plus addend. */
11956 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11957 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11958 && !fits_in_unsigned_long (value
))
11959 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11960 _("symbol size computation overflow"));
11961 fixp
->fx_addsy
= NULL
;
11962 fixp
->fx_subsy
= NULL
;
11963 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11967 /* Fall through. */
11969 case BFD_RELOC_X86_64_PLT32
:
11970 case BFD_RELOC_X86_64_GOT32
:
11971 case BFD_RELOC_X86_64_GOTPCREL
:
11972 case BFD_RELOC_X86_64_GOTPCRELX
:
11973 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11974 case BFD_RELOC_386_PLT32
:
11975 case BFD_RELOC_386_GOT32
:
11976 case BFD_RELOC_386_GOT32X
:
11977 case BFD_RELOC_386_GOTOFF
:
11978 case BFD_RELOC_386_GOTPC
:
11979 case BFD_RELOC_386_TLS_GD
:
11980 case BFD_RELOC_386_TLS_LDM
:
11981 case BFD_RELOC_386_TLS_LDO_32
:
11982 case BFD_RELOC_386_TLS_IE_32
:
11983 case BFD_RELOC_386_TLS_IE
:
11984 case BFD_RELOC_386_TLS_GOTIE
:
11985 case BFD_RELOC_386_TLS_LE_32
:
11986 case BFD_RELOC_386_TLS_LE
:
11987 case BFD_RELOC_386_TLS_GOTDESC
:
11988 case BFD_RELOC_386_TLS_DESC_CALL
:
11989 case BFD_RELOC_X86_64_TLSGD
:
11990 case BFD_RELOC_X86_64_TLSLD
:
11991 case BFD_RELOC_X86_64_DTPOFF32
:
11992 case BFD_RELOC_X86_64_DTPOFF64
:
11993 case BFD_RELOC_X86_64_GOTTPOFF
:
11994 case BFD_RELOC_X86_64_TPOFF32
:
11995 case BFD_RELOC_X86_64_TPOFF64
:
11996 case BFD_RELOC_X86_64_GOTOFF64
:
11997 case BFD_RELOC_X86_64_GOTPC32
:
11998 case BFD_RELOC_X86_64_GOT64
:
11999 case BFD_RELOC_X86_64_GOTPCREL64
:
12000 case BFD_RELOC_X86_64_GOTPC64
:
12001 case BFD_RELOC_X86_64_GOTPLT64
:
12002 case BFD_RELOC_X86_64_PLTOFF64
:
12003 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12004 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12005 case BFD_RELOC_RVA
:
12006 case BFD_RELOC_VTABLE_ENTRY
:
12007 case BFD_RELOC_VTABLE_INHERIT
:
12009 case BFD_RELOC_32_SECREL
:
12011 code
= fixp
->fx_r_type
;
12013 case BFD_RELOC_X86_64_32S
:
12014 if (!fixp
->fx_pcrel
)
12016 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12017 code
= fixp
->fx_r_type
;
12020 /* Fall through. */
12022 if (fixp
->fx_pcrel
)
12024 switch (fixp
->fx_size
)
12027 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12028 _("can not do %d byte pc-relative relocation"),
12030 code
= BFD_RELOC_32_PCREL
;
12032 case 1: code
= BFD_RELOC_8_PCREL
; break;
12033 case 2: code
= BFD_RELOC_16_PCREL
; break;
12034 case 4: code
= BFD_RELOC_32_PCREL
; break;
12036 case 8: code
= BFD_RELOC_64_PCREL
; break;
12042 switch (fixp
->fx_size
)
12045 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12046 _("can not do %d byte relocation"),
12048 code
= BFD_RELOC_32
;
12050 case 1: code
= BFD_RELOC_8
; break;
12051 case 2: code
= BFD_RELOC_16
; break;
12052 case 4: code
= BFD_RELOC_32
; break;
12054 case 8: code
= BFD_RELOC_64
; break;
12061 if ((code
== BFD_RELOC_32
12062 || code
== BFD_RELOC_32_PCREL
12063 || code
== BFD_RELOC_X86_64_32S
)
12065 && fixp
->fx_addsy
== GOT_symbol
)
12068 code
= BFD_RELOC_386_GOTPC
;
12070 code
= BFD_RELOC_X86_64_GOTPC32
;
12072 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12074 && fixp
->fx_addsy
== GOT_symbol
)
12076 code
= BFD_RELOC_X86_64_GOTPC64
;
12079 rel
= XNEW (arelent
);
12080 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12081 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12083 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12085 if (!use_rela_relocations
)
12087 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12088 vtable entry to be used in the relocation's section offset. */
12089 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12090 rel
->address
= fixp
->fx_offset
;
12091 #if defined (OBJ_COFF) && defined (TE_PE)
12092 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12093 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12098 /* Use the rela in 64bit mode. */
12101 if (disallow_64bit_reloc
)
12104 case BFD_RELOC_X86_64_DTPOFF64
:
12105 case BFD_RELOC_X86_64_TPOFF64
:
12106 case BFD_RELOC_64_PCREL
:
12107 case BFD_RELOC_X86_64_GOTOFF64
:
12108 case BFD_RELOC_X86_64_GOT64
:
12109 case BFD_RELOC_X86_64_GOTPCREL64
:
12110 case BFD_RELOC_X86_64_GOTPC64
:
12111 case BFD_RELOC_X86_64_GOTPLT64
:
12112 case BFD_RELOC_X86_64_PLTOFF64
:
12113 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12114 _("cannot represent relocation type %s in x32 mode"),
12115 bfd_get_reloc_code_name (code
));
12121 if (!fixp
->fx_pcrel
)
12122 rel
->addend
= fixp
->fx_offset
;
12126 case BFD_RELOC_X86_64_PLT32
:
12127 case BFD_RELOC_X86_64_GOT32
:
12128 case BFD_RELOC_X86_64_GOTPCREL
:
12129 case BFD_RELOC_X86_64_GOTPCRELX
:
12130 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12131 case BFD_RELOC_X86_64_TLSGD
:
12132 case BFD_RELOC_X86_64_TLSLD
:
12133 case BFD_RELOC_X86_64_GOTTPOFF
:
12134 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12135 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12136 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12139 rel
->addend
= (section
->vma
12141 + fixp
->fx_addnumber
12142 + md_pcrel_from (fixp
));
12147 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12148 if (rel
->howto
== NULL
)
12150 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12151 _("cannot represent relocation type %s"),
12152 bfd_get_reloc_code_name (code
));
12153 /* Set howto to a garbage value so that we can keep going. */
12154 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12155 gas_assert (rel
->howto
!= NULL
);
12161 #include "tc-i386-intel.c"
12164 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12166 int saved_naked_reg
;
12167 char saved_register_dot
;
12169 saved_naked_reg
= allow_naked_reg
;
12170 allow_naked_reg
= 1;
12171 saved_register_dot
= register_chars
['.'];
12172 register_chars
['.'] = '.';
12173 allow_pseudo_reg
= 1;
12174 expression_and_evaluate (exp
);
12175 allow_pseudo_reg
= 0;
12176 register_chars
['.'] = saved_register_dot
;
12177 allow_naked_reg
= saved_naked_reg
;
12179 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12181 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12183 exp
->X_op
= O_constant
;
12184 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12185 .dw2_regnum
[flag_code
>> 1];
12188 exp
->X_op
= O_illegal
;
12193 tc_x86_frame_initial_instructions (void)
12195 static unsigned int sp_regno
[2];
12197 if (!sp_regno
[flag_code
>> 1])
12199 char *saved_input
= input_line_pointer
;
12200 char sp
[][4] = {"esp", "rsp"};
12203 input_line_pointer
= sp
[flag_code
>> 1];
12204 tc_x86_parse_to_dw2regnum (&exp
);
12205 gas_assert (exp
.X_op
== O_constant
);
12206 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12207 input_line_pointer
= saved_input
;
12210 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12211 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12215 x86_dwarf2_addr_size (void)
12217 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12218 if (x86_elf_abi
== X86_64_X32_ABI
)
12221 return bfd_arch_bits_per_address (stdoutput
) / 8;
12225 i386_elf_section_type (const char *str
, size_t len
)
12227 if (flag_code
== CODE_64BIT
12228 && len
== sizeof ("unwind") - 1
12229 && strncmp (str
, "unwind", 6) == 0)
12230 return SHT_X86_64_UNWIND
;
12237 i386_solaris_fix_up_eh_frame (segT sec
)
12239 if (flag_code
== CODE_64BIT
)
12240 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12246 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12250 exp
.X_op
= O_secrel
;
12251 exp
.X_add_symbol
= symbol
;
12252 exp
.X_add_number
= 0;
12253 emit_expr (&exp
, size
);
12257 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12258 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12261 x86_64_section_letter (int letter
, const char **ptr_msg
)
12263 if (flag_code
== CODE_64BIT
)
12266 return SHF_X86_64_LARGE
;
12268 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12271 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12276 x86_64_section_word (char *str
, size_t len
)
12278 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12279 return SHF_X86_64_LARGE
;
12285 handle_large_common (int small ATTRIBUTE_UNUSED
)
12287 if (flag_code
!= CODE_64BIT
)
12289 s_comm_internal (0, elf_common_parse
);
12290 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12294 static segT lbss_section
;
12295 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12296 asection
*saved_bss_section
= bss_section
;
12298 if (lbss_section
== NULL
)
12300 flagword applicable
;
12301 segT seg
= now_seg
;
12302 subsegT subseg
= now_subseg
;
12304 /* The .lbss section is for local .largecomm symbols. */
12305 lbss_section
= subseg_new (".lbss", 0);
12306 applicable
= bfd_applicable_section_flags (stdoutput
);
12307 bfd_set_section_flags (stdoutput
, lbss_section
,
12308 applicable
& SEC_ALLOC
);
12309 seg_info (lbss_section
)->bss
= 1;
12311 subseg_set (seg
, subseg
);
12314 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12315 bss_section
= lbss_section
;
12317 s_comm_internal (0, elf_common_parse
);
12319 elf_com_section_ptr
= saved_com_section_ptr
;
12320 bss_section
= saved_bss_section
;
12323 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */