1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
293 invalid_vsib_address
,
294 invalid_vector_register_set
,
295 unsupported_vector_index_register
,
296 unsupported_broadcast
,
299 mask_not_on_destination
,
302 rc_sae_operand_not_last_imm
,
303 invalid_register_operand
,
308 /* TM holds the template for the insn were currently assembling. */
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands
;
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
321 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types
[MAX_OPERANDS
];
327 /* Displacement expression, immediate expression, or register for each
329 union i386_op op
[MAX_OPERANDS
];
331 /* Flags for operands. */
332 unsigned int flags
[MAX_OPERANDS
];
333 #define Operand_PCrel 1
334 #define Operand_Mem 2
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry
*base_reg
;
342 const reg_entry
*index_reg
;
343 unsigned int log2_scale_factor
;
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry
*seg
[2];
349 /* Copied first memory operand string, for re-checking. */
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes
;
355 unsigned char prefix
[MAX_PREFIXES
];
357 /* Register is in low 3 bits of opcode. */
358 bfd_boolean short_form
;
360 /* The operand to a branch insn indicates an absolute branch. */
361 bfd_boolean jumpabsolute
;
363 /* Has MMX register operands. */
364 bfd_boolean has_regmmx
;
366 /* Has XMM register operands. */
367 bfd_boolean has_regxmm
;
369 /* Has YMM register operands. */
370 bfd_boolean has_regymm
;
372 /* Has ZMM register operands. */
373 bfd_boolean has_regzmm
;
375 /* Has GOTPC or TLS relocation. */
376 bfd_boolean has_gotpc_tls_reloc
;
378 /* RM and SIB are the modrm byte and the sib byte where the
379 addressing modes of this insn are encoded. */
386 /* Masking attributes. */
387 struct Mask_Operation
*mask
;
389 /* Rounding control and SAE attributes. */
390 struct RC_Operation
*rounding
;
392 /* Broadcasting attributes. */
393 struct Broadcast_Operation
*broadcast
;
395 /* Compressed disp8*N attribute. */
396 unsigned int memshift
;
398 /* Prefer load or store in encoding. */
401 dir_encoding_default
= 0,
407 /* Prefer 8bit or 32bit displacement in encoding. */
410 disp_encoding_default
= 0,
415 /* Prefer the REX byte in encoding. */
416 bfd_boolean rex_encoding
;
418 /* Disable instruction size optimization. */
419 bfd_boolean no_optimize
;
421 /* How to encode vector instructions. */
424 vex_encoding_default
= 0,
432 const char *rep_prefix
;
435 const char *hle_prefix
;
437 /* Have BND prefix. */
438 const char *bnd_prefix
;
440 /* Have NOTRACK prefix. */
441 const char *notrack_prefix
;
444 enum i386_error error
;
447 typedef struct _i386_insn i386_insn
;
449 /* Link RC type with corresponding string, that'll be looked for in
458 static const struct RC_name RC_NamesTable
[] =
460 { rne
, STRING_COMMA_LEN ("rn-sae") },
461 { rd
, STRING_COMMA_LEN ("rd-sae") },
462 { ru
, STRING_COMMA_LEN ("ru-sae") },
463 { rz
, STRING_COMMA_LEN ("rz-sae") },
464 { saeonly
, STRING_COMMA_LEN ("sae") },
467 /* List of chars besides those in app.c:symbol_chars that can start an
468 operand. Used to prevent the scrubber eating vital white-space. */
469 const char extra_symbol_chars
[] = "*%-([{}"
478 #if (defined (TE_I386AIX) \
479 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
480 && !defined (TE_GNU) \
481 && !defined (TE_LINUX) \
482 && !defined (TE_NACL) \
483 && !defined (TE_FreeBSD) \
484 && !defined (TE_DragonFly) \
485 && !defined (TE_NetBSD)))
486 /* This array holds the chars that always start a comment. If the
487 pre-processor is disabled, these aren't very useful. The option
488 --divide will remove '/' from this list. */
489 const char *i386_comment_chars
= "#/";
490 #define SVR4_COMMENT_CHARS 1
491 #define PREFIX_SEPARATOR '\\'
494 const char *i386_comment_chars
= "#";
495 #define PREFIX_SEPARATOR '/'
498 /* This array holds the chars that only start a comment at the beginning of
499 a line. If the line seems to have the form '# 123 filename'
500 .line and .file directives will appear in the pre-processed output.
501 Note that input_file.c hand checks for '#' at the beginning of the
502 first line of the input file. This is because the compiler outputs
503 #NO_APP at the beginning of its output.
504 Also note that comments started like this one will always work if
505 '/' isn't otherwise defined. */
506 const char line_comment_chars
[] = "#/";
508 const char line_separator_chars
[] = ";";
510 /* Chars that can be used to separate mant from exp in floating point
512 const char EXP_CHARS
[] = "eE";
514 /* Chars that mean this number is a floating point constant
517 const char FLT_CHARS
[] = "fFdDxX";
519 /* Tables for lexical analysis. */
520 static char mnemonic_chars
[256];
521 static char register_chars
[256];
522 static char operand_chars
[256];
523 static char identifier_chars
[256];
524 static char digit_chars
[256];
526 /* Lexical macros. */
527 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
528 #define is_operand_char(x) (operand_chars[(unsigned char) x])
529 #define is_register_char(x) (register_chars[(unsigned char) x])
530 #define is_space_char(x) ((x) == ' ')
531 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
532 #define is_digit_char(x) (digit_chars[(unsigned char) x])
534 /* All non-digit non-letter characters that may occur in an operand. */
535 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
537 /* md_assemble() always leaves the strings it's passed unaltered. To
538 effect this we maintain a stack of saved characters that we've smashed
539 with '\0's (indicating end of strings for various sub-fields of the
540 assembler instruction). */
541 static char save_stack
[32];
542 static char *save_stack_p
;
543 #define END_STRING_AND_SAVE(s) \
544 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
545 #define RESTORE_END_STRING(s) \
546 do { *(s) = *--save_stack_p; } while (0)
548 /* The instruction we're assembling. */
551 /* Possible templates for current insn. */
552 static const templates
*current_templates
;
554 /* Per instruction expressionS buffers: max displacements & immediates. */
555 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
556 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
558 /* Current operand we are working on. */
559 static int this_operand
= -1;
561 /* We support four different modes. FLAG_CODE variable is used to distinguish
569 static enum flag_code flag_code
;
570 static unsigned int object_64bit
;
571 static unsigned int disallow_64bit_reloc
;
572 static int use_rela_relocations
= 0;
573 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
574 static const char *tls_get_addr
;
576 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
577 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
578 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
580 /* The ELF ABI to use. */
588 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
591 #if defined (TE_PE) || defined (TE_PEP)
592 /* Use big object file format. */
593 static int use_big_obj
= 0;
596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
597 /* 1 if generating code for a shared library. */
598 static int shared
= 0;
601 /* 1 for intel syntax,
603 static int intel_syntax
= 0;
605 static enum x86_64_isa
607 amd64
= 1, /* AMD64 ISA. */
608 intel64
/* Intel64 ISA. */
611 /* 1 for intel mnemonic,
612 0 if att mnemonic. */
613 static int intel_mnemonic
= !SYSV386_COMPAT
;
615 /* 1 if pseudo registers are permitted. */
616 static int allow_pseudo_reg
= 0;
618 /* 1 if register prefix % not required. */
619 static int allow_naked_reg
= 0;
621 /* 1 if the assembler should add BND prefix for all control-transferring
622 instructions supporting it, even if this prefix wasn't specified
624 static int add_bnd_prefix
= 0;
626 /* 1 if pseudo index register, eiz/riz, is allowed . */
627 static int allow_index_reg
= 0;
629 /* 1 if the assembler should ignore LOCK prefix, even if it was
630 specified explicitly. */
631 static int omit_lock_prefix
= 0;
633 /* 1 if the assembler should encode lfence, mfence, and sfence as
634 "lock addl $0, (%{re}sp)". */
635 static int avoid_fence
= 0;
637 /* 1 if lfence should be inserted after every load. */
638 static int lfence_after_load
= 0;
640 /* Non-zero if lfence should be inserted before indirect branch. */
641 static enum lfence_before_indirect_branch_kind
643 lfence_branch_none
= 0,
644 lfence_branch_register
,
645 lfence_branch_memory
,
648 lfence_before_indirect_branch
;
650 /* Non-zero if lfence should be inserted before ret. */
651 static enum lfence_before_ret_kind
653 lfence_before_ret_none
= 0,
654 lfence_before_ret_not
,
655 lfence_before_ret_or
,
656 lfence_before_ret_shl
660 /* Types of previous instruction is .byte or prefix. */
675 /* 1 if the assembler should generate relax relocations. */
677 static int generate_relax_relocations
678 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
680 static enum check_kind
686 sse_check
, operand_check
= check_warning
;
688 /* Non-zero if branches should be aligned within power of 2 boundary. */
689 static int align_branch_power
= 0;
691 /* Types of branches to align. */
692 enum align_branch_kind
694 align_branch_none
= 0,
695 align_branch_jcc
= 1,
696 align_branch_fused
= 2,
697 align_branch_jmp
= 3,
698 align_branch_call
= 4,
699 align_branch_indirect
= 5,
703 /* Type bits of branches to align. */
704 enum align_branch_bit
706 align_branch_jcc_bit
= 1 << align_branch_jcc
,
707 align_branch_fused_bit
= 1 << align_branch_fused
,
708 align_branch_jmp_bit
= 1 << align_branch_jmp
,
709 align_branch_call_bit
= 1 << align_branch_call
,
710 align_branch_indirect_bit
= 1 << align_branch_indirect
,
711 align_branch_ret_bit
= 1 << align_branch_ret
714 static unsigned int align_branch
= (align_branch_jcc_bit
715 | align_branch_fused_bit
716 | align_branch_jmp_bit
);
718 /* Types of condition jump used by macro-fusion. */
721 mf_jcc_jo
= 0, /* base opcode 0x70 */
722 mf_jcc_jc
, /* base opcode 0x72 */
723 mf_jcc_je
, /* base opcode 0x74 */
724 mf_jcc_jna
, /* base opcode 0x76 */
725 mf_jcc_js
, /* base opcode 0x78 */
726 mf_jcc_jp
, /* base opcode 0x7a */
727 mf_jcc_jl
, /* base opcode 0x7c */
728 mf_jcc_jle
, /* base opcode 0x7e */
731 /* Types of compare flag-modifying insntructions used by macro-fusion. */
734 mf_cmp_test_and
, /* test/cmp */
735 mf_cmp_alu_cmp
, /* add/sub/cmp */
736 mf_cmp_incdec
/* inc/dec */
739 /* The maximum padding size for fused jcc. CMP like instruction can
740 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
742 #define MAX_FUSED_JCC_PADDING_SIZE 20
744 /* The maximum number of prefixes added for an instruction. */
745 static unsigned int align_branch_prefix_size
= 5;
748 1. Clear the REX_W bit with register operand if possible.
749 2. Above plus use 128bit vector instruction to clear the full vector
752 static int optimize
= 0;
755 1. Clear the REX_W bit with register operand if possible.
756 2. Above plus use 128bit vector instruction to clear the full vector
758 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
761 static int optimize_for_space
= 0;
763 /* Register prefix used for error message. */
764 static const char *register_prefix
= "%";
766 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
767 leave, push, and pop instructions so that gcc has the same stack
768 frame as in 32 bit mode. */
769 static char stackop_size
= '\0';
771 /* Non-zero to optimize code alignment. */
772 int optimize_align_code
= 1;
774 /* Non-zero to quieten some warnings. */
775 static int quiet_warnings
= 0;
778 static const char *cpu_arch_name
= NULL
;
779 static char *cpu_sub_arch_name
= NULL
;
781 /* CPU feature flags. */
782 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
784 /* If we have selected a cpu we are generating instructions for. */
785 static int cpu_arch_tune_set
= 0;
787 /* Cpu we are generating instructions for. */
788 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
790 /* CPU feature flags of cpu we are generating instructions for. */
791 static i386_cpu_flags cpu_arch_tune_flags
;
793 /* CPU instruction set architecture used. */
794 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
796 /* CPU feature flags of instruction set architecture used. */
797 i386_cpu_flags cpu_arch_isa_flags
;
799 /* If set, conditional jumps are not automatically promoted to handle
800 larger than a byte offset. */
801 static unsigned int no_cond_jump_promotion
= 0;
803 /* Encode SSE instructions with VEX prefix. */
804 static unsigned int sse2avx
;
806 /* Encode scalar AVX instructions with specific vector length. */
813 /* Encode VEX WIG instructions with specific vex.w. */
820 /* Encode scalar EVEX LIG instructions with specific vector length. */
828 /* Encode EVEX WIG instructions with specific evex.w. */
835 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
836 static enum rc_type evexrcig
= rne
;
838 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
839 static symbolS
*GOT_symbol
;
841 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
842 unsigned int x86_dwarf2_return_column
;
844 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
845 int x86_cie_data_alignment
;
847 /* Interface to relax_segment.
848 There are 3 major relax states for 386 jump insns because the
849 different types of jumps add different sizes to frags when we're
850 figuring out what sort of jump to choose to reach a given label.
852 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
853 branches which are handled by md_estimate_size_before_relax() and
854 i386_generic_table_relax_frag(). */
857 #define UNCOND_JUMP 0
859 #define COND_JUMP86 2
860 #define BRANCH_PADDING 3
861 #define BRANCH_PREFIX 4
862 #define FUSED_JCC_PADDING 5
867 #define SMALL16 (SMALL | CODE16)
869 #define BIG16 (BIG | CODE16)
873 #define INLINE __inline__
879 #define ENCODE_RELAX_STATE(type, size) \
880 ((relax_substateT) (((type) << 2) | (size)))
881 #define TYPE_FROM_RELAX_STATE(s) \
883 #define DISP_SIZE_FROM_RELAX_STATE(s) \
884 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
886 /* This table is used by relax_frag to promote short jumps to long
887 ones where necessary. SMALL (short) jumps may be promoted to BIG
888 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
889 don't allow a short jump in a 32 bit code segment to be promoted to
890 a 16 bit offset jump because it's slower (requires data size
891 prefix), and doesn't work, unless the destination is in the bottom
892 64k of the code segment (The top 16 bits of eip are zeroed). */
894 const relax_typeS md_relax_table
[] =
897 1) most positive reach of this state,
898 2) most negative reach of this state,
899 3) how many bytes this mode will have in the variable part of the frag
900 4) which index into the table to try if we can't fit into this one. */
902 /* UNCOND_JUMP states. */
903 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
904 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
905 /* dword jmp adds 4 bytes to frag:
906 0 extra opcode bytes, 4 displacement bytes. */
908 /* word jmp adds 2 byte2 to frag:
909 0 extra opcode bytes, 2 displacement bytes. */
912 /* COND_JUMP states. */
913 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
914 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
915 /* dword conditionals adds 5 bytes to frag:
916 1 extra opcode byte, 4 displacement bytes. */
918 /* word conditionals add 3 bytes to frag:
919 1 extra opcode byte, 2 displacement bytes. */
922 /* COND_JUMP86 states. */
923 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
924 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
925 /* dword conditionals adds 5 bytes to frag:
926 1 extra opcode byte, 4 displacement bytes. */
928 /* word conditionals add 4 bytes to frag:
929 1 displacement byte and a 3 byte long branch insn. */
933 static const arch_entry cpu_arch
[] =
935 /* Do not replace the first two entries - i386_target_format()
936 relies on them being there in this order. */
937 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
938 CPU_GENERIC32_FLAGS
, 0 },
939 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
940 CPU_GENERIC64_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
949 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
951 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
953 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
955 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
957 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
958 CPU_PENTIUMPRO_FLAGS
, 0 },
959 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
961 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
963 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
965 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
967 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
968 CPU_NOCONA_FLAGS
, 0 },
969 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
971 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
973 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
974 CPU_CORE2_FLAGS
, 1 },
975 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
976 CPU_CORE2_FLAGS
, 0 },
977 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
978 CPU_COREI7_FLAGS
, 0 },
979 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
981 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
983 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
984 CPU_IAMCU_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
987 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
989 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
990 CPU_ATHLON_FLAGS
, 0 },
991 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
993 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
995 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
997 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
998 CPU_AMDFAM10_FLAGS
, 0 },
999 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1000 CPU_BDVER1_FLAGS
, 0 },
1001 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1002 CPU_BDVER2_FLAGS
, 0 },
1003 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1004 CPU_BDVER3_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1006 CPU_BDVER4_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1008 CPU_ZNVER1_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1010 CPU_ZNVER2_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1012 CPU_BTVER1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1014 CPU_BTVER2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1016 CPU_8087_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1021 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1024 CPU_CMOV_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1026 CPU_FXSR_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1029 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1032 CPU_SSE2_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1034 CPU_SSE3_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1036 CPU_SSE4A_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1038 CPU_SSSE3_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE4_1_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1042 CPU_SSE4_2_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4_2_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1047 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX2_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512F_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX512CD_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512ER_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512PF_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512DQ_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512BW_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512VL_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1066 CPU_VMFUNC_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1070 CPU_XSAVE_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1072 CPU_XSAVEOPT_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1074 CPU_XSAVEC_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1076 CPU_XSAVES_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1079 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1080 CPU_PCLMUL_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1082 CPU_PCLMUL_FLAGS
, 1 },
1083 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1084 CPU_FSGSBASE_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1086 CPU_RDRND_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1088 CPU_F16C_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1090 CPU_BMI2_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1093 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1094 CPU_FMA4_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1099 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1100 CPU_MOVBE_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1102 CPU_CX16_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1106 CPU_LZCNT_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1108 CPU_POPCNT_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1111 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1114 CPU_INVPCID_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1116 CPU_CLFLUSH_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1119 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1120 CPU_SYSCALL_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1122 CPU_RDTSCP_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1124 CPU_3DNOW_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1126 CPU_3DNOWA_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1128 CPU_PADLOCK_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1130 CPU_SVME_FLAGS
, 1 },
1131 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1132 CPU_SVME_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1134 CPU_SSE4A_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1137 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1139 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1141 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1143 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1144 CPU_RDSEED_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1146 CPU_PRFCHW_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1148 CPU_SMAP_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1151 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1153 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1154 CPU_CLFLUSHOPT_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1156 CPU_PREFETCHWT1_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1159 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1160 CPU_CLWB_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1162 CPU_AVX512IFMA_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1164 CPU_AVX512VBMI_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1166 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512_VBMI2_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_VNNI_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_BITALG_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1178 CPU_CLZERO_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1180 CPU_MWAITX_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1182 CPU_OSPKE_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1184 CPU_RDPID_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1186 CPU_PTWRITE_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1189 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1190 CPU_SHSTK_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1192 CPU_GFNI_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1194 CPU_VAES_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1196 CPU_VPCLMULQDQ_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1198 CPU_WBNOINVD_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1200 CPU_PCONFIG_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1202 CPU_WAITPKG_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1204 CPU_CLDEMOTE_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1206 CPU_MOVDIRI_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1208 CPU_MOVDIR64B_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1210 CPU_AVX512_BF16_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1212 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1214 CPU_ENQCMD_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1216 CPU_SERIALIZE_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1218 CPU_RDPRU_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1220 CPU_MCOMMIT_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1222 CPU_SEV_ES_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1224 CPU_TSXLDTRK_FLAGS
, 0 },
1227 static const noarch_entry cpu_noarch
[] =
1229 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1230 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1231 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1232 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1233 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1234 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1235 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1236 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1237 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1238 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1239 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1240 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1241 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1242 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1243 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1244 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1245 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1246 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1247 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1248 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1249 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1250 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1251 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1252 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1253 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1254 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1255 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1256 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1257 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1258 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1260 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1261 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1262 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1263 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1264 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1267 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1268 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1269 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1270 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1274 /* Like s_lcomm_internal in gas/read.c but the alignment string
1275 is allowed to be optional. */
1278 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1285 && *input_line_pointer
== ',')
1287 align
= parse_align (needs_align
- 1);
1289 if (align
== (addressT
) -1)
1304 bss_alloc (symbolP
, size
, align
);
1309 pe_lcomm (int needs_align
)
1311 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1315 const pseudo_typeS md_pseudo_table
[] =
1317 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1318 {"align", s_align_bytes
, 0},
1320 {"align", s_align_ptwo
, 0},
1322 {"arch", set_cpu_arch
, 0},
1326 {"lcomm", pe_lcomm
, 1},
1328 {"ffloat", float_cons
, 'f'},
1329 {"dfloat", float_cons
, 'd'},
1330 {"tfloat", float_cons
, 'x'},
1332 {"slong", signed_cons
, 4},
1333 {"noopt", s_ignore
, 0},
1334 {"optim", s_ignore
, 0},
1335 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1336 {"code16", set_code_flag
, CODE_16BIT
},
1337 {"code32", set_code_flag
, CODE_32BIT
},
1339 {"code64", set_code_flag
, CODE_64BIT
},
1341 {"intel_syntax", set_intel_syntax
, 1},
1342 {"att_syntax", set_intel_syntax
, 0},
1343 {"intel_mnemonic", set_intel_mnemonic
, 1},
1344 {"att_mnemonic", set_intel_mnemonic
, 0},
1345 {"allow_index_reg", set_allow_index_reg
, 1},
1346 {"disallow_index_reg", set_allow_index_reg
, 0},
1347 {"sse_check", set_check
, 0},
1348 {"operand_check", set_check
, 1},
1349 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1350 {"largecomm", handle_large_common
, 0},
1352 {"file", dwarf2_directive_file
, 0},
1353 {"loc", dwarf2_directive_loc
, 0},
1354 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1357 {"secrel32", pe_directive_secrel
, 0},
1362 /* For interface with expression (). */
1363 extern char *input_line_pointer
;
1365 /* Hash table for instruction mnemonic lookup. */
1366 static struct hash_control
*op_hash
;
1368 /* Hash table for register lookup. */
1369 static struct hash_control
*reg_hash
;
1371 /* Various efficient no-op patterns for aligning code labels.
1372 Note: Don't try to assemble the instructions in the comments.
1373 0L and 0w are not legal. */
1374 static const unsigned char f32_1
[] =
1376 static const unsigned char f32_2
[] =
1377 {0x66,0x90}; /* xchg %ax,%ax */
1378 static const unsigned char f32_3
[] =
1379 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1380 static const unsigned char f32_4
[] =
1381 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1382 static const unsigned char f32_6
[] =
1383 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1384 static const unsigned char f32_7
[] =
1385 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1386 static const unsigned char f16_3
[] =
1387 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1388 static const unsigned char f16_4
[] =
1389 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1390 static const unsigned char jump_disp8
[] =
1391 {0xeb}; /* jmp disp8 */
1392 static const unsigned char jump32_disp32
[] =
1393 {0xe9}; /* jmp disp32 */
1394 static const unsigned char jump16_disp32
[] =
1395 {0x66,0xe9}; /* jmp disp32 */
1396 /* 32-bit NOPs patterns. */
1397 static const unsigned char *const f32_patt
[] = {
1398 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1400 /* 16-bit NOPs patterns. */
1401 static const unsigned char *const f16_patt
[] = {
1402 f32_1
, f32_2
, f16_3
, f16_4
1404 /* nopl (%[re]ax) */
1405 static const unsigned char alt_3
[] =
1407 /* nopl 0(%[re]ax) */
1408 static const unsigned char alt_4
[] =
1409 {0x0f,0x1f,0x40,0x00};
1410 /* nopl 0(%[re]ax,%[re]ax,1) */
1411 static const unsigned char alt_5
[] =
1412 {0x0f,0x1f,0x44,0x00,0x00};
1413 /* nopw 0(%[re]ax,%[re]ax,1) */
1414 static const unsigned char alt_6
[] =
1415 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1416 /* nopl 0L(%[re]ax) */
1417 static const unsigned char alt_7
[] =
1418 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1419 /* nopl 0L(%[re]ax,%[re]ax,1) */
1420 static const unsigned char alt_8
[] =
1421 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1422 /* nopw 0L(%[re]ax,%[re]ax,1) */
1423 static const unsigned char alt_9
[] =
1424 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1425 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1426 static const unsigned char alt_10
[] =
1427 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1428 /* data16 nopw %cs:0L(%eax,%eax,1) */
1429 static const unsigned char alt_11
[] =
1430 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1431 /* 32-bit and 64-bit NOPs patterns. */
1432 static const unsigned char *const alt_patt
[] = {
1433 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1434 alt_9
, alt_10
, alt_11
1437 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1438 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1441 i386_output_nops (char *where
, const unsigned char *const *patt
,
1442 int count
, int max_single_nop_size
)
1445 /* Place the longer NOP first. */
1448 const unsigned char *nops
;
1450 if (max_single_nop_size
< 1)
1452 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1453 max_single_nop_size
);
1457 nops
= patt
[max_single_nop_size
- 1];
1459 /* Use the smaller one if the requsted one isn't available. */
1462 max_single_nop_size
--;
1463 nops
= patt
[max_single_nop_size
- 1];
1466 last
= count
% max_single_nop_size
;
1469 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1470 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1474 nops
= patt
[last
- 1];
1477 /* Use the smaller one plus one-byte NOP if the needed one
1480 nops
= patt
[last
- 1];
1481 memcpy (where
+ offset
, nops
, last
);
1482 where
[offset
+ last
] = *patt
[0];
1485 memcpy (where
+ offset
, nops
, last
);
1490 fits_in_imm7 (offsetT num
)
1492 return (num
& 0x7f) == num
;
1496 fits_in_imm31 (offsetT num
)
1498 return (num
& 0x7fffffff) == num
;
1501 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1502 single NOP instruction LIMIT. */
1505 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1507 const unsigned char *const *patt
= NULL
;
1508 int max_single_nop_size
;
1509 /* Maximum number of NOPs before switching to jump over NOPs. */
1510 int max_number_of_nops
;
1512 switch (fragP
->fr_type
)
1517 case rs_machine_dependent
:
1518 /* Allow NOP padding for jumps and calls. */
1519 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1520 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1527 /* We need to decide which NOP sequence to use for 32bit and
1528 64bit. When -mtune= is used:
1530 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1531 PROCESSOR_GENERIC32, f32_patt will be used.
1532 2. For the rest, alt_patt will be used.
1534 When -mtune= isn't used, alt_patt will be used if
1535 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1538 When -march= or .arch is used, we can't use anything beyond
1539 cpu_arch_isa_flags. */
1541 if (flag_code
== CODE_16BIT
)
1544 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1545 /* Limit number of NOPs to 2 in 16-bit mode. */
1546 max_number_of_nops
= 2;
1550 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1552 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1553 switch (cpu_arch_tune
)
1555 case PROCESSOR_UNKNOWN
:
1556 /* We use cpu_arch_isa_flags to check if we SHOULD
1557 optimize with nops. */
1558 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1563 case PROCESSOR_PENTIUM4
:
1564 case PROCESSOR_NOCONA
:
1565 case PROCESSOR_CORE
:
1566 case PROCESSOR_CORE2
:
1567 case PROCESSOR_COREI7
:
1568 case PROCESSOR_L1OM
:
1569 case PROCESSOR_K1OM
:
1570 case PROCESSOR_GENERIC64
:
1572 case PROCESSOR_ATHLON
:
1574 case PROCESSOR_AMDFAM10
:
1576 case PROCESSOR_ZNVER
:
1580 case PROCESSOR_I386
:
1581 case PROCESSOR_I486
:
1582 case PROCESSOR_PENTIUM
:
1583 case PROCESSOR_PENTIUMPRO
:
1584 case PROCESSOR_IAMCU
:
1585 case PROCESSOR_GENERIC32
:
1592 switch (fragP
->tc_frag_data
.tune
)
1594 case PROCESSOR_UNKNOWN
:
1595 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1596 PROCESSOR_UNKNOWN. */
1600 case PROCESSOR_I386
:
1601 case PROCESSOR_I486
:
1602 case PROCESSOR_PENTIUM
:
1603 case PROCESSOR_IAMCU
:
1605 case PROCESSOR_ATHLON
:
1607 case PROCESSOR_AMDFAM10
:
1609 case PROCESSOR_ZNVER
:
1611 case PROCESSOR_GENERIC32
:
1612 /* We use cpu_arch_isa_flags to check if we CAN optimize
1614 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1619 case PROCESSOR_PENTIUMPRO
:
1620 case PROCESSOR_PENTIUM4
:
1621 case PROCESSOR_NOCONA
:
1622 case PROCESSOR_CORE
:
1623 case PROCESSOR_CORE2
:
1624 case PROCESSOR_COREI7
:
1625 case PROCESSOR_L1OM
:
1626 case PROCESSOR_K1OM
:
1627 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1632 case PROCESSOR_GENERIC64
:
1638 if (patt
== f32_patt
)
1640 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1641 /* Limit number of NOPs to 2 for older processors. */
1642 max_number_of_nops
= 2;
1646 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1647 /* Limit number of NOPs to 7 for newer processors. */
1648 max_number_of_nops
= 7;
1653 limit
= max_single_nop_size
;
1655 if (fragP
->fr_type
== rs_fill_nop
)
1657 /* Output NOPs for .nop directive. */
1658 if (limit
> max_single_nop_size
)
1660 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1661 _("invalid single nop size: %d "
1662 "(expect within [0, %d])"),
1663 limit
, max_single_nop_size
);
1667 else if (fragP
->fr_type
!= rs_machine_dependent
)
1668 fragP
->fr_var
= count
;
1670 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1672 /* Generate jump over NOPs. */
1673 offsetT disp
= count
- 2;
1674 if (fits_in_imm7 (disp
))
1676 /* Use "jmp disp8" if possible. */
1678 where
[0] = jump_disp8
[0];
1684 unsigned int size_of_jump
;
1686 if (flag_code
== CODE_16BIT
)
1688 where
[0] = jump16_disp32
[0];
1689 where
[1] = jump16_disp32
[1];
1694 where
[0] = jump32_disp32
[0];
1698 count
-= size_of_jump
+ 4;
1699 if (!fits_in_imm31 (count
))
1701 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1702 _("jump over nop padding out of range"));
1706 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1707 where
+= size_of_jump
+ 4;
1711 /* Generate multiple NOPs. */
1712 i386_output_nops (where
, patt
, count
, limit
);
1716 operand_type_all_zero (const union i386_operand_type
*x
)
1718 switch (ARRAY_SIZE(x
->array
))
1729 return !x
->array
[0];
1736 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1738 switch (ARRAY_SIZE(x
->array
))
1754 x
->bitfield
.class = ClassNone
;
1755 x
->bitfield
.instance
= InstanceNone
;
1759 operand_type_equal (const union i386_operand_type
*x
,
1760 const union i386_operand_type
*y
)
1762 switch (ARRAY_SIZE(x
->array
))
1765 if (x
->array
[2] != y
->array
[2])
1769 if (x
->array
[1] != y
->array
[1])
1773 return x
->array
[0] == y
->array
[0];
1781 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1783 switch (ARRAY_SIZE(x
->array
))
1798 return !x
->array
[0];
1805 cpu_flags_equal (const union i386_cpu_flags
*x
,
1806 const union i386_cpu_flags
*y
)
1808 switch (ARRAY_SIZE(x
->array
))
1811 if (x
->array
[3] != y
->array
[3])
1815 if (x
->array
[2] != y
->array
[2])
1819 if (x
->array
[1] != y
->array
[1])
1823 return x
->array
[0] == y
->array
[0];
1831 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1833 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1834 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1837 static INLINE i386_cpu_flags
1838 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1840 switch (ARRAY_SIZE (x
.array
))
1843 x
.array
[3] &= y
.array
[3];
1846 x
.array
[2] &= y
.array
[2];
1849 x
.array
[1] &= y
.array
[1];
1852 x
.array
[0] &= y
.array
[0];
1860 static INLINE i386_cpu_flags
1861 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1863 switch (ARRAY_SIZE (x
.array
))
1866 x
.array
[3] |= y
.array
[3];
1869 x
.array
[2] |= y
.array
[2];
1872 x
.array
[1] |= y
.array
[1];
1875 x
.array
[0] |= y
.array
[0];
1883 static INLINE i386_cpu_flags
1884 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1886 switch (ARRAY_SIZE (x
.array
))
1889 x
.array
[3] &= ~y
.array
[3];
1892 x
.array
[2] &= ~y
.array
[2];
1895 x
.array
[1] &= ~y
.array
[1];
1898 x
.array
[0] &= ~y
.array
[0];
1906 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1908 #define CPU_FLAGS_ARCH_MATCH 0x1
1909 #define CPU_FLAGS_64BIT_MATCH 0x2
1911 #define CPU_FLAGS_PERFECT_MATCH \
1912 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1914 /* Return CPU flags match bits. */
1917 cpu_flags_match (const insn_template
*t
)
1919 i386_cpu_flags x
= t
->cpu_flags
;
1920 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1922 x
.bitfield
.cpu64
= 0;
1923 x
.bitfield
.cpuno64
= 0;
1925 if (cpu_flags_all_zero (&x
))
1927 /* This instruction is available on all archs. */
1928 match
|= CPU_FLAGS_ARCH_MATCH
;
1932 /* This instruction is available only on some archs. */
1933 i386_cpu_flags cpu
= cpu_arch_flags
;
1935 /* AVX512VL is no standalone feature - match it and then strip it. */
1936 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1938 x
.bitfield
.cpuavx512vl
= 0;
1940 cpu
= cpu_flags_and (x
, cpu
);
1941 if (!cpu_flags_all_zero (&cpu
))
1943 if (x
.bitfield
.cpuavx
)
1945 /* We need to check a few extra flags with AVX. */
1946 if (cpu
.bitfield
.cpuavx
1947 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1948 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1949 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1950 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1951 match
|= CPU_FLAGS_ARCH_MATCH
;
1953 else if (x
.bitfield
.cpuavx512f
)
1955 /* We need to check a few extra flags with AVX512F. */
1956 if (cpu
.bitfield
.cpuavx512f
1957 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1958 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1959 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1960 match
|= CPU_FLAGS_ARCH_MATCH
;
1963 match
|= CPU_FLAGS_ARCH_MATCH
;
1969 static INLINE i386_operand_type
1970 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1972 if (x
.bitfield
.class != y
.bitfield
.class)
1973 x
.bitfield
.class = ClassNone
;
1974 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1975 x
.bitfield
.instance
= InstanceNone
;
1977 switch (ARRAY_SIZE (x
.array
))
1980 x
.array
[2] &= y
.array
[2];
1983 x
.array
[1] &= y
.array
[1];
1986 x
.array
[0] &= y
.array
[0];
1994 static INLINE i386_operand_type
1995 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1997 gas_assert (y
.bitfield
.class == ClassNone
);
1998 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2000 switch (ARRAY_SIZE (x
.array
))
2003 x
.array
[2] &= ~y
.array
[2];
2006 x
.array
[1] &= ~y
.array
[1];
2009 x
.array
[0] &= ~y
.array
[0];
2017 static INLINE i386_operand_type
2018 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2020 gas_assert (x
.bitfield
.class == ClassNone
||
2021 y
.bitfield
.class == ClassNone
||
2022 x
.bitfield
.class == y
.bitfield
.class);
2023 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2024 y
.bitfield
.instance
== InstanceNone
||
2025 x
.bitfield
.instance
== y
.bitfield
.instance
);
2027 switch (ARRAY_SIZE (x
.array
))
2030 x
.array
[2] |= y
.array
[2];
2033 x
.array
[1] |= y
.array
[1];
2036 x
.array
[0] |= y
.array
[0];
2044 static INLINE i386_operand_type
2045 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2047 gas_assert (y
.bitfield
.class == ClassNone
);
2048 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2050 switch (ARRAY_SIZE (x
.array
))
2053 x
.array
[2] ^= y
.array
[2];
2056 x
.array
[1] ^= y
.array
[1];
2059 x
.array
[0] ^= y
.array
[0];
2067 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2068 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2069 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2070 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2071 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2072 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2073 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2074 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2075 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2076 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2077 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2078 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2079 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2080 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2081 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2082 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2083 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2094 operand_type_check (i386_operand_type t
, enum operand_type c
)
2099 return t
.bitfield
.class == Reg
;
2102 return (t
.bitfield
.imm8
2106 || t
.bitfield
.imm32s
2107 || t
.bitfield
.imm64
);
2110 return (t
.bitfield
.disp8
2111 || t
.bitfield
.disp16
2112 || t
.bitfield
.disp32
2113 || t
.bitfield
.disp32s
2114 || t
.bitfield
.disp64
);
2117 return (t
.bitfield
.disp8
2118 || t
.bitfield
.disp16
2119 || t
.bitfield
.disp32
2120 || t
.bitfield
.disp32s
2121 || t
.bitfield
.disp64
2122 || t
.bitfield
.baseindex
);
2131 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2132 between operand GIVEN and opeand WANTED for instruction template T. */
2135 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2138 return !((i
.types
[given
].bitfield
.byte
2139 && !t
->operand_types
[wanted
].bitfield
.byte
)
2140 || (i
.types
[given
].bitfield
.word
2141 && !t
->operand_types
[wanted
].bitfield
.word
)
2142 || (i
.types
[given
].bitfield
.dword
2143 && !t
->operand_types
[wanted
].bitfield
.dword
)
2144 || (i
.types
[given
].bitfield
.qword
2145 && !t
->operand_types
[wanted
].bitfield
.qword
)
2146 || (i
.types
[given
].bitfield
.tbyte
2147 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2150 /* Return 1 if there is no conflict in SIMD register between operand
2151 GIVEN and opeand WANTED for instruction template T. */
2154 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2157 return !((i
.types
[given
].bitfield
.xmmword
2158 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2159 || (i
.types
[given
].bitfield
.ymmword
2160 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2161 || (i
.types
[given
].bitfield
.zmmword
2162 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2165 /* Return 1 if there is no conflict in any size between operand GIVEN
2166 and opeand WANTED for instruction template T. */
2169 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2172 return (match_operand_size (t
, wanted
, given
)
2173 && !((i
.types
[given
].bitfield
.unspecified
2175 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2176 || (i
.types
[given
].bitfield
.fword
2177 && !t
->operand_types
[wanted
].bitfield
.fword
)
2178 /* For scalar opcode templates to allow register and memory
2179 operands at the same time, some special casing is needed
2180 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2181 down-conversion vpmov*. */
2182 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2183 && t
->operand_types
[wanted
].bitfield
.byte
2184 + t
->operand_types
[wanted
].bitfield
.word
2185 + t
->operand_types
[wanted
].bitfield
.dword
2186 + t
->operand_types
[wanted
].bitfield
.qword
2187 > !!t
->opcode_modifier
.broadcast
)
2188 ? (i
.types
[given
].bitfield
.xmmword
2189 || i
.types
[given
].bitfield
.ymmword
2190 || i
.types
[given
].bitfield
.zmmword
)
2191 : !match_simd_size(t
, wanted
, given
))));
2194 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2195 operands for instruction template T, and it has MATCH_REVERSE set if there
2196 is no size conflict on any operands for the template with operands reversed
2197 (and the template allows for reversing in the first place). */
2199 #define MATCH_STRAIGHT 1
2200 #define MATCH_REVERSE 2
2202 static INLINE
unsigned int
2203 operand_size_match (const insn_template
*t
)
2205 unsigned int j
, match
= MATCH_STRAIGHT
;
2207 /* Don't check non-absolute jump instructions. */
2208 if (t
->opcode_modifier
.jump
2209 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2212 /* Check memory and accumulator operand size. */
2213 for (j
= 0; j
< i
.operands
; j
++)
2215 if (i
.types
[j
].bitfield
.class != Reg
2216 && i
.types
[j
].bitfield
.class != RegSIMD
2217 && t
->opcode_modifier
.anysize
)
2220 if (t
->operand_types
[j
].bitfield
.class == Reg
2221 && !match_operand_size (t
, j
, j
))
2227 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2228 && !match_simd_size (t
, j
, j
))
2234 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2235 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2241 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2248 if (!t
->opcode_modifier
.d
)
2252 i
.error
= operand_size_mismatch
;
2256 /* Check reverse. */
2257 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2259 for (j
= 0; j
< i
.operands
; j
++)
2261 unsigned int given
= i
.operands
- j
- 1;
2263 if (t
->operand_types
[j
].bitfield
.class == Reg
2264 && !match_operand_size (t
, j
, given
))
2267 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2268 && !match_simd_size (t
, j
, given
))
2271 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2272 && (!match_operand_size (t
, j
, given
)
2273 || !match_simd_size (t
, j
, given
)))
2276 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2280 return match
| MATCH_REVERSE
;
2284 operand_type_match (i386_operand_type overlap
,
2285 i386_operand_type given
)
2287 i386_operand_type temp
= overlap
;
2289 temp
.bitfield
.unspecified
= 0;
2290 temp
.bitfield
.byte
= 0;
2291 temp
.bitfield
.word
= 0;
2292 temp
.bitfield
.dword
= 0;
2293 temp
.bitfield
.fword
= 0;
2294 temp
.bitfield
.qword
= 0;
2295 temp
.bitfield
.tbyte
= 0;
2296 temp
.bitfield
.xmmword
= 0;
2297 temp
.bitfield
.ymmword
= 0;
2298 temp
.bitfield
.zmmword
= 0;
2299 if (operand_type_all_zero (&temp
))
2302 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2306 i
.error
= operand_type_mismatch
;
2310 /* If given types g0 and g1 are registers they must be of the same type
2311 unless the expected operand type register overlap is null.
2312 Some Intel syntax memory operand size checking also happens here. */
2315 operand_type_register_match (i386_operand_type g0
,
2316 i386_operand_type t0
,
2317 i386_operand_type g1
,
2318 i386_operand_type t1
)
2320 if (g0
.bitfield
.class != Reg
2321 && g0
.bitfield
.class != RegSIMD
2322 && (!operand_type_check (g0
, anymem
)
2323 || g0
.bitfield
.unspecified
2324 || (t0
.bitfield
.class != Reg
2325 && t0
.bitfield
.class != RegSIMD
)))
2328 if (g1
.bitfield
.class != Reg
2329 && g1
.bitfield
.class != RegSIMD
2330 && (!operand_type_check (g1
, anymem
)
2331 || g1
.bitfield
.unspecified
2332 || (t1
.bitfield
.class != Reg
2333 && t1
.bitfield
.class != RegSIMD
)))
2336 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2337 && g0
.bitfield
.word
== g1
.bitfield
.word
2338 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2339 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2340 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2341 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2342 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2345 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2346 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2347 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2348 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2349 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2350 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2351 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2354 i
.error
= register_type_mismatch
;
2359 static INLINE
unsigned int
2360 register_number (const reg_entry
*r
)
2362 unsigned int nr
= r
->reg_num
;
2364 if (r
->reg_flags
& RegRex
)
2367 if (r
->reg_flags
& RegVRex
)
2373 static INLINE
unsigned int
2374 mode_from_disp_size (i386_operand_type t
)
2376 if (t
.bitfield
.disp8
)
2378 else if (t
.bitfield
.disp16
2379 || t
.bitfield
.disp32
2380 || t
.bitfield
.disp32s
)
2387 fits_in_signed_byte (addressT num
)
2389 return num
+ 0x80 <= 0xff;
2393 fits_in_unsigned_byte (addressT num
)
2399 fits_in_unsigned_word (addressT num
)
2401 return num
<= 0xffff;
2405 fits_in_signed_word (addressT num
)
2407 return num
+ 0x8000 <= 0xffff;
2411 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2416 return num
+ 0x80000000 <= 0xffffffff;
2418 } /* fits_in_signed_long() */
2421 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2426 return num
<= 0xffffffff;
2428 } /* fits_in_unsigned_long() */
2431 fits_in_disp8 (offsetT num
)
2433 int shift
= i
.memshift
;
2439 mask
= (1 << shift
) - 1;
2441 /* Return 0 if NUM isn't properly aligned. */
2445 /* Check if NUM will fit in 8bit after shift. */
2446 return fits_in_signed_byte (num
>> shift
);
2450 fits_in_imm4 (offsetT num
)
2452 return (num
& 0xf) == num
;
2455 static i386_operand_type
2456 smallest_imm_type (offsetT num
)
2458 i386_operand_type t
;
2460 operand_type_set (&t
, 0);
2461 t
.bitfield
.imm64
= 1;
2463 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2465 /* This code is disabled on the 486 because all the Imm1 forms
2466 in the opcode table are slower on the i486. They're the
2467 versions with the implicitly specified single-position
2468 displacement, which has another syntax if you really want to
2470 t
.bitfield
.imm1
= 1;
2471 t
.bitfield
.imm8
= 1;
2472 t
.bitfield
.imm8s
= 1;
2473 t
.bitfield
.imm16
= 1;
2474 t
.bitfield
.imm32
= 1;
2475 t
.bitfield
.imm32s
= 1;
2477 else if (fits_in_signed_byte (num
))
2479 t
.bitfield
.imm8
= 1;
2480 t
.bitfield
.imm8s
= 1;
2481 t
.bitfield
.imm16
= 1;
2482 t
.bitfield
.imm32
= 1;
2483 t
.bitfield
.imm32s
= 1;
2485 else if (fits_in_unsigned_byte (num
))
2487 t
.bitfield
.imm8
= 1;
2488 t
.bitfield
.imm16
= 1;
2489 t
.bitfield
.imm32
= 1;
2490 t
.bitfield
.imm32s
= 1;
2492 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2494 t
.bitfield
.imm16
= 1;
2495 t
.bitfield
.imm32
= 1;
2496 t
.bitfield
.imm32s
= 1;
2498 else if (fits_in_signed_long (num
))
2500 t
.bitfield
.imm32
= 1;
2501 t
.bitfield
.imm32s
= 1;
2503 else if (fits_in_unsigned_long (num
))
2504 t
.bitfield
.imm32
= 1;
2510 offset_in_range (offsetT val
, int size
)
2516 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2517 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2518 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2520 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2526 /* If BFD64, sign extend val for 32bit address mode. */
2527 if (flag_code
!= CODE_64BIT
2528 || i
.prefix
[ADDR_PREFIX
])
2529 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2530 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2533 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2535 char buf1
[40], buf2
[40];
2537 sprint_value (buf1
, val
);
2538 sprint_value (buf2
, val
& mask
);
2539 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2554 a. PREFIX_EXIST if attempting to add a prefix where one from the
2555 same class already exists.
2556 b. PREFIX_LOCK if lock prefix is added.
2557 c. PREFIX_REP if rep/repne prefix is added.
2558 d. PREFIX_DS if ds prefix is added.
2559 e. PREFIX_OTHER if other prefix is added.
2562 static enum PREFIX_GROUP
2563 add_prefix (unsigned int prefix
)
2565 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2568 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2569 && flag_code
== CODE_64BIT
)
2571 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2572 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2573 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2574 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2585 case DS_PREFIX_OPCODE
:
2588 case CS_PREFIX_OPCODE
:
2589 case ES_PREFIX_OPCODE
:
2590 case FS_PREFIX_OPCODE
:
2591 case GS_PREFIX_OPCODE
:
2592 case SS_PREFIX_OPCODE
:
2596 case REPNE_PREFIX_OPCODE
:
2597 case REPE_PREFIX_OPCODE
:
2602 case LOCK_PREFIX_OPCODE
:
2611 case ADDR_PREFIX_OPCODE
:
2615 case DATA_PREFIX_OPCODE
:
2619 if (i
.prefix
[q
] != 0)
2627 i
.prefix
[q
] |= prefix
;
2630 as_bad (_("same type of prefix used twice"));
2636 update_code_flag (int value
, int check
)
2638 PRINTF_LIKE ((*as_error
));
2640 flag_code
= (enum flag_code
) value
;
2641 if (flag_code
== CODE_64BIT
)
2643 cpu_arch_flags
.bitfield
.cpu64
= 1;
2644 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2648 cpu_arch_flags
.bitfield
.cpu64
= 0;
2649 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2651 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2654 as_error
= as_fatal
;
2657 (*as_error
) (_("64bit mode not supported on `%s'."),
2658 cpu_arch_name
? cpu_arch_name
: default_arch
);
2660 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2663 as_error
= as_fatal
;
2666 (*as_error
) (_("32bit mode not supported on `%s'."),
2667 cpu_arch_name
? cpu_arch_name
: default_arch
);
2669 stackop_size
= '\0';
2673 set_code_flag (int value
)
2675 update_code_flag (value
, 0);
2679 set_16bit_gcc_code_flag (int new_code_flag
)
2681 flag_code
= (enum flag_code
) new_code_flag
;
2682 if (flag_code
!= CODE_16BIT
)
2684 cpu_arch_flags
.bitfield
.cpu64
= 0;
2685 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2686 stackop_size
= LONG_MNEM_SUFFIX
;
2690 set_intel_syntax (int syntax_flag
)
2692 /* Find out if register prefixing is specified. */
2693 int ask_naked_reg
= 0;
2696 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2699 int e
= get_symbol_name (&string
);
2701 if (strcmp (string
, "prefix") == 0)
2703 else if (strcmp (string
, "noprefix") == 0)
2706 as_bad (_("bad argument to syntax directive."));
2707 (void) restore_line_pointer (e
);
2709 demand_empty_rest_of_line ();
2711 intel_syntax
= syntax_flag
;
2713 if (ask_naked_reg
== 0)
2714 allow_naked_reg
= (intel_syntax
2715 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2717 allow_naked_reg
= (ask_naked_reg
< 0);
2719 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2721 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2722 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2723 register_prefix
= allow_naked_reg
? "" : "%";
2727 set_intel_mnemonic (int mnemonic_flag
)
2729 intel_mnemonic
= mnemonic_flag
;
2733 set_allow_index_reg (int flag
)
2735 allow_index_reg
= flag
;
2739 set_check (int what
)
2741 enum check_kind
*kind
;
2746 kind
= &operand_check
;
2757 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2760 int e
= get_symbol_name (&string
);
2762 if (strcmp (string
, "none") == 0)
2764 else if (strcmp (string
, "warning") == 0)
2765 *kind
= check_warning
;
2766 else if (strcmp (string
, "error") == 0)
2767 *kind
= check_error
;
2769 as_bad (_("bad argument to %s_check directive."), str
);
2770 (void) restore_line_pointer (e
);
2773 as_bad (_("missing argument for %s_check directive"), str
);
2775 demand_empty_rest_of_line ();
2779 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2780 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2782 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2783 static const char *arch
;
2785 /* Intel LIOM is only supported on ELF. */
2791 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2792 use default_arch. */
2793 arch
= cpu_arch_name
;
2795 arch
= default_arch
;
2798 /* If we are targeting Intel MCU, we must enable it. */
2799 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2800 || new_flag
.bitfield
.cpuiamcu
)
2803 /* If we are targeting Intel L1OM, we must enable it. */
2804 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2805 || new_flag
.bitfield
.cpul1om
)
2808 /* If we are targeting Intel K1OM, we must enable it. */
2809 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2810 || new_flag
.bitfield
.cpuk1om
)
2813 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2818 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2822 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2825 int e
= get_symbol_name (&string
);
2827 i386_cpu_flags flags
;
2829 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2831 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2833 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2837 cpu_arch_name
= cpu_arch
[j
].name
;
2838 cpu_sub_arch_name
= NULL
;
2839 cpu_arch_flags
= cpu_arch
[j
].flags
;
2840 if (flag_code
== CODE_64BIT
)
2842 cpu_arch_flags
.bitfield
.cpu64
= 1;
2843 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2847 cpu_arch_flags
.bitfield
.cpu64
= 0;
2848 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2850 cpu_arch_isa
= cpu_arch
[j
].type
;
2851 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2852 if (!cpu_arch_tune_set
)
2854 cpu_arch_tune
= cpu_arch_isa
;
2855 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2860 flags
= cpu_flags_or (cpu_arch_flags
,
2863 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2865 if (cpu_sub_arch_name
)
2867 char *name
= cpu_sub_arch_name
;
2868 cpu_sub_arch_name
= concat (name
,
2870 (const char *) NULL
);
2874 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2875 cpu_arch_flags
= flags
;
2876 cpu_arch_isa_flags
= flags
;
2880 = cpu_flags_or (cpu_arch_isa_flags
,
2882 (void) restore_line_pointer (e
);
2883 demand_empty_rest_of_line ();
2888 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2890 /* Disable an ISA extension. */
2891 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2892 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2894 flags
= cpu_flags_and_not (cpu_arch_flags
,
2895 cpu_noarch
[j
].flags
);
2896 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2898 if (cpu_sub_arch_name
)
2900 char *name
= cpu_sub_arch_name
;
2901 cpu_sub_arch_name
= concat (name
, string
,
2902 (const char *) NULL
);
2906 cpu_sub_arch_name
= xstrdup (string
);
2907 cpu_arch_flags
= flags
;
2908 cpu_arch_isa_flags
= flags
;
2910 (void) restore_line_pointer (e
);
2911 demand_empty_rest_of_line ();
2915 j
= ARRAY_SIZE (cpu_arch
);
2918 if (j
>= ARRAY_SIZE (cpu_arch
))
2919 as_bad (_("no such architecture: `%s'"), string
);
2921 *input_line_pointer
= e
;
2924 as_bad (_("missing cpu architecture"));
2926 no_cond_jump_promotion
= 0;
2927 if (*input_line_pointer
== ','
2928 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2933 ++input_line_pointer
;
2934 e
= get_symbol_name (&string
);
2936 if (strcmp (string
, "nojumps") == 0)
2937 no_cond_jump_promotion
= 1;
2938 else if (strcmp (string
, "jumps") == 0)
2941 as_bad (_("no such architecture modifier: `%s'"), string
);
2943 (void) restore_line_pointer (e
);
2946 demand_empty_rest_of_line ();
2949 enum bfd_architecture
2952 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2954 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2955 || flag_code
!= CODE_64BIT
)
2956 as_fatal (_("Intel L1OM is 64bit ELF only"));
2957 return bfd_arch_l1om
;
2959 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2961 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2962 || flag_code
!= CODE_64BIT
)
2963 as_fatal (_("Intel K1OM is 64bit ELF only"));
2964 return bfd_arch_k1om
;
2966 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2968 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2969 || flag_code
== CODE_64BIT
)
2970 as_fatal (_("Intel MCU is 32bit ELF only"));
2971 return bfd_arch_iamcu
;
2974 return bfd_arch_i386
;
2980 if (!strncmp (default_arch
, "x86_64", 6))
2982 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2984 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2985 || default_arch
[6] != '\0')
2986 as_fatal (_("Intel L1OM is 64bit ELF only"));
2987 return bfd_mach_l1om
;
2989 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2991 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2992 || default_arch
[6] != '\0')
2993 as_fatal (_("Intel K1OM is 64bit ELF only"));
2994 return bfd_mach_k1om
;
2996 else if (default_arch
[6] == '\0')
2997 return bfd_mach_x86_64
;
2999 return bfd_mach_x64_32
;
3001 else if (!strcmp (default_arch
, "i386")
3002 || !strcmp (default_arch
, "iamcu"))
3004 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3006 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3007 as_fatal (_("Intel MCU is 32bit ELF only"));
3008 return bfd_mach_i386_iamcu
;
3011 return bfd_mach_i386_i386
;
3014 as_fatal (_("unknown architecture"));
3020 const char *hash_err
;
3022 /* Support pseudo prefixes like {disp32}. */
3023 lex_type
['{'] = LEX_BEGIN_NAME
;
3025 /* Initialize op_hash hash table. */
3026 op_hash
= hash_new ();
3029 const insn_template
*optab
;
3030 templates
*core_optab
;
3032 /* Setup for loop. */
3034 core_optab
= XNEW (templates
);
3035 core_optab
->start
= optab
;
3040 if (optab
->name
== NULL
3041 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3043 /* different name --> ship out current template list;
3044 add to hash table; & begin anew. */
3045 core_optab
->end
= optab
;
3046 hash_err
= hash_insert (op_hash
,
3048 (void *) core_optab
);
3051 as_fatal (_("can't hash %s: %s"),
3055 if (optab
->name
== NULL
)
3057 core_optab
= XNEW (templates
);
3058 core_optab
->start
= optab
;
3063 /* Initialize reg_hash hash table. */
3064 reg_hash
= hash_new ();
3066 const reg_entry
*regtab
;
3067 unsigned int regtab_size
= i386_regtab_size
;
3069 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3071 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3073 as_fatal (_("can't hash %s: %s"),
3079 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3084 for (c
= 0; c
< 256; c
++)
3089 mnemonic_chars
[c
] = c
;
3090 register_chars
[c
] = c
;
3091 operand_chars
[c
] = c
;
3093 else if (ISLOWER (c
))
3095 mnemonic_chars
[c
] = c
;
3096 register_chars
[c
] = c
;
3097 operand_chars
[c
] = c
;
3099 else if (ISUPPER (c
))
3101 mnemonic_chars
[c
] = TOLOWER (c
);
3102 register_chars
[c
] = mnemonic_chars
[c
];
3103 operand_chars
[c
] = c
;
3105 else if (c
== '{' || c
== '}')
3107 mnemonic_chars
[c
] = c
;
3108 operand_chars
[c
] = c
;
3111 if (ISALPHA (c
) || ISDIGIT (c
))
3112 identifier_chars
[c
] = c
;
3115 identifier_chars
[c
] = c
;
3116 operand_chars
[c
] = c
;
3121 identifier_chars
['@'] = '@';
3124 identifier_chars
['?'] = '?';
3125 operand_chars
['?'] = '?';
3127 digit_chars
['-'] = '-';
3128 mnemonic_chars
['_'] = '_';
3129 mnemonic_chars
['-'] = '-';
3130 mnemonic_chars
['.'] = '.';
3131 identifier_chars
['_'] = '_';
3132 identifier_chars
['.'] = '.';
3134 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3135 operand_chars
[(unsigned char) *p
] = *p
;
3138 if (flag_code
== CODE_64BIT
)
3140 #if defined (OBJ_COFF) && defined (TE_PE)
3141 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3144 x86_dwarf2_return_column
= 16;
3146 x86_cie_data_alignment
= -8;
3150 x86_dwarf2_return_column
= 8;
3151 x86_cie_data_alignment
= -4;
3154 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3155 can be turned into BRANCH_PREFIX frag. */
3156 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3161 i386_print_statistics (FILE *file
)
3163 hash_print_statistics (file
, "i386 opcode", op_hash
);
3164 hash_print_statistics (file
, "i386 register", reg_hash
);
3169 /* Debugging routines for md_assemble. */
3170 static void pte (insn_template
*);
3171 static void pt (i386_operand_type
);
3172 static void pe (expressionS
*);
3173 static void ps (symbolS
*);
3176 pi (const char *line
, i386_insn
*x
)
3180 fprintf (stdout
, "%s: template ", line
);
3182 fprintf (stdout
, " address: base %s index %s scale %x\n",
3183 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3184 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3185 x
->log2_scale_factor
);
3186 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3187 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3188 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3189 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3190 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3191 (x
->rex
& REX_W
) != 0,
3192 (x
->rex
& REX_R
) != 0,
3193 (x
->rex
& REX_X
) != 0,
3194 (x
->rex
& REX_B
) != 0);
3195 for (j
= 0; j
< x
->operands
; j
++)
3197 fprintf (stdout
, " #%d: ", j
+ 1);
3199 fprintf (stdout
, "\n");
3200 if (x
->types
[j
].bitfield
.class == Reg
3201 || x
->types
[j
].bitfield
.class == RegMMX
3202 || x
->types
[j
].bitfield
.class == RegSIMD
3203 || x
->types
[j
].bitfield
.class == RegMask
3204 || x
->types
[j
].bitfield
.class == SReg
3205 || x
->types
[j
].bitfield
.class == RegCR
3206 || x
->types
[j
].bitfield
.class == RegDR
3207 || x
->types
[j
].bitfield
.class == RegTR
3208 || x
->types
[j
].bitfield
.class == RegBND
)
3209 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3210 if (operand_type_check (x
->types
[j
], imm
))
3212 if (operand_type_check (x
->types
[j
], disp
))
3213 pe (x
->op
[j
].disps
);
3218 pte (insn_template
*t
)
3221 fprintf (stdout
, " %d operands ", t
->operands
);
3222 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3223 if (t
->extension_opcode
!= None
)
3224 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3225 if (t
->opcode_modifier
.d
)
3226 fprintf (stdout
, "D");
3227 if (t
->opcode_modifier
.w
)
3228 fprintf (stdout
, "W");
3229 fprintf (stdout
, "\n");
3230 for (j
= 0; j
< t
->operands
; j
++)
3232 fprintf (stdout
, " #%d type ", j
+ 1);
3233 pt (t
->operand_types
[j
]);
3234 fprintf (stdout
, "\n");
3241 fprintf (stdout
, " operation %d\n", e
->X_op
);
3242 fprintf (stdout
, " add_number %ld (%lx)\n",
3243 (long) e
->X_add_number
, (long) e
->X_add_number
);
3244 if (e
->X_add_symbol
)
3246 fprintf (stdout
, " add_symbol ");
3247 ps (e
->X_add_symbol
);
3248 fprintf (stdout
, "\n");
3252 fprintf (stdout
, " op_symbol ");
3253 ps (e
->X_op_symbol
);
3254 fprintf (stdout
, "\n");
3261 fprintf (stdout
, "%s type %s%s",
3263 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3264 segment_name (S_GET_SEGMENT (s
)));
3267 static struct type_name
3269 i386_operand_type mask
;
3272 const type_names
[] =
3274 { OPERAND_TYPE_REG8
, "r8" },
3275 { OPERAND_TYPE_REG16
, "r16" },
3276 { OPERAND_TYPE_REG32
, "r32" },
3277 { OPERAND_TYPE_REG64
, "r64" },
3278 { OPERAND_TYPE_ACC8
, "acc8" },
3279 { OPERAND_TYPE_ACC16
, "acc16" },
3280 { OPERAND_TYPE_ACC32
, "acc32" },
3281 { OPERAND_TYPE_ACC64
, "acc64" },
3282 { OPERAND_TYPE_IMM8
, "i8" },
3283 { OPERAND_TYPE_IMM8
, "i8s" },
3284 { OPERAND_TYPE_IMM16
, "i16" },
3285 { OPERAND_TYPE_IMM32
, "i32" },
3286 { OPERAND_TYPE_IMM32S
, "i32s" },
3287 { OPERAND_TYPE_IMM64
, "i64" },
3288 { OPERAND_TYPE_IMM1
, "i1" },
3289 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3290 { OPERAND_TYPE_DISP8
, "d8" },
3291 { OPERAND_TYPE_DISP16
, "d16" },
3292 { OPERAND_TYPE_DISP32
, "d32" },
3293 { OPERAND_TYPE_DISP32S
, "d32s" },
3294 { OPERAND_TYPE_DISP64
, "d64" },
3295 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3296 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3297 { OPERAND_TYPE_CONTROL
, "control reg" },
3298 { OPERAND_TYPE_TEST
, "test reg" },
3299 { OPERAND_TYPE_DEBUG
, "debug reg" },
3300 { OPERAND_TYPE_FLOATREG
, "FReg" },
3301 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3302 { OPERAND_TYPE_SREG
, "SReg" },
3303 { OPERAND_TYPE_REGMMX
, "rMMX" },
3304 { OPERAND_TYPE_REGXMM
, "rXMM" },
3305 { OPERAND_TYPE_REGYMM
, "rYMM" },
3306 { OPERAND_TYPE_REGZMM
, "rZMM" },
3307 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3311 pt (i386_operand_type t
)
3314 i386_operand_type a
;
3316 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3318 a
= operand_type_and (t
, type_names
[j
].mask
);
3319 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3320 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3325 #endif /* DEBUG386 */
3327 static bfd_reloc_code_real_type
3328 reloc (unsigned int size
,
3331 bfd_reloc_code_real_type other
)
3333 if (other
!= NO_RELOC
)
3335 reloc_howto_type
*rel
;
3340 case BFD_RELOC_X86_64_GOT32
:
3341 return BFD_RELOC_X86_64_GOT64
;
3343 case BFD_RELOC_X86_64_GOTPLT64
:
3344 return BFD_RELOC_X86_64_GOTPLT64
;
3346 case BFD_RELOC_X86_64_PLTOFF64
:
3347 return BFD_RELOC_X86_64_PLTOFF64
;
3349 case BFD_RELOC_X86_64_GOTPC32
:
3350 other
= BFD_RELOC_X86_64_GOTPC64
;
3352 case BFD_RELOC_X86_64_GOTPCREL
:
3353 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3355 case BFD_RELOC_X86_64_TPOFF32
:
3356 other
= BFD_RELOC_X86_64_TPOFF64
;
3358 case BFD_RELOC_X86_64_DTPOFF32
:
3359 other
= BFD_RELOC_X86_64_DTPOFF64
;
3365 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3366 if (other
== BFD_RELOC_SIZE32
)
3369 other
= BFD_RELOC_SIZE64
;
3372 as_bad (_("there are no pc-relative size relocations"));
3378 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3379 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3382 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3384 as_bad (_("unknown relocation (%u)"), other
);
3385 else if (size
!= bfd_get_reloc_size (rel
))
3386 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3387 bfd_get_reloc_size (rel
),
3389 else if (pcrel
&& !rel
->pc_relative
)
3390 as_bad (_("non-pc-relative relocation for pc-relative field"));
3391 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3393 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3395 as_bad (_("relocated field and relocation type differ in signedness"));
3404 as_bad (_("there are no unsigned pc-relative relocations"));
3407 case 1: return BFD_RELOC_8_PCREL
;
3408 case 2: return BFD_RELOC_16_PCREL
;
3409 case 4: return BFD_RELOC_32_PCREL
;
3410 case 8: return BFD_RELOC_64_PCREL
;
3412 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3419 case 4: return BFD_RELOC_X86_64_32S
;
3424 case 1: return BFD_RELOC_8
;
3425 case 2: return BFD_RELOC_16
;
3426 case 4: return BFD_RELOC_32
;
3427 case 8: return BFD_RELOC_64
;
3429 as_bad (_("cannot do %s %u byte relocation"),
3430 sign
> 0 ? "signed" : "unsigned", size
);
3436 /* Here we decide which fixups can be adjusted to make them relative to
3437 the beginning of the section instead of the symbol. Basically we need
3438 to make sure that the dynamic relocations are done correctly, so in
3439 some cases we force the original symbol to be used. */
3442 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3444 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3448 /* Don't adjust pc-relative references to merge sections in 64-bit
3450 if (use_rela_relocations
3451 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3455 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3456 and changed later by validate_fix. */
3457 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3458 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3461 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3462 for size relocations. */
3463 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3464 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3465 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3466 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3467 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3468 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3473 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3474 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3475 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3492 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3493 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3500 intel_float_operand (const char *mnemonic
)
3502 /* Note that the value returned is meaningful only for opcodes with (memory)
3503 operands, hence the code here is free to improperly handle opcodes that
3504 have no operands (for better performance and smaller code). */
3506 if (mnemonic
[0] != 'f')
3507 return 0; /* non-math */
3509 switch (mnemonic
[1])
3511 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3512 the fs segment override prefix not currently handled because no
3513 call path can make opcodes without operands get here */
3515 return 2 /* integer op */;
3517 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3518 return 3; /* fldcw/fldenv */
3521 if (mnemonic
[2] != 'o' /* fnop */)
3522 return 3; /* non-waiting control op */
3525 if (mnemonic
[2] == 's')
3526 return 3; /* frstor/frstpm */
3529 if (mnemonic
[2] == 'a')
3530 return 3; /* fsave */
3531 if (mnemonic
[2] == 't')
3533 switch (mnemonic
[3])
3535 case 'c': /* fstcw */
3536 case 'd': /* fstdw */
3537 case 'e': /* fstenv */
3538 case 's': /* fsts[gw] */
3544 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3545 return 0; /* fxsave/fxrstor are not really math ops */
3552 /* Build the VEX prefix. */
3555 build_vex_prefix (const insn_template
*t
)
3557 unsigned int register_specifier
;
3558 unsigned int implied_prefix
;
3559 unsigned int vector_length
;
3562 /* Check register specifier. */
3563 if (i
.vex
.register_specifier
)
3565 register_specifier
=
3566 ~register_number (i
.vex
.register_specifier
) & 0xf;
3567 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3570 register_specifier
= 0xf;
3572 /* Use 2-byte VEX prefix by swapping destination and source operand
3573 if there are more than 1 register operand. */
3574 if (i
.reg_operands
> 1
3575 && i
.vec_encoding
!= vex_encoding_vex3
3576 && i
.dir_encoding
== dir_encoding_default
3577 && i
.operands
== i
.reg_operands
3578 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3579 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3580 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3583 unsigned int xchg
= i
.operands
- 1;
3584 union i386_op temp_op
;
3585 i386_operand_type temp_type
;
3587 temp_type
= i
.types
[xchg
];
3588 i
.types
[xchg
] = i
.types
[0];
3589 i
.types
[0] = temp_type
;
3590 temp_op
= i
.op
[xchg
];
3591 i
.op
[xchg
] = i
.op
[0];
3594 gas_assert (i
.rm
.mode
== 3);
3598 i
.rm
.regmem
= i
.rm
.reg
;
3601 if (i
.tm
.opcode_modifier
.d
)
3602 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3603 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3604 else /* Use the next insn. */
3608 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3609 are no memory operands and at least 3 register ones. */
3610 if (i
.reg_operands
>= 3
3611 && i
.vec_encoding
!= vex_encoding_vex3
3612 && i
.reg_operands
== i
.operands
- i
.imm_operands
3613 && i
.tm
.opcode_modifier
.vex
3614 && i
.tm
.opcode_modifier
.commutative
3615 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3617 && i
.vex
.register_specifier
3618 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3620 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3621 union i386_op temp_op
;
3622 i386_operand_type temp_type
;
3624 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3625 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3626 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3627 &i
.types
[i
.operands
- 3]));
3628 gas_assert (i
.rm
.mode
== 3);
3630 temp_type
= i
.types
[xchg
];
3631 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3632 i
.types
[xchg
+ 1] = temp_type
;
3633 temp_op
= i
.op
[xchg
];
3634 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3635 i
.op
[xchg
+ 1] = temp_op
;
3638 xchg
= i
.rm
.regmem
| 8;
3639 i
.rm
.regmem
= ~register_specifier
& 0xf;
3640 gas_assert (!(i
.rm
.regmem
& 8));
3641 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3642 register_specifier
= ~xchg
& 0xf;
3645 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3646 vector_length
= avxscalar
;
3647 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3653 /* Determine vector length from the last multi-length vector
3656 for (op
= t
->operands
; op
--;)
3657 if (t
->operand_types
[op
].bitfield
.xmmword
3658 && t
->operand_types
[op
].bitfield
.ymmword
3659 && i
.types
[op
].bitfield
.ymmword
)
3666 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3671 case DATA_PREFIX_OPCODE
:
3674 case REPE_PREFIX_OPCODE
:
3677 case REPNE_PREFIX_OPCODE
:
3684 /* Check the REX.W bit and VEXW. */
3685 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3686 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3687 else if (i
.tm
.opcode_modifier
.vexw
)
3688 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3690 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3692 /* Use 2-byte VEX prefix if possible. */
3694 && i
.vec_encoding
!= vex_encoding_vex3
3695 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3696 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3698 /* 2-byte VEX prefix. */
3702 i
.vex
.bytes
[0] = 0xc5;
3704 /* Check the REX.R bit. */
3705 r
= (i
.rex
& REX_R
) ? 0 : 1;
3706 i
.vex
.bytes
[1] = (r
<< 7
3707 | register_specifier
<< 3
3708 | vector_length
<< 2
3713 /* 3-byte VEX prefix. */
3718 switch (i
.tm
.opcode_modifier
.vexopcode
)
3722 i
.vex
.bytes
[0] = 0xc4;
3726 i
.vex
.bytes
[0] = 0xc4;
3730 i
.vex
.bytes
[0] = 0xc4;
3734 i
.vex
.bytes
[0] = 0x8f;
3738 i
.vex
.bytes
[0] = 0x8f;
3742 i
.vex
.bytes
[0] = 0x8f;
3748 /* The high 3 bits of the second VEX byte are 1's compliment
3749 of RXB bits from REX. */
3750 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3752 i
.vex
.bytes
[2] = (w
<< 7
3753 | register_specifier
<< 3
3754 | vector_length
<< 2
3759 static INLINE bfd_boolean
3760 is_evex_encoding (const insn_template
*t
)
3762 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3763 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3764 || t
->opcode_modifier
.sae
;
3767 static INLINE bfd_boolean
3768 is_any_vex_encoding (const insn_template
*t
)
3770 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3771 || is_evex_encoding (t
);
3774 /* Build the EVEX prefix. */
3777 build_evex_prefix (void)
3779 unsigned int register_specifier
;
3780 unsigned int implied_prefix
;
3782 rex_byte vrex_used
= 0;
3784 /* Check register specifier. */
3785 if (i
.vex
.register_specifier
)
3787 gas_assert ((i
.vrex
& REX_X
) == 0);
3789 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3790 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3791 register_specifier
+= 8;
3792 /* The upper 16 registers are encoded in the fourth byte of the
3794 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3795 i
.vex
.bytes
[3] = 0x8;
3796 register_specifier
= ~register_specifier
& 0xf;
3800 register_specifier
= 0xf;
3802 /* Encode upper 16 vector index register in the fourth byte of
3804 if (!(i
.vrex
& REX_X
))
3805 i
.vex
.bytes
[3] = 0x8;
3810 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3815 case DATA_PREFIX_OPCODE
:
3818 case REPE_PREFIX_OPCODE
:
3821 case REPNE_PREFIX_OPCODE
:
3828 /* 4 byte EVEX prefix. */
3830 i
.vex
.bytes
[0] = 0x62;
3833 switch (i
.tm
.opcode_modifier
.vexopcode
)
3849 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3851 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3853 /* The fifth bit of the second EVEX byte is 1's compliment of the
3854 REX_R bit in VREX. */
3855 if (!(i
.vrex
& REX_R
))
3856 i
.vex
.bytes
[1] |= 0x10;
3860 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3862 /* When all operands are registers, the REX_X bit in REX is not
3863 used. We reuse it to encode the upper 16 registers, which is
3864 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3865 as 1's compliment. */
3866 if ((i
.vrex
& REX_B
))
3869 i
.vex
.bytes
[1] &= ~0x40;
3873 /* EVEX instructions shouldn't need the REX prefix. */
3874 i
.vrex
&= ~vrex_used
;
3875 gas_assert (i
.vrex
== 0);
3877 /* Check the REX.W bit and VEXW. */
3878 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3879 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3880 else if (i
.tm
.opcode_modifier
.vexw
)
3881 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3883 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3885 /* Encode the U bit. */
3886 implied_prefix
|= 0x4;
3888 /* The third byte of the EVEX prefix. */
3889 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3891 /* The fourth byte of the EVEX prefix. */
3892 /* The zeroing-masking bit. */
3893 if (i
.mask
&& i
.mask
->zeroing
)
3894 i
.vex
.bytes
[3] |= 0x80;
3896 /* Don't always set the broadcast bit if there is no RC. */
3899 /* Encode the vector length. */
3900 unsigned int vec_length
;
3902 if (!i
.tm
.opcode_modifier
.evex
3903 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3907 /* Determine vector length from the last multi-length vector
3910 for (op
= i
.operands
; op
--;)
3911 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3912 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3913 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3915 if (i
.types
[op
].bitfield
.zmmword
)
3917 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3920 else if (i
.types
[op
].bitfield
.ymmword
)
3922 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3925 else if (i
.types
[op
].bitfield
.xmmword
)
3927 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3930 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3932 switch (i
.broadcast
->bytes
)
3935 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3938 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3941 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3950 if (op
>= MAX_OPERANDS
)
3954 switch (i
.tm
.opcode_modifier
.evex
)
3956 case EVEXLIG
: /* LL' is ignored */
3957 vec_length
= evexlig
<< 5;
3960 vec_length
= 0 << 5;
3963 vec_length
= 1 << 5;
3966 vec_length
= 2 << 5;
3972 i
.vex
.bytes
[3] |= vec_length
;
3973 /* Encode the broadcast bit. */
3975 i
.vex
.bytes
[3] |= 0x10;
3979 if (i
.rounding
->type
!= saeonly
)
3980 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3982 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3985 if (i
.mask
&& i
.mask
->mask
)
3986 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3990 process_immext (void)
3994 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3995 which is coded in the same place as an 8-bit immediate field
3996 would be. Here we fake an 8-bit immediate operand from the
3997 opcode suffix stored in tm.extension_opcode.
3999 AVX instructions also use this encoding, for some of
4000 3 argument instructions. */
4002 gas_assert (i
.imm_operands
<= 1
4004 || (is_any_vex_encoding (&i
.tm
)
4005 && i
.operands
<= 4)));
4007 exp
= &im_expressions
[i
.imm_operands
++];
4008 i
.op
[i
.operands
].imms
= exp
;
4009 i
.types
[i
.operands
] = imm8
;
4011 exp
->X_op
= O_constant
;
4012 exp
->X_add_number
= i
.tm
.extension_opcode
;
4013 i
.tm
.extension_opcode
= None
;
4020 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4025 as_bad (_("invalid instruction `%s' after `%s'"),
4026 i
.tm
.name
, i
.hle_prefix
);
4029 if (i
.prefix
[LOCK_PREFIX
])
4031 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4035 case HLEPrefixRelease
:
4036 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4038 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4042 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4044 as_bad (_("memory destination needed for instruction `%s'"
4045 " after `xrelease'"), i
.tm
.name
);
4052 /* Try the shortest encoding by shortening operand size. */
4055 optimize_encoding (void)
4059 if (optimize_for_space
4060 && !is_any_vex_encoding (&i
.tm
)
4061 && i
.reg_operands
== 1
4062 && i
.imm_operands
== 1
4063 && !i
.types
[1].bitfield
.byte
4064 && i
.op
[0].imms
->X_op
== O_constant
4065 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4066 && (i
.tm
.base_opcode
== 0xa8
4067 || (i
.tm
.base_opcode
== 0xf6
4068 && i
.tm
.extension_opcode
== 0x0)))
4071 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4073 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4074 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4076 i
.types
[1].bitfield
.byte
= 1;
4077 /* Ignore the suffix. */
4079 /* Convert to byte registers. */
4080 if (i
.types
[1].bitfield
.word
)
4082 else if (i
.types
[1].bitfield
.dword
)
4086 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4091 else if (flag_code
== CODE_64BIT
4092 && !is_any_vex_encoding (&i
.tm
)
4093 && ((i
.types
[1].bitfield
.qword
4094 && i
.reg_operands
== 1
4095 && i
.imm_operands
== 1
4096 && i
.op
[0].imms
->X_op
== O_constant
4097 && ((i
.tm
.base_opcode
== 0xb8
4098 && i
.tm
.extension_opcode
== None
4099 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4100 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4101 && ((i
.tm
.base_opcode
== 0x24
4102 || i
.tm
.base_opcode
== 0xa8)
4103 || (i
.tm
.base_opcode
== 0x80
4104 && i
.tm
.extension_opcode
== 0x4)
4105 || ((i
.tm
.base_opcode
== 0xf6
4106 || (i
.tm
.base_opcode
| 1) == 0xc7)
4107 && i
.tm
.extension_opcode
== 0x0)))
4108 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4109 && i
.tm
.base_opcode
== 0x83
4110 && i
.tm
.extension_opcode
== 0x4)))
4111 || (i
.types
[0].bitfield
.qword
4112 && ((i
.reg_operands
== 2
4113 && i
.op
[0].regs
== i
.op
[1].regs
4114 && (i
.tm
.base_opcode
== 0x30
4115 || i
.tm
.base_opcode
== 0x28))
4116 || (i
.reg_operands
== 1
4118 && i
.tm
.base_opcode
== 0x30)))))
4121 andq $imm31, %r64 -> andl $imm31, %r32
4122 andq $imm7, %r64 -> andl $imm7, %r32
4123 testq $imm31, %r64 -> testl $imm31, %r32
4124 xorq %r64, %r64 -> xorl %r32, %r32
4125 subq %r64, %r64 -> subl %r32, %r32
4126 movq $imm31, %r64 -> movl $imm31, %r32
4127 movq $imm32, %r64 -> movl $imm32, %r32
4129 i
.tm
.opcode_modifier
.norex64
= 1;
4130 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4133 movq $imm31, %r64 -> movl $imm31, %r32
4134 movq $imm32, %r64 -> movl $imm32, %r32
4136 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4137 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4138 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4139 i
.types
[0].bitfield
.imm32
= 1;
4140 i
.types
[0].bitfield
.imm32s
= 0;
4141 i
.types
[0].bitfield
.imm64
= 0;
4142 i
.types
[1].bitfield
.dword
= 1;
4143 i
.types
[1].bitfield
.qword
= 0;
4144 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4147 movq $imm31, %r64 -> movl $imm31, %r32
4149 i
.tm
.base_opcode
= 0xb8;
4150 i
.tm
.extension_opcode
= None
;
4151 i
.tm
.opcode_modifier
.w
= 0;
4152 i
.tm
.opcode_modifier
.modrm
= 0;
4156 else if (optimize
> 1
4157 && !optimize_for_space
4158 && !is_any_vex_encoding (&i
.tm
)
4159 && i
.reg_operands
== 2
4160 && i
.op
[0].regs
== i
.op
[1].regs
4161 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4162 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4163 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4166 andb %rN, %rN -> testb %rN, %rN
4167 andw %rN, %rN -> testw %rN, %rN
4168 andq %rN, %rN -> testq %rN, %rN
4169 orb %rN, %rN -> testb %rN, %rN
4170 orw %rN, %rN -> testw %rN, %rN
4171 orq %rN, %rN -> testq %rN, %rN
4173 and outside of 64-bit mode
4175 andl %rN, %rN -> testl %rN, %rN
4176 orl %rN, %rN -> testl %rN, %rN
4178 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4180 else if (i
.reg_operands
== 3
4181 && i
.op
[0].regs
== i
.op
[1].regs
4182 && !i
.types
[2].bitfield
.xmmword
4183 && (i
.tm
.opcode_modifier
.vex
4184 || ((!i
.mask
|| i
.mask
->zeroing
)
4186 && is_evex_encoding (&i
.tm
)
4187 && (i
.vec_encoding
!= vex_encoding_evex
4188 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4189 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4190 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4191 && i
.types
[2].bitfield
.ymmword
))))
4192 && ((i
.tm
.base_opcode
== 0x55
4193 || i
.tm
.base_opcode
== 0x6655
4194 || i
.tm
.base_opcode
== 0x66df
4195 || i
.tm
.base_opcode
== 0x57
4196 || i
.tm
.base_opcode
== 0x6657
4197 || i
.tm
.base_opcode
== 0x66ef
4198 || i
.tm
.base_opcode
== 0x66f8
4199 || i
.tm
.base_opcode
== 0x66f9
4200 || i
.tm
.base_opcode
== 0x66fa
4201 || i
.tm
.base_opcode
== 0x66fb
4202 || i
.tm
.base_opcode
== 0x42
4203 || i
.tm
.base_opcode
== 0x6642
4204 || i
.tm
.base_opcode
== 0x47
4205 || i
.tm
.base_opcode
== 0x6647)
4206 && i
.tm
.extension_opcode
== None
))
4209 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4211 EVEX VOP %zmmM, %zmmM, %zmmN
4212 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4213 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4214 EVEX VOP %ymmM, %ymmM, %ymmN
4215 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4216 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4217 VEX VOP %ymmM, %ymmM, %ymmN
4218 -> VEX VOP %xmmM, %xmmM, %xmmN
4219 VOP, one of vpandn and vpxor:
4220 VEX VOP %ymmM, %ymmM, %ymmN
4221 -> VEX VOP %xmmM, %xmmM, %xmmN
4222 VOP, one of vpandnd and vpandnq:
4223 EVEX VOP %zmmM, %zmmM, %zmmN
4224 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4225 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4226 EVEX VOP %ymmM, %ymmM, %ymmN
4227 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4228 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4229 VOP, one of vpxord and vpxorq:
4230 EVEX VOP %zmmM, %zmmM, %zmmN
4231 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4232 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4233 EVEX VOP %ymmM, %ymmM, %ymmN
4234 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4235 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4236 VOP, one of kxord and kxorq:
4237 VEX VOP %kM, %kM, %kN
4238 -> VEX kxorw %kM, %kM, %kN
4239 VOP, one of kandnd and kandnq:
4240 VEX VOP %kM, %kM, %kN
4241 -> VEX kandnw %kM, %kM, %kN
4243 if (is_evex_encoding (&i
.tm
))
4245 if (i
.vec_encoding
!= vex_encoding_evex
)
4247 i
.tm
.opcode_modifier
.vex
= VEX128
;
4248 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4249 i
.tm
.opcode_modifier
.evex
= 0;
4251 else if (optimize
> 1)
4252 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4256 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4258 i
.tm
.base_opcode
&= 0xff;
4259 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4262 i
.tm
.opcode_modifier
.vex
= VEX128
;
4264 if (i
.tm
.opcode_modifier
.vex
)
4265 for (j
= 0; j
< 3; j
++)
4267 i
.types
[j
].bitfield
.xmmword
= 1;
4268 i
.types
[j
].bitfield
.ymmword
= 0;
4271 else if (i
.vec_encoding
!= vex_encoding_evex
4272 && !i
.types
[0].bitfield
.zmmword
4273 && !i
.types
[1].bitfield
.zmmword
4276 && is_evex_encoding (&i
.tm
)
4277 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4278 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4279 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4280 || (i
.tm
.base_opcode
& ~4) == 0x66db
4281 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4282 && i
.tm
.extension_opcode
== None
)
4285 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4286 vmovdqu32 and vmovdqu64:
4287 EVEX VOP %xmmM, %xmmN
4288 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4289 EVEX VOP %ymmM, %ymmN
4290 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4292 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4294 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4296 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4298 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4299 VOP, one of vpand, vpandn, vpor, vpxor:
4300 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4301 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4302 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4303 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4304 EVEX VOP{d,q} mem, %xmmM, %xmmN
4305 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4306 EVEX VOP{d,q} mem, %ymmM, %ymmN
4307 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4309 for (j
= 0; j
< i
.operands
; j
++)
4310 if (operand_type_check (i
.types
[j
], disp
)
4311 && i
.op
[j
].disps
->X_op
== O_constant
)
4313 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4314 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4315 bytes, we choose EVEX Disp8 over VEX Disp32. */
4316 int evex_disp8
, vex_disp8
;
4317 unsigned int memshift
= i
.memshift
;
4318 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4320 evex_disp8
= fits_in_disp8 (n
);
4322 vex_disp8
= fits_in_disp8 (n
);
4323 if (evex_disp8
!= vex_disp8
)
4325 i
.memshift
= memshift
;
4329 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4332 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4333 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4334 i
.tm
.opcode_modifier
.vex
4335 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4336 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4337 /* VPAND, VPOR, and VPXOR are commutative. */
4338 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4339 i
.tm
.opcode_modifier
.commutative
= 1;
4340 i
.tm
.opcode_modifier
.evex
= 0;
4341 i
.tm
.opcode_modifier
.masking
= 0;
4342 i
.tm
.opcode_modifier
.broadcast
= 0;
4343 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4346 i
.types
[j
].bitfield
.disp8
4347 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4351 /* Return non-zero for load instruction. */
4357 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4358 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4362 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4363 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4364 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4365 if (i
.tm
.opcode_modifier
.anysize
)
4368 /* pop, popf, popa. */
4369 if (strcmp (i
.tm
.name
, "pop") == 0
4370 || i
.tm
.base_opcode
== 0x9d
4371 || i
.tm
.base_opcode
== 0x61)
4374 /* movs, cmps, lods, scas. */
4375 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4379 if (base_opcode
== 0x6f
4380 || i
.tm
.base_opcode
== 0xd7)
4382 /* NB: For AMD-specific insns with implicit memory operands,
4383 they're intentionally not covered. */
4386 /* No memory operand. */
4387 if (!i
.mem_operands
)
4393 if (i
.tm
.base_opcode
== 0xae
4394 && i
.tm
.opcode_modifier
.vex
4395 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4396 && i
.tm
.extension_opcode
== 2)
4401 /* test, not, neg, mul, imul, div, idiv. */
4402 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4403 && i
.tm
.extension_opcode
!= 1)
4407 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4410 /* add, or, adc, sbb, and, sub, xor, cmp. */
4411 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4414 /* bt, bts, btr, btc. */
4415 if (i
.tm
.base_opcode
== 0xfba
4416 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4419 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4420 if ((base_opcode
== 0xc1
4421 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4422 && i
.tm
.extension_opcode
!= 6)
4425 /* cmpxchg8b, cmpxchg16b, xrstors. */
4426 if (i
.tm
.base_opcode
== 0xfc7
4427 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4430 /* fxrstor, ldmxcsr, xrstor. */
4431 if (i
.tm
.base_opcode
== 0xfae
4432 && (i
.tm
.extension_opcode
== 1
4433 || i
.tm
.extension_opcode
== 2
4434 || i
.tm
.extension_opcode
== 5))
4437 /* lgdt, lidt, lmsw. */
4438 if (i
.tm
.base_opcode
== 0xf01
4439 && (i
.tm
.extension_opcode
== 2
4440 || i
.tm
.extension_opcode
== 3
4441 || i
.tm
.extension_opcode
== 6))
4445 if (i
.tm
.base_opcode
== 0xfc7
4446 && i
.tm
.extension_opcode
== 6)
4449 /* Check for x87 instructions. */
4450 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4452 /* Skip fst, fstp, fstenv, fstcw. */
4453 if (i
.tm
.base_opcode
== 0xd9
4454 && (i
.tm
.extension_opcode
== 2
4455 || i
.tm
.extension_opcode
== 3
4456 || i
.tm
.extension_opcode
== 6
4457 || i
.tm
.extension_opcode
== 7))
4460 /* Skip fisttp, fist, fistp, fstp. */
4461 if (i
.tm
.base_opcode
== 0xdb
4462 && (i
.tm
.extension_opcode
== 1
4463 || i
.tm
.extension_opcode
== 2
4464 || i
.tm
.extension_opcode
== 3
4465 || i
.tm
.extension_opcode
== 7))
4468 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4469 if (i
.tm
.base_opcode
== 0xdd
4470 && (i
.tm
.extension_opcode
== 1
4471 || i
.tm
.extension_opcode
== 2
4472 || i
.tm
.extension_opcode
== 3
4473 || i
.tm
.extension_opcode
== 6
4474 || i
.tm
.extension_opcode
== 7))
4477 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4478 if (i
.tm
.base_opcode
== 0xdf
4479 && (i
.tm
.extension_opcode
== 1
4480 || i
.tm
.extension_opcode
== 2
4481 || i
.tm
.extension_opcode
== 3
4482 || i
.tm
.extension_opcode
== 6
4483 || i
.tm
.extension_opcode
== 7))
4490 dest
= i
.operands
- 1;
4492 /* Check fake imm8 operand and 3 source operands. */
4493 if ((i
.tm
.opcode_modifier
.immext
4494 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4495 && i
.types
[dest
].bitfield
.imm8
)
4498 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4500 && (base_opcode
== 0x1
4501 || base_opcode
== 0x9
4502 || base_opcode
== 0x11
4503 || base_opcode
== 0x19
4504 || base_opcode
== 0x21
4505 || base_opcode
== 0x29
4506 || base_opcode
== 0x31
4507 || base_opcode
== 0x39
4508 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4509 || base_opcode
== 0xfc1))
4512 /* Check for load instruction. */
4513 return (i
.types
[dest
].bitfield
.class != ClassNone
4514 || i
.types
[dest
].bitfield
.instance
== Accum
);
4517 /* Output lfence, 0xfaee8, after instruction. */
4520 insert_lfence_after (void)
4522 if (lfence_after_load
&& load_insn_p ())
4524 /* There are also two REP string instructions that require
4525 special treatment. Specifically, the compare string (CMPS)
4526 and scan string (SCAS) instructions set EFLAGS in a manner
4527 that depends on the data being compared/scanned. When used
4528 with a REP prefix, the number of iterations may therefore
4529 vary depending on this data. If the data is a program secret
4530 chosen by the adversary using an LVI method,
4531 then this data-dependent behavior may leak some aspect
4533 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4534 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4535 && i
.prefix
[REP_PREFIX
])
4537 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4540 char *p
= frag_more (3);
4547 /* Output lfence, 0xfaee8, before instruction. */
4550 insert_lfence_before (void)
4554 if (is_any_vex_encoding (&i
.tm
))
4557 if (i
.tm
.base_opcode
== 0xff
4558 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4560 /* Insert lfence before indirect branch if needed. */
4562 if (lfence_before_indirect_branch
== lfence_branch_none
)
4565 if (i
.operands
!= 1)
4568 if (i
.reg_operands
== 1)
4570 /* Indirect branch via register. Don't insert lfence with
4571 -mlfence-after-load=yes. */
4572 if (lfence_after_load
4573 || lfence_before_indirect_branch
== lfence_branch_memory
)
4576 else if (i
.mem_operands
== 1
4577 && lfence_before_indirect_branch
!= lfence_branch_register
)
4579 as_warn (_("indirect `%s` with memory operand should be avoided"),
4586 if (last_insn
.kind
!= last_insn_other
4587 && last_insn
.seg
== now_seg
)
4589 as_warn_where (last_insn
.file
, last_insn
.line
,
4590 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4591 last_insn
.name
, i
.tm
.name
);
4602 /* Output or/not/shl and lfence before near ret. */
4603 if (lfence_before_ret
!= lfence_before_ret_none
4604 && (i
.tm
.base_opcode
== 0xc2
4605 || i
.tm
.base_opcode
== 0xc3))
4607 if (last_insn
.kind
!= last_insn_other
4608 && last_insn
.seg
== now_seg
)
4610 as_warn_where (last_insn
.file
, last_insn
.line
,
4611 _("`%s` skips -mlfence-before-ret on `%s`"),
4612 last_insn
.name
, i
.tm
.name
);
4616 /* Near ret ingore operand size override under CPU64. */
4617 char prefix
= flag_code
== CODE_64BIT
4619 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4621 if (lfence_before_ret
== lfence_before_ret_not
)
4623 /* not: 0xf71424, may add prefix
4624 for operand size override or 64-bit code. */
4625 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4639 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4642 if (lfence_before_ret
== lfence_before_ret_or
)
4644 /* or: 0x830c2400, may add prefix
4645 for operand size override or 64-bit code. */
4651 /* shl: 0xc1242400, may add prefix
4652 for operand size override or 64-bit code. */
4667 /* This is the guts of the machine-dependent assembler. LINE points to a
4668 machine dependent instruction. This function is supposed to emit
4669 the frags/bytes it assembles to. */
4672 md_assemble (char *line
)
4675 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4676 const insn_template
*t
;
4678 /* Initialize globals. */
4679 memset (&i
, '\0', sizeof (i
));
4680 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4681 i
.reloc
[j
] = NO_RELOC
;
4682 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4683 memset (im_expressions
, '\0', sizeof (im_expressions
));
4684 save_stack_p
= save_stack
;
4686 /* First parse an instruction mnemonic & call i386_operand for the operands.
4687 We assume that the scrubber has arranged it so that line[0] is the valid
4688 start of a (possibly prefixed) mnemonic. */
4690 line
= parse_insn (line
, mnemonic
);
4693 mnem_suffix
= i
.suffix
;
4695 line
= parse_operands (line
, mnemonic
);
4697 xfree (i
.memop1_string
);
4698 i
.memop1_string
= NULL
;
4702 /* Now we've parsed the mnemonic into a set of templates, and have the
4703 operands at hand. */
4705 /* All Intel opcodes have reversed operands except for "bound", "enter",
4706 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4707 intersegment "jmp" and "call" instructions with 2 immediate operands so
4708 that the immediate segment precedes the offset, as it does when in AT&T
4712 && (strcmp (mnemonic
, "bound") != 0)
4713 && (strcmp (mnemonic
, "invlpga") != 0)
4714 && (strncmp (mnemonic
, "monitor", 7) != 0)
4715 && (strncmp (mnemonic
, "mwait", 5) != 0)
4716 && (strcmp (mnemonic
, "tpause") != 0)
4717 && (strcmp (mnemonic
, "umwait") != 0)
4718 && !(operand_type_check (i
.types
[0], imm
)
4719 && operand_type_check (i
.types
[1], imm
)))
4722 /* The order of the immediates should be reversed
4723 for 2 immediates extrq and insertq instructions */
4724 if (i
.imm_operands
== 2
4725 && (strcmp (mnemonic
, "extrq") == 0
4726 || strcmp (mnemonic
, "insertq") == 0))
4727 swap_2_operands (0, 1);
4732 /* Don't optimize displacement for movabs since it only takes 64bit
4735 && i
.disp_encoding
!= disp_encoding_32bit
4736 && (flag_code
!= CODE_64BIT
4737 || strcmp (mnemonic
, "movabs") != 0))
4740 /* Next, we find a template that matches the given insn,
4741 making sure the overlap of the given operands types is consistent
4742 with the template operand types. */
4744 if (!(t
= match_template (mnem_suffix
)))
4747 if (sse_check
!= check_none
4748 && !i
.tm
.opcode_modifier
.noavx
4749 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4750 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4751 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4752 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4753 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4754 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4755 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4756 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4757 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4758 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4759 || i
.tm
.cpu_flags
.bitfield
.cpusha
4760 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4762 (sse_check
== check_warning
4764 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4767 if (i
.tm
.opcode_modifier
.fwait
)
4768 if (!add_prefix (FWAIT_OPCODE
))
4771 /* Check if REP prefix is OK. */
4772 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4774 as_bad (_("invalid instruction `%s' after `%s'"),
4775 i
.tm
.name
, i
.rep_prefix
);
4779 /* Check for lock without a lockable instruction. Destination operand
4780 must be memory unless it is xchg (0x86). */
4781 if (i
.prefix
[LOCK_PREFIX
]
4782 && (!i
.tm
.opcode_modifier
.islockable
4783 || i
.mem_operands
== 0
4784 || (i
.tm
.base_opcode
!= 0x86
4785 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4787 as_bad (_("expecting lockable instruction after `lock'"));
4791 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4792 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4794 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4798 /* Check if HLE prefix is OK. */
4799 if (i
.hle_prefix
&& !check_hle ())
4802 /* Check BND prefix. */
4803 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4804 as_bad (_("expecting valid branch instruction after `bnd'"));
4806 /* Check NOTRACK prefix. */
4807 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4808 as_bad (_("expecting indirect branch instruction after `notrack'"));
4810 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4812 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4813 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4814 else if (flag_code
!= CODE_16BIT
4815 ? i
.prefix
[ADDR_PREFIX
]
4816 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4817 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4820 /* Insert BND prefix. */
4821 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4823 if (!i
.prefix
[BND_PREFIX
])
4824 add_prefix (BND_PREFIX_OPCODE
);
4825 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4827 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4828 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4832 /* Check string instruction segment overrides. */
4833 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4835 gas_assert (i
.mem_operands
);
4836 if (!check_string ())
4838 i
.disp_operands
= 0;
4841 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4842 optimize_encoding ();
4844 if (!process_suffix ())
4847 /* Update operand types. */
4848 for (j
= 0; j
< i
.operands
; j
++)
4849 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4851 /* Make still unresolved immediate matches conform to size of immediate
4852 given in i.suffix. */
4853 if (!finalize_imm ())
4856 if (i
.types
[0].bitfield
.imm1
)
4857 i
.imm_operands
= 0; /* kludge for shift insns. */
4859 /* We only need to check those implicit registers for instructions
4860 with 3 operands or less. */
4861 if (i
.operands
<= 3)
4862 for (j
= 0; j
< i
.operands
; j
++)
4863 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4864 && !i
.types
[j
].bitfield
.xmmword
)
4867 /* ImmExt should be processed after SSE2AVX. */
4868 if (!i
.tm
.opcode_modifier
.sse2avx
4869 && i
.tm
.opcode_modifier
.immext
)
4872 /* For insns with operands there are more diddles to do to the opcode. */
4875 if (!process_operands ())
4878 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4880 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4881 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4884 if (is_any_vex_encoding (&i
.tm
))
4886 if (!cpu_arch_flags
.bitfield
.cpui286
)
4888 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4893 if (i
.tm
.opcode_modifier
.vex
)
4894 build_vex_prefix (t
);
4896 build_evex_prefix ();
4899 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4900 instructions may define INT_OPCODE as well, so avoid this corner
4901 case for those instructions that use MODRM. */
4902 if (i
.tm
.base_opcode
== INT_OPCODE
4903 && !i
.tm
.opcode_modifier
.modrm
4904 && i
.op
[0].imms
->X_add_number
== 3)
4906 i
.tm
.base_opcode
= INT3_OPCODE
;
4910 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4911 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4912 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4913 && i
.op
[0].disps
->X_op
== O_constant
)
4915 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4916 the absolute address given by the constant. Since ix86 jumps and
4917 calls are pc relative, we need to generate a reloc. */
4918 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4919 i
.op
[0].disps
->X_op
= O_symbol
;
4922 /* For 8 bit registers we need an empty rex prefix. Also if the
4923 instruction already has a prefix, we need to convert old
4924 registers to new ones. */
4926 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4927 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4928 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4929 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4930 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4931 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4936 i
.rex
|= REX_OPCODE
;
4937 for (x
= 0; x
< 2; x
++)
4939 /* Look for 8 bit operand that uses old registers. */
4940 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4941 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4943 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4944 /* In case it is "hi" register, give up. */
4945 if (i
.op
[x
].regs
->reg_num
> 3)
4946 as_bad (_("can't encode register '%s%s' in an "
4947 "instruction requiring REX prefix."),
4948 register_prefix
, i
.op
[x
].regs
->reg_name
);
4950 /* Otherwise it is equivalent to the extended register.
4951 Since the encoding doesn't change this is merely
4952 cosmetic cleanup for debug output. */
4954 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4959 if (i
.rex
== 0 && i
.rex_encoding
)
4961 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4962 that uses legacy register. If it is "hi" register, don't add
4963 the REX_OPCODE byte. */
4965 for (x
= 0; x
< 2; x
++)
4966 if (i
.types
[x
].bitfield
.class == Reg
4967 && i
.types
[x
].bitfield
.byte
4968 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4969 && i
.op
[x
].regs
->reg_num
> 3)
4971 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4972 i
.rex_encoding
= FALSE
;
4981 add_prefix (REX_OPCODE
| i
.rex
);
4983 insert_lfence_before ();
4985 /* We are ready to output the insn. */
4988 insert_lfence_after ();
4990 last_insn
.seg
= now_seg
;
4992 if (i
.tm
.opcode_modifier
.isprefix
)
4994 last_insn
.kind
= last_insn_prefix
;
4995 last_insn
.name
= i
.tm
.name
;
4996 last_insn
.file
= as_where (&last_insn
.line
);
4999 last_insn
.kind
= last_insn_other
;
5003 parse_insn (char *line
, char *mnemonic
)
5006 char *token_start
= l
;
5009 const insn_template
*t
;
5015 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5020 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5022 as_bad (_("no such instruction: `%s'"), token_start
);
5027 if (!is_space_char (*l
)
5028 && *l
!= END_OF_INSN
5030 || (*l
!= PREFIX_SEPARATOR
5033 as_bad (_("invalid character %s in mnemonic"),
5034 output_invalid (*l
));
5037 if (token_start
== l
)
5039 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5040 as_bad (_("expecting prefix; got nothing"));
5042 as_bad (_("expecting mnemonic; got nothing"));
5046 /* Look up instruction (or prefix) via hash table. */
5047 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5049 if (*l
!= END_OF_INSN
5050 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5051 && current_templates
5052 && current_templates
->start
->opcode_modifier
.isprefix
)
5054 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5056 as_bad ((flag_code
!= CODE_64BIT
5057 ? _("`%s' is only supported in 64-bit mode")
5058 : _("`%s' is not supported in 64-bit mode")),
5059 current_templates
->start
->name
);
5062 /* If we are in 16-bit mode, do not allow addr16 or data16.
5063 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5064 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5065 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5066 && flag_code
!= CODE_64BIT
5067 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5068 ^ (flag_code
== CODE_16BIT
)))
5070 as_bad (_("redundant %s prefix"),
5071 current_templates
->start
->name
);
5074 if (current_templates
->start
->opcode_length
== 0)
5076 /* Handle pseudo prefixes. */
5077 switch (current_templates
->start
->base_opcode
)
5081 i
.disp_encoding
= disp_encoding_8bit
;
5085 i
.disp_encoding
= disp_encoding_32bit
;
5089 i
.dir_encoding
= dir_encoding_load
;
5093 i
.dir_encoding
= dir_encoding_store
;
5097 i
.vec_encoding
= vex_encoding_vex
;
5101 i
.vec_encoding
= vex_encoding_vex3
;
5105 i
.vec_encoding
= vex_encoding_evex
;
5109 i
.rex_encoding
= TRUE
;
5113 i
.no_optimize
= TRUE
;
5121 /* Add prefix, checking for repeated prefixes. */
5122 switch (add_prefix (current_templates
->start
->base_opcode
))
5127 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5128 i
.notrack_prefix
= current_templates
->start
->name
;
5131 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5132 i
.hle_prefix
= current_templates
->start
->name
;
5133 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5134 i
.bnd_prefix
= current_templates
->start
->name
;
5136 i
.rep_prefix
= current_templates
->start
->name
;
5142 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5149 if (!current_templates
)
5151 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5152 Check if we should swap operand or force 32bit displacement in
5154 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5155 i
.dir_encoding
= dir_encoding_swap
;
5156 else if (mnem_p
- 3 == dot_p
5159 i
.disp_encoding
= disp_encoding_8bit
;
5160 else if (mnem_p
- 4 == dot_p
5164 i
.disp_encoding
= disp_encoding_32bit
;
5169 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5172 if (!current_templates
)
5175 if (mnem_p
> mnemonic
)
5177 /* See if we can get a match by trimming off a suffix. */
5180 case WORD_MNEM_SUFFIX
:
5181 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5182 i
.suffix
= SHORT_MNEM_SUFFIX
;
5185 case BYTE_MNEM_SUFFIX
:
5186 case QWORD_MNEM_SUFFIX
:
5187 i
.suffix
= mnem_p
[-1];
5189 current_templates
= (const templates
*) hash_find (op_hash
,
5192 case SHORT_MNEM_SUFFIX
:
5193 case LONG_MNEM_SUFFIX
:
5196 i
.suffix
= mnem_p
[-1];
5198 current_templates
= (const templates
*) hash_find (op_hash
,
5207 if (intel_float_operand (mnemonic
) == 1)
5208 i
.suffix
= SHORT_MNEM_SUFFIX
;
5210 i
.suffix
= LONG_MNEM_SUFFIX
;
5212 current_templates
= (const templates
*) hash_find (op_hash
,
5219 if (!current_templates
)
5221 as_bad (_("no such instruction: `%s'"), token_start
);
5226 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5227 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5229 /* Check for a branch hint. We allow ",pt" and ",pn" for
5230 predict taken and predict not taken respectively.
5231 I'm not sure that branch hints actually do anything on loop
5232 and jcxz insns (JumpByte) for current Pentium4 chips. They
5233 may work in the future and it doesn't hurt to accept them
5235 if (l
[0] == ',' && l
[1] == 'p')
5239 if (!add_prefix (DS_PREFIX_OPCODE
))
5243 else if (l
[2] == 'n')
5245 if (!add_prefix (CS_PREFIX_OPCODE
))
5251 /* Any other comma loses. */
5254 as_bad (_("invalid character %s in mnemonic"),
5255 output_invalid (*l
));
5259 /* Check if instruction is supported on specified architecture. */
5261 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5263 supported
|= cpu_flags_match (t
);
5264 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5266 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5267 as_warn (_("use .code16 to ensure correct addressing mode"));
5273 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5274 as_bad (flag_code
== CODE_64BIT
5275 ? _("`%s' is not supported in 64-bit mode")
5276 : _("`%s' is only supported in 64-bit mode"),
5277 current_templates
->start
->name
);
5279 as_bad (_("`%s' is not supported on `%s%s'"),
5280 current_templates
->start
->name
,
5281 cpu_arch_name
? cpu_arch_name
: default_arch
,
5282 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5288 parse_operands (char *l
, const char *mnemonic
)
5292 /* 1 if operand is pending after ','. */
5293 unsigned int expecting_operand
= 0;
5295 /* Non-zero if operand parens not balanced. */
5296 unsigned int paren_not_balanced
;
5298 while (*l
!= END_OF_INSN
)
5300 /* Skip optional white space before operand. */
5301 if (is_space_char (*l
))
5303 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5305 as_bad (_("invalid character %s before operand %d"),
5306 output_invalid (*l
),
5310 token_start
= l
; /* After white space. */
5311 paren_not_balanced
= 0;
5312 while (paren_not_balanced
|| *l
!= ',')
5314 if (*l
== END_OF_INSN
)
5316 if (paren_not_balanced
)
5319 as_bad (_("unbalanced parenthesis in operand %d."),
5322 as_bad (_("unbalanced brackets in operand %d."),
5327 break; /* we are done */
5329 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5331 as_bad (_("invalid character %s in operand %d"),
5332 output_invalid (*l
),
5339 ++paren_not_balanced
;
5341 --paren_not_balanced
;
5346 ++paren_not_balanced
;
5348 --paren_not_balanced
;
5352 if (l
!= token_start
)
5353 { /* Yes, we've read in another operand. */
5354 unsigned int operand_ok
;
5355 this_operand
= i
.operands
++;
5356 if (i
.operands
> MAX_OPERANDS
)
5358 as_bad (_("spurious operands; (%d operands/instruction max)"),
5362 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5363 /* Now parse operand adding info to 'i' as we go along. */
5364 END_STRING_AND_SAVE (l
);
5366 if (i
.mem_operands
> 1)
5368 as_bad (_("too many memory references for `%s'"),
5375 i386_intel_operand (token_start
,
5376 intel_float_operand (mnemonic
));
5378 operand_ok
= i386_att_operand (token_start
);
5380 RESTORE_END_STRING (l
);
5386 if (expecting_operand
)
5388 expecting_operand_after_comma
:
5389 as_bad (_("expecting operand after ','; got nothing"));
5394 as_bad (_("expecting operand before ','; got nothing"));
5399 /* Now *l must be either ',' or END_OF_INSN. */
5402 if (*++l
== END_OF_INSN
)
5404 /* Just skip it, if it's \n complain. */
5405 goto expecting_operand_after_comma
;
5407 expecting_operand
= 1;
5414 swap_2_operands (int xchg1
, int xchg2
)
5416 union i386_op temp_op
;
5417 i386_operand_type temp_type
;
5418 unsigned int temp_flags
;
5419 enum bfd_reloc_code_real temp_reloc
;
5421 temp_type
= i
.types
[xchg2
];
5422 i
.types
[xchg2
] = i
.types
[xchg1
];
5423 i
.types
[xchg1
] = temp_type
;
5425 temp_flags
= i
.flags
[xchg2
];
5426 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5427 i
.flags
[xchg1
] = temp_flags
;
5429 temp_op
= i
.op
[xchg2
];
5430 i
.op
[xchg2
] = i
.op
[xchg1
];
5431 i
.op
[xchg1
] = temp_op
;
5433 temp_reloc
= i
.reloc
[xchg2
];
5434 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5435 i
.reloc
[xchg1
] = temp_reloc
;
5439 if (i
.mask
->operand
== xchg1
)
5440 i
.mask
->operand
= xchg2
;
5441 else if (i
.mask
->operand
== xchg2
)
5442 i
.mask
->operand
= xchg1
;
5446 if (i
.broadcast
->operand
== xchg1
)
5447 i
.broadcast
->operand
= xchg2
;
5448 else if (i
.broadcast
->operand
== xchg2
)
5449 i
.broadcast
->operand
= xchg1
;
5453 if (i
.rounding
->operand
== xchg1
)
5454 i
.rounding
->operand
= xchg2
;
5455 else if (i
.rounding
->operand
== xchg2
)
5456 i
.rounding
->operand
= xchg1
;
5461 swap_operands (void)
5467 swap_2_operands (1, i
.operands
- 2);
5471 swap_2_operands (0, i
.operands
- 1);
5477 if (i
.mem_operands
== 2)
5479 const seg_entry
*temp_seg
;
5480 temp_seg
= i
.seg
[0];
5481 i
.seg
[0] = i
.seg
[1];
5482 i
.seg
[1] = temp_seg
;
5486 /* Try to ensure constant immediates are represented in the smallest
5491 char guess_suffix
= 0;
5495 guess_suffix
= i
.suffix
;
5496 else if (i
.reg_operands
)
5498 /* Figure out a suffix from the last register operand specified.
5499 We can't do this properly yet, i.e. excluding special register
5500 instances, but the following works for instructions with
5501 immediates. In any case, we can't set i.suffix yet. */
5502 for (op
= i
.operands
; --op
>= 0;)
5503 if (i
.types
[op
].bitfield
.class != Reg
)
5505 else if (i
.types
[op
].bitfield
.byte
)
5507 guess_suffix
= BYTE_MNEM_SUFFIX
;
5510 else if (i
.types
[op
].bitfield
.word
)
5512 guess_suffix
= WORD_MNEM_SUFFIX
;
5515 else if (i
.types
[op
].bitfield
.dword
)
5517 guess_suffix
= LONG_MNEM_SUFFIX
;
5520 else if (i
.types
[op
].bitfield
.qword
)
5522 guess_suffix
= QWORD_MNEM_SUFFIX
;
5526 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5527 guess_suffix
= WORD_MNEM_SUFFIX
;
5529 for (op
= i
.operands
; --op
>= 0;)
5530 if (operand_type_check (i
.types
[op
], imm
))
5532 switch (i
.op
[op
].imms
->X_op
)
5535 /* If a suffix is given, this operand may be shortened. */
5536 switch (guess_suffix
)
5538 case LONG_MNEM_SUFFIX
:
5539 i
.types
[op
].bitfield
.imm32
= 1;
5540 i
.types
[op
].bitfield
.imm64
= 1;
5542 case WORD_MNEM_SUFFIX
:
5543 i
.types
[op
].bitfield
.imm16
= 1;
5544 i
.types
[op
].bitfield
.imm32
= 1;
5545 i
.types
[op
].bitfield
.imm32s
= 1;
5546 i
.types
[op
].bitfield
.imm64
= 1;
5548 case BYTE_MNEM_SUFFIX
:
5549 i
.types
[op
].bitfield
.imm8
= 1;
5550 i
.types
[op
].bitfield
.imm8s
= 1;
5551 i
.types
[op
].bitfield
.imm16
= 1;
5552 i
.types
[op
].bitfield
.imm32
= 1;
5553 i
.types
[op
].bitfield
.imm32s
= 1;
5554 i
.types
[op
].bitfield
.imm64
= 1;
5558 /* If this operand is at most 16 bits, convert it
5559 to a signed 16 bit number before trying to see
5560 whether it will fit in an even smaller size.
5561 This allows a 16-bit operand such as $0xffe0 to
5562 be recognised as within Imm8S range. */
5563 if ((i
.types
[op
].bitfield
.imm16
)
5564 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5566 i
.op
[op
].imms
->X_add_number
=
5567 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5570 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5571 if ((i
.types
[op
].bitfield
.imm32
)
5572 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5575 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5576 ^ ((offsetT
) 1 << 31))
5577 - ((offsetT
) 1 << 31));
5581 = operand_type_or (i
.types
[op
],
5582 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5584 /* We must avoid matching of Imm32 templates when 64bit
5585 only immediate is available. */
5586 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5587 i
.types
[op
].bitfield
.imm32
= 0;
5594 /* Symbols and expressions. */
5596 /* Convert symbolic operand to proper sizes for matching, but don't
5597 prevent matching a set of insns that only supports sizes other
5598 than those matching the insn suffix. */
5600 i386_operand_type mask
, allowed
;
5601 const insn_template
*t
;
5603 operand_type_set (&mask
, 0);
5604 operand_type_set (&allowed
, 0);
5606 for (t
= current_templates
->start
;
5607 t
< current_templates
->end
;
5610 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5611 allowed
= operand_type_and (allowed
, anyimm
);
5613 switch (guess_suffix
)
5615 case QWORD_MNEM_SUFFIX
:
5616 mask
.bitfield
.imm64
= 1;
5617 mask
.bitfield
.imm32s
= 1;
5619 case LONG_MNEM_SUFFIX
:
5620 mask
.bitfield
.imm32
= 1;
5622 case WORD_MNEM_SUFFIX
:
5623 mask
.bitfield
.imm16
= 1;
5625 case BYTE_MNEM_SUFFIX
:
5626 mask
.bitfield
.imm8
= 1;
5631 allowed
= operand_type_and (mask
, allowed
);
5632 if (!operand_type_all_zero (&allowed
))
5633 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5640 /* Try to use the smallest displacement type too. */
5642 optimize_disp (void)
5646 for (op
= i
.operands
; --op
>= 0;)
5647 if (operand_type_check (i
.types
[op
], disp
))
5649 if (i
.op
[op
].disps
->X_op
== O_constant
)
5651 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5653 if (i
.types
[op
].bitfield
.disp16
5654 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5656 /* If this operand is at most 16 bits, convert
5657 to a signed 16 bit number and don't use 64bit
5659 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5660 i
.types
[op
].bitfield
.disp64
= 0;
5663 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5664 if (i
.types
[op
].bitfield
.disp32
5665 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5667 /* If this operand is at most 32 bits, convert
5668 to a signed 32 bit number and don't use 64bit
5670 op_disp
&= (((offsetT
) 2 << 31) - 1);
5671 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5672 i
.types
[op
].bitfield
.disp64
= 0;
5675 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5677 i
.types
[op
].bitfield
.disp8
= 0;
5678 i
.types
[op
].bitfield
.disp16
= 0;
5679 i
.types
[op
].bitfield
.disp32
= 0;
5680 i
.types
[op
].bitfield
.disp32s
= 0;
5681 i
.types
[op
].bitfield
.disp64
= 0;
5685 else if (flag_code
== CODE_64BIT
)
5687 if (fits_in_signed_long (op_disp
))
5689 i
.types
[op
].bitfield
.disp64
= 0;
5690 i
.types
[op
].bitfield
.disp32s
= 1;
5692 if (i
.prefix
[ADDR_PREFIX
]
5693 && fits_in_unsigned_long (op_disp
))
5694 i
.types
[op
].bitfield
.disp32
= 1;
5696 if ((i
.types
[op
].bitfield
.disp32
5697 || i
.types
[op
].bitfield
.disp32s
5698 || i
.types
[op
].bitfield
.disp16
)
5699 && fits_in_disp8 (op_disp
))
5700 i
.types
[op
].bitfield
.disp8
= 1;
5702 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5703 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5705 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5706 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5707 i
.types
[op
].bitfield
.disp8
= 0;
5708 i
.types
[op
].bitfield
.disp16
= 0;
5709 i
.types
[op
].bitfield
.disp32
= 0;
5710 i
.types
[op
].bitfield
.disp32s
= 0;
5711 i
.types
[op
].bitfield
.disp64
= 0;
5714 /* We only support 64bit displacement on constants. */
5715 i
.types
[op
].bitfield
.disp64
= 0;
5719 /* Return 1 if there is a match in broadcast bytes between operand
5720 GIVEN and instruction template T. */
5723 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5725 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5726 && i
.types
[given
].bitfield
.byte
)
5727 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5728 && i
.types
[given
].bitfield
.word
)
5729 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5730 && i
.types
[given
].bitfield
.dword
)
5731 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5732 && i
.types
[given
].bitfield
.qword
));
5735 /* Check if operands are valid for the instruction. */
5738 check_VecOperands (const insn_template
*t
)
5743 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5744 any one operand are implicity requiring AVX512VL support if the actual
5745 operand size is YMMword or XMMword. Since this function runs after
5746 template matching, there's no need to check for YMMword/XMMword in
5748 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5749 if (!cpu_flags_all_zero (&cpu
)
5750 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5751 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5753 for (op
= 0; op
< t
->operands
; ++op
)
5755 if (t
->operand_types
[op
].bitfield
.zmmword
5756 && (i
.types
[op
].bitfield
.ymmword
5757 || i
.types
[op
].bitfield
.xmmword
))
5759 i
.error
= unsupported
;
5765 /* Without VSIB byte, we can't have a vector register for index. */
5766 if (!t
->opcode_modifier
.vecsib
5768 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5769 || i
.index_reg
->reg_type
.bitfield
.ymmword
5770 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5772 i
.error
= unsupported_vector_index_register
;
5776 /* Check if default mask is allowed. */
5777 if (t
->opcode_modifier
.nodefmask
5778 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5780 i
.error
= no_default_mask
;
5784 /* For VSIB byte, we need a vector register for index, and all vector
5785 registers must be distinct. */
5786 if (t
->opcode_modifier
.vecsib
)
5789 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5790 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5791 || (t
->opcode_modifier
.vecsib
== VecSIB256
5792 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5793 || (t
->opcode_modifier
.vecsib
== VecSIB512
5794 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5796 i
.error
= invalid_vsib_address
;
5800 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5801 if (i
.reg_operands
== 2 && !i
.mask
)
5803 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5804 gas_assert (i
.types
[0].bitfield
.xmmword
5805 || i
.types
[0].bitfield
.ymmword
);
5806 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5807 gas_assert (i
.types
[2].bitfield
.xmmword
5808 || i
.types
[2].bitfield
.ymmword
);
5809 if (operand_check
== check_none
)
5811 if (register_number (i
.op
[0].regs
)
5812 != register_number (i
.index_reg
)
5813 && register_number (i
.op
[2].regs
)
5814 != register_number (i
.index_reg
)
5815 && register_number (i
.op
[0].regs
)
5816 != register_number (i
.op
[2].regs
))
5818 if (operand_check
== check_error
)
5820 i
.error
= invalid_vector_register_set
;
5823 as_warn (_("mask, index, and destination registers should be distinct"));
5825 else if (i
.reg_operands
== 1 && i
.mask
)
5827 if (i
.types
[1].bitfield
.class == RegSIMD
5828 && (i
.types
[1].bitfield
.xmmword
5829 || i
.types
[1].bitfield
.ymmword
5830 || i
.types
[1].bitfield
.zmmword
)
5831 && (register_number (i
.op
[1].regs
)
5832 == register_number (i
.index_reg
)))
5834 if (operand_check
== check_error
)
5836 i
.error
= invalid_vector_register_set
;
5839 if (operand_check
!= check_none
)
5840 as_warn (_("index and destination registers should be distinct"));
5845 /* Check if broadcast is supported by the instruction and is applied
5846 to the memory operand. */
5849 i386_operand_type type
, overlap
;
5851 /* Check if specified broadcast is supported in this instruction,
5852 and its broadcast bytes match the memory operand. */
5853 op
= i
.broadcast
->operand
;
5854 if (!t
->opcode_modifier
.broadcast
5855 || !(i
.flags
[op
] & Operand_Mem
)
5856 || (!i
.types
[op
].bitfield
.unspecified
5857 && !match_broadcast_size (t
, op
)))
5860 i
.error
= unsupported_broadcast
;
5864 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5865 * i
.broadcast
->type
);
5866 operand_type_set (&type
, 0);
5867 switch (i
.broadcast
->bytes
)
5870 type
.bitfield
.word
= 1;
5873 type
.bitfield
.dword
= 1;
5876 type
.bitfield
.qword
= 1;
5879 type
.bitfield
.xmmword
= 1;
5882 type
.bitfield
.ymmword
= 1;
5885 type
.bitfield
.zmmword
= 1;
5891 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5892 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5893 && t
->operand_types
[op
].bitfield
.byte
5894 + t
->operand_types
[op
].bitfield
.word
5895 + t
->operand_types
[op
].bitfield
.dword
5896 + t
->operand_types
[op
].bitfield
.qword
> 1)
5898 overlap
.bitfield
.xmmword
= 0;
5899 overlap
.bitfield
.ymmword
= 0;
5900 overlap
.bitfield
.zmmword
= 0;
5902 if (operand_type_all_zero (&overlap
))
5905 if (t
->opcode_modifier
.checkregsize
)
5909 type
.bitfield
.baseindex
= 1;
5910 for (j
= 0; j
< i
.operands
; ++j
)
5913 && !operand_type_register_match(i
.types
[j
],
5914 t
->operand_types
[j
],
5916 t
->operand_types
[op
]))
5921 /* If broadcast is supported in this instruction, we need to check if
5922 operand of one-element size isn't specified without broadcast. */
5923 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5925 /* Find memory operand. */
5926 for (op
= 0; op
< i
.operands
; op
++)
5927 if (i
.flags
[op
] & Operand_Mem
)
5929 gas_assert (op
< i
.operands
);
5930 /* Check size of the memory operand. */
5931 if (match_broadcast_size (t
, op
))
5933 i
.error
= broadcast_needed
;
5938 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5940 /* Check if requested masking is supported. */
5943 switch (t
->opcode_modifier
.masking
)
5947 case MERGING_MASKING
:
5948 if (i
.mask
->zeroing
)
5951 i
.error
= unsupported_masking
;
5955 case DYNAMIC_MASKING
:
5956 /* Memory destinations allow only merging masking. */
5957 if (i
.mask
->zeroing
&& i
.mem_operands
)
5959 /* Find memory operand. */
5960 for (op
= 0; op
< i
.operands
; op
++)
5961 if (i
.flags
[op
] & Operand_Mem
)
5963 gas_assert (op
< i
.operands
);
5964 if (op
== i
.operands
- 1)
5966 i
.error
= unsupported_masking
;
5976 /* Check if masking is applied to dest operand. */
5977 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5979 i
.error
= mask_not_on_destination
;
5986 if (!t
->opcode_modifier
.sae
5987 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5989 i
.error
= unsupported_rc_sae
;
5992 /* If the instruction has several immediate operands and one of
5993 them is rounding, the rounding operand should be the last
5994 immediate operand. */
5995 if (i
.imm_operands
> 1
5996 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5998 i
.error
= rc_sae_operand_not_last_imm
;
6003 /* Check the special Imm4 cases; must be the first operand. */
6004 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6006 if (i
.op
[0].imms
->X_op
!= O_constant
6007 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6013 /* Turn off Imm<N> so that update_imm won't complain. */
6014 operand_type_set (&i
.types
[0], 0);
6017 /* Check vector Disp8 operand. */
6018 if (t
->opcode_modifier
.disp8memshift
6019 && i
.disp_encoding
!= disp_encoding_32bit
)
6022 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6023 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6024 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6027 const i386_operand_type
*type
= NULL
;
6030 for (op
= 0; op
< i
.operands
; op
++)
6031 if (i
.flags
[op
] & Operand_Mem
)
6033 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6034 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6035 else if (t
->operand_types
[op
].bitfield
.xmmword
6036 + t
->operand_types
[op
].bitfield
.ymmword
6037 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6038 type
= &t
->operand_types
[op
];
6039 else if (!i
.types
[op
].bitfield
.unspecified
)
6040 type
= &i
.types
[op
];
6042 else if (i
.types
[op
].bitfield
.class == RegSIMD
6043 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6045 if (i
.types
[op
].bitfield
.zmmword
)
6047 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6049 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6055 if (type
->bitfield
.zmmword
)
6057 else if (type
->bitfield
.ymmword
)
6059 else if (type
->bitfield
.xmmword
)
6063 /* For the check in fits_in_disp8(). */
6064 if (i
.memshift
== 0)
6068 for (op
= 0; op
< i
.operands
; op
++)
6069 if (operand_type_check (i
.types
[op
], disp
)
6070 && i
.op
[op
].disps
->X_op
== O_constant
)
6072 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6074 i
.types
[op
].bitfield
.disp8
= 1;
6077 i
.types
[op
].bitfield
.disp8
= 0;
6086 /* Check if encoding requirements are met by the instruction. */
6089 VEX_check_encoding (const insn_template
*t
)
6091 if (i
.vec_encoding
== vex_encoding_error
)
6093 i
.error
= unsupported
;
6097 if (i
.vec_encoding
== vex_encoding_evex
)
6099 /* This instruction must be encoded with EVEX prefix. */
6100 if (!is_evex_encoding (t
))
6102 i
.error
= unsupported
;
6108 if (!t
->opcode_modifier
.vex
)
6110 /* This instruction template doesn't have VEX prefix. */
6111 if (i
.vec_encoding
!= vex_encoding_default
)
6113 i
.error
= unsupported
;
6122 static const insn_template
*
6123 match_template (char mnem_suffix
)
6125 /* Points to template once we've found it. */
6126 const insn_template
*t
;
6127 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6128 i386_operand_type overlap4
;
6129 unsigned int found_reverse_match
;
6130 i386_opcode_modifier suffix_check
;
6131 i386_operand_type operand_types
[MAX_OPERANDS
];
6132 int addr_prefix_disp
;
6133 unsigned int j
, size_match
, check_register
;
6134 enum i386_error specific_error
= 0;
6136 #if MAX_OPERANDS != 5
6137 # error "MAX_OPERANDS must be 5."
6140 found_reverse_match
= 0;
6141 addr_prefix_disp
= -1;
6143 /* Prepare for mnemonic suffix check. */
6144 memset (&suffix_check
, 0, sizeof (suffix_check
));
6145 switch (mnem_suffix
)
6147 case BYTE_MNEM_SUFFIX
:
6148 suffix_check
.no_bsuf
= 1;
6150 case WORD_MNEM_SUFFIX
:
6151 suffix_check
.no_wsuf
= 1;
6153 case SHORT_MNEM_SUFFIX
:
6154 suffix_check
.no_ssuf
= 1;
6156 case LONG_MNEM_SUFFIX
:
6157 suffix_check
.no_lsuf
= 1;
6159 case QWORD_MNEM_SUFFIX
:
6160 suffix_check
.no_qsuf
= 1;
6163 /* NB: In Intel syntax, normally we can check for memory operand
6164 size when there is no mnemonic suffix. But jmp and call have
6165 2 different encodings with Dword memory operand size, one with
6166 No_ldSuf and the other without. i.suffix is set to
6167 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6168 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6169 suffix_check
.no_ldsuf
= 1;
6172 /* Must have right number of operands. */
6173 i
.error
= number_of_operands_mismatch
;
6175 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6177 addr_prefix_disp
= -1;
6178 found_reverse_match
= 0;
6180 if (i
.operands
!= t
->operands
)
6183 /* Check processor support. */
6184 i
.error
= unsupported
;
6185 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6188 /* Check AT&T mnemonic. */
6189 i
.error
= unsupported_with_intel_mnemonic
;
6190 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6193 /* Check AT&T/Intel syntax. */
6194 i
.error
= unsupported_syntax
;
6195 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6196 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6199 /* Check Intel64/AMD64 ISA. */
6203 /* Default: Don't accept Intel64. */
6204 if (t
->opcode_modifier
.isa64
== INTEL64
)
6208 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6209 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6213 /* -mintel64: Don't accept AMD64. */
6214 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6219 /* Check the suffix. */
6220 i
.error
= invalid_instruction_suffix
;
6221 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6222 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6223 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6224 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6225 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6226 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6229 size_match
= operand_size_match (t
);
6233 /* This is intentionally not
6235 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6237 as the case of a missing * on the operand is accepted (perhaps with
6238 a warning, issued further down). */
6239 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6241 i
.error
= operand_type_mismatch
;
6245 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6246 operand_types
[j
] = t
->operand_types
[j
];
6248 /* In general, don't allow
6249 - 64-bit operands outside of 64-bit mode,
6250 - 32-bit operands on pre-386. */
6251 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6252 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6253 && flag_code
!= CODE_64BIT
6254 && (t
->base_opcode
!= 0x0fc7
6255 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6256 || (i
.suffix
== LONG_MNEM_SUFFIX
6257 && !cpu_arch_flags
.bitfield
.cpui386
))
6259 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6260 && !intel_float_operand (t
->name
))
6261 : intel_float_operand (t
->name
) != 2)
6262 && (t
->operands
== i
.imm_operands
6263 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6264 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6265 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6266 || (operand_types
[j
].bitfield
.class != RegMMX
6267 && operand_types
[j
].bitfield
.class != RegSIMD
6268 && operand_types
[j
].bitfield
.class != RegMask
))
6269 && !t
->opcode_modifier
.vecsib
)
6272 /* Do not verify operands when there are none. */
6275 if (VEX_check_encoding (t
))
6277 specific_error
= i
.error
;
6281 /* We've found a match; break out of loop. */
6285 if (!t
->opcode_modifier
.jump
6286 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6288 /* There should be only one Disp operand. */
6289 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6290 if (operand_type_check (operand_types
[j
], disp
))
6292 if (j
< MAX_OPERANDS
)
6294 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6296 addr_prefix_disp
= j
;
6298 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6299 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6303 override
= !override
;
6306 if (operand_types
[j
].bitfield
.disp32
6307 && operand_types
[j
].bitfield
.disp16
)
6309 operand_types
[j
].bitfield
.disp16
= override
;
6310 operand_types
[j
].bitfield
.disp32
= !override
;
6312 operand_types
[j
].bitfield
.disp32s
= 0;
6313 operand_types
[j
].bitfield
.disp64
= 0;
6317 if (operand_types
[j
].bitfield
.disp32s
6318 || operand_types
[j
].bitfield
.disp64
)
6320 operand_types
[j
].bitfield
.disp64
&= !override
;
6321 operand_types
[j
].bitfield
.disp32s
&= !override
;
6322 operand_types
[j
].bitfield
.disp32
= override
;
6324 operand_types
[j
].bitfield
.disp16
= 0;
6330 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6331 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6334 /* We check register size if needed. */
6335 if (t
->opcode_modifier
.checkregsize
)
6337 check_register
= (1 << t
->operands
) - 1;
6339 check_register
&= ~(1 << i
.broadcast
->operand
);
6344 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6345 switch (t
->operands
)
6348 if (!operand_type_match (overlap0
, i
.types
[0]))
6352 /* xchg %eax, %eax is a special case. It is an alias for nop
6353 only in 32bit mode and we can use opcode 0x90. In 64bit
6354 mode, we can't use 0x90 for xchg %eax, %eax since it should
6355 zero-extend %eax to %rax. */
6356 if (flag_code
== CODE_64BIT
6357 && t
->base_opcode
== 0x90
6358 && i
.types
[0].bitfield
.instance
== Accum
6359 && i
.types
[0].bitfield
.dword
6360 && i
.types
[1].bitfield
.instance
== Accum
6361 && i
.types
[1].bitfield
.dword
)
6363 /* xrelease mov %eax, <disp> is another special case. It must not
6364 match the accumulator-only encoding of mov. */
6365 if (flag_code
!= CODE_64BIT
6367 && t
->base_opcode
== 0xa0
6368 && i
.types
[0].bitfield
.instance
== Accum
6369 && (i
.flags
[1] & Operand_Mem
))
6374 if (!(size_match
& MATCH_STRAIGHT
))
6376 /* Reverse direction of operands if swapping is possible in the first
6377 place (operands need to be symmetric) and
6378 - the load form is requested, and the template is a store form,
6379 - the store form is requested, and the template is a load form,
6380 - the non-default (swapped) form is requested. */
6381 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6382 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6383 && !operand_type_all_zero (&overlap1
))
6384 switch (i
.dir_encoding
)
6386 case dir_encoding_load
:
6387 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6388 || t
->opcode_modifier
.regmem
)
6392 case dir_encoding_store
:
6393 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6394 && !t
->opcode_modifier
.regmem
)
6398 case dir_encoding_swap
:
6401 case dir_encoding_default
:
6404 /* If we want store form, we skip the current load. */
6405 if ((i
.dir_encoding
== dir_encoding_store
6406 || i
.dir_encoding
== dir_encoding_swap
)
6407 && i
.mem_operands
== 0
6408 && t
->opcode_modifier
.load
)
6413 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6414 if (!operand_type_match (overlap0
, i
.types
[0])
6415 || !operand_type_match (overlap1
, i
.types
[1])
6416 || ((check_register
& 3) == 3
6417 && !operand_type_register_match (i
.types
[0],
6422 /* Check if other direction is valid ... */
6423 if (!t
->opcode_modifier
.d
)
6427 if (!(size_match
& MATCH_REVERSE
))
6429 /* Try reversing direction of operands. */
6430 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6431 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6432 if (!operand_type_match (overlap0
, i
.types
[0])
6433 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6435 && !operand_type_register_match (i
.types
[0],
6436 operand_types
[i
.operands
- 1],
6437 i
.types
[i
.operands
- 1],
6440 /* Does not match either direction. */
6443 /* found_reverse_match holds which of D or FloatR
6445 if (!t
->opcode_modifier
.d
)
6446 found_reverse_match
= 0;
6447 else if (operand_types
[0].bitfield
.tbyte
)
6448 found_reverse_match
= Opcode_FloatD
;
6449 else if (operand_types
[0].bitfield
.xmmword
6450 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6451 || operand_types
[0].bitfield
.class == RegMMX
6452 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6453 || is_any_vex_encoding(t
))
6454 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6455 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6457 found_reverse_match
= Opcode_D
;
6458 if (t
->opcode_modifier
.floatr
)
6459 found_reverse_match
|= Opcode_FloatR
;
6463 /* Found a forward 2 operand match here. */
6464 switch (t
->operands
)
6467 overlap4
= operand_type_and (i
.types
[4],
6471 overlap3
= operand_type_and (i
.types
[3],
6475 overlap2
= operand_type_and (i
.types
[2],
6480 switch (t
->operands
)
6483 if (!operand_type_match (overlap4
, i
.types
[4])
6484 || !operand_type_register_match (i
.types
[3],
6491 if (!operand_type_match (overlap3
, i
.types
[3])
6492 || ((check_register
& 0xa) == 0xa
6493 && !operand_type_register_match (i
.types
[1],
6497 || ((check_register
& 0xc) == 0xc
6498 && !operand_type_register_match (i
.types
[2],
6505 /* Here we make use of the fact that there are no
6506 reverse match 3 operand instructions. */
6507 if (!operand_type_match (overlap2
, i
.types
[2])
6508 || ((check_register
& 5) == 5
6509 && !operand_type_register_match (i
.types
[0],
6513 || ((check_register
& 6) == 6
6514 && !operand_type_register_match (i
.types
[1],
6522 /* Found either forward/reverse 2, 3 or 4 operand match here:
6523 slip through to break. */
6526 /* Check if vector operands are valid. */
6527 if (check_VecOperands (t
))
6529 specific_error
= i
.error
;
6533 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6534 if (VEX_check_encoding (t
))
6536 specific_error
= i
.error
;
6540 /* We've found a match; break out of loop. */
6544 if (t
== current_templates
->end
)
6546 /* We found no match. */
6547 const char *err_msg
;
6548 switch (specific_error
? specific_error
: i
.error
)
6552 case operand_size_mismatch
:
6553 err_msg
= _("operand size mismatch");
6555 case operand_type_mismatch
:
6556 err_msg
= _("operand type mismatch");
6558 case register_type_mismatch
:
6559 err_msg
= _("register type mismatch");
6561 case number_of_operands_mismatch
:
6562 err_msg
= _("number of operands mismatch");
6564 case invalid_instruction_suffix
:
6565 err_msg
= _("invalid instruction suffix");
6568 err_msg
= _("constant doesn't fit in 4 bits");
6570 case unsupported_with_intel_mnemonic
:
6571 err_msg
= _("unsupported with Intel mnemonic");
6573 case unsupported_syntax
:
6574 err_msg
= _("unsupported syntax");
6577 as_bad (_("unsupported instruction `%s'"),
6578 current_templates
->start
->name
);
6580 case invalid_vsib_address
:
6581 err_msg
= _("invalid VSIB address");
6583 case invalid_vector_register_set
:
6584 err_msg
= _("mask, index, and destination registers must be distinct");
6586 case unsupported_vector_index_register
:
6587 err_msg
= _("unsupported vector index register");
6589 case unsupported_broadcast
:
6590 err_msg
= _("unsupported broadcast");
6592 case broadcast_needed
:
6593 err_msg
= _("broadcast is needed for operand of such type");
6595 case unsupported_masking
:
6596 err_msg
= _("unsupported masking");
6598 case mask_not_on_destination
:
6599 err_msg
= _("mask not on destination operand");
6601 case no_default_mask
:
6602 err_msg
= _("default mask isn't allowed");
6604 case unsupported_rc_sae
:
6605 err_msg
= _("unsupported static rounding/sae");
6607 case rc_sae_operand_not_last_imm
:
6609 err_msg
= _("RC/SAE operand must precede immediate operands");
6611 err_msg
= _("RC/SAE operand must follow immediate operands");
6613 case invalid_register_operand
:
6614 err_msg
= _("invalid register operand");
6617 as_bad (_("%s for `%s'"), err_msg
,
6618 current_templates
->start
->name
);
6622 if (!quiet_warnings
)
6625 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6626 as_warn (_("indirect %s without `*'"), t
->name
);
6628 if (t
->opcode_modifier
.isprefix
6629 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6631 /* Warn them that a data or address size prefix doesn't
6632 affect assembly of the next line of code. */
6633 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6637 /* Copy the template we found. */
6640 if (addr_prefix_disp
!= -1)
6641 i
.tm
.operand_types
[addr_prefix_disp
]
6642 = operand_types
[addr_prefix_disp
];
6644 if (found_reverse_match
)
6646 /* If we found a reverse match we must alter the opcode direction
6647 bit and clear/flip the regmem modifier one. found_reverse_match
6648 holds bits to change (different for int & float insns). */
6650 i
.tm
.base_opcode
^= found_reverse_match
;
6652 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6653 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6655 /* Certain SIMD insns have their load forms specified in the opcode
6656 table, and hence we need to _set_ RegMem instead of clearing it.
6657 We need to avoid setting the bit though on insns like KMOVW. */
6658 i
.tm
.opcode_modifier
.regmem
6659 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6660 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6661 && !i
.tm
.opcode_modifier
.regmem
;
6670 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6671 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6673 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6675 as_bad (_("`%s' operand %u must use `%ses' segment"),
6677 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6682 /* There's only ever one segment override allowed per instruction.
6683 This instruction possibly has a legal segment override on the
6684 second operand, so copy the segment to where non-string
6685 instructions store it, allowing common code. */
6686 i
.seg
[op
] = i
.seg
[1];
6692 process_suffix (void)
6694 /* If matched instruction specifies an explicit instruction mnemonic
6696 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6697 i
.suffix
= WORD_MNEM_SUFFIX
;
6698 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6699 i
.suffix
= LONG_MNEM_SUFFIX
;
6700 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6701 i
.suffix
= QWORD_MNEM_SUFFIX
;
6702 else if (i
.reg_operands
6703 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6704 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6706 unsigned int numop
= i
.operands
;
6708 /* movsx/movzx want only their source operand considered here, for the
6709 ambiguity checking below. The suffix will be replaced afterwards
6710 to represent the destination (register). */
6711 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6712 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6715 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6716 if (i
.tm
.base_opcode
== 0xf20f38f0
6717 && i
.tm
.operand_types
[1].bitfield
.qword
)
6720 /* If there's no instruction mnemonic suffix we try to invent one
6721 based on GPR operands. */
6724 /* We take i.suffix from the last register operand specified,
6725 Destination register type is more significant than source
6726 register type. crc32 in SSE4.2 prefers source register
6728 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6731 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6732 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6734 if (i
.types
[op
].bitfield
.class != Reg
)
6736 if (i
.types
[op
].bitfield
.byte
)
6737 i
.suffix
= BYTE_MNEM_SUFFIX
;
6738 else if (i
.types
[op
].bitfield
.word
)
6739 i
.suffix
= WORD_MNEM_SUFFIX
;
6740 else if (i
.types
[op
].bitfield
.dword
)
6741 i
.suffix
= LONG_MNEM_SUFFIX
;
6742 else if (i
.types
[op
].bitfield
.qword
)
6743 i
.suffix
= QWORD_MNEM_SUFFIX
;
6749 /* As an exception, movsx/movzx silently default to a byte source
6751 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6752 && !i
.suffix
&& !intel_syntax
)
6753 i
.suffix
= BYTE_MNEM_SUFFIX
;
6755 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6758 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6759 && i
.tm
.opcode_modifier
.no_bsuf
)
6761 else if (!check_byte_reg ())
6764 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6767 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6768 && i
.tm
.opcode_modifier
.no_lsuf
6769 && !i
.tm
.opcode_modifier
.todword
6770 && !i
.tm
.opcode_modifier
.toqword
)
6772 else if (!check_long_reg ())
6775 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6778 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6779 && i
.tm
.opcode_modifier
.no_qsuf
6780 && !i
.tm
.opcode_modifier
.todword
6781 && !i
.tm
.opcode_modifier
.toqword
)
6783 else if (!check_qword_reg ())
6786 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6789 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6790 && i
.tm
.opcode_modifier
.no_wsuf
)
6792 else if (!check_word_reg ())
6795 else if (intel_syntax
6796 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6797 /* Do nothing if the instruction is going to ignore the prefix. */
6802 /* Undo the movsx/movzx change done above. */
6805 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6808 i
.suffix
= stackop_size
;
6809 if (stackop_size
== LONG_MNEM_SUFFIX
)
6811 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6812 .code16gcc directive to support 16-bit mode with
6813 32-bit address. For IRET without a suffix, generate
6814 16-bit IRET (opcode 0xcf) to return from an interrupt
6816 if (i
.tm
.base_opcode
== 0xcf)
6818 i
.suffix
= WORD_MNEM_SUFFIX
;
6819 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6821 /* Warn about changed behavior for segment register push/pop. */
6822 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6823 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6828 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6829 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6830 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6831 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6832 && i
.tm
.extension_opcode
<= 3)))
6837 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6839 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6840 || i
.tm
.opcode_modifier
.no_lsuf
)
6841 i
.suffix
= QWORD_MNEM_SUFFIX
;
6846 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6847 i
.suffix
= LONG_MNEM_SUFFIX
;
6850 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6851 i
.suffix
= WORD_MNEM_SUFFIX
;
6857 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6858 /* Also cover lret/retf/iret in 64-bit mode. */
6859 || (flag_code
== CODE_64BIT
6860 && !i
.tm
.opcode_modifier
.no_lsuf
6861 && !i
.tm
.opcode_modifier
.no_qsuf
))
6862 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6863 /* Accept FLDENV et al without suffix. */
6864 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6866 unsigned int suffixes
, evex
= 0;
6868 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6869 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6871 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6873 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6875 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6877 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6880 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6881 also suitable for AT&T syntax mode, it was requested that this be
6882 restricted to just Intel syntax. */
6883 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6887 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6889 if (is_evex_encoding (&i
.tm
)
6890 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6892 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6893 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6894 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6895 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6896 if (!i
.tm
.opcode_modifier
.evex
6897 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6898 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6901 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6902 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6903 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6906 /* Any properly sized operand disambiguates the insn. */
6907 if (i
.types
[op
].bitfield
.xmmword
6908 || i
.types
[op
].bitfield
.ymmword
6909 || i
.types
[op
].bitfield
.zmmword
)
6911 suffixes
&= ~(7 << 6);
6916 if ((i
.flags
[op
] & Operand_Mem
)
6917 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6919 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6921 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6923 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6925 if (is_evex_encoding (&i
.tm
))
6931 /* Are multiple suffixes / operand sizes allowed? */
6932 if (suffixes
& (suffixes
- 1))
6935 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6936 || operand_check
== check_error
))
6938 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6941 if (operand_check
== check_error
)
6943 as_bad (_("no instruction mnemonic suffix given and "
6944 "no register operands; can't size `%s'"), i
.tm
.name
);
6947 if (operand_check
== check_warning
)
6948 as_warn (_("%s; using default for `%s'"),
6950 ? _("ambiguous operand size")
6951 : _("no instruction mnemonic suffix given and "
6952 "no register operands"),
6955 if (i
.tm
.opcode_modifier
.floatmf
)
6956 i
.suffix
= SHORT_MNEM_SUFFIX
;
6957 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6958 || (i
.tm
.base_opcode
== 0x63
6959 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6960 /* handled below */;
6962 i
.tm
.opcode_modifier
.evex
= evex
;
6963 else if (flag_code
== CODE_16BIT
)
6964 i
.suffix
= WORD_MNEM_SUFFIX
;
6965 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6966 i
.suffix
= LONG_MNEM_SUFFIX
;
6968 i
.suffix
= QWORD_MNEM_SUFFIX
;
6972 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6973 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6975 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6976 In AT&T syntax, if there is no suffix (warned about above), the default
6977 will be byte extension. */
6978 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6979 i
.tm
.base_opcode
|= 1;
6981 /* For further processing, the suffix should represent the destination
6982 (register). This is already the case when one was used with
6983 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6984 no suffix to begin with. */
6985 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6987 if (i
.types
[1].bitfield
.word
)
6988 i
.suffix
= WORD_MNEM_SUFFIX
;
6989 else if (i
.types
[1].bitfield
.qword
)
6990 i
.suffix
= QWORD_MNEM_SUFFIX
;
6992 i
.suffix
= LONG_MNEM_SUFFIX
;
6994 i
.tm
.opcode_modifier
.w
= 0;
6998 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6999 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7000 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7002 /* Change the opcode based on the operand size given by i.suffix. */
7005 /* Size floating point instruction. */
7006 case LONG_MNEM_SUFFIX
:
7007 if (i
.tm
.opcode_modifier
.floatmf
)
7009 i
.tm
.base_opcode
^= 4;
7013 case WORD_MNEM_SUFFIX
:
7014 case QWORD_MNEM_SUFFIX
:
7015 /* It's not a byte, select word/dword operation. */
7016 if (i
.tm
.opcode_modifier
.w
)
7019 i
.tm
.base_opcode
|= 8;
7021 i
.tm
.base_opcode
|= 1;
7024 case SHORT_MNEM_SUFFIX
:
7025 /* Now select between word & dword operations via the operand
7026 size prefix, except for instructions that will ignore this
7028 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7029 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7030 && !i
.tm
.opcode_modifier
.floatmf
7031 && !is_any_vex_encoding (&i
.tm
)
7032 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7033 || (flag_code
== CODE_64BIT
7034 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7036 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7038 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7039 prefix
= ADDR_PREFIX_OPCODE
;
7041 if (!add_prefix (prefix
))
7045 /* Set mode64 for an operand. */
7046 if (i
.suffix
== QWORD_MNEM_SUFFIX
7047 && flag_code
== CODE_64BIT
7048 && !i
.tm
.opcode_modifier
.norex64
7049 && !i
.tm
.opcode_modifier
.vexw
7050 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7052 && ! (i
.operands
== 2
7053 && i
.tm
.base_opcode
== 0x90
7054 && i
.tm
.extension_opcode
== None
7055 && i
.types
[0].bitfield
.instance
== Accum
7056 && i
.types
[0].bitfield
.qword
7057 && i
.types
[1].bitfield
.instance
== Accum
7058 && i
.types
[1].bitfield
.qword
))
7064 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7066 gas_assert (!i
.suffix
);
7067 gas_assert (i
.reg_operands
);
7069 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7072 /* The address size override prefix changes the size of the
7074 if (flag_code
== CODE_64BIT
7075 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7077 as_bad (_("16-bit addressing unavailable for `%s'"),
7082 if ((flag_code
== CODE_32BIT
7083 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7084 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7085 && !add_prefix (ADDR_PREFIX_OPCODE
))
7090 /* Check invalid register operand when the address size override
7091 prefix changes the size of register operands. */
7093 enum { need_word
, need_dword
, need_qword
} need
;
7095 if (flag_code
== CODE_32BIT
)
7096 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7097 else if (i
.prefix
[ADDR_PREFIX
])
7100 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7102 for (op
= 0; op
< i
.operands
; op
++)
7104 if (i
.types
[op
].bitfield
.class != Reg
)
7110 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7114 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7118 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7123 as_bad (_("invalid register operand size for `%s'"),
7134 check_byte_reg (void)
7138 for (op
= i
.operands
; --op
>= 0;)
7140 /* Skip non-register operands. */
7141 if (i
.types
[op
].bitfield
.class != Reg
)
7144 /* If this is an eight bit register, it's OK. If it's the 16 or
7145 32 bit version of an eight bit register, we will just use the
7146 low portion, and that's OK too. */
7147 if (i
.types
[op
].bitfield
.byte
)
7150 /* I/O port address operands are OK too. */
7151 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7152 && i
.tm
.operand_types
[op
].bitfield
.word
)
7155 /* crc32 only wants its source operand checked here. */
7156 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7159 /* Any other register is bad. */
7160 as_bad (_("`%s%s' not allowed with `%s%c'"),
7161 register_prefix
, i
.op
[op
].regs
->reg_name
,
7162 i
.tm
.name
, i
.suffix
);
7169 check_long_reg (void)
7173 for (op
= i
.operands
; --op
>= 0;)
7174 /* Skip non-register operands. */
7175 if (i
.types
[op
].bitfield
.class != Reg
)
7177 /* Reject eight bit registers, except where the template requires
7178 them. (eg. movzb) */
7179 else if (i
.types
[op
].bitfield
.byte
7180 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7181 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7182 && (i
.tm
.operand_types
[op
].bitfield
.word
7183 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7185 as_bad (_("`%s%s' not allowed with `%s%c'"),
7187 i
.op
[op
].regs
->reg_name
,
7192 /* Error if the e prefix on a general reg is missing. */
7193 else if (i
.types
[op
].bitfield
.word
7194 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7195 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7196 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7198 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7199 register_prefix
, i
.op
[op
].regs
->reg_name
,
7203 /* Warn if the r prefix on a general reg is present. */
7204 else if (i
.types
[op
].bitfield
.qword
7205 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7206 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7207 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7210 && i
.tm
.opcode_modifier
.toqword
7211 && i
.types
[0].bitfield
.class != RegSIMD
)
7213 /* Convert to QWORD. We want REX byte. */
7214 i
.suffix
= QWORD_MNEM_SUFFIX
;
7218 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7219 register_prefix
, i
.op
[op
].regs
->reg_name
,
7228 check_qword_reg (void)
7232 for (op
= i
.operands
; --op
>= 0; )
7233 /* Skip non-register operands. */
7234 if (i
.types
[op
].bitfield
.class != Reg
)
7236 /* Reject eight bit registers, except where the template requires
7237 them. (eg. movzb) */
7238 else if (i
.types
[op
].bitfield
.byte
7239 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7240 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7241 && (i
.tm
.operand_types
[op
].bitfield
.word
7242 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7244 as_bad (_("`%s%s' not allowed with `%s%c'"),
7246 i
.op
[op
].regs
->reg_name
,
7251 /* Warn if the r prefix on a general reg is missing. */
7252 else if ((i
.types
[op
].bitfield
.word
7253 || i
.types
[op
].bitfield
.dword
)
7254 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7255 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7256 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7258 /* Prohibit these changes in the 64bit mode, since the
7259 lowering is more complicated. */
7261 && i
.tm
.opcode_modifier
.todword
7262 && i
.types
[0].bitfield
.class != RegSIMD
)
7264 /* Convert to DWORD. We don't want REX byte. */
7265 i
.suffix
= LONG_MNEM_SUFFIX
;
7269 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7270 register_prefix
, i
.op
[op
].regs
->reg_name
,
7279 check_word_reg (void)
7282 for (op
= i
.operands
; --op
>= 0;)
7283 /* Skip non-register operands. */
7284 if (i
.types
[op
].bitfield
.class != Reg
)
7286 /* Reject eight bit registers, except where the template requires
7287 them. (eg. movzb) */
7288 else if (i
.types
[op
].bitfield
.byte
7289 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7290 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7291 && (i
.tm
.operand_types
[op
].bitfield
.word
7292 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7294 as_bad (_("`%s%s' not allowed with `%s%c'"),
7296 i
.op
[op
].regs
->reg_name
,
7301 /* Error if the e or r prefix on a general reg is present. */
7302 else if ((i
.types
[op
].bitfield
.dword
7303 || i
.types
[op
].bitfield
.qword
)
7304 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7305 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7306 && i
.tm
.operand_types
[op
].bitfield
.word
)
7308 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7309 register_prefix
, i
.op
[op
].regs
->reg_name
,
7317 update_imm (unsigned int j
)
7319 i386_operand_type overlap
= i
.types
[j
];
7320 if ((overlap
.bitfield
.imm8
7321 || overlap
.bitfield
.imm8s
7322 || overlap
.bitfield
.imm16
7323 || overlap
.bitfield
.imm32
7324 || overlap
.bitfield
.imm32s
7325 || overlap
.bitfield
.imm64
)
7326 && !operand_type_equal (&overlap
, &imm8
)
7327 && !operand_type_equal (&overlap
, &imm8s
)
7328 && !operand_type_equal (&overlap
, &imm16
)
7329 && !operand_type_equal (&overlap
, &imm32
)
7330 && !operand_type_equal (&overlap
, &imm32s
)
7331 && !operand_type_equal (&overlap
, &imm64
))
7335 i386_operand_type temp
;
7337 operand_type_set (&temp
, 0);
7338 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7340 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7341 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7343 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7344 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7345 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7347 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7348 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7351 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7354 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7355 || operand_type_equal (&overlap
, &imm16_32
)
7356 || operand_type_equal (&overlap
, &imm16_32s
))
7358 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7363 if (!operand_type_equal (&overlap
, &imm8
)
7364 && !operand_type_equal (&overlap
, &imm8s
)
7365 && !operand_type_equal (&overlap
, &imm16
)
7366 && !operand_type_equal (&overlap
, &imm32
)
7367 && !operand_type_equal (&overlap
, &imm32s
)
7368 && !operand_type_equal (&overlap
, &imm64
))
7370 as_bad (_("no instruction mnemonic suffix given; "
7371 "can't determine immediate size"));
7375 i
.types
[j
] = overlap
;
7385 /* Update the first 2 immediate operands. */
7386 n
= i
.operands
> 2 ? 2 : i
.operands
;
7389 for (j
= 0; j
< n
; j
++)
7390 if (update_imm (j
) == 0)
7393 /* The 3rd operand can't be immediate operand. */
7394 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7401 process_operands (void)
7403 /* Default segment register this instruction will use for memory
7404 accesses. 0 means unknown. This is only for optimizing out
7405 unnecessary segment overrides. */
7406 const seg_entry
*default_seg
= 0;
7408 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7410 unsigned int dupl
= i
.operands
;
7411 unsigned int dest
= dupl
- 1;
7414 /* The destination must be an xmm register. */
7415 gas_assert (i
.reg_operands
7416 && MAX_OPERANDS
> dupl
7417 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7419 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7420 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7422 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7424 /* Keep xmm0 for instructions with VEX prefix and 3
7426 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7427 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7432 /* We remove the first xmm0 and keep the number of
7433 operands unchanged, which in fact duplicates the
7435 for (j
= 1; j
< i
.operands
; j
++)
7437 i
.op
[j
- 1] = i
.op
[j
];
7438 i
.types
[j
- 1] = i
.types
[j
];
7439 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7440 i
.flags
[j
- 1] = i
.flags
[j
];
7444 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7446 gas_assert ((MAX_OPERANDS
- 1) > dupl
7447 && (i
.tm
.opcode_modifier
.vexsources
7450 /* Add the implicit xmm0 for instructions with VEX prefix
7452 for (j
= i
.operands
; j
> 0; j
--)
7454 i
.op
[j
] = i
.op
[j
- 1];
7455 i
.types
[j
] = i
.types
[j
- 1];
7456 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7457 i
.flags
[j
] = i
.flags
[j
- 1];
7460 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7461 i
.types
[0] = regxmm
;
7462 i
.tm
.operand_types
[0] = regxmm
;
7465 i
.reg_operands
+= 2;
7470 i
.op
[dupl
] = i
.op
[dest
];
7471 i
.types
[dupl
] = i
.types
[dest
];
7472 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7473 i
.flags
[dupl
] = i
.flags
[dest
];
7482 i
.op
[dupl
] = i
.op
[dest
];
7483 i
.types
[dupl
] = i
.types
[dest
];
7484 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7485 i
.flags
[dupl
] = i
.flags
[dest
];
7488 if (i
.tm
.opcode_modifier
.immext
)
7491 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7492 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7496 for (j
= 1; j
< i
.operands
; j
++)
7498 i
.op
[j
- 1] = i
.op
[j
];
7499 i
.types
[j
- 1] = i
.types
[j
];
7501 /* We need to adjust fields in i.tm since they are used by
7502 build_modrm_byte. */
7503 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7505 i
.flags
[j
- 1] = i
.flags
[j
];
7512 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7514 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7516 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7517 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7518 regnum
= register_number (i
.op
[1].regs
);
7519 first_reg_in_group
= regnum
& ~3;
7520 last_reg_in_group
= first_reg_in_group
+ 3;
7521 if (regnum
!= first_reg_in_group
)
7522 as_warn (_("source register `%s%s' implicitly denotes"
7523 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7524 register_prefix
, i
.op
[1].regs
->reg_name
,
7525 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7526 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7529 else if (i
.tm
.opcode_modifier
.regkludge
)
7531 /* The imul $imm, %reg instruction is converted into
7532 imul $imm, %reg, %reg, and the clr %reg instruction
7533 is converted into xor %reg, %reg. */
7535 unsigned int first_reg_op
;
7537 if (operand_type_check (i
.types
[0], reg
))
7541 /* Pretend we saw the extra register operand. */
7542 gas_assert (i
.reg_operands
== 1
7543 && i
.op
[first_reg_op
+ 1].regs
== 0);
7544 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7545 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7550 if (i
.tm
.opcode_modifier
.modrm
)
7552 /* The opcode is completed (modulo i.tm.extension_opcode which
7553 must be put into the modrm byte). Now, we make the modrm and
7554 index base bytes based on all the info we've collected. */
7556 default_seg
= build_modrm_byte ();
7558 else if (i
.types
[0].bitfield
.class == SReg
)
7560 if (flag_code
!= CODE_64BIT
7561 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7562 && i
.op
[0].regs
->reg_num
== 1
7563 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7564 && i
.op
[0].regs
->reg_num
< 4)
7566 as_bad (_("you can't `%s %s%s'"),
7567 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7570 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7572 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7573 i
.tm
.opcode_length
= 2;
7575 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7577 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7581 else if (i
.tm
.opcode_modifier
.isstring
)
7583 /* For the string instructions that allow a segment override
7584 on one of their operands, the default segment is ds. */
7587 else if (i
.short_form
)
7589 /* The register or float register operand is in operand
7591 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7593 /* Register goes in low 3 bits of opcode. */
7594 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7595 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7597 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7599 /* Warn about some common errors, but press on regardless.
7600 The first case can be generated by gcc (<= 2.8.1). */
7601 if (i
.operands
== 2)
7603 /* Reversed arguments on faddp, fsubp, etc. */
7604 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7605 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7606 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7610 /* Extraneous `l' suffix on fp insn. */
7611 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7612 register_prefix
, i
.op
[0].regs
->reg_name
);
7617 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7618 && i
.tm
.base_opcode
== 0x8d /* lea */
7619 && !is_any_vex_encoding(&i
.tm
))
7621 if (!quiet_warnings
)
7622 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7626 i
.prefix
[SEG_PREFIX
] = 0;
7630 /* If a segment was explicitly specified, and the specified segment
7631 is neither the default nor the one already recorded from a prefix,
7632 use an opcode prefix to select it. If we never figured out what
7633 the default segment is, then default_seg will be zero at this
7634 point, and the specified segment prefix will always be used. */
7636 && i
.seg
[0] != default_seg
7637 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7639 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7645 static const seg_entry
*
7646 build_modrm_byte (void)
7648 const seg_entry
*default_seg
= 0;
7649 unsigned int source
, dest
;
7652 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7655 unsigned int nds
, reg_slot
;
7658 dest
= i
.operands
- 1;
7661 /* There are 2 kinds of instructions:
7662 1. 5 operands: 4 register operands or 3 register operands
7663 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7664 VexW0 or VexW1. The destination must be either XMM, YMM or
7666 2. 4 operands: 4 register operands or 3 register operands
7667 plus 1 memory operand, with VexXDS. */
7668 gas_assert ((i
.reg_operands
== 4
7669 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7670 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7671 && i
.tm
.opcode_modifier
.vexw
7672 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7674 /* If VexW1 is set, the first non-immediate operand is the source and
7675 the second non-immediate one is encoded in the immediate operand. */
7676 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7678 source
= i
.imm_operands
;
7679 reg_slot
= i
.imm_operands
+ 1;
7683 source
= i
.imm_operands
+ 1;
7684 reg_slot
= i
.imm_operands
;
7687 if (i
.imm_operands
== 0)
7689 /* When there is no immediate operand, generate an 8bit
7690 immediate operand to encode the first operand. */
7691 exp
= &im_expressions
[i
.imm_operands
++];
7692 i
.op
[i
.operands
].imms
= exp
;
7693 i
.types
[i
.operands
] = imm8
;
7696 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7697 exp
->X_op
= O_constant
;
7698 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7699 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7703 gas_assert (i
.imm_operands
== 1);
7704 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7705 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7707 /* Turn on Imm8 again so that output_imm will generate it. */
7708 i
.types
[0].bitfield
.imm8
= 1;
7710 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7711 i
.op
[0].imms
->X_add_number
7712 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7713 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7716 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7717 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7722 /* i.reg_operands MUST be the number of real register operands;
7723 implicit registers do not count. If there are 3 register
7724 operands, it must be a instruction with VexNDS. For a
7725 instruction with VexNDD, the destination register is encoded
7726 in VEX prefix. If there are 4 register operands, it must be
7727 a instruction with VEX prefix and 3 sources. */
7728 if (i
.mem_operands
== 0
7729 && ((i
.reg_operands
== 2
7730 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7731 || (i
.reg_operands
== 3
7732 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7733 || (i
.reg_operands
== 4 && vex_3_sources
)))
7741 /* When there are 3 operands, one of them may be immediate,
7742 which may be the first or the last operand. Otherwise,
7743 the first operand must be shift count register (cl) or it
7744 is an instruction with VexNDS. */
7745 gas_assert (i
.imm_operands
== 1
7746 || (i
.imm_operands
== 0
7747 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7748 || (i
.types
[0].bitfield
.instance
== RegC
7749 && i
.types
[0].bitfield
.byte
))));
7750 if (operand_type_check (i
.types
[0], imm
)
7751 || (i
.types
[0].bitfield
.instance
== RegC
7752 && i
.types
[0].bitfield
.byte
))
7758 /* When there are 4 operands, the first two must be 8bit
7759 immediate operands. The source operand will be the 3rd
7762 For instructions with VexNDS, if the first operand
7763 an imm8, the source operand is the 2nd one. If the last
7764 operand is imm8, the source operand is the first one. */
7765 gas_assert ((i
.imm_operands
== 2
7766 && i
.types
[0].bitfield
.imm8
7767 && i
.types
[1].bitfield
.imm8
)
7768 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7769 && i
.imm_operands
== 1
7770 && (i
.types
[0].bitfield
.imm8
7771 || i
.types
[i
.operands
- 1].bitfield
.imm8
7773 if (i
.imm_operands
== 2)
7777 if (i
.types
[0].bitfield
.imm8
)
7784 if (is_evex_encoding (&i
.tm
))
7786 /* For EVEX instructions, when there are 5 operands, the
7787 first one must be immediate operand. If the second one
7788 is immediate operand, the source operand is the 3th
7789 one. If the last one is immediate operand, the source
7790 operand is the 2nd one. */
7791 gas_assert (i
.imm_operands
== 2
7792 && i
.tm
.opcode_modifier
.sae
7793 && operand_type_check (i
.types
[0], imm
));
7794 if (operand_type_check (i
.types
[1], imm
))
7796 else if (operand_type_check (i
.types
[4], imm
))
7810 /* RC/SAE operand could be between DEST and SRC. That happens
7811 when one operand is GPR and the other one is XMM/YMM/ZMM
7813 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7816 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7818 /* For instructions with VexNDS, the register-only source
7819 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7820 register. It is encoded in VEX prefix. */
7822 i386_operand_type op
;
7825 /* Check register-only source operand when two source
7826 operands are swapped. */
7827 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7828 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7836 op
= i
.tm
.operand_types
[vvvv
];
7837 if ((dest
+ 1) >= i
.operands
7838 || ((op
.bitfield
.class != Reg
7839 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7840 && op
.bitfield
.class != RegSIMD
7841 && !operand_type_equal (&op
, ®mask
)))
7843 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7849 /* One of the register operands will be encoded in the i.rm.reg
7850 field, the other in the combined i.rm.mode and i.rm.regmem
7851 fields. If no form of this instruction supports a memory
7852 destination operand, then we assume the source operand may
7853 sometimes be a memory operand and so we need to store the
7854 destination in the i.rm.reg field. */
7855 if (!i
.tm
.opcode_modifier
.regmem
7856 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7858 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7859 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7860 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7861 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7862 i
.has_regmmx
= TRUE
;
7863 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7864 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7866 if (i
.types
[dest
].bitfield
.zmmword
7867 || i
.types
[source
].bitfield
.zmmword
)
7868 i
.has_regzmm
= TRUE
;
7869 else if (i
.types
[dest
].bitfield
.ymmword
7870 || i
.types
[source
].bitfield
.ymmword
)
7871 i
.has_regymm
= TRUE
;
7873 i
.has_regxmm
= TRUE
;
7875 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7877 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7879 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7881 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7886 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7887 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7888 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7890 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7892 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7894 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7897 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7899 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7902 add_prefix (LOCK_PREFIX_OPCODE
);
7906 { /* If it's not 2 reg operands... */
7911 unsigned int fake_zero_displacement
= 0;
7914 for (op
= 0; op
< i
.operands
; op
++)
7915 if (i
.flags
[op
] & Operand_Mem
)
7917 gas_assert (op
< i
.operands
);
7919 if (i
.tm
.opcode_modifier
.vecsib
)
7921 if (i
.index_reg
->reg_num
== RegIZ
)
7924 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7927 i
.sib
.base
= NO_BASE_REGISTER
;
7928 i
.sib
.scale
= i
.log2_scale_factor
;
7929 i
.types
[op
].bitfield
.disp8
= 0;
7930 i
.types
[op
].bitfield
.disp16
= 0;
7931 i
.types
[op
].bitfield
.disp64
= 0;
7932 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7934 /* Must be 32 bit */
7935 i
.types
[op
].bitfield
.disp32
= 1;
7936 i
.types
[op
].bitfield
.disp32s
= 0;
7940 i
.types
[op
].bitfield
.disp32
= 0;
7941 i
.types
[op
].bitfield
.disp32s
= 1;
7944 i
.sib
.index
= i
.index_reg
->reg_num
;
7945 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7947 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7953 if (i
.base_reg
== 0)
7956 if (!i
.disp_operands
)
7957 fake_zero_displacement
= 1;
7958 if (i
.index_reg
== 0)
7960 i386_operand_type newdisp
;
7962 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7963 /* Operand is just <disp> */
7964 if (flag_code
== CODE_64BIT
)
7966 /* 64bit mode overwrites the 32bit absolute
7967 addressing by RIP relative addressing and
7968 absolute addressing is encoded by one of the
7969 redundant SIB forms. */
7970 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7971 i
.sib
.base
= NO_BASE_REGISTER
;
7972 i
.sib
.index
= NO_INDEX_REGISTER
;
7973 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7975 else if ((flag_code
== CODE_16BIT
)
7976 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7978 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7983 i
.rm
.regmem
= NO_BASE_REGISTER
;
7986 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7987 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7989 else if (!i
.tm
.opcode_modifier
.vecsib
)
7991 /* !i.base_reg && i.index_reg */
7992 if (i
.index_reg
->reg_num
== RegIZ
)
7993 i
.sib
.index
= NO_INDEX_REGISTER
;
7995 i
.sib
.index
= i
.index_reg
->reg_num
;
7996 i
.sib
.base
= NO_BASE_REGISTER
;
7997 i
.sib
.scale
= i
.log2_scale_factor
;
7998 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7999 i
.types
[op
].bitfield
.disp8
= 0;
8000 i
.types
[op
].bitfield
.disp16
= 0;
8001 i
.types
[op
].bitfield
.disp64
= 0;
8002 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8004 /* Must be 32 bit */
8005 i
.types
[op
].bitfield
.disp32
= 1;
8006 i
.types
[op
].bitfield
.disp32s
= 0;
8010 i
.types
[op
].bitfield
.disp32
= 0;
8011 i
.types
[op
].bitfield
.disp32s
= 1;
8013 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8017 /* RIP addressing for 64bit mode. */
8018 else if (i
.base_reg
->reg_num
== RegIP
)
8020 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8021 i
.rm
.regmem
= NO_BASE_REGISTER
;
8022 i
.types
[op
].bitfield
.disp8
= 0;
8023 i
.types
[op
].bitfield
.disp16
= 0;
8024 i
.types
[op
].bitfield
.disp32
= 0;
8025 i
.types
[op
].bitfield
.disp32s
= 1;
8026 i
.types
[op
].bitfield
.disp64
= 0;
8027 i
.flags
[op
] |= Operand_PCrel
;
8028 if (! i
.disp_operands
)
8029 fake_zero_displacement
= 1;
8031 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8033 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8034 switch (i
.base_reg
->reg_num
)
8037 if (i
.index_reg
== 0)
8039 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8040 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8044 if (i
.index_reg
== 0)
8047 if (operand_type_check (i
.types
[op
], disp
) == 0)
8049 /* fake (%bp) into 0(%bp) */
8050 i
.types
[op
].bitfield
.disp8
= 1;
8051 fake_zero_displacement
= 1;
8054 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8055 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8057 default: /* (%si) -> 4 or (%di) -> 5 */
8058 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8060 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8062 else /* i.base_reg and 32/64 bit mode */
8064 if (flag_code
== CODE_64BIT
8065 && operand_type_check (i
.types
[op
], disp
))
8067 i
.types
[op
].bitfield
.disp16
= 0;
8068 i
.types
[op
].bitfield
.disp64
= 0;
8069 if (i
.prefix
[ADDR_PREFIX
] == 0)
8071 i
.types
[op
].bitfield
.disp32
= 0;
8072 i
.types
[op
].bitfield
.disp32s
= 1;
8076 i
.types
[op
].bitfield
.disp32
= 1;
8077 i
.types
[op
].bitfield
.disp32s
= 0;
8081 if (!i
.tm
.opcode_modifier
.vecsib
)
8082 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8083 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8085 i
.sib
.base
= i
.base_reg
->reg_num
;
8086 /* x86-64 ignores REX prefix bit here to avoid decoder
8088 if (!(i
.base_reg
->reg_flags
& RegRex
)
8089 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8090 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8092 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8094 fake_zero_displacement
= 1;
8095 i
.types
[op
].bitfield
.disp8
= 1;
8097 i
.sib
.scale
= i
.log2_scale_factor
;
8098 if (i
.index_reg
== 0)
8100 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8101 /* <disp>(%esp) becomes two byte modrm with no index
8102 register. We've already stored the code for esp
8103 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8104 Any base register besides %esp will not use the
8105 extra modrm byte. */
8106 i
.sib
.index
= NO_INDEX_REGISTER
;
8108 else if (!i
.tm
.opcode_modifier
.vecsib
)
8110 if (i
.index_reg
->reg_num
== RegIZ
)
8111 i
.sib
.index
= NO_INDEX_REGISTER
;
8113 i
.sib
.index
= i
.index_reg
->reg_num
;
8114 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8115 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8120 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8121 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8125 if (!fake_zero_displacement
8129 fake_zero_displacement
= 1;
8130 if (i
.disp_encoding
== disp_encoding_8bit
)
8131 i
.types
[op
].bitfield
.disp8
= 1;
8133 i
.types
[op
].bitfield
.disp32
= 1;
8135 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8139 if (fake_zero_displacement
)
8141 /* Fakes a zero displacement assuming that i.types[op]
8142 holds the correct displacement size. */
8145 gas_assert (i
.op
[op
].disps
== 0);
8146 exp
= &disp_expressions
[i
.disp_operands
++];
8147 i
.op
[op
].disps
= exp
;
8148 exp
->X_op
= O_constant
;
8149 exp
->X_add_number
= 0;
8150 exp
->X_add_symbol
= (symbolS
*) 0;
8151 exp
->X_op_symbol
= (symbolS
*) 0;
8159 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8161 if (operand_type_check (i
.types
[0], imm
))
8162 i
.vex
.register_specifier
= NULL
;
8165 /* VEX.vvvv encodes one of the sources when the first
8166 operand is not an immediate. */
8167 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8168 i
.vex
.register_specifier
= i
.op
[0].regs
;
8170 i
.vex
.register_specifier
= i
.op
[1].regs
;
8173 /* Destination is a XMM register encoded in the ModRM.reg
8175 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8176 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8179 /* ModRM.rm and VEX.B encodes the other source. */
8180 if (!i
.mem_operands
)
8184 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8185 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8187 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8189 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8193 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8195 i
.vex
.register_specifier
= i
.op
[2].regs
;
8196 if (!i
.mem_operands
)
8199 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8200 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8204 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8205 (if any) based on i.tm.extension_opcode. Again, we must be
8206 careful to make sure that segment/control/debug/test/MMX
8207 registers are coded into the i.rm.reg field. */
8208 else if (i
.reg_operands
)
8211 unsigned int vex_reg
= ~0;
8213 for (op
= 0; op
< i
.operands
; op
++)
8215 if (i
.types
[op
].bitfield
.class == Reg
8216 || i
.types
[op
].bitfield
.class == RegBND
8217 || i
.types
[op
].bitfield
.class == RegMask
8218 || i
.types
[op
].bitfield
.class == SReg
8219 || i
.types
[op
].bitfield
.class == RegCR
8220 || i
.types
[op
].bitfield
.class == RegDR
8221 || i
.types
[op
].bitfield
.class == RegTR
)
8223 if (i
.types
[op
].bitfield
.class == RegSIMD
)
8225 if (i
.types
[op
].bitfield
.zmmword
)
8226 i
.has_regzmm
= TRUE
;
8227 else if (i
.types
[op
].bitfield
.ymmword
)
8228 i
.has_regymm
= TRUE
;
8230 i
.has_regxmm
= TRUE
;
8233 if (i
.types
[op
].bitfield
.class == RegMMX
)
8235 i
.has_regmmx
= TRUE
;
8242 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8244 /* For instructions with VexNDS, the register-only
8245 source operand is encoded in VEX prefix. */
8246 gas_assert (mem
!= (unsigned int) ~0);
8251 gas_assert (op
< i
.operands
);
8255 /* Check register-only source operand when two source
8256 operands are swapped. */
8257 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8258 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8262 gas_assert (mem
== (vex_reg
+ 1)
8263 && op
< i
.operands
);
8268 gas_assert (vex_reg
< i
.operands
);
8272 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8274 /* For instructions with VexNDD, the register destination
8275 is encoded in VEX prefix. */
8276 if (i
.mem_operands
== 0)
8278 /* There is no memory operand. */
8279 gas_assert ((op
+ 2) == i
.operands
);
8284 /* There are only 2 non-immediate operands. */
8285 gas_assert (op
< i
.imm_operands
+ 2
8286 && i
.operands
== i
.imm_operands
+ 2);
8287 vex_reg
= i
.imm_operands
+ 1;
8291 gas_assert (op
< i
.operands
);
8293 if (vex_reg
!= (unsigned int) ~0)
8295 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8297 if ((type
->bitfield
.class != Reg
8298 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8299 && type
->bitfield
.class != RegSIMD
8300 && !operand_type_equal (type
, ®mask
))
8303 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8306 /* Don't set OP operand twice. */
8309 /* If there is an extension opcode to put here, the
8310 register number must be put into the regmem field. */
8311 if (i
.tm
.extension_opcode
!= None
)
8313 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8314 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
8316 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
8321 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8322 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
8324 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
8329 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8330 must set it to 3 to indicate this is a register operand
8331 in the regmem field. */
8332 if (!i
.mem_operands
)
8336 /* Fill in i.rm.reg field with extension opcode (if any). */
8337 if (i
.tm
.extension_opcode
!= None
)
8338 i
.rm
.reg
= i
.tm
.extension_opcode
;
8344 flip_code16 (unsigned int code16
)
8346 gas_assert (i
.tm
.operands
== 1);
8348 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8349 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8350 || i
.tm
.operand_types
[0].bitfield
.disp32s
8351 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8356 output_branch (void)
8362 relax_substateT subtype
;
8366 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8367 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8370 if (i
.prefix
[DATA_PREFIX
] != 0)
8374 code16
^= flip_code16(code16
);
8376 /* Pentium4 branch hints. */
8377 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8378 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8383 if (i
.prefix
[REX_PREFIX
] != 0)
8389 /* BND prefixed jump. */
8390 if (i
.prefix
[BND_PREFIX
] != 0)
8396 if (i
.prefixes
!= 0)
8397 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8399 /* It's always a symbol; End frag & setup for relax.
8400 Make sure there is enough room in this frag for the largest
8401 instruction we may generate in md_convert_frag. This is 2
8402 bytes for the opcode and room for the prefix and largest
8404 frag_grow (prefix
+ 2 + 4);
8405 /* Prefix and 1 opcode byte go in fr_fix. */
8406 p
= frag_more (prefix
+ 1);
8407 if (i
.prefix
[DATA_PREFIX
] != 0)
8408 *p
++ = DATA_PREFIX_OPCODE
;
8409 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8410 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8411 *p
++ = i
.prefix
[SEG_PREFIX
];
8412 if (i
.prefix
[BND_PREFIX
] != 0)
8413 *p
++ = BND_PREFIX_OPCODE
;
8414 if (i
.prefix
[REX_PREFIX
] != 0)
8415 *p
++ = i
.prefix
[REX_PREFIX
];
8416 *p
= i
.tm
.base_opcode
;
8418 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8419 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8420 else if (cpu_arch_flags
.bitfield
.cpui386
)
8421 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8423 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8426 sym
= i
.op
[0].disps
->X_add_symbol
;
8427 off
= i
.op
[0].disps
->X_add_number
;
8429 if (i
.op
[0].disps
->X_op
!= O_constant
8430 && i
.op
[0].disps
->X_op
!= O_symbol
)
8432 /* Handle complex expressions. */
8433 sym
= make_expr_symbol (i
.op
[0].disps
);
8437 /* 1 possible extra opcode + 4 byte displacement go in var part.
8438 Pass reloc in fr_var. */
8439 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8442 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8443 /* Return TRUE iff PLT32 relocation should be used for branching to
8447 need_plt32_p (symbolS
*s
)
8449 /* PLT32 relocation is ELF only. */
8454 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8455 krtld support it. */
8459 /* Since there is no need to prepare for PLT branch on x86-64, we
8460 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8461 be used as a marker for 32-bit PC-relative branches. */
8465 /* Weak or undefined symbol need PLT32 relocation. */
8466 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8469 /* Non-global symbol doesn't need PLT32 relocation. */
8470 if (! S_IS_EXTERNAL (s
))
8473 /* Other global symbols need PLT32 relocation. NB: Symbol with
8474 non-default visibilities are treated as normal global symbol
8475 so that PLT32 relocation can be used as a marker for 32-bit
8476 PC-relative branches. It is useful for linker relaxation. */
8487 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8489 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8491 /* This is a loop or jecxz type instruction. */
8493 if (i
.prefix
[ADDR_PREFIX
] != 0)
8495 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8498 /* Pentium4 branch hints. */
8499 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8500 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8502 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8511 if (flag_code
== CODE_16BIT
)
8514 if (i
.prefix
[DATA_PREFIX
] != 0)
8516 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8518 code16
^= flip_code16(code16
);
8526 /* BND prefixed jump. */
8527 if (i
.prefix
[BND_PREFIX
] != 0)
8529 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8533 if (i
.prefix
[REX_PREFIX
] != 0)
8535 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8539 if (i
.prefixes
!= 0)
8540 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8542 p
= frag_more (i
.tm
.opcode_length
+ size
);
8543 switch (i
.tm
.opcode_length
)
8546 *p
++ = i
.tm
.base_opcode
>> 8;
8549 *p
++ = i
.tm
.base_opcode
;
8555 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8557 && jump_reloc
== NO_RELOC
8558 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8559 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8562 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8564 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8565 i
.op
[0].disps
, 1, jump_reloc
);
8567 /* All jumps handled here are signed, but don't use a signed limit
8568 check for 32 and 16 bit jumps as we want to allow wrap around at
8569 4G and 64k respectively. */
8571 fixP
->fx_signed
= 1;
8575 output_interseg_jump (void)
8583 if (flag_code
== CODE_16BIT
)
8587 if (i
.prefix
[DATA_PREFIX
] != 0)
8594 gas_assert (!i
.prefix
[REX_PREFIX
]);
8600 if (i
.prefixes
!= 0)
8601 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8603 /* 1 opcode; 2 segment; offset */
8604 p
= frag_more (prefix
+ 1 + 2 + size
);
8606 if (i
.prefix
[DATA_PREFIX
] != 0)
8607 *p
++ = DATA_PREFIX_OPCODE
;
8609 if (i
.prefix
[REX_PREFIX
] != 0)
8610 *p
++ = i
.prefix
[REX_PREFIX
];
8612 *p
++ = i
.tm
.base_opcode
;
8613 if (i
.op
[1].imms
->X_op
== O_constant
)
8615 offsetT n
= i
.op
[1].imms
->X_add_number
;
8618 && !fits_in_unsigned_word (n
)
8619 && !fits_in_signed_word (n
))
8621 as_bad (_("16-bit jump out of range"));
8624 md_number_to_chars (p
, n
, size
);
8627 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8628 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8629 if (i
.op
[0].imms
->X_op
!= O_constant
)
8630 as_bad (_("can't handle non absolute segment in `%s'"),
8632 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8635 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8640 asection
*seg
= now_seg
;
8641 subsegT subseg
= now_subseg
;
8643 unsigned int alignment
, align_size_1
;
8644 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8645 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8646 unsigned int padding
;
8648 if (!IS_ELF
|| !x86_used_note
)
8651 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8653 /* The .note.gnu.property section layout:
8655 Field Length Contents
8658 n_descsz 4 The note descriptor size
8659 n_type 4 NT_GNU_PROPERTY_TYPE_0
8661 n_desc n_descsz The program property array
8665 /* Create the .note.gnu.property section. */
8666 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8667 bfd_set_section_flags (sec
,
8674 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8685 bfd_set_section_alignment (sec
, alignment
);
8686 elf_section_type (sec
) = SHT_NOTE
;
8688 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8690 isa_1_descsz_raw
= 4 + 4 + 4;
8691 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8692 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8694 feature_2_descsz_raw
= isa_1_descsz
;
8695 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8697 feature_2_descsz_raw
+= 4 + 4 + 4;
8698 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8699 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8702 descsz
= feature_2_descsz
;
8703 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8704 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8706 /* Write n_namsz. */
8707 md_number_to_chars (p
, (valueT
) 4, 4);
8709 /* Write n_descsz. */
8710 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8713 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8716 memcpy (p
+ 4 * 3, "GNU", 4);
8718 /* Write 4-byte type. */
8719 md_number_to_chars (p
+ 4 * 4,
8720 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8722 /* Write 4-byte data size. */
8723 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8725 /* Write 4-byte data. */
8726 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8728 /* Zero out paddings. */
8729 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8731 memset (p
+ 4 * 7, 0, padding
);
8733 /* Write 4-byte type. */
8734 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8735 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8737 /* Write 4-byte data size. */
8738 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8740 /* Write 4-byte data. */
8741 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8742 (valueT
) x86_feature_2_used
, 4);
8744 /* Zero out paddings. */
8745 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8747 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8749 /* We probably can't restore the current segment, for there likely
8752 subseg_set (seg
, subseg
);
8757 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8758 const char *frag_now_ptr
)
8760 unsigned int len
= 0;
8762 if (start_frag
!= frag_now
)
8764 const fragS
*fr
= start_frag
;
8769 } while (fr
&& fr
!= frag_now
);
8772 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8775 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8776 be macro-fused with conditional jumps.
8777 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8778 or is one of the following format:
8791 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8793 /* No RIP address. */
8794 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8797 /* No VEX/EVEX encoding. */
8798 if (is_any_vex_encoding (&i
.tm
))
8801 /* add, sub without add/sub m, imm. */
8802 if (i
.tm
.base_opcode
<= 5
8803 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8804 || ((i
.tm
.base_opcode
| 3) == 0x83
8805 && (i
.tm
.extension_opcode
== 0x5
8806 || i
.tm
.extension_opcode
== 0x0)))
8808 *mf_cmp_p
= mf_cmp_alu_cmp
;
8809 return !(i
.mem_operands
&& i
.imm_operands
);
8812 /* and without and m, imm. */
8813 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8814 || ((i
.tm
.base_opcode
| 3) == 0x83
8815 && i
.tm
.extension_opcode
== 0x4))
8817 *mf_cmp_p
= mf_cmp_test_and
;
8818 return !(i
.mem_operands
&& i
.imm_operands
);
8821 /* test without test m imm. */
8822 if ((i
.tm
.base_opcode
| 1) == 0x85
8823 || (i
.tm
.base_opcode
| 1) == 0xa9
8824 || ((i
.tm
.base_opcode
| 1) == 0xf7
8825 && i
.tm
.extension_opcode
== 0))
8827 *mf_cmp_p
= mf_cmp_test_and
;
8828 return !(i
.mem_operands
&& i
.imm_operands
);
8831 /* cmp without cmp m, imm. */
8832 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8833 || ((i
.tm
.base_opcode
| 3) == 0x83
8834 && (i
.tm
.extension_opcode
== 0x7)))
8836 *mf_cmp_p
= mf_cmp_alu_cmp
;
8837 return !(i
.mem_operands
&& i
.imm_operands
);
8840 /* inc, dec without inc/dec m. */
8841 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8842 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8843 || ((i
.tm
.base_opcode
| 1) == 0xff
8844 && i
.tm
.extension_opcode
<= 0x1))
8846 *mf_cmp_p
= mf_cmp_incdec
;
8847 return !i
.mem_operands
;
8853 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8856 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8858 /* NB: Don't work with COND_JUMP86 without i386. */
8859 if (!align_branch_power
8860 || now_seg
== absolute_section
8861 || !cpu_arch_flags
.bitfield
.cpui386
8862 || !(align_branch
& align_branch_fused_bit
))
8865 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8867 if (last_insn
.kind
== last_insn_other
8868 || last_insn
.seg
!= now_seg
)
8871 as_warn_where (last_insn
.file
, last_insn
.line
,
8872 _("`%s` skips -malign-branch-boundary on `%s`"),
8873 last_insn
.name
, i
.tm
.name
);
8879 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8882 add_branch_prefix_frag_p (void)
8884 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8885 to PadLock instructions since they include prefixes in opcode. */
8886 if (!align_branch_power
8887 || !align_branch_prefix_size
8888 || now_seg
== absolute_section
8889 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8890 || !cpu_arch_flags
.bitfield
.cpui386
)
8893 /* Don't add prefix if it is a prefix or there is no operand in case
8894 that segment prefix is special. */
8895 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8898 if (last_insn
.kind
== last_insn_other
8899 || last_insn
.seg
!= now_seg
)
8903 as_warn_where (last_insn
.file
, last_insn
.line
,
8904 _("`%s` skips -malign-branch-boundary on `%s`"),
8905 last_insn
.name
, i
.tm
.name
);
8910 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8913 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8914 enum mf_jcc_kind
*mf_jcc_p
)
8918 /* NB: Don't work with COND_JUMP86 without i386. */
8919 if (!align_branch_power
8920 || now_seg
== absolute_section
8921 || !cpu_arch_flags
.bitfield
.cpui386
)
8926 /* Check for jcc and direct jmp. */
8927 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8929 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8931 *branch_p
= align_branch_jmp
;
8932 add_padding
= align_branch
& align_branch_jmp_bit
;
8936 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8937 igore the lowest bit. */
8938 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8939 *branch_p
= align_branch_jcc
;
8940 if ((align_branch
& align_branch_jcc_bit
))
8944 else if (is_any_vex_encoding (&i
.tm
))
8946 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8949 *branch_p
= align_branch_ret
;
8950 if ((align_branch
& align_branch_ret_bit
))
8955 /* Check for indirect jmp, direct and indirect calls. */
8956 if (i
.tm
.base_opcode
== 0xe8)
8959 *branch_p
= align_branch_call
;
8960 if ((align_branch
& align_branch_call_bit
))
8963 else if (i
.tm
.base_opcode
== 0xff
8964 && (i
.tm
.extension_opcode
== 2
8965 || i
.tm
.extension_opcode
== 4))
8967 /* Indirect call and jmp. */
8968 *branch_p
= align_branch_indirect
;
8969 if ((align_branch
& align_branch_indirect_bit
))
8976 && (i
.op
[0].disps
->X_op
== O_symbol
8977 || (i
.op
[0].disps
->X_op
== O_subtract
8978 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8980 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8981 /* No padding to call to global or undefined tls_get_addr. */
8982 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8983 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8989 && last_insn
.kind
!= last_insn_other
8990 && last_insn
.seg
== now_seg
)
8993 as_warn_where (last_insn
.file
, last_insn
.line
,
8994 _("`%s` skips -malign-branch-boundary on `%s`"),
8995 last_insn
.name
, i
.tm
.name
);
9005 fragS
*insn_start_frag
;
9006 offsetT insn_start_off
;
9007 fragS
*fragP
= NULL
;
9008 enum align_branch_kind branch
= align_branch_none
;
9009 /* The initializer is arbitrary just to avoid uninitialized error.
9010 it's actually either assigned in add_branch_padding_frag_p
9011 or never be used. */
9012 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9015 if (IS_ELF
&& x86_used_note
)
9017 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
9018 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
9019 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
9020 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
9021 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
9022 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
9023 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
9024 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
9025 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
9026 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
9027 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
9028 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
9029 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
9030 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
9031 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9032 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
9033 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
9034 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
9035 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
9036 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
9037 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
9038 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
9039 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
9040 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
9041 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
9042 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
9043 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
9044 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
9045 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
9046 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
9047 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
9048 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
9049 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
9050 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
9051 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
9052 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
9053 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
9054 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
9055 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
9056 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
9057 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
9058 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
9059 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
9060 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9061 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9062 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9063 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9064 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9065 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9066 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9068 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9069 || i
.tm
.cpu_flags
.bitfield
.cpu287
9070 || i
.tm
.cpu_flags
.bitfield
.cpu387
9071 || i
.tm
.cpu_flags
.bitfield
.cpu687
9072 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9073 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9075 || i
.tm
.base_opcode
== 0xf77 /* emms */
9076 || i
.tm
.base_opcode
== 0xf0e /* femms */
9077 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
9078 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
9079 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9081 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9083 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9085 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9086 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9087 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9088 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9089 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9090 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9091 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9092 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9093 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9097 /* Tie dwarf2 debug info to the address at the start of the insn.
9098 We can't do this after the insn has been output as the current
9099 frag may have been closed off. eg. by frag_var. */
9100 dwarf2_emit_insn (0);
9102 insn_start_frag
= frag_now
;
9103 insn_start_off
= frag_now_fix ();
9105 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9108 /* Branch can be 8 bytes. Leave some room for prefixes. */
9109 unsigned int max_branch_padding_size
= 14;
9111 /* Align section to boundary. */
9112 record_alignment (now_seg
, align_branch_power
);
9114 /* Make room for padding. */
9115 frag_grow (max_branch_padding_size
);
9117 /* Start of the padding. */
9122 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9123 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9126 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9127 fragP
->tc_frag_data
.branch_type
= branch
;
9128 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9132 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9134 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9135 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9137 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9138 output_interseg_jump ();
9141 /* Output normal instructions here. */
9145 unsigned int prefix
;
9146 enum mf_cmp_kind mf_cmp
;
9149 && (i
.tm
.base_opcode
== 0xfaee8
9150 || i
.tm
.base_opcode
== 0xfaef0
9151 || i
.tm
.base_opcode
== 0xfaef8))
9153 /* Encode lfence, mfence, and sfence as
9154 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9155 offsetT val
= 0x240483f0ULL
;
9157 md_number_to_chars (p
, val
, 5);
9161 /* Some processors fail on LOCK prefix. This options makes
9162 assembler ignore LOCK prefix and serves as a workaround. */
9163 if (omit_lock_prefix
)
9165 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9167 i
.prefix
[LOCK_PREFIX
] = 0;
9171 /* Skip if this is a branch. */
9173 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9175 /* Make room for padding. */
9176 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9181 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9182 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9185 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9186 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9187 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9189 else if (add_branch_prefix_frag_p ())
9191 unsigned int max_prefix_size
= align_branch_prefix_size
;
9193 /* Make room for padding. */
9194 frag_grow (max_prefix_size
);
9199 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9200 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9203 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9206 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9207 don't need the explicit prefix. */
9208 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9210 switch (i
.tm
.opcode_length
)
9213 if (i
.tm
.base_opcode
& 0xff000000)
9215 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9216 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9217 || prefix
!= REPE_PREFIX_OPCODE
9218 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9219 add_prefix (prefix
);
9223 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9225 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9226 add_prefix (prefix
);
9232 /* Check for pseudo prefixes. */
9233 as_bad_where (insn_start_frag
->fr_file
,
9234 insn_start_frag
->fr_line
,
9235 _("pseudo prefix without instruction"));
9241 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9242 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9243 R_X86_64_GOTTPOFF relocation so that linker can safely
9244 perform IE->LE optimization. A dummy REX_OPCODE prefix
9245 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9246 relocation for GDesc -> IE/LE optimization. */
9247 if (x86_elf_abi
== X86_64_X32_ABI
9249 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9250 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9251 && i
.prefix
[REX_PREFIX
] == 0)
9252 add_prefix (REX_OPCODE
);
9255 /* The prefix bytes. */
9256 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9258 FRAG_APPEND_1_CHAR (*q
);
9262 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9267 /* REX byte is encoded in VEX prefix. */
9271 FRAG_APPEND_1_CHAR (*q
);
9274 /* There should be no other prefixes for instructions
9279 /* For EVEX instructions i.vrex should become 0 after
9280 build_evex_prefix. For VEX instructions upper 16 registers
9281 aren't available, so VREX should be 0. */
9284 /* Now the VEX prefix. */
9285 p
= frag_more (i
.vex
.length
);
9286 for (j
= 0; j
< i
.vex
.length
; j
++)
9287 p
[j
] = i
.vex
.bytes
[j
];
9290 /* Now the opcode; be careful about word order here! */
9291 if (i
.tm
.opcode_length
== 1)
9293 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9297 switch (i
.tm
.opcode_length
)
9301 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9302 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9306 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9316 /* Put out high byte first: can't use md_number_to_chars! */
9317 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9318 *p
= i
.tm
.base_opcode
& 0xff;
9321 /* Now the modrm byte and sib byte (if present). */
9322 if (i
.tm
.opcode_modifier
.modrm
)
9324 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
9327 /* If i.rm.regmem == ESP (4)
9328 && i.rm.mode != (Register mode)
9330 ==> need second modrm byte. */
9331 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9333 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9334 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
9336 | i
.sib
.scale
<< 6));
9339 if (i
.disp_operands
)
9340 output_disp (insn_start_frag
, insn_start_off
);
9343 output_imm (insn_start_frag
, insn_start_off
);
9346 * frag_now_fix () returning plain abs_section_offset when we're in the
9347 * absolute section, and abs_section_offset not getting updated as data
9348 * gets added to the frag breaks the logic below.
9350 if (now_seg
!= absolute_section
)
9352 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9354 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9358 /* NB: Don't add prefix with GOTPC relocation since
9359 output_disp() above depends on the fixed encoding
9360 length. Can't add prefix with TLS relocation since
9361 it breaks TLS linker optimization. */
9362 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9363 /* Prefix count on the current instruction. */
9364 unsigned int count
= i
.vex
.length
;
9366 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9367 /* REX byte is encoded in VEX/EVEX prefix. */
9368 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9371 /* Count prefixes for extended opcode maps. */
9373 switch (i
.tm
.opcode_length
)
9376 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9379 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9391 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9400 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9403 /* Set the maximum prefix size in BRANCH_PREFIX
9405 if (fragP
->tc_frag_data
.max_bytes
> max
)
9406 fragP
->tc_frag_data
.max_bytes
= max
;
9407 if (fragP
->tc_frag_data
.max_bytes
> count
)
9408 fragP
->tc_frag_data
.max_bytes
-= count
;
9410 fragP
->tc_frag_data
.max_bytes
= 0;
9414 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9416 unsigned int max_prefix_size
;
9417 if (align_branch_prefix_size
> max
)
9418 max_prefix_size
= max
;
9420 max_prefix_size
= align_branch_prefix_size
;
9421 if (max_prefix_size
> count
)
9422 fragP
->tc_frag_data
.max_prefix_length
9423 = max_prefix_size
- count
;
9426 /* Use existing segment prefix if possible. Use CS
9427 segment prefix in 64-bit mode. In 32-bit mode, use SS
9428 segment prefix with ESP/EBP base register and use DS
9429 segment prefix without ESP/EBP base register. */
9430 if (i
.prefix
[SEG_PREFIX
])
9431 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9432 else if (flag_code
== CODE_64BIT
)
9433 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9435 && (i
.base_reg
->reg_num
== 4
9436 || i
.base_reg
->reg_num
== 5))
9437 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9439 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9444 /* NB: Don't work with COND_JUMP86 without i386. */
9445 if (align_branch_power
9446 && now_seg
!= absolute_section
9447 && cpu_arch_flags
.bitfield
.cpui386
)
9449 /* Terminate each frag so that we can add prefix and check for
9451 frag_wane (frag_now
);
9458 pi ("" /*line*/, &i
);
9460 #endif /* DEBUG386 */
9463 /* Return the size of the displacement operand N. */
9466 disp_size (unsigned int n
)
9470 if (i
.types
[n
].bitfield
.disp64
)
9472 else if (i
.types
[n
].bitfield
.disp8
)
9474 else if (i
.types
[n
].bitfield
.disp16
)
9479 /* Return the size of the immediate operand N. */
9482 imm_size (unsigned int n
)
9485 if (i
.types
[n
].bitfield
.imm64
)
9487 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9489 else if (i
.types
[n
].bitfield
.imm16
)
9495 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9500 for (n
= 0; n
< i
.operands
; n
++)
9502 if (operand_type_check (i
.types
[n
], disp
))
9504 if (i
.op
[n
].disps
->X_op
== O_constant
)
9506 int size
= disp_size (n
);
9507 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9509 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9511 p
= frag_more (size
);
9512 md_number_to_chars (p
, val
, size
);
9516 enum bfd_reloc_code_real reloc_type
;
9517 int size
= disp_size (n
);
9518 int sign
= i
.types
[n
].bitfield
.disp32s
;
9519 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9522 /* We can't have 8 bit displacement here. */
9523 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9525 /* The PC relative address is computed relative
9526 to the instruction boundary, so in case immediate
9527 fields follows, we need to adjust the value. */
9528 if (pcrel
&& i
.imm_operands
)
9533 for (n1
= 0; n1
< i
.operands
; n1
++)
9534 if (operand_type_check (i
.types
[n1
], imm
))
9536 /* Only one immediate is allowed for PC
9537 relative address. */
9538 gas_assert (sz
== 0);
9540 i
.op
[n
].disps
->X_add_number
-= sz
;
9542 /* We should find the immediate. */
9543 gas_assert (sz
!= 0);
9546 p
= frag_more (size
);
9547 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9549 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9550 && (((reloc_type
== BFD_RELOC_32
9551 || reloc_type
== BFD_RELOC_X86_64_32S
9552 || (reloc_type
== BFD_RELOC_64
9554 && (i
.op
[n
].disps
->X_op
== O_symbol
9555 || (i
.op
[n
].disps
->X_op
== O_add
9556 && ((symbol_get_value_expression
9557 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9559 || reloc_type
== BFD_RELOC_32_PCREL
))
9563 reloc_type
= BFD_RELOC_386_GOTPC
;
9564 i
.has_gotpc_tls_reloc
= TRUE
;
9565 i
.op
[n
].imms
->X_add_number
+=
9566 encoding_length (insn_start_frag
, insn_start_off
, p
);
9568 else if (reloc_type
== BFD_RELOC_64
)
9569 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9571 /* Don't do the adjustment for x86-64, as there
9572 the pcrel addressing is relative to the _next_
9573 insn, and that is taken care of in other code. */
9574 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9576 else if (align_branch_power
)
9580 case BFD_RELOC_386_TLS_GD
:
9581 case BFD_RELOC_386_TLS_LDM
:
9582 case BFD_RELOC_386_TLS_IE
:
9583 case BFD_RELOC_386_TLS_IE_32
:
9584 case BFD_RELOC_386_TLS_GOTIE
:
9585 case BFD_RELOC_386_TLS_GOTDESC
:
9586 case BFD_RELOC_386_TLS_DESC_CALL
:
9587 case BFD_RELOC_X86_64_TLSGD
:
9588 case BFD_RELOC_X86_64_TLSLD
:
9589 case BFD_RELOC_X86_64_GOTTPOFF
:
9590 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9591 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9592 i
.has_gotpc_tls_reloc
= TRUE
;
9597 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9598 size
, i
.op
[n
].disps
, pcrel
,
9600 /* Check for "call/jmp *mem", "mov mem, %reg",
9601 "test %reg, mem" and "binop mem, %reg" where binop
9602 is one of adc, add, and, cmp, or, sbb, sub, xor
9603 instructions without data prefix. Always generate
9604 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9605 if (i
.prefix
[DATA_PREFIX
] == 0
9606 && (generate_relax_relocations
9609 && i
.rm
.regmem
== 5))
9611 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9612 && !is_any_vex_encoding(&i
.tm
)
9613 && ((i
.operands
== 1
9614 && i
.tm
.base_opcode
== 0xff
9615 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9617 && (i
.tm
.base_opcode
== 0x8b
9618 || i
.tm
.base_opcode
== 0x85
9619 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9623 fixP
->fx_tcbit
= i
.rex
!= 0;
9625 && (i
.base_reg
->reg_num
== RegIP
))
9626 fixP
->fx_tcbit2
= 1;
9629 fixP
->fx_tcbit2
= 1;
9637 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9642 for (n
= 0; n
< i
.operands
; n
++)
9644 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9645 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9648 if (operand_type_check (i
.types
[n
], imm
))
9650 if (i
.op
[n
].imms
->X_op
== O_constant
)
9652 int size
= imm_size (n
);
9655 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9657 p
= frag_more (size
);
9658 md_number_to_chars (p
, val
, size
);
9662 /* Not absolute_section.
9663 Need a 32-bit fixup (don't support 8bit
9664 non-absolute imms). Try to support other
9666 enum bfd_reloc_code_real reloc_type
;
9667 int size
= imm_size (n
);
9670 if (i
.types
[n
].bitfield
.imm32s
9671 && (i
.suffix
== QWORD_MNEM_SUFFIX
9672 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9677 p
= frag_more (size
);
9678 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9680 /* This is tough to explain. We end up with this one if we
9681 * have operands that look like
9682 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9683 * obtain the absolute address of the GOT, and it is strongly
9684 * preferable from a performance point of view to avoid using
9685 * a runtime relocation for this. The actual sequence of
9686 * instructions often look something like:
9691 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9693 * The call and pop essentially return the absolute address
9694 * of the label .L66 and store it in %ebx. The linker itself
9695 * will ultimately change the first operand of the addl so
9696 * that %ebx points to the GOT, but to keep things simple, the
9697 * .o file must have this operand set so that it generates not
9698 * the absolute address of .L66, but the absolute address of
9699 * itself. This allows the linker itself simply treat a GOTPC
9700 * relocation as asking for a pcrel offset to the GOT to be
9701 * added in, and the addend of the relocation is stored in the
9702 * operand field for the instruction itself.
9704 * Our job here is to fix the operand so that it would add
9705 * the correct offset so that %ebx would point to itself. The
9706 * thing that is tricky is that .-.L66 will point to the
9707 * beginning of the instruction, so we need to further modify
9708 * the operand so that it will point to itself. There are
9709 * other cases where you have something like:
9711 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9713 * and here no correction would be required. Internally in
9714 * the assembler we treat operands of this form as not being
9715 * pcrel since the '.' is explicitly mentioned, and I wonder
9716 * whether it would simplify matters to do it this way. Who
9717 * knows. In earlier versions of the PIC patches, the
9718 * pcrel_adjust field was used to store the correction, but
9719 * since the expression is not pcrel, I felt it would be
9720 * confusing to do it this way. */
9722 if ((reloc_type
== BFD_RELOC_32
9723 || reloc_type
== BFD_RELOC_X86_64_32S
9724 || reloc_type
== BFD_RELOC_64
)
9726 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9727 && (i
.op
[n
].imms
->X_op
== O_symbol
9728 || (i
.op
[n
].imms
->X_op
== O_add
9729 && ((symbol_get_value_expression
9730 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9734 reloc_type
= BFD_RELOC_386_GOTPC
;
9736 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9738 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9739 i
.has_gotpc_tls_reloc
= TRUE
;
9740 i
.op
[n
].imms
->X_add_number
+=
9741 encoding_length (insn_start_frag
, insn_start_off
, p
);
9743 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9744 i
.op
[n
].imms
, 0, reloc_type
);
9750 /* x86_cons_fix_new is called via the expression parsing code when a
9751 reloc is needed. We use this hook to get the correct .got reloc. */
9752 static int cons_sign
= -1;
9755 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9756 expressionS
*exp
, bfd_reloc_code_real_type r
)
9758 r
= reloc (len
, 0, cons_sign
, r
);
9761 if (exp
->X_op
== O_secrel
)
9763 exp
->X_op
= O_symbol
;
9764 r
= BFD_RELOC_32_SECREL
;
9768 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9771 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9772 purpose of the `.dc.a' internal pseudo-op. */
9775 x86_address_bytes (void)
9777 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9779 return stdoutput
->arch_info
->bits_per_address
/ 8;
9782 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9784 # define lex_got(reloc, adjust, types) NULL
9786 /* Parse operands of the form
9787 <symbol>@GOTOFF+<nnn>
9788 and similar .plt or .got references.
9790 If we find one, set up the correct relocation in RELOC and copy the
9791 input string, minus the `@GOTOFF' into a malloc'd buffer for
9792 parsing by the calling routine. Return this buffer, and if ADJUST
9793 is non-null set it to the length of the string we removed from the
9794 input line. Otherwise return NULL. */
9796 lex_got (enum bfd_reloc_code_real
*rel
,
9798 i386_operand_type
*types
)
9800 /* Some of the relocations depend on the size of what field is to
9801 be relocated. But in our callers i386_immediate and i386_displacement
9802 we don't yet know the operand size (this will be set by insn
9803 matching). Hence we record the word32 relocation here,
9804 and adjust the reloc according to the real size in reloc(). */
9805 static const struct {
9808 const enum bfd_reloc_code_real rel
[2];
9809 const i386_operand_type types64
;
9811 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9812 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9814 OPERAND_TYPE_IMM32_64
},
9816 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9817 BFD_RELOC_X86_64_PLTOFF64
},
9818 OPERAND_TYPE_IMM64
},
9819 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9820 BFD_RELOC_X86_64_PLT32
},
9821 OPERAND_TYPE_IMM32_32S_DISP32
},
9822 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9823 BFD_RELOC_X86_64_GOTPLT64
},
9824 OPERAND_TYPE_IMM64_DISP64
},
9825 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9826 BFD_RELOC_X86_64_GOTOFF64
},
9827 OPERAND_TYPE_IMM64_DISP64
},
9828 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9829 BFD_RELOC_X86_64_GOTPCREL
},
9830 OPERAND_TYPE_IMM32_32S_DISP32
},
9831 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9832 BFD_RELOC_X86_64_TLSGD
},
9833 OPERAND_TYPE_IMM32_32S_DISP32
},
9834 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9835 _dummy_first_bfd_reloc_code_real
},
9836 OPERAND_TYPE_NONE
},
9837 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9838 BFD_RELOC_X86_64_TLSLD
},
9839 OPERAND_TYPE_IMM32_32S_DISP32
},
9840 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9841 BFD_RELOC_X86_64_GOTTPOFF
},
9842 OPERAND_TYPE_IMM32_32S_DISP32
},
9843 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9844 BFD_RELOC_X86_64_TPOFF32
},
9845 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9846 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9847 _dummy_first_bfd_reloc_code_real
},
9848 OPERAND_TYPE_NONE
},
9849 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9850 BFD_RELOC_X86_64_DTPOFF32
},
9851 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9852 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9853 _dummy_first_bfd_reloc_code_real
},
9854 OPERAND_TYPE_NONE
},
9855 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9856 _dummy_first_bfd_reloc_code_real
},
9857 OPERAND_TYPE_NONE
},
9858 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9859 BFD_RELOC_X86_64_GOT32
},
9860 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9861 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9862 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9863 OPERAND_TYPE_IMM32_32S_DISP32
},
9864 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9865 BFD_RELOC_X86_64_TLSDESC_CALL
},
9866 OPERAND_TYPE_IMM32_32S_DISP32
},
9871 #if defined (OBJ_MAYBE_ELF)
9876 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9877 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9880 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9882 int len
= gotrel
[j
].len
;
9883 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9885 if (gotrel
[j
].rel
[object_64bit
] != 0)
9888 char *tmpbuf
, *past_reloc
;
9890 *rel
= gotrel
[j
].rel
[object_64bit
];
9894 if (flag_code
!= CODE_64BIT
)
9896 types
->bitfield
.imm32
= 1;
9897 types
->bitfield
.disp32
= 1;
9900 *types
= gotrel
[j
].types64
;
9903 if (j
!= 0 && GOT_symbol
== NULL
)
9904 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9906 /* The length of the first part of our input line. */
9907 first
= cp
- input_line_pointer
;
9909 /* The second part goes from after the reloc token until
9910 (and including) an end_of_line char or comma. */
9911 past_reloc
= cp
+ 1 + len
;
9913 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9915 second
= cp
+ 1 - past_reloc
;
9917 /* Allocate and copy string. The trailing NUL shouldn't
9918 be necessary, but be safe. */
9919 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9920 memcpy (tmpbuf
, input_line_pointer
, first
);
9921 if (second
!= 0 && *past_reloc
!= ' ')
9922 /* Replace the relocation token with ' ', so that
9923 errors like foo@GOTOFF1 will be detected. */
9924 tmpbuf
[first
++] = ' ';
9926 /* Increment length by 1 if the relocation token is
9931 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9932 tmpbuf
[first
+ second
] = '\0';
9936 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9937 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9942 /* Might be a symbol version string. Don't as_bad here. */
9951 /* Parse operands of the form
9952 <symbol>@SECREL32+<nnn>
9954 If we find one, set up the correct relocation in RELOC and copy the
9955 input string, minus the `@SECREL32' into a malloc'd buffer for
9956 parsing by the calling routine. Return this buffer, and if ADJUST
9957 is non-null set it to the length of the string we removed from the
9958 input line. Otherwise return NULL.
9960 This function is copied from the ELF version above adjusted for PE targets. */
9963 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9964 int *adjust ATTRIBUTE_UNUSED
,
9965 i386_operand_type
*types
)
9971 const enum bfd_reloc_code_real rel
[2];
9972 const i386_operand_type types64
;
9976 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9977 BFD_RELOC_32_SECREL
},
9978 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9984 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9985 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9988 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9990 int len
= gotrel
[j
].len
;
9992 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9994 if (gotrel
[j
].rel
[object_64bit
] != 0)
9997 char *tmpbuf
, *past_reloc
;
9999 *rel
= gotrel
[j
].rel
[object_64bit
];
10005 if (flag_code
!= CODE_64BIT
)
10007 types
->bitfield
.imm32
= 1;
10008 types
->bitfield
.disp32
= 1;
10011 *types
= gotrel
[j
].types64
;
10014 /* The length of the first part of our input line. */
10015 first
= cp
- input_line_pointer
;
10017 /* The second part goes from after the reloc token until
10018 (and including) an end_of_line char or comma. */
10019 past_reloc
= cp
+ 1 + len
;
10021 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10023 second
= cp
+ 1 - past_reloc
;
10025 /* Allocate and copy string. The trailing NUL shouldn't
10026 be necessary, but be safe. */
10027 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10028 memcpy (tmpbuf
, input_line_pointer
, first
);
10029 if (second
!= 0 && *past_reloc
!= ' ')
10030 /* Replace the relocation token with ' ', so that
10031 errors like foo@SECLREL321 will be detected. */
10032 tmpbuf
[first
++] = ' ';
10033 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10034 tmpbuf
[first
+ second
] = '\0';
10038 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10039 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10044 /* Might be a symbol version string. Don't as_bad here. */
10050 bfd_reloc_code_real_type
10051 x86_cons (expressionS
*exp
, int size
)
10053 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10055 intel_syntax
= -intel_syntax
;
10058 if (size
== 4 || (object_64bit
&& size
== 8))
10060 /* Handle @GOTOFF and the like in an expression. */
10062 char *gotfree_input_line
;
10065 save
= input_line_pointer
;
10066 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10067 if (gotfree_input_line
)
10068 input_line_pointer
= gotfree_input_line
;
10072 if (gotfree_input_line
)
10074 /* expression () has merrily parsed up to the end of line,
10075 or a comma - in the wrong buffer. Transfer how far
10076 input_line_pointer has moved to the right buffer. */
10077 input_line_pointer
= (save
10078 + (input_line_pointer
- gotfree_input_line
)
10080 free (gotfree_input_line
);
10081 if (exp
->X_op
== O_constant
10082 || exp
->X_op
== O_absent
10083 || exp
->X_op
== O_illegal
10084 || exp
->X_op
== O_register
10085 || exp
->X_op
== O_big
)
10087 char c
= *input_line_pointer
;
10088 *input_line_pointer
= 0;
10089 as_bad (_("missing or invalid expression `%s'"), save
);
10090 *input_line_pointer
= c
;
10092 else if ((got_reloc
== BFD_RELOC_386_PLT32
10093 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10094 && exp
->X_op
!= O_symbol
)
10096 char c
= *input_line_pointer
;
10097 *input_line_pointer
= 0;
10098 as_bad (_("invalid PLT expression `%s'"), save
);
10099 *input_line_pointer
= c
;
10106 intel_syntax
= -intel_syntax
;
10109 i386_intel_simplify (exp
);
10115 signed_cons (int size
)
10117 if (flag_code
== CODE_64BIT
)
10125 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10132 if (exp
.X_op
== O_symbol
)
10133 exp
.X_op
= O_secrel
;
10135 emit_expr (&exp
, 4);
10137 while (*input_line_pointer
++ == ',');
10139 input_line_pointer
--;
10140 demand_empty_rest_of_line ();
10144 /* Handle Vector operations. */
10147 check_VecOperations (char *op_string
, char *op_end
)
10149 const reg_entry
*mask
;
10154 && (op_end
== NULL
|| op_string
< op_end
))
10157 if (*op_string
== '{')
10161 /* Check broadcasts. */
10162 if (strncmp (op_string
, "1to", 3) == 0)
10167 goto duplicated_vec_op
;
10170 if (*op_string
== '8')
10172 else if (*op_string
== '4')
10174 else if (*op_string
== '2')
10176 else if (*op_string
== '1'
10177 && *(op_string
+1) == '6')
10184 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10189 broadcast_op
.type
= bcst_type
;
10190 broadcast_op
.operand
= this_operand
;
10191 broadcast_op
.bytes
= 0;
10192 i
.broadcast
= &broadcast_op
;
10194 /* Check masking operation. */
10195 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10197 if (mask
== &bad_reg
)
10200 /* k0 can't be used for write mask. */
10201 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10203 as_bad (_("`%s%s' can't be used for write mask"),
10204 register_prefix
, mask
->reg_name
);
10210 mask_op
.mask
= mask
;
10211 mask_op
.zeroing
= 0;
10212 mask_op
.operand
= this_operand
;
10218 goto duplicated_vec_op
;
10220 i
.mask
->mask
= mask
;
10222 /* Only "{z}" is allowed here. No need to check
10223 zeroing mask explicitly. */
10224 if (i
.mask
->operand
!= this_operand
)
10226 as_bad (_("invalid write mask `%s'"), saved
);
10231 op_string
= end_op
;
10233 /* Check zeroing-flag for masking operation. */
10234 else if (*op_string
== 'z')
10238 mask_op
.mask
= NULL
;
10239 mask_op
.zeroing
= 1;
10240 mask_op
.operand
= this_operand
;
10245 if (i
.mask
->zeroing
)
10248 as_bad (_("duplicated `%s'"), saved
);
10252 i
.mask
->zeroing
= 1;
10254 /* Only "{%k}" is allowed here. No need to check mask
10255 register explicitly. */
10256 if (i
.mask
->operand
!= this_operand
)
10258 as_bad (_("invalid zeroing-masking `%s'"),
10267 goto unknown_vec_op
;
10269 if (*op_string
!= '}')
10271 as_bad (_("missing `}' in `%s'"), saved
);
10276 /* Strip whitespace since the addition of pseudo prefixes
10277 changed how the scrubber treats '{'. */
10278 if (is_space_char (*op_string
))
10284 /* We don't know this one. */
10285 as_bad (_("unknown vector operation: `%s'"), saved
);
10289 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10291 as_bad (_("zeroing-masking only allowed with write mask"));
10299 i386_immediate (char *imm_start
)
10301 char *save_input_line_pointer
;
10302 char *gotfree_input_line
;
10305 i386_operand_type types
;
10307 operand_type_set (&types
, ~0);
10309 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10311 as_bad (_("at most %d immediate operands are allowed"),
10312 MAX_IMMEDIATE_OPERANDS
);
10316 exp
= &im_expressions
[i
.imm_operands
++];
10317 i
.op
[this_operand
].imms
= exp
;
10319 if (is_space_char (*imm_start
))
10322 save_input_line_pointer
= input_line_pointer
;
10323 input_line_pointer
= imm_start
;
10325 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10326 if (gotfree_input_line
)
10327 input_line_pointer
= gotfree_input_line
;
10329 exp_seg
= expression (exp
);
10331 SKIP_WHITESPACE ();
10333 /* Handle vector operations. */
10334 if (*input_line_pointer
== '{')
10336 input_line_pointer
= check_VecOperations (input_line_pointer
,
10338 if (input_line_pointer
== NULL
)
10342 if (*input_line_pointer
)
10343 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10345 input_line_pointer
= save_input_line_pointer
;
10346 if (gotfree_input_line
)
10348 free (gotfree_input_line
);
10350 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10351 exp
->X_op
= O_illegal
;
10354 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10358 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10359 i386_operand_type types
, const char *imm_start
)
10361 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10364 as_bad (_("missing or invalid immediate expression `%s'"),
10368 else if (exp
->X_op
== O_constant
)
10370 /* Size it properly later. */
10371 i
.types
[this_operand
].bitfield
.imm64
= 1;
10372 /* If not 64bit, sign extend val. */
10373 if (flag_code
!= CODE_64BIT
10374 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10376 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10378 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10379 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10380 && exp_seg
!= absolute_section
10381 && exp_seg
!= text_section
10382 && exp_seg
!= data_section
10383 && exp_seg
!= bss_section
10384 && exp_seg
!= undefined_section
10385 && !bfd_is_com_section (exp_seg
))
10387 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10391 else if (!intel_syntax
&& exp_seg
== reg_section
)
10394 as_bad (_("illegal immediate register operand %s"), imm_start
);
10399 /* This is an address. The size of the address will be
10400 determined later, depending on destination register,
10401 suffix, or the default for the section. */
10402 i
.types
[this_operand
].bitfield
.imm8
= 1;
10403 i
.types
[this_operand
].bitfield
.imm16
= 1;
10404 i
.types
[this_operand
].bitfield
.imm32
= 1;
10405 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10406 i
.types
[this_operand
].bitfield
.imm64
= 1;
10407 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10415 i386_scale (char *scale
)
10418 char *save
= input_line_pointer
;
10420 input_line_pointer
= scale
;
10421 val
= get_absolute_expression ();
10426 i
.log2_scale_factor
= 0;
10429 i
.log2_scale_factor
= 1;
10432 i
.log2_scale_factor
= 2;
10435 i
.log2_scale_factor
= 3;
10439 char sep
= *input_line_pointer
;
10441 *input_line_pointer
= '\0';
10442 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10444 *input_line_pointer
= sep
;
10445 input_line_pointer
= save
;
10449 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10451 as_warn (_("scale factor of %d without an index register"),
10452 1 << i
.log2_scale_factor
);
10453 i
.log2_scale_factor
= 0;
10455 scale
= input_line_pointer
;
10456 input_line_pointer
= save
;
10461 i386_displacement (char *disp_start
, char *disp_end
)
10465 char *save_input_line_pointer
;
10466 char *gotfree_input_line
;
10468 i386_operand_type bigdisp
, types
= anydisp
;
10471 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10473 as_bad (_("at most %d displacement operands are allowed"),
10474 MAX_MEMORY_OPERANDS
);
10478 operand_type_set (&bigdisp
, 0);
10480 || i
.types
[this_operand
].bitfield
.baseindex
10481 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10482 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10484 i386_addressing_mode ();
10485 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10486 if (flag_code
== CODE_64BIT
)
10490 bigdisp
.bitfield
.disp32s
= 1;
10491 bigdisp
.bitfield
.disp64
= 1;
10494 bigdisp
.bitfield
.disp32
= 1;
10496 else if ((flag_code
== CODE_16BIT
) ^ override
)
10497 bigdisp
.bitfield
.disp16
= 1;
10499 bigdisp
.bitfield
.disp32
= 1;
10503 /* For PC-relative branches, the width of the displacement may be
10504 dependent upon data size, but is never dependent upon address size.
10505 Also make sure to not unintentionally match against a non-PC-relative
10506 branch template. */
10507 static templates aux_templates
;
10508 const insn_template
*t
= current_templates
->start
;
10509 bfd_boolean has_intel64
= FALSE
;
10511 aux_templates
.start
= t
;
10512 while (++t
< current_templates
->end
)
10514 if (t
->opcode_modifier
.jump
10515 != current_templates
->start
->opcode_modifier
.jump
)
10517 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10518 has_intel64
= TRUE
;
10520 if (t
< current_templates
->end
)
10522 aux_templates
.end
= t
;
10523 current_templates
= &aux_templates
;
10526 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10527 if (flag_code
== CODE_64BIT
)
10529 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10530 && (!intel64
|| !has_intel64
))
10531 bigdisp
.bitfield
.disp16
= 1;
10533 bigdisp
.bitfield
.disp32s
= 1;
10538 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10540 : LONG_MNEM_SUFFIX
));
10541 bigdisp
.bitfield
.disp32
= 1;
10542 if ((flag_code
== CODE_16BIT
) ^ override
)
10544 bigdisp
.bitfield
.disp32
= 0;
10545 bigdisp
.bitfield
.disp16
= 1;
10549 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10552 exp
= &disp_expressions
[i
.disp_operands
];
10553 i
.op
[this_operand
].disps
= exp
;
10555 save_input_line_pointer
= input_line_pointer
;
10556 input_line_pointer
= disp_start
;
10557 END_STRING_AND_SAVE (disp_end
);
10559 #ifndef GCC_ASM_O_HACK
10560 #define GCC_ASM_O_HACK 0
10563 END_STRING_AND_SAVE (disp_end
+ 1);
10564 if (i
.types
[this_operand
].bitfield
.baseIndex
10565 && displacement_string_end
[-1] == '+')
10567 /* This hack is to avoid a warning when using the "o"
10568 constraint within gcc asm statements.
10571 #define _set_tssldt_desc(n,addr,limit,type) \
10572 __asm__ __volatile__ ( \
10573 "movw %w2,%0\n\t" \
10574 "movw %w1,2+%0\n\t" \
10575 "rorl $16,%1\n\t" \
10576 "movb %b1,4+%0\n\t" \
10577 "movb %4,5+%0\n\t" \
10578 "movb $0,6+%0\n\t" \
10579 "movb %h1,7+%0\n\t" \
10581 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10583 This works great except that the output assembler ends
10584 up looking a bit weird if it turns out that there is
10585 no offset. You end up producing code that looks like:
10598 So here we provide the missing zero. */
10600 *displacement_string_end
= '0';
10603 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10604 if (gotfree_input_line
)
10605 input_line_pointer
= gotfree_input_line
;
10607 exp_seg
= expression (exp
);
10609 SKIP_WHITESPACE ();
10610 if (*input_line_pointer
)
10611 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10613 RESTORE_END_STRING (disp_end
+ 1);
10615 input_line_pointer
= save_input_line_pointer
;
10616 if (gotfree_input_line
)
10618 free (gotfree_input_line
);
10620 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10621 exp
->X_op
= O_illegal
;
10624 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10626 RESTORE_END_STRING (disp_end
);
10632 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10633 i386_operand_type types
, const char *disp_start
)
10635 i386_operand_type bigdisp
;
10638 /* We do this to make sure that the section symbol is in
10639 the symbol table. We will ultimately change the relocation
10640 to be relative to the beginning of the section. */
10641 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10642 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10643 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10645 if (exp
->X_op
!= O_symbol
)
10648 if (S_IS_LOCAL (exp
->X_add_symbol
)
10649 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10650 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10651 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10652 exp
->X_op
= O_subtract
;
10653 exp
->X_op_symbol
= GOT_symbol
;
10654 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10655 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10656 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10657 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10659 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10662 else if (exp
->X_op
== O_absent
10663 || exp
->X_op
== O_illegal
10664 || exp
->X_op
== O_big
)
10667 as_bad (_("missing or invalid displacement expression `%s'"),
10672 else if (flag_code
== CODE_64BIT
10673 && !i
.prefix
[ADDR_PREFIX
]
10674 && exp
->X_op
== O_constant
)
10676 /* Since displacement is signed extended to 64bit, don't allow
10677 disp32 and turn off disp32s if they are out of range. */
10678 i
.types
[this_operand
].bitfield
.disp32
= 0;
10679 if (!fits_in_signed_long (exp
->X_add_number
))
10681 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10682 if (i
.types
[this_operand
].bitfield
.baseindex
)
10684 as_bad (_("0x%lx out range of signed 32bit displacement"),
10685 (long) exp
->X_add_number
);
10691 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10692 else if (exp
->X_op
!= O_constant
10693 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10694 && exp_seg
!= absolute_section
10695 && exp_seg
!= text_section
10696 && exp_seg
!= data_section
10697 && exp_seg
!= bss_section
10698 && exp_seg
!= undefined_section
10699 && !bfd_is_com_section (exp_seg
))
10701 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10706 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10707 /* Constants get taken care of by optimize_disp(). */
10708 && exp
->X_op
!= O_constant
)
10709 i
.types
[this_operand
].bitfield
.disp8
= 1;
10711 /* Check if this is a displacement only operand. */
10712 bigdisp
= i
.types
[this_operand
];
10713 bigdisp
.bitfield
.disp8
= 0;
10714 bigdisp
.bitfield
.disp16
= 0;
10715 bigdisp
.bitfield
.disp32
= 0;
10716 bigdisp
.bitfield
.disp32s
= 0;
10717 bigdisp
.bitfield
.disp64
= 0;
10718 if (operand_type_all_zero (&bigdisp
))
10719 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10725 /* Return the active addressing mode, taking address override and
10726 registers forming the address into consideration. Update the
10727 address override prefix if necessary. */
10729 static enum flag_code
10730 i386_addressing_mode (void)
10732 enum flag_code addr_mode
;
10734 if (i
.prefix
[ADDR_PREFIX
])
10735 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10736 else if (flag_code
== CODE_16BIT
10737 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10738 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10739 from md_assemble() by "is not a valid base/index expression"
10740 when there is a base and/or index. */
10741 && !i
.types
[this_operand
].bitfield
.baseindex
)
10743 /* MPX insn memory operands with neither base nor index must be forced
10744 to use 32-bit addressing in 16-bit mode. */
10745 addr_mode
= CODE_32BIT
;
10746 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10748 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10749 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10753 addr_mode
= flag_code
;
10755 #if INFER_ADDR_PREFIX
10756 if (i
.mem_operands
== 0)
10758 /* Infer address prefix from the first memory operand. */
10759 const reg_entry
*addr_reg
= i
.base_reg
;
10761 if (addr_reg
== NULL
)
10762 addr_reg
= i
.index_reg
;
10766 if (addr_reg
->reg_type
.bitfield
.dword
)
10767 addr_mode
= CODE_32BIT
;
10768 else if (flag_code
!= CODE_64BIT
10769 && addr_reg
->reg_type
.bitfield
.word
)
10770 addr_mode
= CODE_16BIT
;
10772 if (addr_mode
!= flag_code
)
10774 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10776 /* Change the size of any displacement too. At most one
10777 of Disp16 or Disp32 is set.
10778 FIXME. There doesn't seem to be any real need for
10779 separate Disp16 and Disp32 flags. The same goes for
10780 Imm16 and Imm32. Removing them would probably clean
10781 up the code quite a lot. */
10782 if (flag_code
!= CODE_64BIT
10783 && (i
.types
[this_operand
].bitfield
.disp16
10784 || i
.types
[this_operand
].bitfield
.disp32
))
10785 i
.types
[this_operand
]
10786 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10796 /* Make sure the memory operand we've been dealt is valid.
10797 Return 1 on success, 0 on a failure. */
10800 i386_index_check (const char *operand_string
)
10802 const char *kind
= "base/index";
10803 enum flag_code addr_mode
= i386_addressing_mode ();
10805 if (current_templates
->start
->opcode_modifier
.isstring
10806 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10807 && (current_templates
->end
[-1].opcode_modifier
.isstring
10808 || i
.mem_operands
))
10810 /* Memory operands of string insns are special in that they only allow
10811 a single register (rDI, rSI, or rBX) as their memory address. */
10812 const reg_entry
*expected_reg
;
10813 static const char *di_si
[][2] =
10819 static const char *bx
[] = { "ebx", "bx", "rbx" };
10821 kind
= "string address";
10823 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10825 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10826 - IS_STRING_ES_OP0
;
10829 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10830 || ((!i
.mem_operands
!= !intel_syntax
)
10831 && current_templates
->end
[-1].operand_types
[1]
10832 .bitfield
.baseindex
))
10834 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10837 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10839 if (i
.base_reg
!= expected_reg
10841 || operand_type_check (i
.types
[this_operand
], disp
))
10843 /* The second memory operand must have the same size as
10847 && !((addr_mode
== CODE_64BIT
10848 && i
.base_reg
->reg_type
.bitfield
.qword
)
10849 || (addr_mode
== CODE_32BIT
10850 ? i
.base_reg
->reg_type
.bitfield
.dword
10851 : i
.base_reg
->reg_type
.bitfield
.word
)))
10854 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10856 intel_syntax
? '[' : '(',
10858 expected_reg
->reg_name
,
10859 intel_syntax
? ']' : ')');
10866 as_bad (_("`%s' is not a valid %s expression"),
10867 operand_string
, kind
);
10872 if (addr_mode
!= CODE_16BIT
)
10874 /* 32-bit/64-bit checks. */
10876 && ((addr_mode
== CODE_64BIT
10877 ? !i
.base_reg
->reg_type
.bitfield
.qword
10878 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10879 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10880 || i
.base_reg
->reg_num
== RegIZ
))
10882 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10883 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10884 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10885 && ((addr_mode
== CODE_64BIT
10886 ? !i
.index_reg
->reg_type
.bitfield
.qword
10887 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10888 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10891 /* bndmk, bndldx, and bndstx have special restrictions. */
10892 if (current_templates
->start
->base_opcode
== 0xf30f1b
10893 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10895 /* They cannot use RIP-relative addressing. */
10896 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10898 as_bad (_("`%s' cannot be used here"), operand_string
);
10902 /* bndldx and bndstx ignore their scale factor. */
10903 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10904 && i
.log2_scale_factor
)
10905 as_warn (_("register scaling is being ignored here"));
10910 /* 16-bit checks. */
10912 && (!i
.base_reg
->reg_type
.bitfield
.word
10913 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10915 && (!i
.index_reg
->reg_type
.bitfield
.word
10916 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10918 && i
.base_reg
->reg_num
< 6
10919 && i
.index_reg
->reg_num
>= 6
10920 && i
.log2_scale_factor
== 0))))
10927 /* Handle vector immediates. */
10930 RC_SAE_immediate (const char *imm_start
)
10932 unsigned int match_found
, j
;
10933 const char *pstr
= imm_start
;
10941 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10943 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10947 rc_op
.type
= RC_NamesTable
[j
].type
;
10948 rc_op
.operand
= this_operand
;
10949 i
.rounding
= &rc_op
;
10953 as_bad (_("duplicated `%s'"), imm_start
);
10956 pstr
+= RC_NamesTable
[j
].len
;
10964 if (*pstr
++ != '}')
10966 as_bad (_("Missing '}': '%s'"), imm_start
);
10969 /* RC/SAE immediate string should contain nothing more. */;
10972 as_bad (_("Junk after '}': '%s'"), imm_start
);
10976 exp
= &im_expressions
[i
.imm_operands
++];
10977 i
.op
[this_operand
].imms
= exp
;
10979 exp
->X_op
= O_constant
;
10980 exp
->X_add_number
= 0;
10981 exp
->X_add_symbol
= (symbolS
*) 0;
10982 exp
->X_op_symbol
= (symbolS
*) 0;
10984 i
.types
[this_operand
].bitfield
.imm8
= 1;
10988 /* Only string instructions can have a second memory operand, so
10989 reduce current_templates to just those if it contains any. */
10991 maybe_adjust_templates (void)
10993 const insn_template
*t
;
10995 gas_assert (i
.mem_operands
== 1);
10997 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10998 if (t
->opcode_modifier
.isstring
)
11001 if (t
< current_templates
->end
)
11003 static templates aux_templates
;
11004 bfd_boolean recheck
;
11006 aux_templates
.start
= t
;
11007 for (; t
< current_templates
->end
; ++t
)
11008 if (!t
->opcode_modifier
.isstring
)
11010 aux_templates
.end
= t
;
11012 /* Determine whether to re-check the first memory operand. */
11013 recheck
= (aux_templates
.start
!= current_templates
->start
11014 || t
!= current_templates
->end
);
11016 current_templates
= &aux_templates
;
11020 i
.mem_operands
= 0;
11021 if (i
.memop1_string
!= NULL
11022 && i386_index_check (i
.memop1_string
) == 0)
11024 i
.mem_operands
= 1;
11031 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11035 i386_att_operand (char *operand_string
)
11037 const reg_entry
*r
;
11039 char *op_string
= operand_string
;
11041 if (is_space_char (*op_string
))
11044 /* We check for an absolute prefix (differentiating,
11045 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11046 if (*op_string
== ABSOLUTE_PREFIX
)
11049 if (is_space_char (*op_string
))
11051 i
.jumpabsolute
= TRUE
;
11054 /* Check if operand is a register. */
11055 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11057 i386_operand_type temp
;
11062 /* Check for a segment override by searching for ':' after a
11063 segment register. */
11064 op_string
= end_op
;
11065 if (is_space_char (*op_string
))
11067 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11069 switch (r
->reg_num
)
11072 i
.seg
[i
.mem_operands
] = &es
;
11075 i
.seg
[i
.mem_operands
] = &cs
;
11078 i
.seg
[i
.mem_operands
] = &ss
;
11081 i
.seg
[i
.mem_operands
] = &ds
;
11084 i
.seg
[i
.mem_operands
] = &fs
;
11087 i
.seg
[i
.mem_operands
] = &gs
;
11091 /* Skip the ':' and whitespace. */
11093 if (is_space_char (*op_string
))
11096 if (!is_digit_char (*op_string
)
11097 && !is_identifier_char (*op_string
)
11098 && *op_string
!= '('
11099 && *op_string
!= ABSOLUTE_PREFIX
)
11101 as_bad (_("bad memory operand `%s'"), op_string
);
11104 /* Handle case of %es:*foo. */
11105 if (*op_string
== ABSOLUTE_PREFIX
)
11108 if (is_space_char (*op_string
))
11110 i
.jumpabsolute
= TRUE
;
11112 goto do_memory_reference
;
11115 /* Handle vector operations. */
11116 if (*op_string
== '{')
11118 op_string
= check_VecOperations (op_string
, NULL
);
11119 if (op_string
== NULL
)
11125 as_bad (_("junk `%s' after register"), op_string
);
11128 temp
= r
->reg_type
;
11129 temp
.bitfield
.baseindex
= 0;
11130 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11132 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11133 i
.op
[this_operand
].regs
= r
;
11136 else if (*op_string
== REGISTER_PREFIX
)
11138 as_bad (_("bad register name `%s'"), op_string
);
11141 else if (*op_string
== IMMEDIATE_PREFIX
)
11144 if (i
.jumpabsolute
)
11146 as_bad (_("immediate operand illegal with absolute jump"));
11149 if (!i386_immediate (op_string
))
11152 else if (RC_SAE_immediate (operand_string
))
11154 /* If it is a RC or SAE immediate, do nothing. */
11157 else if (is_digit_char (*op_string
)
11158 || is_identifier_char (*op_string
)
11159 || *op_string
== '"'
11160 || *op_string
== '(')
11162 /* This is a memory reference of some sort. */
11165 /* Start and end of displacement string expression (if found). */
11166 char *displacement_string_start
;
11167 char *displacement_string_end
;
11170 do_memory_reference
:
11171 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11173 if ((i
.mem_operands
== 1
11174 && !current_templates
->start
->opcode_modifier
.isstring
)
11175 || i
.mem_operands
== 2)
11177 as_bad (_("too many memory references for `%s'"),
11178 current_templates
->start
->name
);
11182 /* Check for base index form. We detect the base index form by
11183 looking for an ')' at the end of the operand, searching
11184 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11186 base_string
= op_string
+ strlen (op_string
);
11188 /* Handle vector operations. */
11189 vop_start
= strchr (op_string
, '{');
11190 if (vop_start
&& vop_start
< base_string
)
11192 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11194 base_string
= vop_start
;
11198 if (is_space_char (*base_string
))
11201 /* If we only have a displacement, set-up for it to be parsed later. */
11202 displacement_string_start
= op_string
;
11203 displacement_string_end
= base_string
+ 1;
11205 if (*base_string
== ')')
11208 unsigned int parens_balanced
= 1;
11209 /* We've already checked that the number of left & right ()'s are
11210 equal, so this loop will not be infinite. */
11214 if (*base_string
== ')')
11216 if (*base_string
== '(')
11219 while (parens_balanced
);
11221 temp_string
= base_string
;
11223 /* Skip past '(' and whitespace. */
11225 if (is_space_char (*base_string
))
11228 if (*base_string
== ','
11229 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11232 displacement_string_end
= temp_string
;
11234 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11238 if (i
.base_reg
== &bad_reg
)
11240 base_string
= end_op
;
11241 if (is_space_char (*base_string
))
11245 /* There may be an index reg or scale factor here. */
11246 if (*base_string
== ',')
11249 if (is_space_char (*base_string
))
11252 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11255 if (i
.index_reg
== &bad_reg
)
11257 base_string
= end_op
;
11258 if (is_space_char (*base_string
))
11260 if (*base_string
== ',')
11263 if (is_space_char (*base_string
))
11266 else if (*base_string
!= ')')
11268 as_bad (_("expecting `,' or `)' "
11269 "after index register in `%s'"),
11274 else if (*base_string
== REGISTER_PREFIX
)
11276 end_op
= strchr (base_string
, ',');
11279 as_bad (_("bad register name `%s'"), base_string
);
11283 /* Check for scale factor. */
11284 if (*base_string
!= ')')
11286 char *end_scale
= i386_scale (base_string
);
11291 base_string
= end_scale
;
11292 if (is_space_char (*base_string
))
11294 if (*base_string
!= ')')
11296 as_bad (_("expecting `)' "
11297 "after scale factor in `%s'"),
11302 else if (!i
.index_reg
)
11304 as_bad (_("expecting index register or scale factor "
11305 "after `,'; got '%c'"),
11310 else if (*base_string
!= ')')
11312 as_bad (_("expecting `,' or `)' "
11313 "after base register in `%s'"),
11318 else if (*base_string
== REGISTER_PREFIX
)
11320 end_op
= strchr (base_string
, ',');
11323 as_bad (_("bad register name `%s'"), base_string
);
11328 /* If there's an expression beginning the operand, parse it,
11329 assuming displacement_string_start and
11330 displacement_string_end are meaningful. */
11331 if (displacement_string_start
!= displacement_string_end
)
11333 if (!i386_displacement (displacement_string_start
,
11334 displacement_string_end
))
11338 /* Special case for (%dx) while doing input/output op. */
11340 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11341 && i
.base_reg
->reg_type
.bitfield
.word
11342 && i
.index_reg
== 0
11343 && i
.log2_scale_factor
== 0
11344 && i
.seg
[i
.mem_operands
] == 0
11345 && !operand_type_check (i
.types
[this_operand
], disp
))
11347 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11351 if (i386_index_check (operand_string
) == 0)
11353 i
.flags
[this_operand
] |= Operand_Mem
;
11354 if (i
.mem_operands
== 0)
11355 i
.memop1_string
= xstrdup (operand_string
);
11360 /* It's not a memory operand; argh! */
11361 as_bad (_("invalid char %s beginning operand %d `%s'"),
11362 output_invalid (*op_string
),
11367 return 1; /* Normal return. */
11370 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11371 that an rs_machine_dependent frag may reach. */
11374 i386_frag_max_var (fragS
*frag
)
11376 /* The only relaxable frags are for jumps.
11377 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11378 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11379 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11382 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11384 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11386 /* STT_GNU_IFUNC symbol must go through PLT. */
11387 if ((symbol_get_bfdsym (fr_symbol
)->flags
11388 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11391 if (!S_IS_EXTERNAL (fr_symbol
))
11392 /* Symbol may be weak or local. */
11393 return !S_IS_WEAK (fr_symbol
);
11395 /* Global symbols with non-default visibility can't be preempted. */
11396 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11399 if (fr_var
!= NO_RELOC
)
11400 switch ((enum bfd_reloc_code_real
) fr_var
)
11402 case BFD_RELOC_386_PLT32
:
11403 case BFD_RELOC_X86_64_PLT32
:
11404 /* Symbol with PLT relocation may be preempted. */
11410 /* Global symbols with default visibility in a shared library may be
11411 preempted by another definition. */
11416 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11417 Note also work for Skylake and Cascadelake.
11418 ---------------------------------------------------------------------
11419 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11420 | ------ | ----------- | ------- | -------- |
11422 | Jno | N | N | Y |
11423 | Jc/Jb | Y | N | Y |
11424 | Jae/Jnb | Y | N | Y |
11425 | Je/Jz | Y | Y | Y |
11426 | Jne/Jnz | Y | Y | Y |
11427 | Jna/Jbe | Y | N | Y |
11428 | Ja/Jnbe | Y | N | Y |
11430 | Jns | N | N | Y |
11431 | Jp/Jpe | N | N | Y |
11432 | Jnp/Jpo | N | N | Y |
11433 | Jl/Jnge | Y | Y | Y |
11434 | Jge/Jnl | Y | Y | Y |
11435 | Jle/Jng | Y | Y | Y |
11436 | Jg/Jnle | Y | Y | Y |
11437 --------------------------------------------------------------------- */
11439 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11441 if (mf_cmp
== mf_cmp_alu_cmp
)
11442 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11443 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11444 if (mf_cmp
== mf_cmp_incdec
)
11445 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11446 || mf_jcc
== mf_jcc_jle
);
11447 if (mf_cmp
== mf_cmp_test_and
)
11452 /* Return the next non-empty frag. */
11455 i386_next_non_empty_frag (fragS
*fragP
)
11457 /* There may be a frag with a ".fill 0" when there is no room in
11458 the current frag for frag_grow in output_insn. */
11459 for (fragP
= fragP
->fr_next
;
11461 && fragP
->fr_type
== rs_fill
11462 && fragP
->fr_fix
== 0);
11463 fragP
= fragP
->fr_next
)
11468 /* Return the next jcc frag after BRANCH_PADDING. */
11471 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11473 fragS
*branch_fragP
;
11477 if (pad_fragP
->fr_type
== rs_machine_dependent
11478 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11479 == BRANCH_PADDING
))
11481 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11482 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11484 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11485 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11486 pad_fragP
->tc_frag_data
.mf_type
))
11487 return branch_fragP
;
11493 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11496 i386_classify_machine_dependent_frag (fragS
*fragP
)
11500 fragS
*branch_fragP
;
11502 unsigned int max_prefix_length
;
11504 if (fragP
->tc_frag_data
.classified
)
11507 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11508 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11509 for (next_fragP
= fragP
;
11510 next_fragP
!= NULL
;
11511 next_fragP
= next_fragP
->fr_next
)
11513 next_fragP
->tc_frag_data
.classified
= 1;
11514 if (next_fragP
->fr_type
== rs_machine_dependent
)
11515 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11517 case BRANCH_PADDING
:
11518 /* The BRANCH_PADDING frag must be followed by a branch
11520 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11521 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11523 case FUSED_JCC_PADDING
:
11524 /* Check if this is a fused jcc:
11526 CMP like instruction
11530 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11531 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11532 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11535 /* The BRANCH_PADDING frag is merged with the
11536 FUSED_JCC_PADDING frag. */
11537 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11538 /* CMP like instruction size. */
11539 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11540 frag_wane (pad_fragP
);
11541 /* Skip to branch_fragP. */
11542 next_fragP
= branch_fragP
;
11544 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11546 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11548 next_fragP
->fr_subtype
11549 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11550 next_fragP
->tc_frag_data
.max_bytes
11551 = next_fragP
->tc_frag_data
.max_prefix_length
;
11552 /* This will be updated in the BRANCH_PREFIX scan. */
11553 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11556 frag_wane (next_fragP
);
11561 /* Stop if there is no BRANCH_PREFIX. */
11562 if (!align_branch_prefix_size
)
11565 /* Scan for BRANCH_PREFIX. */
11566 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11568 if (fragP
->fr_type
!= rs_machine_dependent
11569 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11573 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11574 COND_JUMP_PREFIX. */
11575 max_prefix_length
= 0;
11576 for (next_fragP
= fragP
;
11577 next_fragP
!= NULL
;
11578 next_fragP
= next_fragP
->fr_next
)
11580 if (next_fragP
->fr_type
== rs_fill
)
11581 /* Skip rs_fill frags. */
11583 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11584 /* Stop for all other frags. */
11587 /* rs_machine_dependent frags. */
11588 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11591 /* Count BRANCH_PREFIX frags. */
11592 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11594 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11595 frag_wane (next_fragP
);
11599 += next_fragP
->tc_frag_data
.max_bytes
;
11601 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11603 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11604 == FUSED_JCC_PADDING
))
11606 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11607 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11611 /* Stop for other rs_machine_dependent frags. */
11615 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11617 /* Skip to the next frag. */
11618 fragP
= next_fragP
;
11622 /* Compute padding size for
11625 CMP like instruction
11627 COND_JUMP/UNCOND_JUMP
11632 COND_JUMP/UNCOND_JUMP
11636 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11638 unsigned int offset
, size
, padding_size
;
11639 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11641 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11643 address
= fragP
->fr_address
;
11644 address
+= fragP
->fr_fix
;
11646 /* CMP like instrunction size. */
11647 size
= fragP
->tc_frag_data
.cmp_size
;
11649 /* The base size of the branch frag. */
11650 size
+= branch_fragP
->fr_fix
;
11652 /* Add opcode and displacement bytes for the rs_machine_dependent
11654 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11655 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11657 /* Check if branch is within boundary and doesn't end at the last
11659 offset
= address
& ((1U << align_branch_power
) - 1);
11660 if ((offset
+ size
) >= (1U << align_branch_power
))
11661 /* Padding needed to avoid crossing boundary. */
11662 padding_size
= (1U << align_branch_power
) - offset
;
11664 /* No padding needed. */
11667 /* The return value may be saved in tc_frag_data.length which is
11669 if (!fits_in_unsigned_byte (padding_size
))
11672 return padding_size
;
11675 /* i386_generic_table_relax_frag()
11677 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11678 grow/shrink padding to align branch frags. Hand others to
11682 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11684 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11685 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11687 long padding_size
= i386_branch_padding_size (fragP
, 0);
11688 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11690 /* When the BRANCH_PREFIX frag is used, the computed address
11691 must match the actual address and there should be no padding. */
11692 if (fragP
->tc_frag_data
.padding_address
11693 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11697 /* Update the padding size. */
11699 fragP
->tc_frag_data
.length
= padding_size
;
11703 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11705 fragS
*padding_fragP
, *next_fragP
;
11706 long padding_size
, left_size
, last_size
;
11708 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11709 if (!padding_fragP
)
11710 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11711 return (fragP
->tc_frag_data
.length
11712 - fragP
->tc_frag_data
.last_length
);
11714 /* Compute the relative address of the padding frag in the very
11715 first time where the BRANCH_PREFIX frag sizes are zero. */
11716 if (!fragP
->tc_frag_data
.padding_address
)
11717 fragP
->tc_frag_data
.padding_address
11718 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11720 /* First update the last length from the previous interation. */
11721 left_size
= fragP
->tc_frag_data
.prefix_length
;
11722 for (next_fragP
= fragP
;
11723 next_fragP
!= padding_fragP
;
11724 next_fragP
= next_fragP
->fr_next
)
11725 if (next_fragP
->fr_type
== rs_machine_dependent
11726 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11731 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11735 if (max
> left_size
)
11740 next_fragP
->tc_frag_data
.last_length
= size
;
11744 next_fragP
->tc_frag_data
.last_length
= 0;
11747 /* Check the padding size for the padding frag. */
11748 padding_size
= i386_branch_padding_size
11749 (padding_fragP
, (fragP
->fr_address
11750 + fragP
->tc_frag_data
.padding_address
));
11752 last_size
= fragP
->tc_frag_data
.prefix_length
;
11753 /* Check if there is change from the last interation. */
11754 if (padding_size
== last_size
)
11756 /* Update the expected address of the padding frag. */
11757 padding_fragP
->tc_frag_data
.padding_address
11758 = (fragP
->fr_address
+ padding_size
11759 + fragP
->tc_frag_data
.padding_address
);
11763 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11765 /* No padding if there is no sufficient room. Clear the
11766 expected address of the padding frag. */
11767 padding_fragP
->tc_frag_data
.padding_address
= 0;
11771 /* Store the expected address of the padding frag. */
11772 padding_fragP
->tc_frag_data
.padding_address
11773 = (fragP
->fr_address
+ padding_size
11774 + fragP
->tc_frag_data
.padding_address
);
11776 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11778 /* Update the length for the current interation. */
11779 left_size
= padding_size
;
11780 for (next_fragP
= fragP
;
11781 next_fragP
!= padding_fragP
;
11782 next_fragP
= next_fragP
->fr_next
)
11783 if (next_fragP
->fr_type
== rs_machine_dependent
11784 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11789 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11793 if (max
> left_size
)
11798 next_fragP
->tc_frag_data
.length
= size
;
11802 next_fragP
->tc_frag_data
.length
= 0;
11805 return (fragP
->tc_frag_data
.length
11806 - fragP
->tc_frag_data
.last_length
);
11808 return relax_frag (segment
, fragP
, stretch
);
11811 /* md_estimate_size_before_relax()
11813 Called just before relax() for rs_machine_dependent frags. The x86
11814 assembler uses these frags to handle variable size jump
11817 Any symbol that is now undefined will not become defined.
11818 Return the correct fr_subtype in the frag.
11819 Return the initial "guess for variable size of frag" to caller.
11820 The guess is actually the growth beyond the fixed part. Whatever
11821 we do to grow the fixed or variable part contributes to our
11825 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11827 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11828 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11829 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11831 i386_classify_machine_dependent_frag (fragP
);
11832 return fragP
->tc_frag_data
.length
;
11835 /* We've already got fragP->fr_subtype right; all we have to do is
11836 check for un-relaxable symbols. On an ELF system, we can't relax
11837 an externally visible symbol, because it may be overridden by a
11839 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11840 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11842 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11845 #if defined (OBJ_COFF) && defined (TE_PE)
11846 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11847 && S_IS_WEAK (fragP
->fr_symbol
))
11851 /* Symbol is undefined in this segment, or we need to keep a
11852 reloc so that weak symbols can be overridden. */
11853 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11854 enum bfd_reloc_code_real reloc_type
;
11855 unsigned char *opcode
;
11858 if (fragP
->fr_var
!= NO_RELOC
)
11859 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11860 else if (size
== 2)
11861 reloc_type
= BFD_RELOC_16_PCREL
;
11862 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11863 else if (need_plt32_p (fragP
->fr_symbol
))
11864 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11867 reloc_type
= BFD_RELOC_32_PCREL
;
11869 old_fr_fix
= fragP
->fr_fix
;
11870 opcode
= (unsigned char *) fragP
->fr_opcode
;
11872 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11875 /* Make jmp (0xeb) a (d)word displacement jump. */
11877 fragP
->fr_fix
+= size
;
11878 fix_new (fragP
, old_fr_fix
, size
,
11880 fragP
->fr_offset
, 1,
11886 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11888 /* Negate the condition, and branch past an
11889 unconditional jump. */
11892 /* Insert an unconditional jump. */
11894 /* We added two extra opcode bytes, and have a two byte
11896 fragP
->fr_fix
+= 2 + 2;
11897 fix_new (fragP
, old_fr_fix
+ 2, 2,
11899 fragP
->fr_offset
, 1,
11903 /* Fall through. */
11906 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11910 fragP
->fr_fix
+= 1;
11911 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11913 fragP
->fr_offset
, 1,
11914 BFD_RELOC_8_PCREL
);
11915 fixP
->fx_signed
= 1;
11919 /* This changes the byte-displacement jump 0x7N
11920 to the (d)word-displacement jump 0x0f,0x8N. */
11921 opcode
[1] = opcode
[0] + 0x10;
11922 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11923 /* We've added an opcode byte. */
11924 fragP
->fr_fix
+= 1 + size
;
11925 fix_new (fragP
, old_fr_fix
+ 1, size
,
11927 fragP
->fr_offset
, 1,
11932 BAD_CASE (fragP
->fr_subtype
);
11936 return fragP
->fr_fix
- old_fr_fix
;
11939 /* Guess size depending on current relax state. Initially the relax
11940 state will correspond to a short jump and we return 1, because
11941 the variable part of the frag (the branch offset) is one byte
11942 long. However, we can relax a section more than once and in that
11943 case we must either set fr_subtype back to the unrelaxed state,
11944 or return the value for the appropriate branch. */
11945 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11948 /* Called after relax() is finished.
11950 In: Address of frag.
11951 fr_type == rs_machine_dependent.
11952 fr_subtype is what the address relaxed to.
11954 Out: Any fixSs and constants are set up.
11955 Caller will turn frag into a ".space 0". */
11958 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11961 unsigned char *opcode
;
11962 unsigned char *where_to_put_displacement
= NULL
;
11963 offsetT target_address
;
11964 offsetT opcode_address
;
11965 unsigned int extension
= 0;
11966 offsetT displacement_from_opcode_start
;
11968 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11969 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11970 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11972 /* Generate nop padding. */
11973 unsigned int size
= fragP
->tc_frag_data
.length
;
11976 if (size
> fragP
->tc_frag_data
.max_bytes
)
11982 const char *branch
= "branch";
11983 const char *prefix
= "";
11984 fragS
*padding_fragP
;
11985 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11988 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11989 switch (fragP
->tc_frag_data
.default_prefix
)
11994 case CS_PREFIX_OPCODE
:
11997 case DS_PREFIX_OPCODE
:
12000 case ES_PREFIX_OPCODE
:
12003 case FS_PREFIX_OPCODE
:
12006 case GS_PREFIX_OPCODE
:
12009 case SS_PREFIX_OPCODE
:
12014 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12015 "%s within %d-byte boundary\n");
12017 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12018 "align %s within %d-byte boundary\n");
12022 padding_fragP
= fragP
;
12023 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12024 "%s within %d-byte boundary\n");
12028 switch (padding_fragP
->tc_frag_data
.branch_type
)
12030 case align_branch_jcc
:
12033 case align_branch_fused
:
12034 branch
= "fused jcc";
12036 case align_branch_jmp
:
12039 case align_branch_call
:
12042 case align_branch_indirect
:
12043 branch
= "indiret branch";
12045 case align_branch_ret
:
12052 fprintf (stdout
, msg
,
12053 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12054 (long long) fragP
->fr_address
, branch
,
12055 1 << align_branch_power
);
12057 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12058 memset (fragP
->fr_opcode
,
12059 fragP
->tc_frag_data
.default_prefix
, size
);
12061 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12063 fragP
->fr_fix
+= size
;
12068 opcode
= (unsigned char *) fragP
->fr_opcode
;
12070 /* Address we want to reach in file space. */
12071 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12073 /* Address opcode resides at in file space. */
12074 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12076 /* Displacement from opcode start to fill into instruction. */
12077 displacement_from_opcode_start
= target_address
- opcode_address
;
12079 if ((fragP
->fr_subtype
& BIG
) == 0)
12081 /* Don't have to change opcode. */
12082 extension
= 1; /* 1 opcode + 1 displacement */
12083 where_to_put_displacement
= &opcode
[1];
12087 if (no_cond_jump_promotion
12088 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12089 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12090 _("long jump required"));
12092 switch (fragP
->fr_subtype
)
12094 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12095 extension
= 4; /* 1 opcode + 4 displacement */
12097 where_to_put_displacement
= &opcode
[1];
12100 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12101 extension
= 2; /* 1 opcode + 2 displacement */
12103 where_to_put_displacement
= &opcode
[1];
12106 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12107 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12108 extension
= 5; /* 2 opcode + 4 displacement */
12109 opcode
[1] = opcode
[0] + 0x10;
12110 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12111 where_to_put_displacement
= &opcode
[2];
12114 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12115 extension
= 3; /* 2 opcode + 2 displacement */
12116 opcode
[1] = opcode
[0] + 0x10;
12117 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12118 where_to_put_displacement
= &opcode
[2];
12121 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12126 where_to_put_displacement
= &opcode
[3];
12130 BAD_CASE (fragP
->fr_subtype
);
12135 /* If size if less then four we are sure that the operand fits,
12136 but if it's 4, then it could be that the displacement is larger
12138 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12140 && ((addressT
) (displacement_from_opcode_start
- extension
12141 + ((addressT
) 1 << 31))
12142 > (((addressT
) 2 << 31) - 1)))
12144 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12145 _("jump target out of range"));
12146 /* Make us emit 0. */
12147 displacement_from_opcode_start
= extension
;
12149 /* Now put displacement after opcode. */
12150 md_number_to_chars ((char *) where_to_put_displacement
,
12151 (valueT
) (displacement_from_opcode_start
- extension
),
12152 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12153 fragP
->fr_fix
+= extension
;
12156 /* Apply a fixup (fixP) to segment data, once it has been determined
12157 by our caller that we have all the info we need to fix it up.
12159 Parameter valP is the pointer to the value of the bits.
12161 On the 386, immediates, displacements, and data pointers are all in
12162 the same (little-endian) format, so we don't need to care about which
12163 we are handling. */
12166 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12168 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12169 valueT value
= *valP
;
12171 #if !defined (TE_Mach)
12172 if (fixP
->fx_pcrel
)
12174 switch (fixP
->fx_r_type
)
12180 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12183 case BFD_RELOC_X86_64_32S
:
12184 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12187 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12190 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12195 if (fixP
->fx_addsy
!= NULL
12196 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12197 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12198 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12199 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12200 && !use_rela_relocations
)
12202 /* This is a hack. There should be a better way to handle this.
12203 This covers for the fact that bfd_install_relocation will
12204 subtract the current location (for partial_inplace, PC relative
12205 relocations); see more below. */
12209 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12212 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12214 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12217 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12219 if ((sym_seg
== seg
12220 || (symbol_section_p (fixP
->fx_addsy
)
12221 && sym_seg
!= absolute_section
))
12222 && !generic_force_reloc (fixP
))
12224 /* Yes, we add the values in twice. This is because
12225 bfd_install_relocation subtracts them out again. I think
12226 bfd_install_relocation is broken, but I don't dare change
12228 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12232 #if defined (OBJ_COFF) && defined (TE_PE)
12233 /* For some reason, the PE format does not store a
12234 section address offset for a PC relative symbol. */
12235 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12236 || S_IS_WEAK (fixP
->fx_addsy
))
12237 value
+= md_pcrel_from (fixP
);
12240 #if defined (OBJ_COFF) && defined (TE_PE)
12241 if (fixP
->fx_addsy
!= NULL
12242 && S_IS_WEAK (fixP
->fx_addsy
)
12243 /* PR 16858: Do not modify weak function references. */
12244 && ! fixP
->fx_pcrel
)
12246 #if !defined (TE_PEP)
12247 /* For x86 PE weak function symbols are neither PC-relative
12248 nor do they set S_IS_FUNCTION. So the only reliable way
12249 to detect them is to check the flags of their containing
12251 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12252 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12256 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12260 /* Fix a few things - the dynamic linker expects certain values here,
12261 and we must not disappoint it. */
12262 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12263 if (IS_ELF
&& fixP
->fx_addsy
)
12264 switch (fixP
->fx_r_type
)
12266 case BFD_RELOC_386_PLT32
:
12267 case BFD_RELOC_X86_64_PLT32
:
12268 /* Make the jump instruction point to the address of the operand.
12269 At runtime we merely add the offset to the actual PLT entry.
12270 NB: Subtract the offset size only for jump instructions. */
12271 if (fixP
->fx_pcrel
)
12275 case BFD_RELOC_386_TLS_GD
:
12276 case BFD_RELOC_386_TLS_LDM
:
12277 case BFD_RELOC_386_TLS_IE_32
:
12278 case BFD_RELOC_386_TLS_IE
:
12279 case BFD_RELOC_386_TLS_GOTIE
:
12280 case BFD_RELOC_386_TLS_GOTDESC
:
12281 case BFD_RELOC_X86_64_TLSGD
:
12282 case BFD_RELOC_X86_64_TLSLD
:
12283 case BFD_RELOC_X86_64_GOTTPOFF
:
12284 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12285 value
= 0; /* Fully resolved at runtime. No addend. */
12287 case BFD_RELOC_386_TLS_LE
:
12288 case BFD_RELOC_386_TLS_LDO_32
:
12289 case BFD_RELOC_386_TLS_LE_32
:
12290 case BFD_RELOC_X86_64_DTPOFF32
:
12291 case BFD_RELOC_X86_64_DTPOFF64
:
12292 case BFD_RELOC_X86_64_TPOFF32
:
12293 case BFD_RELOC_X86_64_TPOFF64
:
12294 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12297 case BFD_RELOC_386_TLS_DESC_CALL
:
12298 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12299 value
= 0; /* Fully resolved at runtime. No addend. */
12300 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12304 case BFD_RELOC_VTABLE_INHERIT
:
12305 case BFD_RELOC_VTABLE_ENTRY
:
12312 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12314 #endif /* !defined (TE_Mach) */
12316 /* Are we finished with this relocation now? */
12317 if (fixP
->fx_addsy
== NULL
)
12319 #if defined (OBJ_COFF) && defined (TE_PE)
12320 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12323 /* Remember value for tc_gen_reloc. */
12324 fixP
->fx_addnumber
= value
;
12325 /* Clear out the frag for now. */
12329 else if (use_rela_relocations
)
12331 fixP
->fx_no_overflow
= 1;
12332 /* Remember value for tc_gen_reloc. */
12333 fixP
->fx_addnumber
= value
;
12337 md_number_to_chars (p
, value
, fixP
->fx_size
);
12341 md_atof (int type
, char *litP
, int *sizeP
)
12343 /* This outputs the LITTLENUMs in REVERSE order;
12344 in accord with the bigendian 386. */
12345 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12348 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12351 output_invalid (int c
)
12354 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12357 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12358 "(0x%x)", (unsigned char) c
);
12359 return output_invalid_buf
;
12362 /* Verify that @r can be used in the current context. */
12364 static bfd_boolean
check_register (const reg_entry
*r
)
12366 if (allow_pseudo_reg
)
12369 if (operand_type_all_zero (&r
->reg_type
))
12372 if ((r
->reg_type
.bitfield
.dword
12373 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12374 || r
->reg_type
.bitfield
.class == RegCR
12375 || r
->reg_type
.bitfield
.class == RegDR
)
12376 && !cpu_arch_flags
.bitfield
.cpui386
)
12379 if (r
->reg_type
.bitfield
.class == RegTR
12380 && (flag_code
== CODE_64BIT
12381 || !cpu_arch_flags
.bitfield
.cpui386
12382 || cpu_arch_isa_flags
.bitfield
.cpui586
12383 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12386 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12389 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12391 if (r
->reg_type
.bitfield
.zmmword
12392 || r
->reg_type
.bitfield
.class == RegMask
)
12395 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12397 if (r
->reg_type
.bitfield
.ymmword
)
12400 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12405 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12408 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12409 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12412 /* Upper 16 vector registers are only available with VREX in 64bit
12413 mode, and require EVEX encoding. */
12414 if (r
->reg_flags
& RegVRex
)
12416 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12417 || flag_code
!= CODE_64BIT
)
12420 if (i
.vec_encoding
== vex_encoding_default
)
12421 i
.vec_encoding
= vex_encoding_evex
;
12422 else if (i
.vec_encoding
!= vex_encoding_evex
)
12423 i
.vec_encoding
= vex_encoding_error
;
12426 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12427 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12428 && flag_code
!= CODE_64BIT
)
12431 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12438 /* REG_STRING starts *before* REGISTER_PREFIX. */
12440 static const reg_entry
*
12441 parse_real_register (char *reg_string
, char **end_op
)
12443 char *s
= reg_string
;
12445 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12446 const reg_entry
*r
;
12448 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12449 if (*s
== REGISTER_PREFIX
)
12452 if (is_space_char (*s
))
12455 p
= reg_name_given
;
12456 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12458 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12459 return (const reg_entry
*) NULL
;
12463 /* For naked regs, make sure that we are not dealing with an identifier.
12464 This prevents confusing an identifier like `eax_var' with register
12466 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12467 return (const reg_entry
*) NULL
;
12471 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12473 /* Handle floating point regs, allowing spaces in the (i) part. */
12474 if (r
== i386_regtab
/* %st is first entry of table */)
12476 if (!cpu_arch_flags
.bitfield
.cpu8087
12477 && !cpu_arch_flags
.bitfield
.cpu287
12478 && !cpu_arch_flags
.bitfield
.cpu387
12479 && !allow_pseudo_reg
)
12480 return (const reg_entry
*) NULL
;
12482 if (is_space_char (*s
))
12487 if (is_space_char (*s
))
12489 if (*s
>= '0' && *s
<= '7')
12491 int fpr
= *s
- '0';
12493 if (is_space_char (*s
))
12498 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12503 /* We have "%st(" then garbage. */
12504 return (const reg_entry
*) NULL
;
12508 return r
&& check_register (r
) ? r
: NULL
;
12511 /* REG_STRING starts *before* REGISTER_PREFIX. */
12513 static const reg_entry
*
12514 parse_register (char *reg_string
, char **end_op
)
12516 const reg_entry
*r
;
12518 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12519 r
= parse_real_register (reg_string
, end_op
);
12524 char *save
= input_line_pointer
;
12528 input_line_pointer
= reg_string
;
12529 c
= get_symbol_name (®_string
);
12530 symbolP
= symbol_find (reg_string
);
12531 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12533 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12535 know (e
->X_op
== O_register
);
12536 know (e
->X_add_number
>= 0
12537 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12538 r
= i386_regtab
+ e
->X_add_number
;
12539 if (!check_register (r
))
12541 as_bad (_("register '%s%s' cannot be used here"),
12542 register_prefix
, r
->reg_name
);
12545 *end_op
= input_line_pointer
;
12547 *input_line_pointer
= c
;
12548 input_line_pointer
= save
;
12554 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12556 const reg_entry
*r
;
12557 char *end
= input_line_pointer
;
12560 r
= parse_register (name
, &input_line_pointer
);
12561 if (r
&& end
<= input_line_pointer
)
12563 *nextcharP
= *input_line_pointer
;
12564 *input_line_pointer
= 0;
12567 e
->X_op
= O_register
;
12568 e
->X_add_number
= r
- i386_regtab
;
12571 e
->X_op
= O_illegal
;
12574 input_line_pointer
= end
;
12576 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12580 md_operand (expressionS
*e
)
12583 const reg_entry
*r
;
12585 switch (*input_line_pointer
)
12587 case REGISTER_PREFIX
:
12588 r
= parse_real_register (input_line_pointer
, &end
);
12591 e
->X_op
= O_register
;
12592 e
->X_add_number
= r
- i386_regtab
;
12593 input_line_pointer
= end
;
12598 gas_assert (intel_syntax
);
12599 end
= input_line_pointer
++;
12601 if (*input_line_pointer
== ']')
12603 ++input_line_pointer
;
12604 e
->X_op_symbol
= make_expr_symbol (e
);
12605 e
->X_add_symbol
= NULL
;
12606 e
->X_add_number
= 0;
12611 e
->X_op
= O_absent
;
12612 input_line_pointer
= end
;
12619 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12620 const char *md_shortopts
= "kVQ:sqnO::";
12622 const char *md_shortopts
= "qnO::";
12625 #define OPTION_32 (OPTION_MD_BASE + 0)
12626 #define OPTION_64 (OPTION_MD_BASE + 1)
12627 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12628 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12629 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12630 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12631 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12632 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12633 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12634 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12635 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12636 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12637 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12638 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12639 #define OPTION_X32 (OPTION_MD_BASE + 14)
12640 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12641 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12642 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12643 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12644 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12645 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12646 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12647 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12648 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12649 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12650 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12651 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12652 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12653 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12654 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12655 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12656 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12657 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12658 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12660 struct option md_longopts
[] =
12662 {"32", no_argument
, NULL
, OPTION_32
},
12663 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12664 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12665 {"64", no_argument
, NULL
, OPTION_64
},
12667 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12668 {"x32", no_argument
, NULL
, OPTION_X32
},
12669 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12670 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12672 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12673 {"march", required_argument
, NULL
, OPTION_MARCH
},
12674 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12675 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12676 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12677 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12678 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12679 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12680 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12681 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12682 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12683 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12684 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12685 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12686 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12687 # if defined (TE_PE) || defined (TE_PEP)
12688 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12690 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12691 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12692 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12693 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12694 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12695 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12696 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12697 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12698 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12699 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12700 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12701 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12702 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12703 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12704 {NULL
, no_argument
, NULL
, 0}
12706 size_t md_longopts_size
= sizeof (md_longopts
);
12709 md_parse_option (int c
, const char *arg
)
12712 char *arch
, *next
, *saved
, *type
;
12717 optimize_align_code
= 0;
12721 quiet_warnings
= 1;
12724 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12725 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12726 should be emitted or not. FIXME: Not implemented. */
12728 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12732 /* -V: SVR4 argument to print version ID. */
12734 print_version_id ();
12737 /* -k: Ignore for FreeBSD compatibility. */
12742 /* -s: On i386 Solaris, this tells the native assembler to use
12743 .stab instead of .stab.excl. We always use .stab anyhow. */
12746 case OPTION_MSHARED
:
12750 case OPTION_X86_USED_NOTE
:
12751 if (strcasecmp (arg
, "yes") == 0)
12753 else if (strcasecmp (arg
, "no") == 0)
12756 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12761 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12762 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12765 const char **list
, **l
;
12767 list
= bfd_target_list ();
12768 for (l
= list
; *l
!= NULL
; l
++)
12769 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12770 || strcmp (*l
, "coff-x86-64") == 0
12771 || strcmp (*l
, "pe-x86-64") == 0
12772 || strcmp (*l
, "pei-x86-64") == 0
12773 || strcmp (*l
, "mach-o-x86-64") == 0)
12775 default_arch
= "x86_64";
12779 as_fatal (_("no compiled in support for x86_64"));
12785 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12789 const char **list
, **l
;
12791 list
= bfd_target_list ();
12792 for (l
= list
; *l
!= NULL
; l
++)
12793 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12795 default_arch
= "x86_64:32";
12799 as_fatal (_("no compiled in support for 32bit x86_64"));
12803 as_fatal (_("32bit x86_64 is only supported for ELF"));
12808 default_arch
= "i386";
12811 case OPTION_DIVIDE
:
12812 #ifdef SVR4_COMMENT_CHARS
12817 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12819 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12823 i386_comment_chars
= n
;
12829 saved
= xstrdup (arg
);
12831 /* Allow -march=+nosse. */
12837 as_fatal (_("invalid -march= option: `%s'"), arg
);
12838 next
= strchr (arch
, '+');
12841 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12843 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12846 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12849 cpu_arch_name
= cpu_arch
[j
].name
;
12850 cpu_sub_arch_name
= NULL
;
12851 cpu_arch_flags
= cpu_arch
[j
].flags
;
12852 cpu_arch_isa
= cpu_arch
[j
].type
;
12853 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12854 if (!cpu_arch_tune_set
)
12856 cpu_arch_tune
= cpu_arch_isa
;
12857 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12861 else if (*cpu_arch
[j
].name
== '.'
12862 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12864 /* ISA extension. */
12865 i386_cpu_flags flags
;
12867 flags
= cpu_flags_or (cpu_arch_flags
,
12868 cpu_arch
[j
].flags
);
12870 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12872 if (cpu_sub_arch_name
)
12874 char *name
= cpu_sub_arch_name
;
12875 cpu_sub_arch_name
= concat (name
,
12877 (const char *) NULL
);
12881 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12882 cpu_arch_flags
= flags
;
12883 cpu_arch_isa_flags
= flags
;
12887 = cpu_flags_or (cpu_arch_isa_flags
,
12888 cpu_arch
[j
].flags
);
12893 if (j
>= ARRAY_SIZE (cpu_arch
))
12895 /* Disable an ISA extension. */
12896 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12897 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12899 i386_cpu_flags flags
;
12901 flags
= cpu_flags_and_not (cpu_arch_flags
,
12902 cpu_noarch
[j
].flags
);
12903 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12905 if (cpu_sub_arch_name
)
12907 char *name
= cpu_sub_arch_name
;
12908 cpu_sub_arch_name
= concat (arch
,
12909 (const char *) NULL
);
12913 cpu_sub_arch_name
= xstrdup (arch
);
12914 cpu_arch_flags
= flags
;
12915 cpu_arch_isa_flags
= flags
;
12920 if (j
>= ARRAY_SIZE (cpu_noarch
))
12921 j
= ARRAY_SIZE (cpu_arch
);
12924 if (j
>= ARRAY_SIZE (cpu_arch
))
12925 as_fatal (_("invalid -march= option: `%s'"), arg
);
12929 while (next
!= NULL
);
12935 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12936 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12938 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12940 cpu_arch_tune_set
= 1;
12941 cpu_arch_tune
= cpu_arch
[j
].type
;
12942 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12946 if (j
>= ARRAY_SIZE (cpu_arch
))
12947 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12950 case OPTION_MMNEMONIC
:
12951 if (strcasecmp (arg
, "att") == 0)
12952 intel_mnemonic
= 0;
12953 else if (strcasecmp (arg
, "intel") == 0)
12954 intel_mnemonic
= 1;
12956 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12959 case OPTION_MSYNTAX
:
12960 if (strcasecmp (arg
, "att") == 0)
12962 else if (strcasecmp (arg
, "intel") == 0)
12965 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12968 case OPTION_MINDEX_REG
:
12969 allow_index_reg
= 1;
12972 case OPTION_MNAKED_REG
:
12973 allow_naked_reg
= 1;
12976 case OPTION_MSSE2AVX
:
12980 case OPTION_MSSE_CHECK
:
12981 if (strcasecmp (arg
, "error") == 0)
12982 sse_check
= check_error
;
12983 else if (strcasecmp (arg
, "warning") == 0)
12984 sse_check
= check_warning
;
12985 else if (strcasecmp (arg
, "none") == 0)
12986 sse_check
= check_none
;
12988 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12991 case OPTION_MOPERAND_CHECK
:
12992 if (strcasecmp (arg
, "error") == 0)
12993 operand_check
= check_error
;
12994 else if (strcasecmp (arg
, "warning") == 0)
12995 operand_check
= check_warning
;
12996 else if (strcasecmp (arg
, "none") == 0)
12997 operand_check
= check_none
;
12999 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13002 case OPTION_MAVXSCALAR
:
13003 if (strcasecmp (arg
, "128") == 0)
13004 avxscalar
= vex128
;
13005 else if (strcasecmp (arg
, "256") == 0)
13006 avxscalar
= vex256
;
13008 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13011 case OPTION_MVEXWIG
:
13012 if (strcmp (arg
, "0") == 0)
13014 else if (strcmp (arg
, "1") == 0)
13017 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13020 case OPTION_MADD_BND_PREFIX
:
13021 add_bnd_prefix
= 1;
13024 case OPTION_MEVEXLIG
:
13025 if (strcmp (arg
, "128") == 0)
13026 evexlig
= evexl128
;
13027 else if (strcmp (arg
, "256") == 0)
13028 evexlig
= evexl256
;
13029 else if (strcmp (arg
, "512") == 0)
13030 evexlig
= evexl512
;
13032 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13035 case OPTION_MEVEXRCIG
:
13036 if (strcmp (arg
, "rne") == 0)
13038 else if (strcmp (arg
, "rd") == 0)
13040 else if (strcmp (arg
, "ru") == 0)
13042 else if (strcmp (arg
, "rz") == 0)
13045 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13048 case OPTION_MEVEXWIG
:
13049 if (strcmp (arg
, "0") == 0)
13051 else if (strcmp (arg
, "1") == 0)
13054 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13057 # if defined (TE_PE) || defined (TE_PEP)
13058 case OPTION_MBIG_OBJ
:
13063 case OPTION_MOMIT_LOCK_PREFIX
:
13064 if (strcasecmp (arg
, "yes") == 0)
13065 omit_lock_prefix
= 1;
13066 else if (strcasecmp (arg
, "no") == 0)
13067 omit_lock_prefix
= 0;
13069 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13072 case OPTION_MFENCE_AS_LOCK_ADD
:
13073 if (strcasecmp (arg
, "yes") == 0)
13075 else if (strcasecmp (arg
, "no") == 0)
13078 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13081 case OPTION_MLFENCE_AFTER_LOAD
:
13082 if (strcasecmp (arg
, "yes") == 0)
13083 lfence_after_load
= 1;
13084 else if (strcasecmp (arg
, "no") == 0)
13085 lfence_after_load
= 0;
13087 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13090 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13091 if (strcasecmp (arg
, "all") == 0)
13093 lfence_before_indirect_branch
= lfence_branch_all
;
13094 if (lfence_before_ret
== lfence_before_ret_none
)
13095 lfence_before_ret
= lfence_before_ret_shl
;
13097 else if (strcasecmp (arg
, "memory") == 0)
13098 lfence_before_indirect_branch
= lfence_branch_memory
;
13099 else if (strcasecmp (arg
, "register") == 0)
13100 lfence_before_indirect_branch
= lfence_branch_register
;
13101 else if (strcasecmp (arg
, "none") == 0)
13102 lfence_before_indirect_branch
= lfence_branch_none
;
13104 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13108 case OPTION_MLFENCE_BEFORE_RET
:
13109 if (strcasecmp (arg
, "or") == 0)
13110 lfence_before_ret
= lfence_before_ret_or
;
13111 else if (strcasecmp (arg
, "not") == 0)
13112 lfence_before_ret
= lfence_before_ret_not
;
13113 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13114 lfence_before_ret
= lfence_before_ret_shl
;
13115 else if (strcasecmp (arg
, "none") == 0)
13116 lfence_before_ret
= lfence_before_ret_none
;
13118 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13122 case OPTION_MRELAX_RELOCATIONS
:
13123 if (strcasecmp (arg
, "yes") == 0)
13124 generate_relax_relocations
= 1;
13125 else if (strcasecmp (arg
, "no") == 0)
13126 generate_relax_relocations
= 0;
13128 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13131 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13134 long int align
= strtoul (arg
, &end
, 0);
13139 align_branch_power
= 0;
13142 else if (align
>= 16)
13145 for (align_power
= 0;
13147 align
>>= 1, align_power
++)
13149 /* Limit alignment power to 31. */
13150 if (align
== 1 && align_power
< 32)
13152 align_branch_power
= align_power
;
13157 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13161 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13164 int align
= strtoul (arg
, &end
, 0);
13165 /* Some processors only support 5 prefixes. */
13166 if (*end
== '\0' && align
>= 0 && align
< 6)
13168 align_branch_prefix_size
= align
;
13171 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13176 case OPTION_MALIGN_BRANCH
:
13178 saved
= xstrdup (arg
);
13182 next
= strchr (type
, '+');
13185 if (strcasecmp (type
, "jcc") == 0)
13186 align_branch
|= align_branch_jcc_bit
;
13187 else if (strcasecmp (type
, "fused") == 0)
13188 align_branch
|= align_branch_fused_bit
;
13189 else if (strcasecmp (type
, "jmp") == 0)
13190 align_branch
|= align_branch_jmp_bit
;
13191 else if (strcasecmp (type
, "call") == 0)
13192 align_branch
|= align_branch_call_bit
;
13193 else if (strcasecmp (type
, "ret") == 0)
13194 align_branch
|= align_branch_ret_bit
;
13195 else if (strcasecmp (type
, "indirect") == 0)
13196 align_branch
|= align_branch_indirect_bit
;
13198 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13201 while (next
!= NULL
);
13205 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13206 align_branch_power
= 5;
13207 align_branch_prefix_size
= 5;
13208 align_branch
= (align_branch_jcc_bit
13209 | align_branch_fused_bit
13210 | align_branch_jmp_bit
);
13213 case OPTION_MAMD64
:
13217 case OPTION_MINTEL64
:
13225 /* Turn off -Os. */
13226 optimize_for_space
= 0;
13228 else if (*arg
== 's')
13230 optimize_for_space
= 1;
13231 /* Turn on all encoding optimizations. */
13232 optimize
= INT_MAX
;
13236 optimize
= atoi (arg
);
13237 /* Turn off -Os. */
13238 optimize_for_space
= 0;
13248 #define MESSAGE_TEMPLATE \
13252 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13253 int *left_p
, const char *name
, int len
)
13255 int size
= sizeof (MESSAGE_TEMPLATE
);
13256 int left
= *left_p
;
13258 /* Reserve 2 spaces for ", " or ",\0" */
13261 /* Check if there is any room. */
13269 p
= mempcpy (p
, name
, len
);
13273 /* Output the current message now and start a new one. */
13276 fprintf (stream
, "%s\n", message
);
13278 left
= size
- (start
- message
) - len
- 2;
13280 gas_assert (left
>= 0);
13282 p
= mempcpy (p
, name
, len
);
13290 show_arch (FILE *stream
, int ext
, int check
)
13292 static char message
[] = MESSAGE_TEMPLATE
;
13293 char *start
= message
+ 27;
13295 int size
= sizeof (MESSAGE_TEMPLATE
);
13302 left
= size
- (start
- message
);
13303 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13305 /* Should it be skipped? */
13306 if (cpu_arch
[j
].skip
)
13309 name
= cpu_arch
[j
].name
;
13310 len
= cpu_arch
[j
].len
;
13313 /* It is an extension. Skip if we aren't asked to show it. */
13324 /* It is an processor. Skip if we show only extension. */
13327 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13329 /* It is an impossible processor - skip. */
13333 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13336 /* Display disabled extensions. */
13338 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13340 name
= cpu_noarch
[j
].name
;
13341 len
= cpu_noarch
[j
].len
;
13342 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13347 fprintf (stream
, "%s\n", message
);
13351 md_show_usage (FILE *stream
)
13353 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13354 fprintf (stream
, _("\
13355 -Qy, -Qn ignored\n\
13356 -V print assembler version number\n\
13359 fprintf (stream
, _("\
13360 -n Do not optimize code alignment\n\
13361 -q quieten some warnings\n"));
13362 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13363 fprintf (stream
, _("\
13366 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13367 || defined (TE_PE) || defined (TE_PEP))
13368 fprintf (stream
, _("\
13369 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13371 #ifdef SVR4_COMMENT_CHARS
13372 fprintf (stream
, _("\
13373 --divide do not treat `/' as a comment character\n"));
13375 fprintf (stream
, _("\
13376 --divide ignored\n"));
13378 fprintf (stream
, _("\
13379 -march=CPU[,+EXTENSION...]\n\
13380 generate code for CPU and EXTENSION, CPU is one of:\n"));
13381 show_arch (stream
, 0, 1);
13382 fprintf (stream
, _("\
13383 EXTENSION is combination of:\n"));
13384 show_arch (stream
, 1, 0);
13385 fprintf (stream
, _("\
13386 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13387 show_arch (stream
, 0, 0);
13388 fprintf (stream
, _("\
13389 -msse2avx encode SSE instructions with VEX prefix\n"));
13390 fprintf (stream
, _("\
13391 -msse-check=[none|error|warning] (default: warning)\n\
13392 check SSE instructions\n"));
13393 fprintf (stream
, _("\
13394 -moperand-check=[none|error|warning] (default: warning)\n\
13395 check operand combinations for validity\n"));
13396 fprintf (stream
, _("\
13397 -mavxscalar=[128|256] (default: 128)\n\
13398 encode scalar AVX instructions with specific vector\n\
13400 fprintf (stream
, _("\
13401 -mvexwig=[0|1] (default: 0)\n\
13402 encode VEX instructions with specific VEX.W value\n\
13403 for VEX.W bit ignored instructions\n"));
13404 fprintf (stream
, _("\
13405 -mevexlig=[128|256|512] (default: 128)\n\
13406 encode scalar EVEX instructions with specific vector\n\
13408 fprintf (stream
, _("\
13409 -mevexwig=[0|1] (default: 0)\n\
13410 encode EVEX instructions with specific EVEX.W value\n\
13411 for EVEX.W bit ignored instructions\n"));
13412 fprintf (stream
, _("\
13413 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13414 encode EVEX instructions with specific EVEX.RC value\n\
13415 for SAE-only ignored instructions\n"));
13416 fprintf (stream
, _("\
13417 -mmnemonic=[att|intel] "));
13418 if (SYSV386_COMPAT
)
13419 fprintf (stream
, _("(default: att)\n"));
13421 fprintf (stream
, _("(default: intel)\n"));
13422 fprintf (stream
, _("\
13423 use AT&T/Intel mnemonic\n"));
13424 fprintf (stream
, _("\
13425 -msyntax=[att|intel] (default: att)\n\
13426 use AT&T/Intel syntax\n"));
13427 fprintf (stream
, _("\
13428 -mindex-reg support pseudo index registers\n"));
13429 fprintf (stream
, _("\
13430 -mnaked-reg don't require `%%' prefix for registers\n"));
13431 fprintf (stream
, _("\
13432 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13433 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13434 fprintf (stream
, _("\
13435 -mshared disable branch optimization for shared code\n"));
13436 fprintf (stream
, _("\
13437 -mx86-used-note=[no|yes] "));
13438 if (DEFAULT_X86_USED_NOTE
)
13439 fprintf (stream
, _("(default: yes)\n"));
13441 fprintf (stream
, _("(default: no)\n"));
13442 fprintf (stream
, _("\
13443 generate x86 used ISA and feature properties\n"));
13445 #if defined (TE_PE) || defined (TE_PEP)
13446 fprintf (stream
, _("\
13447 -mbig-obj generate big object files\n"));
13449 fprintf (stream
, _("\
13450 -momit-lock-prefix=[no|yes] (default: no)\n\
13451 strip all lock prefixes\n"));
13452 fprintf (stream
, _("\
13453 -mfence-as-lock-add=[no|yes] (default: no)\n\
13454 encode lfence, mfence and sfence as\n\
13455 lock addl $0x0, (%%{re}sp)\n"));
13456 fprintf (stream
, _("\
13457 -mrelax-relocations=[no|yes] "));
13458 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13459 fprintf (stream
, _("(default: yes)\n"));
13461 fprintf (stream
, _("(default: no)\n"));
13462 fprintf (stream
, _("\
13463 generate relax relocations\n"));
13464 fprintf (stream
, _("\
13465 -malign-branch-boundary=NUM (default: 0)\n\
13466 align branches within NUM byte boundary\n"));
13467 fprintf (stream
, _("\
13468 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13469 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13471 specify types of branches to align\n"));
13472 fprintf (stream
, _("\
13473 -malign-branch-prefix-size=NUM (default: 5)\n\
13474 align branches with NUM prefixes per instruction\n"));
13475 fprintf (stream
, _("\
13476 -mbranches-within-32B-boundaries\n\
13477 align branches within 32 byte boundary\n"));
13478 fprintf (stream
, _("\
13479 -mlfence-after-load=[no|yes] (default: no)\n\
13480 generate lfence after load\n"));
13481 fprintf (stream
, _("\
13482 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13483 generate lfence before indirect near branch\n"));
13484 fprintf (stream
, _("\
13485 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13486 generate lfence before ret\n"));
13487 fprintf (stream
, _("\
13488 -mamd64 accept only AMD64 ISA [default]\n"));
13489 fprintf (stream
, _("\
13490 -mintel64 accept only Intel64 ISA\n"));
13493 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13494 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13495 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13497 /* Pick the target format to use. */
13500 i386_target_format (void)
13502 if (!strncmp (default_arch
, "x86_64", 6))
13504 update_code_flag (CODE_64BIT
, 1);
13505 if (default_arch
[6] == '\0')
13506 x86_elf_abi
= X86_64_ABI
;
13508 x86_elf_abi
= X86_64_X32_ABI
;
13510 else if (!strcmp (default_arch
, "i386"))
13511 update_code_flag (CODE_32BIT
, 1);
13512 else if (!strcmp (default_arch
, "iamcu"))
13514 update_code_flag (CODE_32BIT
, 1);
13515 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13517 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13518 cpu_arch_name
= "iamcu";
13519 cpu_sub_arch_name
= NULL
;
13520 cpu_arch_flags
= iamcu_flags
;
13521 cpu_arch_isa
= PROCESSOR_IAMCU
;
13522 cpu_arch_isa_flags
= iamcu_flags
;
13523 if (!cpu_arch_tune_set
)
13525 cpu_arch_tune
= cpu_arch_isa
;
13526 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13529 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13530 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13534 as_fatal (_("unknown architecture"));
13536 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13537 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13538 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13539 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13541 switch (OUTPUT_FLAVOR
)
13543 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13544 case bfd_target_aout_flavour
:
13545 return AOUT_TARGET_FORMAT
;
13547 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13548 # if defined (TE_PE) || defined (TE_PEP)
13549 case bfd_target_coff_flavour
:
13550 if (flag_code
== CODE_64BIT
)
13551 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13553 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13554 # elif defined (TE_GO32)
13555 case bfd_target_coff_flavour
:
13556 return "coff-go32";
13558 case bfd_target_coff_flavour
:
13559 return "coff-i386";
13562 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13563 case bfd_target_elf_flavour
:
13565 const char *format
;
13567 switch (x86_elf_abi
)
13570 format
= ELF_TARGET_FORMAT
;
13572 tls_get_addr
= "___tls_get_addr";
13576 use_rela_relocations
= 1;
13579 tls_get_addr
= "__tls_get_addr";
13581 format
= ELF_TARGET_FORMAT64
;
13583 case X86_64_X32_ABI
:
13584 use_rela_relocations
= 1;
13587 tls_get_addr
= "__tls_get_addr";
13589 disallow_64bit_reloc
= 1;
13590 format
= ELF_TARGET_FORMAT32
;
13593 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13595 if (x86_elf_abi
!= X86_64_ABI
)
13596 as_fatal (_("Intel L1OM is 64bit only"));
13597 return ELF_TARGET_L1OM_FORMAT
;
13599 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13601 if (x86_elf_abi
!= X86_64_ABI
)
13602 as_fatal (_("Intel K1OM is 64bit only"));
13603 return ELF_TARGET_K1OM_FORMAT
;
13605 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13607 if (x86_elf_abi
!= I386_ABI
)
13608 as_fatal (_("Intel MCU is 32bit only"));
13609 return ELF_TARGET_IAMCU_FORMAT
;
13615 #if defined (OBJ_MACH_O)
13616 case bfd_target_mach_o_flavour
:
13617 if (flag_code
== CODE_64BIT
)
13619 use_rela_relocations
= 1;
13621 return "mach-o-x86-64";
13624 return "mach-o-i386";
13632 #endif /* OBJ_MAYBE_ more than one */
13635 md_undefined_symbol (char *name
)
13637 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13638 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13639 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13640 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13644 if (symbol_find (name
))
13645 as_bad (_("GOT already in symbol table"));
13646 GOT_symbol
= symbol_new (name
, undefined_section
,
13647 (valueT
) 0, &zero_address_frag
);
13654 /* Round up a section size to the appropriate boundary. */
13657 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13659 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13660 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13662 /* For a.out, force the section size to be aligned. If we don't do
13663 this, BFD will align it for us, but it will not write out the
13664 final bytes of the section. This may be a bug in BFD, but it is
13665 easier to fix it here since that is how the other a.out targets
13669 align
= bfd_section_alignment (segment
);
13670 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13677 /* On the i386, PC-relative offsets are relative to the start of the
13678 next instruction. That is, the address of the offset, plus its
13679 size, since the offset is always the last part of the insn. */
13682 md_pcrel_from (fixS
*fixP
)
13684 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13690 s_bss (int ignore ATTRIBUTE_UNUSED
)
13694 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13696 obj_elf_section_change_hook ();
13698 temp
= get_absolute_expression ();
13699 subseg_set (bss_section
, (subsegT
) temp
);
13700 demand_empty_rest_of_line ();
13705 /* Remember constant directive. */
13708 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13710 if (last_insn
.kind
!= last_insn_directive
13711 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13713 last_insn
.seg
= now_seg
;
13714 last_insn
.kind
= last_insn_directive
;
13715 last_insn
.name
= "constant directive";
13716 last_insn
.file
= as_where (&last_insn
.line
);
13717 if (lfence_before_ret
!= lfence_before_ret_none
)
13719 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13720 as_warn (_("constant directive skips -mlfence-before-ret "
13721 "and -mlfence-before-indirect-branch"));
13723 as_warn (_("constant directive skips -mlfence-before-ret"));
13725 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13726 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13731 i386_validate_fix (fixS
*fixp
)
13733 if (fixp
->fx_subsy
)
13735 if (fixp
->fx_subsy
== GOT_symbol
)
13737 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13741 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13742 if (fixp
->fx_tcbit2
)
13743 fixp
->fx_r_type
= (fixp
->fx_tcbit
13744 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13745 : BFD_RELOC_X86_64_GOTPCRELX
);
13748 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13753 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13755 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13757 fixp
->fx_subsy
= 0;
13760 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13761 else if (!object_64bit
)
13763 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13764 && fixp
->fx_tcbit2
)
13765 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13771 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13774 bfd_reloc_code_real_type code
;
13776 switch (fixp
->fx_r_type
)
13778 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13779 case BFD_RELOC_SIZE32
:
13780 case BFD_RELOC_SIZE64
:
13781 if (S_IS_DEFINED (fixp
->fx_addsy
)
13782 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13784 /* Resolve size relocation against local symbol to size of
13785 the symbol plus addend. */
13786 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13787 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13788 && !fits_in_unsigned_long (value
))
13789 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13790 _("symbol size computation overflow"));
13791 fixp
->fx_addsy
= NULL
;
13792 fixp
->fx_subsy
= NULL
;
13793 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13797 /* Fall through. */
13799 case BFD_RELOC_X86_64_PLT32
:
13800 case BFD_RELOC_X86_64_GOT32
:
13801 case BFD_RELOC_X86_64_GOTPCREL
:
13802 case BFD_RELOC_X86_64_GOTPCRELX
:
13803 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13804 case BFD_RELOC_386_PLT32
:
13805 case BFD_RELOC_386_GOT32
:
13806 case BFD_RELOC_386_GOT32X
:
13807 case BFD_RELOC_386_GOTOFF
:
13808 case BFD_RELOC_386_GOTPC
:
13809 case BFD_RELOC_386_TLS_GD
:
13810 case BFD_RELOC_386_TLS_LDM
:
13811 case BFD_RELOC_386_TLS_LDO_32
:
13812 case BFD_RELOC_386_TLS_IE_32
:
13813 case BFD_RELOC_386_TLS_IE
:
13814 case BFD_RELOC_386_TLS_GOTIE
:
13815 case BFD_RELOC_386_TLS_LE_32
:
13816 case BFD_RELOC_386_TLS_LE
:
13817 case BFD_RELOC_386_TLS_GOTDESC
:
13818 case BFD_RELOC_386_TLS_DESC_CALL
:
13819 case BFD_RELOC_X86_64_TLSGD
:
13820 case BFD_RELOC_X86_64_TLSLD
:
13821 case BFD_RELOC_X86_64_DTPOFF32
:
13822 case BFD_RELOC_X86_64_DTPOFF64
:
13823 case BFD_RELOC_X86_64_GOTTPOFF
:
13824 case BFD_RELOC_X86_64_TPOFF32
:
13825 case BFD_RELOC_X86_64_TPOFF64
:
13826 case BFD_RELOC_X86_64_GOTOFF64
:
13827 case BFD_RELOC_X86_64_GOTPC32
:
13828 case BFD_RELOC_X86_64_GOT64
:
13829 case BFD_RELOC_X86_64_GOTPCREL64
:
13830 case BFD_RELOC_X86_64_GOTPC64
:
13831 case BFD_RELOC_X86_64_GOTPLT64
:
13832 case BFD_RELOC_X86_64_PLTOFF64
:
13833 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13834 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13835 case BFD_RELOC_RVA
:
13836 case BFD_RELOC_VTABLE_ENTRY
:
13837 case BFD_RELOC_VTABLE_INHERIT
:
13839 case BFD_RELOC_32_SECREL
:
13841 code
= fixp
->fx_r_type
;
13843 case BFD_RELOC_X86_64_32S
:
13844 if (!fixp
->fx_pcrel
)
13846 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13847 code
= fixp
->fx_r_type
;
13850 /* Fall through. */
13852 if (fixp
->fx_pcrel
)
13854 switch (fixp
->fx_size
)
13857 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13858 _("can not do %d byte pc-relative relocation"),
13860 code
= BFD_RELOC_32_PCREL
;
13862 case 1: code
= BFD_RELOC_8_PCREL
; break;
13863 case 2: code
= BFD_RELOC_16_PCREL
; break;
13864 case 4: code
= BFD_RELOC_32_PCREL
; break;
13866 case 8: code
= BFD_RELOC_64_PCREL
; break;
13872 switch (fixp
->fx_size
)
13875 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13876 _("can not do %d byte relocation"),
13878 code
= BFD_RELOC_32
;
13880 case 1: code
= BFD_RELOC_8
; break;
13881 case 2: code
= BFD_RELOC_16
; break;
13882 case 4: code
= BFD_RELOC_32
; break;
13884 case 8: code
= BFD_RELOC_64
; break;
13891 if ((code
== BFD_RELOC_32
13892 || code
== BFD_RELOC_32_PCREL
13893 || code
== BFD_RELOC_X86_64_32S
)
13895 && fixp
->fx_addsy
== GOT_symbol
)
13898 code
= BFD_RELOC_386_GOTPC
;
13900 code
= BFD_RELOC_X86_64_GOTPC32
;
13902 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13904 && fixp
->fx_addsy
== GOT_symbol
)
13906 code
= BFD_RELOC_X86_64_GOTPC64
;
13909 rel
= XNEW (arelent
);
13910 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13911 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13913 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13915 if (!use_rela_relocations
)
13917 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13918 vtable entry to be used in the relocation's section offset. */
13919 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13920 rel
->address
= fixp
->fx_offset
;
13921 #if defined (OBJ_COFF) && defined (TE_PE)
13922 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13923 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13928 /* Use the rela in 64bit mode. */
13931 if (disallow_64bit_reloc
)
13934 case BFD_RELOC_X86_64_DTPOFF64
:
13935 case BFD_RELOC_X86_64_TPOFF64
:
13936 case BFD_RELOC_64_PCREL
:
13937 case BFD_RELOC_X86_64_GOTOFF64
:
13938 case BFD_RELOC_X86_64_GOT64
:
13939 case BFD_RELOC_X86_64_GOTPCREL64
:
13940 case BFD_RELOC_X86_64_GOTPC64
:
13941 case BFD_RELOC_X86_64_GOTPLT64
:
13942 case BFD_RELOC_X86_64_PLTOFF64
:
13943 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13944 _("cannot represent relocation type %s in x32 mode"),
13945 bfd_get_reloc_code_name (code
));
13951 if (!fixp
->fx_pcrel
)
13952 rel
->addend
= fixp
->fx_offset
;
13956 case BFD_RELOC_X86_64_PLT32
:
13957 case BFD_RELOC_X86_64_GOT32
:
13958 case BFD_RELOC_X86_64_GOTPCREL
:
13959 case BFD_RELOC_X86_64_GOTPCRELX
:
13960 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13961 case BFD_RELOC_X86_64_TLSGD
:
13962 case BFD_RELOC_X86_64_TLSLD
:
13963 case BFD_RELOC_X86_64_GOTTPOFF
:
13964 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13965 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13966 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13969 rel
->addend
= (section
->vma
13971 + fixp
->fx_addnumber
13972 + md_pcrel_from (fixp
));
13977 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13978 if (rel
->howto
== NULL
)
13980 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13981 _("cannot represent relocation type %s"),
13982 bfd_get_reloc_code_name (code
));
13983 /* Set howto to a garbage value so that we can keep going. */
13984 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13985 gas_assert (rel
->howto
!= NULL
);
13991 #include "tc-i386-intel.c"
13994 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13996 int saved_naked_reg
;
13997 char saved_register_dot
;
13999 saved_naked_reg
= allow_naked_reg
;
14000 allow_naked_reg
= 1;
14001 saved_register_dot
= register_chars
['.'];
14002 register_chars
['.'] = '.';
14003 allow_pseudo_reg
= 1;
14004 expression_and_evaluate (exp
);
14005 allow_pseudo_reg
= 0;
14006 register_chars
['.'] = saved_register_dot
;
14007 allow_naked_reg
= saved_naked_reg
;
14009 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14011 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14013 exp
->X_op
= O_constant
;
14014 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14015 .dw2_regnum
[flag_code
>> 1];
14018 exp
->X_op
= O_illegal
;
14023 tc_x86_frame_initial_instructions (void)
14025 static unsigned int sp_regno
[2];
14027 if (!sp_regno
[flag_code
>> 1])
14029 char *saved_input
= input_line_pointer
;
14030 char sp
[][4] = {"esp", "rsp"};
14033 input_line_pointer
= sp
[flag_code
>> 1];
14034 tc_x86_parse_to_dw2regnum (&exp
);
14035 gas_assert (exp
.X_op
== O_constant
);
14036 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14037 input_line_pointer
= saved_input
;
14040 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14041 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14045 x86_dwarf2_addr_size (void)
14047 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14048 if (x86_elf_abi
== X86_64_X32_ABI
)
14051 return bfd_arch_bits_per_address (stdoutput
) / 8;
14055 i386_elf_section_type (const char *str
, size_t len
)
14057 if (flag_code
== CODE_64BIT
14058 && len
== sizeof ("unwind") - 1
14059 && strncmp (str
, "unwind", 6) == 0)
14060 return SHT_X86_64_UNWIND
;
14067 i386_solaris_fix_up_eh_frame (segT sec
)
14069 if (flag_code
== CODE_64BIT
)
14070 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14076 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14080 exp
.X_op
= O_secrel
;
14081 exp
.X_add_symbol
= symbol
;
14082 exp
.X_add_number
= 0;
14083 emit_expr (&exp
, size
);
14087 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14088 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14091 x86_64_section_letter (int letter
, const char **ptr_msg
)
14093 if (flag_code
== CODE_64BIT
)
14096 return SHF_X86_64_LARGE
;
14098 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14101 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14106 x86_64_section_word (char *str
, size_t len
)
14108 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14109 return SHF_X86_64_LARGE
;
14115 handle_large_common (int small ATTRIBUTE_UNUSED
)
14117 if (flag_code
!= CODE_64BIT
)
14119 s_comm_internal (0, elf_common_parse
);
14120 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14124 static segT lbss_section
;
14125 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14126 asection
*saved_bss_section
= bss_section
;
14128 if (lbss_section
== NULL
)
14130 flagword applicable
;
14131 segT seg
= now_seg
;
14132 subsegT subseg
= now_subseg
;
14134 /* The .lbss section is for local .largecomm symbols. */
14135 lbss_section
= subseg_new (".lbss", 0);
14136 applicable
= bfd_applicable_section_flags (stdoutput
);
14137 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14138 seg_info (lbss_section
)->bss
= 1;
14140 subseg_set (seg
, subseg
);
14143 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14144 bss_section
= lbss_section
;
14146 s_comm_internal (0, elf_common_parse
);
14148 elf_com_section_ptr
= saved_com_section_ptr
;
14149 bss_section
= saved_bss_section
;
14152 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */