1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
293 invalid_vsib_address
,
294 invalid_vector_register_set
,
295 unsupported_vector_index_register
,
296 unsupported_broadcast
,
299 mask_not_on_destination
,
302 rc_sae_operand_not_last_imm
,
303 invalid_register_operand
,
308 /* TM holds the template for the insn were currently assembling. */
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands
;
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
321 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types
[MAX_OPERANDS
];
327 /* Displacement expression, immediate expression, or register for each
329 union i386_op op
[MAX_OPERANDS
];
331 /* Flags for operands. */
332 unsigned int flags
[MAX_OPERANDS
];
333 #define Operand_PCrel 1
334 #define Operand_Mem 2
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry
*base_reg
;
342 const reg_entry
*index_reg
;
343 unsigned int log2_scale_factor
;
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry
*seg
[2];
349 /* Copied first memory operand string, for re-checking. */
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes
;
355 unsigned char prefix
[MAX_PREFIXES
];
357 /* Register is in low 3 bits of opcode. */
358 bfd_boolean short_form
;
360 /* The operand to a branch insn indicates an absolute branch. */
361 bfd_boolean jumpabsolute
;
363 /* Has MMX register operands. */
364 bfd_boolean has_regmmx
;
366 /* Has XMM register operands. */
367 bfd_boolean has_regxmm
;
369 /* Has YMM register operands. */
370 bfd_boolean has_regymm
;
372 /* Has ZMM register operands. */
373 bfd_boolean has_regzmm
;
375 /* Has GOTPC or TLS relocation. */
376 bfd_boolean has_gotpc_tls_reloc
;
378 /* RM and SIB are the modrm byte and the sib byte where the
379 addressing modes of this insn are encoded. */
386 /* Masking attributes. */
387 struct Mask_Operation
*mask
;
389 /* Rounding control and SAE attributes. */
390 struct RC_Operation
*rounding
;
392 /* Broadcasting attributes. */
393 struct Broadcast_Operation
*broadcast
;
395 /* Compressed disp8*N attribute. */
396 unsigned int memshift
;
398 /* Prefer load or store in encoding. */
401 dir_encoding_default
= 0,
407 /* Prefer 8bit or 32bit displacement in encoding. */
410 disp_encoding_default
= 0,
415 /* Prefer the REX byte in encoding. */
416 bfd_boolean rex_encoding
;
418 /* Disable instruction size optimization. */
419 bfd_boolean no_optimize
;
421 /* How to encode vector instructions. */
424 vex_encoding_default
= 0,
432 const char *rep_prefix
;
435 const char *hle_prefix
;
437 /* Have BND prefix. */
438 const char *bnd_prefix
;
440 /* Have NOTRACK prefix. */
441 const char *notrack_prefix
;
444 enum i386_error error
;
447 typedef struct _i386_insn i386_insn
;
449 /* Link RC type with corresponding string, that'll be looked for in
458 static const struct RC_name RC_NamesTable
[] =
460 { rne
, STRING_COMMA_LEN ("rn-sae") },
461 { rd
, STRING_COMMA_LEN ("rd-sae") },
462 { ru
, STRING_COMMA_LEN ("ru-sae") },
463 { rz
, STRING_COMMA_LEN ("rz-sae") },
464 { saeonly
, STRING_COMMA_LEN ("sae") },
467 /* List of chars besides those in app.c:symbol_chars that can start an
468 operand. Used to prevent the scrubber eating vital white-space. */
469 const char extra_symbol_chars
[] = "*%-([{}"
478 #if (defined (TE_I386AIX) \
479 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
480 && !defined (TE_GNU) \
481 && !defined (TE_LINUX) \
482 && !defined (TE_NACL) \
483 && !defined (TE_FreeBSD) \
484 && !defined (TE_DragonFly) \
485 && !defined (TE_NetBSD)))
486 /* This array holds the chars that always start a comment. If the
487 pre-processor is disabled, these aren't very useful. The option
488 --divide will remove '/' from this list. */
489 const char *i386_comment_chars
= "#/";
490 #define SVR4_COMMENT_CHARS 1
491 #define PREFIX_SEPARATOR '\\'
494 const char *i386_comment_chars
= "#";
495 #define PREFIX_SEPARATOR '/'
498 /* This array holds the chars that only start a comment at the beginning of
499 a line. If the line seems to have the form '# 123 filename'
500 .line and .file directives will appear in the pre-processed output.
501 Note that input_file.c hand checks for '#' at the beginning of the
502 first line of the input file. This is because the compiler outputs
503 #NO_APP at the beginning of its output.
504 Also note that comments started like this one will always work if
505 '/' isn't otherwise defined. */
506 const char line_comment_chars
[] = "#/";
508 const char line_separator_chars
[] = ";";
510 /* Chars that can be used to separate mant from exp in floating point
512 const char EXP_CHARS
[] = "eE";
514 /* Chars that mean this number is a floating point constant
517 const char FLT_CHARS
[] = "fFdDxX";
519 /* Tables for lexical analysis. */
520 static char mnemonic_chars
[256];
521 static char register_chars
[256];
522 static char operand_chars
[256];
523 static char identifier_chars
[256];
524 static char digit_chars
[256];
526 /* Lexical macros. */
527 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
528 #define is_operand_char(x) (operand_chars[(unsigned char) x])
529 #define is_register_char(x) (register_chars[(unsigned char) x])
530 #define is_space_char(x) ((x) == ' ')
531 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
532 #define is_digit_char(x) (digit_chars[(unsigned char) x])
534 /* All non-digit non-letter characters that may occur in an operand. */
535 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
537 /* md_assemble() always leaves the strings it's passed unaltered. To
538 effect this we maintain a stack of saved characters that we've smashed
539 with '\0's (indicating end of strings for various sub-fields of the
540 assembler instruction). */
541 static char save_stack
[32];
542 static char *save_stack_p
;
543 #define END_STRING_AND_SAVE(s) \
544 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
545 #define RESTORE_END_STRING(s) \
546 do { *(s) = *--save_stack_p; } while (0)
548 /* The instruction we're assembling. */
551 /* Possible templates for current insn. */
552 static const templates
*current_templates
;
554 /* Per instruction expressionS buffers: max displacements & immediates. */
555 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
556 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
558 /* Current operand we are working on. */
559 static int this_operand
= -1;
561 /* We support four different modes. FLAG_CODE variable is used to distinguish
569 static enum flag_code flag_code
;
570 static unsigned int object_64bit
;
571 static unsigned int disallow_64bit_reloc
;
572 static int use_rela_relocations
= 0;
573 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
574 static const char *tls_get_addr
;
576 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
577 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
578 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
580 /* The ELF ABI to use. */
588 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
591 #if defined (TE_PE) || defined (TE_PEP)
592 /* Use big object file format. */
593 static int use_big_obj
= 0;
596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
597 /* 1 if generating code for a shared library. */
598 static int shared
= 0;
601 /* 1 for intel syntax,
603 static int intel_syntax
= 0;
605 static enum x86_64_isa
607 amd64
= 1, /* AMD64 ISA. */
608 intel64
/* Intel64 ISA. */
611 /* 1 for intel mnemonic,
612 0 if att mnemonic. */
613 static int intel_mnemonic
= !SYSV386_COMPAT
;
615 /* 1 if pseudo registers are permitted. */
616 static int allow_pseudo_reg
= 0;
618 /* 1 if register prefix % not required. */
619 static int allow_naked_reg
= 0;
621 /* 1 if the assembler should add BND prefix for all control-transferring
622 instructions supporting it, even if this prefix wasn't specified
624 static int add_bnd_prefix
= 0;
626 /* 1 if pseudo index register, eiz/riz, is allowed . */
627 static int allow_index_reg
= 0;
629 /* 1 if the assembler should ignore LOCK prefix, even if it was
630 specified explicitly. */
631 static int omit_lock_prefix
= 0;
633 /* 1 if the assembler should encode lfence, mfence, and sfence as
634 "lock addl $0, (%{re}sp)". */
635 static int avoid_fence
= 0;
637 /* 1 if lfence should be inserted after every load. */
638 static int lfence_after_load
= 0;
640 /* Non-zero if lfence should be inserted before indirect branch. */
641 static enum lfence_before_indirect_branch_kind
643 lfence_branch_none
= 0,
644 lfence_branch_register
,
645 lfence_branch_memory
,
648 lfence_before_indirect_branch
;
650 /* Non-zero if lfence should be inserted before ret. */
651 static enum lfence_before_ret_kind
653 lfence_before_ret_none
= 0,
654 lfence_before_ret_not
,
655 lfence_before_ret_or
,
656 lfence_before_ret_shl
660 /* Types of previous instruction is .byte or prefix. */
675 /* 1 if the assembler should generate relax relocations. */
677 static int generate_relax_relocations
678 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
680 static enum check_kind
686 sse_check
, operand_check
= check_warning
;
688 /* Non-zero if branches should be aligned within power of 2 boundary. */
689 static int align_branch_power
= 0;
691 /* Types of branches to align. */
692 enum align_branch_kind
694 align_branch_none
= 0,
695 align_branch_jcc
= 1,
696 align_branch_fused
= 2,
697 align_branch_jmp
= 3,
698 align_branch_call
= 4,
699 align_branch_indirect
= 5,
703 /* Type bits of branches to align. */
704 enum align_branch_bit
706 align_branch_jcc_bit
= 1 << align_branch_jcc
,
707 align_branch_fused_bit
= 1 << align_branch_fused
,
708 align_branch_jmp_bit
= 1 << align_branch_jmp
,
709 align_branch_call_bit
= 1 << align_branch_call
,
710 align_branch_indirect_bit
= 1 << align_branch_indirect
,
711 align_branch_ret_bit
= 1 << align_branch_ret
714 static unsigned int align_branch
= (align_branch_jcc_bit
715 | align_branch_fused_bit
716 | align_branch_jmp_bit
);
718 /* Types of condition jump used by macro-fusion. */
721 mf_jcc_jo
= 0, /* base opcode 0x70 */
722 mf_jcc_jc
, /* base opcode 0x72 */
723 mf_jcc_je
, /* base opcode 0x74 */
724 mf_jcc_jna
, /* base opcode 0x76 */
725 mf_jcc_js
, /* base opcode 0x78 */
726 mf_jcc_jp
, /* base opcode 0x7a */
727 mf_jcc_jl
, /* base opcode 0x7c */
728 mf_jcc_jle
, /* base opcode 0x7e */
731 /* Types of compare flag-modifying insntructions used by macro-fusion. */
734 mf_cmp_test_and
, /* test/cmp */
735 mf_cmp_alu_cmp
, /* add/sub/cmp */
736 mf_cmp_incdec
/* inc/dec */
739 /* The maximum padding size for fused jcc. CMP like instruction can
740 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
742 #define MAX_FUSED_JCC_PADDING_SIZE 20
744 /* The maximum number of prefixes added for an instruction. */
745 static unsigned int align_branch_prefix_size
= 5;
748 1. Clear the REX_W bit with register operand if possible.
749 2. Above plus use 128bit vector instruction to clear the full vector
752 static int optimize
= 0;
755 1. Clear the REX_W bit with register operand if possible.
756 2. Above plus use 128bit vector instruction to clear the full vector
758 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
761 static int optimize_for_space
= 0;
763 /* Register prefix used for error message. */
764 static const char *register_prefix
= "%";
766 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
767 leave, push, and pop instructions so that gcc has the same stack
768 frame as in 32 bit mode. */
769 static char stackop_size
= '\0';
771 /* Non-zero to optimize code alignment. */
772 int optimize_align_code
= 1;
774 /* Non-zero to quieten some warnings. */
775 static int quiet_warnings
= 0;
778 static const char *cpu_arch_name
= NULL
;
779 static char *cpu_sub_arch_name
= NULL
;
781 /* CPU feature flags. */
782 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
784 /* If we have selected a cpu we are generating instructions for. */
785 static int cpu_arch_tune_set
= 0;
787 /* Cpu we are generating instructions for. */
788 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
790 /* CPU feature flags of cpu we are generating instructions for. */
791 static i386_cpu_flags cpu_arch_tune_flags
;
793 /* CPU instruction set architecture used. */
794 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
796 /* CPU feature flags of instruction set architecture used. */
797 i386_cpu_flags cpu_arch_isa_flags
;
799 /* If set, conditional jumps are not automatically promoted to handle
800 larger than a byte offset. */
801 static unsigned int no_cond_jump_promotion
= 0;
803 /* Encode SSE instructions with VEX prefix. */
804 static unsigned int sse2avx
;
806 /* Encode scalar AVX instructions with specific vector length. */
813 /* Encode VEX WIG instructions with specific vex.w. */
820 /* Encode scalar EVEX LIG instructions with specific vector length. */
828 /* Encode EVEX WIG instructions with specific evex.w. */
835 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
836 static enum rc_type evexrcig
= rne
;
838 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
839 static symbolS
*GOT_symbol
;
841 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
842 unsigned int x86_dwarf2_return_column
;
844 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
845 int x86_cie_data_alignment
;
847 /* Interface to relax_segment.
848 There are 3 major relax states for 386 jump insns because the
849 different types of jumps add different sizes to frags when we're
850 figuring out what sort of jump to choose to reach a given label.
852 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
853 branches which are handled by md_estimate_size_before_relax() and
854 i386_generic_table_relax_frag(). */
857 #define UNCOND_JUMP 0
859 #define COND_JUMP86 2
860 #define BRANCH_PADDING 3
861 #define BRANCH_PREFIX 4
862 #define FUSED_JCC_PADDING 5
867 #define SMALL16 (SMALL | CODE16)
869 #define BIG16 (BIG | CODE16)
873 #define INLINE __inline__
879 #define ENCODE_RELAX_STATE(type, size) \
880 ((relax_substateT) (((type) << 2) | (size)))
881 #define TYPE_FROM_RELAX_STATE(s) \
883 #define DISP_SIZE_FROM_RELAX_STATE(s) \
884 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
886 /* This table is used by relax_frag to promote short jumps to long
887 ones where necessary. SMALL (short) jumps may be promoted to BIG
888 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
889 don't allow a short jump in a 32 bit code segment to be promoted to
890 a 16 bit offset jump because it's slower (requires data size
891 prefix), and doesn't work, unless the destination is in the bottom
892 64k of the code segment (The top 16 bits of eip are zeroed). */
894 const relax_typeS md_relax_table
[] =
897 1) most positive reach of this state,
898 2) most negative reach of this state,
899 3) how many bytes this mode will have in the variable part of the frag
900 4) which index into the table to try if we can't fit into this one. */
902 /* UNCOND_JUMP states. */
903 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
904 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
905 /* dword jmp adds 4 bytes to frag:
906 0 extra opcode bytes, 4 displacement bytes. */
908 /* word jmp adds 2 byte2 to frag:
909 0 extra opcode bytes, 2 displacement bytes. */
912 /* COND_JUMP states. */
913 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
914 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
915 /* dword conditionals adds 5 bytes to frag:
916 1 extra opcode byte, 4 displacement bytes. */
918 /* word conditionals add 3 bytes to frag:
919 1 extra opcode byte, 2 displacement bytes. */
922 /* COND_JUMP86 states. */
923 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
924 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
925 /* dword conditionals adds 5 bytes to frag:
926 1 extra opcode byte, 4 displacement bytes. */
928 /* word conditionals add 4 bytes to frag:
929 1 displacement byte and a 3 byte long branch insn. */
933 static const arch_entry cpu_arch
[] =
935 /* Do not replace the first two entries - i386_target_format()
936 relies on them being there in this order. */
937 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
938 CPU_GENERIC32_FLAGS
, 0 },
939 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
940 CPU_GENERIC64_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
949 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
951 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
953 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
955 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
957 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
958 CPU_PENTIUMPRO_FLAGS
, 0 },
959 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
961 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
963 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
965 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
967 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
968 CPU_NOCONA_FLAGS
, 0 },
969 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
971 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
973 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
974 CPU_CORE2_FLAGS
, 1 },
975 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
976 CPU_CORE2_FLAGS
, 0 },
977 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
978 CPU_COREI7_FLAGS
, 0 },
979 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
981 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
983 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
984 CPU_IAMCU_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
987 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
989 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
990 CPU_ATHLON_FLAGS
, 0 },
991 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
993 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
995 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
997 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
998 CPU_AMDFAM10_FLAGS
, 0 },
999 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1000 CPU_BDVER1_FLAGS
, 0 },
1001 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1002 CPU_BDVER2_FLAGS
, 0 },
1003 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1004 CPU_BDVER3_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1006 CPU_BDVER4_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1008 CPU_ZNVER1_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1010 CPU_ZNVER2_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1012 CPU_BTVER1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1014 CPU_BTVER2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1016 CPU_8087_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1021 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1024 CPU_CMOV_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1026 CPU_FXSR_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1029 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1032 CPU_SSE2_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1034 CPU_SSE3_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1036 CPU_SSE4A_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1038 CPU_SSSE3_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE4_1_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1042 CPU_SSE4_2_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4_2_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1047 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX2_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512F_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX512CD_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512ER_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512PF_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512DQ_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512BW_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512VL_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1066 CPU_VMFUNC_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1070 CPU_XSAVE_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1072 CPU_XSAVEOPT_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1074 CPU_XSAVEC_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1076 CPU_XSAVES_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1079 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1080 CPU_PCLMUL_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1082 CPU_PCLMUL_FLAGS
, 1 },
1083 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1084 CPU_FSGSBASE_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1086 CPU_RDRND_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1088 CPU_F16C_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1090 CPU_BMI2_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1093 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1094 CPU_FMA4_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1099 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1100 CPU_MOVBE_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1102 CPU_CX16_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1106 CPU_LZCNT_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1108 CPU_POPCNT_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1111 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1114 CPU_INVPCID_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1116 CPU_CLFLUSH_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1119 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1120 CPU_SYSCALL_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1122 CPU_RDTSCP_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1124 CPU_3DNOW_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1126 CPU_3DNOWA_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1128 CPU_PADLOCK_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1130 CPU_SVME_FLAGS
, 1 },
1131 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1132 CPU_SVME_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1134 CPU_SSE4A_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1137 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1139 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1141 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1143 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1144 CPU_RDSEED_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1146 CPU_PRFCHW_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1148 CPU_SMAP_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1151 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1153 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1154 CPU_CLFLUSHOPT_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1156 CPU_PREFETCHWT1_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1159 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1160 CPU_CLWB_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1162 CPU_AVX512IFMA_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1164 CPU_AVX512VBMI_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1166 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512_VBMI2_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_VNNI_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_BITALG_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1178 CPU_CLZERO_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1180 CPU_MWAITX_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1182 CPU_OSPKE_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1184 CPU_RDPID_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1186 CPU_PTWRITE_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1189 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1190 CPU_SHSTK_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1192 CPU_GFNI_FLAGS
, 0 },
1193 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1194 CPU_VAES_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1196 CPU_VPCLMULQDQ_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1198 CPU_WBNOINVD_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1200 CPU_PCONFIG_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1202 CPU_WAITPKG_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1204 CPU_CLDEMOTE_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1206 CPU_MOVDIRI_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1208 CPU_MOVDIR64B_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1210 CPU_AVX512_BF16_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1212 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1214 CPU_ENQCMD_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1216 CPU_SERIALIZE_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1218 CPU_RDPRU_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1220 CPU_MCOMMIT_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1222 CPU_SEV_ES_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1224 CPU_TSXLDTRK_FLAGS
, 0 },
1227 static const noarch_entry cpu_noarch
[] =
1229 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1230 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1231 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1232 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1233 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1234 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1235 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1236 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1237 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1238 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1239 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1240 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1241 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1242 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1243 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1244 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1245 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1246 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1247 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1248 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1249 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1250 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1251 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1252 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1253 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1254 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1255 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1256 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1257 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1258 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1260 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1261 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1262 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1263 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1264 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1267 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1268 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1269 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1270 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1274 /* Like s_lcomm_internal in gas/read.c but the alignment string
1275 is allowed to be optional. */
1278 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1285 && *input_line_pointer
== ',')
1287 align
= parse_align (needs_align
- 1);
1289 if (align
== (addressT
) -1)
1304 bss_alloc (symbolP
, size
, align
);
1309 pe_lcomm (int needs_align
)
1311 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1315 const pseudo_typeS md_pseudo_table
[] =
1317 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1318 {"align", s_align_bytes
, 0},
1320 {"align", s_align_ptwo
, 0},
1322 {"arch", set_cpu_arch
, 0},
1326 {"lcomm", pe_lcomm
, 1},
1328 {"ffloat", float_cons
, 'f'},
1329 {"dfloat", float_cons
, 'd'},
1330 {"tfloat", float_cons
, 'x'},
1332 {"slong", signed_cons
, 4},
1333 {"noopt", s_ignore
, 0},
1334 {"optim", s_ignore
, 0},
1335 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1336 {"code16", set_code_flag
, CODE_16BIT
},
1337 {"code32", set_code_flag
, CODE_32BIT
},
1339 {"code64", set_code_flag
, CODE_64BIT
},
1341 {"intel_syntax", set_intel_syntax
, 1},
1342 {"att_syntax", set_intel_syntax
, 0},
1343 {"intel_mnemonic", set_intel_mnemonic
, 1},
1344 {"att_mnemonic", set_intel_mnemonic
, 0},
1345 {"allow_index_reg", set_allow_index_reg
, 1},
1346 {"disallow_index_reg", set_allow_index_reg
, 0},
1347 {"sse_check", set_check
, 0},
1348 {"operand_check", set_check
, 1},
1349 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1350 {"largecomm", handle_large_common
, 0},
1352 {"file", dwarf2_directive_file
, 0},
1353 {"loc", dwarf2_directive_loc
, 0},
1354 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1357 {"secrel32", pe_directive_secrel
, 0},
1362 /* For interface with expression (). */
1363 extern char *input_line_pointer
;
1365 /* Hash table for instruction mnemonic lookup. */
1366 static struct hash_control
*op_hash
;
1368 /* Hash table for register lookup. */
1369 static struct hash_control
*reg_hash
;
1371 /* Various efficient no-op patterns for aligning code labels.
1372 Note: Don't try to assemble the instructions in the comments.
1373 0L and 0w are not legal. */
1374 static const unsigned char f32_1
[] =
1376 static const unsigned char f32_2
[] =
1377 {0x66,0x90}; /* xchg %ax,%ax */
1378 static const unsigned char f32_3
[] =
1379 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1380 static const unsigned char f32_4
[] =
1381 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1382 static const unsigned char f32_6
[] =
1383 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1384 static const unsigned char f32_7
[] =
1385 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1386 static const unsigned char f16_3
[] =
1387 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1388 static const unsigned char f16_4
[] =
1389 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1390 static const unsigned char jump_disp8
[] =
1391 {0xeb}; /* jmp disp8 */
1392 static const unsigned char jump32_disp32
[] =
1393 {0xe9}; /* jmp disp32 */
1394 static const unsigned char jump16_disp32
[] =
1395 {0x66,0xe9}; /* jmp disp32 */
1396 /* 32-bit NOPs patterns. */
1397 static const unsigned char *const f32_patt
[] = {
1398 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1400 /* 16-bit NOPs patterns. */
1401 static const unsigned char *const f16_patt
[] = {
1402 f32_1
, f32_2
, f16_3
, f16_4
1404 /* nopl (%[re]ax) */
1405 static const unsigned char alt_3
[] =
1407 /* nopl 0(%[re]ax) */
1408 static const unsigned char alt_4
[] =
1409 {0x0f,0x1f,0x40,0x00};
1410 /* nopl 0(%[re]ax,%[re]ax,1) */
1411 static const unsigned char alt_5
[] =
1412 {0x0f,0x1f,0x44,0x00,0x00};
1413 /* nopw 0(%[re]ax,%[re]ax,1) */
1414 static const unsigned char alt_6
[] =
1415 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1416 /* nopl 0L(%[re]ax) */
1417 static const unsigned char alt_7
[] =
1418 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1419 /* nopl 0L(%[re]ax,%[re]ax,1) */
1420 static const unsigned char alt_8
[] =
1421 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1422 /* nopw 0L(%[re]ax,%[re]ax,1) */
1423 static const unsigned char alt_9
[] =
1424 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1425 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1426 static const unsigned char alt_10
[] =
1427 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1428 /* data16 nopw %cs:0L(%eax,%eax,1) */
1429 static const unsigned char alt_11
[] =
1430 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1431 /* 32-bit and 64-bit NOPs patterns. */
1432 static const unsigned char *const alt_patt
[] = {
1433 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1434 alt_9
, alt_10
, alt_11
1437 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1438 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1441 i386_output_nops (char *where
, const unsigned char *const *patt
,
1442 int count
, int max_single_nop_size
)
1445 /* Place the longer NOP first. */
1448 const unsigned char *nops
;
1450 if (max_single_nop_size
< 1)
1452 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1453 max_single_nop_size
);
1457 nops
= patt
[max_single_nop_size
- 1];
1459 /* Use the smaller one if the requsted one isn't available. */
1462 max_single_nop_size
--;
1463 nops
= patt
[max_single_nop_size
- 1];
1466 last
= count
% max_single_nop_size
;
1469 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1470 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1474 nops
= patt
[last
- 1];
1477 /* Use the smaller one plus one-byte NOP if the needed one
1480 nops
= patt
[last
- 1];
1481 memcpy (where
+ offset
, nops
, last
);
1482 where
[offset
+ last
] = *patt
[0];
1485 memcpy (where
+ offset
, nops
, last
);
1490 fits_in_imm7 (offsetT num
)
1492 return (num
& 0x7f) == num
;
1496 fits_in_imm31 (offsetT num
)
1498 return (num
& 0x7fffffff) == num
;
1501 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1502 single NOP instruction LIMIT. */
1505 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1507 const unsigned char *const *patt
= NULL
;
1508 int max_single_nop_size
;
1509 /* Maximum number of NOPs before switching to jump over NOPs. */
1510 int max_number_of_nops
;
1512 switch (fragP
->fr_type
)
1517 case rs_machine_dependent
:
1518 /* Allow NOP padding for jumps and calls. */
1519 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1520 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1527 /* We need to decide which NOP sequence to use for 32bit and
1528 64bit. When -mtune= is used:
1530 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1531 PROCESSOR_GENERIC32, f32_patt will be used.
1532 2. For the rest, alt_patt will be used.
1534 When -mtune= isn't used, alt_patt will be used if
1535 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1538 When -march= or .arch is used, we can't use anything beyond
1539 cpu_arch_isa_flags. */
1541 if (flag_code
== CODE_16BIT
)
1544 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1545 /* Limit number of NOPs to 2 in 16-bit mode. */
1546 max_number_of_nops
= 2;
1550 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1552 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1553 switch (cpu_arch_tune
)
1555 case PROCESSOR_UNKNOWN
:
1556 /* We use cpu_arch_isa_flags to check if we SHOULD
1557 optimize with nops. */
1558 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1563 case PROCESSOR_PENTIUM4
:
1564 case PROCESSOR_NOCONA
:
1565 case PROCESSOR_CORE
:
1566 case PROCESSOR_CORE2
:
1567 case PROCESSOR_COREI7
:
1568 case PROCESSOR_L1OM
:
1569 case PROCESSOR_K1OM
:
1570 case PROCESSOR_GENERIC64
:
1572 case PROCESSOR_ATHLON
:
1574 case PROCESSOR_AMDFAM10
:
1576 case PROCESSOR_ZNVER
:
1580 case PROCESSOR_I386
:
1581 case PROCESSOR_I486
:
1582 case PROCESSOR_PENTIUM
:
1583 case PROCESSOR_PENTIUMPRO
:
1584 case PROCESSOR_IAMCU
:
1585 case PROCESSOR_GENERIC32
:
1592 switch (fragP
->tc_frag_data
.tune
)
1594 case PROCESSOR_UNKNOWN
:
1595 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1596 PROCESSOR_UNKNOWN. */
1600 case PROCESSOR_I386
:
1601 case PROCESSOR_I486
:
1602 case PROCESSOR_PENTIUM
:
1603 case PROCESSOR_IAMCU
:
1605 case PROCESSOR_ATHLON
:
1607 case PROCESSOR_AMDFAM10
:
1609 case PROCESSOR_ZNVER
:
1611 case PROCESSOR_GENERIC32
:
1612 /* We use cpu_arch_isa_flags to check if we CAN optimize
1614 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1619 case PROCESSOR_PENTIUMPRO
:
1620 case PROCESSOR_PENTIUM4
:
1621 case PROCESSOR_NOCONA
:
1622 case PROCESSOR_CORE
:
1623 case PROCESSOR_CORE2
:
1624 case PROCESSOR_COREI7
:
1625 case PROCESSOR_L1OM
:
1626 case PROCESSOR_K1OM
:
1627 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1632 case PROCESSOR_GENERIC64
:
1638 if (patt
== f32_patt
)
1640 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1641 /* Limit number of NOPs to 2 for older processors. */
1642 max_number_of_nops
= 2;
1646 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1647 /* Limit number of NOPs to 7 for newer processors. */
1648 max_number_of_nops
= 7;
1653 limit
= max_single_nop_size
;
1655 if (fragP
->fr_type
== rs_fill_nop
)
1657 /* Output NOPs for .nop directive. */
1658 if (limit
> max_single_nop_size
)
1660 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1661 _("invalid single nop size: %d "
1662 "(expect within [0, %d])"),
1663 limit
, max_single_nop_size
);
1667 else if (fragP
->fr_type
!= rs_machine_dependent
)
1668 fragP
->fr_var
= count
;
1670 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1672 /* Generate jump over NOPs. */
1673 offsetT disp
= count
- 2;
1674 if (fits_in_imm7 (disp
))
1676 /* Use "jmp disp8" if possible. */
1678 where
[0] = jump_disp8
[0];
1684 unsigned int size_of_jump
;
1686 if (flag_code
== CODE_16BIT
)
1688 where
[0] = jump16_disp32
[0];
1689 where
[1] = jump16_disp32
[1];
1694 where
[0] = jump32_disp32
[0];
1698 count
-= size_of_jump
+ 4;
1699 if (!fits_in_imm31 (count
))
1701 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1702 _("jump over nop padding out of range"));
1706 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1707 where
+= size_of_jump
+ 4;
1711 /* Generate multiple NOPs. */
1712 i386_output_nops (where
, patt
, count
, limit
);
1716 operand_type_all_zero (const union i386_operand_type
*x
)
1718 switch (ARRAY_SIZE(x
->array
))
1729 return !x
->array
[0];
1736 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1738 switch (ARRAY_SIZE(x
->array
))
1754 x
->bitfield
.class = ClassNone
;
1755 x
->bitfield
.instance
= InstanceNone
;
1759 operand_type_equal (const union i386_operand_type
*x
,
1760 const union i386_operand_type
*y
)
1762 switch (ARRAY_SIZE(x
->array
))
1765 if (x
->array
[2] != y
->array
[2])
1769 if (x
->array
[1] != y
->array
[1])
1773 return x
->array
[0] == y
->array
[0];
1781 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1783 switch (ARRAY_SIZE(x
->array
))
1798 return !x
->array
[0];
1805 cpu_flags_equal (const union i386_cpu_flags
*x
,
1806 const union i386_cpu_flags
*y
)
1808 switch (ARRAY_SIZE(x
->array
))
1811 if (x
->array
[3] != y
->array
[3])
1815 if (x
->array
[2] != y
->array
[2])
1819 if (x
->array
[1] != y
->array
[1])
1823 return x
->array
[0] == y
->array
[0];
1831 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1833 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1834 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1837 static INLINE i386_cpu_flags
1838 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1840 switch (ARRAY_SIZE (x
.array
))
1843 x
.array
[3] &= y
.array
[3];
1846 x
.array
[2] &= y
.array
[2];
1849 x
.array
[1] &= y
.array
[1];
1852 x
.array
[0] &= y
.array
[0];
1860 static INLINE i386_cpu_flags
1861 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1863 switch (ARRAY_SIZE (x
.array
))
1866 x
.array
[3] |= y
.array
[3];
1869 x
.array
[2] |= y
.array
[2];
1872 x
.array
[1] |= y
.array
[1];
1875 x
.array
[0] |= y
.array
[0];
1883 static INLINE i386_cpu_flags
1884 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1886 switch (ARRAY_SIZE (x
.array
))
1889 x
.array
[3] &= ~y
.array
[3];
1892 x
.array
[2] &= ~y
.array
[2];
1895 x
.array
[1] &= ~y
.array
[1];
1898 x
.array
[0] &= ~y
.array
[0];
1906 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1908 #define CPU_FLAGS_ARCH_MATCH 0x1
1909 #define CPU_FLAGS_64BIT_MATCH 0x2
1911 #define CPU_FLAGS_PERFECT_MATCH \
1912 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1914 /* Return CPU flags match bits. */
1917 cpu_flags_match (const insn_template
*t
)
1919 i386_cpu_flags x
= t
->cpu_flags
;
1920 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1922 x
.bitfield
.cpu64
= 0;
1923 x
.bitfield
.cpuno64
= 0;
1925 if (cpu_flags_all_zero (&x
))
1927 /* This instruction is available on all archs. */
1928 match
|= CPU_FLAGS_ARCH_MATCH
;
1932 /* This instruction is available only on some archs. */
1933 i386_cpu_flags cpu
= cpu_arch_flags
;
1935 /* AVX512VL is no standalone feature - match it and then strip it. */
1936 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1938 x
.bitfield
.cpuavx512vl
= 0;
1940 cpu
= cpu_flags_and (x
, cpu
);
1941 if (!cpu_flags_all_zero (&cpu
))
1943 if (x
.bitfield
.cpuavx
)
1945 /* We need to check a few extra flags with AVX. */
1946 if (cpu
.bitfield
.cpuavx
1947 && (!t
->opcode_modifier
.sse2avx
1948 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1949 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1950 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1951 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1952 match
|= CPU_FLAGS_ARCH_MATCH
;
1954 else if (x
.bitfield
.cpuavx512f
)
1956 /* We need to check a few extra flags with AVX512F. */
1957 if (cpu
.bitfield
.cpuavx512f
1958 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1959 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1960 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1961 match
|= CPU_FLAGS_ARCH_MATCH
;
1964 match
|= CPU_FLAGS_ARCH_MATCH
;
1970 static INLINE i386_operand_type
1971 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1973 if (x
.bitfield
.class != y
.bitfield
.class)
1974 x
.bitfield
.class = ClassNone
;
1975 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1976 x
.bitfield
.instance
= InstanceNone
;
1978 switch (ARRAY_SIZE (x
.array
))
1981 x
.array
[2] &= y
.array
[2];
1984 x
.array
[1] &= y
.array
[1];
1987 x
.array
[0] &= y
.array
[0];
1995 static INLINE i386_operand_type
1996 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1998 gas_assert (y
.bitfield
.class == ClassNone
);
1999 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2001 switch (ARRAY_SIZE (x
.array
))
2004 x
.array
[2] &= ~y
.array
[2];
2007 x
.array
[1] &= ~y
.array
[1];
2010 x
.array
[0] &= ~y
.array
[0];
2018 static INLINE i386_operand_type
2019 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2021 gas_assert (x
.bitfield
.class == ClassNone
||
2022 y
.bitfield
.class == ClassNone
||
2023 x
.bitfield
.class == y
.bitfield
.class);
2024 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2025 y
.bitfield
.instance
== InstanceNone
||
2026 x
.bitfield
.instance
== y
.bitfield
.instance
);
2028 switch (ARRAY_SIZE (x
.array
))
2031 x
.array
[2] |= y
.array
[2];
2034 x
.array
[1] |= y
.array
[1];
2037 x
.array
[0] |= y
.array
[0];
2045 static INLINE i386_operand_type
2046 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2048 gas_assert (y
.bitfield
.class == ClassNone
);
2049 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2051 switch (ARRAY_SIZE (x
.array
))
2054 x
.array
[2] ^= y
.array
[2];
2057 x
.array
[1] ^= y
.array
[1];
2060 x
.array
[0] ^= y
.array
[0];
2068 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2069 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2070 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2071 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2072 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2073 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2074 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2075 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2076 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2077 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2078 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2079 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2080 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2081 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2082 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2083 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2084 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2095 operand_type_check (i386_operand_type t
, enum operand_type c
)
2100 return t
.bitfield
.class == Reg
;
2103 return (t
.bitfield
.imm8
2107 || t
.bitfield
.imm32s
2108 || t
.bitfield
.imm64
);
2111 return (t
.bitfield
.disp8
2112 || t
.bitfield
.disp16
2113 || t
.bitfield
.disp32
2114 || t
.bitfield
.disp32s
2115 || t
.bitfield
.disp64
);
2118 return (t
.bitfield
.disp8
2119 || t
.bitfield
.disp16
2120 || t
.bitfield
.disp32
2121 || t
.bitfield
.disp32s
2122 || t
.bitfield
.disp64
2123 || t
.bitfield
.baseindex
);
2132 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2133 between operand GIVEN and opeand WANTED for instruction template T. */
2136 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2139 return !((i
.types
[given
].bitfield
.byte
2140 && !t
->operand_types
[wanted
].bitfield
.byte
)
2141 || (i
.types
[given
].bitfield
.word
2142 && !t
->operand_types
[wanted
].bitfield
.word
)
2143 || (i
.types
[given
].bitfield
.dword
2144 && !t
->operand_types
[wanted
].bitfield
.dword
)
2145 || (i
.types
[given
].bitfield
.qword
2146 && !t
->operand_types
[wanted
].bitfield
.qword
)
2147 || (i
.types
[given
].bitfield
.tbyte
2148 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2151 /* Return 1 if there is no conflict in SIMD register between operand
2152 GIVEN and opeand WANTED for instruction template T. */
2155 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2158 return !((i
.types
[given
].bitfield
.xmmword
2159 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2160 || (i
.types
[given
].bitfield
.ymmword
2161 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2162 || (i
.types
[given
].bitfield
.zmmword
2163 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2166 /* Return 1 if there is no conflict in any size between operand GIVEN
2167 and opeand WANTED for instruction template T. */
2170 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2173 return (match_operand_size (t
, wanted
, given
)
2174 && !((i
.types
[given
].bitfield
.unspecified
2176 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2177 || (i
.types
[given
].bitfield
.fword
2178 && !t
->operand_types
[wanted
].bitfield
.fword
)
2179 /* For scalar opcode templates to allow register and memory
2180 operands at the same time, some special casing is needed
2181 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2182 down-conversion vpmov*. */
2183 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2184 && t
->operand_types
[wanted
].bitfield
.byte
2185 + t
->operand_types
[wanted
].bitfield
.word
2186 + t
->operand_types
[wanted
].bitfield
.dword
2187 + t
->operand_types
[wanted
].bitfield
.qword
2188 > !!t
->opcode_modifier
.broadcast
)
2189 ? (i
.types
[given
].bitfield
.xmmword
2190 || i
.types
[given
].bitfield
.ymmword
2191 || i
.types
[given
].bitfield
.zmmword
)
2192 : !match_simd_size(t
, wanted
, given
))));
2195 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2196 operands for instruction template T, and it has MATCH_REVERSE set if there
2197 is no size conflict on any operands for the template with operands reversed
2198 (and the template allows for reversing in the first place). */
2200 #define MATCH_STRAIGHT 1
2201 #define MATCH_REVERSE 2
2203 static INLINE
unsigned int
2204 operand_size_match (const insn_template
*t
)
2206 unsigned int j
, match
= MATCH_STRAIGHT
;
2208 /* Don't check non-absolute jump instructions. */
2209 if (t
->opcode_modifier
.jump
2210 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2213 /* Check memory and accumulator operand size. */
2214 for (j
= 0; j
< i
.operands
; j
++)
2216 if (i
.types
[j
].bitfield
.class != Reg
2217 && i
.types
[j
].bitfield
.class != RegSIMD
2218 && t
->opcode_modifier
.anysize
)
2221 if (t
->operand_types
[j
].bitfield
.class == Reg
2222 && !match_operand_size (t
, j
, j
))
2228 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2229 && !match_simd_size (t
, j
, j
))
2235 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2236 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2242 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2249 if (!t
->opcode_modifier
.d
)
2253 i
.error
= operand_size_mismatch
;
2257 /* Check reverse. */
2258 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2260 for (j
= 0; j
< i
.operands
; j
++)
2262 unsigned int given
= i
.operands
- j
- 1;
2264 if (t
->operand_types
[j
].bitfield
.class == Reg
2265 && !match_operand_size (t
, j
, given
))
2268 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2269 && !match_simd_size (t
, j
, given
))
2272 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2273 && (!match_operand_size (t
, j
, given
)
2274 || !match_simd_size (t
, j
, given
)))
2277 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2281 return match
| MATCH_REVERSE
;
2285 operand_type_match (i386_operand_type overlap
,
2286 i386_operand_type given
)
2288 i386_operand_type temp
= overlap
;
2290 temp
.bitfield
.unspecified
= 0;
2291 temp
.bitfield
.byte
= 0;
2292 temp
.bitfield
.word
= 0;
2293 temp
.bitfield
.dword
= 0;
2294 temp
.bitfield
.fword
= 0;
2295 temp
.bitfield
.qword
= 0;
2296 temp
.bitfield
.tbyte
= 0;
2297 temp
.bitfield
.xmmword
= 0;
2298 temp
.bitfield
.ymmword
= 0;
2299 temp
.bitfield
.zmmword
= 0;
2300 if (operand_type_all_zero (&temp
))
2303 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2307 i
.error
= operand_type_mismatch
;
2311 /* If given types g0 and g1 are registers they must be of the same type
2312 unless the expected operand type register overlap is null.
2313 Some Intel syntax memory operand size checking also happens here. */
2316 operand_type_register_match (i386_operand_type g0
,
2317 i386_operand_type t0
,
2318 i386_operand_type g1
,
2319 i386_operand_type t1
)
2321 if (g0
.bitfield
.class != Reg
2322 && g0
.bitfield
.class != RegSIMD
2323 && (!operand_type_check (g0
, anymem
)
2324 || g0
.bitfield
.unspecified
2325 || (t0
.bitfield
.class != Reg
2326 && t0
.bitfield
.class != RegSIMD
)))
2329 if (g1
.bitfield
.class != Reg
2330 && g1
.bitfield
.class != RegSIMD
2331 && (!operand_type_check (g1
, anymem
)
2332 || g1
.bitfield
.unspecified
2333 || (t1
.bitfield
.class != Reg
2334 && t1
.bitfield
.class != RegSIMD
)))
2337 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2338 && g0
.bitfield
.word
== g1
.bitfield
.word
2339 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2340 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2341 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2342 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2343 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2346 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2347 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2348 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2349 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2350 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2351 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2352 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2355 i
.error
= register_type_mismatch
;
2360 static INLINE
unsigned int
2361 register_number (const reg_entry
*r
)
2363 unsigned int nr
= r
->reg_num
;
2365 if (r
->reg_flags
& RegRex
)
2368 if (r
->reg_flags
& RegVRex
)
2374 static INLINE
unsigned int
2375 mode_from_disp_size (i386_operand_type t
)
2377 if (t
.bitfield
.disp8
)
2379 else if (t
.bitfield
.disp16
2380 || t
.bitfield
.disp32
2381 || t
.bitfield
.disp32s
)
2388 fits_in_signed_byte (addressT num
)
2390 return num
+ 0x80 <= 0xff;
2394 fits_in_unsigned_byte (addressT num
)
2400 fits_in_unsigned_word (addressT num
)
2402 return num
<= 0xffff;
2406 fits_in_signed_word (addressT num
)
2408 return num
+ 0x8000 <= 0xffff;
2412 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2417 return num
+ 0x80000000 <= 0xffffffff;
2419 } /* fits_in_signed_long() */
2422 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2427 return num
<= 0xffffffff;
2429 } /* fits_in_unsigned_long() */
2432 fits_in_disp8 (offsetT num
)
2434 int shift
= i
.memshift
;
2440 mask
= (1 << shift
) - 1;
2442 /* Return 0 if NUM isn't properly aligned. */
2446 /* Check if NUM will fit in 8bit after shift. */
2447 return fits_in_signed_byte (num
>> shift
);
2451 fits_in_imm4 (offsetT num
)
2453 return (num
& 0xf) == num
;
2456 static i386_operand_type
2457 smallest_imm_type (offsetT num
)
2459 i386_operand_type t
;
2461 operand_type_set (&t
, 0);
2462 t
.bitfield
.imm64
= 1;
2464 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2466 /* This code is disabled on the 486 because all the Imm1 forms
2467 in the opcode table are slower on the i486. They're the
2468 versions with the implicitly specified single-position
2469 displacement, which has another syntax if you really want to
2471 t
.bitfield
.imm1
= 1;
2472 t
.bitfield
.imm8
= 1;
2473 t
.bitfield
.imm8s
= 1;
2474 t
.bitfield
.imm16
= 1;
2475 t
.bitfield
.imm32
= 1;
2476 t
.bitfield
.imm32s
= 1;
2478 else if (fits_in_signed_byte (num
))
2480 t
.bitfield
.imm8
= 1;
2481 t
.bitfield
.imm8s
= 1;
2482 t
.bitfield
.imm16
= 1;
2483 t
.bitfield
.imm32
= 1;
2484 t
.bitfield
.imm32s
= 1;
2486 else if (fits_in_unsigned_byte (num
))
2488 t
.bitfield
.imm8
= 1;
2489 t
.bitfield
.imm16
= 1;
2490 t
.bitfield
.imm32
= 1;
2491 t
.bitfield
.imm32s
= 1;
2493 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2495 t
.bitfield
.imm16
= 1;
2496 t
.bitfield
.imm32
= 1;
2497 t
.bitfield
.imm32s
= 1;
2499 else if (fits_in_signed_long (num
))
2501 t
.bitfield
.imm32
= 1;
2502 t
.bitfield
.imm32s
= 1;
2504 else if (fits_in_unsigned_long (num
))
2505 t
.bitfield
.imm32
= 1;
2511 offset_in_range (offsetT val
, int size
)
2517 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2518 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2519 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2521 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2527 /* If BFD64, sign extend val for 32bit address mode. */
2528 if (flag_code
!= CODE_64BIT
2529 || i
.prefix
[ADDR_PREFIX
])
2530 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2531 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2534 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2536 char buf1
[40], buf2
[40];
2538 sprint_value (buf1
, val
);
2539 sprint_value (buf2
, val
& mask
);
2540 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2555 a. PREFIX_EXIST if attempting to add a prefix where one from the
2556 same class already exists.
2557 b. PREFIX_LOCK if lock prefix is added.
2558 c. PREFIX_REP if rep/repne prefix is added.
2559 d. PREFIX_DS if ds prefix is added.
2560 e. PREFIX_OTHER if other prefix is added.
2563 static enum PREFIX_GROUP
2564 add_prefix (unsigned int prefix
)
2566 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2569 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2570 && flag_code
== CODE_64BIT
)
2572 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2573 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2574 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2575 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2586 case DS_PREFIX_OPCODE
:
2589 case CS_PREFIX_OPCODE
:
2590 case ES_PREFIX_OPCODE
:
2591 case FS_PREFIX_OPCODE
:
2592 case GS_PREFIX_OPCODE
:
2593 case SS_PREFIX_OPCODE
:
2597 case REPNE_PREFIX_OPCODE
:
2598 case REPE_PREFIX_OPCODE
:
2603 case LOCK_PREFIX_OPCODE
:
2612 case ADDR_PREFIX_OPCODE
:
2616 case DATA_PREFIX_OPCODE
:
2620 if (i
.prefix
[q
] != 0)
2628 i
.prefix
[q
] |= prefix
;
2631 as_bad (_("same type of prefix used twice"));
2637 update_code_flag (int value
, int check
)
2639 PRINTF_LIKE ((*as_error
));
2641 flag_code
= (enum flag_code
) value
;
2642 if (flag_code
== CODE_64BIT
)
2644 cpu_arch_flags
.bitfield
.cpu64
= 1;
2645 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2649 cpu_arch_flags
.bitfield
.cpu64
= 0;
2650 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2652 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2655 as_error
= as_fatal
;
2658 (*as_error
) (_("64bit mode not supported on `%s'."),
2659 cpu_arch_name
? cpu_arch_name
: default_arch
);
2661 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2664 as_error
= as_fatal
;
2667 (*as_error
) (_("32bit mode not supported on `%s'."),
2668 cpu_arch_name
? cpu_arch_name
: default_arch
);
2670 stackop_size
= '\0';
2674 set_code_flag (int value
)
2676 update_code_flag (value
, 0);
2680 set_16bit_gcc_code_flag (int new_code_flag
)
2682 flag_code
= (enum flag_code
) new_code_flag
;
2683 if (flag_code
!= CODE_16BIT
)
2685 cpu_arch_flags
.bitfield
.cpu64
= 0;
2686 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2687 stackop_size
= LONG_MNEM_SUFFIX
;
2691 set_intel_syntax (int syntax_flag
)
2693 /* Find out if register prefixing is specified. */
2694 int ask_naked_reg
= 0;
2697 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2700 int e
= get_symbol_name (&string
);
2702 if (strcmp (string
, "prefix") == 0)
2704 else if (strcmp (string
, "noprefix") == 0)
2707 as_bad (_("bad argument to syntax directive."));
2708 (void) restore_line_pointer (e
);
2710 demand_empty_rest_of_line ();
2712 intel_syntax
= syntax_flag
;
2714 if (ask_naked_reg
== 0)
2715 allow_naked_reg
= (intel_syntax
2716 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2718 allow_naked_reg
= (ask_naked_reg
< 0);
2720 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2722 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2723 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2724 register_prefix
= allow_naked_reg
? "" : "%";
2728 set_intel_mnemonic (int mnemonic_flag
)
2730 intel_mnemonic
= mnemonic_flag
;
2734 set_allow_index_reg (int flag
)
2736 allow_index_reg
= flag
;
2740 set_check (int what
)
2742 enum check_kind
*kind
;
2747 kind
= &operand_check
;
2758 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2761 int e
= get_symbol_name (&string
);
2763 if (strcmp (string
, "none") == 0)
2765 else if (strcmp (string
, "warning") == 0)
2766 *kind
= check_warning
;
2767 else if (strcmp (string
, "error") == 0)
2768 *kind
= check_error
;
2770 as_bad (_("bad argument to %s_check directive."), str
);
2771 (void) restore_line_pointer (e
);
2774 as_bad (_("missing argument for %s_check directive"), str
);
2776 demand_empty_rest_of_line ();
2780 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2781 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2783 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2784 static const char *arch
;
2786 /* Intel LIOM is only supported on ELF. */
2792 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2793 use default_arch. */
2794 arch
= cpu_arch_name
;
2796 arch
= default_arch
;
2799 /* If we are targeting Intel MCU, we must enable it. */
2800 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2801 || new_flag
.bitfield
.cpuiamcu
)
2804 /* If we are targeting Intel L1OM, we must enable it. */
2805 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2806 || new_flag
.bitfield
.cpul1om
)
2809 /* If we are targeting Intel K1OM, we must enable it. */
2810 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2811 || new_flag
.bitfield
.cpuk1om
)
2814 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2819 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2823 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2826 int e
= get_symbol_name (&string
);
2828 i386_cpu_flags flags
;
2830 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2832 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2834 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2838 cpu_arch_name
= cpu_arch
[j
].name
;
2839 cpu_sub_arch_name
= NULL
;
2840 cpu_arch_flags
= cpu_arch
[j
].flags
;
2841 if (flag_code
== CODE_64BIT
)
2843 cpu_arch_flags
.bitfield
.cpu64
= 1;
2844 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2848 cpu_arch_flags
.bitfield
.cpu64
= 0;
2849 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2851 cpu_arch_isa
= cpu_arch
[j
].type
;
2852 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2853 if (!cpu_arch_tune_set
)
2855 cpu_arch_tune
= cpu_arch_isa
;
2856 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2861 flags
= cpu_flags_or (cpu_arch_flags
,
2864 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2866 if (cpu_sub_arch_name
)
2868 char *name
= cpu_sub_arch_name
;
2869 cpu_sub_arch_name
= concat (name
,
2871 (const char *) NULL
);
2875 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2876 cpu_arch_flags
= flags
;
2877 cpu_arch_isa_flags
= flags
;
2881 = cpu_flags_or (cpu_arch_isa_flags
,
2883 (void) restore_line_pointer (e
);
2884 demand_empty_rest_of_line ();
2889 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2891 /* Disable an ISA extension. */
2892 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2893 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2895 flags
= cpu_flags_and_not (cpu_arch_flags
,
2896 cpu_noarch
[j
].flags
);
2897 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2899 if (cpu_sub_arch_name
)
2901 char *name
= cpu_sub_arch_name
;
2902 cpu_sub_arch_name
= concat (name
, string
,
2903 (const char *) NULL
);
2907 cpu_sub_arch_name
= xstrdup (string
);
2908 cpu_arch_flags
= flags
;
2909 cpu_arch_isa_flags
= flags
;
2911 (void) restore_line_pointer (e
);
2912 demand_empty_rest_of_line ();
2916 j
= ARRAY_SIZE (cpu_arch
);
2919 if (j
>= ARRAY_SIZE (cpu_arch
))
2920 as_bad (_("no such architecture: `%s'"), string
);
2922 *input_line_pointer
= e
;
2925 as_bad (_("missing cpu architecture"));
2927 no_cond_jump_promotion
= 0;
2928 if (*input_line_pointer
== ','
2929 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2934 ++input_line_pointer
;
2935 e
= get_symbol_name (&string
);
2937 if (strcmp (string
, "nojumps") == 0)
2938 no_cond_jump_promotion
= 1;
2939 else if (strcmp (string
, "jumps") == 0)
2942 as_bad (_("no such architecture modifier: `%s'"), string
);
2944 (void) restore_line_pointer (e
);
2947 demand_empty_rest_of_line ();
2950 enum bfd_architecture
2953 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2955 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2956 || flag_code
!= CODE_64BIT
)
2957 as_fatal (_("Intel L1OM is 64bit ELF only"));
2958 return bfd_arch_l1om
;
2960 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2962 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2963 || flag_code
!= CODE_64BIT
)
2964 as_fatal (_("Intel K1OM is 64bit ELF only"));
2965 return bfd_arch_k1om
;
2967 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2969 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2970 || flag_code
== CODE_64BIT
)
2971 as_fatal (_("Intel MCU is 32bit ELF only"));
2972 return bfd_arch_iamcu
;
2975 return bfd_arch_i386
;
2981 if (!strncmp (default_arch
, "x86_64", 6))
2983 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2985 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2986 || default_arch
[6] != '\0')
2987 as_fatal (_("Intel L1OM is 64bit ELF only"));
2988 return bfd_mach_l1om
;
2990 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2992 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2993 || default_arch
[6] != '\0')
2994 as_fatal (_("Intel K1OM is 64bit ELF only"));
2995 return bfd_mach_k1om
;
2997 else if (default_arch
[6] == '\0')
2998 return bfd_mach_x86_64
;
3000 return bfd_mach_x64_32
;
3002 else if (!strcmp (default_arch
, "i386")
3003 || !strcmp (default_arch
, "iamcu"))
3005 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3007 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3008 as_fatal (_("Intel MCU is 32bit ELF only"));
3009 return bfd_mach_i386_iamcu
;
3012 return bfd_mach_i386_i386
;
3015 as_fatal (_("unknown architecture"));
3021 const char *hash_err
;
3023 /* Support pseudo prefixes like {disp32}. */
3024 lex_type
['{'] = LEX_BEGIN_NAME
;
3026 /* Initialize op_hash hash table. */
3027 op_hash
= hash_new ();
3030 const insn_template
*optab
;
3031 templates
*core_optab
;
3033 /* Setup for loop. */
3035 core_optab
= XNEW (templates
);
3036 core_optab
->start
= optab
;
3041 if (optab
->name
== NULL
3042 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3044 /* different name --> ship out current template list;
3045 add to hash table; & begin anew. */
3046 core_optab
->end
= optab
;
3047 hash_err
= hash_insert (op_hash
,
3049 (void *) core_optab
);
3052 as_fatal (_("can't hash %s: %s"),
3056 if (optab
->name
== NULL
)
3058 core_optab
= XNEW (templates
);
3059 core_optab
->start
= optab
;
3064 /* Initialize reg_hash hash table. */
3065 reg_hash
= hash_new ();
3067 const reg_entry
*regtab
;
3068 unsigned int regtab_size
= i386_regtab_size
;
3070 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3072 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3074 as_fatal (_("can't hash %s: %s"),
3080 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3085 for (c
= 0; c
< 256; c
++)
3090 mnemonic_chars
[c
] = c
;
3091 register_chars
[c
] = c
;
3092 operand_chars
[c
] = c
;
3094 else if (ISLOWER (c
))
3096 mnemonic_chars
[c
] = c
;
3097 register_chars
[c
] = c
;
3098 operand_chars
[c
] = c
;
3100 else if (ISUPPER (c
))
3102 mnemonic_chars
[c
] = TOLOWER (c
);
3103 register_chars
[c
] = mnemonic_chars
[c
];
3104 operand_chars
[c
] = c
;
3106 else if (c
== '{' || c
== '}')
3108 mnemonic_chars
[c
] = c
;
3109 operand_chars
[c
] = c
;
3112 if (ISALPHA (c
) || ISDIGIT (c
))
3113 identifier_chars
[c
] = c
;
3116 identifier_chars
[c
] = c
;
3117 operand_chars
[c
] = c
;
3122 identifier_chars
['@'] = '@';
3125 identifier_chars
['?'] = '?';
3126 operand_chars
['?'] = '?';
3128 digit_chars
['-'] = '-';
3129 mnemonic_chars
['_'] = '_';
3130 mnemonic_chars
['-'] = '-';
3131 mnemonic_chars
['.'] = '.';
3132 identifier_chars
['_'] = '_';
3133 identifier_chars
['.'] = '.';
3135 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3136 operand_chars
[(unsigned char) *p
] = *p
;
3139 if (flag_code
== CODE_64BIT
)
3141 #if defined (OBJ_COFF) && defined (TE_PE)
3142 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3145 x86_dwarf2_return_column
= 16;
3147 x86_cie_data_alignment
= -8;
3151 x86_dwarf2_return_column
= 8;
3152 x86_cie_data_alignment
= -4;
3155 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3156 can be turned into BRANCH_PREFIX frag. */
3157 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3162 i386_print_statistics (FILE *file
)
3164 hash_print_statistics (file
, "i386 opcode", op_hash
);
3165 hash_print_statistics (file
, "i386 register", reg_hash
);
3170 /* Debugging routines for md_assemble. */
3171 static void pte (insn_template
*);
3172 static void pt (i386_operand_type
);
3173 static void pe (expressionS
*);
3174 static void ps (symbolS
*);
3177 pi (const char *line
, i386_insn
*x
)
3181 fprintf (stdout
, "%s: template ", line
);
3183 fprintf (stdout
, " address: base %s index %s scale %x\n",
3184 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3185 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3186 x
->log2_scale_factor
);
3187 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3188 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3189 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3190 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3191 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3192 (x
->rex
& REX_W
) != 0,
3193 (x
->rex
& REX_R
) != 0,
3194 (x
->rex
& REX_X
) != 0,
3195 (x
->rex
& REX_B
) != 0);
3196 for (j
= 0; j
< x
->operands
; j
++)
3198 fprintf (stdout
, " #%d: ", j
+ 1);
3200 fprintf (stdout
, "\n");
3201 if (x
->types
[j
].bitfield
.class == Reg
3202 || x
->types
[j
].bitfield
.class == RegMMX
3203 || x
->types
[j
].bitfield
.class == RegSIMD
3204 || x
->types
[j
].bitfield
.class == RegMask
3205 || x
->types
[j
].bitfield
.class == SReg
3206 || x
->types
[j
].bitfield
.class == RegCR
3207 || x
->types
[j
].bitfield
.class == RegDR
3208 || x
->types
[j
].bitfield
.class == RegTR
3209 || x
->types
[j
].bitfield
.class == RegBND
)
3210 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3211 if (operand_type_check (x
->types
[j
], imm
))
3213 if (operand_type_check (x
->types
[j
], disp
))
3214 pe (x
->op
[j
].disps
);
3219 pte (insn_template
*t
)
3222 fprintf (stdout
, " %d operands ", t
->operands
);
3223 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3224 if (t
->extension_opcode
!= None
)
3225 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3226 if (t
->opcode_modifier
.d
)
3227 fprintf (stdout
, "D");
3228 if (t
->opcode_modifier
.w
)
3229 fprintf (stdout
, "W");
3230 fprintf (stdout
, "\n");
3231 for (j
= 0; j
< t
->operands
; j
++)
3233 fprintf (stdout
, " #%d type ", j
+ 1);
3234 pt (t
->operand_types
[j
]);
3235 fprintf (stdout
, "\n");
3242 fprintf (stdout
, " operation %d\n", e
->X_op
);
3243 fprintf (stdout
, " add_number %ld (%lx)\n",
3244 (long) e
->X_add_number
, (long) e
->X_add_number
);
3245 if (e
->X_add_symbol
)
3247 fprintf (stdout
, " add_symbol ");
3248 ps (e
->X_add_symbol
);
3249 fprintf (stdout
, "\n");
3253 fprintf (stdout
, " op_symbol ");
3254 ps (e
->X_op_symbol
);
3255 fprintf (stdout
, "\n");
3262 fprintf (stdout
, "%s type %s%s",
3264 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3265 segment_name (S_GET_SEGMENT (s
)));
3268 static struct type_name
3270 i386_operand_type mask
;
3273 const type_names
[] =
3275 { OPERAND_TYPE_REG8
, "r8" },
3276 { OPERAND_TYPE_REG16
, "r16" },
3277 { OPERAND_TYPE_REG32
, "r32" },
3278 { OPERAND_TYPE_REG64
, "r64" },
3279 { OPERAND_TYPE_ACC8
, "acc8" },
3280 { OPERAND_TYPE_ACC16
, "acc16" },
3281 { OPERAND_TYPE_ACC32
, "acc32" },
3282 { OPERAND_TYPE_ACC64
, "acc64" },
3283 { OPERAND_TYPE_IMM8
, "i8" },
3284 { OPERAND_TYPE_IMM8
, "i8s" },
3285 { OPERAND_TYPE_IMM16
, "i16" },
3286 { OPERAND_TYPE_IMM32
, "i32" },
3287 { OPERAND_TYPE_IMM32S
, "i32s" },
3288 { OPERAND_TYPE_IMM64
, "i64" },
3289 { OPERAND_TYPE_IMM1
, "i1" },
3290 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3291 { OPERAND_TYPE_DISP8
, "d8" },
3292 { OPERAND_TYPE_DISP16
, "d16" },
3293 { OPERAND_TYPE_DISP32
, "d32" },
3294 { OPERAND_TYPE_DISP32S
, "d32s" },
3295 { OPERAND_TYPE_DISP64
, "d64" },
3296 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3297 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3298 { OPERAND_TYPE_CONTROL
, "control reg" },
3299 { OPERAND_TYPE_TEST
, "test reg" },
3300 { OPERAND_TYPE_DEBUG
, "debug reg" },
3301 { OPERAND_TYPE_FLOATREG
, "FReg" },
3302 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3303 { OPERAND_TYPE_SREG
, "SReg" },
3304 { OPERAND_TYPE_REGMMX
, "rMMX" },
3305 { OPERAND_TYPE_REGXMM
, "rXMM" },
3306 { OPERAND_TYPE_REGYMM
, "rYMM" },
3307 { OPERAND_TYPE_REGZMM
, "rZMM" },
3308 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3312 pt (i386_operand_type t
)
3315 i386_operand_type a
;
3317 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3319 a
= operand_type_and (t
, type_names
[j
].mask
);
3320 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3321 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3326 #endif /* DEBUG386 */
3328 static bfd_reloc_code_real_type
3329 reloc (unsigned int size
,
3332 bfd_reloc_code_real_type other
)
3334 if (other
!= NO_RELOC
)
3336 reloc_howto_type
*rel
;
3341 case BFD_RELOC_X86_64_GOT32
:
3342 return BFD_RELOC_X86_64_GOT64
;
3344 case BFD_RELOC_X86_64_GOTPLT64
:
3345 return BFD_RELOC_X86_64_GOTPLT64
;
3347 case BFD_RELOC_X86_64_PLTOFF64
:
3348 return BFD_RELOC_X86_64_PLTOFF64
;
3350 case BFD_RELOC_X86_64_GOTPC32
:
3351 other
= BFD_RELOC_X86_64_GOTPC64
;
3353 case BFD_RELOC_X86_64_GOTPCREL
:
3354 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3356 case BFD_RELOC_X86_64_TPOFF32
:
3357 other
= BFD_RELOC_X86_64_TPOFF64
;
3359 case BFD_RELOC_X86_64_DTPOFF32
:
3360 other
= BFD_RELOC_X86_64_DTPOFF64
;
3366 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3367 if (other
== BFD_RELOC_SIZE32
)
3370 other
= BFD_RELOC_SIZE64
;
3373 as_bad (_("there are no pc-relative size relocations"));
3379 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3380 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3383 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3385 as_bad (_("unknown relocation (%u)"), other
);
3386 else if (size
!= bfd_get_reloc_size (rel
))
3387 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3388 bfd_get_reloc_size (rel
),
3390 else if (pcrel
&& !rel
->pc_relative
)
3391 as_bad (_("non-pc-relative relocation for pc-relative field"));
3392 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3394 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3396 as_bad (_("relocated field and relocation type differ in signedness"));
3405 as_bad (_("there are no unsigned pc-relative relocations"));
3408 case 1: return BFD_RELOC_8_PCREL
;
3409 case 2: return BFD_RELOC_16_PCREL
;
3410 case 4: return BFD_RELOC_32_PCREL
;
3411 case 8: return BFD_RELOC_64_PCREL
;
3413 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3420 case 4: return BFD_RELOC_X86_64_32S
;
3425 case 1: return BFD_RELOC_8
;
3426 case 2: return BFD_RELOC_16
;
3427 case 4: return BFD_RELOC_32
;
3428 case 8: return BFD_RELOC_64
;
3430 as_bad (_("cannot do %s %u byte relocation"),
3431 sign
> 0 ? "signed" : "unsigned", size
);
3437 /* Here we decide which fixups can be adjusted to make them relative to
3438 the beginning of the section instead of the symbol. Basically we need
3439 to make sure that the dynamic relocations are done correctly, so in
3440 some cases we force the original symbol to be used. */
3443 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3449 /* Don't adjust pc-relative references to merge sections in 64-bit
3451 if (use_rela_relocations
3452 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3456 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3457 and changed later by validate_fix. */
3458 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3459 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3462 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3463 for size relocations. */
3464 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3465 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3466 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3467 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3468 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3473 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3474 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3475 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3478 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3492 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3493 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3494 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3501 intel_float_operand (const char *mnemonic
)
3503 /* Note that the value returned is meaningful only for opcodes with (memory)
3504 operands, hence the code here is free to improperly handle opcodes that
3505 have no operands (for better performance and smaller code). */
3507 if (mnemonic
[0] != 'f')
3508 return 0; /* non-math */
3510 switch (mnemonic
[1])
3512 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3513 the fs segment override prefix not currently handled because no
3514 call path can make opcodes without operands get here */
3516 return 2 /* integer op */;
3518 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3519 return 3; /* fldcw/fldenv */
3522 if (mnemonic
[2] != 'o' /* fnop */)
3523 return 3; /* non-waiting control op */
3526 if (mnemonic
[2] == 's')
3527 return 3; /* frstor/frstpm */
3530 if (mnemonic
[2] == 'a')
3531 return 3; /* fsave */
3532 if (mnemonic
[2] == 't')
3534 switch (mnemonic
[3])
3536 case 'c': /* fstcw */
3537 case 'd': /* fstdw */
3538 case 'e': /* fstenv */
3539 case 's': /* fsts[gw] */
3545 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3546 return 0; /* fxsave/fxrstor are not really math ops */
3553 /* Build the VEX prefix. */
3556 build_vex_prefix (const insn_template
*t
)
3558 unsigned int register_specifier
;
3559 unsigned int implied_prefix
;
3560 unsigned int vector_length
;
3563 /* Check register specifier. */
3564 if (i
.vex
.register_specifier
)
3566 register_specifier
=
3567 ~register_number (i
.vex
.register_specifier
) & 0xf;
3568 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3571 register_specifier
= 0xf;
3573 /* Use 2-byte VEX prefix by swapping destination and source operand
3574 if there are more than 1 register operand. */
3575 if (i
.reg_operands
> 1
3576 && i
.vec_encoding
!= vex_encoding_vex3
3577 && i
.dir_encoding
== dir_encoding_default
3578 && i
.operands
== i
.reg_operands
3579 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3580 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3581 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3584 unsigned int xchg
= i
.operands
- 1;
3585 union i386_op temp_op
;
3586 i386_operand_type temp_type
;
3588 temp_type
= i
.types
[xchg
];
3589 i
.types
[xchg
] = i
.types
[0];
3590 i
.types
[0] = temp_type
;
3591 temp_op
= i
.op
[xchg
];
3592 i
.op
[xchg
] = i
.op
[0];
3595 gas_assert (i
.rm
.mode
== 3);
3599 i
.rm
.regmem
= i
.rm
.reg
;
3602 if (i
.tm
.opcode_modifier
.d
)
3603 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3604 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3605 else /* Use the next insn. */
3609 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3610 are no memory operands and at least 3 register ones. */
3611 if (i
.reg_operands
>= 3
3612 && i
.vec_encoding
!= vex_encoding_vex3
3613 && i
.reg_operands
== i
.operands
- i
.imm_operands
3614 && i
.tm
.opcode_modifier
.vex
3615 && i
.tm
.opcode_modifier
.commutative
3616 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3618 && i
.vex
.register_specifier
3619 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3621 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3622 union i386_op temp_op
;
3623 i386_operand_type temp_type
;
3625 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3626 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3627 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3628 &i
.types
[i
.operands
- 3]));
3629 gas_assert (i
.rm
.mode
== 3);
3631 temp_type
= i
.types
[xchg
];
3632 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3633 i
.types
[xchg
+ 1] = temp_type
;
3634 temp_op
= i
.op
[xchg
];
3635 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3636 i
.op
[xchg
+ 1] = temp_op
;
3639 xchg
= i
.rm
.regmem
| 8;
3640 i
.rm
.regmem
= ~register_specifier
& 0xf;
3641 gas_assert (!(i
.rm
.regmem
& 8));
3642 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3643 register_specifier
= ~xchg
& 0xf;
3646 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3647 vector_length
= avxscalar
;
3648 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3654 /* Determine vector length from the last multi-length vector
3657 for (op
= t
->operands
; op
--;)
3658 if (t
->operand_types
[op
].bitfield
.xmmword
3659 && t
->operand_types
[op
].bitfield
.ymmword
3660 && i
.types
[op
].bitfield
.ymmword
)
3667 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3672 case DATA_PREFIX_OPCODE
:
3675 case REPE_PREFIX_OPCODE
:
3678 case REPNE_PREFIX_OPCODE
:
3685 /* Check the REX.W bit and VEXW. */
3686 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3687 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3688 else if (i
.tm
.opcode_modifier
.vexw
)
3689 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3691 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3693 /* Use 2-byte VEX prefix if possible. */
3695 && i
.vec_encoding
!= vex_encoding_vex3
3696 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3697 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3699 /* 2-byte VEX prefix. */
3703 i
.vex
.bytes
[0] = 0xc5;
3705 /* Check the REX.R bit. */
3706 r
= (i
.rex
& REX_R
) ? 0 : 1;
3707 i
.vex
.bytes
[1] = (r
<< 7
3708 | register_specifier
<< 3
3709 | vector_length
<< 2
3714 /* 3-byte VEX prefix. */
3719 switch (i
.tm
.opcode_modifier
.vexopcode
)
3723 i
.vex
.bytes
[0] = 0xc4;
3727 i
.vex
.bytes
[0] = 0xc4;
3731 i
.vex
.bytes
[0] = 0xc4;
3735 i
.vex
.bytes
[0] = 0x8f;
3739 i
.vex
.bytes
[0] = 0x8f;
3743 i
.vex
.bytes
[0] = 0x8f;
3749 /* The high 3 bits of the second VEX byte are 1's compliment
3750 of RXB bits from REX. */
3751 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3753 i
.vex
.bytes
[2] = (w
<< 7
3754 | register_specifier
<< 3
3755 | vector_length
<< 2
3760 static INLINE bfd_boolean
3761 is_evex_encoding (const insn_template
*t
)
3763 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3764 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3765 || t
->opcode_modifier
.sae
;
3768 static INLINE bfd_boolean
3769 is_any_vex_encoding (const insn_template
*t
)
3771 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3772 || is_evex_encoding (t
);
3775 /* Build the EVEX prefix. */
3778 build_evex_prefix (void)
3780 unsigned int register_specifier
;
3781 unsigned int implied_prefix
;
3783 rex_byte vrex_used
= 0;
3785 /* Check register specifier. */
3786 if (i
.vex
.register_specifier
)
3788 gas_assert ((i
.vrex
& REX_X
) == 0);
3790 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3791 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3792 register_specifier
+= 8;
3793 /* The upper 16 registers are encoded in the fourth byte of the
3795 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3796 i
.vex
.bytes
[3] = 0x8;
3797 register_specifier
= ~register_specifier
& 0xf;
3801 register_specifier
= 0xf;
3803 /* Encode upper 16 vector index register in the fourth byte of
3805 if (!(i
.vrex
& REX_X
))
3806 i
.vex
.bytes
[3] = 0x8;
3811 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3816 case DATA_PREFIX_OPCODE
:
3819 case REPE_PREFIX_OPCODE
:
3822 case REPNE_PREFIX_OPCODE
:
3829 /* 4 byte EVEX prefix. */
3831 i
.vex
.bytes
[0] = 0x62;
3834 switch (i
.tm
.opcode_modifier
.vexopcode
)
3850 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3852 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3854 /* The fifth bit of the second EVEX byte is 1's compliment of the
3855 REX_R bit in VREX. */
3856 if (!(i
.vrex
& REX_R
))
3857 i
.vex
.bytes
[1] |= 0x10;
3861 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3863 /* When all operands are registers, the REX_X bit in REX is not
3864 used. We reuse it to encode the upper 16 registers, which is
3865 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3866 as 1's compliment. */
3867 if ((i
.vrex
& REX_B
))
3870 i
.vex
.bytes
[1] &= ~0x40;
3874 /* EVEX instructions shouldn't need the REX prefix. */
3875 i
.vrex
&= ~vrex_used
;
3876 gas_assert (i
.vrex
== 0);
3878 /* Check the REX.W bit and VEXW. */
3879 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3880 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3881 else if (i
.tm
.opcode_modifier
.vexw
)
3882 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3884 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3886 /* Encode the U bit. */
3887 implied_prefix
|= 0x4;
3889 /* The third byte of the EVEX prefix. */
3890 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3892 /* The fourth byte of the EVEX prefix. */
3893 /* The zeroing-masking bit. */
3894 if (i
.mask
&& i
.mask
->zeroing
)
3895 i
.vex
.bytes
[3] |= 0x80;
3897 /* Don't always set the broadcast bit if there is no RC. */
3900 /* Encode the vector length. */
3901 unsigned int vec_length
;
3903 if (!i
.tm
.opcode_modifier
.evex
3904 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3908 /* Determine vector length from the last multi-length vector
3910 for (op
= i
.operands
; op
--;)
3911 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3912 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3913 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3915 if (i
.types
[op
].bitfield
.zmmword
)
3917 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3920 else if (i
.types
[op
].bitfield
.ymmword
)
3922 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3925 else if (i
.types
[op
].bitfield
.xmmword
)
3927 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3930 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3932 switch (i
.broadcast
->bytes
)
3935 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3938 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3941 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3950 if (op
>= MAX_OPERANDS
)
3954 switch (i
.tm
.opcode_modifier
.evex
)
3956 case EVEXLIG
: /* LL' is ignored */
3957 vec_length
= evexlig
<< 5;
3960 vec_length
= 0 << 5;
3963 vec_length
= 1 << 5;
3966 vec_length
= 2 << 5;
3972 i
.vex
.bytes
[3] |= vec_length
;
3973 /* Encode the broadcast bit. */
3975 i
.vex
.bytes
[3] |= 0x10;
3979 if (i
.rounding
->type
!= saeonly
)
3980 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3982 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3985 if (i
.mask
&& i
.mask
->mask
)
3986 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3990 process_immext (void)
3994 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3995 which is coded in the same place as an 8-bit immediate field
3996 would be. Here we fake an 8-bit immediate operand from the
3997 opcode suffix stored in tm.extension_opcode.
3999 AVX instructions also use this encoding, for some of
4000 3 argument instructions. */
4002 gas_assert (i
.imm_operands
<= 1
4004 || (is_any_vex_encoding (&i
.tm
)
4005 && i
.operands
<= 4)));
4007 exp
= &im_expressions
[i
.imm_operands
++];
4008 i
.op
[i
.operands
].imms
= exp
;
4009 i
.types
[i
.operands
] = imm8
;
4011 exp
->X_op
= O_constant
;
4012 exp
->X_add_number
= i
.tm
.extension_opcode
;
4013 i
.tm
.extension_opcode
= None
;
4020 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4025 as_bad (_("invalid instruction `%s' after `%s'"),
4026 i
.tm
.name
, i
.hle_prefix
);
4029 if (i
.prefix
[LOCK_PREFIX
])
4031 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4035 case HLEPrefixRelease
:
4036 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4038 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4042 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4044 as_bad (_("memory destination needed for instruction `%s'"
4045 " after `xrelease'"), i
.tm
.name
);
4052 /* Try the shortest encoding by shortening operand size. */
4055 optimize_encoding (void)
4059 if (optimize_for_space
4060 && !is_any_vex_encoding (&i
.tm
)
4061 && i
.reg_operands
== 1
4062 && i
.imm_operands
== 1
4063 && !i
.types
[1].bitfield
.byte
4064 && i
.op
[0].imms
->X_op
== O_constant
4065 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4066 && (i
.tm
.base_opcode
== 0xa8
4067 || (i
.tm
.base_opcode
== 0xf6
4068 && i
.tm
.extension_opcode
== 0x0)))
4071 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4073 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4074 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4076 i
.types
[1].bitfield
.byte
= 1;
4077 /* Ignore the suffix. */
4079 /* Convert to byte registers. */
4080 if (i
.types
[1].bitfield
.word
)
4082 else if (i
.types
[1].bitfield
.dword
)
4086 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4091 else if (flag_code
== CODE_64BIT
4092 && !is_any_vex_encoding (&i
.tm
)
4093 && ((i
.types
[1].bitfield
.qword
4094 && i
.reg_operands
== 1
4095 && i
.imm_operands
== 1
4096 && i
.op
[0].imms
->X_op
== O_constant
4097 && ((i
.tm
.base_opcode
== 0xb8
4098 && i
.tm
.extension_opcode
== None
4099 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4100 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4101 && ((i
.tm
.base_opcode
== 0x24
4102 || i
.tm
.base_opcode
== 0xa8)
4103 || (i
.tm
.base_opcode
== 0x80
4104 && i
.tm
.extension_opcode
== 0x4)
4105 || ((i
.tm
.base_opcode
== 0xf6
4106 || (i
.tm
.base_opcode
| 1) == 0xc7)
4107 && i
.tm
.extension_opcode
== 0x0)))
4108 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4109 && i
.tm
.base_opcode
== 0x83
4110 && i
.tm
.extension_opcode
== 0x4)))
4111 || (i
.types
[0].bitfield
.qword
4112 && ((i
.reg_operands
== 2
4113 && i
.op
[0].regs
== i
.op
[1].regs
4114 && (i
.tm
.base_opcode
== 0x30
4115 || i
.tm
.base_opcode
== 0x28))
4116 || (i
.reg_operands
== 1
4118 && i
.tm
.base_opcode
== 0x30)))))
4121 andq $imm31, %r64 -> andl $imm31, %r32
4122 andq $imm7, %r64 -> andl $imm7, %r32
4123 testq $imm31, %r64 -> testl $imm31, %r32
4124 xorq %r64, %r64 -> xorl %r32, %r32
4125 subq %r64, %r64 -> subl %r32, %r32
4126 movq $imm31, %r64 -> movl $imm31, %r32
4127 movq $imm32, %r64 -> movl $imm32, %r32
4129 i
.tm
.opcode_modifier
.norex64
= 1;
4130 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4133 movq $imm31, %r64 -> movl $imm31, %r32
4134 movq $imm32, %r64 -> movl $imm32, %r32
4136 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4137 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4138 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4139 i
.types
[0].bitfield
.imm32
= 1;
4140 i
.types
[0].bitfield
.imm32s
= 0;
4141 i
.types
[0].bitfield
.imm64
= 0;
4142 i
.types
[1].bitfield
.dword
= 1;
4143 i
.types
[1].bitfield
.qword
= 0;
4144 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4147 movq $imm31, %r64 -> movl $imm31, %r32
4149 i
.tm
.base_opcode
= 0xb8;
4150 i
.tm
.extension_opcode
= None
;
4151 i
.tm
.opcode_modifier
.w
= 0;
4152 i
.tm
.opcode_modifier
.modrm
= 0;
4156 else if (optimize
> 1
4157 && !optimize_for_space
4158 && !is_any_vex_encoding (&i
.tm
)
4159 && i
.reg_operands
== 2
4160 && i
.op
[0].regs
== i
.op
[1].regs
4161 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4162 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4163 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4166 andb %rN, %rN -> testb %rN, %rN
4167 andw %rN, %rN -> testw %rN, %rN
4168 andq %rN, %rN -> testq %rN, %rN
4169 orb %rN, %rN -> testb %rN, %rN
4170 orw %rN, %rN -> testw %rN, %rN
4171 orq %rN, %rN -> testq %rN, %rN
4173 and outside of 64-bit mode
4175 andl %rN, %rN -> testl %rN, %rN
4176 orl %rN, %rN -> testl %rN, %rN
4178 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4180 else if (i
.reg_operands
== 3
4181 && i
.op
[0].regs
== i
.op
[1].regs
4182 && !i
.types
[2].bitfield
.xmmword
4183 && (i
.tm
.opcode_modifier
.vex
4184 || ((!i
.mask
|| i
.mask
->zeroing
)
4186 && is_evex_encoding (&i
.tm
)
4187 && (i
.vec_encoding
!= vex_encoding_evex
4188 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4189 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4190 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4191 && i
.types
[2].bitfield
.ymmword
))))
4192 && ((i
.tm
.base_opcode
== 0x55
4193 || i
.tm
.base_opcode
== 0x6655
4194 || i
.tm
.base_opcode
== 0x66df
4195 || i
.tm
.base_opcode
== 0x57
4196 || i
.tm
.base_opcode
== 0x6657
4197 || i
.tm
.base_opcode
== 0x66ef
4198 || i
.tm
.base_opcode
== 0x66f8
4199 || i
.tm
.base_opcode
== 0x66f9
4200 || i
.tm
.base_opcode
== 0x66fa
4201 || i
.tm
.base_opcode
== 0x66fb
4202 || i
.tm
.base_opcode
== 0x42
4203 || i
.tm
.base_opcode
== 0x6642
4204 || i
.tm
.base_opcode
== 0x47
4205 || i
.tm
.base_opcode
== 0x6647)
4206 && i
.tm
.extension_opcode
== None
))
4209 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4211 EVEX VOP %zmmM, %zmmM, %zmmN
4212 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4213 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4214 EVEX VOP %ymmM, %ymmM, %ymmN
4215 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4216 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4217 VEX VOP %ymmM, %ymmM, %ymmN
4218 -> VEX VOP %xmmM, %xmmM, %xmmN
4219 VOP, one of vpandn and vpxor:
4220 VEX VOP %ymmM, %ymmM, %ymmN
4221 -> VEX VOP %xmmM, %xmmM, %xmmN
4222 VOP, one of vpandnd and vpandnq:
4223 EVEX VOP %zmmM, %zmmM, %zmmN
4224 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4225 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4226 EVEX VOP %ymmM, %ymmM, %ymmN
4227 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4228 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4229 VOP, one of vpxord and vpxorq:
4230 EVEX VOP %zmmM, %zmmM, %zmmN
4231 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4232 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4233 EVEX VOP %ymmM, %ymmM, %ymmN
4234 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4235 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4236 VOP, one of kxord and kxorq:
4237 VEX VOP %kM, %kM, %kN
4238 -> VEX kxorw %kM, %kM, %kN
4239 VOP, one of kandnd and kandnq:
4240 VEX VOP %kM, %kM, %kN
4241 -> VEX kandnw %kM, %kM, %kN
4243 if (is_evex_encoding (&i
.tm
))
4245 if (i
.vec_encoding
!= vex_encoding_evex
)
4247 i
.tm
.opcode_modifier
.vex
= VEX128
;
4248 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4249 i
.tm
.opcode_modifier
.evex
= 0;
4251 else if (optimize
> 1)
4252 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4256 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4258 i
.tm
.base_opcode
&= 0xff;
4259 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4262 i
.tm
.opcode_modifier
.vex
= VEX128
;
4264 if (i
.tm
.opcode_modifier
.vex
)
4265 for (j
= 0; j
< 3; j
++)
4267 i
.types
[j
].bitfield
.xmmword
= 1;
4268 i
.types
[j
].bitfield
.ymmword
= 0;
4271 else if (i
.vec_encoding
!= vex_encoding_evex
4272 && !i
.types
[0].bitfield
.zmmword
4273 && !i
.types
[1].bitfield
.zmmword
4276 && is_evex_encoding (&i
.tm
)
4277 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4278 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4279 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4280 || (i
.tm
.base_opcode
& ~4) == 0x66db
4281 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4282 && i
.tm
.extension_opcode
== None
)
4285 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4286 vmovdqu32 and vmovdqu64:
4287 EVEX VOP %xmmM, %xmmN
4288 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4289 EVEX VOP %ymmM, %ymmN
4290 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4292 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4294 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4296 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4298 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4299 VOP, one of vpand, vpandn, vpor, vpxor:
4300 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4301 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4302 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4303 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4304 EVEX VOP{d,q} mem, %xmmM, %xmmN
4305 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4306 EVEX VOP{d,q} mem, %ymmM, %ymmN
4307 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4309 for (j
= 0; j
< i
.operands
; j
++)
4310 if (operand_type_check (i
.types
[j
], disp
)
4311 && i
.op
[j
].disps
->X_op
== O_constant
)
4313 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4314 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4315 bytes, we choose EVEX Disp8 over VEX Disp32. */
4316 int evex_disp8
, vex_disp8
;
4317 unsigned int memshift
= i
.memshift
;
4318 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4320 evex_disp8
= fits_in_disp8 (n
);
4322 vex_disp8
= fits_in_disp8 (n
);
4323 if (evex_disp8
!= vex_disp8
)
4325 i
.memshift
= memshift
;
4329 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4332 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4333 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4334 i
.tm
.opcode_modifier
.vex
4335 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4336 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4337 /* VPAND, VPOR, and VPXOR are commutative. */
4338 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4339 i
.tm
.opcode_modifier
.commutative
= 1;
4340 i
.tm
.opcode_modifier
.evex
= 0;
4341 i
.tm
.opcode_modifier
.masking
= 0;
4342 i
.tm
.opcode_modifier
.broadcast
= 0;
4343 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4346 i
.types
[j
].bitfield
.disp8
4347 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4351 /* Return non-zero for load instruction. */
4357 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4358 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4362 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4363 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4364 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4365 if (i
.tm
.opcode_modifier
.anysize
)
4368 /* pop, popf, popa. */
4369 if (strcmp (i
.tm
.name
, "pop") == 0
4370 || i
.tm
.base_opcode
== 0x9d
4371 || i
.tm
.base_opcode
== 0x61)
4374 /* movs, cmps, lods, scas. */
4375 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4379 if (base_opcode
== 0x6f
4380 || i
.tm
.base_opcode
== 0xd7)
4382 /* NB: For AMD-specific insns with implicit memory operands,
4383 they're intentionally not covered. */
4386 /* No memory operand. */
4387 if (!i
.mem_operands
)
4393 if (i
.tm
.base_opcode
== 0xae
4394 && i
.tm
.opcode_modifier
.vex
4395 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4396 && i
.tm
.extension_opcode
== 2)
4401 /* test, not, neg, mul, imul, div, idiv. */
4402 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4403 && i
.tm
.extension_opcode
!= 1)
4407 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4410 /* add, or, adc, sbb, and, sub, xor, cmp. */
4411 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4414 /* bt, bts, btr, btc. */
4415 if (i
.tm
.base_opcode
== 0xfba
4416 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4419 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4420 if ((base_opcode
== 0xc1
4421 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4422 && i
.tm
.extension_opcode
!= 6)
4425 /* cmpxchg8b, cmpxchg16b, xrstors. */
4426 if (i
.tm
.base_opcode
== 0xfc7
4427 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4430 /* fxrstor, ldmxcsr, xrstor. */
4431 if (i
.tm
.base_opcode
== 0xfae
4432 && (i
.tm
.extension_opcode
== 1
4433 || i
.tm
.extension_opcode
== 2
4434 || i
.tm
.extension_opcode
== 5))
4437 /* lgdt, lidt, lmsw. */
4438 if (i
.tm
.base_opcode
== 0xf01
4439 && (i
.tm
.extension_opcode
== 2
4440 || i
.tm
.extension_opcode
== 3
4441 || i
.tm
.extension_opcode
== 6))
4445 if (i
.tm
.base_opcode
== 0xfc7
4446 && i
.tm
.extension_opcode
== 6)
4449 /* Check for x87 instructions. */
4450 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4452 /* Skip fst, fstp, fstenv, fstcw. */
4453 if (i
.tm
.base_opcode
== 0xd9
4454 && (i
.tm
.extension_opcode
== 2
4455 || i
.tm
.extension_opcode
== 3
4456 || i
.tm
.extension_opcode
== 6
4457 || i
.tm
.extension_opcode
== 7))
4460 /* Skip fisttp, fist, fistp, fstp. */
4461 if (i
.tm
.base_opcode
== 0xdb
4462 && (i
.tm
.extension_opcode
== 1
4463 || i
.tm
.extension_opcode
== 2
4464 || i
.tm
.extension_opcode
== 3
4465 || i
.tm
.extension_opcode
== 7))
4468 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4469 if (i
.tm
.base_opcode
== 0xdd
4470 && (i
.tm
.extension_opcode
== 1
4471 || i
.tm
.extension_opcode
== 2
4472 || i
.tm
.extension_opcode
== 3
4473 || i
.tm
.extension_opcode
== 6
4474 || i
.tm
.extension_opcode
== 7))
4477 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4478 if (i
.tm
.base_opcode
== 0xdf
4479 && (i
.tm
.extension_opcode
== 1
4480 || i
.tm
.extension_opcode
== 2
4481 || i
.tm
.extension_opcode
== 3
4482 || i
.tm
.extension_opcode
== 6
4483 || i
.tm
.extension_opcode
== 7))
4490 dest
= i
.operands
- 1;
4492 /* Check fake imm8 operand and 3 source operands. */
4493 if ((i
.tm
.opcode_modifier
.immext
4494 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4495 && i
.types
[dest
].bitfield
.imm8
)
4498 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4500 && (base_opcode
== 0x1
4501 || base_opcode
== 0x9
4502 || base_opcode
== 0x11
4503 || base_opcode
== 0x19
4504 || base_opcode
== 0x21
4505 || base_opcode
== 0x29
4506 || base_opcode
== 0x31
4507 || base_opcode
== 0x39
4508 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4509 || base_opcode
== 0xfc1))
4512 /* Check for load instruction. */
4513 return (i
.types
[dest
].bitfield
.class != ClassNone
4514 || i
.types
[dest
].bitfield
.instance
== Accum
);
4517 /* Output lfence, 0xfaee8, after instruction. */
4520 insert_lfence_after (void)
4522 if (lfence_after_load
&& load_insn_p ())
4524 /* There are also two REP string instructions that require
4525 special treatment. Specifically, the compare string (CMPS)
4526 and scan string (SCAS) instructions set EFLAGS in a manner
4527 that depends on the data being compared/scanned. When used
4528 with a REP prefix, the number of iterations may therefore
4529 vary depending on this data. If the data is a program secret
4530 chosen by the adversary using an LVI method,
4531 then this data-dependent behavior may leak some aspect
4533 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4534 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4535 && i
.prefix
[REP_PREFIX
])
4537 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4540 char *p
= frag_more (3);
4547 /* Output lfence, 0xfaee8, before instruction. */
4550 insert_lfence_before (void)
4554 if (is_any_vex_encoding (&i
.tm
))
4557 if (i
.tm
.base_opcode
== 0xff
4558 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4560 /* Insert lfence before indirect branch if needed. */
4562 if (lfence_before_indirect_branch
== lfence_branch_none
)
4565 if (i
.operands
!= 1)
4568 if (i
.reg_operands
== 1)
4570 /* Indirect branch via register. Don't insert lfence with
4571 -mlfence-after-load=yes. */
4572 if (lfence_after_load
4573 || lfence_before_indirect_branch
== lfence_branch_memory
)
4576 else if (i
.mem_operands
== 1
4577 && lfence_before_indirect_branch
!= lfence_branch_register
)
4579 as_warn (_("indirect `%s` with memory operand should be avoided"),
4586 if (last_insn
.kind
!= last_insn_other
4587 && last_insn
.seg
== now_seg
)
4589 as_warn_where (last_insn
.file
, last_insn
.line
,
4590 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4591 last_insn
.name
, i
.tm
.name
);
4602 /* Output or/not/shl and lfence before near ret. */
4603 if (lfence_before_ret
!= lfence_before_ret_none
4604 && (i
.tm
.base_opcode
== 0xc2
4605 || i
.tm
.base_opcode
== 0xc3))
4607 if (last_insn
.kind
!= last_insn_other
4608 && last_insn
.seg
== now_seg
)
4610 as_warn_where (last_insn
.file
, last_insn
.line
,
4611 _("`%s` skips -mlfence-before-ret on `%s`"),
4612 last_insn
.name
, i
.tm
.name
);
4616 /* Near ret ingore operand size override under CPU64. */
4617 char prefix
= flag_code
== CODE_64BIT
4619 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4621 if (lfence_before_ret
== lfence_before_ret_not
)
4623 /* not: 0xf71424, may add prefix
4624 for operand size override or 64-bit code. */
4625 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4639 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4642 if (lfence_before_ret
== lfence_before_ret_or
)
4644 /* or: 0x830c2400, may add prefix
4645 for operand size override or 64-bit code. */
4651 /* shl: 0xc1242400, may add prefix
4652 for operand size override or 64-bit code. */
4667 /* This is the guts of the machine-dependent assembler. LINE points to a
4668 machine dependent instruction. This function is supposed to emit
4669 the frags/bytes it assembles to. */
4672 md_assemble (char *line
)
4675 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4676 const insn_template
*t
;
4678 /* Initialize globals. */
4679 memset (&i
, '\0', sizeof (i
));
4680 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4681 i
.reloc
[j
] = NO_RELOC
;
4682 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4683 memset (im_expressions
, '\0', sizeof (im_expressions
));
4684 save_stack_p
= save_stack
;
4686 /* First parse an instruction mnemonic & call i386_operand for the operands.
4687 We assume that the scrubber has arranged it so that line[0] is the valid
4688 start of a (possibly prefixed) mnemonic. */
4690 line
= parse_insn (line
, mnemonic
);
4693 mnem_suffix
= i
.suffix
;
4695 line
= parse_operands (line
, mnemonic
);
4697 xfree (i
.memop1_string
);
4698 i
.memop1_string
= NULL
;
4702 /* Now we've parsed the mnemonic into a set of templates, and have the
4703 operands at hand. */
4705 /* All Intel opcodes have reversed operands except for "bound", "enter",
4706 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4707 intersegment "jmp" and "call" instructions with 2 immediate operands so
4708 that the immediate segment precedes the offset, as it does when in AT&T
4712 && (strcmp (mnemonic
, "bound") != 0)
4713 && (strcmp (mnemonic
, "invlpga") != 0)
4714 && (strncmp (mnemonic
, "monitor", 7) != 0)
4715 && (strncmp (mnemonic
, "mwait", 5) != 0)
4716 && (strcmp (mnemonic
, "tpause") != 0)
4717 && (strcmp (mnemonic
, "umwait") != 0)
4718 && !(operand_type_check (i
.types
[0], imm
)
4719 && operand_type_check (i
.types
[1], imm
)))
4722 /* The order of the immediates should be reversed
4723 for 2 immediates extrq and insertq instructions */
4724 if (i
.imm_operands
== 2
4725 && (strcmp (mnemonic
, "extrq") == 0
4726 || strcmp (mnemonic
, "insertq") == 0))
4727 swap_2_operands (0, 1);
4732 /* Don't optimize displacement for movabs since it only takes 64bit
4735 && i
.disp_encoding
!= disp_encoding_32bit
4736 && (flag_code
!= CODE_64BIT
4737 || strcmp (mnemonic
, "movabs") != 0))
4740 /* Next, we find a template that matches the given insn,
4741 making sure the overlap of the given operands types is consistent
4742 with the template operand types. */
4744 if (!(t
= match_template (mnem_suffix
)))
4747 if (sse_check
!= check_none
4748 && !i
.tm
.opcode_modifier
.noavx
4749 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4750 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4751 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4752 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4753 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4754 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4755 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4756 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4757 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4758 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4759 || i
.tm
.cpu_flags
.bitfield
.cpusha
4760 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4762 (sse_check
== check_warning
4764 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4767 if (i
.tm
.opcode_modifier
.fwait
)
4768 if (!add_prefix (FWAIT_OPCODE
))
4771 /* Check if REP prefix is OK. */
4772 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4774 as_bad (_("invalid instruction `%s' after `%s'"),
4775 i
.tm
.name
, i
.rep_prefix
);
4779 /* Check for lock without a lockable instruction. Destination operand
4780 must be memory unless it is xchg (0x86). */
4781 if (i
.prefix
[LOCK_PREFIX
]
4782 && (!i
.tm
.opcode_modifier
.islockable
4783 || i
.mem_operands
== 0
4784 || (i
.tm
.base_opcode
!= 0x86
4785 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4787 as_bad (_("expecting lockable instruction after `lock'"));
4791 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4792 if (i
.prefix
[DATA_PREFIX
]
4793 && (is_any_vex_encoding (&i
.tm
)
4794 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4795 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4797 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4801 /* Check if HLE prefix is OK. */
4802 if (i
.hle_prefix
&& !check_hle ())
4805 /* Check BND prefix. */
4806 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4807 as_bad (_("expecting valid branch instruction after `bnd'"));
4809 /* Check NOTRACK prefix. */
4810 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4811 as_bad (_("expecting indirect branch instruction after `notrack'"));
4813 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4815 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4816 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4817 else if (flag_code
!= CODE_16BIT
4818 ? i
.prefix
[ADDR_PREFIX
]
4819 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4820 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4823 /* Insert BND prefix. */
4824 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4826 if (!i
.prefix
[BND_PREFIX
])
4827 add_prefix (BND_PREFIX_OPCODE
);
4828 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4830 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4831 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4835 /* Check string instruction segment overrides. */
4836 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4838 gas_assert (i
.mem_operands
);
4839 if (!check_string ())
4841 i
.disp_operands
= 0;
4844 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4845 optimize_encoding ();
4847 if (!process_suffix ())
4850 /* Update operand types. */
4851 for (j
= 0; j
< i
.operands
; j
++)
4852 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4854 /* Make still unresolved immediate matches conform to size of immediate
4855 given in i.suffix. */
4856 if (!finalize_imm ())
4859 if (i
.types
[0].bitfield
.imm1
)
4860 i
.imm_operands
= 0; /* kludge for shift insns. */
4862 /* We only need to check those implicit registers for instructions
4863 with 3 operands or less. */
4864 if (i
.operands
<= 3)
4865 for (j
= 0; j
< i
.operands
; j
++)
4866 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4867 && !i
.types
[j
].bitfield
.xmmword
)
4870 /* ImmExt should be processed after SSE2AVX. */
4871 if (!i
.tm
.opcode_modifier
.sse2avx
4872 && i
.tm
.opcode_modifier
.immext
)
4875 /* For insns with operands there are more diddles to do to the opcode. */
4878 if (!process_operands ())
4881 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4883 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4884 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4887 if (is_any_vex_encoding (&i
.tm
))
4889 if (!cpu_arch_flags
.bitfield
.cpui286
)
4891 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4896 if (i
.tm
.opcode_modifier
.vex
)
4897 build_vex_prefix (t
);
4899 build_evex_prefix ();
4902 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4903 instructions may define INT_OPCODE as well, so avoid this corner
4904 case for those instructions that use MODRM. */
4905 if (i
.tm
.base_opcode
== INT_OPCODE
4906 && !i
.tm
.opcode_modifier
.modrm
4907 && i
.op
[0].imms
->X_add_number
== 3)
4909 i
.tm
.base_opcode
= INT3_OPCODE
;
4913 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4914 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4915 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4916 && i
.op
[0].disps
->X_op
== O_constant
)
4918 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4919 the absolute address given by the constant. Since ix86 jumps and
4920 calls are pc relative, we need to generate a reloc. */
4921 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4922 i
.op
[0].disps
->X_op
= O_symbol
;
4925 /* For 8 bit registers we need an empty rex prefix. Also if the
4926 instruction already has a prefix, we need to convert old
4927 registers to new ones. */
4929 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4930 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4931 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4932 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4933 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4934 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4939 i
.rex
|= REX_OPCODE
;
4940 for (x
= 0; x
< 2; x
++)
4942 /* Look for 8 bit operand that uses old registers. */
4943 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4944 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4946 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4947 /* In case it is "hi" register, give up. */
4948 if (i
.op
[x
].regs
->reg_num
> 3)
4949 as_bad (_("can't encode register '%s%s' in an "
4950 "instruction requiring REX prefix."),
4951 register_prefix
, i
.op
[x
].regs
->reg_name
);
4953 /* Otherwise it is equivalent to the extended register.
4954 Since the encoding doesn't change this is merely
4955 cosmetic cleanup for debug output. */
4957 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4962 if (i
.rex
== 0 && i
.rex_encoding
)
4964 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4965 that uses legacy register. If it is "hi" register, don't add
4966 the REX_OPCODE byte. */
4968 for (x
= 0; x
< 2; x
++)
4969 if (i
.types
[x
].bitfield
.class == Reg
4970 && i
.types
[x
].bitfield
.byte
4971 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4972 && i
.op
[x
].regs
->reg_num
> 3)
4974 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4975 i
.rex_encoding
= FALSE
;
4984 add_prefix (REX_OPCODE
| i
.rex
);
4986 insert_lfence_before ();
4988 /* We are ready to output the insn. */
4991 insert_lfence_after ();
4993 last_insn
.seg
= now_seg
;
4995 if (i
.tm
.opcode_modifier
.isprefix
)
4997 last_insn
.kind
= last_insn_prefix
;
4998 last_insn
.name
= i
.tm
.name
;
4999 last_insn
.file
= as_where (&last_insn
.line
);
5002 last_insn
.kind
= last_insn_other
;
5006 parse_insn (char *line
, char *mnemonic
)
5009 char *token_start
= l
;
5012 const insn_template
*t
;
5018 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5023 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5025 as_bad (_("no such instruction: `%s'"), token_start
);
5030 if (!is_space_char (*l
)
5031 && *l
!= END_OF_INSN
5033 || (*l
!= PREFIX_SEPARATOR
5036 as_bad (_("invalid character %s in mnemonic"),
5037 output_invalid (*l
));
5040 if (token_start
== l
)
5042 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5043 as_bad (_("expecting prefix; got nothing"));
5045 as_bad (_("expecting mnemonic; got nothing"));
5049 /* Look up instruction (or prefix) via hash table. */
5050 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5052 if (*l
!= END_OF_INSN
5053 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5054 && current_templates
5055 && current_templates
->start
->opcode_modifier
.isprefix
)
5057 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5059 as_bad ((flag_code
!= CODE_64BIT
5060 ? _("`%s' is only supported in 64-bit mode")
5061 : _("`%s' is not supported in 64-bit mode")),
5062 current_templates
->start
->name
);
5065 /* If we are in 16-bit mode, do not allow addr16 or data16.
5066 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5067 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5068 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5069 && flag_code
!= CODE_64BIT
5070 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5071 ^ (flag_code
== CODE_16BIT
)))
5073 as_bad (_("redundant %s prefix"),
5074 current_templates
->start
->name
);
5077 if (current_templates
->start
->opcode_length
== 0)
5079 /* Handle pseudo prefixes. */
5080 switch (current_templates
->start
->base_opcode
)
5084 i
.disp_encoding
= disp_encoding_8bit
;
5088 i
.disp_encoding
= disp_encoding_32bit
;
5092 i
.dir_encoding
= dir_encoding_load
;
5096 i
.dir_encoding
= dir_encoding_store
;
5100 i
.vec_encoding
= vex_encoding_vex
;
5104 i
.vec_encoding
= vex_encoding_vex3
;
5108 i
.vec_encoding
= vex_encoding_evex
;
5112 i
.rex_encoding
= TRUE
;
5116 i
.no_optimize
= TRUE
;
5124 /* Add prefix, checking for repeated prefixes. */
5125 switch (add_prefix (current_templates
->start
->base_opcode
))
5130 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5131 i
.notrack_prefix
= current_templates
->start
->name
;
5134 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5135 i
.hle_prefix
= current_templates
->start
->name
;
5136 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5137 i
.bnd_prefix
= current_templates
->start
->name
;
5139 i
.rep_prefix
= current_templates
->start
->name
;
5145 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5152 if (!current_templates
)
5154 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5155 Check if we should swap operand or force 32bit displacement in
5157 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5158 i
.dir_encoding
= dir_encoding_swap
;
5159 else if (mnem_p
- 3 == dot_p
5162 i
.disp_encoding
= disp_encoding_8bit
;
5163 else if (mnem_p
- 4 == dot_p
5167 i
.disp_encoding
= disp_encoding_32bit
;
5172 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5175 if (!current_templates
)
5178 if (mnem_p
> mnemonic
)
5180 /* See if we can get a match by trimming off a suffix. */
5183 case WORD_MNEM_SUFFIX
:
5184 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5185 i
.suffix
= SHORT_MNEM_SUFFIX
;
5188 case BYTE_MNEM_SUFFIX
:
5189 case QWORD_MNEM_SUFFIX
:
5190 i
.suffix
= mnem_p
[-1];
5192 current_templates
= (const templates
*) hash_find (op_hash
,
5195 case SHORT_MNEM_SUFFIX
:
5196 case LONG_MNEM_SUFFIX
:
5199 i
.suffix
= mnem_p
[-1];
5201 current_templates
= (const templates
*) hash_find (op_hash
,
5210 if (intel_float_operand (mnemonic
) == 1)
5211 i
.suffix
= SHORT_MNEM_SUFFIX
;
5213 i
.suffix
= LONG_MNEM_SUFFIX
;
5215 current_templates
= (const templates
*) hash_find (op_hash
,
5222 if (!current_templates
)
5224 as_bad (_("no such instruction: `%s'"), token_start
);
5229 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5230 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5232 /* Check for a branch hint. We allow ",pt" and ",pn" for
5233 predict taken and predict not taken respectively.
5234 I'm not sure that branch hints actually do anything on loop
5235 and jcxz insns (JumpByte) for current Pentium4 chips. They
5236 may work in the future and it doesn't hurt to accept them
5238 if (l
[0] == ',' && l
[1] == 'p')
5242 if (!add_prefix (DS_PREFIX_OPCODE
))
5246 else if (l
[2] == 'n')
5248 if (!add_prefix (CS_PREFIX_OPCODE
))
5254 /* Any other comma loses. */
5257 as_bad (_("invalid character %s in mnemonic"),
5258 output_invalid (*l
));
5262 /* Check if instruction is supported on specified architecture. */
5264 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5266 supported
|= cpu_flags_match (t
);
5267 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5269 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5270 as_warn (_("use .code16 to ensure correct addressing mode"));
5276 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5277 as_bad (flag_code
== CODE_64BIT
5278 ? _("`%s' is not supported in 64-bit mode")
5279 : _("`%s' is only supported in 64-bit mode"),
5280 current_templates
->start
->name
);
5282 as_bad (_("`%s' is not supported on `%s%s'"),
5283 current_templates
->start
->name
,
5284 cpu_arch_name
? cpu_arch_name
: default_arch
,
5285 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5291 parse_operands (char *l
, const char *mnemonic
)
5295 /* 1 if operand is pending after ','. */
5296 unsigned int expecting_operand
= 0;
5298 /* Non-zero if operand parens not balanced. */
5299 unsigned int paren_not_balanced
;
5301 while (*l
!= END_OF_INSN
)
5303 /* Skip optional white space before operand. */
5304 if (is_space_char (*l
))
5306 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5308 as_bad (_("invalid character %s before operand %d"),
5309 output_invalid (*l
),
5313 token_start
= l
; /* After white space. */
5314 paren_not_balanced
= 0;
5315 while (paren_not_balanced
|| *l
!= ',')
5317 if (*l
== END_OF_INSN
)
5319 if (paren_not_balanced
)
5322 as_bad (_("unbalanced parenthesis in operand %d."),
5325 as_bad (_("unbalanced brackets in operand %d."),
5330 break; /* we are done */
5332 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5334 as_bad (_("invalid character %s in operand %d"),
5335 output_invalid (*l
),
5342 ++paren_not_balanced
;
5344 --paren_not_balanced
;
5349 ++paren_not_balanced
;
5351 --paren_not_balanced
;
5355 if (l
!= token_start
)
5356 { /* Yes, we've read in another operand. */
5357 unsigned int operand_ok
;
5358 this_operand
= i
.operands
++;
5359 if (i
.operands
> MAX_OPERANDS
)
5361 as_bad (_("spurious operands; (%d operands/instruction max)"),
5365 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5366 /* Now parse operand adding info to 'i' as we go along. */
5367 END_STRING_AND_SAVE (l
);
5369 if (i
.mem_operands
> 1)
5371 as_bad (_("too many memory references for `%s'"),
5378 i386_intel_operand (token_start
,
5379 intel_float_operand (mnemonic
));
5381 operand_ok
= i386_att_operand (token_start
);
5383 RESTORE_END_STRING (l
);
5389 if (expecting_operand
)
5391 expecting_operand_after_comma
:
5392 as_bad (_("expecting operand after ','; got nothing"));
5397 as_bad (_("expecting operand before ','; got nothing"));
5402 /* Now *l must be either ',' or END_OF_INSN. */
5405 if (*++l
== END_OF_INSN
)
5407 /* Just skip it, if it's \n complain. */
5408 goto expecting_operand_after_comma
;
5410 expecting_operand
= 1;
5417 swap_2_operands (int xchg1
, int xchg2
)
5419 union i386_op temp_op
;
5420 i386_operand_type temp_type
;
5421 unsigned int temp_flags
;
5422 enum bfd_reloc_code_real temp_reloc
;
5424 temp_type
= i
.types
[xchg2
];
5425 i
.types
[xchg2
] = i
.types
[xchg1
];
5426 i
.types
[xchg1
] = temp_type
;
5428 temp_flags
= i
.flags
[xchg2
];
5429 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5430 i
.flags
[xchg1
] = temp_flags
;
5432 temp_op
= i
.op
[xchg2
];
5433 i
.op
[xchg2
] = i
.op
[xchg1
];
5434 i
.op
[xchg1
] = temp_op
;
5436 temp_reloc
= i
.reloc
[xchg2
];
5437 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5438 i
.reloc
[xchg1
] = temp_reloc
;
5442 if (i
.mask
->operand
== xchg1
)
5443 i
.mask
->operand
= xchg2
;
5444 else if (i
.mask
->operand
== xchg2
)
5445 i
.mask
->operand
= xchg1
;
5449 if (i
.broadcast
->operand
== xchg1
)
5450 i
.broadcast
->operand
= xchg2
;
5451 else if (i
.broadcast
->operand
== xchg2
)
5452 i
.broadcast
->operand
= xchg1
;
5456 if (i
.rounding
->operand
== xchg1
)
5457 i
.rounding
->operand
= xchg2
;
5458 else if (i
.rounding
->operand
== xchg2
)
5459 i
.rounding
->operand
= xchg1
;
5464 swap_operands (void)
5470 swap_2_operands (1, i
.operands
- 2);
5474 swap_2_operands (0, i
.operands
- 1);
5480 if (i
.mem_operands
== 2)
5482 const seg_entry
*temp_seg
;
5483 temp_seg
= i
.seg
[0];
5484 i
.seg
[0] = i
.seg
[1];
5485 i
.seg
[1] = temp_seg
;
5489 /* Try to ensure constant immediates are represented in the smallest
5494 char guess_suffix
= 0;
5498 guess_suffix
= i
.suffix
;
5499 else if (i
.reg_operands
)
5501 /* Figure out a suffix from the last register operand specified.
5502 We can't do this properly yet, i.e. excluding special register
5503 instances, but the following works for instructions with
5504 immediates. In any case, we can't set i.suffix yet. */
5505 for (op
= i
.operands
; --op
>= 0;)
5506 if (i
.types
[op
].bitfield
.class != Reg
)
5508 else if (i
.types
[op
].bitfield
.byte
)
5510 guess_suffix
= BYTE_MNEM_SUFFIX
;
5513 else if (i
.types
[op
].bitfield
.word
)
5515 guess_suffix
= WORD_MNEM_SUFFIX
;
5518 else if (i
.types
[op
].bitfield
.dword
)
5520 guess_suffix
= LONG_MNEM_SUFFIX
;
5523 else if (i
.types
[op
].bitfield
.qword
)
5525 guess_suffix
= QWORD_MNEM_SUFFIX
;
5529 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5530 guess_suffix
= WORD_MNEM_SUFFIX
;
5532 for (op
= i
.operands
; --op
>= 0;)
5533 if (operand_type_check (i
.types
[op
], imm
))
5535 switch (i
.op
[op
].imms
->X_op
)
5538 /* If a suffix is given, this operand may be shortened. */
5539 switch (guess_suffix
)
5541 case LONG_MNEM_SUFFIX
:
5542 i
.types
[op
].bitfield
.imm32
= 1;
5543 i
.types
[op
].bitfield
.imm64
= 1;
5545 case WORD_MNEM_SUFFIX
:
5546 i
.types
[op
].bitfield
.imm16
= 1;
5547 i
.types
[op
].bitfield
.imm32
= 1;
5548 i
.types
[op
].bitfield
.imm32s
= 1;
5549 i
.types
[op
].bitfield
.imm64
= 1;
5551 case BYTE_MNEM_SUFFIX
:
5552 i
.types
[op
].bitfield
.imm8
= 1;
5553 i
.types
[op
].bitfield
.imm8s
= 1;
5554 i
.types
[op
].bitfield
.imm16
= 1;
5555 i
.types
[op
].bitfield
.imm32
= 1;
5556 i
.types
[op
].bitfield
.imm32s
= 1;
5557 i
.types
[op
].bitfield
.imm64
= 1;
5561 /* If this operand is at most 16 bits, convert it
5562 to a signed 16 bit number before trying to see
5563 whether it will fit in an even smaller size.
5564 This allows a 16-bit operand such as $0xffe0 to
5565 be recognised as within Imm8S range. */
5566 if ((i
.types
[op
].bitfield
.imm16
)
5567 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5569 i
.op
[op
].imms
->X_add_number
=
5570 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5573 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5574 if ((i
.types
[op
].bitfield
.imm32
)
5575 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5578 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5579 ^ ((offsetT
) 1 << 31))
5580 - ((offsetT
) 1 << 31));
5584 = operand_type_or (i
.types
[op
],
5585 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5587 /* We must avoid matching of Imm32 templates when 64bit
5588 only immediate is available. */
5589 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5590 i
.types
[op
].bitfield
.imm32
= 0;
5597 /* Symbols and expressions. */
5599 /* Convert symbolic operand to proper sizes for matching, but don't
5600 prevent matching a set of insns that only supports sizes other
5601 than those matching the insn suffix. */
5603 i386_operand_type mask
, allowed
;
5604 const insn_template
*t
;
5606 operand_type_set (&mask
, 0);
5607 operand_type_set (&allowed
, 0);
5609 for (t
= current_templates
->start
;
5610 t
< current_templates
->end
;
5613 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5614 allowed
= operand_type_and (allowed
, anyimm
);
5616 switch (guess_suffix
)
5618 case QWORD_MNEM_SUFFIX
:
5619 mask
.bitfield
.imm64
= 1;
5620 mask
.bitfield
.imm32s
= 1;
5622 case LONG_MNEM_SUFFIX
:
5623 mask
.bitfield
.imm32
= 1;
5625 case WORD_MNEM_SUFFIX
:
5626 mask
.bitfield
.imm16
= 1;
5628 case BYTE_MNEM_SUFFIX
:
5629 mask
.bitfield
.imm8
= 1;
5634 allowed
= operand_type_and (mask
, allowed
);
5635 if (!operand_type_all_zero (&allowed
))
5636 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5643 /* Try to use the smallest displacement type too. */
5645 optimize_disp (void)
5649 for (op
= i
.operands
; --op
>= 0;)
5650 if (operand_type_check (i
.types
[op
], disp
))
5652 if (i
.op
[op
].disps
->X_op
== O_constant
)
5654 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5656 if (i
.types
[op
].bitfield
.disp16
5657 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5659 /* If this operand is at most 16 bits, convert
5660 to a signed 16 bit number and don't use 64bit
5662 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5663 i
.types
[op
].bitfield
.disp64
= 0;
5666 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5667 if (i
.types
[op
].bitfield
.disp32
5668 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5670 /* If this operand is at most 32 bits, convert
5671 to a signed 32 bit number and don't use 64bit
5673 op_disp
&= (((offsetT
) 2 << 31) - 1);
5674 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5675 i
.types
[op
].bitfield
.disp64
= 0;
5678 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5680 i
.types
[op
].bitfield
.disp8
= 0;
5681 i
.types
[op
].bitfield
.disp16
= 0;
5682 i
.types
[op
].bitfield
.disp32
= 0;
5683 i
.types
[op
].bitfield
.disp32s
= 0;
5684 i
.types
[op
].bitfield
.disp64
= 0;
5688 else if (flag_code
== CODE_64BIT
)
5690 if (fits_in_signed_long (op_disp
))
5692 i
.types
[op
].bitfield
.disp64
= 0;
5693 i
.types
[op
].bitfield
.disp32s
= 1;
5695 if (i
.prefix
[ADDR_PREFIX
]
5696 && fits_in_unsigned_long (op_disp
))
5697 i
.types
[op
].bitfield
.disp32
= 1;
5699 if ((i
.types
[op
].bitfield
.disp32
5700 || i
.types
[op
].bitfield
.disp32s
5701 || i
.types
[op
].bitfield
.disp16
)
5702 && fits_in_disp8 (op_disp
))
5703 i
.types
[op
].bitfield
.disp8
= 1;
5705 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5706 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5708 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5709 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5710 i
.types
[op
].bitfield
.disp8
= 0;
5711 i
.types
[op
].bitfield
.disp16
= 0;
5712 i
.types
[op
].bitfield
.disp32
= 0;
5713 i
.types
[op
].bitfield
.disp32s
= 0;
5714 i
.types
[op
].bitfield
.disp64
= 0;
5717 /* We only support 64bit displacement on constants. */
5718 i
.types
[op
].bitfield
.disp64
= 0;
5722 /* Return 1 if there is a match in broadcast bytes between operand
5723 GIVEN and instruction template T. */
5726 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5728 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5729 && i
.types
[given
].bitfield
.byte
)
5730 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5731 && i
.types
[given
].bitfield
.word
)
5732 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5733 && i
.types
[given
].bitfield
.dword
)
5734 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5735 && i
.types
[given
].bitfield
.qword
));
5738 /* Check if operands are valid for the instruction. */
5741 check_VecOperands (const insn_template
*t
)
5746 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5747 any one operand are implicity requiring AVX512VL support if the actual
5748 operand size is YMMword or XMMword. Since this function runs after
5749 template matching, there's no need to check for YMMword/XMMword in
5751 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5752 if (!cpu_flags_all_zero (&cpu
)
5753 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5754 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5756 for (op
= 0; op
< t
->operands
; ++op
)
5758 if (t
->operand_types
[op
].bitfield
.zmmword
5759 && (i
.types
[op
].bitfield
.ymmword
5760 || i
.types
[op
].bitfield
.xmmword
))
5762 i
.error
= unsupported
;
5768 /* Without VSIB byte, we can't have a vector register for index. */
5769 if (!t
->opcode_modifier
.vecsib
5771 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5772 || i
.index_reg
->reg_type
.bitfield
.ymmword
5773 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5775 i
.error
= unsupported_vector_index_register
;
5779 /* Check if default mask is allowed. */
5780 if (t
->opcode_modifier
.nodefmask
5781 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5783 i
.error
= no_default_mask
;
5787 /* For VSIB byte, we need a vector register for index, and all vector
5788 registers must be distinct. */
5789 if (t
->opcode_modifier
.vecsib
)
5792 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5793 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5794 || (t
->opcode_modifier
.vecsib
== VecSIB256
5795 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5796 || (t
->opcode_modifier
.vecsib
== VecSIB512
5797 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5799 i
.error
= invalid_vsib_address
;
5803 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5804 if (i
.reg_operands
== 2 && !i
.mask
)
5806 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5807 gas_assert (i
.types
[0].bitfield
.xmmword
5808 || i
.types
[0].bitfield
.ymmword
);
5809 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5810 gas_assert (i
.types
[2].bitfield
.xmmword
5811 || i
.types
[2].bitfield
.ymmword
);
5812 if (operand_check
== check_none
)
5814 if (register_number (i
.op
[0].regs
)
5815 != register_number (i
.index_reg
)
5816 && register_number (i
.op
[2].regs
)
5817 != register_number (i
.index_reg
)
5818 && register_number (i
.op
[0].regs
)
5819 != register_number (i
.op
[2].regs
))
5821 if (operand_check
== check_error
)
5823 i
.error
= invalid_vector_register_set
;
5826 as_warn (_("mask, index, and destination registers should be distinct"));
5828 else if (i
.reg_operands
== 1 && i
.mask
)
5830 if (i
.types
[1].bitfield
.class == RegSIMD
5831 && (i
.types
[1].bitfield
.xmmword
5832 || i
.types
[1].bitfield
.ymmword
5833 || i
.types
[1].bitfield
.zmmword
)
5834 && (register_number (i
.op
[1].regs
)
5835 == register_number (i
.index_reg
)))
5837 if (operand_check
== check_error
)
5839 i
.error
= invalid_vector_register_set
;
5842 if (operand_check
!= check_none
)
5843 as_warn (_("index and destination registers should be distinct"));
5848 /* Check if broadcast is supported by the instruction and is applied
5849 to the memory operand. */
5852 i386_operand_type type
, overlap
;
5854 /* Check if specified broadcast is supported in this instruction,
5855 and its broadcast bytes match the memory operand. */
5856 op
= i
.broadcast
->operand
;
5857 if (!t
->opcode_modifier
.broadcast
5858 || !(i
.flags
[op
] & Operand_Mem
)
5859 || (!i
.types
[op
].bitfield
.unspecified
5860 && !match_broadcast_size (t
, op
)))
5863 i
.error
= unsupported_broadcast
;
5867 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5868 * i
.broadcast
->type
);
5869 operand_type_set (&type
, 0);
5870 switch (i
.broadcast
->bytes
)
5873 type
.bitfield
.word
= 1;
5876 type
.bitfield
.dword
= 1;
5879 type
.bitfield
.qword
= 1;
5882 type
.bitfield
.xmmword
= 1;
5885 type
.bitfield
.ymmword
= 1;
5888 type
.bitfield
.zmmword
= 1;
5894 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5895 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5896 && t
->operand_types
[op
].bitfield
.byte
5897 + t
->operand_types
[op
].bitfield
.word
5898 + t
->operand_types
[op
].bitfield
.dword
5899 + t
->operand_types
[op
].bitfield
.qword
> 1)
5901 overlap
.bitfield
.xmmword
= 0;
5902 overlap
.bitfield
.ymmword
= 0;
5903 overlap
.bitfield
.zmmword
= 0;
5905 if (operand_type_all_zero (&overlap
))
5908 if (t
->opcode_modifier
.checkregsize
)
5912 type
.bitfield
.baseindex
= 1;
5913 for (j
= 0; j
< i
.operands
; ++j
)
5916 && !operand_type_register_match(i
.types
[j
],
5917 t
->operand_types
[j
],
5919 t
->operand_types
[op
]))
5924 /* If broadcast is supported in this instruction, we need to check if
5925 operand of one-element size isn't specified without broadcast. */
5926 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5928 /* Find memory operand. */
5929 for (op
= 0; op
< i
.operands
; op
++)
5930 if (i
.flags
[op
] & Operand_Mem
)
5932 gas_assert (op
< i
.operands
);
5933 /* Check size of the memory operand. */
5934 if (match_broadcast_size (t
, op
))
5936 i
.error
= broadcast_needed
;
5941 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5943 /* Check if requested masking is supported. */
5946 switch (t
->opcode_modifier
.masking
)
5950 case MERGING_MASKING
:
5951 if (i
.mask
->zeroing
)
5954 i
.error
= unsupported_masking
;
5958 case DYNAMIC_MASKING
:
5959 /* Memory destinations allow only merging masking. */
5960 if (i
.mask
->zeroing
&& i
.mem_operands
)
5962 /* Find memory operand. */
5963 for (op
= 0; op
< i
.operands
; op
++)
5964 if (i
.flags
[op
] & Operand_Mem
)
5966 gas_assert (op
< i
.operands
);
5967 if (op
== i
.operands
- 1)
5969 i
.error
= unsupported_masking
;
5979 /* Check if masking is applied to dest operand. */
5980 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5982 i
.error
= mask_not_on_destination
;
5989 if (!t
->opcode_modifier
.sae
5990 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5992 i
.error
= unsupported_rc_sae
;
5995 /* If the instruction has several immediate operands and one of
5996 them is rounding, the rounding operand should be the last
5997 immediate operand. */
5998 if (i
.imm_operands
> 1
5999 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6001 i
.error
= rc_sae_operand_not_last_imm
;
6006 /* Check the special Imm4 cases; must be the first operand. */
6007 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6009 if (i
.op
[0].imms
->X_op
!= O_constant
6010 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6016 /* Turn off Imm<N> so that update_imm won't complain. */
6017 operand_type_set (&i
.types
[0], 0);
6020 /* Check vector Disp8 operand. */
6021 if (t
->opcode_modifier
.disp8memshift
6022 && i
.disp_encoding
!= disp_encoding_32bit
)
6025 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6026 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6027 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6030 const i386_operand_type
*type
= NULL
;
6033 for (op
= 0; op
< i
.operands
; op
++)
6034 if (i
.flags
[op
] & Operand_Mem
)
6036 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6037 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6038 else if (t
->operand_types
[op
].bitfield
.xmmword
6039 + t
->operand_types
[op
].bitfield
.ymmword
6040 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6041 type
= &t
->operand_types
[op
];
6042 else if (!i
.types
[op
].bitfield
.unspecified
)
6043 type
= &i
.types
[op
];
6045 else if (i
.types
[op
].bitfield
.class == RegSIMD
6046 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6048 if (i
.types
[op
].bitfield
.zmmword
)
6050 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6052 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6058 if (type
->bitfield
.zmmword
)
6060 else if (type
->bitfield
.ymmword
)
6062 else if (type
->bitfield
.xmmword
)
6066 /* For the check in fits_in_disp8(). */
6067 if (i
.memshift
== 0)
6071 for (op
= 0; op
< i
.operands
; op
++)
6072 if (operand_type_check (i
.types
[op
], disp
)
6073 && i
.op
[op
].disps
->X_op
== O_constant
)
6075 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6077 i
.types
[op
].bitfield
.disp8
= 1;
6080 i
.types
[op
].bitfield
.disp8
= 0;
6089 /* Check if encoding requirements are met by the instruction. */
6092 VEX_check_encoding (const insn_template
*t
)
6094 if (i
.vec_encoding
== vex_encoding_error
)
6096 i
.error
= unsupported
;
6100 if (i
.vec_encoding
== vex_encoding_evex
)
6102 /* This instruction must be encoded with EVEX prefix. */
6103 if (!is_evex_encoding (t
))
6105 i
.error
= unsupported
;
6111 if (!t
->opcode_modifier
.vex
)
6113 /* This instruction template doesn't have VEX prefix. */
6114 if (i
.vec_encoding
!= vex_encoding_default
)
6116 i
.error
= unsupported
;
6125 static const insn_template
*
6126 match_template (char mnem_suffix
)
6128 /* Points to template once we've found it. */
6129 const insn_template
*t
;
6130 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6131 i386_operand_type overlap4
;
6132 unsigned int found_reverse_match
;
6133 i386_opcode_modifier suffix_check
;
6134 i386_operand_type operand_types
[MAX_OPERANDS
];
6135 int addr_prefix_disp
;
6136 unsigned int j
, size_match
, check_register
;
6137 enum i386_error specific_error
= 0;
6139 #if MAX_OPERANDS != 5
6140 # error "MAX_OPERANDS must be 5."
6143 found_reverse_match
= 0;
6144 addr_prefix_disp
= -1;
6146 /* Prepare for mnemonic suffix check. */
6147 memset (&suffix_check
, 0, sizeof (suffix_check
));
6148 switch (mnem_suffix
)
6150 case BYTE_MNEM_SUFFIX
:
6151 suffix_check
.no_bsuf
= 1;
6153 case WORD_MNEM_SUFFIX
:
6154 suffix_check
.no_wsuf
= 1;
6156 case SHORT_MNEM_SUFFIX
:
6157 suffix_check
.no_ssuf
= 1;
6159 case LONG_MNEM_SUFFIX
:
6160 suffix_check
.no_lsuf
= 1;
6162 case QWORD_MNEM_SUFFIX
:
6163 suffix_check
.no_qsuf
= 1;
6166 /* NB: In Intel syntax, normally we can check for memory operand
6167 size when there is no mnemonic suffix. But jmp and call have
6168 2 different encodings with Dword memory operand size, one with
6169 No_ldSuf and the other without. i.suffix is set to
6170 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6171 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6172 suffix_check
.no_ldsuf
= 1;
6175 /* Must have right number of operands. */
6176 i
.error
= number_of_operands_mismatch
;
6178 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6180 addr_prefix_disp
= -1;
6181 found_reverse_match
= 0;
6183 if (i
.operands
!= t
->operands
)
6186 /* Check processor support. */
6187 i
.error
= unsupported
;
6188 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6191 /* Check AT&T mnemonic. */
6192 i
.error
= unsupported_with_intel_mnemonic
;
6193 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6196 /* Check AT&T/Intel syntax. */
6197 i
.error
= unsupported_syntax
;
6198 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6199 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6202 /* Check Intel64/AMD64 ISA. */
6206 /* Default: Don't accept Intel64. */
6207 if (t
->opcode_modifier
.isa64
== INTEL64
)
6211 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6212 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6216 /* -mintel64: Don't accept AMD64. */
6217 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6222 /* Check the suffix. */
6223 i
.error
= invalid_instruction_suffix
;
6224 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6225 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6226 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6227 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6228 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6229 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6232 size_match
= operand_size_match (t
);
6236 /* This is intentionally not
6238 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6240 as the case of a missing * on the operand is accepted (perhaps with
6241 a warning, issued further down). */
6242 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6244 i
.error
= operand_type_mismatch
;
6248 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6249 operand_types
[j
] = t
->operand_types
[j
];
6251 /* In general, don't allow
6252 - 64-bit operands outside of 64-bit mode,
6253 - 32-bit operands on pre-386. */
6254 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6255 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6256 && flag_code
!= CODE_64BIT
6257 && (t
->base_opcode
!= 0x0fc7
6258 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6259 || (i
.suffix
== LONG_MNEM_SUFFIX
6260 && !cpu_arch_flags
.bitfield
.cpui386
))
6262 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6263 && !intel_float_operand (t
->name
))
6264 : intel_float_operand (t
->name
) != 2)
6265 && (t
->operands
== i
.imm_operands
6266 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6267 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6268 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6269 || (operand_types
[j
].bitfield
.class != RegMMX
6270 && operand_types
[j
].bitfield
.class != RegSIMD
6271 && operand_types
[j
].bitfield
.class != RegMask
))
6272 && !t
->opcode_modifier
.vecsib
)
6275 /* Do not verify operands when there are none. */
6278 if (VEX_check_encoding (t
))
6280 specific_error
= i
.error
;
6284 /* We've found a match; break out of loop. */
6288 if (!t
->opcode_modifier
.jump
6289 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6291 /* There should be only one Disp operand. */
6292 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6293 if (operand_type_check (operand_types
[j
], disp
))
6295 if (j
< MAX_OPERANDS
)
6297 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6299 addr_prefix_disp
= j
;
6301 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6302 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6306 override
= !override
;
6309 if (operand_types
[j
].bitfield
.disp32
6310 && operand_types
[j
].bitfield
.disp16
)
6312 operand_types
[j
].bitfield
.disp16
= override
;
6313 operand_types
[j
].bitfield
.disp32
= !override
;
6315 operand_types
[j
].bitfield
.disp32s
= 0;
6316 operand_types
[j
].bitfield
.disp64
= 0;
6320 if (operand_types
[j
].bitfield
.disp32s
6321 || operand_types
[j
].bitfield
.disp64
)
6323 operand_types
[j
].bitfield
.disp64
&= !override
;
6324 operand_types
[j
].bitfield
.disp32s
&= !override
;
6325 operand_types
[j
].bitfield
.disp32
= override
;
6327 operand_types
[j
].bitfield
.disp16
= 0;
6333 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6334 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6337 /* We check register size if needed. */
6338 if (t
->opcode_modifier
.checkregsize
)
6340 check_register
= (1 << t
->operands
) - 1;
6342 check_register
&= ~(1 << i
.broadcast
->operand
);
6347 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6348 switch (t
->operands
)
6351 if (!operand_type_match (overlap0
, i
.types
[0]))
6355 /* xchg %eax, %eax is a special case. It is an alias for nop
6356 only in 32bit mode and we can use opcode 0x90. In 64bit
6357 mode, we can't use 0x90 for xchg %eax, %eax since it should
6358 zero-extend %eax to %rax. */
6359 if (flag_code
== CODE_64BIT
6360 && t
->base_opcode
== 0x90
6361 && i
.types
[0].bitfield
.instance
== Accum
6362 && i
.types
[0].bitfield
.dword
6363 && i
.types
[1].bitfield
.instance
== Accum
6364 && i
.types
[1].bitfield
.dword
)
6366 /* xrelease mov %eax, <disp> is another special case. It must not
6367 match the accumulator-only encoding of mov. */
6368 if (flag_code
!= CODE_64BIT
6370 && t
->base_opcode
== 0xa0
6371 && i
.types
[0].bitfield
.instance
== Accum
6372 && (i
.flags
[1] & Operand_Mem
))
6377 if (!(size_match
& MATCH_STRAIGHT
))
6379 /* Reverse direction of operands if swapping is possible in the first
6380 place (operands need to be symmetric) and
6381 - the load form is requested, and the template is a store form,
6382 - the store form is requested, and the template is a load form,
6383 - the non-default (swapped) form is requested. */
6384 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6385 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6386 && !operand_type_all_zero (&overlap1
))
6387 switch (i
.dir_encoding
)
6389 case dir_encoding_load
:
6390 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6391 || t
->opcode_modifier
.regmem
)
6395 case dir_encoding_store
:
6396 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6397 && !t
->opcode_modifier
.regmem
)
6401 case dir_encoding_swap
:
6404 case dir_encoding_default
:
6407 /* If we want store form, we skip the current load. */
6408 if ((i
.dir_encoding
== dir_encoding_store
6409 || i
.dir_encoding
== dir_encoding_swap
)
6410 && i
.mem_operands
== 0
6411 && t
->opcode_modifier
.load
)
6416 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6417 if (!operand_type_match (overlap0
, i
.types
[0])
6418 || !operand_type_match (overlap1
, i
.types
[1])
6419 || ((check_register
& 3) == 3
6420 && !operand_type_register_match (i
.types
[0],
6425 /* Check if other direction is valid ... */
6426 if (!t
->opcode_modifier
.d
)
6430 if (!(size_match
& MATCH_REVERSE
))
6432 /* Try reversing direction of operands. */
6433 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6434 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6435 if (!operand_type_match (overlap0
, i
.types
[0])
6436 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6438 && !operand_type_register_match (i
.types
[0],
6439 operand_types
[i
.operands
- 1],
6440 i
.types
[i
.operands
- 1],
6443 /* Does not match either direction. */
6446 /* found_reverse_match holds which of D or FloatR
6448 if (!t
->opcode_modifier
.d
)
6449 found_reverse_match
= 0;
6450 else if (operand_types
[0].bitfield
.tbyte
)
6451 found_reverse_match
= Opcode_FloatD
;
6452 else if (operand_types
[0].bitfield
.xmmword
6453 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6454 || operand_types
[0].bitfield
.class == RegMMX
6455 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6456 || is_any_vex_encoding(t
))
6457 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6458 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6460 found_reverse_match
= Opcode_D
;
6461 if (t
->opcode_modifier
.floatr
)
6462 found_reverse_match
|= Opcode_FloatR
;
6466 /* Found a forward 2 operand match here. */
6467 switch (t
->operands
)
6470 overlap4
= operand_type_and (i
.types
[4],
6474 overlap3
= operand_type_and (i
.types
[3],
6478 overlap2
= operand_type_and (i
.types
[2],
6483 switch (t
->operands
)
6486 if (!operand_type_match (overlap4
, i
.types
[4])
6487 || !operand_type_register_match (i
.types
[3],
6494 if (!operand_type_match (overlap3
, i
.types
[3])
6495 || ((check_register
& 0xa) == 0xa
6496 && !operand_type_register_match (i
.types
[1],
6500 || ((check_register
& 0xc) == 0xc
6501 && !operand_type_register_match (i
.types
[2],
6508 /* Here we make use of the fact that there are no
6509 reverse match 3 operand instructions. */
6510 if (!operand_type_match (overlap2
, i
.types
[2])
6511 || ((check_register
& 5) == 5
6512 && !operand_type_register_match (i
.types
[0],
6516 || ((check_register
& 6) == 6
6517 && !operand_type_register_match (i
.types
[1],
6525 /* Found either forward/reverse 2, 3 or 4 operand match here:
6526 slip through to break. */
6529 /* Check if vector operands are valid. */
6530 if (check_VecOperands (t
))
6532 specific_error
= i
.error
;
6536 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6537 if (VEX_check_encoding (t
))
6539 specific_error
= i
.error
;
6543 /* We've found a match; break out of loop. */
6547 if (t
== current_templates
->end
)
6549 /* We found no match. */
6550 const char *err_msg
;
6551 switch (specific_error
? specific_error
: i
.error
)
6555 case operand_size_mismatch
:
6556 err_msg
= _("operand size mismatch");
6558 case operand_type_mismatch
:
6559 err_msg
= _("operand type mismatch");
6561 case register_type_mismatch
:
6562 err_msg
= _("register type mismatch");
6564 case number_of_operands_mismatch
:
6565 err_msg
= _("number of operands mismatch");
6567 case invalid_instruction_suffix
:
6568 err_msg
= _("invalid instruction suffix");
6571 err_msg
= _("constant doesn't fit in 4 bits");
6573 case unsupported_with_intel_mnemonic
:
6574 err_msg
= _("unsupported with Intel mnemonic");
6576 case unsupported_syntax
:
6577 err_msg
= _("unsupported syntax");
6580 as_bad (_("unsupported instruction `%s'"),
6581 current_templates
->start
->name
);
6583 case invalid_vsib_address
:
6584 err_msg
= _("invalid VSIB address");
6586 case invalid_vector_register_set
:
6587 err_msg
= _("mask, index, and destination registers must be distinct");
6589 case unsupported_vector_index_register
:
6590 err_msg
= _("unsupported vector index register");
6592 case unsupported_broadcast
:
6593 err_msg
= _("unsupported broadcast");
6595 case broadcast_needed
:
6596 err_msg
= _("broadcast is needed for operand of such type");
6598 case unsupported_masking
:
6599 err_msg
= _("unsupported masking");
6601 case mask_not_on_destination
:
6602 err_msg
= _("mask not on destination operand");
6604 case no_default_mask
:
6605 err_msg
= _("default mask isn't allowed");
6607 case unsupported_rc_sae
:
6608 err_msg
= _("unsupported static rounding/sae");
6610 case rc_sae_operand_not_last_imm
:
6612 err_msg
= _("RC/SAE operand must precede immediate operands");
6614 err_msg
= _("RC/SAE operand must follow immediate operands");
6616 case invalid_register_operand
:
6617 err_msg
= _("invalid register operand");
6620 as_bad (_("%s for `%s'"), err_msg
,
6621 current_templates
->start
->name
);
6625 if (!quiet_warnings
)
6628 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6629 as_warn (_("indirect %s without `*'"), t
->name
);
6631 if (t
->opcode_modifier
.isprefix
6632 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6634 /* Warn them that a data or address size prefix doesn't
6635 affect assembly of the next line of code. */
6636 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6640 /* Copy the template we found. */
6643 if (addr_prefix_disp
!= -1)
6644 i
.tm
.operand_types
[addr_prefix_disp
]
6645 = operand_types
[addr_prefix_disp
];
6647 if (found_reverse_match
)
6649 /* If we found a reverse match we must alter the opcode direction
6650 bit and clear/flip the regmem modifier one. found_reverse_match
6651 holds bits to change (different for int & float insns). */
6653 i
.tm
.base_opcode
^= found_reverse_match
;
6655 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6656 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6658 /* Certain SIMD insns have their load forms specified in the opcode
6659 table, and hence we need to _set_ RegMem instead of clearing it.
6660 We need to avoid setting the bit though on insns like KMOVW. */
6661 i
.tm
.opcode_modifier
.regmem
6662 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6663 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6664 && !i
.tm
.opcode_modifier
.regmem
;
6673 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6674 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6676 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6678 as_bad (_("`%s' operand %u must use `%ses' segment"),
6680 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6685 /* There's only ever one segment override allowed per instruction.
6686 This instruction possibly has a legal segment override on the
6687 second operand, so copy the segment to where non-string
6688 instructions store it, allowing common code. */
6689 i
.seg
[op
] = i
.seg
[1];
6695 process_suffix (void)
6697 /* If matched instruction specifies an explicit instruction mnemonic
6699 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6700 i
.suffix
= WORD_MNEM_SUFFIX
;
6701 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6702 i
.suffix
= LONG_MNEM_SUFFIX
;
6703 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6704 i
.suffix
= QWORD_MNEM_SUFFIX
;
6705 else if (i
.reg_operands
6706 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6707 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6709 unsigned int numop
= i
.operands
;
6711 /* movsx/movzx want only their source operand considered here, for the
6712 ambiguity checking below. The suffix will be replaced afterwards
6713 to represent the destination (register). */
6714 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6715 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6718 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6719 if (i
.tm
.base_opcode
== 0xf20f38f0
6720 && i
.tm
.operand_types
[1].bitfield
.qword
)
6723 /* If there's no instruction mnemonic suffix we try to invent one
6724 based on GPR operands. */
6727 /* We take i.suffix from the last register operand specified,
6728 Destination register type is more significant than source
6729 register type. crc32 in SSE4.2 prefers source register
6731 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6734 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6735 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6737 if (i
.types
[op
].bitfield
.class != Reg
)
6739 if (i
.types
[op
].bitfield
.byte
)
6740 i
.suffix
= BYTE_MNEM_SUFFIX
;
6741 else if (i
.types
[op
].bitfield
.word
)
6742 i
.suffix
= WORD_MNEM_SUFFIX
;
6743 else if (i
.types
[op
].bitfield
.dword
)
6744 i
.suffix
= LONG_MNEM_SUFFIX
;
6745 else if (i
.types
[op
].bitfield
.qword
)
6746 i
.suffix
= QWORD_MNEM_SUFFIX
;
6752 /* As an exception, movsx/movzx silently default to a byte source
6754 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6755 && !i
.suffix
&& !intel_syntax
)
6756 i
.suffix
= BYTE_MNEM_SUFFIX
;
6758 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6761 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6762 && i
.tm
.opcode_modifier
.no_bsuf
)
6764 else if (!check_byte_reg ())
6767 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6770 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6771 && i
.tm
.opcode_modifier
.no_lsuf
6772 && !i
.tm
.opcode_modifier
.todword
6773 && !i
.tm
.opcode_modifier
.toqword
)
6775 else if (!check_long_reg ())
6778 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6781 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6782 && i
.tm
.opcode_modifier
.no_qsuf
6783 && !i
.tm
.opcode_modifier
.todword
6784 && !i
.tm
.opcode_modifier
.toqword
)
6786 else if (!check_qword_reg ())
6789 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6792 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6793 && i
.tm
.opcode_modifier
.no_wsuf
)
6795 else if (!check_word_reg ())
6798 else if (intel_syntax
6799 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6800 /* Do nothing if the instruction is going to ignore the prefix. */
6805 /* Undo the movsx/movzx change done above. */
6808 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6811 i
.suffix
= stackop_size
;
6812 if (stackop_size
== LONG_MNEM_SUFFIX
)
6814 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6815 .code16gcc directive to support 16-bit mode with
6816 32-bit address. For IRET without a suffix, generate
6817 16-bit IRET (opcode 0xcf) to return from an interrupt
6819 if (i
.tm
.base_opcode
== 0xcf)
6821 i
.suffix
= WORD_MNEM_SUFFIX
;
6822 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6824 /* Warn about changed behavior for segment register push/pop. */
6825 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6826 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6831 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6832 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6833 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6834 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6835 && i
.tm
.extension_opcode
<= 3)))
6840 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6842 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6843 || i
.tm
.opcode_modifier
.no_lsuf
)
6844 i
.suffix
= QWORD_MNEM_SUFFIX
;
6849 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6850 i
.suffix
= LONG_MNEM_SUFFIX
;
6853 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6854 i
.suffix
= WORD_MNEM_SUFFIX
;
6860 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6861 /* Also cover lret/retf/iret in 64-bit mode. */
6862 || (flag_code
== CODE_64BIT
6863 && !i
.tm
.opcode_modifier
.no_lsuf
6864 && !i
.tm
.opcode_modifier
.no_qsuf
))
6865 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6866 /* Accept FLDENV et al without suffix. */
6867 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6869 unsigned int suffixes
, evex
= 0;
6871 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6872 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6874 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6876 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6878 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6880 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6883 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6884 also suitable for AT&T syntax mode, it was requested that this be
6885 restricted to just Intel syntax. */
6886 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6890 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6892 if (is_evex_encoding (&i
.tm
)
6893 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6895 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6896 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6897 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6898 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6899 if (!i
.tm
.opcode_modifier
.evex
6900 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6901 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6904 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6905 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6906 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6909 /* Any properly sized operand disambiguates the insn. */
6910 if (i
.types
[op
].bitfield
.xmmword
6911 || i
.types
[op
].bitfield
.ymmword
6912 || i
.types
[op
].bitfield
.zmmword
)
6914 suffixes
&= ~(7 << 6);
6919 if ((i
.flags
[op
] & Operand_Mem
)
6920 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6922 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6924 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6926 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6928 if (is_evex_encoding (&i
.tm
))
6934 /* Are multiple suffixes / operand sizes allowed? */
6935 if (suffixes
& (suffixes
- 1))
6938 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6939 || operand_check
== check_error
))
6941 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6944 if (operand_check
== check_error
)
6946 as_bad (_("no instruction mnemonic suffix given and "
6947 "no register operands; can't size `%s'"), i
.tm
.name
);
6950 if (operand_check
== check_warning
)
6951 as_warn (_("%s; using default for `%s'"),
6953 ? _("ambiguous operand size")
6954 : _("no instruction mnemonic suffix given and "
6955 "no register operands"),
6958 if (i
.tm
.opcode_modifier
.floatmf
)
6959 i
.suffix
= SHORT_MNEM_SUFFIX
;
6960 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6961 || (i
.tm
.base_opcode
== 0x63
6962 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6963 /* handled below */;
6965 i
.tm
.opcode_modifier
.evex
= evex
;
6966 else if (flag_code
== CODE_16BIT
)
6967 i
.suffix
= WORD_MNEM_SUFFIX
;
6968 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6969 i
.suffix
= LONG_MNEM_SUFFIX
;
6971 i
.suffix
= QWORD_MNEM_SUFFIX
;
6975 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6976 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6978 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6979 In AT&T syntax, if there is no suffix (warned about above), the default
6980 will be byte extension. */
6981 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6982 i
.tm
.base_opcode
|= 1;
6984 /* For further processing, the suffix should represent the destination
6985 (register). This is already the case when one was used with
6986 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6987 no suffix to begin with. */
6988 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6990 if (i
.types
[1].bitfield
.word
)
6991 i
.suffix
= WORD_MNEM_SUFFIX
;
6992 else if (i
.types
[1].bitfield
.qword
)
6993 i
.suffix
= QWORD_MNEM_SUFFIX
;
6995 i
.suffix
= LONG_MNEM_SUFFIX
;
6997 i
.tm
.opcode_modifier
.w
= 0;
7001 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7002 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7003 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7005 /* Change the opcode based on the operand size given by i.suffix. */
7008 /* Size floating point instruction. */
7009 case LONG_MNEM_SUFFIX
:
7010 if (i
.tm
.opcode_modifier
.floatmf
)
7012 i
.tm
.base_opcode
^= 4;
7016 case WORD_MNEM_SUFFIX
:
7017 case QWORD_MNEM_SUFFIX
:
7018 /* It's not a byte, select word/dword operation. */
7019 if (i
.tm
.opcode_modifier
.w
)
7022 i
.tm
.base_opcode
|= 8;
7024 i
.tm
.base_opcode
|= 1;
7027 case SHORT_MNEM_SUFFIX
:
7028 /* Now select between word & dword operations via the operand
7029 size prefix, except for instructions that will ignore this
7031 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7032 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7033 && !i
.tm
.opcode_modifier
.floatmf
7034 && !is_any_vex_encoding (&i
.tm
)
7035 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7036 || (flag_code
== CODE_64BIT
7037 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7039 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7041 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7042 prefix
= ADDR_PREFIX_OPCODE
;
7044 if (!add_prefix (prefix
))
7048 /* Set mode64 for an operand. */
7049 if (i
.suffix
== QWORD_MNEM_SUFFIX
7050 && flag_code
== CODE_64BIT
7051 && !i
.tm
.opcode_modifier
.norex64
7052 && !i
.tm
.opcode_modifier
.vexw
7053 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7055 && ! (i
.operands
== 2
7056 && i
.tm
.base_opcode
== 0x90
7057 && i
.tm
.extension_opcode
== None
7058 && i
.types
[0].bitfield
.instance
== Accum
7059 && i
.types
[0].bitfield
.qword
7060 && i
.types
[1].bitfield
.instance
== Accum
7061 && i
.types
[1].bitfield
.qword
))
7067 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7069 gas_assert (!i
.suffix
);
7070 gas_assert (i
.reg_operands
);
7072 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7075 /* The address size override prefix changes the size of the
7077 if (flag_code
== CODE_64BIT
7078 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7080 as_bad (_("16-bit addressing unavailable for `%s'"),
7085 if ((flag_code
== CODE_32BIT
7086 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7087 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7088 && !add_prefix (ADDR_PREFIX_OPCODE
))
7093 /* Check invalid register operand when the address size override
7094 prefix changes the size of register operands. */
7096 enum { need_word
, need_dword
, need_qword
} need
;
7098 if (flag_code
== CODE_32BIT
)
7099 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7100 else if (i
.prefix
[ADDR_PREFIX
])
7103 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7105 for (op
= 0; op
< i
.operands
; op
++)
7107 if (i
.types
[op
].bitfield
.class != Reg
)
7113 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7117 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7121 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7126 as_bad (_("invalid register operand size for `%s'"),
7137 check_byte_reg (void)
7141 for (op
= i
.operands
; --op
>= 0;)
7143 /* Skip non-register operands. */
7144 if (i
.types
[op
].bitfield
.class != Reg
)
7147 /* If this is an eight bit register, it's OK. If it's the 16 or
7148 32 bit version of an eight bit register, we will just use the
7149 low portion, and that's OK too. */
7150 if (i
.types
[op
].bitfield
.byte
)
7153 /* I/O port address operands are OK too. */
7154 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7155 && i
.tm
.operand_types
[op
].bitfield
.word
)
7158 /* crc32 only wants its source operand checked here. */
7159 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7162 /* Any other register is bad. */
7163 as_bad (_("`%s%s' not allowed with `%s%c'"),
7164 register_prefix
, i
.op
[op
].regs
->reg_name
,
7165 i
.tm
.name
, i
.suffix
);
7172 check_long_reg (void)
7176 for (op
= i
.operands
; --op
>= 0;)
7177 /* Skip non-register operands. */
7178 if (i
.types
[op
].bitfield
.class != Reg
)
7180 /* Reject eight bit registers, except where the template requires
7181 them. (eg. movzb) */
7182 else if (i
.types
[op
].bitfield
.byte
7183 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7184 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7185 && (i
.tm
.operand_types
[op
].bitfield
.word
7186 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7188 as_bad (_("`%s%s' not allowed with `%s%c'"),
7190 i
.op
[op
].regs
->reg_name
,
7195 /* Error if the e prefix on a general reg is missing. */
7196 else if (i
.types
[op
].bitfield
.word
7197 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7198 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7199 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7201 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7202 register_prefix
, i
.op
[op
].regs
->reg_name
,
7206 /* Warn if the r prefix on a general reg is present. */
7207 else if (i
.types
[op
].bitfield
.qword
7208 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7209 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7210 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7213 && i
.tm
.opcode_modifier
.toqword
7214 && i
.types
[0].bitfield
.class != RegSIMD
)
7216 /* Convert to QWORD. We want REX byte. */
7217 i
.suffix
= QWORD_MNEM_SUFFIX
;
7221 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7222 register_prefix
, i
.op
[op
].regs
->reg_name
,
7231 check_qword_reg (void)
7235 for (op
= i
.operands
; --op
>= 0; )
7236 /* Skip non-register operands. */
7237 if (i
.types
[op
].bitfield
.class != Reg
)
7239 /* Reject eight bit registers, except where the template requires
7240 them. (eg. movzb) */
7241 else if (i
.types
[op
].bitfield
.byte
7242 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7243 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7244 && (i
.tm
.operand_types
[op
].bitfield
.word
7245 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7247 as_bad (_("`%s%s' not allowed with `%s%c'"),
7249 i
.op
[op
].regs
->reg_name
,
7254 /* Warn if the r prefix on a general reg is missing. */
7255 else if ((i
.types
[op
].bitfield
.word
7256 || i
.types
[op
].bitfield
.dword
)
7257 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7258 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7259 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7261 /* Prohibit these changes in the 64bit mode, since the
7262 lowering is more complicated. */
7264 && i
.tm
.opcode_modifier
.todword
7265 && i
.types
[0].bitfield
.class != RegSIMD
)
7267 /* Convert to DWORD. We don't want REX byte. */
7268 i
.suffix
= LONG_MNEM_SUFFIX
;
7272 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7273 register_prefix
, i
.op
[op
].regs
->reg_name
,
7282 check_word_reg (void)
7285 for (op
= i
.operands
; --op
>= 0;)
7286 /* Skip non-register operands. */
7287 if (i
.types
[op
].bitfield
.class != Reg
)
7289 /* Reject eight bit registers, except where the template requires
7290 them. (eg. movzb) */
7291 else if (i
.types
[op
].bitfield
.byte
7292 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7293 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7294 && (i
.tm
.operand_types
[op
].bitfield
.word
7295 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7297 as_bad (_("`%s%s' not allowed with `%s%c'"),
7299 i
.op
[op
].regs
->reg_name
,
7304 /* Error if the e or r prefix on a general reg is present. */
7305 else if ((i
.types
[op
].bitfield
.dword
7306 || i
.types
[op
].bitfield
.qword
)
7307 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7308 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7309 && i
.tm
.operand_types
[op
].bitfield
.word
)
7311 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7312 register_prefix
, i
.op
[op
].regs
->reg_name
,
7320 update_imm (unsigned int j
)
7322 i386_operand_type overlap
= i
.types
[j
];
7323 if ((overlap
.bitfield
.imm8
7324 || overlap
.bitfield
.imm8s
7325 || overlap
.bitfield
.imm16
7326 || overlap
.bitfield
.imm32
7327 || overlap
.bitfield
.imm32s
7328 || overlap
.bitfield
.imm64
)
7329 && !operand_type_equal (&overlap
, &imm8
)
7330 && !operand_type_equal (&overlap
, &imm8s
)
7331 && !operand_type_equal (&overlap
, &imm16
)
7332 && !operand_type_equal (&overlap
, &imm32
)
7333 && !operand_type_equal (&overlap
, &imm32s
)
7334 && !operand_type_equal (&overlap
, &imm64
))
7338 i386_operand_type temp
;
7340 operand_type_set (&temp
, 0);
7341 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7343 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7344 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7346 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7347 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7348 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7350 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7351 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7354 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7357 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7358 || operand_type_equal (&overlap
, &imm16_32
)
7359 || operand_type_equal (&overlap
, &imm16_32s
))
7361 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7366 if (!operand_type_equal (&overlap
, &imm8
)
7367 && !operand_type_equal (&overlap
, &imm8s
)
7368 && !operand_type_equal (&overlap
, &imm16
)
7369 && !operand_type_equal (&overlap
, &imm32
)
7370 && !operand_type_equal (&overlap
, &imm32s
)
7371 && !operand_type_equal (&overlap
, &imm64
))
7373 as_bad (_("no instruction mnemonic suffix given; "
7374 "can't determine immediate size"));
7378 i
.types
[j
] = overlap
;
7388 /* Update the first 2 immediate operands. */
7389 n
= i
.operands
> 2 ? 2 : i
.operands
;
7392 for (j
= 0; j
< n
; j
++)
7393 if (update_imm (j
) == 0)
7396 /* The 3rd operand can't be immediate operand. */
7397 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7404 process_operands (void)
7406 /* Default segment register this instruction will use for memory
7407 accesses. 0 means unknown. This is only for optimizing out
7408 unnecessary segment overrides. */
7409 const seg_entry
*default_seg
= 0;
7411 if (i
.tm
.opcode_modifier
.sse2avx
)
7413 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7415 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7416 i
.prefix
[REX_PREFIX
] = 0;
7420 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7422 unsigned int dupl
= i
.operands
;
7423 unsigned int dest
= dupl
- 1;
7426 /* The destination must be an xmm register. */
7427 gas_assert (i
.reg_operands
7428 && MAX_OPERANDS
> dupl
7429 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7431 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7432 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7434 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7436 /* Keep xmm0 for instructions with VEX prefix and 3
7438 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7439 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7444 /* We remove the first xmm0 and keep the number of
7445 operands unchanged, which in fact duplicates the
7447 for (j
= 1; j
< i
.operands
; j
++)
7449 i
.op
[j
- 1] = i
.op
[j
];
7450 i
.types
[j
- 1] = i
.types
[j
];
7451 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7452 i
.flags
[j
- 1] = i
.flags
[j
];
7456 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7458 gas_assert ((MAX_OPERANDS
- 1) > dupl
7459 && (i
.tm
.opcode_modifier
.vexsources
7462 /* Add the implicit xmm0 for instructions with VEX prefix
7464 for (j
= i
.operands
; j
> 0; j
--)
7466 i
.op
[j
] = i
.op
[j
- 1];
7467 i
.types
[j
] = i
.types
[j
- 1];
7468 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7469 i
.flags
[j
] = i
.flags
[j
- 1];
7472 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7473 i
.types
[0] = regxmm
;
7474 i
.tm
.operand_types
[0] = regxmm
;
7477 i
.reg_operands
+= 2;
7482 i
.op
[dupl
] = i
.op
[dest
];
7483 i
.types
[dupl
] = i
.types
[dest
];
7484 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7485 i
.flags
[dupl
] = i
.flags
[dest
];
7494 i
.op
[dupl
] = i
.op
[dest
];
7495 i
.types
[dupl
] = i
.types
[dest
];
7496 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7497 i
.flags
[dupl
] = i
.flags
[dest
];
7500 if (i
.tm
.opcode_modifier
.immext
)
7503 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7504 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7508 for (j
= 1; j
< i
.operands
; j
++)
7510 i
.op
[j
- 1] = i
.op
[j
];
7511 i
.types
[j
- 1] = i
.types
[j
];
7513 /* We need to adjust fields in i.tm since they are used by
7514 build_modrm_byte. */
7515 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7517 i
.flags
[j
- 1] = i
.flags
[j
];
7524 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7526 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7528 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7529 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7530 regnum
= register_number (i
.op
[1].regs
);
7531 first_reg_in_group
= regnum
& ~3;
7532 last_reg_in_group
= first_reg_in_group
+ 3;
7533 if (regnum
!= first_reg_in_group
)
7534 as_warn (_("source register `%s%s' implicitly denotes"
7535 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7536 register_prefix
, i
.op
[1].regs
->reg_name
,
7537 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7538 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7541 else if (i
.tm
.opcode_modifier
.regkludge
)
7543 /* The imul $imm, %reg instruction is converted into
7544 imul $imm, %reg, %reg, and the clr %reg instruction
7545 is converted into xor %reg, %reg. */
7547 unsigned int first_reg_op
;
7549 if (operand_type_check (i
.types
[0], reg
))
7553 /* Pretend we saw the extra register operand. */
7554 gas_assert (i
.reg_operands
== 1
7555 && i
.op
[first_reg_op
+ 1].regs
== 0);
7556 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7557 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7562 if (i
.tm
.opcode_modifier
.modrm
)
7564 /* The opcode is completed (modulo i.tm.extension_opcode which
7565 must be put into the modrm byte). Now, we make the modrm and
7566 index base bytes based on all the info we've collected. */
7568 default_seg
= build_modrm_byte ();
7570 else if (i
.types
[0].bitfield
.class == SReg
)
7572 if (flag_code
!= CODE_64BIT
7573 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7574 && i
.op
[0].regs
->reg_num
== 1
7575 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7576 && i
.op
[0].regs
->reg_num
< 4)
7578 as_bad (_("you can't `%s %s%s'"),
7579 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7582 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7584 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7585 i
.tm
.opcode_length
= 2;
7587 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7589 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7593 else if (i
.tm
.opcode_modifier
.isstring
)
7595 /* For the string instructions that allow a segment override
7596 on one of their operands, the default segment is ds. */
7599 else if (i
.short_form
)
7601 /* The register or float register operand is in operand
7603 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7605 /* Register goes in low 3 bits of opcode. */
7606 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7607 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7609 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7611 /* Warn about some common errors, but press on regardless.
7612 The first case can be generated by gcc (<= 2.8.1). */
7613 if (i
.operands
== 2)
7615 /* Reversed arguments on faddp, fsubp, etc. */
7616 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7617 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7618 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7622 /* Extraneous `l' suffix on fp insn. */
7623 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7624 register_prefix
, i
.op
[0].regs
->reg_name
);
7629 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7630 && i
.tm
.base_opcode
== 0x8d /* lea */
7631 && !is_any_vex_encoding(&i
.tm
))
7633 if (!quiet_warnings
)
7634 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7638 i
.prefix
[SEG_PREFIX
] = 0;
7642 /* If a segment was explicitly specified, and the specified segment
7643 is neither the default nor the one already recorded from a prefix,
7644 use an opcode prefix to select it. If we never figured out what
7645 the default segment is, then default_seg will be zero at this
7646 point, and the specified segment prefix will always be used. */
7648 && i
.seg
[0] != default_seg
7649 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7651 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7657 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7658 bfd_boolean do_sse2avx
)
7660 if (r
->reg_flags
& RegRex
)
7662 if (i
.rex
& rex_bit
)
7663 as_bad (_("same type of prefix used twice"));
7666 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7668 gas_assert (i
.vex
.register_specifier
== r
);
7669 i
.vex
.register_specifier
+= 8;
7672 if (r
->reg_flags
& RegVRex
)
7676 static const seg_entry
*
7677 build_modrm_byte (void)
7679 const seg_entry
*default_seg
= 0;
7680 unsigned int source
, dest
;
7683 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7686 unsigned int nds
, reg_slot
;
7689 dest
= i
.operands
- 1;
7692 /* There are 2 kinds of instructions:
7693 1. 5 operands: 4 register operands or 3 register operands
7694 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7695 VexW0 or VexW1. The destination must be either XMM, YMM or
7697 2. 4 operands: 4 register operands or 3 register operands
7698 plus 1 memory operand, with VexXDS. */
7699 gas_assert ((i
.reg_operands
== 4
7700 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7701 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7702 && i
.tm
.opcode_modifier
.vexw
7703 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7705 /* If VexW1 is set, the first non-immediate operand is the source and
7706 the second non-immediate one is encoded in the immediate operand. */
7707 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7709 source
= i
.imm_operands
;
7710 reg_slot
= i
.imm_operands
+ 1;
7714 source
= i
.imm_operands
+ 1;
7715 reg_slot
= i
.imm_operands
;
7718 if (i
.imm_operands
== 0)
7720 /* When there is no immediate operand, generate an 8bit
7721 immediate operand to encode the first operand. */
7722 exp
= &im_expressions
[i
.imm_operands
++];
7723 i
.op
[i
.operands
].imms
= exp
;
7724 i
.types
[i
.operands
] = imm8
;
7727 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7728 exp
->X_op
= O_constant
;
7729 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7730 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7734 gas_assert (i
.imm_operands
== 1);
7735 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7736 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7738 /* Turn on Imm8 again so that output_imm will generate it. */
7739 i
.types
[0].bitfield
.imm8
= 1;
7741 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7742 i
.op
[0].imms
->X_add_number
7743 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7744 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7747 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7748 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7753 /* i.reg_operands MUST be the number of real register operands;
7754 implicit registers do not count. If there are 3 register
7755 operands, it must be a instruction with VexNDS. For a
7756 instruction with VexNDD, the destination register is encoded
7757 in VEX prefix. If there are 4 register operands, it must be
7758 a instruction with VEX prefix and 3 sources. */
7759 if (i
.mem_operands
== 0
7760 && ((i
.reg_operands
== 2
7761 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7762 || (i
.reg_operands
== 3
7763 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7764 || (i
.reg_operands
== 4 && vex_3_sources
)))
7772 /* When there are 3 operands, one of them may be immediate,
7773 which may be the first or the last operand. Otherwise,
7774 the first operand must be shift count register (cl) or it
7775 is an instruction with VexNDS. */
7776 gas_assert (i
.imm_operands
== 1
7777 || (i
.imm_operands
== 0
7778 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7779 || (i
.types
[0].bitfield
.instance
== RegC
7780 && i
.types
[0].bitfield
.byte
))));
7781 if (operand_type_check (i
.types
[0], imm
)
7782 || (i
.types
[0].bitfield
.instance
== RegC
7783 && i
.types
[0].bitfield
.byte
))
7789 /* When there are 4 operands, the first two must be 8bit
7790 immediate operands. The source operand will be the 3rd
7793 For instructions with VexNDS, if the first operand
7794 an imm8, the source operand is the 2nd one. If the last
7795 operand is imm8, the source operand is the first one. */
7796 gas_assert ((i
.imm_operands
== 2
7797 && i
.types
[0].bitfield
.imm8
7798 && i
.types
[1].bitfield
.imm8
)
7799 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7800 && i
.imm_operands
== 1
7801 && (i
.types
[0].bitfield
.imm8
7802 || i
.types
[i
.operands
- 1].bitfield
.imm8
7804 if (i
.imm_operands
== 2)
7808 if (i
.types
[0].bitfield
.imm8
)
7815 if (is_evex_encoding (&i
.tm
))
7817 /* For EVEX instructions, when there are 5 operands, the
7818 first one must be immediate operand. If the second one
7819 is immediate operand, the source operand is the 3th
7820 one. If the last one is immediate operand, the source
7821 operand is the 2nd one. */
7822 gas_assert (i
.imm_operands
== 2
7823 && i
.tm
.opcode_modifier
.sae
7824 && operand_type_check (i
.types
[0], imm
));
7825 if (operand_type_check (i
.types
[1], imm
))
7827 else if (operand_type_check (i
.types
[4], imm
))
7841 /* RC/SAE operand could be between DEST and SRC. That happens
7842 when one operand is GPR and the other one is XMM/YMM/ZMM
7844 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7847 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7849 /* For instructions with VexNDS, the register-only source
7850 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7851 register. It is encoded in VEX prefix. */
7853 i386_operand_type op
;
7856 /* Check register-only source operand when two source
7857 operands are swapped. */
7858 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7859 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7867 op
= i
.tm
.operand_types
[vvvv
];
7868 if ((dest
+ 1) >= i
.operands
7869 || ((op
.bitfield
.class != Reg
7870 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7871 && op
.bitfield
.class != RegSIMD
7872 && !operand_type_equal (&op
, ®mask
)))
7874 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7880 /* One of the register operands will be encoded in the i.rm.reg
7881 field, the other in the combined i.rm.mode and i.rm.regmem
7882 fields. If no form of this instruction supports a memory
7883 destination operand, then we assume the source operand may
7884 sometimes be a memory operand and so we need to store the
7885 destination in the i.rm.reg field. */
7886 if (!i
.tm
.opcode_modifier
.regmem
7887 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7889 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7890 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7891 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7892 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7893 i
.has_regmmx
= TRUE
;
7894 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7895 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7897 if (i
.types
[dest
].bitfield
.zmmword
7898 || i
.types
[source
].bitfield
.zmmword
)
7899 i
.has_regzmm
= TRUE
;
7900 else if (i
.types
[dest
].bitfield
.ymmword
7901 || i
.types
[source
].bitfield
.ymmword
)
7902 i
.has_regymm
= TRUE
;
7904 i
.has_regxmm
= TRUE
;
7906 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
7907 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
7911 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7912 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7913 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
7914 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
7916 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7918 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7921 add_prefix (LOCK_PREFIX_OPCODE
);
7925 { /* If it's not 2 reg operands... */
7930 unsigned int fake_zero_displacement
= 0;
7933 for (op
= 0; op
< i
.operands
; op
++)
7934 if (i
.flags
[op
] & Operand_Mem
)
7936 gas_assert (op
< i
.operands
);
7938 if (i
.tm
.opcode_modifier
.vecsib
)
7940 if (i
.index_reg
->reg_num
== RegIZ
)
7943 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7946 i
.sib
.base
= NO_BASE_REGISTER
;
7947 i
.sib
.scale
= i
.log2_scale_factor
;
7948 i
.types
[op
].bitfield
.disp8
= 0;
7949 i
.types
[op
].bitfield
.disp16
= 0;
7950 i
.types
[op
].bitfield
.disp64
= 0;
7951 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7953 /* Must be 32 bit */
7954 i
.types
[op
].bitfield
.disp32
= 1;
7955 i
.types
[op
].bitfield
.disp32s
= 0;
7959 i
.types
[op
].bitfield
.disp32
= 0;
7960 i
.types
[op
].bitfield
.disp32s
= 1;
7963 i
.sib
.index
= i
.index_reg
->reg_num
;
7964 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
7969 if (i
.base_reg
== 0)
7972 if (!i
.disp_operands
)
7973 fake_zero_displacement
= 1;
7974 if (i
.index_reg
== 0)
7976 i386_operand_type newdisp
;
7978 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7979 /* Operand is just <disp> */
7980 if (flag_code
== CODE_64BIT
)
7982 /* 64bit mode overwrites the 32bit absolute
7983 addressing by RIP relative addressing and
7984 absolute addressing is encoded by one of the
7985 redundant SIB forms. */
7986 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7987 i
.sib
.base
= NO_BASE_REGISTER
;
7988 i
.sib
.index
= NO_INDEX_REGISTER
;
7989 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7991 else if ((flag_code
== CODE_16BIT
)
7992 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7994 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7999 i
.rm
.regmem
= NO_BASE_REGISTER
;
8002 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8003 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8005 else if (!i
.tm
.opcode_modifier
.vecsib
)
8007 /* !i.base_reg && i.index_reg */
8008 if (i
.index_reg
->reg_num
== RegIZ
)
8009 i
.sib
.index
= NO_INDEX_REGISTER
;
8011 i
.sib
.index
= i
.index_reg
->reg_num
;
8012 i
.sib
.base
= NO_BASE_REGISTER
;
8013 i
.sib
.scale
= i
.log2_scale_factor
;
8014 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8015 i
.types
[op
].bitfield
.disp8
= 0;
8016 i
.types
[op
].bitfield
.disp16
= 0;
8017 i
.types
[op
].bitfield
.disp64
= 0;
8018 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8020 /* Must be 32 bit */
8021 i
.types
[op
].bitfield
.disp32
= 1;
8022 i
.types
[op
].bitfield
.disp32s
= 0;
8026 i
.types
[op
].bitfield
.disp32
= 0;
8027 i
.types
[op
].bitfield
.disp32s
= 1;
8029 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8033 /* RIP addressing for 64bit mode. */
8034 else if (i
.base_reg
->reg_num
== RegIP
)
8036 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8037 i
.rm
.regmem
= NO_BASE_REGISTER
;
8038 i
.types
[op
].bitfield
.disp8
= 0;
8039 i
.types
[op
].bitfield
.disp16
= 0;
8040 i
.types
[op
].bitfield
.disp32
= 0;
8041 i
.types
[op
].bitfield
.disp32s
= 1;
8042 i
.types
[op
].bitfield
.disp64
= 0;
8043 i
.flags
[op
] |= Operand_PCrel
;
8044 if (! i
.disp_operands
)
8045 fake_zero_displacement
= 1;
8047 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8049 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8050 switch (i
.base_reg
->reg_num
)
8053 if (i
.index_reg
== 0)
8055 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8056 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8060 if (i
.index_reg
== 0)
8063 if (operand_type_check (i
.types
[op
], disp
) == 0)
8065 /* fake (%bp) into 0(%bp) */
8066 i
.types
[op
].bitfield
.disp8
= 1;
8067 fake_zero_displacement
= 1;
8070 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8071 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8073 default: /* (%si) -> 4 or (%di) -> 5 */
8074 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8076 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8078 else /* i.base_reg and 32/64 bit mode */
8080 if (flag_code
== CODE_64BIT
8081 && operand_type_check (i
.types
[op
], disp
))
8083 i
.types
[op
].bitfield
.disp16
= 0;
8084 i
.types
[op
].bitfield
.disp64
= 0;
8085 if (i
.prefix
[ADDR_PREFIX
] == 0)
8087 i
.types
[op
].bitfield
.disp32
= 0;
8088 i
.types
[op
].bitfield
.disp32s
= 1;
8092 i
.types
[op
].bitfield
.disp32
= 1;
8093 i
.types
[op
].bitfield
.disp32s
= 0;
8097 if (!i
.tm
.opcode_modifier
.vecsib
)
8098 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8099 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8101 i
.sib
.base
= i
.base_reg
->reg_num
;
8102 /* x86-64 ignores REX prefix bit here to avoid decoder
8104 if (!(i
.base_reg
->reg_flags
& RegRex
)
8105 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8106 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8108 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8110 fake_zero_displacement
= 1;
8111 i
.types
[op
].bitfield
.disp8
= 1;
8113 i
.sib
.scale
= i
.log2_scale_factor
;
8114 if (i
.index_reg
== 0)
8116 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8117 /* <disp>(%esp) becomes two byte modrm with no index
8118 register. We've already stored the code for esp
8119 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8120 Any base register besides %esp will not use the
8121 extra modrm byte. */
8122 i
.sib
.index
= NO_INDEX_REGISTER
;
8124 else if (!i
.tm
.opcode_modifier
.vecsib
)
8126 if (i
.index_reg
->reg_num
== RegIZ
)
8127 i
.sib
.index
= NO_INDEX_REGISTER
;
8129 i
.sib
.index
= i
.index_reg
->reg_num
;
8130 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8131 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8136 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8137 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8141 if (!fake_zero_displacement
8145 fake_zero_displacement
= 1;
8146 if (i
.disp_encoding
== disp_encoding_8bit
)
8147 i
.types
[op
].bitfield
.disp8
= 1;
8149 i
.types
[op
].bitfield
.disp32
= 1;
8151 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8155 if (fake_zero_displacement
)
8157 /* Fakes a zero displacement assuming that i.types[op]
8158 holds the correct displacement size. */
8161 gas_assert (i
.op
[op
].disps
== 0);
8162 exp
= &disp_expressions
[i
.disp_operands
++];
8163 i
.op
[op
].disps
= exp
;
8164 exp
->X_op
= O_constant
;
8165 exp
->X_add_number
= 0;
8166 exp
->X_add_symbol
= (symbolS
*) 0;
8167 exp
->X_op_symbol
= (symbolS
*) 0;
8175 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8177 if (operand_type_check (i
.types
[0], imm
))
8178 i
.vex
.register_specifier
= NULL
;
8181 /* VEX.vvvv encodes one of the sources when the first
8182 operand is not an immediate. */
8183 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8184 i
.vex
.register_specifier
= i
.op
[0].regs
;
8186 i
.vex
.register_specifier
= i
.op
[1].regs
;
8189 /* Destination is a XMM register encoded in the ModRM.reg
8191 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8192 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8195 /* ModRM.rm and VEX.B encodes the other source. */
8196 if (!i
.mem_operands
)
8200 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8201 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8203 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8205 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8209 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8211 i
.vex
.register_specifier
= i
.op
[2].regs
;
8212 if (!i
.mem_operands
)
8215 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8216 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8220 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8221 (if any) based on i.tm.extension_opcode. Again, we must be
8222 careful to make sure that segment/control/debug/test/MMX
8223 registers are coded into the i.rm.reg field. */
8224 else if (i
.reg_operands
)
8227 unsigned int vex_reg
= ~0;
8229 for (op
= 0; op
< i
.operands
; op
++)
8231 if (i
.types
[op
].bitfield
.class == Reg
8232 || i
.types
[op
].bitfield
.class == RegBND
8233 || i
.types
[op
].bitfield
.class == RegMask
8234 || i
.types
[op
].bitfield
.class == SReg
8235 || i
.types
[op
].bitfield
.class == RegCR
8236 || i
.types
[op
].bitfield
.class == RegDR
8237 || i
.types
[op
].bitfield
.class == RegTR
)
8239 if (i
.types
[op
].bitfield
.class == RegSIMD
)
8241 if (i
.types
[op
].bitfield
.zmmword
)
8242 i
.has_regzmm
= TRUE
;
8243 else if (i
.types
[op
].bitfield
.ymmword
)
8244 i
.has_regymm
= TRUE
;
8246 i
.has_regxmm
= TRUE
;
8249 if (i
.types
[op
].bitfield
.class == RegMMX
)
8251 i
.has_regmmx
= TRUE
;
8258 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8260 /* For instructions with VexNDS, the register-only
8261 source operand is encoded in VEX prefix. */
8262 gas_assert (mem
!= (unsigned int) ~0);
8267 gas_assert (op
< i
.operands
);
8271 /* Check register-only source operand when two source
8272 operands are swapped. */
8273 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8274 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8278 gas_assert (mem
== (vex_reg
+ 1)
8279 && op
< i
.operands
);
8284 gas_assert (vex_reg
< i
.operands
);
8288 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8290 /* For instructions with VexNDD, the register destination
8291 is encoded in VEX prefix. */
8292 if (i
.mem_operands
== 0)
8294 /* There is no memory operand. */
8295 gas_assert ((op
+ 2) == i
.operands
);
8300 /* There are only 2 non-immediate operands. */
8301 gas_assert (op
< i
.imm_operands
+ 2
8302 && i
.operands
== i
.imm_operands
+ 2);
8303 vex_reg
= i
.imm_operands
+ 1;
8307 gas_assert (op
< i
.operands
);
8309 if (vex_reg
!= (unsigned int) ~0)
8311 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8313 if ((type
->bitfield
.class != Reg
8314 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8315 && type
->bitfield
.class != RegSIMD
8316 && !operand_type_equal (type
, ®mask
))
8319 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8322 /* Don't set OP operand twice. */
8325 /* If there is an extension opcode to put here, the
8326 register number must be put into the regmem field. */
8327 if (i
.tm
.extension_opcode
!= None
)
8329 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8330 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8331 i
.tm
.opcode_modifier
.sse2avx
);
8335 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8336 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8337 i
.tm
.opcode_modifier
.sse2avx
);
8341 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8342 must set it to 3 to indicate this is a register operand
8343 in the regmem field. */
8344 if (!i
.mem_operands
)
8348 /* Fill in i.rm.reg field with extension opcode (if any). */
8349 if (i
.tm
.extension_opcode
!= None
)
8350 i
.rm
.reg
= i
.tm
.extension_opcode
;
8356 flip_code16 (unsigned int code16
)
8358 gas_assert (i
.tm
.operands
== 1);
8360 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8361 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8362 || i
.tm
.operand_types
[0].bitfield
.disp32s
8363 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8368 output_branch (void)
8374 relax_substateT subtype
;
8378 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8379 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8382 if (i
.prefix
[DATA_PREFIX
] != 0)
8386 code16
^= flip_code16(code16
);
8388 /* Pentium4 branch hints. */
8389 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8390 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8395 if (i
.prefix
[REX_PREFIX
] != 0)
8401 /* BND prefixed jump. */
8402 if (i
.prefix
[BND_PREFIX
] != 0)
8408 if (i
.prefixes
!= 0)
8409 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8411 /* It's always a symbol; End frag & setup for relax.
8412 Make sure there is enough room in this frag for the largest
8413 instruction we may generate in md_convert_frag. This is 2
8414 bytes for the opcode and room for the prefix and largest
8416 frag_grow (prefix
+ 2 + 4);
8417 /* Prefix and 1 opcode byte go in fr_fix. */
8418 p
= frag_more (prefix
+ 1);
8419 if (i
.prefix
[DATA_PREFIX
] != 0)
8420 *p
++ = DATA_PREFIX_OPCODE
;
8421 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8422 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8423 *p
++ = i
.prefix
[SEG_PREFIX
];
8424 if (i
.prefix
[BND_PREFIX
] != 0)
8425 *p
++ = BND_PREFIX_OPCODE
;
8426 if (i
.prefix
[REX_PREFIX
] != 0)
8427 *p
++ = i
.prefix
[REX_PREFIX
];
8428 *p
= i
.tm
.base_opcode
;
8430 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8431 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8432 else if (cpu_arch_flags
.bitfield
.cpui386
)
8433 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8435 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8438 sym
= i
.op
[0].disps
->X_add_symbol
;
8439 off
= i
.op
[0].disps
->X_add_number
;
8441 if (i
.op
[0].disps
->X_op
!= O_constant
8442 && i
.op
[0].disps
->X_op
!= O_symbol
)
8444 /* Handle complex expressions. */
8445 sym
= make_expr_symbol (i
.op
[0].disps
);
8449 /* 1 possible extra opcode + 4 byte displacement go in var part.
8450 Pass reloc in fr_var. */
8451 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8454 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8455 /* Return TRUE iff PLT32 relocation should be used for branching to
8459 need_plt32_p (symbolS
*s
)
8461 /* PLT32 relocation is ELF only. */
8466 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8467 krtld support it. */
8471 /* Since there is no need to prepare for PLT branch on x86-64, we
8472 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8473 be used as a marker for 32-bit PC-relative branches. */
8477 /* Weak or undefined symbol need PLT32 relocation. */
8478 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8481 /* Non-global symbol doesn't need PLT32 relocation. */
8482 if (! S_IS_EXTERNAL (s
))
8485 /* Other global symbols need PLT32 relocation. NB: Symbol with
8486 non-default visibilities are treated as normal global symbol
8487 so that PLT32 relocation can be used as a marker for 32-bit
8488 PC-relative branches. It is useful for linker relaxation. */
8499 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8501 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8503 /* This is a loop or jecxz type instruction. */
8505 if (i
.prefix
[ADDR_PREFIX
] != 0)
8507 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8510 /* Pentium4 branch hints. */
8511 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8512 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8514 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8523 if (flag_code
== CODE_16BIT
)
8526 if (i
.prefix
[DATA_PREFIX
] != 0)
8528 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8530 code16
^= flip_code16(code16
);
8538 /* BND prefixed jump. */
8539 if (i
.prefix
[BND_PREFIX
] != 0)
8541 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8545 if (i
.prefix
[REX_PREFIX
] != 0)
8547 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8551 if (i
.prefixes
!= 0)
8552 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8554 p
= frag_more (i
.tm
.opcode_length
+ size
);
8555 switch (i
.tm
.opcode_length
)
8558 *p
++ = i
.tm
.base_opcode
>> 8;
8561 *p
++ = i
.tm
.base_opcode
;
8567 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8569 && jump_reloc
== NO_RELOC
8570 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8571 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8574 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8576 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8577 i
.op
[0].disps
, 1, jump_reloc
);
8579 /* All jumps handled here are signed, but don't use a signed limit
8580 check for 32 and 16 bit jumps as we want to allow wrap around at
8581 4G and 64k respectively. */
8583 fixP
->fx_signed
= 1;
8587 output_interseg_jump (void)
8595 if (flag_code
== CODE_16BIT
)
8599 if (i
.prefix
[DATA_PREFIX
] != 0)
8606 gas_assert (!i
.prefix
[REX_PREFIX
]);
8612 if (i
.prefixes
!= 0)
8613 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8615 /* 1 opcode; 2 segment; offset */
8616 p
= frag_more (prefix
+ 1 + 2 + size
);
8618 if (i
.prefix
[DATA_PREFIX
] != 0)
8619 *p
++ = DATA_PREFIX_OPCODE
;
8621 if (i
.prefix
[REX_PREFIX
] != 0)
8622 *p
++ = i
.prefix
[REX_PREFIX
];
8624 *p
++ = i
.tm
.base_opcode
;
8625 if (i
.op
[1].imms
->X_op
== O_constant
)
8627 offsetT n
= i
.op
[1].imms
->X_add_number
;
8630 && !fits_in_unsigned_word (n
)
8631 && !fits_in_signed_word (n
))
8633 as_bad (_("16-bit jump out of range"));
8636 md_number_to_chars (p
, n
, size
);
8639 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8640 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8641 if (i
.op
[0].imms
->X_op
!= O_constant
)
8642 as_bad (_("can't handle non absolute segment in `%s'"),
8644 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8647 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8652 asection
*seg
= now_seg
;
8653 subsegT subseg
= now_subseg
;
8655 unsigned int alignment
, align_size_1
;
8656 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8657 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8658 unsigned int padding
;
8660 if (!IS_ELF
|| !x86_used_note
)
8663 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8665 /* The .note.gnu.property section layout:
8667 Field Length Contents
8670 n_descsz 4 The note descriptor size
8671 n_type 4 NT_GNU_PROPERTY_TYPE_0
8673 n_desc n_descsz The program property array
8677 /* Create the .note.gnu.property section. */
8678 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8679 bfd_set_section_flags (sec
,
8686 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8697 bfd_set_section_alignment (sec
, alignment
);
8698 elf_section_type (sec
) = SHT_NOTE
;
8700 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8702 isa_1_descsz_raw
= 4 + 4 + 4;
8703 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8704 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8706 feature_2_descsz_raw
= isa_1_descsz
;
8707 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8709 feature_2_descsz_raw
+= 4 + 4 + 4;
8710 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8711 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8714 descsz
= feature_2_descsz
;
8715 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8716 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8718 /* Write n_namsz. */
8719 md_number_to_chars (p
, (valueT
) 4, 4);
8721 /* Write n_descsz. */
8722 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8725 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8728 memcpy (p
+ 4 * 3, "GNU", 4);
8730 /* Write 4-byte type. */
8731 md_number_to_chars (p
+ 4 * 4,
8732 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8734 /* Write 4-byte data size. */
8735 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8737 /* Write 4-byte data. */
8738 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8740 /* Zero out paddings. */
8741 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8743 memset (p
+ 4 * 7, 0, padding
);
8745 /* Write 4-byte type. */
8746 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8747 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8749 /* Write 4-byte data size. */
8750 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8752 /* Write 4-byte data. */
8753 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8754 (valueT
) x86_feature_2_used
, 4);
8756 /* Zero out paddings. */
8757 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8759 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8761 /* We probably can't restore the current segment, for there likely
8764 subseg_set (seg
, subseg
);
8769 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8770 const char *frag_now_ptr
)
8772 unsigned int len
= 0;
8774 if (start_frag
!= frag_now
)
8776 const fragS
*fr
= start_frag
;
8781 } while (fr
&& fr
!= frag_now
);
8784 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8787 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8788 be macro-fused with conditional jumps.
8789 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8790 or is one of the following format:
8803 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8805 /* No RIP address. */
8806 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8809 /* No VEX/EVEX encoding. */
8810 if (is_any_vex_encoding (&i
.tm
))
8813 /* add, sub without add/sub m, imm. */
8814 if (i
.tm
.base_opcode
<= 5
8815 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8816 || ((i
.tm
.base_opcode
| 3) == 0x83
8817 && (i
.tm
.extension_opcode
== 0x5
8818 || i
.tm
.extension_opcode
== 0x0)))
8820 *mf_cmp_p
= mf_cmp_alu_cmp
;
8821 return !(i
.mem_operands
&& i
.imm_operands
);
8824 /* and without and m, imm. */
8825 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8826 || ((i
.tm
.base_opcode
| 3) == 0x83
8827 && i
.tm
.extension_opcode
== 0x4))
8829 *mf_cmp_p
= mf_cmp_test_and
;
8830 return !(i
.mem_operands
&& i
.imm_operands
);
8833 /* test without test m imm. */
8834 if ((i
.tm
.base_opcode
| 1) == 0x85
8835 || (i
.tm
.base_opcode
| 1) == 0xa9
8836 || ((i
.tm
.base_opcode
| 1) == 0xf7
8837 && i
.tm
.extension_opcode
== 0))
8839 *mf_cmp_p
= mf_cmp_test_and
;
8840 return !(i
.mem_operands
&& i
.imm_operands
);
8843 /* cmp without cmp m, imm. */
8844 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8845 || ((i
.tm
.base_opcode
| 3) == 0x83
8846 && (i
.tm
.extension_opcode
== 0x7)))
8848 *mf_cmp_p
= mf_cmp_alu_cmp
;
8849 return !(i
.mem_operands
&& i
.imm_operands
);
8852 /* inc, dec without inc/dec m. */
8853 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8854 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8855 || ((i
.tm
.base_opcode
| 1) == 0xff
8856 && i
.tm
.extension_opcode
<= 0x1))
8858 *mf_cmp_p
= mf_cmp_incdec
;
8859 return !i
.mem_operands
;
8865 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8868 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8870 /* NB: Don't work with COND_JUMP86 without i386. */
8871 if (!align_branch_power
8872 || now_seg
== absolute_section
8873 || !cpu_arch_flags
.bitfield
.cpui386
8874 || !(align_branch
& align_branch_fused_bit
))
8877 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8879 if (last_insn
.kind
== last_insn_other
8880 || last_insn
.seg
!= now_seg
)
8883 as_warn_where (last_insn
.file
, last_insn
.line
,
8884 _("`%s` skips -malign-branch-boundary on `%s`"),
8885 last_insn
.name
, i
.tm
.name
);
8891 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8894 add_branch_prefix_frag_p (void)
8896 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8897 to PadLock instructions since they include prefixes in opcode. */
8898 if (!align_branch_power
8899 || !align_branch_prefix_size
8900 || now_seg
== absolute_section
8901 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8902 || !cpu_arch_flags
.bitfield
.cpui386
)
8905 /* Don't add prefix if it is a prefix or there is no operand in case
8906 that segment prefix is special. */
8907 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8910 if (last_insn
.kind
== last_insn_other
8911 || last_insn
.seg
!= now_seg
)
8915 as_warn_where (last_insn
.file
, last_insn
.line
,
8916 _("`%s` skips -malign-branch-boundary on `%s`"),
8917 last_insn
.name
, i
.tm
.name
);
8922 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8925 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8926 enum mf_jcc_kind
*mf_jcc_p
)
8930 /* NB: Don't work with COND_JUMP86 without i386. */
8931 if (!align_branch_power
8932 || now_seg
== absolute_section
8933 || !cpu_arch_flags
.bitfield
.cpui386
)
8938 /* Check for jcc and direct jmp. */
8939 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8941 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8943 *branch_p
= align_branch_jmp
;
8944 add_padding
= align_branch
& align_branch_jmp_bit
;
8948 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8949 igore the lowest bit. */
8950 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8951 *branch_p
= align_branch_jcc
;
8952 if ((align_branch
& align_branch_jcc_bit
))
8956 else if (is_any_vex_encoding (&i
.tm
))
8958 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8961 *branch_p
= align_branch_ret
;
8962 if ((align_branch
& align_branch_ret_bit
))
8967 /* Check for indirect jmp, direct and indirect calls. */
8968 if (i
.tm
.base_opcode
== 0xe8)
8971 *branch_p
= align_branch_call
;
8972 if ((align_branch
& align_branch_call_bit
))
8975 else if (i
.tm
.base_opcode
== 0xff
8976 && (i
.tm
.extension_opcode
== 2
8977 || i
.tm
.extension_opcode
== 4))
8979 /* Indirect call and jmp. */
8980 *branch_p
= align_branch_indirect
;
8981 if ((align_branch
& align_branch_indirect_bit
))
8988 && (i
.op
[0].disps
->X_op
== O_symbol
8989 || (i
.op
[0].disps
->X_op
== O_subtract
8990 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8992 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8993 /* No padding to call to global or undefined tls_get_addr. */
8994 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8995 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9001 && last_insn
.kind
!= last_insn_other
9002 && last_insn
.seg
== now_seg
)
9005 as_warn_where (last_insn
.file
, last_insn
.line
,
9006 _("`%s` skips -malign-branch-boundary on `%s`"),
9007 last_insn
.name
, i
.tm
.name
);
9017 fragS
*insn_start_frag
;
9018 offsetT insn_start_off
;
9019 fragS
*fragP
= NULL
;
9020 enum align_branch_kind branch
= align_branch_none
;
9021 /* The initializer is arbitrary just to avoid uninitialized error.
9022 it's actually either assigned in add_branch_padding_frag_p
9023 or never be used. */
9024 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9027 if (IS_ELF
&& x86_used_note
)
9029 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
9030 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
9031 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
9032 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
9033 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
9034 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
9035 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
9036 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
9037 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
9038 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
9039 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
9040 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
9041 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
9042 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
9043 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9044 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
9045 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
9046 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
9047 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
9048 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
9049 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
9050 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
9051 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
9052 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
9053 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
9054 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
9055 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
9056 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
9057 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
9058 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
9059 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
9060 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
9061 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
9062 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
9063 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
9064 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
9065 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
9066 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
9067 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
9068 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
9069 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
9070 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
9071 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
9072 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9073 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9074 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9075 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9076 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9077 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9078 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9080 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9081 || i
.tm
.cpu_flags
.bitfield
.cpu287
9082 || i
.tm
.cpu_flags
.bitfield
.cpu387
9083 || i
.tm
.cpu_flags
.bitfield
.cpu687
9084 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9085 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9087 || i
.tm
.base_opcode
== 0xf77 /* emms */
9088 || i
.tm
.base_opcode
== 0xf0e /* femms */
9089 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
9090 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
9091 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9093 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9095 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9097 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9098 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9099 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9100 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9101 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9102 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9103 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9104 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9105 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9109 /* Tie dwarf2 debug info to the address at the start of the insn.
9110 We can't do this after the insn has been output as the current
9111 frag may have been closed off. eg. by frag_var. */
9112 dwarf2_emit_insn (0);
9114 insn_start_frag
= frag_now
;
9115 insn_start_off
= frag_now_fix ();
9117 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9120 /* Branch can be 8 bytes. Leave some room for prefixes. */
9121 unsigned int max_branch_padding_size
= 14;
9123 /* Align section to boundary. */
9124 record_alignment (now_seg
, align_branch_power
);
9126 /* Make room for padding. */
9127 frag_grow (max_branch_padding_size
);
9129 /* Start of the padding. */
9134 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9135 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9138 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9139 fragP
->tc_frag_data
.branch_type
= branch
;
9140 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9144 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9146 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9147 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9149 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9150 output_interseg_jump ();
9153 /* Output normal instructions here. */
9157 unsigned int prefix
;
9158 enum mf_cmp_kind mf_cmp
;
9161 && (i
.tm
.base_opcode
== 0xfaee8
9162 || i
.tm
.base_opcode
== 0xfaef0
9163 || i
.tm
.base_opcode
== 0xfaef8))
9165 /* Encode lfence, mfence, and sfence as
9166 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9167 offsetT val
= 0x240483f0ULL
;
9169 md_number_to_chars (p
, val
, 5);
9173 /* Some processors fail on LOCK prefix. This options makes
9174 assembler ignore LOCK prefix and serves as a workaround. */
9175 if (omit_lock_prefix
)
9177 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9179 i
.prefix
[LOCK_PREFIX
] = 0;
9183 /* Skip if this is a branch. */
9185 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9187 /* Make room for padding. */
9188 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9193 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9194 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9197 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9198 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9199 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9201 else if (add_branch_prefix_frag_p ())
9203 unsigned int max_prefix_size
= align_branch_prefix_size
;
9205 /* Make room for padding. */
9206 frag_grow (max_prefix_size
);
9211 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9212 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9215 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9218 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9219 don't need the explicit prefix. */
9220 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9222 switch (i
.tm
.opcode_length
)
9225 if (i
.tm
.base_opcode
& 0xff000000)
9227 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9228 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9229 || prefix
!= REPE_PREFIX_OPCODE
9230 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9231 add_prefix (prefix
);
9235 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9237 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9238 add_prefix (prefix
);
9244 /* Check for pseudo prefixes. */
9245 as_bad_where (insn_start_frag
->fr_file
,
9246 insn_start_frag
->fr_line
,
9247 _("pseudo prefix without instruction"));
9253 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9254 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9255 R_X86_64_GOTTPOFF relocation so that linker can safely
9256 perform IE->LE optimization. A dummy REX_OPCODE prefix
9257 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9258 relocation for GDesc -> IE/LE optimization. */
9259 if (x86_elf_abi
== X86_64_X32_ABI
9261 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9262 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9263 && i
.prefix
[REX_PREFIX
] == 0)
9264 add_prefix (REX_OPCODE
);
9267 /* The prefix bytes. */
9268 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9270 FRAG_APPEND_1_CHAR (*q
);
9274 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9279 /* REX byte is encoded in VEX prefix. */
9283 FRAG_APPEND_1_CHAR (*q
);
9286 /* There should be no other prefixes for instructions
9291 /* For EVEX instructions i.vrex should become 0 after
9292 build_evex_prefix. For VEX instructions upper 16 registers
9293 aren't available, so VREX should be 0. */
9296 /* Now the VEX prefix. */
9297 p
= frag_more (i
.vex
.length
);
9298 for (j
= 0; j
< i
.vex
.length
; j
++)
9299 p
[j
] = i
.vex
.bytes
[j
];
9302 /* Now the opcode; be careful about word order here! */
9303 if (i
.tm
.opcode_length
== 1)
9305 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9309 switch (i
.tm
.opcode_length
)
9313 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9314 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9318 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9328 /* Put out high byte first: can't use md_number_to_chars! */
9329 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9330 *p
= i
.tm
.base_opcode
& 0xff;
9333 /* Now the modrm byte and sib byte (if present). */
9334 if (i
.tm
.opcode_modifier
.modrm
)
9336 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
9339 /* If i.rm.regmem == ESP (4)
9340 && i.rm.mode != (Register mode)
9342 ==> need second modrm byte. */
9343 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9345 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9346 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
9348 | i
.sib
.scale
<< 6));
9351 if (i
.disp_operands
)
9352 output_disp (insn_start_frag
, insn_start_off
);
9355 output_imm (insn_start_frag
, insn_start_off
);
9358 * frag_now_fix () returning plain abs_section_offset when we're in the
9359 * absolute section, and abs_section_offset not getting updated as data
9360 * gets added to the frag breaks the logic below.
9362 if (now_seg
!= absolute_section
)
9364 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9366 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9370 /* NB: Don't add prefix with GOTPC relocation since
9371 output_disp() above depends on the fixed encoding
9372 length. Can't add prefix with TLS relocation since
9373 it breaks TLS linker optimization. */
9374 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9375 /* Prefix count on the current instruction. */
9376 unsigned int count
= i
.vex
.length
;
9378 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9379 /* REX byte is encoded in VEX/EVEX prefix. */
9380 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9383 /* Count prefixes for extended opcode maps. */
9385 switch (i
.tm
.opcode_length
)
9388 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9391 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9403 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9412 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9415 /* Set the maximum prefix size in BRANCH_PREFIX
9417 if (fragP
->tc_frag_data
.max_bytes
> max
)
9418 fragP
->tc_frag_data
.max_bytes
= max
;
9419 if (fragP
->tc_frag_data
.max_bytes
> count
)
9420 fragP
->tc_frag_data
.max_bytes
-= count
;
9422 fragP
->tc_frag_data
.max_bytes
= 0;
9426 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9428 unsigned int max_prefix_size
;
9429 if (align_branch_prefix_size
> max
)
9430 max_prefix_size
= max
;
9432 max_prefix_size
= align_branch_prefix_size
;
9433 if (max_prefix_size
> count
)
9434 fragP
->tc_frag_data
.max_prefix_length
9435 = max_prefix_size
- count
;
9438 /* Use existing segment prefix if possible. Use CS
9439 segment prefix in 64-bit mode. In 32-bit mode, use SS
9440 segment prefix with ESP/EBP base register and use DS
9441 segment prefix without ESP/EBP base register. */
9442 if (i
.prefix
[SEG_PREFIX
])
9443 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9444 else if (flag_code
== CODE_64BIT
)
9445 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9447 && (i
.base_reg
->reg_num
== 4
9448 || i
.base_reg
->reg_num
== 5))
9449 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9451 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9456 /* NB: Don't work with COND_JUMP86 without i386. */
9457 if (align_branch_power
9458 && now_seg
!= absolute_section
9459 && cpu_arch_flags
.bitfield
.cpui386
)
9461 /* Terminate each frag so that we can add prefix and check for
9463 frag_wane (frag_now
);
9470 pi ("" /*line*/, &i
);
9472 #endif /* DEBUG386 */
9475 /* Return the size of the displacement operand N. */
9478 disp_size (unsigned int n
)
9482 if (i
.types
[n
].bitfield
.disp64
)
9484 else if (i
.types
[n
].bitfield
.disp8
)
9486 else if (i
.types
[n
].bitfield
.disp16
)
9491 /* Return the size of the immediate operand N. */
9494 imm_size (unsigned int n
)
9497 if (i
.types
[n
].bitfield
.imm64
)
9499 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9501 else if (i
.types
[n
].bitfield
.imm16
)
9507 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9512 for (n
= 0; n
< i
.operands
; n
++)
9514 if (operand_type_check (i
.types
[n
], disp
))
9516 if (i
.op
[n
].disps
->X_op
== O_constant
)
9518 int size
= disp_size (n
);
9519 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9521 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9523 p
= frag_more (size
);
9524 md_number_to_chars (p
, val
, size
);
9528 enum bfd_reloc_code_real reloc_type
;
9529 int size
= disp_size (n
);
9530 int sign
= i
.types
[n
].bitfield
.disp32s
;
9531 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9534 /* We can't have 8 bit displacement here. */
9535 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9537 /* The PC relative address is computed relative
9538 to the instruction boundary, so in case immediate
9539 fields follows, we need to adjust the value. */
9540 if (pcrel
&& i
.imm_operands
)
9545 for (n1
= 0; n1
< i
.operands
; n1
++)
9546 if (operand_type_check (i
.types
[n1
], imm
))
9548 /* Only one immediate is allowed for PC
9549 relative address. */
9550 gas_assert (sz
== 0);
9552 i
.op
[n
].disps
->X_add_number
-= sz
;
9554 /* We should find the immediate. */
9555 gas_assert (sz
!= 0);
9558 p
= frag_more (size
);
9559 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9561 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9562 && (((reloc_type
== BFD_RELOC_32
9563 || reloc_type
== BFD_RELOC_X86_64_32S
9564 || (reloc_type
== BFD_RELOC_64
9566 && (i
.op
[n
].disps
->X_op
== O_symbol
9567 || (i
.op
[n
].disps
->X_op
== O_add
9568 && ((symbol_get_value_expression
9569 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9571 || reloc_type
== BFD_RELOC_32_PCREL
))
9575 reloc_type
= BFD_RELOC_386_GOTPC
;
9576 i
.has_gotpc_tls_reloc
= TRUE
;
9577 i
.op
[n
].imms
->X_add_number
+=
9578 encoding_length (insn_start_frag
, insn_start_off
, p
);
9580 else if (reloc_type
== BFD_RELOC_64
)
9581 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9583 /* Don't do the adjustment for x86-64, as there
9584 the pcrel addressing is relative to the _next_
9585 insn, and that is taken care of in other code. */
9586 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9588 else if (align_branch_power
)
9592 case BFD_RELOC_386_TLS_GD
:
9593 case BFD_RELOC_386_TLS_LDM
:
9594 case BFD_RELOC_386_TLS_IE
:
9595 case BFD_RELOC_386_TLS_IE_32
:
9596 case BFD_RELOC_386_TLS_GOTIE
:
9597 case BFD_RELOC_386_TLS_GOTDESC
:
9598 case BFD_RELOC_386_TLS_DESC_CALL
:
9599 case BFD_RELOC_X86_64_TLSGD
:
9600 case BFD_RELOC_X86_64_TLSLD
:
9601 case BFD_RELOC_X86_64_GOTTPOFF
:
9602 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9603 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9604 i
.has_gotpc_tls_reloc
= TRUE
;
9609 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9610 size
, i
.op
[n
].disps
, pcrel
,
9612 /* Check for "call/jmp *mem", "mov mem, %reg",
9613 "test %reg, mem" and "binop mem, %reg" where binop
9614 is one of adc, add, and, cmp, or, sbb, sub, xor
9615 instructions without data prefix. Always generate
9616 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9617 if (i
.prefix
[DATA_PREFIX
] == 0
9618 && (generate_relax_relocations
9621 && i
.rm
.regmem
== 5))
9623 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9624 && !is_any_vex_encoding(&i
.tm
)
9625 && ((i
.operands
== 1
9626 && i
.tm
.base_opcode
== 0xff
9627 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9629 && (i
.tm
.base_opcode
== 0x8b
9630 || i
.tm
.base_opcode
== 0x85
9631 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9635 fixP
->fx_tcbit
= i
.rex
!= 0;
9637 && (i
.base_reg
->reg_num
== RegIP
))
9638 fixP
->fx_tcbit2
= 1;
9641 fixP
->fx_tcbit2
= 1;
9649 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9654 for (n
= 0; n
< i
.operands
; n
++)
9656 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9657 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9660 if (operand_type_check (i
.types
[n
], imm
))
9662 if (i
.op
[n
].imms
->X_op
== O_constant
)
9664 int size
= imm_size (n
);
9667 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9669 p
= frag_more (size
);
9670 md_number_to_chars (p
, val
, size
);
9674 /* Not absolute_section.
9675 Need a 32-bit fixup (don't support 8bit
9676 non-absolute imms). Try to support other
9678 enum bfd_reloc_code_real reloc_type
;
9679 int size
= imm_size (n
);
9682 if (i
.types
[n
].bitfield
.imm32s
9683 && (i
.suffix
== QWORD_MNEM_SUFFIX
9684 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9689 p
= frag_more (size
);
9690 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9692 /* This is tough to explain. We end up with this one if we
9693 * have operands that look like
9694 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9695 * obtain the absolute address of the GOT, and it is strongly
9696 * preferable from a performance point of view to avoid using
9697 * a runtime relocation for this. The actual sequence of
9698 * instructions often look something like:
9703 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9705 * The call and pop essentially return the absolute address
9706 * of the label .L66 and store it in %ebx. The linker itself
9707 * will ultimately change the first operand of the addl so
9708 * that %ebx points to the GOT, but to keep things simple, the
9709 * .o file must have this operand set so that it generates not
9710 * the absolute address of .L66, but the absolute address of
9711 * itself. This allows the linker itself simply treat a GOTPC
9712 * relocation as asking for a pcrel offset to the GOT to be
9713 * added in, and the addend of the relocation is stored in the
9714 * operand field for the instruction itself.
9716 * Our job here is to fix the operand so that it would add
9717 * the correct offset so that %ebx would point to itself. The
9718 * thing that is tricky is that .-.L66 will point to the
9719 * beginning of the instruction, so we need to further modify
9720 * the operand so that it will point to itself. There are
9721 * other cases where you have something like:
9723 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9725 * and here no correction would be required. Internally in
9726 * the assembler we treat operands of this form as not being
9727 * pcrel since the '.' is explicitly mentioned, and I wonder
9728 * whether it would simplify matters to do it this way. Who
9729 * knows. In earlier versions of the PIC patches, the
9730 * pcrel_adjust field was used to store the correction, but
9731 * since the expression is not pcrel, I felt it would be
9732 * confusing to do it this way. */
9734 if ((reloc_type
== BFD_RELOC_32
9735 || reloc_type
== BFD_RELOC_X86_64_32S
9736 || reloc_type
== BFD_RELOC_64
)
9738 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9739 && (i
.op
[n
].imms
->X_op
== O_symbol
9740 || (i
.op
[n
].imms
->X_op
== O_add
9741 && ((symbol_get_value_expression
9742 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9746 reloc_type
= BFD_RELOC_386_GOTPC
;
9748 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9750 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9751 i
.has_gotpc_tls_reloc
= TRUE
;
9752 i
.op
[n
].imms
->X_add_number
+=
9753 encoding_length (insn_start_frag
, insn_start_off
, p
);
9755 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9756 i
.op
[n
].imms
, 0, reloc_type
);
9762 /* x86_cons_fix_new is called via the expression parsing code when a
9763 reloc is needed. We use this hook to get the correct .got reloc. */
9764 static int cons_sign
= -1;
9767 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9768 expressionS
*exp
, bfd_reloc_code_real_type r
)
9770 r
= reloc (len
, 0, cons_sign
, r
);
9773 if (exp
->X_op
== O_secrel
)
9775 exp
->X_op
= O_symbol
;
9776 r
= BFD_RELOC_32_SECREL
;
9780 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9783 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9784 purpose of the `.dc.a' internal pseudo-op. */
9787 x86_address_bytes (void)
9789 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9791 return stdoutput
->arch_info
->bits_per_address
/ 8;
9794 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9796 # define lex_got(reloc, adjust, types) NULL
9798 /* Parse operands of the form
9799 <symbol>@GOTOFF+<nnn>
9800 and similar .plt or .got references.
9802 If we find one, set up the correct relocation in RELOC and copy the
9803 input string, minus the `@GOTOFF' into a malloc'd buffer for
9804 parsing by the calling routine. Return this buffer, and if ADJUST
9805 is non-null set it to the length of the string we removed from the
9806 input line. Otherwise return NULL. */
9808 lex_got (enum bfd_reloc_code_real
*rel
,
9810 i386_operand_type
*types
)
9812 /* Some of the relocations depend on the size of what field is to
9813 be relocated. But in our callers i386_immediate and i386_displacement
9814 we don't yet know the operand size (this will be set by insn
9815 matching). Hence we record the word32 relocation here,
9816 and adjust the reloc according to the real size in reloc(). */
9817 static const struct {
9820 const enum bfd_reloc_code_real rel
[2];
9821 const i386_operand_type types64
;
9823 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9824 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9826 OPERAND_TYPE_IMM32_64
},
9828 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9829 BFD_RELOC_X86_64_PLTOFF64
},
9830 OPERAND_TYPE_IMM64
},
9831 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9832 BFD_RELOC_X86_64_PLT32
},
9833 OPERAND_TYPE_IMM32_32S_DISP32
},
9834 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9835 BFD_RELOC_X86_64_GOTPLT64
},
9836 OPERAND_TYPE_IMM64_DISP64
},
9837 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9838 BFD_RELOC_X86_64_GOTOFF64
},
9839 OPERAND_TYPE_IMM64_DISP64
},
9840 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9841 BFD_RELOC_X86_64_GOTPCREL
},
9842 OPERAND_TYPE_IMM32_32S_DISP32
},
9843 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9844 BFD_RELOC_X86_64_TLSGD
},
9845 OPERAND_TYPE_IMM32_32S_DISP32
},
9846 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9847 _dummy_first_bfd_reloc_code_real
},
9848 OPERAND_TYPE_NONE
},
9849 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9850 BFD_RELOC_X86_64_TLSLD
},
9851 OPERAND_TYPE_IMM32_32S_DISP32
},
9852 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9853 BFD_RELOC_X86_64_GOTTPOFF
},
9854 OPERAND_TYPE_IMM32_32S_DISP32
},
9855 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9856 BFD_RELOC_X86_64_TPOFF32
},
9857 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9858 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9859 _dummy_first_bfd_reloc_code_real
},
9860 OPERAND_TYPE_NONE
},
9861 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9862 BFD_RELOC_X86_64_DTPOFF32
},
9863 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9864 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9865 _dummy_first_bfd_reloc_code_real
},
9866 OPERAND_TYPE_NONE
},
9867 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9868 _dummy_first_bfd_reloc_code_real
},
9869 OPERAND_TYPE_NONE
},
9870 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9871 BFD_RELOC_X86_64_GOT32
},
9872 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9873 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9874 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9875 OPERAND_TYPE_IMM32_32S_DISP32
},
9876 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9877 BFD_RELOC_X86_64_TLSDESC_CALL
},
9878 OPERAND_TYPE_IMM32_32S_DISP32
},
9883 #if defined (OBJ_MAYBE_ELF)
9888 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9889 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9892 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9894 int len
= gotrel
[j
].len
;
9895 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9897 if (gotrel
[j
].rel
[object_64bit
] != 0)
9900 char *tmpbuf
, *past_reloc
;
9902 *rel
= gotrel
[j
].rel
[object_64bit
];
9906 if (flag_code
!= CODE_64BIT
)
9908 types
->bitfield
.imm32
= 1;
9909 types
->bitfield
.disp32
= 1;
9912 *types
= gotrel
[j
].types64
;
9915 if (j
!= 0 && GOT_symbol
== NULL
)
9916 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9918 /* The length of the first part of our input line. */
9919 first
= cp
- input_line_pointer
;
9921 /* The second part goes from after the reloc token until
9922 (and including) an end_of_line char or comma. */
9923 past_reloc
= cp
+ 1 + len
;
9925 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9927 second
= cp
+ 1 - past_reloc
;
9929 /* Allocate and copy string. The trailing NUL shouldn't
9930 be necessary, but be safe. */
9931 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9932 memcpy (tmpbuf
, input_line_pointer
, first
);
9933 if (second
!= 0 && *past_reloc
!= ' ')
9934 /* Replace the relocation token with ' ', so that
9935 errors like foo@GOTOFF1 will be detected. */
9936 tmpbuf
[first
++] = ' ';
9938 /* Increment length by 1 if the relocation token is
9943 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9944 tmpbuf
[first
+ second
] = '\0';
9948 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9949 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9954 /* Might be a symbol version string. Don't as_bad here. */
9963 /* Parse operands of the form
9964 <symbol>@SECREL32+<nnn>
9966 If we find one, set up the correct relocation in RELOC and copy the
9967 input string, minus the `@SECREL32' into a malloc'd buffer for
9968 parsing by the calling routine. Return this buffer, and if ADJUST
9969 is non-null set it to the length of the string we removed from the
9970 input line. Otherwise return NULL.
9972 This function is copied from the ELF version above adjusted for PE targets. */
9975 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9976 int *adjust ATTRIBUTE_UNUSED
,
9977 i386_operand_type
*types
)
9983 const enum bfd_reloc_code_real rel
[2];
9984 const i386_operand_type types64
;
9988 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9989 BFD_RELOC_32_SECREL
},
9990 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9996 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9997 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10000 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10002 int len
= gotrel
[j
].len
;
10004 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10006 if (gotrel
[j
].rel
[object_64bit
] != 0)
10009 char *tmpbuf
, *past_reloc
;
10011 *rel
= gotrel
[j
].rel
[object_64bit
];
10017 if (flag_code
!= CODE_64BIT
)
10019 types
->bitfield
.imm32
= 1;
10020 types
->bitfield
.disp32
= 1;
10023 *types
= gotrel
[j
].types64
;
10026 /* The length of the first part of our input line. */
10027 first
= cp
- input_line_pointer
;
10029 /* The second part goes from after the reloc token until
10030 (and including) an end_of_line char or comma. */
10031 past_reloc
= cp
+ 1 + len
;
10033 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10035 second
= cp
+ 1 - past_reloc
;
10037 /* Allocate and copy string. The trailing NUL shouldn't
10038 be necessary, but be safe. */
10039 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10040 memcpy (tmpbuf
, input_line_pointer
, first
);
10041 if (second
!= 0 && *past_reloc
!= ' ')
10042 /* Replace the relocation token with ' ', so that
10043 errors like foo@SECLREL321 will be detected. */
10044 tmpbuf
[first
++] = ' ';
10045 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10046 tmpbuf
[first
+ second
] = '\0';
10050 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10051 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10056 /* Might be a symbol version string. Don't as_bad here. */
10062 bfd_reloc_code_real_type
10063 x86_cons (expressionS
*exp
, int size
)
10065 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10067 intel_syntax
= -intel_syntax
;
10070 if (size
== 4 || (object_64bit
&& size
== 8))
10072 /* Handle @GOTOFF and the like in an expression. */
10074 char *gotfree_input_line
;
10077 save
= input_line_pointer
;
10078 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10079 if (gotfree_input_line
)
10080 input_line_pointer
= gotfree_input_line
;
10084 if (gotfree_input_line
)
10086 /* expression () has merrily parsed up to the end of line,
10087 or a comma - in the wrong buffer. Transfer how far
10088 input_line_pointer has moved to the right buffer. */
10089 input_line_pointer
= (save
10090 + (input_line_pointer
- gotfree_input_line
)
10092 free (gotfree_input_line
);
10093 if (exp
->X_op
== O_constant
10094 || exp
->X_op
== O_absent
10095 || exp
->X_op
== O_illegal
10096 || exp
->X_op
== O_register
10097 || exp
->X_op
== O_big
)
10099 char c
= *input_line_pointer
;
10100 *input_line_pointer
= 0;
10101 as_bad (_("missing or invalid expression `%s'"), save
);
10102 *input_line_pointer
= c
;
10104 else if ((got_reloc
== BFD_RELOC_386_PLT32
10105 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10106 && exp
->X_op
!= O_symbol
)
10108 char c
= *input_line_pointer
;
10109 *input_line_pointer
= 0;
10110 as_bad (_("invalid PLT expression `%s'"), save
);
10111 *input_line_pointer
= c
;
10118 intel_syntax
= -intel_syntax
;
10121 i386_intel_simplify (exp
);
10127 signed_cons (int size
)
10129 if (flag_code
== CODE_64BIT
)
10137 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10144 if (exp
.X_op
== O_symbol
)
10145 exp
.X_op
= O_secrel
;
10147 emit_expr (&exp
, 4);
10149 while (*input_line_pointer
++ == ',');
10151 input_line_pointer
--;
10152 demand_empty_rest_of_line ();
10156 /* Handle Vector operations. */
10159 check_VecOperations (char *op_string
, char *op_end
)
10161 const reg_entry
*mask
;
10166 && (op_end
== NULL
|| op_string
< op_end
))
10169 if (*op_string
== '{')
10173 /* Check broadcasts. */
10174 if (strncmp (op_string
, "1to", 3) == 0)
10179 goto duplicated_vec_op
;
10182 if (*op_string
== '8')
10184 else if (*op_string
== '4')
10186 else if (*op_string
== '2')
10188 else if (*op_string
== '1'
10189 && *(op_string
+1) == '6')
10196 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10201 broadcast_op
.type
= bcst_type
;
10202 broadcast_op
.operand
= this_operand
;
10203 broadcast_op
.bytes
= 0;
10204 i
.broadcast
= &broadcast_op
;
10206 /* Check masking operation. */
10207 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10209 if (mask
== &bad_reg
)
10212 /* k0 can't be used for write mask. */
10213 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10215 as_bad (_("`%s%s' can't be used for write mask"),
10216 register_prefix
, mask
->reg_name
);
10222 mask_op
.mask
= mask
;
10223 mask_op
.zeroing
= 0;
10224 mask_op
.operand
= this_operand
;
10230 goto duplicated_vec_op
;
10232 i
.mask
->mask
= mask
;
10234 /* Only "{z}" is allowed here. No need to check
10235 zeroing mask explicitly. */
10236 if (i
.mask
->operand
!= this_operand
)
10238 as_bad (_("invalid write mask `%s'"), saved
);
10243 op_string
= end_op
;
10245 /* Check zeroing-flag for masking operation. */
10246 else if (*op_string
== 'z')
10250 mask_op
.mask
= NULL
;
10251 mask_op
.zeroing
= 1;
10252 mask_op
.operand
= this_operand
;
10257 if (i
.mask
->zeroing
)
10260 as_bad (_("duplicated `%s'"), saved
);
10264 i
.mask
->zeroing
= 1;
10266 /* Only "{%k}" is allowed here. No need to check mask
10267 register explicitly. */
10268 if (i
.mask
->operand
!= this_operand
)
10270 as_bad (_("invalid zeroing-masking `%s'"),
10279 goto unknown_vec_op
;
10281 if (*op_string
!= '}')
10283 as_bad (_("missing `}' in `%s'"), saved
);
10288 /* Strip whitespace since the addition of pseudo prefixes
10289 changed how the scrubber treats '{'. */
10290 if (is_space_char (*op_string
))
10296 /* We don't know this one. */
10297 as_bad (_("unknown vector operation: `%s'"), saved
);
10301 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10303 as_bad (_("zeroing-masking only allowed with write mask"));
10311 i386_immediate (char *imm_start
)
10313 char *save_input_line_pointer
;
10314 char *gotfree_input_line
;
10317 i386_operand_type types
;
10319 operand_type_set (&types
, ~0);
10321 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10323 as_bad (_("at most %d immediate operands are allowed"),
10324 MAX_IMMEDIATE_OPERANDS
);
10328 exp
= &im_expressions
[i
.imm_operands
++];
10329 i
.op
[this_operand
].imms
= exp
;
10331 if (is_space_char (*imm_start
))
10334 save_input_line_pointer
= input_line_pointer
;
10335 input_line_pointer
= imm_start
;
10337 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10338 if (gotfree_input_line
)
10339 input_line_pointer
= gotfree_input_line
;
10341 exp_seg
= expression (exp
);
10343 SKIP_WHITESPACE ();
10345 /* Handle vector operations. */
10346 if (*input_line_pointer
== '{')
10348 input_line_pointer
= check_VecOperations (input_line_pointer
,
10350 if (input_line_pointer
== NULL
)
10354 if (*input_line_pointer
)
10355 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10357 input_line_pointer
= save_input_line_pointer
;
10358 if (gotfree_input_line
)
10360 free (gotfree_input_line
);
10362 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10363 exp
->X_op
= O_illegal
;
10366 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10370 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10371 i386_operand_type types
, const char *imm_start
)
10373 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10376 as_bad (_("missing or invalid immediate expression `%s'"),
10380 else if (exp
->X_op
== O_constant
)
10382 /* Size it properly later. */
10383 i
.types
[this_operand
].bitfield
.imm64
= 1;
10384 /* If not 64bit, sign extend val. */
10385 if (flag_code
!= CODE_64BIT
10386 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10388 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10390 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10391 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10392 && exp_seg
!= absolute_section
10393 && exp_seg
!= text_section
10394 && exp_seg
!= data_section
10395 && exp_seg
!= bss_section
10396 && exp_seg
!= undefined_section
10397 && !bfd_is_com_section (exp_seg
))
10399 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10403 else if (!intel_syntax
&& exp_seg
== reg_section
)
10406 as_bad (_("illegal immediate register operand %s"), imm_start
);
10411 /* This is an address. The size of the address will be
10412 determined later, depending on destination register,
10413 suffix, or the default for the section. */
10414 i
.types
[this_operand
].bitfield
.imm8
= 1;
10415 i
.types
[this_operand
].bitfield
.imm16
= 1;
10416 i
.types
[this_operand
].bitfield
.imm32
= 1;
10417 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10418 i
.types
[this_operand
].bitfield
.imm64
= 1;
10419 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10427 i386_scale (char *scale
)
10430 char *save
= input_line_pointer
;
10432 input_line_pointer
= scale
;
10433 val
= get_absolute_expression ();
10438 i
.log2_scale_factor
= 0;
10441 i
.log2_scale_factor
= 1;
10444 i
.log2_scale_factor
= 2;
10447 i
.log2_scale_factor
= 3;
10451 char sep
= *input_line_pointer
;
10453 *input_line_pointer
= '\0';
10454 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10456 *input_line_pointer
= sep
;
10457 input_line_pointer
= save
;
10461 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10463 as_warn (_("scale factor of %d without an index register"),
10464 1 << i
.log2_scale_factor
);
10465 i
.log2_scale_factor
= 0;
10467 scale
= input_line_pointer
;
10468 input_line_pointer
= save
;
10473 i386_displacement (char *disp_start
, char *disp_end
)
10477 char *save_input_line_pointer
;
10478 char *gotfree_input_line
;
10480 i386_operand_type bigdisp
, types
= anydisp
;
10483 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10485 as_bad (_("at most %d displacement operands are allowed"),
10486 MAX_MEMORY_OPERANDS
);
10490 operand_type_set (&bigdisp
, 0);
10492 || i
.types
[this_operand
].bitfield
.baseindex
10493 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10494 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10496 i386_addressing_mode ();
10497 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10498 if (flag_code
== CODE_64BIT
)
10502 bigdisp
.bitfield
.disp32s
= 1;
10503 bigdisp
.bitfield
.disp64
= 1;
10506 bigdisp
.bitfield
.disp32
= 1;
10508 else if ((flag_code
== CODE_16BIT
) ^ override
)
10509 bigdisp
.bitfield
.disp16
= 1;
10511 bigdisp
.bitfield
.disp32
= 1;
10515 /* For PC-relative branches, the width of the displacement may be
10516 dependent upon data size, but is never dependent upon address size.
10517 Also make sure to not unintentionally match against a non-PC-relative
10518 branch template. */
10519 static templates aux_templates
;
10520 const insn_template
*t
= current_templates
->start
;
10521 bfd_boolean has_intel64
= FALSE
;
10523 aux_templates
.start
= t
;
10524 while (++t
< current_templates
->end
)
10526 if (t
->opcode_modifier
.jump
10527 != current_templates
->start
->opcode_modifier
.jump
)
10529 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10530 has_intel64
= TRUE
;
10532 if (t
< current_templates
->end
)
10534 aux_templates
.end
= t
;
10535 current_templates
= &aux_templates
;
10538 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10539 if (flag_code
== CODE_64BIT
)
10541 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10542 && (!intel64
|| !has_intel64
))
10543 bigdisp
.bitfield
.disp16
= 1;
10545 bigdisp
.bitfield
.disp32s
= 1;
10550 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10552 : LONG_MNEM_SUFFIX
));
10553 bigdisp
.bitfield
.disp32
= 1;
10554 if ((flag_code
== CODE_16BIT
) ^ override
)
10556 bigdisp
.bitfield
.disp32
= 0;
10557 bigdisp
.bitfield
.disp16
= 1;
10561 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10564 exp
= &disp_expressions
[i
.disp_operands
];
10565 i
.op
[this_operand
].disps
= exp
;
10567 save_input_line_pointer
= input_line_pointer
;
10568 input_line_pointer
= disp_start
;
10569 END_STRING_AND_SAVE (disp_end
);
10571 #ifndef GCC_ASM_O_HACK
10572 #define GCC_ASM_O_HACK 0
10575 END_STRING_AND_SAVE (disp_end
+ 1);
10576 if (i
.types
[this_operand
].bitfield
.baseIndex
10577 && displacement_string_end
[-1] == '+')
10579 /* This hack is to avoid a warning when using the "o"
10580 constraint within gcc asm statements.
10583 #define _set_tssldt_desc(n,addr,limit,type) \
10584 __asm__ __volatile__ ( \
10585 "movw %w2,%0\n\t" \
10586 "movw %w1,2+%0\n\t" \
10587 "rorl $16,%1\n\t" \
10588 "movb %b1,4+%0\n\t" \
10589 "movb %4,5+%0\n\t" \
10590 "movb $0,6+%0\n\t" \
10591 "movb %h1,7+%0\n\t" \
10593 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10595 This works great except that the output assembler ends
10596 up looking a bit weird if it turns out that there is
10597 no offset. You end up producing code that looks like:
10610 So here we provide the missing zero. */
10612 *displacement_string_end
= '0';
10615 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10616 if (gotfree_input_line
)
10617 input_line_pointer
= gotfree_input_line
;
10619 exp_seg
= expression (exp
);
10621 SKIP_WHITESPACE ();
10622 if (*input_line_pointer
)
10623 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10625 RESTORE_END_STRING (disp_end
+ 1);
10627 input_line_pointer
= save_input_line_pointer
;
10628 if (gotfree_input_line
)
10630 free (gotfree_input_line
);
10632 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10633 exp
->X_op
= O_illegal
;
10636 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10638 RESTORE_END_STRING (disp_end
);
10644 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10645 i386_operand_type types
, const char *disp_start
)
10647 i386_operand_type bigdisp
;
10650 /* We do this to make sure that the section symbol is in
10651 the symbol table. We will ultimately change the relocation
10652 to be relative to the beginning of the section. */
10653 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10654 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10655 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10657 if (exp
->X_op
!= O_symbol
)
10660 if (S_IS_LOCAL (exp
->X_add_symbol
)
10661 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10662 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10663 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10664 exp
->X_op
= O_subtract
;
10665 exp
->X_op_symbol
= GOT_symbol
;
10666 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10667 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10668 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10669 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10671 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10674 else if (exp
->X_op
== O_absent
10675 || exp
->X_op
== O_illegal
10676 || exp
->X_op
== O_big
)
10679 as_bad (_("missing or invalid displacement expression `%s'"),
10684 else if (flag_code
== CODE_64BIT
10685 && !i
.prefix
[ADDR_PREFIX
]
10686 && exp
->X_op
== O_constant
)
10688 /* Since displacement is signed extended to 64bit, don't allow
10689 disp32 and turn off disp32s if they are out of range. */
10690 i
.types
[this_operand
].bitfield
.disp32
= 0;
10691 if (!fits_in_signed_long (exp
->X_add_number
))
10693 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10694 if (i
.types
[this_operand
].bitfield
.baseindex
)
10696 as_bad (_("0x%lx out range of signed 32bit displacement"),
10697 (long) exp
->X_add_number
);
10703 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10704 else if (exp
->X_op
!= O_constant
10705 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10706 && exp_seg
!= absolute_section
10707 && exp_seg
!= text_section
10708 && exp_seg
!= data_section
10709 && exp_seg
!= bss_section
10710 && exp_seg
!= undefined_section
10711 && !bfd_is_com_section (exp_seg
))
10713 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10718 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10719 /* Constants get taken care of by optimize_disp(). */
10720 && exp
->X_op
!= O_constant
)
10721 i
.types
[this_operand
].bitfield
.disp8
= 1;
10723 /* Check if this is a displacement only operand. */
10724 bigdisp
= i
.types
[this_operand
];
10725 bigdisp
.bitfield
.disp8
= 0;
10726 bigdisp
.bitfield
.disp16
= 0;
10727 bigdisp
.bitfield
.disp32
= 0;
10728 bigdisp
.bitfield
.disp32s
= 0;
10729 bigdisp
.bitfield
.disp64
= 0;
10730 if (operand_type_all_zero (&bigdisp
))
10731 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10737 /* Return the active addressing mode, taking address override and
10738 registers forming the address into consideration. Update the
10739 address override prefix if necessary. */
10741 static enum flag_code
10742 i386_addressing_mode (void)
10744 enum flag_code addr_mode
;
10746 if (i
.prefix
[ADDR_PREFIX
])
10747 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10748 else if (flag_code
== CODE_16BIT
10749 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10750 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10751 from md_assemble() by "is not a valid base/index expression"
10752 when there is a base and/or index. */
10753 && !i
.types
[this_operand
].bitfield
.baseindex
)
10755 /* MPX insn memory operands with neither base nor index must be forced
10756 to use 32-bit addressing in 16-bit mode. */
10757 addr_mode
= CODE_32BIT
;
10758 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10760 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10761 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10765 addr_mode
= flag_code
;
10767 #if INFER_ADDR_PREFIX
10768 if (i
.mem_operands
== 0)
10770 /* Infer address prefix from the first memory operand. */
10771 const reg_entry
*addr_reg
= i
.base_reg
;
10773 if (addr_reg
== NULL
)
10774 addr_reg
= i
.index_reg
;
10778 if (addr_reg
->reg_type
.bitfield
.dword
)
10779 addr_mode
= CODE_32BIT
;
10780 else if (flag_code
!= CODE_64BIT
10781 && addr_reg
->reg_type
.bitfield
.word
)
10782 addr_mode
= CODE_16BIT
;
10784 if (addr_mode
!= flag_code
)
10786 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10788 /* Change the size of any displacement too. At most one
10789 of Disp16 or Disp32 is set.
10790 FIXME. There doesn't seem to be any real need for
10791 separate Disp16 and Disp32 flags. The same goes for
10792 Imm16 and Imm32. Removing them would probably clean
10793 up the code quite a lot. */
10794 if (flag_code
!= CODE_64BIT
10795 && (i
.types
[this_operand
].bitfield
.disp16
10796 || i
.types
[this_operand
].bitfield
.disp32
))
10797 i
.types
[this_operand
]
10798 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10808 /* Make sure the memory operand we've been dealt is valid.
10809 Return 1 on success, 0 on a failure. */
10812 i386_index_check (const char *operand_string
)
10814 const char *kind
= "base/index";
10815 enum flag_code addr_mode
= i386_addressing_mode ();
10817 if (current_templates
->start
->opcode_modifier
.isstring
10818 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10819 && (current_templates
->end
[-1].opcode_modifier
.isstring
10820 || i
.mem_operands
))
10822 /* Memory operands of string insns are special in that they only allow
10823 a single register (rDI, rSI, or rBX) as their memory address. */
10824 const reg_entry
*expected_reg
;
10825 static const char *di_si
[][2] =
10831 static const char *bx
[] = { "ebx", "bx", "rbx" };
10833 kind
= "string address";
10835 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10837 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10838 - IS_STRING_ES_OP0
;
10841 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10842 || ((!i
.mem_operands
!= !intel_syntax
)
10843 && current_templates
->end
[-1].operand_types
[1]
10844 .bitfield
.baseindex
))
10846 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10849 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10851 if (i
.base_reg
!= expected_reg
10853 || operand_type_check (i
.types
[this_operand
], disp
))
10855 /* The second memory operand must have the same size as
10859 && !((addr_mode
== CODE_64BIT
10860 && i
.base_reg
->reg_type
.bitfield
.qword
)
10861 || (addr_mode
== CODE_32BIT
10862 ? i
.base_reg
->reg_type
.bitfield
.dword
10863 : i
.base_reg
->reg_type
.bitfield
.word
)))
10866 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10868 intel_syntax
? '[' : '(',
10870 expected_reg
->reg_name
,
10871 intel_syntax
? ']' : ')');
10878 as_bad (_("`%s' is not a valid %s expression"),
10879 operand_string
, kind
);
10884 if (addr_mode
!= CODE_16BIT
)
10886 /* 32-bit/64-bit checks. */
10888 && ((addr_mode
== CODE_64BIT
10889 ? !i
.base_reg
->reg_type
.bitfield
.qword
10890 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10891 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10892 || i
.base_reg
->reg_num
== RegIZ
))
10894 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10895 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10896 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10897 && ((addr_mode
== CODE_64BIT
10898 ? !i
.index_reg
->reg_type
.bitfield
.qword
10899 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10900 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10903 /* bndmk, bndldx, and bndstx have special restrictions. */
10904 if (current_templates
->start
->base_opcode
== 0xf30f1b
10905 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10907 /* They cannot use RIP-relative addressing. */
10908 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10910 as_bad (_("`%s' cannot be used here"), operand_string
);
10914 /* bndldx and bndstx ignore their scale factor. */
10915 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10916 && i
.log2_scale_factor
)
10917 as_warn (_("register scaling is being ignored here"));
10922 /* 16-bit checks. */
10924 && (!i
.base_reg
->reg_type
.bitfield
.word
10925 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10927 && (!i
.index_reg
->reg_type
.bitfield
.word
10928 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10930 && i
.base_reg
->reg_num
< 6
10931 && i
.index_reg
->reg_num
>= 6
10932 && i
.log2_scale_factor
== 0))))
10939 /* Handle vector immediates. */
10942 RC_SAE_immediate (const char *imm_start
)
10944 unsigned int match_found
, j
;
10945 const char *pstr
= imm_start
;
10953 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10955 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10959 rc_op
.type
= RC_NamesTable
[j
].type
;
10960 rc_op
.operand
= this_operand
;
10961 i
.rounding
= &rc_op
;
10965 as_bad (_("duplicated `%s'"), imm_start
);
10968 pstr
+= RC_NamesTable
[j
].len
;
10976 if (*pstr
++ != '}')
10978 as_bad (_("Missing '}': '%s'"), imm_start
);
10981 /* RC/SAE immediate string should contain nothing more. */;
10984 as_bad (_("Junk after '}': '%s'"), imm_start
);
10988 exp
= &im_expressions
[i
.imm_operands
++];
10989 i
.op
[this_operand
].imms
= exp
;
10991 exp
->X_op
= O_constant
;
10992 exp
->X_add_number
= 0;
10993 exp
->X_add_symbol
= (symbolS
*) 0;
10994 exp
->X_op_symbol
= (symbolS
*) 0;
10996 i
.types
[this_operand
].bitfield
.imm8
= 1;
11000 /* Only string instructions can have a second memory operand, so
11001 reduce current_templates to just those if it contains any. */
11003 maybe_adjust_templates (void)
11005 const insn_template
*t
;
11007 gas_assert (i
.mem_operands
== 1);
11009 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11010 if (t
->opcode_modifier
.isstring
)
11013 if (t
< current_templates
->end
)
11015 static templates aux_templates
;
11016 bfd_boolean recheck
;
11018 aux_templates
.start
= t
;
11019 for (; t
< current_templates
->end
; ++t
)
11020 if (!t
->opcode_modifier
.isstring
)
11022 aux_templates
.end
= t
;
11024 /* Determine whether to re-check the first memory operand. */
11025 recheck
= (aux_templates
.start
!= current_templates
->start
11026 || t
!= current_templates
->end
);
11028 current_templates
= &aux_templates
;
11032 i
.mem_operands
= 0;
11033 if (i
.memop1_string
!= NULL
11034 && i386_index_check (i
.memop1_string
) == 0)
11036 i
.mem_operands
= 1;
11043 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11047 i386_att_operand (char *operand_string
)
11049 const reg_entry
*r
;
11051 char *op_string
= operand_string
;
11053 if (is_space_char (*op_string
))
11056 /* We check for an absolute prefix (differentiating,
11057 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11058 if (*op_string
== ABSOLUTE_PREFIX
)
11061 if (is_space_char (*op_string
))
11063 i
.jumpabsolute
= TRUE
;
11066 /* Check if operand is a register. */
11067 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11069 i386_operand_type temp
;
11074 /* Check for a segment override by searching for ':' after a
11075 segment register. */
11076 op_string
= end_op
;
11077 if (is_space_char (*op_string
))
11079 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11081 switch (r
->reg_num
)
11084 i
.seg
[i
.mem_operands
] = &es
;
11087 i
.seg
[i
.mem_operands
] = &cs
;
11090 i
.seg
[i
.mem_operands
] = &ss
;
11093 i
.seg
[i
.mem_operands
] = &ds
;
11096 i
.seg
[i
.mem_operands
] = &fs
;
11099 i
.seg
[i
.mem_operands
] = &gs
;
11103 /* Skip the ':' and whitespace. */
11105 if (is_space_char (*op_string
))
11108 if (!is_digit_char (*op_string
)
11109 && !is_identifier_char (*op_string
)
11110 && *op_string
!= '('
11111 && *op_string
!= ABSOLUTE_PREFIX
)
11113 as_bad (_("bad memory operand `%s'"), op_string
);
11116 /* Handle case of %es:*foo. */
11117 if (*op_string
== ABSOLUTE_PREFIX
)
11120 if (is_space_char (*op_string
))
11122 i
.jumpabsolute
= TRUE
;
11124 goto do_memory_reference
;
11127 /* Handle vector operations. */
11128 if (*op_string
== '{')
11130 op_string
= check_VecOperations (op_string
, NULL
);
11131 if (op_string
== NULL
)
11137 as_bad (_("junk `%s' after register"), op_string
);
11140 temp
= r
->reg_type
;
11141 temp
.bitfield
.baseindex
= 0;
11142 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11144 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11145 i
.op
[this_operand
].regs
= r
;
11148 else if (*op_string
== REGISTER_PREFIX
)
11150 as_bad (_("bad register name `%s'"), op_string
);
11153 else if (*op_string
== IMMEDIATE_PREFIX
)
11156 if (i
.jumpabsolute
)
11158 as_bad (_("immediate operand illegal with absolute jump"));
11161 if (!i386_immediate (op_string
))
11164 else if (RC_SAE_immediate (operand_string
))
11166 /* If it is a RC or SAE immediate, do nothing. */
11169 else if (is_digit_char (*op_string
)
11170 || is_identifier_char (*op_string
)
11171 || *op_string
== '"'
11172 || *op_string
== '(')
11174 /* This is a memory reference of some sort. */
11177 /* Start and end of displacement string expression (if found). */
11178 char *displacement_string_start
;
11179 char *displacement_string_end
;
11182 do_memory_reference
:
11183 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11185 if ((i
.mem_operands
== 1
11186 && !current_templates
->start
->opcode_modifier
.isstring
)
11187 || i
.mem_operands
== 2)
11189 as_bad (_("too many memory references for `%s'"),
11190 current_templates
->start
->name
);
11194 /* Check for base index form. We detect the base index form by
11195 looking for an ')' at the end of the operand, searching
11196 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11198 base_string
= op_string
+ strlen (op_string
);
11200 /* Handle vector operations. */
11201 vop_start
= strchr (op_string
, '{');
11202 if (vop_start
&& vop_start
< base_string
)
11204 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11206 base_string
= vop_start
;
11210 if (is_space_char (*base_string
))
11213 /* If we only have a displacement, set-up for it to be parsed later. */
11214 displacement_string_start
= op_string
;
11215 displacement_string_end
= base_string
+ 1;
11217 if (*base_string
== ')')
11220 unsigned int parens_balanced
= 1;
11221 /* We've already checked that the number of left & right ()'s are
11222 equal, so this loop will not be infinite. */
11226 if (*base_string
== ')')
11228 if (*base_string
== '(')
11231 while (parens_balanced
);
11233 temp_string
= base_string
;
11235 /* Skip past '(' and whitespace. */
11237 if (is_space_char (*base_string
))
11240 if (*base_string
== ','
11241 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11244 displacement_string_end
= temp_string
;
11246 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11250 if (i
.base_reg
== &bad_reg
)
11252 base_string
= end_op
;
11253 if (is_space_char (*base_string
))
11257 /* There may be an index reg or scale factor here. */
11258 if (*base_string
== ',')
11261 if (is_space_char (*base_string
))
11264 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11267 if (i
.index_reg
== &bad_reg
)
11269 base_string
= end_op
;
11270 if (is_space_char (*base_string
))
11272 if (*base_string
== ',')
11275 if (is_space_char (*base_string
))
11278 else if (*base_string
!= ')')
11280 as_bad (_("expecting `,' or `)' "
11281 "after index register in `%s'"),
11286 else if (*base_string
== REGISTER_PREFIX
)
11288 end_op
= strchr (base_string
, ',');
11291 as_bad (_("bad register name `%s'"), base_string
);
11295 /* Check for scale factor. */
11296 if (*base_string
!= ')')
11298 char *end_scale
= i386_scale (base_string
);
11303 base_string
= end_scale
;
11304 if (is_space_char (*base_string
))
11306 if (*base_string
!= ')')
11308 as_bad (_("expecting `)' "
11309 "after scale factor in `%s'"),
11314 else if (!i
.index_reg
)
11316 as_bad (_("expecting index register or scale factor "
11317 "after `,'; got '%c'"),
11322 else if (*base_string
!= ')')
11324 as_bad (_("expecting `,' or `)' "
11325 "after base register in `%s'"),
11330 else if (*base_string
== REGISTER_PREFIX
)
11332 end_op
= strchr (base_string
, ',');
11335 as_bad (_("bad register name `%s'"), base_string
);
11340 /* If there's an expression beginning the operand, parse it,
11341 assuming displacement_string_start and
11342 displacement_string_end are meaningful. */
11343 if (displacement_string_start
!= displacement_string_end
)
11345 if (!i386_displacement (displacement_string_start
,
11346 displacement_string_end
))
11350 /* Special case for (%dx) while doing input/output op. */
11352 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11353 && i
.base_reg
->reg_type
.bitfield
.word
11354 && i
.index_reg
== 0
11355 && i
.log2_scale_factor
== 0
11356 && i
.seg
[i
.mem_operands
] == 0
11357 && !operand_type_check (i
.types
[this_operand
], disp
))
11359 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11363 if (i386_index_check (operand_string
) == 0)
11365 i
.flags
[this_operand
] |= Operand_Mem
;
11366 if (i
.mem_operands
== 0)
11367 i
.memop1_string
= xstrdup (operand_string
);
11372 /* It's not a memory operand; argh! */
11373 as_bad (_("invalid char %s beginning operand %d `%s'"),
11374 output_invalid (*op_string
),
11379 return 1; /* Normal return. */
11382 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11383 that an rs_machine_dependent frag may reach. */
11386 i386_frag_max_var (fragS
*frag
)
11388 /* The only relaxable frags are for jumps.
11389 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11390 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11391 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11394 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11396 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11398 /* STT_GNU_IFUNC symbol must go through PLT. */
11399 if ((symbol_get_bfdsym (fr_symbol
)->flags
11400 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11403 if (!S_IS_EXTERNAL (fr_symbol
))
11404 /* Symbol may be weak or local. */
11405 return !S_IS_WEAK (fr_symbol
);
11407 /* Global symbols with non-default visibility can't be preempted. */
11408 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11411 if (fr_var
!= NO_RELOC
)
11412 switch ((enum bfd_reloc_code_real
) fr_var
)
11414 case BFD_RELOC_386_PLT32
:
11415 case BFD_RELOC_X86_64_PLT32
:
11416 /* Symbol with PLT relocation may be preempted. */
11422 /* Global symbols with default visibility in a shared library may be
11423 preempted by another definition. */
11428 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11429 Note also work for Skylake and Cascadelake.
11430 ---------------------------------------------------------------------
11431 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11432 | ------ | ----------- | ------- | -------- |
11434 | Jno | N | N | Y |
11435 | Jc/Jb | Y | N | Y |
11436 | Jae/Jnb | Y | N | Y |
11437 | Je/Jz | Y | Y | Y |
11438 | Jne/Jnz | Y | Y | Y |
11439 | Jna/Jbe | Y | N | Y |
11440 | Ja/Jnbe | Y | N | Y |
11442 | Jns | N | N | Y |
11443 | Jp/Jpe | N | N | Y |
11444 | Jnp/Jpo | N | N | Y |
11445 | Jl/Jnge | Y | Y | Y |
11446 | Jge/Jnl | Y | Y | Y |
11447 | Jle/Jng | Y | Y | Y |
11448 | Jg/Jnle | Y | Y | Y |
11449 --------------------------------------------------------------------- */
11451 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11453 if (mf_cmp
== mf_cmp_alu_cmp
)
11454 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11455 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11456 if (mf_cmp
== mf_cmp_incdec
)
11457 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11458 || mf_jcc
== mf_jcc_jle
);
11459 if (mf_cmp
== mf_cmp_test_and
)
11464 /* Return the next non-empty frag. */
11467 i386_next_non_empty_frag (fragS
*fragP
)
11469 /* There may be a frag with a ".fill 0" when there is no room in
11470 the current frag for frag_grow in output_insn. */
11471 for (fragP
= fragP
->fr_next
;
11473 && fragP
->fr_type
== rs_fill
11474 && fragP
->fr_fix
== 0);
11475 fragP
= fragP
->fr_next
)
11480 /* Return the next jcc frag after BRANCH_PADDING. */
11483 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11485 fragS
*branch_fragP
;
11489 if (pad_fragP
->fr_type
== rs_machine_dependent
11490 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11491 == BRANCH_PADDING
))
11493 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11494 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11496 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11497 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11498 pad_fragP
->tc_frag_data
.mf_type
))
11499 return branch_fragP
;
11505 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11508 i386_classify_machine_dependent_frag (fragS
*fragP
)
11512 fragS
*branch_fragP
;
11514 unsigned int max_prefix_length
;
11516 if (fragP
->tc_frag_data
.classified
)
11519 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11520 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11521 for (next_fragP
= fragP
;
11522 next_fragP
!= NULL
;
11523 next_fragP
= next_fragP
->fr_next
)
11525 next_fragP
->tc_frag_data
.classified
= 1;
11526 if (next_fragP
->fr_type
== rs_machine_dependent
)
11527 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11529 case BRANCH_PADDING
:
11530 /* The BRANCH_PADDING frag must be followed by a branch
11532 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11533 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11535 case FUSED_JCC_PADDING
:
11536 /* Check if this is a fused jcc:
11538 CMP like instruction
11542 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11543 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11544 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11547 /* The BRANCH_PADDING frag is merged with the
11548 FUSED_JCC_PADDING frag. */
11549 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11550 /* CMP like instruction size. */
11551 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11552 frag_wane (pad_fragP
);
11553 /* Skip to branch_fragP. */
11554 next_fragP
= branch_fragP
;
11556 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11558 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11560 next_fragP
->fr_subtype
11561 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11562 next_fragP
->tc_frag_data
.max_bytes
11563 = next_fragP
->tc_frag_data
.max_prefix_length
;
11564 /* This will be updated in the BRANCH_PREFIX scan. */
11565 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11568 frag_wane (next_fragP
);
11573 /* Stop if there is no BRANCH_PREFIX. */
11574 if (!align_branch_prefix_size
)
11577 /* Scan for BRANCH_PREFIX. */
11578 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11580 if (fragP
->fr_type
!= rs_machine_dependent
11581 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11585 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11586 COND_JUMP_PREFIX. */
11587 max_prefix_length
= 0;
11588 for (next_fragP
= fragP
;
11589 next_fragP
!= NULL
;
11590 next_fragP
= next_fragP
->fr_next
)
11592 if (next_fragP
->fr_type
== rs_fill
)
11593 /* Skip rs_fill frags. */
11595 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11596 /* Stop for all other frags. */
11599 /* rs_machine_dependent frags. */
11600 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11603 /* Count BRANCH_PREFIX frags. */
11604 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11606 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11607 frag_wane (next_fragP
);
11611 += next_fragP
->tc_frag_data
.max_bytes
;
11613 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11615 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11616 == FUSED_JCC_PADDING
))
11618 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11619 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11623 /* Stop for other rs_machine_dependent frags. */
11627 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11629 /* Skip to the next frag. */
11630 fragP
= next_fragP
;
11634 /* Compute padding size for
11637 CMP like instruction
11639 COND_JUMP/UNCOND_JUMP
11644 COND_JUMP/UNCOND_JUMP
11648 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11650 unsigned int offset
, size
, padding_size
;
11651 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11653 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11655 address
= fragP
->fr_address
;
11656 address
+= fragP
->fr_fix
;
11658 /* CMP like instrunction size. */
11659 size
= fragP
->tc_frag_data
.cmp_size
;
11661 /* The base size of the branch frag. */
11662 size
+= branch_fragP
->fr_fix
;
11664 /* Add opcode and displacement bytes for the rs_machine_dependent
11666 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11667 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11669 /* Check if branch is within boundary and doesn't end at the last
11671 offset
= address
& ((1U << align_branch_power
) - 1);
11672 if ((offset
+ size
) >= (1U << align_branch_power
))
11673 /* Padding needed to avoid crossing boundary. */
11674 padding_size
= (1U << align_branch_power
) - offset
;
11676 /* No padding needed. */
11679 /* The return value may be saved in tc_frag_data.length which is
11681 if (!fits_in_unsigned_byte (padding_size
))
11684 return padding_size
;
11687 /* i386_generic_table_relax_frag()
11689 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11690 grow/shrink padding to align branch frags. Hand others to
11694 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11696 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11697 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11699 long padding_size
= i386_branch_padding_size (fragP
, 0);
11700 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11702 /* When the BRANCH_PREFIX frag is used, the computed address
11703 must match the actual address and there should be no padding. */
11704 if (fragP
->tc_frag_data
.padding_address
11705 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11709 /* Update the padding size. */
11711 fragP
->tc_frag_data
.length
= padding_size
;
11715 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11717 fragS
*padding_fragP
, *next_fragP
;
11718 long padding_size
, left_size
, last_size
;
11720 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11721 if (!padding_fragP
)
11722 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11723 return (fragP
->tc_frag_data
.length
11724 - fragP
->tc_frag_data
.last_length
);
11726 /* Compute the relative address of the padding frag in the very
11727 first time where the BRANCH_PREFIX frag sizes are zero. */
11728 if (!fragP
->tc_frag_data
.padding_address
)
11729 fragP
->tc_frag_data
.padding_address
11730 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11732 /* First update the last length from the previous interation. */
11733 left_size
= fragP
->tc_frag_data
.prefix_length
;
11734 for (next_fragP
= fragP
;
11735 next_fragP
!= padding_fragP
;
11736 next_fragP
= next_fragP
->fr_next
)
11737 if (next_fragP
->fr_type
== rs_machine_dependent
11738 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11743 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11747 if (max
> left_size
)
11752 next_fragP
->tc_frag_data
.last_length
= size
;
11756 next_fragP
->tc_frag_data
.last_length
= 0;
11759 /* Check the padding size for the padding frag. */
11760 padding_size
= i386_branch_padding_size
11761 (padding_fragP
, (fragP
->fr_address
11762 + fragP
->tc_frag_data
.padding_address
));
11764 last_size
= fragP
->tc_frag_data
.prefix_length
;
11765 /* Check if there is change from the last interation. */
11766 if (padding_size
== last_size
)
11768 /* Update the expected address of the padding frag. */
11769 padding_fragP
->tc_frag_data
.padding_address
11770 = (fragP
->fr_address
+ padding_size
11771 + fragP
->tc_frag_data
.padding_address
);
11775 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11777 /* No padding if there is no sufficient room. Clear the
11778 expected address of the padding frag. */
11779 padding_fragP
->tc_frag_data
.padding_address
= 0;
11783 /* Store the expected address of the padding frag. */
11784 padding_fragP
->tc_frag_data
.padding_address
11785 = (fragP
->fr_address
+ padding_size
11786 + fragP
->tc_frag_data
.padding_address
);
11788 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11790 /* Update the length for the current interation. */
11791 left_size
= padding_size
;
11792 for (next_fragP
= fragP
;
11793 next_fragP
!= padding_fragP
;
11794 next_fragP
= next_fragP
->fr_next
)
11795 if (next_fragP
->fr_type
== rs_machine_dependent
11796 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11801 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11805 if (max
> left_size
)
11810 next_fragP
->tc_frag_data
.length
= size
;
11814 next_fragP
->tc_frag_data
.length
= 0;
11817 return (fragP
->tc_frag_data
.length
11818 - fragP
->tc_frag_data
.last_length
);
11820 return relax_frag (segment
, fragP
, stretch
);
11823 /* md_estimate_size_before_relax()
11825 Called just before relax() for rs_machine_dependent frags. The x86
11826 assembler uses these frags to handle variable size jump
11829 Any symbol that is now undefined will not become defined.
11830 Return the correct fr_subtype in the frag.
11831 Return the initial "guess for variable size of frag" to caller.
11832 The guess is actually the growth beyond the fixed part. Whatever
11833 we do to grow the fixed or variable part contributes to our
11837 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11839 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11840 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11841 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11843 i386_classify_machine_dependent_frag (fragP
);
11844 return fragP
->tc_frag_data
.length
;
11847 /* We've already got fragP->fr_subtype right; all we have to do is
11848 check for un-relaxable symbols. On an ELF system, we can't relax
11849 an externally visible symbol, because it may be overridden by a
11851 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11852 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11854 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11857 #if defined (OBJ_COFF) && defined (TE_PE)
11858 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11859 && S_IS_WEAK (fragP
->fr_symbol
))
11863 /* Symbol is undefined in this segment, or we need to keep a
11864 reloc so that weak symbols can be overridden. */
11865 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11866 enum bfd_reloc_code_real reloc_type
;
11867 unsigned char *opcode
;
11870 if (fragP
->fr_var
!= NO_RELOC
)
11871 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11872 else if (size
== 2)
11873 reloc_type
= BFD_RELOC_16_PCREL
;
11874 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11875 else if (need_plt32_p (fragP
->fr_symbol
))
11876 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11879 reloc_type
= BFD_RELOC_32_PCREL
;
11881 old_fr_fix
= fragP
->fr_fix
;
11882 opcode
= (unsigned char *) fragP
->fr_opcode
;
11884 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11887 /* Make jmp (0xeb) a (d)word displacement jump. */
11889 fragP
->fr_fix
+= size
;
11890 fix_new (fragP
, old_fr_fix
, size
,
11892 fragP
->fr_offset
, 1,
11898 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11900 /* Negate the condition, and branch past an
11901 unconditional jump. */
11904 /* Insert an unconditional jump. */
11906 /* We added two extra opcode bytes, and have a two byte
11908 fragP
->fr_fix
+= 2 + 2;
11909 fix_new (fragP
, old_fr_fix
+ 2, 2,
11911 fragP
->fr_offset
, 1,
11915 /* Fall through. */
11918 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11922 fragP
->fr_fix
+= 1;
11923 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11925 fragP
->fr_offset
, 1,
11926 BFD_RELOC_8_PCREL
);
11927 fixP
->fx_signed
= 1;
11931 /* This changes the byte-displacement jump 0x7N
11932 to the (d)word-displacement jump 0x0f,0x8N. */
11933 opcode
[1] = opcode
[0] + 0x10;
11934 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11935 /* We've added an opcode byte. */
11936 fragP
->fr_fix
+= 1 + size
;
11937 fix_new (fragP
, old_fr_fix
+ 1, size
,
11939 fragP
->fr_offset
, 1,
11944 BAD_CASE (fragP
->fr_subtype
);
11948 return fragP
->fr_fix
- old_fr_fix
;
11951 /* Guess size depending on current relax state. Initially the relax
11952 state will correspond to a short jump and we return 1, because
11953 the variable part of the frag (the branch offset) is one byte
11954 long. However, we can relax a section more than once and in that
11955 case we must either set fr_subtype back to the unrelaxed state,
11956 or return the value for the appropriate branch. */
11957 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11960 /* Called after relax() is finished.
11962 In: Address of frag.
11963 fr_type == rs_machine_dependent.
11964 fr_subtype is what the address relaxed to.
11966 Out: Any fixSs and constants are set up.
11967 Caller will turn frag into a ".space 0". */
11970 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11973 unsigned char *opcode
;
11974 unsigned char *where_to_put_displacement
= NULL
;
11975 offsetT target_address
;
11976 offsetT opcode_address
;
11977 unsigned int extension
= 0;
11978 offsetT displacement_from_opcode_start
;
11980 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11981 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11982 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11984 /* Generate nop padding. */
11985 unsigned int size
= fragP
->tc_frag_data
.length
;
11988 if (size
> fragP
->tc_frag_data
.max_bytes
)
11994 const char *branch
= "branch";
11995 const char *prefix
= "";
11996 fragS
*padding_fragP
;
11997 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12000 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12001 switch (fragP
->tc_frag_data
.default_prefix
)
12006 case CS_PREFIX_OPCODE
:
12009 case DS_PREFIX_OPCODE
:
12012 case ES_PREFIX_OPCODE
:
12015 case FS_PREFIX_OPCODE
:
12018 case GS_PREFIX_OPCODE
:
12021 case SS_PREFIX_OPCODE
:
12026 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12027 "%s within %d-byte boundary\n");
12029 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12030 "align %s within %d-byte boundary\n");
12034 padding_fragP
= fragP
;
12035 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12036 "%s within %d-byte boundary\n");
12040 switch (padding_fragP
->tc_frag_data
.branch_type
)
12042 case align_branch_jcc
:
12045 case align_branch_fused
:
12046 branch
= "fused jcc";
12048 case align_branch_jmp
:
12051 case align_branch_call
:
12054 case align_branch_indirect
:
12055 branch
= "indiret branch";
12057 case align_branch_ret
:
12064 fprintf (stdout
, msg
,
12065 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12066 (long long) fragP
->fr_address
, branch
,
12067 1 << align_branch_power
);
12069 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12070 memset (fragP
->fr_opcode
,
12071 fragP
->tc_frag_data
.default_prefix
, size
);
12073 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12075 fragP
->fr_fix
+= size
;
12080 opcode
= (unsigned char *) fragP
->fr_opcode
;
12082 /* Address we want to reach in file space. */
12083 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12085 /* Address opcode resides at in file space. */
12086 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12088 /* Displacement from opcode start to fill into instruction. */
12089 displacement_from_opcode_start
= target_address
- opcode_address
;
12091 if ((fragP
->fr_subtype
& BIG
) == 0)
12093 /* Don't have to change opcode. */
12094 extension
= 1; /* 1 opcode + 1 displacement */
12095 where_to_put_displacement
= &opcode
[1];
12099 if (no_cond_jump_promotion
12100 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12101 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12102 _("long jump required"));
12104 switch (fragP
->fr_subtype
)
12106 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12107 extension
= 4; /* 1 opcode + 4 displacement */
12109 where_to_put_displacement
= &opcode
[1];
12112 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12113 extension
= 2; /* 1 opcode + 2 displacement */
12115 where_to_put_displacement
= &opcode
[1];
12118 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12119 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12120 extension
= 5; /* 2 opcode + 4 displacement */
12121 opcode
[1] = opcode
[0] + 0x10;
12122 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12123 where_to_put_displacement
= &opcode
[2];
12126 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12127 extension
= 3; /* 2 opcode + 2 displacement */
12128 opcode
[1] = opcode
[0] + 0x10;
12129 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12130 where_to_put_displacement
= &opcode
[2];
12133 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12138 where_to_put_displacement
= &opcode
[3];
12142 BAD_CASE (fragP
->fr_subtype
);
12147 /* If size if less then four we are sure that the operand fits,
12148 but if it's 4, then it could be that the displacement is larger
12150 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12152 && ((addressT
) (displacement_from_opcode_start
- extension
12153 + ((addressT
) 1 << 31))
12154 > (((addressT
) 2 << 31) - 1)))
12156 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12157 _("jump target out of range"));
12158 /* Make us emit 0. */
12159 displacement_from_opcode_start
= extension
;
12161 /* Now put displacement after opcode. */
12162 md_number_to_chars ((char *) where_to_put_displacement
,
12163 (valueT
) (displacement_from_opcode_start
- extension
),
12164 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12165 fragP
->fr_fix
+= extension
;
12168 /* Apply a fixup (fixP) to segment data, once it has been determined
12169 by our caller that we have all the info we need to fix it up.
12171 Parameter valP is the pointer to the value of the bits.
12173 On the 386, immediates, displacements, and data pointers are all in
12174 the same (little-endian) format, so we don't need to care about which
12175 we are handling. */
12178 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12180 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12181 valueT value
= *valP
;
12183 #if !defined (TE_Mach)
12184 if (fixP
->fx_pcrel
)
12186 switch (fixP
->fx_r_type
)
12192 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12195 case BFD_RELOC_X86_64_32S
:
12196 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12199 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12202 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12207 if (fixP
->fx_addsy
!= NULL
12208 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12209 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12210 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12211 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12212 && !use_rela_relocations
)
12214 /* This is a hack. There should be a better way to handle this.
12215 This covers for the fact that bfd_install_relocation will
12216 subtract the current location (for partial_inplace, PC relative
12217 relocations); see more below. */
12221 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12224 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12226 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12229 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12231 if ((sym_seg
== seg
12232 || (symbol_section_p (fixP
->fx_addsy
)
12233 && sym_seg
!= absolute_section
))
12234 && !generic_force_reloc (fixP
))
12236 /* Yes, we add the values in twice. This is because
12237 bfd_install_relocation subtracts them out again. I think
12238 bfd_install_relocation is broken, but I don't dare change
12240 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12244 #if defined (OBJ_COFF) && defined (TE_PE)
12245 /* For some reason, the PE format does not store a
12246 section address offset for a PC relative symbol. */
12247 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12248 || S_IS_WEAK (fixP
->fx_addsy
))
12249 value
+= md_pcrel_from (fixP
);
12252 #if defined (OBJ_COFF) && defined (TE_PE)
12253 if (fixP
->fx_addsy
!= NULL
12254 && S_IS_WEAK (fixP
->fx_addsy
)
12255 /* PR 16858: Do not modify weak function references. */
12256 && ! fixP
->fx_pcrel
)
12258 #if !defined (TE_PEP)
12259 /* For x86 PE weak function symbols are neither PC-relative
12260 nor do they set S_IS_FUNCTION. So the only reliable way
12261 to detect them is to check the flags of their containing
12263 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12264 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12268 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12272 /* Fix a few things - the dynamic linker expects certain values here,
12273 and we must not disappoint it. */
12274 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12275 if (IS_ELF
&& fixP
->fx_addsy
)
12276 switch (fixP
->fx_r_type
)
12278 case BFD_RELOC_386_PLT32
:
12279 case BFD_RELOC_X86_64_PLT32
:
12280 /* Make the jump instruction point to the address of the operand.
12281 At runtime we merely add the offset to the actual PLT entry.
12282 NB: Subtract the offset size only for jump instructions. */
12283 if (fixP
->fx_pcrel
)
12287 case BFD_RELOC_386_TLS_GD
:
12288 case BFD_RELOC_386_TLS_LDM
:
12289 case BFD_RELOC_386_TLS_IE_32
:
12290 case BFD_RELOC_386_TLS_IE
:
12291 case BFD_RELOC_386_TLS_GOTIE
:
12292 case BFD_RELOC_386_TLS_GOTDESC
:
12293 case BFD_RELOC_X86_64_TLSGD
:
12294 case BFD_RELOC_X86_64_TLSLD
:
12295 case BFD_RELOC_X86_64_GOTTPOFF
:
12296 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12297 value
= 0; /* Fully resolved at runtime. No addend. */
12299 case BFD_RELOC_386_TLS_LE
:
12300 case BFD_RELOC_386_TLS_LDO_32
:
12301 case BFD_RELOC_386_TLS_LE_32
:
12302 case BFD_RELOC_X86_64_DTPOFF32
:
12303 case BFD_RELOC_X86_64_DTPOFF64
:
12304 case BFD_RELOC_X86_64_TPOFF32
:
12305 case BFD_RELOC_X86_64_TPOFF64
:
12306 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12309 case BFD_RELOC_386_TLS_DESC_CALL
:
12310 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12311 value
= 0; /* Fully resolved at runtime. No addend. */
12312 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12316 case BFD_RELOC_VTABLE_INHERIT
:
12317 case BFD_RELOC_VTABLE_ENTRY
:
12324 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12326 #endif /* !defined (TE_Mach) */
12328 /* Are we finished with this relocation now? */
12329 if (fixP
->fx_addsy
== NULL
)
12331 #if defined (OBJ_COFF) && defined (TE_PE)
12332 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12335 /* Remember value for tc_gen_reloc. */
12336 fixP
->fx_addnumber
= value
;
12337 /* Clear out the frag for now. */
12341 else if (use_rela_relocations
)
12343 fixP
->fx_no_overflow
= 1;
12344 /* Remember value for tc_gen_reloc. */
12345 fixP
->fx_addnumber
= value
;
12349 md_number_to_chars (p
, value
, fixP
->fx_size
);
12353 md_atof (int type
, char *litP
, int *sizeP
)
12355 /* This outputs the LITTLENUMs in REVERSE order;
12356 in accord with the bigendian 386. */
12357 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12360 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12363 output_invalid (int c
)
12366 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12369 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12370 "(0x%x)", (unsigned char) c
);
12371 return output_invalid_buf
;
12374 /* Verify that @r can be used in the current context. */
12376 static bfd_boolean
check_register (const reg_entry
*r
)
12378 if (allow_pseudo_reg
)
12381 if (operand_type_all_zero (&r
->reg_type
))
12384 if ((r
->reg_type
.bitfield
.dword
12385 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12386 || r
->reg_type
.bitfield
.class == RegCR
12387 || r
->reg_type
.bitfield
.class == RegDR
)
12388 && !cpu_arch_flags
.bitfield
.cpui386
)
12391 if (r
->reg_type
.bitfield
.class == RegTR
12392 && (flag_code
== CODE_64BIT
12393 || !cpu_arch_flags
.bitfield
.cpui386
12394 || cpu_arch_isa_flags
.bitfield
.cpui586
12395 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12398 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12401 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12403 if (r
->reg_type
.bitfield
.zmmword
12404 || r
->reg_type
.bitfield
.class == RegMask
)
12407 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12409 if (r
->reg_type
.bitfield
.ymmword
)
12412 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12417 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12420 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12421 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12424 /* Upper 16 vector registers are only available with VREX in 64bit
12425 mode, and require EVEX encoding. */
12426 if (r
->reg_flags
& RegVRex
)
12428 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12429 || flag_code
!= CODE_64BIT
)
12432 if (i
.vec_encoding
== vex_encoding_default
)
12433 i
.vec_encoding
= vex_encoding_evex
;
12434 else if (i
.vec_encoding
!= vex_encoding_evex
)
12435 i
.vec_encoding
= vex_encoding_error
;
12438 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12439 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12440 && flag_code
!= CODE_64BIT
)
12443 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12450 /* REG_STRING starts *before* REGISTER_PREFIX. */
12452 static const reg_entry
*
12453 parse_real_register (char *reg_string
, char **end_op
)
12455 char *s
= reg_string
;
12457 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12458 const reg_entry
*r
;
12460 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12461 if (*s
== REGISTER_PREFIX
)
12464 if (is_space_char (*s
))
12467 p
= reg_name_given
;
12468 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12470 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12471 return (const reg_entry
*) NULL
;
12475 /* For naked regs, make sure that we are not dealing with an identifier.
12476 This prevents confusing an identifier like `eax_var' with register
12478 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12479 return (const reg_entry
*) NULL
;
12483 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12485 /* Handle floating point regs, allowing spaces in the (i) part. */
12486 if (r
== i386_regtab
/* %st is first entry of table */)
12488 if (!cpu_arch_flags
.bitfield
.cpu8087
12489 && !cpu_arch_flags
.bitfield
.cpu287
12490 && !cpu_arch_flags
.bitfield
.cpu387
12491 && !allow_pseudo_reg
)
12492 return (const reg_entry
*) NULL
;
12494 if (is_space_char (*s
))
12499 if (is_space_char (*s
))
12501 if (*s
>= '0' && *s
<= '7')
12503 int fpr
= *s
- '0';
12505 if (is_space_char (*s
))
12510 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12515 /* We have "%st(" then garbage. */
12516 return (const reg_entry
*) NULL
;
12520 return r
&& check_register (r
) ? r
: NULL
;
12523 /* REG_STRING starts *before* REGISTER_PREFIX. */
12525 static const reg_entry
*
12526 parse_register (char *reg_string
, char **end_op
)
12528 const reg_entry
*r
;
12530 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12531 r
= parse_real_register (reg_string
, end_op
);
12536 char *save
= input_line_pointer
;
12540 input_line_pointer
= reg_string
;
12541 c
= get_symbol_name (®_string
);
12542 symbolP
= symbol_find (reg_string
);
12543 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12545 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12547 know (e
->X_op
== O_register
);
12548 know (e
->X_add_number
>= 0
12549 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12550 r
= i386_regtab
+ e
->X_add_number
;
12551 if (!check_register (r
))
12553 as_bad (_("register '%s%s' cannot be used here"),
12554 register_prefix
, r
->reg_name
);
12557 *end_op
= input_line_pointer
;
12559 *input_line_pointer
= c
;
12560 input_line_pointer
= save
;
12566 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12568 const reg_entry
*r
;
12569 char *end
= input_line_pointer
;
12572 r
= parse_register (name
, &input_line_pointer
);
12573 if (r
&& end
<= input_line_pointer
)
12575 *nextcharP
= *input_line_pointer
;
12576 *input_line_pointer
= 0;
12579 e
->X_op
= O_register
;
12580 e
->X_add_number
= r
- i386_regtab
;
12583 e
->X_op
= O_illegal
;
12586 input_line_pointer
= end
;
12588 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12592 md_operand (expressionS
*e
)
12595 const reg_entry
*r
;
12597 switch (*input_line_pointer
)
12599 case REGISTER_PREFIX
:
12600 r
= parse_real_register (input_line_pointer
, &end
);
12603 e
->X_op
= O_register
;
12604 e
->X_add_number
= r
- i386_regtab
;
12605 input_line_pointer
= end
;
12610 gas_assert (intel_syntax
);
12611 end
= input_line_pointer
++;
12613 if (*input_line_pointer
== ']')
12615 ++input_line_pointer
;
12616 e
->X_op_symbol
= make_expr_symbol (e
);
12617 e
->X_add_symbol
= NULL
;
12618 e
->X_add_number
= 0;
12623 e
->X_op
= O_absent
;
12624 input_line_pointer
= end
;
12631 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12632 const char *md_shortopts
= "kVQ:sqnO::";
12634 const char *md_shortopts
= "qnO::";
12637 #define OPTION_32 (OPTION_MD_BASE + 0)
12638 #define OPTION_64 (OPTION_MD_BASE + 1)
12639 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12640 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12641 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12642 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12643 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12644 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12645 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12646 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12647 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12648 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12649 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12650 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12651 #define OPTION_X32 (OPTION_MD_BASE + 14)
12652 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12653 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12654 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12655 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12656 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12657 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12658 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12659 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12660 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12661 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12662 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12663 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12664 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12665 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12666 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12667 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12668 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12669 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12670 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12672 struct option md_longopts
[] =
12674 {"32", no_argument
, NULL
, OPTION_32
},
12675 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12676 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12677 {"64", no_argument
, NULL
, OPTION_64
},
12679 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12680 {"x32", no_argument
, NULL
, OPTION_X32
},
12681 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12682 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12684 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12685 {"march", required_argument
, NULL
, OPTION_MARCH
},
12686 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12687 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12688 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12689 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12690 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12691 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12692 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12693 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12694 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12695 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12696 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12697 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12698 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12699 # if defined (TE_PE) || defined (TE_PEP)
12700 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12702 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12703 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12704 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12705 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12706 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12707 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12708 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12709 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12710 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12711 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12712 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12713 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12714 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12715 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12716 {NULL
, no_argument
, NULL
, 0}
12718 size_t md_longopts_size
= sizeof (md_longopts
);
12721 md_parse_option (int c
, const char *arg
)
12724 char *arch
, *next
, *saved
, *type
;
12729 optimize_align_code
= 0;
12733 quiet_warnings
= 1;
12736 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12737 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12738 should be emitted or not. FIXME: Not implemented. */
12740 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12744 /* -V: SVR4 argument to print version ID. */
12746 print_version_id ();
12749 /* -k: Ignore for FreeBSD compatibility. */
12754 /* -s: On i386 Solaris, this tells the native assembler to use
12755 .stab instead of .stab.excl. We always use .stab anyhow. */
12758 case OPTION_MSHARED
:
12762 case OPTION_X86_USED_NOTE
:
12763 if (strcasecmp (arg
, "yes") == 0)
12765 else if (strcasecmp (arg
, "no") == 0)
12768 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12773 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12774 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12777 const char **list
, **l
;
12779 list
= bfd_target_list ();
12780 for (l
= list
; *l
!= NULL
; l
++)
12781 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12782 || strcmp (*l
, "coff-x86-64") == 0
12783 || strcmp (*l
, "pe-x86-64") == 0
12784 || strcmp (*l
, "pei-x86-64") == 0
12785 || strcmp (*l
, "mach-o-x86-64") == 0)
12787 default_arch
= "x86_64";
12791 as_fatal (_("no compiled in support for x86_64"));
12797 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12801 const char **list
, **l
;
12803 list
= bfd_target_list ();
12804 for (l
= list
; *l
!= NULL
; l
++)
12805 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12807 default_arch
= "x86_64:32";
12811 as_fatal (_("no compiled in support for 32bit x86_64"));
12815 as_fatal (_("32bit x86_64 is only supported for ELF"));
12820 default_arch
= "i386";
12823 case OPTION_DIVIDE
:
12824 #ifdef SVR4_COMMENT_CHARS
12829 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12831 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12835 i386_comment_chars
= n
;
12841 saved
= xstrdup (arg
);
12843 /* Allow -march=+nosse. */
12849 as_fatal (_("invalid -march= option: `%s'"), arg
);
12850 next
= strchr (arch
, '+');
12853 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12855 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12858 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12861 cpu_arch_name
= cpu_arch
[j
].name
;
12862 cpu_sub_arch_name
= NULL
;
12863 cpu_arch_flags
= cpu_arch
[j
].flags
;
12864 cpu_arch_isa
= cpu_arch
[j
].type
;
12865 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12866 if (!cpu_arch_tune_set
)
12868 cpu_arch_tune
= cpu_arch_isa
;
12869 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12873 else if (*cpu_arch
[j
].name
== '.'
12874 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12876 /* ISA extension. */
12877 i386_cpu_flags flags
;
12879 flags
= cpu_flags_or (cpu_arch_flags
,
12880 cpu_arch
[j
].flags
);
12882 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12884 if (cpu_sub_arch_name
)
12886 char *name
= cpu_sub_arch_name
;
12887 cpu_sub_arch_name
= concat (name
,
12889 (const char *) NULL
);
12893 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12894 cpu_arch_flags
= flags
;
12895 cpu_arch_isa_flags
= flags
;
12899 = cpu_flags_or (cpu_arch_isa_flags
,
12900 cpu_arch
[j
].flags
);
12905 if (j
>= ARRAY_SIZE (cpu_arch
))
12907 /* Disable an ISA extension. */
12908 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12909 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12911 i386_cpu_flags flags
;
12913 flags
= cpu_flags_and_not (cpu_arch_flags
,
12914 cpu_noarch
[j
].flags
);
12915 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12917 if (cpu_sub_arch_name
)
12919 char *name
= cpu_sub_arch_name
;
12920 cpu_sub_arch_name
= concat (arch
,
12921 (const char *) NULL
);
12925 cpu_sub_arch_name
= xstrdup (arch
);
12926 cpu_arch_flags
= flags
;
12927 cpu_arch_isa_flags
= flags
;
12932 if (j
>= ARRAY_SIZE (cpu_noarch
))
12933 j
= ARRAY_SIZE (cpu_arch
);
12936 if (j
>= ARRAY_SIZE (cpu_arch
))
12937 as_fatal (_("invalid -march= option: `%s'"), arg
);
12941 while (next
!= NULL
);
12947 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12948 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12950 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12952 cpu_arch_tune_set
= 1;
12953 cpu_arch_tune
= cpu_arch
[j
].type
;
12954 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12958 if (j
>= ARRAY_SIZE (cpu_arch
))
12959 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12962 case OPTION_MMNEMONIC
:
12963 if (strcasecmp (arg
, "att") == 0)
12964 intel_mnemonic
= 0;
12965 else if (strcasecmp (arg
, "intel") == 0)
12966 intel_mnemonic
= 1;
12968 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12971 case OPTION_MSYNTAX
:
12972 if (strcasecmp (arg
, "att") == 0)
12974 else if (strcasecmp (arg
, "intel") == 0)
12977 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12980 case OPTION_MINDEX_REG
:
12981 allow_index_reg
= 1;
12984 case OPTION_MNAKED_REG
:
12985 allow_naked_reg
= 1;
12988 case OPTION_MSSE2AVX
:
12992 case OPTION_MSSE_CHECK
:
12993 if (strcasecmp (arg
, "error") == 0)
12994 sse_check
= check_error
;
12995 else if (strcasecmp (arg
, "warning") == 0)
12996 sse_check
= check_warning
;
12997 else if (strcasecmp (arg
, "none") == 0)
12998 sse_check
= check_none
;
13000 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13003 case OPTION_MOPERAND_CHECK
:
13004 if (strcasecmp (arg
, "error") == 0)
13005 operand_check
= check_error
;
13006 else if (strcasecmp (arg
, "warning") == 0)
13007 operand_check
= check_warning
;
13008 else if (strcasecmp (arg
, "none") == 0)
13009 operand_check
= check_none
;
13011 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13014 case OPTION_MAVXSCALAR
:
13015 if (strcasecmp (arg
, "128") == 0)
13016 avxscalar
= vex128
;
13017 else if (strcasecmp (arg
, "256") == 0)
13018 avxscalar
= vex256
;
13020 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13023 case OPTION_MVEXWIG
:
13024 if (strcmp (arg
, "0") == 0)
13026 else if (strcmp (arg
, "1") == 0)
13029 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13032 case OPTION_MADD_BND_PREFIX
:
13033 add_bnd_prefix
= 1;
13036 case OPTION_MEVEXLIG
:
13037 if (strcmp (arg
, "128") == 0)
13038 evexlig
= evexl128
;
13039 else if (strcmp (arg
, "256") == 0)
13040 evexlig
= evexl256
;
13041 else if (strcmp (arg
, "512") == 0)
13042 evexlig
= evexl512
;
13044 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13047 case OPTION_MEVEXRCIG
:
13048 if (strcmp (arg
, "rne") == 0)
13050 else if (strcmp (arg
, "rd") == 0)
13052 else if (strcmp (arg
, "ru") == 0)
13054 else if (strcmp (arg
, "rz") == 0)
13057 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13060 case OPTION_MEVEXWIG
:
13061 if (strcmp (arg
, "0") == 0)
13063 else if (strcmp (arg
, "1") == 0)
13066 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13069 # if defined (TE_PE) || defined (TE_PEP)
13070 case OPTION_MBIG_OBJ
:
13075 case OPTION_MOMIT_LOCK_PREFIX
:
13076 if (strcasecmp (arg
, "yes") == 0)
13077 omit_lock_prefix
= 1;
13078 else if (strcasecmp (arg
, "no") == 0)
13079 omit_lock_prefix
= 0;
13081 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13084 case OPTION_MFENCE_AS_LOCK_ADD
:
13085 if (strcasecmp (arg
, "yes") == 0)
13087 else if (strcasecmp (arg
, "no") == 0)
13090 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13093 case OPTION_MLFENCE_AFTER_LOAD
:
13094 if (strcasecmp (arg
, "yes") == 0)
13095 lfence_after_load
= 1;
13096 else if (strcasecmp (arg
, "no") == 0)
13097 lfence_after_load
= 0;
13099 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13102 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13103 if (strcasecmp (arg
, "all") == 0)
13105 lfence_before_indirect_branch
= lfence_branch_all
;
13106 if (lfence_before_ret
== lfence_before_ret_none
)
13107 lfence_before_ret
= lfence_before_ret_shl
;
13109 else if (strcasecmp (arg
, "memory") == 0)
13110 lfence_before_indirect_branch
= lfence_branch_memory
;
13111 else if (strcasecmp (arg
, "register") == 0)
13112 lfence_before_indirect_branch
= lfence_branch_register
;
13113 else if (strcasecmp (arg
, "none") == 0)
13114 lfence_before_indirect_branch
= lfence_branch_none
;
13116 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13120 case OPTION_MLFENCE_BEFORE_RET
:
13121 if (strcasecmp (arg
, "or") == 0)
13122 lfence_before_ret
= lfence_before_ret_or
;
13123 else if (strcasecmp (arg
, "not") == 0)
13124 lfence_before_ret
= lfence_before_ret_not
;
13125 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13126 lfence_before_ret
= lfence_before_ret_shl
;
13127 else if (strcasecmp (arg
, "none") == 0)
13128 lfence_before_ret
= lfence_before_ret_none
;
13130 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13134 case OPTION_MRELAX_RELOCATIONS
:
13135 if (strcasecmp (arg
, "yes") == 0)
13136 generate_relax_relocations
= 1;
13137 else if (strcasecmp (arg
, "no") == 0)
13138 generate_relax_relocations
= 0;
13140 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13143 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13146 long int align
= strtoul (arg
, &end
, 0);
13151 align_branch_power
= 0;
13154 else if (align
>= 16)
13157 for (align_power
= 0;
13159 align
>>= 1, align_power
++)
13161 /* Limit alignment power to 31. */
13162 if (align
== 1 && align_power
< 32)
13164 align_branch_power
= align_power
;
13169 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13173 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13176 int align
= strtoul (arg
, &end
, 0);
13177 /* Some processors only support 5 prefixes. */
13178 if (*end
== '\0' && align
>= 0 && align
< 6)
13180 align_branch_prefix_size
= align
;
13183 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13188 case OPTION_MALIGN_BRANCH
:
13190 saved
= xstrdup (arg
);
13194 next
= strchr (type
, '+');
13197 if (strcasecmp (type
, "jcc") == 0)
13198 align_branch
|= align_branch_jcc_bit
;
13199 else if (strcasecmp (type
, "fused") == 0)
13200 align_branch
|= align_branch_fused_bit
;
13201 else if (strcasecmp (type
, "jmp") == 0)
13202 align_branch
|= align_branch_jmp_bit
;
13203 else if (strcasecmp (type
, "call") == 0)
13204 align_branch
|= align_branch_call_bit
;
13205 else if (strcasecmp (type
, "ret") == 0)
13206 align_branch
|= align_branch_ret_bit
;
13207 else if (strcasecmp (type
, "indirect") == 0)
13208 align_branch
|= align_branch_indirect_bit
;
13210 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13213 while (next
!= NULL
);
13217 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13218 align_branch_power
= 5;
13219 align_branch_prefix_size
= 5;
13220 align_branch
= (align_branch_jcc_bit
13221 | align_branch_fused_bit
13222 | align_branch_jmp_bit
);
13225 case OPTION_MAMD64
:
13229 case OPTION_MINTEL64
:
13237 /* Turn off -Os. */
13238 optimize_for_space
= 0;
13240 else if (*arg
== 's')
13242 optimize_for_space
= 1;
13243 /* Turn on all encoding optimizations. */
13244 optimize
= INT_MAX
;
13248 optimize
= atoi (arg
);
13249 /* Turn off -Os. */
13250 optimize_for_space
= 0;
13260 #define MESSAGE_TEMPLATE \
13264 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13265 int *left_p
, const char *name
, int len
)
13267 int size
= sizeof (MESSAGE_TEMPLATE
);
13268 int left
= *left_p
;
13270 /* Reserve 2 spaces for ", " or ",\0" */
13273 /* Check if there is any room. */
13281 p
= mempcpy (p
, name
, len
);
13285 /* Output the current message now and start a new one. */
13288 fprintf (stream
, "%s\n", message
);
13290 left
= size
- (start
- message
) - len
- 2;
13292 gas_assert (left
>= 0);
13294 p
= mempcpy (p
, name
, len
);
13302 show_arch (FILE *stream
, int ext
, int check
)
13304 static char message
[] = MESSAGE_TEMPLATE
;
13305 char *start
= message
+ 27;
13307 int size
= sizeof (MESSAGE_TEMPLATE
);
13314 left
= size
- (start
- message
);
13315 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13317 /* Should it be skipped? */
13318 if (cpu_arch
[j
].skip
)
13321 name
= cpu_arch
[j
].name
;
13322 len
= cpu_arch
[j
].len
;
13325 /* It is an extension. Skip if we aren't asked to show it. */
13336 /* It is an processor. Skip if we show only extension. */
13339 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13341 /* It is an impossible processor - skip. */
13345 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13348 /* Display disabled extensions. */
13350 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13352 name
= cpu_noarch
[j
].name
;
13353 len
= cpu_noarch
[j
].len
;
13354 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13359 fprintf (stream
, "%s\n", message
);
13363 md_show_usage (FILE *stream
)
13365 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13366 fprintf (stream
, _("\
13367 -Qy, -Qn ignored\n\
13368 -V print assembler version number\n\
13371 fprintf (stream
, _("\
13372 -n Do not optimize code alignment\n\
13373 -q quieten some warnings\n"));
13374 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13375 fprintf (stream
, _("\
13378 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13379 || defined (TE_PE) || defined (TE_PEP))
13380 fprintf (stream
, _("\
13381 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13383 #ifdef SVR4_COMMENT_CHARS
13384 fprintf (stream
, _("\
13385 --divide do not treat `/' as a comment character\n"));
13387 fprintf (stream
, _("\
13388 --divide ignored\n"));
13390 fprintf (stream
, _("\
13391 -march=CPU[,+EXTENSION...]\n\
13392 generate code for CPU and EXTENSION, CPU is one of:\n"));
13393 show_arch (stream
, 0, 1);
13394 fprintf (stream
, _("\
13395 EXTENSION is combination of:\n"));
13396 show_arch (stream
, 1, 0);
13397 fprintf (stream
, _("\
13398 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13399 show_arch (stream
, 0, 0);
13400 fprintf (stream
, _("\
13401 -msse2avx encode SSE instructions with VEX prefix\n"));
13402 fprintf (stream
, _("\
13403 -msse-check=[none|error|warning] (default: warning)\n\
13404 check SSE instructions\n"));
13405 fprintf (stream
, _("\
13406 -moperand-check=[none|error|warning] (default: warning)\n\
13407 check operand combinations for validity\n"));
13408 fprintf (stream
, _("\
13409 -mavxscalar=[128|256] (default: 128)\n\
13410 encode scalar AVX instructions with specific vector\n\
13412 fprintf (stream
, _("\
13413 -mvexwig=[0|1] (default: 0)\n\
13414 encode VEX instructions with specific VEX.W value\n\
13415 for VEX.W bit ignored instructions\n"));
13416 fprintf (stream
, _("\
13417 -mevexlig=[128|256|512] (default: 128)\n\
13418 encode scalar EVEX instructions with specific vector\n\
13420 fprintf (stream
, _("\
13421 -mevexwig=[0|1] (default: 0)\n\
13422 encode EVEX instructions with specific EVEX.W value\n\
13423 for EVEX.W bit ignored instructions\n"));
13424 fprintf (stream
, _("\
13425 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13426 encode EVEX instructions with specific EVEX.RC value\n\
13427 for SAE-only ignored instructions\n"));
13428 fprintf (stream
, _("\
13429 -mmnemonic=[att|intel] "));
13430 if (SYSV386_COMPAT
)
13431 fprintf (stream
, _("(default: att)\n"));
13433 fprintf (stream
, _("(default: intel)\n"));
13434 fprintf (stream
, _("\
13435 use AT&T/Intel mnemonic\n"));
13436 fprintf (stream
, _("\
13437 -msyntax=[att|intel] (default: att)\n\
13438 use AT&T/Intel syntax\n"));
13439 fprintf (stream
, _("\
13440 -mindex-reg support pseudo index registers\n"));
13441 fprintf (stream
, _("\
13442 -mnaked-reg don't require `%%' prefix for registers\n"));
13443 fprintf (stream
, _("\
13444 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13446 fprintf (stream
, _("\
13447 -mshared disable branch optimization for shared code\n"));
13448 fprintf (stream
, _("\
13449 -mx86-used-note=[no|yes] "));
13450 if (DEFAULT_X86_USED_NOTE
)
13451 fprintf (stream
, _("(default: yes)\n"));
13453 fprintf (stream
, _("(default: no)\n"));
13454 fprintf (stream
, _("\
13455 generate x86 used ISA and feature properties\n"));
13457 #if defined (TE_PE) || defined (TE_PEP)
13458 fprintf (stream
, _("\
13459 -mbig-obj generate big object files\n"));
13461 fprintf (stream
, _("\
13462 -momit-lock-prefix=[no|yes] (default: no)\n\
13463 strip all lock prefixes\n"));
13464 fprintf (stream
, _("\
13465 -mfence-as-lock-add=[no|yes] (default: no)\n\
13466 encode lfence, mfence and sfence as\n\
13467 lock addl $0x0, (%%{re}sp)\n"));
13468 fprintf (stream
, _("\
13469 -mrelax-relocations=[no|yes] "));
13470 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13471 fprintf (stream
, _("(default: yes)\n"));
13473 fprintf (stream
, _("(default: no)\n"));
13474 fprintf (stream
, _("\
13475 generate relax relocations\n"));
13476 fprintf (stream
, _("\
13477 -malign-branch-boundary=NUM (default: 0)\n\
13478 align branches within NUM byte boundary\n"));
13479 fprintf (stream
, _("\
13480 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13481 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13483 specify types of branches to align\n"));
13484 fprintf (stream
, _("\
13485 -malign-branch-prefix-size=NUM (default: 5)\n\
13486 align branches with NUM prefixes per instruction\n"));
13487 fprintf (stream
, _("\
13488 -mbranches-within-32B-boundaries\n\
13489 align branches within 32 byte boundary\n"));
13490 fprintf (stream
, _("\
13491 -mlfence-after-load=[no|yes] (default: no)\n\
13492 generate lfence after load\n"));
13493 fprintf (stream
, _("\
13494 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13495 generate lfence before indirect near branch\n"));
13496 fprintf (stream
, _("\
13497 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13498 generate lfence before ret\n"));
13499 fprintf (stream
, _("\
13500 -mamd64 accept only AMD64 ISA [default]\n"));
13501 fprintf (stream
, _("\
13502 -mintel64 accept only Intel64 ISA\n"));
13505 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13506 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13507 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13509 /* Pick the target format to use. */
13512 i386_target_format (void)
13514 if (!strncmp (default_arch
, "x86_64", 6))
13516 update_code_flag (CODE_64BIT
, 1);
13517 if (default_arch
[6] == '\0')
13518 x86_elf_abi
= X86_64_ABI
;
13520 x86_elf_abi
= X86_64_X32_ABI
;
13522 else if (!strcmp (default_arch
, "i386"))
13523 update_code_flag (CODE_32BIT
, 1);
13524 else if (!strcmp (default_arch
, "iamcu"))
13526 update_code_flag (CODE_32BIT
, 1);
13527 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13529 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13530 cpu_arch_name
= "iamcu";
13531 cpu_sub_arch_name
= NULL
;
13532 cpu_arch_flags
= iamcu_flags
;
13533 cpu_arch_isa
= PROCESSOR_IAMCU
;
13534 cpu_arch_isa_flags
= iamcu_flags
;
13535 if (!cpu_arch_tune_set
)
13537 cpu_arch_tune
= cpu_arch_isa
;
13538 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13541 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13542 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13546 as_fatal (_("unknown architecture"));
13548 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13549 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13550 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13551 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13553 switch (OUTPUT_FLAVOR
)
13555 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13556 case bfd_target_aout_flavour
:
13557 return AOUT_TARGET_FORMAT
;
13559 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13560 # if defined (TE_PE) || defined (TE_PEP)
13561 case bfd_target_coff_flavour
:
13562 if (flag_code
== CODE_64BIT
)
13563 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13565 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13566 # elif defined (TE_GO32)
13567 case bfd_target_coff_flavour
:
13568 return "coff-go32";
13570 case bfd_target_coff_flavour
:
13571 return "coff-i386";
13574 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13575 case bfd_target_elf_flavour
:
13577 const char *format
;
13579 switch (x86_elf_abi
)
13582 format
= ELF_TARGET_FORMAT
;
13584 tls_get_addr
= "___tls_get_addr";
13588 use_rela_relocations
= 1;
13591 tls_get_addr
= "__tls_get_addr";
13593 format
= ELF_TARGET_FORMAT64
;
13595 case X86_64_X32_ABI
:
13596 use_rela_relocations
= 1;
13599 tls_get_addr
= "__tls_get_addr";
13601 disallow_64bit_reloc
= 1;
13602 format
= ELF_TARGET_FORMAT32
;
13605 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13607 if (x86_elf_abi
!= X86_64_ABI
)
13608 as_fatal (_("Intel L1OM is 64bit only"));
13609 return ELF_TARGET_L1OM_FORMAT
;
13611 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13613 if (x86_elf_abi
!= X86_64_ABI
)
13614 as_fatal (_("Intel K1OM is 64bit only"));
13615 return ELF_TARGET_K1OM_FORMAT
;
13617 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13619 if (x86_elf_abi
!= I386_ABI
)
13620 as_fatal (_("Intel MCU is 32bit only"));
13621 return ELF_TARGET_IAMCU_FORMAT
;
13627 #if defined (OBJ_MACH_O)
13628 case bfd_target_mach_o_flavour
:
13629 if (flag_code
== CODE_64BIT
)
13631 use_rela_relocations
= 1;
13633 return "mach-o-x86-64";
13636 return "mach-o-i386";
13644 #endif /* OBJ_MAYBE_ more than one */
13647 md_undefined_symbol (char *name
)
13649 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13650 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13651 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13652 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13656 if (symbol_find (name
))
13657 as_bad (_("GOT already in symbol table"));
13658 GOT_symbol
= symbol_new (name
, undefined_section
,
13659 (valueT
) 0, &zero_address_frag
);
13666 /* Round up a section size to the appropriate boundary. */
13669 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13671 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13672 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13674 /* For a.out, force the section size to be aligned. If we don't do
13675 this, BFD will align it for us, but it will not write out the
13676 final bytes of the section. This may be a bug in BFD, but it is
13677 easier to fix it here since that is how the other a.out targets
13681 align
= bfd_section_alignment (segment
);
13682 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13689 /* On the i386, PC-relative offsets are relative to the start of the
13690 next instruction. That is, the address of the offset, plus its
13691 size, since the offset is always the last part of the insn. */
13694 md_pcrel_from (fixS
*fixP
)
13696 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13702 s_bss (int ignore ATTRIBUTE_UNUSED
)
13706 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13708 obj_elf_section_change_hook ();
13710 temp
= get_absolute_expression ();
13711 subseg_set (bss_section
, (subsegT
) temp
);
13712 demand_empty_rest_of_line ();
13717 /* Remember constant directive. */
13720 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13722 if (last_insn
.kind
!= last_insn_directive
13723 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13725 last_insn
.seg
= now_seg
;
13726 last_insn
.kind
= last_insn_directive
;
13727 last_insn
.name
= "constant directive";
13728 last_insn
.file
= as_where (&last_insn
.line
);
13729 if (lfence_before_ret
!= lfence_before_ret_none
)
13731 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13732 as_warn (_("constant directive skips -mlfence-before-ret "
13733 "and -mlfence-before-indirect-branch"));
13735 as_warn (_("constant directive skips -mlfence-before-ret"));
13737 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13738 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13743 i386_validate_fix (fixS
*fixp
)
13745 if (fixp
->fx_subsy
)
13747 if (fixp
->fx_subsy
== GOT_symbol
)
13749 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13753 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13754 if (fixp
->fx_tcbit2
)
13755 fixp
->fx_r_type
= (fixp
->fx_tcbit
13756 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13757 : BFD_RELOC_X86_64_GOTPCRELX
);
13760 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13765 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13767 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13769 fixp
->fx_subsy
= 0;
13772 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13773 else if (!object_64bit
)
13775 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13776 && fixp
->fx_tcbit2
)
13777 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13783 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13786 bfd_reloc_code_real_type code
;
13788 switch (fixp
->fx_r_type
)
13790 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13791 case BFD_RELOC_SIZE32
:
13792 case BFD_RELOC_SIZE64
:
13793 if (S_IS_DEFINED (fixp
->fx_addsy
)
13794 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13796 /* Resolve size relocation against local symbol to size of
13797 the symbol plus addend. */
13798 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13799 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13800 && !fits_in_unsigned_long (value
))
13801 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13802 _("symbol size computation overflow"));
13803 fixp
->fx_addsy
= NULL
;
13804 fixp
->fx_subsy
= NULL
;
13805 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13809 /* Fall through. */
13811 case BFD_RELOC_X86_64_PLT32
:
13812 case BFD_RELOC_X86_64_GOT32
:
13813 case BFD_RELOC_X86_64_GOTPCREL
:
13814 case BFD_RELOC_X86_64_GOTPCRELX
:
13815 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13816 case BFD_RELOC_386_PLT32
:
13817 case BFD_RELOC_386_GOT32
:
13818 case BFD_RELOC_386_GOT32X
:
13819 case BFD_RELOC_386_GOTOFF
:
13820 case BFD_RELOC_386_GOTPC
:
13821 case BFD_RELOC_386_TLS_GD
:
13822 case BFD_RELOC_386_TLS_LDM
:
13823 case BFD_RELOC_386_TLS_LDO_32
:
13824 case BFD_RELOC_386_TLS_IE_32
:
13825 case BFD_RELOC_386_TLS_IE
:
13826 case BFD_RELOC_386_TLS_GOTIE
:
13827 case BFD_RELOC_386_TLS_LE_32
:
13828 case BFD_RELOC_386_TLS_LE
:
13829 case BFD_RELOC_386_TLS_GOTDESC
:
13830 case BFD_RELOC_386_TLS_DESC_CALL
:
13831 case BFD_RELOC_X86_64_TLSGD
:
13832 case BFD_RELOC_X86_64_TLSLD
:
13833 case BFD_RELOC_X86_64_DTPOFF32
:
13834 case BFD_RELOC_X86_64_DTPOFF64
:
13835 case BFD_RELOC_X86_64_GOTTPOFF
:
13836 case BFD_RELOC_X86_64_TPOFF32
:
13837 case BFD_RELOC_X86_64_TPOFF64
:
13838 case BFD_RELOC_X86_64_GOTOFF64
:
13839 case BFD_RELOC_X86_64_GOTPC32
:
13840 case BFD_RELOC_X86_64_GOT64
:
13841 case BFD_RELOC_X86_64_GOTPCREL64
:
13842 case BFD_RELOC_X86_64_GOTPC64
:
13843 case BFD_RELOC_X86_64_GOTPLT64
:
13844 case BFD_RELOC_X86_64_PLTOFF64
:
13845 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13846 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13847 case BFD_RELOC_RVA
:
13848 case BFD_RELOC_VTABLE_ENTRY
:
13849 case BFD_RELOC_VTABLE_INHERIT
:
13851 case BFD_RELOC_32_SECREL
:
13853 code
= fixp
->fx_r_type
;
13855 case BFD_RELOC_X86_64_32S
:
13856 if (!fixp
->fx_pcrel
)
13858 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13859 code
= fixp
->fx_r_type
;
13862 /* Fall through. */
13864 if (fixp
->fx_pcrel
)
13866 switch (fixp
->fx_size
)
13869 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13870 _("can not do %d byte pc-relative relocation"),
13872 code
= BFD_RELOC_32_PCREL
;
13874 case 1: code
= BFD_RELOC_8_PCREL
; break;
13875 case 2: code
= BFD_RELOC_16_PCREL
; break;
13876 case 4: code
= BFD_RELOC_32_PCREL
; break;
13878 case 8: code
= BFD_RELOC_64_PCREL
; break;
13884 switch (fixp
->fx_size
)
13887 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13888 _("can not do %d byte relocation"),
13890 code
= BFD_RELOC_32
;
13892 case 1: code
= BFD_RELOC_8
; break;
13893 case 2: code
= BFD_RELOC_16
; break;
13894 case 4: code
= BFD_RELOC_32
; break;
13896 case 8: code
= BFD_RELOC_64
; break;
13903 if ((code
== BFD_RELOC_32
13904 || code
== BFD_RELOC_32_PCREL
13905 || code
== BFD_RELOC_X86_64_32S
)
13907 && fixp
->fx_addsy
== GOT_symbol
)
13910 code
= BFD_RELOC_386_GOTPC
;
13912 code
= BFD_RELOC_X86_64_GOTPC32
;
13914 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13916 && fixp
->fx_addsy
== GOT_symbol
)
13918 code
= BFD_RELOC_X86_64_GOTPC64
;
13921 rel
= XNEW (arelent
);
13922 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13923 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13925 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13927 if (!use_rela_relocations
)
13929 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13930 vtable entry to be used in the relocation's section offset. */
13931 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13932 rel
->address
= fixp
->fx_offset
;
13933 #if defined (OBJ_COFF) && defined (TE_PE)
13934 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13935 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13940 /* Use the rela in 64bit mode. */
13943 if (disallow_64bit_reloc
)
13946 case BFD_RELOC_X86_64_DTPOFF64
:
13947 case BFD_RELOC_X86_64_TPOFF64
:
13948 case BFD_RELOC_64_PCREL
:
13949 case BFD_RELOC_X86_64_GOTOFF64
:
13950 case BFD_RELOC_X86_64_GOT64
:
13951 case BFD_RELOC_X86_64_GOTPCREL64
:
13952 case BFD_RELOC_X86_64_GOTPC64
:
13953 case BFD_RELOC_X86_64_GOTPLT64
:
13954 case BFD_RELOC_X86_64_PLTOFF64
:
13955 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13956 _("cannot represent relocation type %s in x32 mode"),
13957 bfd_get_reloc_code_name (code
));
13963 if (!fixp
->fx_pcrel
)
13964 rel
->addend
= fixp
->fx_offset
;
13968 case BFD_RELOC_X86_64_PLT32
:
13969 case BFD_RELOC_X86_64_GOT32
:
13970 case BFD_RELOC_X86_64_GOTPCREL
:
13971 case BFD_RELOC_X86_64_GOTPCRELX
:
13972 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13973 case BFD_RELOC_X86_64_TLSGD
:
13974 case BFD_RELOC_X86_64_TLSLD
:
13975 case BFD_RELOC_X86_64_GOTTPOFF
:
13976 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13977 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13978 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13981 rel
->addend
= (section
->vma
13983 + fixp
->fx_addnumber
13984 + md_pcrel_from (fixp
));
13989 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13990 if (rel
->howto
== NULL
)
13992 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13993 _("cannot represent relocation type %s"),
13994 bfd_get_reloc_code_name (code
));
13995 /* Set howto to a garbage value so that we can keep going. */
13996 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13997 gas_assert (rel
->howto
!= NULL
);
14003 #include "tc-i386-intel.c"
14006 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14008 int saved_naked_reg
;
14009 char saved_register_dot
;
14011 saved_naked_reg
= allow_naked_reg
;
14012 allow_naked_reg
= 1;
14013 saved_register_dot
= register_chars
['.'];
14014 register_chars
['.'] = '.';
14015 allow_pseudo_reg
= 1;
14016 expression_and_evaluate (exp
);
14017 allow_pseudo_reg
= 0;
14018 register_chars
['.'] = saved_register_dot
;
14019 allow_naked_reg
= saved_naked_reg
;
14021 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14023 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14025 exp
->X_op
= O_constant
;
14026 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14027 .dw2_regnum
[flag_code
>> 1];
14030 exp
->X_op
= O_illegal
;
14035 tc_x86_frame_initial_instructions (void)
14037 static unsigned int sp_regno
[2];
14039 if (!sp_regno
[flag_code
>> 1])
14041 char *saved_input
= input_line_pointer
;
14042 char sp
[][4] = {"esp", "rsp"};
14045 input_line_pointer
= sp
[flag_code
>> 1];
14046 tc_x86_parse_to_dw2regnum (&exp
);
14047 gas_assert (exp
.X_op
== O_constant
);
14048 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14049 input_line_pointer
= saved_input
;
14052 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14053 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14057 x86_dwarf2_addr_size (void)
14059 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14060 if (x86_elf_abi
== X86_64_X32_ABI
)
14063 return bfd_arch_bits_per_address (stdoutput
) / 8;
14067 i386_elf_section_type (const char *str
, size_t len
)
14069 if (flag_code
== CODE_64BIT
14070 && len
== sizeof ("unwind") - 1
14071 && strncmp (str
, "unwind", 6) == 0)
14072 return SHT_X86_64_UNWIND
;
14079 i386_solaris_fix_up_eh_frame (segT sec
)
14081 if (flag_code
== CODE_64BIT
)
14082 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14088 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14092 exp
.X_op
= O_secrel
;
14093 exp
.X_add_symbol
= symbol
;
14094 exp
.X_add_number
= 0;
14095 emit_expr (&exp
, size
);
14099 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14100 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14103 x86_64_section_letter (int letter
, const char **ptr_msg
)
14105 if (flag_code
== CODE_64BIT
)
14108 return SHF_X86_64_LARGE
;
14110 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14113 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14118 x86_64_section_word (char *str
, size_t len
)
14120 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14121 return SHF_X86_64_LARGE
;
14127 handle_large_common (int small ATTRIBUTE_UNUSED
)
14129 if (flag_code
!= CODE_64BIT
)
14131 s_comm_internal (0, elf_common_parse
);
14132 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14136 static segT lbss_section
;
14137 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14138 asection
*saved_bss_section
= bss_section
;
14140 if (lbss_section
== NULL
)
14142 flagword applicable
;
14143 segT seg
= now_seg
;
14144 subsegT subseg
= now_subseg
;
14146 /* The .lbss section is for local .largecomm symbols. */
14147 lbss_section
= subseg_new (".lbss", 0);
14148 applicable
= bfd_applicable_section_flags (stdoutput
);
14149 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14150 seg_info (lbss_section
)->bss
= 1;
14152 subseg_set (seg
, subseg
);
14155 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14156 bss_section
= lbss_section
;
14158 s_comm_internal (0, elf_common_parse
);
14160 elf_com_section_ptr
= saved_com_section_ptr
;
14161 bss_section
= saved_bss_section
;
14164 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */