1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars
= "|#";
47 const char *m68k_comment_chars
= "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars
[] = "#*";
59 const char line_separator_chars
[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS
[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 const int md_reloc_size
= 8; /* Size of relocation record. */
75 /* Are we trying to generate PIC code? If so, absolute references
76 ought to be made into linkage table references or pc-relative
77 references. Not implemented. For ELF there are other means
78 to denote pic relocations. */
81 static int flag_short_refs
; /* -l option. */
82 static int flag_long_jumps
; /* -S option. */
83 static int flag_keep_pcrel
; /* --pcrel option. */
85 #ifdef REGISTER_PREFIX_OPTIONAL
86 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
88 int flag_reg_prefix_optional
;
91 /* Whether --register-prefix-optional was used on the command line. */
92 static int reg_prefix_optional_seen
;
94 /* The floating point coprocessor to use by default. */
95 static enum m68k_register m68k_float_copnum
= COP1
;
97 /* If this is non-zero, then references to number(%pc) will be taken
98 to refer to number, rather than to %pc + number. */
99 static int m68k_abspcadd
;
101 /* If this is non-zero, then the quick forms of the move, add, and sub
102 instructions are used when possible. */
103 static int m68k_quick
= 1;
105 /* If this is non-zero, then if the size is not specified for a base
106 or outer displacement, the assembler assumes that the size should
108 static int m68k_rel32
= 1;
110 /* This is non-zero if m68k_rel32 was set from the command line. */
111 static int m68k_rel32_from_cmdline
;
113 /* The default width to use for an index register when using a base
115 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
117 /* We want to warn if any text labels are misaligned. In order to get
118 the right line number, we need to record the line number for each
122 struct label_line
*next
;
129 /* The list of labels. */
131 static struct label_line
*labels
;
133 /* The current label. */
135 static struct label_line
*current_label
;
137 /* Pointer to list holding the opcodes sorted by name. */
138 static struct m68k_opcode
const ** m68k_sorted_opcodes
;
140 /* Its an arbitrary name: This means I don't approve of it.
142 static struct obstack robyn
;
146 const char *m_operands
;
147 unsigned long m_opcode
;
151 struct m68k_incant
*m_next
;
154 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
155 #define gettwo(x) (((x)->m_opcode)&0xffff)
157 static const enum m68k_register m68000_control_regs
[] = { 0 };
158 static const enum m68k_register m68010_control_regs
[] = {
162 static const enum m68k_register m68020_control_regs
[] = {
163 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
166 static const enum m68k_register m68040_control_regs
[] = {
167 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
168 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
171 static const enum m68k_register m68060_control_regs
[] = {
172 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
173 USP
, VBR
, URP
, SRP
, PCR
,
176 static const enum m68k_register mcf_control_regs
[] = {
177 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
178 RAMBAR0
, RAMBAR1
, MBAR
,
181 static const enum m68k_register mcf528x_control_regs
[] = {
182 CACR
, ACR0
, ACR1
, VBR
, FLASHBAR
, RAMBAR
,
185 static const enum m68k_register mcfv4e_control_regs
[] = {
186 CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
, VBR
, PC
, ROMBAR
,
187 ROMBAR1
, RAMBAR0
, RAMBAR1
, MPCR
, EDRAMBAR
, SECMBAR
, MBAR
, MBAR0
, MBAR1
,
188 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
189 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
192 #define cpu32_control_regs m68010_control_regs
194 static const enum m68k_register
*control_regs
;
196 /* Internal form of a 68020 instruction. */
200 const char *args
; /* List of opcode info. */
203 int numo
; /* Number of shorts in opcode. */
206 struct m68k_op operands
[6];
208 int nexp
; /* Number of exprs in use. */
209 struct m68k_exp exprs
[4];
211 int nfrag
; /* Number of frags we have to produce. */
214 int fragoff
; /* Where in the current opcode the frag ends. */
221 int nrel
; /* Num of reloc strucs in use. */
228 /* In a pc relative address the difference between the address
229 of the offset and the address that the offset is relative
230 to. This depends on the addressing mode. Basically this
231 is the value to put in the offset field to address the
232 first byte of the offset, without regarding the special
233 significance of some values (in the branch instruction, for
237 /* Whether this expression needs special pic relocation, and if
239 enum pic_relocation pic_reloc
;
242 reloc
[5]; /* Five is enough??? */
245 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
246 #define float_of_arch(x) ((x) & mfloat)
247 #define mmu_of_arch(x) ((x) & mmmu)
248 #define arch_coldfire_p(x) ((x) & mcfisa_a)
249 #define arch_coldfire_fpu(x) ((x) & cfloat)
251 /* Macros for determining if cpu supports a specific addressing mode. */
252 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
254 static struct m68k_it the_ins
; /* The instruction being assembled. */
256 #define op(ex) ((ex)->exp.X_op)
257 #define adds(ex) ((ex)->exp.X_add_symbol)
258 #define subs(ex) ((ex)->exp.X_op_symbol)
259 #define offs(ex) ((ex)->exp.X_add_number)
261 /* Macros for adding things to the m68k_it struct. */
262 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
264 /* Like addword, but goes BEFORE general operands. */
267 insop (int w
, const struct m68k_incant
*opcode
)
270 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
271 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
272 for (z
= 0; z
< the_ins
.nrel
; z
++)
273 the_ins
.reloc
[z
].n
+= 2;
274 for (z
= 0; z
< the_ins
.nfrag
; z
++)
275 the_ins
.fragb
[z
].fragoff
++;
276 the_ins
.opcode
[opcode
->m_codenum
] = w
;
280 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
283 add_fix (int width
, struct m68k_exp
*exp
, int pc_rel
, int pc_fix
)
285 the_ins
.reloc
[the_ins
.nrel
].n
= (width
== 'B' || width
== '3'
286 ? the_ins
.numo
* 2 - 1
288 ? the_ins
.numo
* 2 + 1
289 : the_ins
.numo
* 2));
290 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
291 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
292 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
294 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
296 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
299 /* Cause an extra frag to be generated here, inserting up to 10 bytes
300 (that value is chosen in the frag_var call in md_assemble). TYPE
301 is the subtype of the frag to be generated; its primary type is
302 rs_machine_dependent.
304 The TYPE parameter is also used by md_convert_frag_1 and
305 md_estimate_size_before_relax. The appropriate type of fixup will
306 be emitted by md_convert_frag_1.
308 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
310 add_frag (symbolS
*add
, offsetT off
, int type
)
312 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
313 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
314 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
315 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
319 (op (ex) != O_constant && op (ex) != O_big)
321 static char *crack_operand (char *str
, struct m68k_op
*opP
);
322 static int get_num (struct m68k_exp
*exp
, int ok
);
323 static int reverse_16_bits (int in
);
324 static int reverse_8_bits (int in
);
325 static void install_gen_operand (int mode
, int val
);
326 static void install_operand (int mode
, int val
);
327 static void s_bss (int);
328 static void s_data1 (int);
329 static void s_data2 (int);
330 static void s_even (int);
331 static void s_proc (int);
332 static void s_chip (int);
333 static void s_fopt (int);
334 static void s_opt (int);
335 static void s_reg (int);
336 static void s_restore (int);
337 static void s_save (int);
338 static void s_mri_if (int);
339 static void s_mri_else (int);
340 static void s_mri_endi (int);
341 static void s_mri_break (int);
342 static void s_mri_next (int);
343 static void s_mri_for (int);
344 static void s_mri_endf (int);
345 static void s_mri_repeat (int);
346 static void s_mri_until (int);
347 static void s_mri_while (int);
348 static void s_mri_endw (int);
350 static int current_architecture
;
351 static int current_chip
;
361 static const struct m68k_cpu archs
[] =
363 { m68000
, m68000
, "68000", 0 },
364 { m68010
, m68010
, "68010", 0 },
365 { m68020
, m68020
, "68020", 0 },
366 { m68030
, m68030
, "68030", 0 },
367 { m68040
, m68040
, "68040", 0 },
368 { m68060
, m68060
, "68060", 0 },
369 { cpu32
, cpu32
, "cpu32", 0 },
370 { m68881
, m68881
, "68881", 0 },
371 { m68851
, m68851
, "68851", 0 },
372 { mcfisa_a
, mcf5200
, "5200", 0 },
373 { mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5206e
, "5206e", 0 },
374 { mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf521x
, "521x", 0 },
375 { mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5249
, "5249", 0 },
376 { mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf528x
, "528x", 0 },
377 { mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5307
, "5307", 0 },
378 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
, mcf5407
, "5407", 0 },
379 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "547x", 0 },
380 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5480
, "548x", 0 },
381 /* Aliases (effectively, so far as gas is concerned) for the above
383 { m68020
, m68020
, "68k", 1 },
384 { m68000
, m68000
, "68008", 1 },
385 { m68000
, m68000
, "68302", 1 },
386 { m68000
, m68000
, "68306", 1 },
387 { m68000
, m68000
, "68307", 1 },
388 { m68000
, m68000
, "68322", 1 },
389 { m68000
, m68000
, "68356", 1 },
390 { m68000
, m68000
, "68ec000", 1 },
391 { m68000
, m68000
, "68hc000", 1 },
392 { m68000
, m68000
, "68hc001", 1 },
393 { m68020
, m68020
, "68ec020", 1 },
394 { m68030
, m68030
, "68ec030", 1 },
395 { m68040
, m68040
, "68ec040", 1 },
396 { m68060
, m68060
, "68ec060", 1 },
397 { cpu32
, cpu32
, "68330", 1 },
398 { cpu32
, cpu32
, "68331", 1 },
399 { cpu32
, cpu32
, "68332", 1 },
400 { cpu32
, cpu32
, "68333", 1 },
401 { cpu32
, cpu32
, "68334", 1 },
402 { cpu32
, cpu32
, "68336", 1 },
403 { cpu32
, cpu32
, "68340", 1 },
404 { cpu32
, cpu32
, "68341", 1 },
405 { cpu32
, cpu32
, "68349", 1 },
406 { cpu32
, cpu32
, "68360", 1 },
407 { m68881
, m68881
, "68882", 1 },
408 { mcfisa_a
, mcf5200
, "5202", 1 },
409 { mcfisa_a
, mcf5200
, "5204", 1 },
410 { mcfisa_a
, mcf5200
, "5206", 1 },
411 { mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfemac
, mcf521x
, "5214", 1 },
412 { mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfemac
, mcf521x
, "5216", 1 },
413 { mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
, mcf528x
, "5280", 1 },
414 { mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
, mcf528x
, "5281", 1 },
415 { mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
, mcf528x
, "5282", 1 },
416 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
, mcf5407
, "cfv4", 1 },
417 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5470", 1 },
418 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5471", 1 },
419 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5472", 1 },
420 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5473", 1 },
421 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5474", 1 },
422 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5475", 1 },
423 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5480", 1 },
424 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5481", 1 },
425 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5482", 1 },
426 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5483", 1 },
427 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5484", 1 },
428 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5485", 1 },
429 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "cfv4e", 1 },
432 static const int n_archs
= sizeof (archs
) / sizeof (archs
[0]);
434 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
435 architecture and we have a lot of relaxation modes. */
437 /* Macros used in the relaxation code. */
438 #define TAB(x,y) (((x) << 2) + (y))
439 #define TABTYPE(x) ((x) >> 2)
441 /* Relaxation states. */
447 /* Here are all the relaxation modes we support. First we can relax ordinary
448 branches. On 68020 and higher and on CPU32 all branch instructions take
449 three forms, so on these CPUs all branches always remain as such. When we
450 have to expand to the LONG form on a 68000, though, we substitute an
451 absolute jump instead. This is a direct replacement for unconditional
452 branches and a branch over a jump for conditional branches. However, if the
453 user requires PIC and disables this with --pcrel, we can only relax between
454 BYTE and SHORT forms, punting if that isn't enough. This gives us four
455 different relaxation modes for branches: */
457 #define BRANCHBWL 0 /* Branch byte, word, or long. */
458 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
459 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
460 #define BRANCHBW 3 /* Branch byte or word. */
462 /* We also relax coprocessor branches and DBcc's. All CPUs that support
463 coprocessor branches support them in word and long forms, so we have only
464 one relaxation mode for them. DBcc's are word only on all CPUs. We can
465 relax them to the LONG form with a branch-around sequence. This sequence
466 can use a long branch (if available) or an absolute jump (if acceptable).
467 This gives us two relaxation modes. If long branches are not available and
468 absolute jumps are not acceptable, we don't relax DBcc's. */
470 #define FBRANCH 4 /* Coprocessor branch. */
471 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
472 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
474 /* That's all for instruction relaxation. However, we also relax PC-relative
475 operands. Specifically, we have three operand relaxation modes. On the
476 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
477 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
478 two. Also PC+displacement+index operands in their simple form (with a non-
479 suppressed index without memory indirection) are supported on all CPUs, but
480 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
481 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
482 form of the PC+displacement+index operand. Finally, some absolute operands
483 can be relaxed down to 16-bit PC-relative. */
485 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
486 #define PCINDEX 8 /* PC + displacement + index. */
487 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
489 /* Note that calls to frag_var need to specify the maximum expansion
490 needed; this is currently 10 bytes for DBCC. */
493 How far Forward this mode will reach:
494 How far Backward this mode will reach:
495 How many bytes this mode will add to the size of the frag
496 Which mode to go to if the offset won't fit in this one
498 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
499 relax_typeS md_relax_table
[] =
501 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
502 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
506 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
507 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
511 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
512 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
516 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
521 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
522 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
526 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
527 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
531 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
532 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
536 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
537 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
541 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
542 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
546 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
547 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
552 /* These are the machine dependent pseudo-ops. These are included so
553 the assembler can work on the output from the SUN C compiler, which
556 /* This table describes all the machine specific pseudo-ops the assembler
557 has to support. The fields are:
558 pseudo-op name without dot
559 function to call to execute this pseudo-op
560 Integer arg to pass to the function. */
561 const pseudo_typeS md_pseudo_table
[] =
563 {"data1", s_data1
, 0},
564 {"data2", s_data2
, 0},
567 {"skip", s_space
, 0},
569 #if defined (TE_SUN3) || defined (OBJ_ELF)
570 {"align", s_align_bytes
, 0},
573 {"swbeg", s_ignore
, 0},
575 {"extend", float_cons
, 'x'},
576 {"ldouble", float_cons
, 'x'},
578 /* The following pseudo-ops are supported for MRI compatibility. */
580 {"comline", s_space
, 1},
582 {"mask2", s_ignore
, 0},
585 {"restore", s_restore
, 0},
589 {"if.b", s_mri_if
, 'b'},
590 {"if.w", s_mri_if
, 'w'},
591 {"if.l", s_mri_if
, 'l'},
592 {"else", s_mri_else
, 0},
593 {"else.s", s_mri_else
, 's'},
594 {"else.l", s_mri_else
, 'l'},
595 {"endi", s_mri_endi
, 0},
596 {"break", s_mri_break
, 0},
597 {"break.s", s_mri_break
, 's'},
598 {"break.l", s_mri_break
, 'l'},
599 {"next", s_mri_next
, 0},
600 {"next.s", s_mri_next
, 's'},
601 {"next.l", s_mri_next
, 'l'},
602 {"for", s_mri_for
, 0},
603 {"for.b", s_mri_for
, 'b'},
604 {"for.w", s_mri_for
, 'w'},
605 {"for.l", s_mri_for
, 'l'},
606 {"endf", s_mri_endf
, 0},
607 {"repeat", s_mri_repeat
, 0},
608 {"until", s_mri_until
, 0},
609 {"until.b", s_mri_until
, 'b'},
610 {"until.w", s_mri_until
, 'w'},
611 {"until.l", s_mri_until
, 'l'},
612 {"while", s_mri_while
, 0},
613 {"while.b", s_mri_while
, 'b'},
614 {"while.w", s_mri_while
, 'w'},
615 {"while.l", s_mri_while
, 'l'},
616 {"endw", s_mri_endw
, 0},
621 /* The mote pseudo ops are put into the opcode table, since they
622 don't start with a . they look like opcodes to gas. */
624 const pseudo_typeS mote_pseudo_table
[] =
637 {"xdef", s_globl
, 0},
639 {"align", s_align_bytes
, 0},
641 {"align", s_align_ptwo
, 0},
644 {"sect", obj_coff_section
, 0},
645 {"section", obj_coff_section
, 0},
650 #define issbyte(x) ((x) >= -128 && (x) <= 127)
651 #define isubyte(x) ((x) >= 0 && (x) <= 255)
652 #define issword(x) ((x) >= -32768 && (x) <= 32767)
653 #define isuword(x) ((x) >= 0 && (x) <= 65535)
655 #define isbyte(x) ((x) >= -255 && (x) <= 255)
656 #define isword(x) ((x) >= -65536 && (x) <= 65535)
657 #define islong(x) (1)
659 static char notend_table
[256];
660 static char alt_notend_table
[256];
662 (! (notend_table[(unsigned char) *s] \
664 && alt_notend_table[(unsigned char) s[1]])))
666 /* Return a human readable string holding the list of chips that are
667 valid for a particular architecture, suppressing aliases (unless
668 there is only one of them). */
671 find_cf_chip (int architecture
)
673 static char buf
[1024];
674 int i
, j
, n_chips
, n_alias
;
678 cp
= buf
+ strlen (buf
);
680 for (i
= 0, n_chips
= 0, n_alias
= 0; i
< n_archs
; ++i
)
681 if (archs
[i
].arch
& architecture
)
689 as_fatal (_("no matching ColdFire architectures found"));
694 for (i
= 0, j
= 0; i
< n_archs
&& j
< n_chips
; ++i
)
695 if (archs
[i
].arch
& architecture
)
699 if ((j
== n_chips
- 1 && !(n_alias
> 1)) || ! n_alias
)
703 strncpy (cp
, _(" or "), (sizeof (buf
) - (cp
- buf
)));
708 strncpy (cp
, _(", or "), (sizeof (buf
) - (cp
- buf
)));
714 strncpy (cp
, ", ", (sizeof (buf
) - (cp
- buf
)));
718 strncpy (cp
, archs
[i
].name
, (sizeof (buf
) - (cp
- buf
)));
725 strncpy (cp
, _(", or aliases"), (sizeof (buf
) - (cp
- buf
)));
729 strncpy (cp
, ")", (sizeof (buf
) - (cp
- buf
)));
734 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
736 #ifdef NO_PCREL_RELOCS
739 make_pcrel_absolute (fixS
*fixP
, long *add_number
)
741 register unsigned char *opcode
= fixP
->fx_frag
->fr_opcode
;
743 /* Rewrite the PC relative instructions to absolute address ones.
744 these are rumored to be faster, and the apollo linker refuses
745 to deal with the PC relative relocations. */
746 if (opcode
[0] == 0x60 && opcode
[1] == 0xff) /* BRA -> JMP. */
749 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
753 else if (opcode
[0] == 0x61 && opcode
[1] == 0xff) /* BSR -> JSR. */
756 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
761 as_fatal (_("Unknown PC relative instruction"));
766 #endif /* NO_PCREL_RELOCS */
769 tc_coff_fix2rtype (fixS
*fixP
)
771 if (fixP
->fx_tcbit
&& fixP
->fx_size
== 4)
772 return R_RELLONG_NEG
;
773 #ifdef NO_PCREL_RELOCS
774 know (fixP
->fx_pcrel
== 0);
775 return (fixP
->fx_size
== 1 ? R_RELBYTE
776 : fixP
->fx_size
== 2 ? R_DIR16
779 return (fixP
->fx_pcrel
780 ? (fixP
->fx_size
== 1 ? R_PCRBYTE
781 : fixP
->fx_size
== 2 ? R_PCRWORD
783 : (fixP
->fx_size
== 1 ? R_RELBYTE
784 : fixP
->fx_size
== 2 ? R_RELWORD
793 /* Return zero if the reference to SYMBOL from within the same segment may
796 /* On an ELF system, we can't relax an externally visible symbol,
797 because it may be overridden by a shared library. However, if
798 TARGET_OS is "elf", then we presume that we are assembling for an
799 embedded system, in which case we don't have to worry about shared
800 libraries, and we can relax any external sym. */
802 #define relaxable_symbol(symbol) \
803 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
804 || S_IS_WEAK (symbol)))
806 /* Compute the relocation code for a fixup of SIZE bytes, using pc
807 relative relocation if PCREL is non-zero. PIC says whether a special
808 pic relocation was requested. */
810 static bfd_reloc_code_real_type
811 get_reloc_code (int size
, int pcrel
, enum pic_relocation pic
)
819 return BFD_RELOC_8_GOT_PCREL
;
821 return BFD_RELOC_16_GOT_PCREL
;
823 return BFD_RELOC_32_GOT_PCREL
;
831 return BFD_RELOC_8_GOTOFF
;
833 return BFD_RELOC_16_GOTOFF
;
835 return BFD_RELOC_32_GOTOFF
;
843 return BFD_RELOC_8_PLT_PCREL
;
845 return BFD_RELOC_16_PLT_PCREL
;
847 return BFD_RELOC_32_PLT_PCREL
;
855 return BFD_RELOC_8_PLTOFF
;
857 return BFD_RELOC_16_PLTOFF
;
859 return BFD_RELOC_32_PLTOFF
;
869 return BFD_RELOC_8_PCREL
;
871 return BFD_RELOC_16_PCREL
;
873 return BFD_RELOC_32_PCREL
;
893 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
895 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
900 as_bad (_("Can not do %d byte relocation"), size
);
902 as_bad (_("Can not do %d byte pic relocation"), size
);
905 return BFD_RELOC_NONE
;
908 /* Here we decide which fixups can be adjusted to make them relative
909 to the beginning of the section instead of the symbol. Basically
910 we need to make sure that the dynamic relocations are done
911 correctly, so in some cases we force the original symbol to be
914 tc_m68k_fix_adjustable (fixS
*fixP
)
916 /* Adjust_reloc_syms doesn't know about the GOT. */
917 switch (fixP
->fx_r_type
)
919 case BFD_RELOC_8_GOT_PCREL
:
920 case BFD_RELOC_16_GOT_PCREL
:
921 case BFD_RELOC_32_GOT_PCREL
:
922 case BFD_RELOC_8_GOTOFF
:
923 case BFD_RELOC_16_GOTOFF
:
924 case BFD_RELOC_32_GOTOFF
:
925 case BFD_RELOC_8_PLT_PCREL
:
926 case BFD_RELOC_16_PLT_PCREL
:
927 case BFD_RELOC_32_PLT_PCREL
:
928 case BFD_RELOC_8_PLTOFF
:
929 case BFD_RELOC_16_PLTOFF
:
930 case BFD_RELOC_32_PLTOFF
:
933 case BFD_RELOC_VTABLE_INHERIT
:
934 case BFD_RELOC_VTABLE_ENTRY
:
944 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
946 #define relaxable_symbol(symbol) 1
953 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
956 bfd_reloc_code_real_type code
;
958 /* If the tcbit is set, then this was a fixup of a negative value
959 that was never resolved. We do not have a reloc to handle this,
960 so just return. We assume that other code will have detected this
961 situation and produced a helpful error message, so we just tell the
962 user that the reloc cannot be produced. */
966 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
967 _("Unable to produce reloc against symbol '%s'"),
968 S_GET_NAME (fixp
->fx_addsy
));
972 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
974 code
= fixp
->fx_r_type
;
976 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
977 that fixup_segment converted a non-PC relative reloc into a
978 PC relative reloc. In such a case, we need to convert the
985 code
= BFD_RELOC_8_PCREL
;
988 code
= BFD_RELOC_16_PCREL
;
991 code
= BFD_RELOC_32_PCREL
;
993 case BFD_RELOC_8_PCREL
:
994 case BFD_RELOC_16_PCREL
:
995 case BFD_RELOC_32_PCREL
:
996 case BFD_RELOC_8_GOT_PCREL
:
997 case BFD_RELOC_16_GOT_PCREL
:
998 case BFD_RELOC_32_GOT_PCREL
:
999 case BFD_RELOC_8_GOTOFF
:
1000 case BFD_RELOC_16_GOTOFF
:
1001 case BFD_RELOC_32_GOTOFF
:
1002 case BFD_RELOC_8_PLT_PCREL
:
1003 case BFD_RELOC_16_PLT_PCREL
:
1004 case BFD_RELOC_32_PLT_PCREL
:
1005 case BFD_RELOC_8_PLTOFF
:
1006 case BFD_RELOC_16_PLTOFF
:
1007 case BFD_RELOC_32_PLTOFF
:
1010 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1011 _("Cannot make %s relocation PC relative"),
1012 bfd_get_reloc_code_name (code
));
1018 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1019 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1021 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1022 MAP (1, 0, BFD_RELOC_8
);
1023 MAP (2, 0, BFD_RELOC_16
);
1024 MAP (4, 0, BFD_RELOC_32
);
1025 MAP (1, 1, BFD_RELOC_8_PCREL
);
1026 MAP (2, 1, BFD_RELOC_16_PCREL
);
1027 MAP (4, 1, BFD_RELOC_32_PCREL
);
1035 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1036 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1037 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1038 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1041 reloc
->addend
= fixp
->fx_addnumber
;
1045 if (!fixp
->fx_pcrel
)
1046 reloc
->addend
= fixp
->fx_addnumber
;
1048 reloc
->addend
= (section
->vma
1049 /* Explicit sign extension in case char is
1051 + ((fixp
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80
1052 + fixp
->fx_addnumber
1053 + md_pcrel_from (fixp
));
1056 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1057 assert (reloc
->howto
!= 0);
1062 #endif /* BFD_ASSEMBLER */
1064 /* Handle of the OPCODE hash table. NULL means any use before
1065 m68k_ip_begin() will crash. */
1066 static struct hash_control
*op_hash
;
1068 /* Assemble an m68k instruction. */
1071 m68k_ip (char *instring
)
1074 register struct m68k_op
*opP
;
1075 register const struct m68k_incant
*opcode
;
1076 register const char *s
;
1077 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1078 char *pdot
, *pdotmove
;
1079 enum m68k_size siz1
, siz2
;
1083 LITTLENUM_TYPE words
[6];
1084 LITTLENUM_TYPE
*wordp
;
1085 unsigned long ok_arch
= 0;
1087 if (*instring
== ' ')
1088 instring
++; /* Skip leading whitespace. */
1090 /* Scan up to end of operation-code, which MUST end in end-of-string
1091 or exactly 1 space. */
1093 for (p
= instring
; *p
!= '\0'; p
++)
1103 the_ins
.error
= _("No operator");
1107 /* p now points to the end of the opcode name, probably whitespace.
1108 Make sure the name is null terminated by clobbering the
1109 whitespace, look it up in the hash table, then fix it back.
1110 Remove a dot, first, since the opcode tables have none. */
1113 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1114 *pdotmove
= pdotmove
[1];
1120 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1125 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1126 *pdotmove
= pdotmove
[-1];
1133 the_ins
.error
= _("Unknown operator");
1137 /* Found a legitimate opcode, start matching operands. */
1141 if (opcode
->m_operands
== 0)
1143 char *old
= input_line_pointer
;
1145 input_line_pointer
= p
;
1146 /* Ahh - it's a motorola style psuedo op. */
1147 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1148 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1149 input_line_pointer
= old
;
1155 if (flag_mri
&& opcode
->m_opnum
== 0)
1157 /* In MRI mode, random garbage is allowed after an instruction
1158 which accepts no operands. */
1159 the_ins
.args
= opcode
->m_operands
;
1160 the_ins
.numargs
= opcode
->m_opnum
;
1161 the_ins
.numo
= opcode
->m_codenum
;
1162 the_ins
.opcode
[0] = getone (opcode
);
1163 the_ins
.opcode
[1] = gettwo (opcode
);
1167 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1169 p
= crack_operand (p
, opP
);
1173 the_ins
.error
= opP
->error
;
1178 opsfound
= opP
- &the_ins
.operands
[0];
1180 /* This ugly hack is to support the floating pt opcodes in their
1181 standard form. Essentially, we fake a first enty of type COP#1 */
1182 if (opcode
->m_operands
[0] == 'I')
1186 for (n
= opsfound
; n
> 0; --n
)
1187 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1189 memset (&the_ins
.operands
[0], '\0', sizeof (the_ins
.operands
[0]));
1190 the_ins
.operands
[0].mode
= CONTROL
;
1191 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1195 /* We've got the operands. Find an opcode that'll accept them. */
1198 /* If we didn't get the right number of ops, or we have no
1199 common model with this pattern then reject this pattern. */
1201 ok_arch
|= opcode
->m_arch
;
1202 if (opsfound
!= opcode
->m_opnum
1203 || ((opcode
->m_arch
& current_architecture
) == 0))
1207 for (s
= opcode
->m_operands
, opP
= &the_ins
.operands
[0];
1211 /* Warning: this switch is huge! */
1212 /* I've tried to organize the cases into this order:
1213 non-alpha first, then alpha by letter. Lower-case
1214 goes directly before uppercase counterpart. */
1215 /* Code with multiple case ...: gets sorted by the lowest
1216 case ... it belongs to. I hope this makes sense. */
1322 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1339 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1358 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1368 if (opP
->mode
!= IMMED
)
1370 else if (s
[1] == 'b'
1371 && ! isvar (&opP
->disp
)
1372 && (opP
->disp
.exp
.X_op
!= O_constant
1373 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1375 else if (s
[1] == 'B'
1376 && ! isvar (&opP
->disp
)
1377 && (opP
->disp
.exp
.X_op
!= O_constant
1378 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1380 else if (s
[1] == 'w'
1381 && ! isvar (&opP
->disp
)
1382 && (opP
->disp
.exp
.X_op
!= O_constant
1383 || ! isword (opP
->disp
.exp
.X_add_number
)))
1385 else if (s
[1] == 'W'
1386 && ! isvar (&opP
->disp
)
1387 && (opP
->disp
.exp
.X_op
!= O_constant
1388 || ! issword (opP
->disp
.exp
.X_add_number
)))
1394 if (opP
->mode
!= IMMED
)
1399 if (opP
->mode
== AREG
1400 || opP
->mode
== CONTROL
1401 || opP
->mode
== FPREG
1402 || opP
->mode
== IMMED
1403 || opP
->mode
== REGLST
1404 || (opP
->mode
!= ABSL
1406 || opP
->reg
== ZPC
)))
1411 if (opP
->mode
== CONTROL
1412 || opP
->mode
== FPREG
1413 || opP
->mode
== REGLST
1414 || opP
->mode
== IMMED
1415 || (opP
->mode
!= ABSL
1417 || opP
->reg
== ZPC
)))
1445 if (opP
->mode
== CONTROL
1446 || opP
->mode
== FPREG
1447 || opP
->mode
== REGLST
)
1452 if (opP
->mode
!= AINC
)
1457 if (opP
->mode
!= ADEC
)
1507 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1528 case '~': /* For now! (JF FOO is this right?) */
1550 if (opP
->mode
!= CONTROL
1551 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1556 if (opP
->mode
!= AREG
)
1561 if (opP
->mode
!= AINDR
)
1566 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1567 && (opP
->mode
!= DISP
1569 || opP
->reg
> ADDR7
))
1574 if (opP
->mode
!= ABSL
1576 && strncmp (instring
, "jbsr", 4) == 0))
1599 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1604 if (opP
->mode
!= DISP
1606 || opP
->reg
> ADDR7
)
1611 if (opP
->mode
!= DREG
)
1616 if (opP
->reg
!= ACC
)
1621 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1622 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1627 if (opP
->mode
!= FPREG
)
1632 if (opP
->reg
!= MACSR
)
1637 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1642 if (opP
->reg
!= MASK
)
1647 if (opP
->mode
!= CONTROL
1654 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1659 if (opP
->mode
!= CONTROL
1661 || opP
->reg
> last_movec_reg
)
1665 const enum m68k_register
*rp
;
1666 for (rp
= control_regs
; *rp
; rp
++)
1667 if (*rp
== opP
->reg
)
1675 if (opP
->mode
!= IMMED
)
1681 if (opP
->mode
== DREG
1682 || opP
->mode
== AREG
1683 || opP
->mode
== FPREG
)
1692 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1695 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1698 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1706 else if (opP
->mode
== CONTROL
)
1715 opP
->mask
= 1 << 24;
1718 opP
->mask
= 1 << 25;
1721 opP
->mask
= 1 << 26;
1730 else if (opP
->mode
!= REGLST
)
1732 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1734 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1739 if (opP
->mode
!= IMMED
)
1741 else if (opP
->disp
.exp
.X_op
!= O_constant
1742 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1744 else if (! m68k_quick
1745 && instring
[3] != 'q'
1746 && instring
[4] != 'q')
1751 if (opP
->mode
!= DREG
1752 && opP
->mode
!= IMMED
1753 && opP
->mode
!= ABSL
)
1758 if (opP
->mode
!= IMMED
)
1760 else if (opP
->disp
.exp
.X_op
!= O_constant
1761 || opP
->disp
.exp
.X_add_number
< 1
1762 || opP
->disp
.exp
.X_add_number
> 8)
1764 else if (! m68k_quick
1765 && (strncmp (instring
, "add", 3) == 0
1766 || strncmp (instring
, "sub", 3) == 0)
1767 && instring
[3] != 'q')
1772 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1777 if (opP
->mode
!= AINDR
1778 && (opP
->mode
!= BASE
1780 && opP
->reg
!= ZADDR0
)
1781 || opP
->disp
.exp
.X_op
!= O_absent
1782 || ((opP
->index
.reg
< DATA0
1783 || opP
->index
.reg
> DATA7
)
1784 && (opP
->index
.reg
< ADDR0
1785 || opP
->index
.reg
> ADDR7
))
1786 || opP
->index
.size
!= SIZE_UNSPEC
1787 || opP
->index
.scale
!= 1))
1792 if (opP
->mode
!= CONTROL
1793 || ! (opP
->reg
== FPI
1795 || opP
->reg
== FPC
))
1800 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1805 if (opP
->mode
!= IMMED
)
1807 else if (opP
->disp
.exp
.X_op
!= O_constant
1808 || opP
->disp
.exp
.X_add_number
< 0
1809 || opP
->disp
.exp
.X_add_number
> 7)
1814 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1819 if (opP
->mode
!= IMMED
)
1821 else if (opP
->disp
.exp
.X_op
!= O_constant
1822 || opP
->disp
.exp
.X_add_number
< -1
1823 || opP
->disp
.exp
.X_add_number
> 7
1824 || opP
->disp
.exp
.X_add_number
== 0)
1828 /* JF these are out of order. We could put them
1829 in order if we were willing to put up with
1830 bunches of #ifdef m68851s in the code.
1832 Don't forget that you need these operands
1833 to use 68030 MMU instructions. */
1835 /* Memory addressing mode used by pflushr. */
1837 if (opP
->mode
== CONTROL
1838 || opP
->mode
== FPREG
1839 || opP
->mode
== DREG
1840 || opP
->mode
== AREG
1841 || opP
->mode
== REGLST
)
1843 /* We should accept immediate operands, but they
1844 supposedly have to be quad word, and we don't
1845 handle that. I would like to see what a Motorola
1846 assembler does before doing something here. */
1847 if (opP
->mode
== IMMED
)
1852 if (opP
->mode
!= CONTROL
1853 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1858 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
1863 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
1868 if (opP
->mode
!= CONTROL
1871 && opP
->reg
!= SCC
))
1876 if (opP
->mode
!= CONTROL
1882 if (opP
->mode
!= CONTROL
1885 && opP
->reg
!= CRP
))
1909 if (opP
->mode
!= CONTROL
1910 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
1911 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1916 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
1921 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
1926 if (opP
->mode
!= CONTROL
1935 if (opP
->mode
!= ABSL
)
1940 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
1942 /* FIXME: kludge instead of fixing parser:
1943 upper/lower registers are *not* CONTROL
1944 registers, but ordinary ones. */
1945 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
1946 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
1953 if (!(opP
->mode
== AINDR
1954 || (opP
->mode
== DISP
1955 && !(opP
->reg
== PC
|| opP
->reg
== ZPC
))))
1960 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
1976 opcode
= opcode
->m_next
;
1981 && !(ok_arch
& current_architecture
))
1986 _("invalid instruction for this architecture; needs "),
1988 cp
= buf
+ strlen (buf
);
1992 strncpy (cp
, _("ColdFire ISA_A"),
1993 sizeof (buf
) - (cp
- buf
));
1995 strncpy (cp
, find_cf_chip (ok_arch
),
1996 sizeof (buf
) - (cp
- buf
));
2000 strncpy (cp
, _("ColdFire hardware divide"),
2001 sizeof (buf
) - (cp
- buf
));
2003 strncpy (cp
, find_cf_chip (ok_arch
),
2004 sizeof (buf
) - (cp
- buf
));
2008 strncpy (cp
, _("ColdFire ISA_A+"),
2009 sizeof (buf
) - (cp
- buf
));
2011 strncpy (cp
, find_cf_chip (ok_arch
),
2012 sizeof (buf
) - (cp
- buf
));
2016 strncpy (cp
, _("ColdFire ISA_B"),
2017 sizeof (buf
) - (cp
- buf
));
2019 strncpy (cp
, find_cf_chip (ok_arch
),
2020 sizeof (buf
) - (cp
- buf
));
2024 strncpy (cp
, _("ColdFire fpu"), sizeof (buf
) - (cp
- buf
));
2026 strncpy (cp
, find_cf_chip (ok_arch
),
2027 sizeof (buf
) - (cp
- buf
));
2031 strcpy (cp
, _("fpu (68040, 68060 or 68881/68882)"));
2034 strcpy (cp
, _("mmu (68030 or 68851)"));
2037 strcpy (cp
, _("68020 or higher"));
2040 strcpy (cp
, _("68000 or higher"));
2043 strcpy (cp
, _("68010 or higher"));
2047 int got_one
= 0, idx
;
2049 for (idx
= 0; idx
< n_archs
; idx
++)
2051 if ((archs
[idx
].arch
& ok_arch
)
2052 && ! archs
[idx
].alias
)
2056 strcpy (cp
, " or ");
2060 strcpy (cp
, archs
[idx
].name
);
2066 cp
= xmalloc (strlen (buf
) + 1);
2071 the_ins
.error
= _("operands mismatch");
2078 /* Now assemble it. */
2079 the_ins
.args
= opcode
->m_operands
;
2080 the_ins
.numargs
= opcode
->m_opnum
;
2081 the_ins
.numo
= opcode
->m_codenum
;
2082 the_ins
.opcode
[0] = getone (opcode
);
2083 the_ins
.opcode
[1] = gettwo (opcode
);
2085 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2087 /* This switch is a doozy.
2088 Watch the first step; its a big one! */
2121 tmpreg
= 0x3c; /* 7.4 */
2122 if (strchr ("bwl", s
[1]))
2123 nextword
= get_num (&opP
->disp
, 90);
2125 nextword
= get_num (&opP
->disp
, 0);
2126 if (isvar (&opP
->disp
))
2127 add_fix (s
[1], &opP
->disp
, 0, 0);
2131 if (!isbyte (nextword
))
2132 opP
->error
= _("operand out of range");
2137 if (!isword (nextword
))
2138 opP
->error
= _("operand out of range");
2143 if (!issword (nextword
))
2144 opP
->error
= _("operand out of range");
2149 addword (nextword
>> 16);
2176 /* We gotta put out some float. */
2177 if (op (&opP
->disp
) != O_big
)
2182 /* Can other cases happen here? */
2183 if (op (&opP
->disp
) != O_constant
)
2186 val
= (valueT
) offs (&opP
->disp
);
2190 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2191 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2195 offs (&opP
->disp
) = gencnt
;
2197 if (offs (&opP
->disp
) > 0)
2199 if (offs (&opP
->disp
) > baseo
)
2201 as_warn (_("Bignum too big for %c format; truncated"),
2203 offs (&opP
->disp
) = baseo
;
2205 baseo
-= offs (&opP
->disp
);
2208 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2209 offs (&opP
->disp
)--;
2214 gen_to_words (words
, baseo
, (long) outro
);
2215 for (wordp
= words
; baseo
--; wordp
++)
2219 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2222 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2225 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2228 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2231 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2235 nextword
= get_num (&opP
->disp
, 90);
2237 /* Convert mode 5 addressing with a zero offset into
2238 mode 2 addressing to reduce the instruction size by a
2240 if (! isvar (&opP
->disp
)
2242 && (opP
->disp
.size
== SIZE_UNSPEC
)
2243 && (opP
->reg
>= ADDR0
)
2244 && (opP
->reg
<= ADDR7
))
2246 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2251 && ! isvar (&opP
->disp
)
2254 opP
->disp
.exp
.X_op
= O_symbol
;
2255 #ifndef BFD_ASSEMBLER
2256 opP
->disp
.exp
.X_add_symbol
= &abs_symbol
;
2258 opP
->disp
.exp
.X_add_symbol
=
2259 section_symbol (absolute_section
);
2263 /* Force into index mode. Hope this works. */
2265 /* We do the first bit for 32-bit displacements, and the
2266 second bit for 16 bit ones. It is possible that we
2267 should make the default be WORD instead of LONG, but
2268 I think that'd break GCC, so we put up with a little
2269 inefficiency for the sake of working output. */
2271 if (!issword (nextword
)
2272 || (isvar (&opP
->disp
)
2273 && ((opP
->disp
.size
== SIZE_UNSPEC
2274 && flag_short_refs
== 0
2275 && cpu_of_arch (current_architecture
) >= m68020
2276 && ! arch_coldfire_p (current_architecture
))
2277 || opP
->disp
.size
== SIZE_LONG
)))
2279 if (cpu_of_arch (current_architecture
) < m68020
2280 || arch_coldfire_p (current_architecture
))
2282 _("displacement too large for this architecture; needs 68020 or higher");
2284 tmpreg
= 0x3B; /* 7.3 */
2286 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2287 if (isvar (&opP
->disp
))
2291 if (opP
->disp
.size
== SIZE_LONG
2293 /* If the displacement needs pic
2294 relocation it cannot be relaxed. */
2295 || opP
->disp
.pic_reloc
!= pic_none
2300 add_fix ('l', &opP
->disp
, 1, 2);
2304 add_frag (adds (&opP
->disp
),
2306 TAB (PCREL1632
, SZ_UNDEF
));
2313 add_fix ('l', &opP
->disp
, 0, 0);
2318 addword (nextword
>> 16);
2323 tmpreg
= 0x3A; /* 7.2 */
2325 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2327 if (isvar (&opP
->disp
))
2331 add_fix ('w', &opP
->disp
, 1, 0);
2334 add_fix ('w', &opP
->disp
, 0, 0);
2344 baseo
= get_num (&opP
->disp
, 90);
2345 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2346 outro
= get_num (&opP
->odisp
, 90);
2347 /* Figure out the `addressing mode'.
2348 Also turn on the BASE_DISABLE bit, if needed. */
2349 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2351 tmpreg
= 0x3b; /* 7.3 */
2352 if (opP
->reg
== ZPC
)
2355 else if (opP
->reg
== 0)
2358 tmpreg
= 0x30; /* 6.garbage */
2360 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2363 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2366 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2368 siz1
= opP
->disp
.size
;
2369 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2370 siz2
= opP
->odisp
.size
;
2374 /* Index register stuff. */
2375 if (opP
->index
.reg
!= 0
2376 && opP
->index
.reg
>= DATA
2377 && opP
->index
.reg
<= ADDR7
)
2379 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2381 if (opP
->index
.size
== SIZE_LONG
2382 || (opP
->index
.size
== SIZE_UNSPEC
2383 && m68k_index_width_default
== SIZE_LONG
))
2386 if ((opP
->index
.scale
!= 1
2387 && cpu_of_arch (current_architecture
) < m68020
)
2388 || (opP
->index
.scale
== 8
2389 && (arch_coldfire_p (current_architecture
)
2390 && !arch_coldfire_fpu (current_architecture
))))
2393 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2396 if (arch_coldfire_p (current_architecture
)
2397 && opP
->index
.size
== SIZE_WORD
)
2398 opP
->error
= _("invalid index size for coldfire");
2400 switch (opP
->index
.scale
)
2417 GET US OUT OF HERE! */
2419 /* Must be INDEX, with an index register. Address
2420 register cannot be ZERO-PC, and either :b was
2421 forced, or we know it will fit. For a 68000 or
2422 68010, force this mode anyways, because the
2423 larger modes aren't supported. */
2424 if (opP
->mode
== BASE
2425 && ((opP
->reg
>= ADDR0
2426 && opP
->reg
<= ADDR7
)
2429 if (siz1
== SIZE_BYTE
2430 || cpu_of_arch (current_architecture
) < m68020
2431 || arch_coldfire_p (current_architecture
)
2432 || (siz1
== SIZE_UNSPEC
2433 && ! isvar (&opP
->disp
)
2434 && issbyte (baseo
)))
2436 nextword
+= baseo
& 0xff;
2438 if (isvar (&opP
->disp
))
2440 /* Do a byte relocation. If it doesn't
2441 fit (possible on m68000) let the
2442 fixup processing complain later. */
2444 add_fix ('B', &opP
->disp
, 1, 1);
2446 add_fix ('B', &opP
->disp
, 0, 0);
2448 else if (siz1
!= SIZE_BYTE
)
2450 if (siz1
!= SIZE_UNSPEC
)
2451 as_warn (_("Forcing byte displacement"));
2452 if (! issbyte (baseo
))
2453 opP
->error
= _("byte displacement out of range");
2458 else if (siz1
== SIZE_UNSPEC
2460 && isvar (&opP
->disp
)
2461 && subs (&opP
->disp
) == NULL
2463 /* If the displacement needs pic
2464 relocation it cannot be relaxed. */
2465 && opP
->disp
.pic_reloc
== pic_none
2469 /* The code in md_convert_frag_1 needs to be
2470 able to adjust nextword. Call frag_grow
2471 to ensure that we have enough space in
2472 the frag obstack to make all the bytes
2475 nextword
+= baseo
& 0xff;
2477 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2478 TAB (PCINDEX
, SZ_UNDEF
));
2486 nextword
|= 0x40; /* No index reg. */
2487 if (opP
->index
.reg
>= ZDATA0
2488 && opP
->index
.reg
<= ZDATA7
)
2489 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2490 else if (opP
->index
.reg
>= ZADDR0
2491 || opP
->index
.reg
<= ZADDR7
)
2492 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2495 /* It isn't simple. */
2497 if (cpu_of_arch (current_architecture
) < m68020
2498 || arch_coldfire_p (current_architecture
))
2500 _("invalid operand mode for this architecture; needs 68020 or higher");
2503 /* If the guy specified a width, we assume that it is
2504 wide enough. Maybe it isn't. If so, we lose. */
2508 if (isvar (&opP
->disp
)
2510 : ! issword (baseo
))
2515 else if (! isvar (&opP
->disp
) && baseo
== 0)
2524 as_warn (_(":b not permitted; defaulting to :w"));
2534 /* Figure out inner displacement stuff. */
2535 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2537 if (cpu_of_arch (current_architecture
) & cpu32
)
2538 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2542 if (isvar (&opP
->odisp
)
2544 : ! issword (outro
))
2549 else if (! isvar (&opP
->odisp
) && outro
== 0)
2558 as_warn (_(":b not permitted; defaulting to :w"));
2567 if (opP
->mode
== POST
2568 && (nextword
& 0x40) == 0)
2573 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2575 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2576 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2578 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2580 if (siz1
== SIZE_LONG
)
2581 addword (baseo
>> 16);
2582 if (siz1
!= SIZE_UNSPEC
)
2585 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2586 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2587 if (siz2
== SIZE_LONG
)
2588 addword (outro
>> 16);
2589 if (siz2
!= SIZE_UNSPEC
)
2595 nextword
= get_num (&opP
->disp
, 90);
2596 switch (opP
->disp
.size
)
2601 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2603 tmpreg
= 0x38; /* 7.0 */
2607 if (isvar (&opP
->disp
)
2608 && !subs (&opP
->disp
)
2609 && adds (&opP
->disp
)
2611 /* If the displacement needs pic relocation it
2612 cannot be relaxed. */
2613 && opP
->disp
.pic_reloc
== pic_none
2616 && !strchr ("~%&$?", s
[0]))
2618 tmpreg
= 0x3A; /* 7.2 */
2619 add_frag (adds (&opP
->disp
),
2621 TAB (ABSTOPCREL
, SZ_UNDEF
));
2624 /* Fall through into long. */
2626 if (isvar (&opP
->disp
))
2627 add_fix ('l', &opP
->disp
, 0, 0);
2629 tmpreg
= 0x39;/* 7.1 mode */
2630 addword (nextword
>> 16);
2635 as_bad (_("unsupported byte value; use a different suffix"));
2639 if (isvar (&opP
->disp
))
2640 add_fix ('w', &opP
->disp
, 0, 0);
2642 tmpreg
= 0x38;/* 7.0 mode */
2650 as_bad (_("unknown/incorrect operand"));
2654 /* If s[0] is '4', then this is for the mac instructions
2655 that can have a trailing_ampersand set. If so, set 0x100
2656 bit on tmpreg so install_gen_operand can check for it and
2657 set the appropriate bit (word2, bit 5). */
2660 if (opP
->trailing_ampersand
)
2663 install_gen_operand (s
[1], tmpreg
);
2669 { /* JF: I hate floating point! */
2684 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2685 if (isvar (&opP
->disp
))
2686 add_fix (s
[1], &opP
->disp
, 0, 0);
2689 case 'b': /* Danger: These do no check for
2690 certain types of overflow.
2692 if (!isbyte (tmpreg
))
2693 opP
->error
= _("out of range");
2694 insop (tmpreg
, opcode
);
2695 if (isvar (&opP
->disp
))
2696 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2697 (opcode
->m_codenum
) * 2 + 1;
2700 if (!issbyte (tmpreg
))
2701 opP
->error
= _("out of range");
2702 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2703 if (isvar (&opP
->disp
))
2704 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2707 if (!isword (tmpreg
))
2708 opP
->error
= _("out of range");
2709 insop (tmpreg
, opcode
);
2710 if (isvar (&opP
->disp
))
2711 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2714 if (!issword (tmpreg
))
2715 opP
->error
= _("out of range");
2716 insop (tmpreg
, opcode
);
2717 if (isvar (&opP
->disp
))
2718 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2721 /* Because of the way insop works, we put these two out
2723 insop (tmpreg
, opcode
);
2724 insop (tmpreg
>> 16, opcode
);
2725 if (isvar (&opP
->disp
))
2726 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2733 install_operand (s
[1], tmpreg
);
2744 install_operand (s
[1], opP
->reg
- ADDR
);
2748 tmpreg
= get_num (&opP
->disp
, 90);
2752 add_fix ('B', &opP
->disp
, 1, -1);
2755 add_fix ('w', &opP
->disp
, 1, 0);
2760 if (! HAVE_LONG_BRANCH (current_architecture
))
2761 as_warn (_("Can't use long branches on 68000/68010/5200"));
2762 the_ins
.opcode
[0] |= 0xff;
2763 add_fix ('l', &opP
->disp
, 1, 0);
2768 if (subs (&opP
->disp
)) /* We can't relax it. */
2772 /* If the displacement needs pic relocation it cannot be
2774 if (opP
->disp
.pic_reloc
!= pic_none
)
2777 /* This could either be a symbol, or an absolute
2778 address. If it's an absolute address, turn it into
2779 an absolute jump right here and keep it out of the
2781 if (adds (&opP
->disp
) == 0)
2783 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
2784 the_ins
.opcode
[0] = 0x4EF9;
2785 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
2786 the_ins
.opcode
[0] = 0x4EB9;
2789 the_ins
.opcode
[0] ^= 0x0100;
2790 the_ins
.opcode
[0] |= 0x0006;
2793 add_fix ('l', &opP
->disp
, 0, 0);
2799 /* Now we know it's going into the relaxer. Now figure
2800 out which mode. We try in this order of preference:
2801 long branch, absolute jump, byte/word branches only. */
2802 if (HAVE_LONG_BRANCH (current_architecture
))
2803 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2804 TAB (BRANCHBWL
, SZ_UNDEF
));
2805 else if (! flag_keep_pcrel
)
2807 if ((the_ins
.opcode
[0] == 0x6000)
2808 || (the_ins
.opcode
[0] == 0x6100))
2809 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2810 TAB (BRABSJUNC
, SZ_UNDEF
));
2812 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2813 TAB (BRABSJCOND
, SZ_UNDEF
));
2816 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2817 TAB (BRANCHBW
, SZ_UNDEF
));
2820 if (isvar (&opP
->disp
))
2822 /* Check for DBcc instructions. We can relax them,
2823 but only if we have long branches and/or absolute
2825 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2826 && (HAVE_LONG_BRANCH (current_architecture
)
2827 || (! flag_keep_pcrel
)))
2829 if (HAVE_LONG_BRANCH (current_architecture
))
2830 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2831 TAB (DBCCLBR
, SZ_UNDEF
));
2833 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2834 TAB (DBCCABSJ
, SZ_UNDEF
));
2837 add_fix ('w', &opP
->disp
, 1, 0);
2841 case 'C': /* Fixed size LONG coproc branches. */
2842 add_fix ('l', &opP
->disp
, 1, 0);
2846 case 'c': /* Var size Coprocesssor branches. */
2847 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
2849 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2850 add_fix ('l', &opP
->disp
, 1, 0);
2855 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2856 TAB (FBRANCH
, SZ_UNDEF
));
2863 case 'C': /* Ignore it. */
2866 case 'd': /* JF this is a kludge. */
2867 install_operand ('s', opP
->reg
- ADDR
);
2868 tmpreg
= get_num (&opP
->disp
, 90);
2869 if (!issword (tmpreg
))
2871 as_warn (_("Expression out of range, using 0"));
2878 install_operand (s
[1], opP
->reg
- DATA
);
2881 case 'e': /* EMAC ACCx, reg/reg. */
2882 install_operand (s
[1], opP
->reg
- ACC
);
2885 case 'E': /* Ignore it. */
2889 install_operand (s
[1], opP
->reg
- FP0
);
2892 case 'g': /* EMAC ACCEXTx. */
2893 install_operand (s
[1], opP
->reg
- ACCEXT01
);
2896 case 'G': /* Ignore it. */
2901 tmpreg
= opP
->reg
- COP0
;
2902 install_operand (s
[1], tmpreg
);
2905 case 'i': /* MAC/EMAC scale factor. */
2906 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
2909 case 'J': /* JF foo. */
3038 install_operand (s
[1], tmpreg
);
3042 tmpreg
= get_num (&opP
->disp
, 55);
3043 install_operand (s
[1], tmpreg
& 0x7f);
3050 if (tmpreg
& 0x7FF0000)
3051 as_bad (_("Floating point register in register list"));
3052 insop (reverse_16_bits (tmpreg
), opcode
);
3056 if (tmpreg
& 0x700FFFF)
3057 as_bad (_("Wrong register in floating-point reglist"));
3058 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
3066 if (tmpreg
& 0x7FF0000)
3067 as_bad (_("Floating point register in register list"));
3068 insop (tmpreg
, opcode
);
3070 else if (s
[1] == '8')
3072 if (tmpreg
& 0x0FFFFFF)
3073 as_bad (_("incorrect register in reglist"));
3074 install_operand (s
[1], tmpreg
>> 24);
3078 if (tmpreg
& 0x700FFFF)
3079 as_bad (_("wrong register in floating-point reglist"));
3081 install_operand (s
[1], tmpreg
>> 16);
3086 install_operand (s
[1], get_num (&opP
->disp
, 60));
3090 tmpreg
= ((opP
->mode
== DREG
)
3091 ? 0x20 + (int) (opP
->reg
- DATA
)
3092 : (get_num (&opP
->disp
, 40) & 0x1F));
3093 install_operand (s
[1], tmpreg
);
3097 tmpreg
= get_num (&opP
->disp
, 10);
3100 install_operand (s
[1], tmpreg
);
3104 /* This depends on the fact that ADDR registers are eight
3105 more than their corresponding DATA regs, so the result
3106 will have the ADDR_REG bit set. */
3107 install_operand (s
[1], opP
->reg
- DATA
);
3111 if (opP
->mode
== AINDR
)
3112 install_operand (s
[1], opP
->reg
- DATA
);
3114 install_operand (s
[1], opP
->index
.reg
- DATA
);
3118 if (opP
->reg
== FPI
)
3120 else if (opP
->reg
== FPS
)
3122 else if (opP
->reg
== FPC
)
3126 install_operand (s
[1], tmpreg
);
3129 case 'S': /* Ignore it. */
3133 install_operand (s
[1], get_num (&opP
->disp
, 30));
3136 case 'U': /* Ignore it. */
3155 as_fatal (_("failed sanity check"));
3156 } /* switch on cache token. */
3157 install_operand (s
[1], tmpreg
);
3160 /* JF: These are out of order, I fear. */
3173 install_operand (s
[1], tmpreg
);
3199 install_operand (s
[1], tmpreg
);
3203 if (opP
->reg
== VAL
)
3222 install_operand (s
[1], tmpreg
);
3236 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3247 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3253 install_operand (s
[1], tmpreg
);
3256 know (opP
->reg
== PSR
);
3259 know (opP
->reg
== PCSR
);
3274 install_operand (s
[1], tmpreg
);
3277 tmpreg
= get_num (&opP
->disp
, 20);
3278 install_operand (s
[1], tmpreg
);
3280 case '_': /* used only for move16 absolute 32-bit address. */
3281 if (isvar (&opP
->disp
))
3282 add_fix ('l', &opP
->disp
, 0, 0);
3283 tmpreg
= get_num (&opP
->disp
, 90);
3284 addword (tmpreg
>> 16);
3285 addword (tmpreg
& 0xFFFF);
3288 install_operand (s
[1], opP
->reg
- DATA0L
);
3289 opP
->reg
-= (DATA0L
);
3290 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3293 tmpreg
= get_num (&opP
->disp
, 80);
3296 install_operand (s
[1], tmpreg
);
3303 /* By the time whe get here (FINALLY) the_ins contains the complete
3304 instruction, ready to be emitted. . . */
3308 reverse_16_bits (int in
)
3313 static int mask
[16] =
3315 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3316 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3318 for (n
= 0; n
< 16; n
++)
3321 out
|= mask
[15 - n
];
3324 } /* reverse_16_bits() */
3327 reverse_8_bits (int in
)
3332 static int mask
[8] =
3334 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3337 for (n
= 0; n
< 8; n
++)
3343 } /* reverse_8_bits() */
3345 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3346 (that value is chosen in the frag_var call in md_assemble). TYPE
3347 is the subtype of the frag to be generated; its primary type is
3348 rs_machine_dependent.
3350 The TYPE parameter is also used by md_convert_frag_1 and
3351 md_estimate_size_before_relax. The appropriate type of fixup will
3352 be emitted by md_convert_frag_1.
3354 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3356 install_operand (int mode
, int val
)
3361 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3364 the_ins
.opcode
[0] |= val
<< 9;
3367 the_ins
.opcode
[1] |= val
<< 12;
3370 the_ins
.opcode
[1] |= val
<< 6;
3373 the_ins
.opcode
[1] |= val
;
3376 the_ins
.opcode
[2] |= val
<< 12;
3379 the_ins
.opcode
[2] |= val
<< 6;
3382 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3383 three words long! */
3385 the_ins
.opcode
[2] |= val
;
3388 the_ins
.opcode
[1] |= val
<< 7;
3391 the_ins
.opcode
[1] |= val
<< 10;
3395 the_ins
.opcode
[1] |= val
<< 5;
3400 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3403 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3406 the_ins
.opcode
[0] |= val
= 0xff;
3409 the_ins
.opcode
[0] |= val
<< 9;
3412 the_ins
.opcode
[1] |= val
;
3415 the_ins
.opcode
[1] |= val
;
3416 the_ins
.numo
++; /* What a hack. */
3419 the_ins
.opcode
[1] |= val
<< 4;
3427 the_ins
.opcode
[0] |= (val
<< 6);
3430 the_ins
.opcode
[1] = (val
>> 16);
3431 the_ins
.opcode
[2] = val
& 0xffff;
3434 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3435 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3436 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3438 case 'n': /* MAC/EMAC Rx on !load. */
3439 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3440 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3441 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3443 case 'o': /* MAC/EMAC Rx on load. */
3444 the_ins
.opcode
[1] |= val
<< 12;
3445 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3447 case 'M': /* MAC/EMAC Ry on !load. */
3448 the_ins
.opcode
[0] |= (val
& 0xF);
3449 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3451 case 'N': /* MAC/EMAC Ry on load. */
3452 the_ins
.opcode
[1] |= (val
& 0xF);
3453 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3456 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3459 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3462 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3464 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3465 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3466 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3468 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3469 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3470 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3473 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3476 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3480 as_fatal (_("failed sanity check."));
3485 install_gen_operand (int mode
, int val
)
3489 case '/': /* Special for mask loads for mac/msac insns with
3490 possible mask; trailing_ampersend set in bit 8. */
3491 the_ins
.opcode
[0] |= (val
& 0x3f);
3492 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3495 the_ins
.opcode
[0] |= val
;
3498 /* This is a kludge!!! */
3499 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3508 the_ins
.opcode
[0] |= val
;
3510 /* more stuff goes here. */
3512 as_fatal (_("failed sanity check."));
3516 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3517 then deal with the bitfield hack. */
3520 crack_operand (char *str
, struct m68k_op
*opP
)
3522 register int parens
;
3524 register char *beg_str
;
3532 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3538 else if (*str
== ')')
3542 opP
->error
= _("Extra )");
3548 if (flag_mri
&& *str
== '\'')
3549 inquote
= ! inquote
;
3551 if (!*str
&& parens
)
3553 opP
->error
= _("Missing )");
3558 if (m68k_ip_op (beg_str
, opP
) != 0)
3565 c
= *++str
; /* JF bitfield hack. */
3570 as_bad (_("Missing operand"));
3573 /* Detect MRI REG symbols and convert them to REGLSTs. */
3574 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3577 opP
->mask
= ~(int)opP
->reg
;
3584 /* This is the guts of the machine-dependent assembler. STR points to a
3585 machine dependent instruction. This function is supposed to emit
3586 the frags/bytes it assembles to.
3590 insert_reg (const char *regname
, int regnum
)
3595 #ifdef REGISTER_PREFIX
3596 if (!flag_reg_prefix_optional
)
3598 buf
[0] = REGISTER_PREFIX
;
3599 strcpy (buf
+ 1, regname
);
3604 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3605 &zero_address_frag
));
3607 for (i
= 0; regname
[i
]; i
++)
3608 buf
[i
] = TOUPPER (regname
[i
]);
3611 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3612 &zero_address_frag
));
3621 static const struct init_entry init_table
[] =
3681 { "accext01", ACCEXT01
},
3682 { "accext23", ACCEXT23
},
3686 /* Control registers. */
3687 { "sfc", SFC
}, /* Source Function Code. */
3689 { "dfc", DFC
}, /* Destination Function Code. */
3691 { "cacr", CACR
}, /* Cache Control Register. */
3692 { "caar", CAAR
}, /* Cache Address Register. */
3694 { "usp", USP
}, /* User Stack Pointer. */
3695 { "vbr", VBR
}, /* Vector Base Register. */
3696 { "msp", MSP
}, /* Master Stack Pointer. */
3697 { "isp", ISP
}, /* Interrupt Stack Pointer. */
3699 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
3700 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
3701 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
3702 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
3704 /* 68ec040 versions of same */
3705 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
3706 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
3707 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
3708 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
3710 /* mcf5200 versions of same. The ColdFire programmer's reference
3711 manual indicated that the order is 2,3,0,1, but Ken Rose
3712 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3713 { "acr0", ACR0
}, /* Access Control Unit 0. */
3714 { "acr1", ACR1
}, /* Access Control Unit 1. */
3715 { "acr2", ACR2
}, /* Access Control Unit 2. */
3716 { "acr3", ACR3
}, /* Access Control Unit 3. */
3718 { "tc", TC
}, /* MMU Translation Control Register. */
3721 { "mmusr", MMUSR
}, /* MMU Status Register. */
3722 { "srp", SRP
}, /* User Root Pointer. */
3723 { "urp", URP
}, /* Supervisor Root Pointer. */
3728 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
3729 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
3730 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
3731 { "mbar", MBAR
}, /* Module Base Address Register. */
3733 { "mbar0", MBAR0
}, /* mcfv4e registers. */
3734 { "mbar1", MBAR1
}, /* mcfv4e registers. */
3735 { "rombar0", ROMBAR
}, /* mcfv4e registers. */
3736 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
3737 { "mpcr", MPCR
}, /* mcfv4e registers. */
3738 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
3739 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
3740 { "asid", TC
}, /* mcfv4e registers. */
3741 { "mmubar", BUSCR
}, /* mcfv4e registers. */
3742 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
3743 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
3744 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
3745 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
3746 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
3747 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
3748 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
3749 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
3750 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
3751 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
3752 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
3753 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
3755 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
3756 { "rambar", RAMBAR
}, /* mcf528x registers. */
3757 /* End of control registers. */
3791 /* 68ec030 versions of same. */
3794 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3797 /* Suppressed data and address registers. */
3815 /* Upper and lower data and address registers, used by macw and msacw. */
3856 init_regtable (void)
3859 for (i
= 0; init_table
[i
].name
; i
++)
3860 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3863 static int no_68851
, no_68881
;
3866 /* a.out machine type. Default to 68020. */
3867 int m68k_aout_machtype
= 2;
3871 md_assemble (char *str
)
3878 int shorts_this_frag
;
3881 /* In MRI mode, the instruction and operands are separated by a
3882 space. Anything following the operands is a comment. The label
3883 has already been removed. */
3891 for (s
= str
; *s
!= '\0'; s
++)
3893 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
3911 inquote
= ! inquote
;
3916 memset (&the_ins
, '\0', sizeof (the_ins
));
3921 for (n
= 0; n
< the_ins
.numargs
; n
++)
3922 if (the_ins
.operands
[n
].error
)
3924 er
= the_ins
.operands
[n
].error
;
3930 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
3934 /* If there is a current label, record that it marks an instruction. */
3935 if (current_label
!= NULL
)
3937 current_label
->text
= 1;
3938 current_label
= NULL
;
3942 /* Tie dwarf2 debug info to the address at the start of the insn. */
3943 dwarf2_emit_insn (0);
3946 if (the_ins
.nfrag
== 0)
3948 /* No frag hacking involved; just put it out. */
3949 toP
= frag_more (2 * the_ins
.numo
);
3950 fromP
= &the_ins
.opcode
[0];
3951 for (m
= the_ins
.numo
; m
; --m
)
3953 md_number_to_chars (toP
, (long) (*fromP
), 2);
3957 /* Put out symbol-dependent info. */
3958 for (m
= 0; m
< the_ins
.nrel
; m
++)
3960 switch (the_ins
.reloc
[m
].wid
)
3979 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3980 the_ins
.reloc
[m
].wid
);
3983 fixP
= fix_new_exp (frag_now
,
3984 ((toP
- frag_now
->fr_literal
)
3985 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3987 &the_ins
.reloc
[m
].exp
,
3988 the_ins
.reloc
[m
].pcrel
,
3989 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
3990 the_ins
.reloc
[m
].pic_reloc
));
3991 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3992 if (the_ins
.reloc
[m
].wid
== 'B')
3993 fixP
->fx_signed
= 1;
3998 /* There's some frag hacking. */
4000 /* Calculate the max frag size. */
4003 wid
= 2 * the_ins
.fragb
[0].fragoff
;
4004 for (n
= 1; n
< the_ins
.nfrag
; n
++)
4005 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4006 /* frag_var part. */
4008 /* Make sure the whole insn fits in one chunk, in particular that
4009 the var part is attached, as we access one byte before the
4010 variable frag for byte branches. */
4014 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
4019 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
4021 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4022 toP
= frag_more (wid
);
4024 shorts_this_frag
= 0;
4025 for (m
= wid
/ 2; m
; --m
)
4027 md_number_to_chars (toP
, (long) (*fromP
), 2);
4032 for (m
= 0; m
< the_ins
.nrel
; m
++)
4034 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
4036 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
4039 wid
= the_ins
.reloc
[m
].wid
;
4042 the_ins
.reloc
[m
].wid
= 0;
4043 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4045 fixP
= fix_new_exp (frag_now
,
4046 ((toP
- frag_now
->fr_literal
)
4047 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4049 &the_ins
.reloc
[m
].exp
,
4050 the_ins
.reloc
[m
].pcrel
,
4051 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4052 the_ins
.reloc
[m
].pic_reloc
));
4053 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4055 (void) frag_var (rs_machine_dependent
, 10, 0,
4056 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
4057 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
4059 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4060 shorts_this_frag
= 0;
4063 toP
= frag_more (n
* sizeof (short));
4066 md_number_to_chars (toP
, (long) (*fromP
), 2);
4072 for (m
= 0; m
< the_ins
.nrel
; m
++)
4076 wid
= the_ins
.reloc
[m
].wid
;
4079 the_ins
.reloc
[m
].wid
= 0;
4080 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4082 fixP
= fix_new_exp (frag_now
,
4083 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
4084 - shorts_this_frag
* 2),
4086 &the_ins
.reloc
[m
].exp
,
4087 the_ins
.reloc
[m
].pcrel
,
4088 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4089 the_ins
.reloc
[m
].pic_reloc
));
4090 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4094 /* Comparison function used by qsort to rank the opcode entries by name. */
4097 m68k_compare_opcode (const void * v1
, const void * v2
)
4099 struct m68k_opcode
* op1
, * op2
;
4102 op1
= *(struct m68k_opcode
**) v1
;
4103 op2
= *(struct m68k_opcode
**) v2
;
4105 /* Compare the two names. If different, return the comparison.
4106 If the same, return the order they are in the opcode table. */
4107 ret
= strcmp (op1
->name
, op2
->name
);
4118 const struct m68k_opcode
*ins
;
4119 struct m68k_incant
*hack
, *slak
;
4120 const char *retval
= 0; /* Empty string, or error msg text. */
4123 /* Set up hash tables with 68000 instructions.
4124 similar to what the vax assembler does. */
4125 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4126 a copy of it at runtime, adding in the information we want but isn't
4127 there. I think it'd be better to have an awk script hack the table
4128 at compile time. Or even just xstr the table and use it as-is. But
4129 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4134 flag_reg_prefix_optional
= 1;
4136 if (! m68k_rel32_from_cmdline
)
4140 /* First sort the opcode table into alphabetical order to seperate
4141 the order that the assembler wants to see the opcodes from the
4142 order that the disassembler wants to see them. */
4143 m68k_sorted_opcodes
= xmalloc (m68k_numopcodes
* sizeof (* m68k_sorted_opcodes
));
4144 if (!m68k_sorted_opcodes
)
4145 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4146 m68k_numopcodes
* sizeof (* m68k_sorted_opcodes
));
4148 for (i
= m68k_numopcodes
; i
--;)
4149 m68k_sorted_opcodes
[i
] = m68k_opcodes
+ i
;
4151 qsort (m68k_sorted_opcodes
, m68k_numopcodes
,
4152 sizeof (m68k_sorted_opcodes
[0]), m68k_compare_opcode
);
4154 op_hash
= hash_new ();
4156 obstack_begin (&robyn
, 4000);
4157 for (i
= 0; i
< m68k_numopcodes
; i
++)
4159 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4162 ins
= m68k_sorted_opcodes
[i
];
4164 /* We *could* ignore insns that don't match our
4165 arch here by just leaving them out of the hash. */
4166 slak
->m_operands
= ins
->args
;
4167 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4168 slak
->m_arch
= ins
->arch
;
4169 slak
->m_opcode
= ins
->opcode
;
4170 /* This is kludgey. */
4171 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
4172 if (i
+ 1 != m68k_numopcodes
4173 && !strcmp (ins
->name
, m68k_sorted_opcodes
[i
+ 1]->name
))
4175 slak
->m_next
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4180 slak
= slak
->m_next
;
4184 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
4186 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
4189 for (i
= 0; i
< m68k_numaliases
; i
++)
4191 const char *name
= m68k_opcode_aliases
[i
].primary
;
4192 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4193 PTR val
= hash_find (op_hash
, name
);
4196 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4197 retval
= hash_insert (op_hash
, alias
, val
);
4199 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4202 /* In MRI mode, all unsized branches are variable sized. Normally,
4203 they are word sized. */
4206 static struct m68k_opcode_alias mri_aliases
[] =
4227 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4230 const char *name
= mri_aliases
[i
].primary
;
4231 const char *alias
= mri_aliases
[i
].alias
;
4232 PTR val
= hash_find (op_hash
, name
);
4235 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4236 retval
= hash_jam (op_hash
, alias
, val
);
4238 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4242 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4244 notend_table
[i
] = 0;
4245 alt_notend_table
[i
] = 0;
4248 notend_table
[','] = 1;
4249 notend_table
['{'] = 1;
4250 notend_table
['}'] = 1;
4251 alt_notend_table
['a'] = 1;
4252 alt_notend_table
['A'] = 1;
4253 alt_notend_table
['d'] = 1;
4254 alt_notend_table
['D'] = 1;
4255 alt_notend_table
['#'] = 1;
4256 alt_notend_table
['&'] = 1;
4257 alt_notend_table
['f'] = 1;
4258 alt_notend_table
['F'] = 1;
4259 #ifdef REGISTER_PREFIX
4260 alt_notend_table
[REGISTER_PREFIX
] = 1;
4263 /* We need to put '(' in alt_notend_table to handle
4264 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4265 alt_notend_table
['('] = 1;
4267 /* We need to put '@' in alt_notend_table to handle
4268 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4269 alt_notend_table
['@'] = 1;
4271 /* We need to put digits in alt_notend_table to handle
4272 bfextu %d0{24:1},%d0 */
4273 alt_notend_table
['0'] = 1;
4274 alt_notend_table
['1'] = 1;
4275 alt_notend_table
['2'] = 1;
4276 alt_notend_table
['3'] = 1;
4277 alt_notend_table
['4'] = 1;
4278 alt_notend_table
['5'] = 1;
4279 alt_notend_table
['6'] = 1;
4280 alt_notend_table
['7'] = 1;
4281 alt_notend_table
['8'] = 1;
4282 alt_notend_table
['9'] = 1;
4284 #ifndef MIT_SYNTAX_ONLY
4285 /* Insert pseudo ops, these have to go into the opcode table since
4286 gas expects pseudo ops to start with a dot. */
4290 while (mote_pseudo_table
[n
].poc_name
)
4292 hack
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4293 hash_insert (op_hash
,
4294 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
4295 hack
->m_operands
= 0;
4305 record_alignment (text_section
, 2);
4306 record_alignment (data_section
, 2);
4307 record_alignment (bss_section
, 2);
4312 select_control_regs (void)
4314 /* Note which set of "movec" control registers is available. */
4315 switch (current_chip
)
4319 as_warn (_("architecture not yet selected: defaulting to 68020"));
4320 control_regs
= m68020_control_regs
;
4324 control_regs
= m68000_control_regs
;
4327 control_regs
= m68010_control_regs
;
4331 control_regs
= m68020_control_regs
;
4334 control_regs
= m68040_control_regs
;
4337 control_regs
= m68060_control_regs
;
4340 control_regs
= cpu32_control_regs
;
4347 control_regs
= mcf_control_regs
;
4351 control_regs
= mcf528x_control_regs
;
4355 control_regs
= mcfv4e_control_regs
;
4363 m68k_init_after_args (void)
4365 if (cpu_of_arch (current_architecture
) == 0)
4368 const char *default_cpu
= TARGET_CPU
;
4370 if (*default_cpu
== 'm')
4372 for (i
= 0; i
< n_archs
; i
++)
4373 if (strcasecmp (default_cpu
, archs
[i
].name
) == 0)
4377 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU
);
4378 current_architecture
|= m68020
;
4381 current_architecture
|= archs
[i
].arch
;
4383 /* Permit m68881 specification with all cpus; those that can't work
4384 with a coprocessor could be doing emulation. */
4385 if (current_architecture
& m68851
)
4387 if (current_architecture
& m68040
)
4388 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4390 /* What other incompatibilities could we check for? */
4392 /* Toss in some default assumptions about coprocessors. */
4394 && (cpu_of_arch (current_architecture
)
4395 /* Can CPU32 have a 68881 coprocessor?? */
4396 & (m68020
| m68030
| cpu32
)))
4397 current_architecture
|= m68881
;
4400 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
4401 && (cpu_of_arch (current_architecture
) & m68040up
) == 0)
4402 current_architecture
|= m68851
;
4404 if (no_68881
&& (current_architecture
& m68881
))
4405 as_bad (_("options for 68881 and no-68881 both given"));
4407 if (no_68851
&& (current_architecture
& m68851
))
4408 as_bad (_("options for 68851 and no-68851 both given"));
4411 /* Work out the magic number. This isn't very general. */
4412 if (current_architecture
& m68000
)
4413 m68k_aout_machtype
= 0;
4414 else if (current_architecture
& m68010
)
4415 m68k_aout_machtype
= 1;
4416 else if (current_architecture
& m68020
)
4417 m68k_aout_machtype
= 2;
4419 m68k_aout_machtype
= 2;
4422 /* Note which set of "movec" control registers is available. */
4423 select_control_regs ();
4425 if (cpu_of_arch (current_architecture
) < m68020
4426 || arch_coldfire_p (current_architecture
))
4427 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
4430 /* This is called when a label is defined. */
4433 m68k_frob_label (symbolS
*sym
)
4435 struct label_line
*n
;
4437 n
= (struct label_line
*) xmalloc (sizeof *n
);
4440 as_where (&n
->file
, &n
->line
);
4446 /* This is called when a value that is not an instruction is emitted. */
4449 m68k_flush_pending_output (void)
4451 current_label
= NULL
;
4454 /* This is called at the end of the assembly, when the final value of
4455 the label is known. We warn if this is a text symbol aligned at an
4459 m68k_frob_symbol (symbolS
*sym
)
4461 if (S_GET_SEGMENT (sym
) == reg_section
4462 && (int) S_GET_VALUE (sym
) < 0)
4464 S_SET_SEGMENT (sym
, absolute_section
);
4465 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4467 else if ((S_GET_VALUE (sym
) & 1) != 0)
4469 struct label_line
*l
;
4471 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4473 if (l
->label
== sym
)
4476 as_warn_where (l
->file
, l
->line
,
4477 _("text label `%s' aligned to odd boundary"),
4485 /* This is called if we go in or out of MRI mode because of the .mri
4489 m68k_mri_mode_change (int on
)
4493 if (! flag_reg_prefix_optional
)
4495 flag_reg_prefix_optional
= 1;
4496 #ifdef REGISTER_PREFIX
4501 if (! m68k_rel32_from_cmdline
)
4506 if (! reg_prefix_optional_seen
)
4508 #ifdef REGISTER_PREFIX_OPTIONAL
4509 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4511 flag_reg_prefix_optional
= 0;
4513 #ifdef REGISTER_PREFIX
4518 if (! m68k_rel32_from_cmdline
)
4523 /* Equal to MAX_PRECISION in atof-ieee.c. */
4524 #define MAX_LITTLENUMS 6
4526 /* Turn a string in input_line_pointer into a floating point constant
4527 of type TYPE, and store the appropriate bytes in *LITP. The number
4528 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4529 returned, or NULL on OK. */
4532 md_atof (int type
, char *litP
, int *sizeP
)
4535 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4536 LITTLENUM_TYPE
*wordP
;
4567 return _("Bad call to MD_ATOF()");
4569 t
= atof_ieee (input_line_pointer
, type
, words
);
4571 input_line_pointer
= t
;
4573 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4574 for (wordP
= words
; prec
--;)
4576 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4577 litP
+= sizeof (LITTLENUM_TYPE
);
4583 md_number_to_chars (char *buf
, valueT val
, int n
)
4585 number_to_chars_bigendian (buf
, val
, n
);
4589 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4591 offsetT val
= *valP
;
4592 addressT upper_limit
;
4593 offsetT lower_limit
;
4595 /* This is unnecessary but it convinces the native rs6000 compiler
4596 to generate the code we want. */
4597 char *buf
= fixP
->fx_frag
->fr_literal
;
4598 buf
+= fixP
->fx_where
;
4599 /* End ibm compiler workaround. */
4601 val
= ((val
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4603 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4609 memset (buf
, 0, fixP
->fx_size
);
4610 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4612 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4613 && !S_IS_DEFINED (fixP
->fx_addsy
)
4614 && !S_IS_WEAK (fixP
->fx_addsy
))
4615 S_SET_WEAK (fixP
->fx_addsy
);
4620 #ifdef BFD_ASSEMBLER
4621 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4622 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4626 switch (fixP
->fx_size
)
4628 /* The cast to offsetT below are necessary to make code
4629 correct for machines where ints are smaller than offsetT. */
4633 lower_limit
= - (offsetT
) 0x80;
4636 *buf
++ = (val
>> 8);
4638 upper_limit
= 0x7fff;
4639 lower_limit
= - (offsetT
) 0x8000;
4642 *buf
++ = (val
>> 24);
4643 *buf
++ = (val
>> 16);
4644 *buf
++ = (val
>> 8);
4646 upper_limit
= 0x7fffffff;
4647 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4650 BAD_CASE (fixP
->fx_size
);
4653 /* Fix up a negative reloc. */
4654 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4656 fixP
->fx_addsy
= fixP
->fx_subsy
;
4657 fixP
->fx_subsy
= NULL
;
4661 /* For non-pc-relative values, it's conceivable we might get something
4662 like "0xff" for a byte field. So extend the upper part of the range
4663 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4664 so that we can do any range checking at all. */
4665 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4666 upper_limit
= upper_limit
* 2 + 1;
4668 if ((addressT
) val
> upper_limit
4669 && (val
> 0 || val
< lower_limit
))
4670 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("value out of range"));
4672 /* A one byte PC-relative reloc means a short branch. We can't use
4673 a short branch with a value of 0 or -1, because those indicate
4674 different opcodes (branches with longer offsets). fixup_segment
4675 in write.c may have clobbered fx_pcrel, so we need to examine the
4678 #ifdef BFD_ASSEMBLER
4679 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
4682 && fixP
->fx_size
== 1
4683 && (fixP
->fx_addsy
== NULL
4684 || S_IS_DEFINED (fixP
->fx_addsy
))
4685 && (val
== 0 || val
== -1))
4686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("invalid byte branch offset"));
4689 /* *fragP has been relaxed to its final size, and now needs to have
4690 the bytes inside it modified to conform to the new size There is UGLY
4694 md_convert_frag_1 (fragS
*fragP
)
4699 /* Address in object code of the displacement. */
4700 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4702 /* Address in gas core of the place to store the displacement. */
4703 /* This convinces the native rs6000 compiler to generate the code we
4705 register char *buffer_address
= fragP
->fr_literal
;
4706 buffer_address
+= fragP
->fr_fix
;
4707 /* End ibm compiler workaround. */
4709 /* The displacement of the address, from current location. */
4710 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4711 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4713 switch (fragP
->fr_subtype
)
4715 case TAB (BRANCHBWL
, BYTE
):
4716 case TAB (BRABSJUNC
, BYTE
):
4717 case TAB (BRABSJCOND
, BYTE
):
4718 case TAB (BRANCHBW
, BYTE
):
4719 know (issbyte (disp
));
4721 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4722 _("short branch with zero offset: use :w"));
4723 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4724 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4725 fixP
->fx_pcrel_adjust
= -1;
4727 case TAB (BRANCHBWL
, SHORT
):
4728 case TAB (BRABSJUNC
, SHORT
):
4729 case TAB (BRABSJCOND
, SHORT
):
4730 case TAB (BRANCHBW
, SHORT
):
4731 fragP
->fr_opcode
[1] = 0x00;
4732 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4733 1, RELAX_RELOC_PC16
);
4736 case TAB (BRANCHBWL
, LONG
):
4737 fragP
->fr_opcode
[1] = (char) 0xFF;
4738 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4739 1, RELAX_RELOC_PC32
);
4742 case TAB (BRABSJUNC
, LONG
):
4743 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
4745 if (flag_keep_pcrel
)
4746 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4747 fragP
->fr_opcode
[0] = 0x4E;
4748 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4749 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4750 0, RELAX_RELOC_ABS32
);
4753 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
4755 if (flag_keep_pcrel
)
4756 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4757 fragP
->fr_opcode
[0] = 0x4E;
4758 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4759 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4760 0, RELAX_RELOC_ABS32
);
4765 /* This cannot happen, because jbsr and jbra are the only two
4766 unconditional branches. */
4770 case TAB (BRABSJCOND
, LONG
):
4771 if (flag_keep_pcrel
)
4772 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4774 /* Only Bcc 68000 instructions can come here
4775 Change bcc into b!cc/jmp absl long. */
4776 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
4777 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
4779 /* JF: these used to be fr_opcode[2,3], but they may be in a
4780 different frag, in which case referring to them is a no-no.
4781 Only fr_opcode[0,1] are guaranteed to work. */
4782 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4783 *buffer_address
++ = (char) 0xf9;
4784 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
4785 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4786 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4789 case TAB (FBRANCH
, SHORT
):
4790 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4791 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4792 1, RELAX_RELOC_PC16
);
4795 case TAB (FBRANCH
, LONG
):
4796 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
4797 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4798 1, RELAX_RELOC_PC32
);
4801 case TAB (DBCCLBR
, SHORT
):
4802 case TAB (DBCCABSJ
, SHORT
):
4803 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4804 1, RELAX_RELOC_PC16
);
4807 case TAB (DBCCLBR
, LONG
):
4808 /* Only DBcc instructions can come here.
4809 Change dbcc into dbcc/bral.
4810 JF: these used to be fr_opcode[2-7], but that's wrong. */
4811 if (flag_keep_pcrel
)
4812 as_fatal (_("Tried to convert DBcc to absolute jump"));
4814 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4815 *buffer_address
++ = 0x04;
4816 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
4817 *buffer_address
++ = 0x06;
4818 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
4819 *buffer_address
++ = (char) 0xff;
4821 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4822 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 1,
4826 case TAB (DBCCABSJ
, LONG
):
4827 /* Only DBcc instructions can come here.
4828 Change dbcc into dbcc/jmp.
4829 JF: these used to be fr_opcode[2-7], but that's wrong. */
4830 if (flag_keep_pcrel
)
4831 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4833 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4834 *buffer_address
++ = 0x04;
4835 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
4836 *buffer_address
++ = 0x06;
4837 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
4838 *buffer_address
++ = (char) 0xf9;
4840 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4841 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 0,
4845 case TAB (PCREL1632
, SHORT
):
4846 fragP
->fr_opcode
[1] &= ~0x3F;
4847 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
4848 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4849 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4852 case TAB (PCREL1632
, LONG
):
4853 /* Already set to mode 7.3; this indicates: PC indirect with
4854 suppressed index, 32-bit displacement. */
4855 *buffer_address
++ = 0x01;
4856 *buffer_address
++ = 0x70;
4858 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4859 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4860 fixP
->fx_pcrel_adjust
= 2;
4863 case TAB (PCINDEX
, BYTE
):
4864 assert (fragP
->fr_fix
>= 2);
4865 buffer_address
[-2] &= ~1;
4866 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4867 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4868 fixP
->fx_pcrel_adjust
= 1;
4870 case TAB (PCINDEX
, SHORT
):
4871 assert (fragP
->fr_fix
>= 2);
4872 buffer_address
[-2] |= 0x1;
4873 buffer_address
[-1] = 0x20;
4874 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4875 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4876 fixP
->fx_pcrel_adjust
= 2;
4879 case TAB (PCINDEX
, LONG
):
4880 assert (fragP
->fr_fix
>= 2);
4881 buffer_address
[-2] |= 0x1;
4882 buffer_address
[-1] = 0x30;
4883 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4884 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4885 fixP
->fx_pcrel_adjust
= 2;
4888 case TAB (ABSTOPCREL
, SHORT
):
4889 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4890 1, RELAX_RELOC_PC16
);
4893 case TAB (ABSTOPCREL
, LONG
):
4894 if (flag_keep_pcrel
)
4895 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4896 /* The thing to do here is force it to ABSOLUTE LONG, since
4897 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4898 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4900 fragP
->fr_opcode
[1] &= ~0x3F;
4901 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4902 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4903 0, RELAX_RELOC_ABS32
);
4909 #ifndef BFD_ASSEMBLER
4912 md_convert_frag (object_headers
*headers ATTRIBUTE_UNUSED
,
4913 segT sec ATTRIBUTE_UNUSED
,
4916 md_convert_frag_1 (fragP
);
4922 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
4923 segT sec ATTRIBUTE_UNUSED
,
4926 md_convert_frag_1 (fragP
);
4930 /* Force truly undefined symbols to their maximum size, and generally set up
4931 the frag list to be relaxed
4934 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
4936 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4937 switch (fragP
->fr_subtype
)
4939 case TAB (BRANCHBWL
, SZ_UNDEF
):
4940 case TAB (BRABSJUNC
, SZ_UNDEF
):
4941 case TAB (BRABSJCOND
, SZ_UNDEF
):
4943 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4944 && relaxable_symbol (fragP
->fr_symbol
))
4946 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4948 else if (flag_short_refs
)
4950 /* Symbol is undefined and we want short ref. */
4951 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4955 /* Symbol is still undefined. Make it LONG. */
4956 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4961 case TAB (BRANCHBW
, SZ_UNDEF
):
4963 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4964 && relaxable_symbol (fragP
->fr_symbol
))
4966 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4970 /* Symbol is undefined and we don't have long branches. */
4971 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4976 case TAB (FBRANCH
, SZ_UNDEF
):
4977 case TAB (DBCCLBR
, SZ_UNDEF
):
4978 case TAB (DBCCABSJ
, SZ_UNDEF
):
4979 case TAB (PCREL1632
, SZ_UNDEF
):
4981 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4982 && relaxable_symbol (fragP
->fr_symbol
))
4985 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4989 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4994 case TAB (PCINDEX
, SZ_UNDEF
):
4995 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4996 && relaxable_symbol (fragP
->fr_symbol
)))
4998 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
5002 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
5006 case TAB (ABSTOPCREL
, SZ_UNDEF
):
5008 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5009 && relaxable_symbol (fragP
->fr_symbol
)))
5011 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
5015 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
5024 /* Now that SZ_UNDEF are taken care of, check others. */
5025 switch (fragP
->fr_subtype
)
5027 case TAB (BRANCHBWL
, BYTE
):
5028 case TAB (BRABSJUNC
, BYTE
):
5029 case TAB (BRABSJCOND
, BYTE
):
5030 case TAB (BRANCHBW
, BYTE
):
5031 /* We can't do a short jump to the next instruction, so in that
5032 case we force word mode. If the symbol is at the start of a
5033 frag, and it is the next frag with any data in it (usually
5034 this is just the next frag, but assembler listings may
5035 introduce empty frags), we must use word mode. */
5036 if (fragP
->fr_symbol
)
5040 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
5041 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
5045 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
5049 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5056 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5059 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5060 /* the bit-field entries in the relocation_info struct plays hell
5061 with the byte-order problems of cross-assembly. So as a hack,
5062 I added this mach. dependent ri twiddler. Ugly, but it gets
5064 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5065 are symbolnum, most sig. byte first. Last byte is broken up with
5066 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5067 nibble as nuthin. (on Sun 3 at least) */
5068 /* Translate the internal relocation information into target-specific
5072 md_ri_to_chars (char *the_bytes
, struct reloc_info_generic
*ri
)
5075 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
5076 /* Now the fun stuff. */
5077 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
5078 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
5079 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
5080 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80)
5081 | ((ri
->r_length
<< 5) & 0x60)
5082 | ((ri
->r_extern
<< 4) & 0x10));
5087 #ifndef BFD_ASSEMBLER
5089 tc_aout_fix_to_chars (char *where
, fixS
*fixP
,
5090 relax_addressT segment_address_in_file
)
5093 * In: length of relocation (or of address) in chars: 1, 2 or 4.
5094 * Out: GNU LD relocation length code: 0, 1, or 2.
5097 static const unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
5100 know (fixP
->fx_addsy
!= NULL
);
5102 md_number_to_chars (where
,
5103 (fixP
->fx_frag
->fr_address
5104 + fixP
->fx_where
- segment_address_in_file
), 4);
5106 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
5107 ? S_GET_TYPE (fixP
->fx_addsy
)
5108 : fixP
->fx_addsy
->sy_number
);
5110 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
5111 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
5112 where
[6] = r_symbolnum
& 0x0ff;
5113 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80)
5114 | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60)
5115 | ((!S_IS_DEFINED (fixP
->fx_addsy
) << 4) & 0x10));
5119 #endif /* OBJ_AOUT or OBJ_BOUT */
5121 #ifndef WORKING_DOT_WORD
5122 const int md_short_jump_size
= 4;
5123 const int md_long_jump_size
= 6;
5126 md_create_short_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5127 fragS
*frag ATTRIBUTE_UNUSED
,
5128 symbolS
*to_symbol ATTRIBUTE_UNUSED
)
5132 offset
= to_addr
- (from_addr
+ 2);
5134 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5135 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5139 md_create_long_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5140 fragS
*frag
, symbolS
*to_symbol
)
5144 if (!HAVE_LONG_BRANCH (current_architecture
))
5146 if (flag_keep_pcrel
)
5147 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5148 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5149 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5150 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5151 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5156 offset
= to_addr
- (from_addr
+ 2);
5157 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5158 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5164 /* Different values of OK tell what its OK to return. Things that
5165 aren't OK are an error (what a shock, no?)
5168 10: Absolute 1:8 only
5169 20: Absolute 0:7 only
5170 30: absolute 0:15 only
5171 40: Absolute 0:31 only
5172 50: absolute 0:127 only
5173 55: absolute -64:63 only
5174 60: absolute -128:127 only
5175 70: absolute 0:4095 only
5176 80: absolute -1, 1:7 only
5180 get_num (struct m68k_exp
*exp
, int ok
)
5182 if (exp
->exp
.X_op
== O_absent
)
5184 /* Do the same thing the VAX asm does. */
5185 op (exp
) = O_constant
;
5191 as_warn (_("expression out of range: defaulting to 1"));
5195 else if (exp
->exp
.X_op
== O_constant
)
5200 if (offs (exp
) < 1 || offs (exp
) > 8)
5202 as_warn (_("expression out of range: defaulting to 1"));
5207 if (offs (exp
) < 0 || offs (exp
) > 7)
5211 if (offs (exp
) < 0 || offs (exp
) > 15)
5215 if (offs (exp
) < 0 || offs (exp
) > 32)
5219 if (offs (exp
) < 0 || offs (exp
) > 127)
5223 if (offs (exp
) < -64 || offs (exp
) > 63)
5227 if (offs (exp
) < -128 || offs (exp
) > 127)
5231 if (offs (exp
) < 0 || offs (exp
) > 4095)
5234 as_warn (_("expression out of range: defaulting to 0"));
5243 as_warn (_("expression out of range: defaulting to 1"));
5251 else if (exp
->exp
.X_op
== O_big
)
5253 if (offs (exp
) <= 0 /* flonum. */
5254 && (ok
== 90 /* no bignums */
5255 || (ok
> 10 /* Small-int ranges including 0 ok. */
5256 /* If we have a flonum zero, a zero integer should
5257 do as well (e.g., in moveq). */
5258 && generic_floating_point_number
.exponent
== 0
5259 && generic_floating_point_number
.low
[0] == 0)))
5261 /* HACK! Turn it into a long. */
5262 LITTLENUM_TYPE words
[6];
5264 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5265 op (exp
) = O_constant
;
5268 offs (exp
) = words
[1] | (words
[0] << 16);
5272 op (exp
) = O_constant
;
5275 offs (exp
) = (ok
== 10) ? 1 : 0;
5276 as_warn (_("Can't deal with expression; defaulting to %ld"),
5282 if (ok
>= 10 && ok
<= 80)
5284 op (exp
) = O_constant
;
5287 offs (exp
) = (ok
== 10) ? 1 : 0;
5288 as_warn (_("Can't deal with expression; defaulting to %ld"),
5293 if (exp
->size
!= SIZE_UNSPEC
)
5301 if (!isbyte (offs (exp
)))
5302 as_warn (_("expression doesn't fit in BYTE"));
5305 if (!isword (offs (exp
)))
5306 as_warn (_("expression doesn't fit in WORD"));
5314 /* These are the back-ends for the various machine dependent pseudo-ops. */
5317 s_data1 (int ignore ATTRIBUTE_UNUSED
)
5319 subseg_set (data_section
, 1);
5320 demand_empty_rest_of_line ();
5324 s_data2 (int ignore ATTRIBUTE_UNUSED
)
5326 subseg_set (data_section
, 2);
5327 demand_empty_rest_of_line ();
5331 s_bss (int ignore ATTRIBUTE_UNUSED
)
5333 /* We don't support putting frags in the BSS segment, we fake it
5334 by marking in_bss, then looking at s_skip for clues. */
5336 subseg_set (bss_section
, 0);
5337 demand_empty_rest_of_line ();
5341 s_even (int ignore ATTRIBUTE_UNUSED
)
5344 register long temp_fill
;
5346 temp
= 1; /* JF should be 2? */
5347 temp_fill
= get_absolute_expression ();
5348 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5349 frag_align (temp
, (int) temp_fill
, 0);
5350 demand_empty_rest_of_line ();
5351 record_alignment (now_seg
, temp
);
5355 s_proc (int ignore ATTRIBUTE_UNUSED
)
5357 demand_empty_rest_of_line ();
5360 /* Pseudo-ops handled for MRI compatibility. */
5362 /* This function returns non-zero if the argument is a conditional
5363 pseudo-op. This is called when checking whether a pending
5364 alignment is needed. */
5367 m68k_conditional_pseudoop (pseudo_typeS
*pop
)
5369 return (pop
->poc_handler
== s_mri_if
5370 || pop
->poc_handler
== s_mri_else
);
5373 /* Handle an MRI style chip specification. */
5382 s
= input_line_pointer
;
5383 /* We can't use get_symbol_end since the processor names are not proper
5385 while (is_part_of_name (c
= *input_line_pointer
++))
5387 *--input_line_pointer
= 0;
5388 for (i
= 0; i
< n_archs
; i
++)
5389 if (strcasecmp (s
, archs
[i
].name
) == 0)
5393 as_bad (_("%s: unrecognized processor name"), s
);
5394 *input_line_pointer
= c
;
5395 ignore_rest_of_line ();
5398 *input_line_pointer
= c
;
5400 if (*input_line_pointer
== '/')
5401 current_architecture
= 0;
5403 current_architecture
&= m68881
| m68851
;
5404 current_architecture
|= archs
[i
].arch
;
5405 current_chip
= archs
[i
].chip
;
5407 while (*input_line_pointer
== '/')
5409 ++input_line_pointer
;
5410 s
= input_line_pointer
;
5411 /* We can't use get_symbol_end since the processor names are not
5413 while (is_part_of_name (c
= *input_line_pointer
++))
5415 *--input_line_pointer
= 0;
5416 if (strcmp (s
, "68881") == 0)
5417 current_architecture
|= m68881
;
5418 else if (strcmp (s
, "68851") == 0)
5419 current_architecture
|= m68851
;
5420 *input_line_pointer
= c
;
5423 /* Update info about available control registers. */
5424 select_control_regs ();
5427 /* The MRI CHIP pseudo-op. */
5430 s_chip (int ignore ATTRIBUTE_UNUSED
)
5436 stop
= mri_comment_field (&stopc
);
5439 mri_comment_end (stop
, stopc
);
5440 demand_empty_rest_of_line ();
5443 /* The MRI FOPT pseudo-op. */
5446 s_fopt (int ignore ATTRIBUTE_UNUSED
)
5450 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5454 input_line_pointer
+= 3;
5455 temp
= get_absolute_expression ();
5456 if (temp
< 0 || temp
> 7)
5457 as_bad (_("bad coprocessor id"));
5459 m68k_float_copnum
= COP0
+ temp
;
5463 as_bad (_("unrecognized fopt option"));
5464 ignore_rest_of_line ();
5468 demand_empty_rest_of_line ();
5471 /* The structure used to handle the MRI OPT pseudo-op. */
5475 /* The name of the option. */
5478 /* If this is not NULL, just call this function. The first argument
5479 is the ARG field of this structure, the second argument is
5480 whether the option was negated. */
5481 void (*pfn
) (int arg
, int on
);
5483 /* If this is not NULL, and the PFN field is NULL, set the variable
5484 this points to. Set it to the ARG field if the option was not
5485 negated, and the NOTARG field otherwise. */
5488 /* The value to pass to PFN or to assign to *PVAR. */
5491 /* The value to assign to *PVAR if the option is negated. If PFN is
5492 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5493 the option may not be negated. */
5497 /* The table used to handle the MRI OPT pseudo-op. */
5499 static void skip_to_comma (int, int);
5500 static void opt_nest (int, int);
5501 static void opt_chip (int, int);
5502 static void opt_list (int, int);
5503 static void opt_list_symbols (int, int);
5505 static const struct opt_action opt_table
[] =
5507 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5509 /* We do relaxing, so there is little use for these options. */
5510 { "b", 0, 0, 0, 0 },
5511 { "brs", 0, 0, 0, 0 },
5512 { "brb", 0, 0, 0, 0 },
5513 { "brl", 0, 0, 0, 0 },
5514 { "brw", 0, 0, 0, 0 },
5516 { "c", 0, 0, 0, 0 },
5517 { "cex", 0, 0, 0, 0 },
5518 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5519 { "cl", 0, 0, 0, 0 },
5520 { "cre", 0, 0, 0, 0 },
5521 { "d", 0, &flag_keep_locals
, 1, 0 },
5522 { "e", 0, 0, 0, 0 },
5523 { "f", 0, &flag_short_refs
, 1, 0 },
5524 { "frs", 0, &flag_short_refs
, 1, 0 },
5525 { "frl", 0, &flag_short_refs
, 0, 1 },
5526 { "g", 0, 0, 0, 0 },
5527 { "i", 0, 0, 0, 0 },
5528 { "m", 0, 0, 0, 0 },
5529 { "mex", 0, 0, 0, 0 },
5530 { "mc", 0, 0, 0, 0 },
5531 { "md", 0, 0, 0, 0 },
5532 { "nest", opt_nest
, 0, 0, 0 },
5533 { "next", skip_to_comma
, 0, 0, 0 },
5534 { "o", 0, 0, 0, 0 },
5535 { "old", 0, 0, 0, 0 },
5536 { "op", skip_to_comma
, 0, 0, 0 },
5537 { "pco", 0, 0, 0, 0 },
5538 { "p", opt_chip
, 0, 0, 0 },
5539 { "pcr", 0, 0, 0, 0 },
5540 { "pcs", 0, 0, 0, 0 },
5541 { "r", 0, 0, 0, 0 },
5542 { "quick", 0, &m68k_quick
, 1, 0 },
5543 { "rel32", 0, &m68k_rel32
, 1, 0 },
5544 { "s", opt_list
, 0, 0, 0 },
5545 { "t", opt_list_symbols
, 0, 0, 0 },
5546 { "w", 0, &flag_no_warnings
, 0, 1 },
5550 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5552 /* The MRI OPT pseudo-op. */
5555 s_opt (int ignore ATTRIBUTE_UNUSED
)
5563 const struct opt_action
*o
;
5568 if (*input_line_pointer
== '-')
5570 ++input_line_pointer
;
5573 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5575 input_line_pointer
+= 2;
5579 s
= input_line_pointer
;
5580 c
= get_symbol_end ();
5582 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5584 if (strcasecmp (s
, o
->name
) == 0)
5588 /* Restore input_line_pointer now in case the option
5590 *input_line_pointer
= c
;
5591 (*o
->pfn
) (o
->arg
, t
);
5593 else if (o
->pvar
!= NULL
)
5595 if (! t
&& o
->arg
== o
->notarg
)
5596 as_bad (_("option `%s' may not be negated"), s
);
5597 *input_line_pointer
= c
;
5598 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5601 *input_line_pointer
= c
;
5607 as_bad (_("option `%s' not recognized"), s
);
5608 *input_line_pointer
= c
;
5611 while (*input_line_pointer
++ == ',');
5613 /* Move back to terminating character. */
5614 --input_line_pointer
;
5615 demand_empty_rest_of_line ();
5618 /* Skip ahead to a comma. This is used for OPT options which we do
5619 not support and which take arguments. */
5622 skip_to_comma (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5624 while (*input_line_pointer
!= ','
5625 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5626 ++input_line_pointer
;
5629 /* Handle the OPT NEST=depth option. */
5632 opt_nest (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5634 if (*input_line_pointer
!= '=')
5636 as_bad (_("bad format of OPT NEST=depth"));
5640 ++input_line_pointer
;
5641 max_macro_nest
= get_absolute_expression ();
5644 /* Handle the OPT P=chip option. */
5647 opt_chip (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5649 if (*input_line_pointer
!= '=')
5651 /* This is just OPT P, which we do not support. */
5655 ++input_line_pointer
;
5659 /* Handle the OPT S option. */
5662 opt_list (int arg ATTRIBUTE_UNUSED
, int on
)
5667 /* Handle the OPT T option. */
5670 opt_list_symbols (int arg ATTRIBUTE_UNUSED
, int on
)
5673 listing
|= LISTING_SYMBOLS
;
5675 listing
&= ~LISTING_SYMBOLS
;
5678 /* Handle the MRI REG pseudo-op. */
5681 s_reg (int ignore ATTRIBUTE_UNUSED
)
5690 if (line_label
== NULL
)
5692 as_bad (_("missing label"));
5693 ignore_rest_of_line ();
5698 stop
= mri_comment_field (&stopc
);
5702 s
= input_line_pointer
;
5703 while (ISALNUM (*input_line_pointer
)
5704 #ifdef REGISTER_PREFIX
5705 || *input_line_pointer
== REGISTER_PREFIX
5707 || *input_line_pointer
== '/'
5708 || *input_line_pointer
== '-')
5709 ++input_line_pointer
;
5710 c
= *input_line_pointer
;
5711 *input_line_pointer
= '\0';
5713 if (m68k_ip_op (s
, &rop
) != 0)
5715 if (rop
.error
== NULL
)
5716 as_bad (_("bad register list"));
5718 as_bad (_("bad register list: %s"), rop
.error
);
5719 *input_line_pointer
= c
;
5720 ignore_rest_of_line ();
5724 *input_line_pointer
= c
;
5726 if (rop
.mode
== REGLST
)
5728 else if (rop
.mode
== DREG
)
5729 mask
= 1 << (rop
.reg
- DATA0
);
5730 else if (rop
.mode
== AREG
)
5731 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5732 else if (rop
.mode
== FPREG
)
5733 mask
= 1 << (rop
.reg
- FP0
+ 16);
5734 else if (rop
.mode
== CONTROL
5737 else if (rop
.mode
== CONTROL
5740 else if (rop
.mode
== CONTROL
5745 as_bad (_("bad register list"));
5746 ignore_rest_of_line ();
5750 S_SET_SEGMENT (line_label
, reg_section
);
5751 S_SET_VALUE (line_label
, ~mask
);
5752 symbol_set_frag (line_label
, &zero_address_frag
);
5755 mri_comment_end (stop
, stopc
);
5757 demand_empty_rest_of_line ();
5760 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5764 struct save_opts
*next
;
5766 int symbols_case_sensitive
;
5775 /* FIXME: We don't save OPT S. */
5778 /* This variable holds the stack of saved options. */
5780 static struct save_opts
*save_stack
;
5782 /* The MRI SAVE pseudo-op. */
5785 s_save (int ignore ATTRIBUTE_UNUSED
)
5787 struct save_opts
*s
;
5789 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
5790 s
->abspcadd
= m68k_abspcadd
;
5791 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5792 s
->keep_locals
= flag_keep_locals
;
5793 s
->short_refs
= flag_short_refs
;
5794 s
->architecture
= current_architecture
;
5795 s
->chip
= current_chip
;
5796 s
->quick
= m68k_quick
;
5797 s
->rel32
= m68k_rel32
;
5798 s
->listing
= listing
;
5799 s
->no_warnings
= flag_no_warnings
;
5801 s
->next
= save_stack
;
5804 demand_empty_rest_of_line ();
5807 /* The MRI RESTORE pseudo-op. */
5810 s_restore (int ignore ATTRIBUTE_UNUSED
)
5812 struct save_opts
*s
;
5814 if (save_stack
== NULL
)
5816 as_bad (_("restore without save"));
5817 ignore_rest_of_line ();
5822 save_stack
= s
->next
;
5824 m68k_abspcadd
= s
->abspcadd
;
5825 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5826 flag_keep_locals
= s
->keep_locals
;
5827 flag_short_refs
= s
->short_refs
;
5828 current_architecture
= s
->architecture
;
5829 current_chip
= s
->chip
;
5830 m68k_quick
= s
->quick
;
5831 m68k_rel32
= s
->rel32
;
5832 listing
= s
->listing
;
5833 flag_no_warnings
= s
->no_warnings
;
5837 demand_empty_rest_of_line ();
5840 /* Types of MRI structured control directives. */
5842 enum mri_control_type
5850 /* This structure is used to stack the MRI structured control
5853 struct mri_control_info
5855 /* The directive within which this one is enclosed. */
5856 struct mri_control_info
*outer
;
5858 /* The type of directive. */
5859 enum mri_control_type type
;
5861 /* Whether an ELSE has been in an IF. */
5864 /* The add or sub statement at the end of a FOR. */
5867 /* The label of the top of a FOR or REPEAT loop. */
5870 /* The label to jump to for the next iteration, or the else
5871 expression of a conditional. */
5874 /* The label to jump to to break out of the loop, or the label past
5875 the end of a conditional. */
5879 /* The stack of MRI structured control directives. */
5881 static struct mri_control_info
*mri_control_stack
;
5883 /* The current MRI structured control directive index number, used to
5884 generate label names. */
5886 static int mri_control_index
;
5888 /* Assemble an instruction for an MRI structured control directive. */
5891 mri_assemble (char *str
)
5895 /* md_assemble expects the opcode to be in lower case. */
5896 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
5902 /* Generate a new MRI label structured control directive label name. */
5905 mri_control_label (void)
5909 n
= (char *) xmalloc (20);
5910 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
5911 ++mri_control_index
;
5915 /* Create a new MRI structured control directive. */
5917 static struct mri_control_info
*
5918 push_mri_control (enum mri_control_type type
)
5920 struct mri_control_info
*n
;
5922 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
5926 if (type
== mri_if
|| type
== mri_while
)
5929 n
->top
= mri_control_label ();
5930 n
->next
= mri_control_label ();
5931 n
->bottom
= mri_control_label ();
5933 n
->outer
= mri_control_stack
;
5934 mri_control_stack
= n
;
5939 /* Pop off the stack of MRI structured control directives. */
5942 pop_mri_control (void)
5944 struct mri_control_info
*n
;
5946 n
= mri_control_stack
;
5947 mri_control_stack
= n
->outer
;
5955 /* Recognize a condition code in an MRI structured control expression. */
5958 parse_mri_condition (int *pcc
)
5962 know (*input_line_pointer
== '<');
5964 ++input_line_pointer
;
5965 c1
= *input_line_pointer
++;
5966 c2
= *input_line_pointer
++;
5968 if (*input_line_pointer
!= '>')
5970 as_bad (_("syntax error in structured control directive"));
5974 ++input_line_pointer
;
5980 *pcc
= (c1
<< 8) | c2
;
5985 /* Parse a single operand in an MRI structured control expression. */
5988 parse_mri_control_operand (int *pcc
, char **leftstart
, char **leftstop
,
5989 char **rightstart
, char **rightstop
)
6001 if (*input_line_pointer
== '<')
6003 /* It's just a condition code. */
6004 return parse_mri_condition (pcc
);
6007 /* Look ahead for the condition code. */
6008 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6010 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
6015 as_bad (_("missing condition code in structured control directive"));
6019 *leftstart
= input_line_pointer
;
6021 if (*leftstop
> *leftstart
6022 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
6025 input_line_pointer
= s
;
6026 if (! parse_mri_condition (pcc
))
6029 /* Look ahead for AND or OR or end of line. */
6030 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6032 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6033 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6035 if ((s
== input_line_pointer
6038 && ((strncasecmp (s
, "AND", 3) == 0
6039 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
6040 || (strncasecmp (s
, "OR", 2) == 0
6041 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
6045 *rightstart
= input_line_pointer
;
6047 if (*rightstop
> *rightstart
6048 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
6051 input_line_pointer
= s
;
6056 #define MCC(b1, b2) (((b1) << 8) | (b2))
6058 /* Swap the sense of a condition. This changes the condition so that
6059 it generates the same result when the operands are swapped. */
6062 swap_mri_condition (int cc
)
6066 case MCC ('h', 'i'): return MCC ('c', 's');
6067 case MCC ('l', 's'): return MCC ('c', 'c');
6068 /* <HS> is an alias for <CC>. */
6069 case MCC ('h', 's'):
6070 case MCC ('c', 'c'): return MCC ('l', 's');
6071 /* <LO> is an alias for <CS>. */
6072 case MCC ('l', 'o'):
6073 case MCC ('c', 's'): return MCC ('h', 'i');
6074 case MCC ('p', 'l'): return MCC ('m', 'i');
6075 case MCC ('m', 'i'): return MCC ('p', 'l');
6076 case MCC ('g', 'e'): return MCC ('l', 'e');
6077 case MCC ('l', 't'): return MCC ('g', 't');
6078 case MCC ('g', 't'): return MCC ('l', 't');
6079 case MCC ('l', 'e'): return MCC ('g', 'e');
6080 /* Issue a warning for conditions we can not swap. */
6081 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6082 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6083 case MCC ('v', 'c'):
6084 case MCC ('v', 's'):
6086 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6087 (char) (cc
>> 8), (char) (cc
));
6093 /* Reverse the sense of a condition. */
6096 reverse_mri_condition (int cc
)
6100 case MCC ('h', 'i'): return MCC ('l', 's');
6101 case MCC ('l', 's'): return MCC ('h', 'i');
6102 /* <HS> is an alias for <CC> */
6103 case MCC ('h', 's'): return MCC ('l', 'o');
6104 case MCC ('c', 'c'): return MCC ('c', 's');
6105 /* <LO> is an alias for <CS> */
6106 case MCC ('l', 'o'): return MCC ('h', 's');
6107 case MCC ('c', 's'): return MCC ('c', 'c');
6108 case MCC ('n', 'e'): return MCC ('e', 'q');
6109 case MCC ('e', 'q'): return MCC ('n', 'e');
6110 case MCC ('v', 'c'): return MCC ('v', 's');
6111 case MCC ('v', 's'): return MCC ('v', 'c');
6112 case MCC ('p', 'l'): return MCC ('m', 'i');
6113 case MCC ('m', 'i'): return MCC ('p', 'l');
6114 case MCC ('g', 'e'): return MCC ('l', 't');
6115 case MCC ('l', 't'): return MCC ('g', 'e');
6116 case MCC ('g', 't'): return MCC ('l', 'e');
6117 case MCC ('l', 'e'): return MCC ('g', 't');
6122 /* Build an MRI structured control expression. This generates test
6123 and branch instructions. It goes to TRUELAB if the condition is
6124 true, and to FALSELAB if the condition is false. Exactly one of
6125 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6126 is the size qualifier for the expression. EXTENT is the size to
6127 use for the branch. */
6130 build_mri_control_operand (int qual
, int cc
, char *leftstart
, char *leftstop
,
6131 char *rightstart
, char *rightstop
,
6132 const char *truelab
, const char *falselab
,
6138 if (leftstart
!= NULL
)
6140 struct m68k_op leftop
, rightop
;
6143 /* Swap the compare operands, if necessary, to produce a legal
6144 m68k compare instruction. Comparing a register operand with
6145 a non-register operand requires the register to be on the
6146 right (cmp, cmpa). Comparing an immediate value with
6147 anything requires the immediate value to be on the left
6152 (void) m68k_ip_op (leftstart
, &leftop
);
6157 (void) m68k_ip_op (rightstart
, &rightop
);
6160 if (rightop
.mode
== IMMED
6161 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6162 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6166 /* Correct conditional handling:
6167 if #1 <lt> d0 then ;means if (1 < d0)
6173 cmp #1,d0 if we do *not* swap the operands
6174 bgt true we need the swapped condition!
6181 leftstart
= rightstart
;
6184 leftstop
= rightstop
;
6189 cc
= swap_mri_condition (cc
);
6193 if (truelab
== NULL
)
6195 cc
= reverse_mri_condition (cc
);
6199 if (leftstart
!= NULL
)
6201 buf
= (char *) xmalloc (20
6202 + (leftstop
- leftstart
)
6203 + (rightstop
- rightstart
));
6209 *s
++ = TOLOWER (qual
);
6211 memcpy (s
, leftstart
, leftstop
- leftstart
);
6212 s
+= leftstop
- leftstart
;
6214 memcpy (s
, rightstart
, rightstop
- rightstart
);
6215 s
+= rightstop
- rightstart
;
6221 buf
= (char *) xmalloc (20 + strlen (truelab
));
6227 *s
++ = TOLOWER (extent
);
6229 strcpy (s
, truelab
);
6234 /* Parse an MRI structured control expression. This generates test
6235 and branch instructions. STOP is where the expression ends. It
6236 goes to TRUELAB if the condition is true, and to FALSELAB if the
6237 condition is false. Exactly one of TRUELAB and FALSELAB will be
6238 NULL, meaning to fall through. QUAL is the size qualifier for the
6239 expression. EXTENT is the size to use for the branch. */
6242 parse_mri_control_expression (char *stop
, int qual
, const char *truelab
,
6243 const char *falselab
, int extent
)
6255 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6256 &rightstart
, &rightstop
))
6262 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6266 if (falselab
!= NULL
)
6269 flab
= mri_control_label ();
6271 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6272 rightstop
, (const char *) NULL
, flab
, extent
);
6274 input_line_pointer
+= 3;
6275 if (*input_line_pointer
!= '.'
6276 || input_line_pointer
[1] == '\0')
6280 qual
= input_line_pointer
[1];
6281 input_line_pointer
+= 2;
6284 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6285 &rightstart
, &rightstop
))
6291 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6292 rightstop
, truelab
, falselab
, extent
);
6294 if (falselab
== NULL
)
6297 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6301 if (truelab
!= NULL
)
6304 tlab
= mri_control_label ();
6306 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6307 rightstop
, tlab
, (const char *) NULL
, extent
);
6309 input_line_pointer
+= 2;
6310 if (*input_line_pointer
!= '.'
6311 || input_line_pointer
[1] == '\0')
6315 qual
= input_line_pointer
[1];
6316 input_line_pointer
+= 2;
6319 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6320 &rightstart
, &rightstop
))
6326 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6327 rightstop
, truelab
, falselab
, extent
);
6329 if (truelab
== NULL
)
6334 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6335 rightstop
, truelab
, falselab
, extent
);
6339 if (input_line_pointer
!= stop
)
6340 as_bad (_("syntax error in structured control directive"));
6343 /* Handle the MRI IF pseudo-op. This may be a structured control
6344 directive, or it may be a regular assembler conditional, depending
6352 struct mri_control_info
*n
;
6354 /* A structured control directive must end with THEN with an
6355 optional qualifier. */
6356 s
= input_line_pointer
;
6357 /* We only accept '*' as introduction of comments if preceded by white space
6358 or at first column of a line (I think this can't actually happen here?)
6359 This is important when assembling:
6360 if d0 <ne> 12(a0,d0*2) then
6361 if d0 <ne> #CONST*20 then. */
6362 while (! (is_end_of_line
[(unsigned char) *s
]
6365 && (s
== input_line_pointer
6367 || *(s
-1) == '\t'))))
6370 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6373 if (s
- input_line_pointer
> 1
6377 if (s
- input_line_pointer
< 3
6378 || strncasecmp (s
- 3, "THEN", 4) != 0)
6382 as_bad (_("missing then"));
6383 ignore_rest_of_line ();
6387 /* It's a conditional. */
6392 /* Since this might be a conditional if, this pseudo-op will be
6393 called even if we are supported to be ignoring input. Double
6394 check now. Clobber *input_line_pointer so that ignore_input
6395 thinks that this is not a special pseudo-op. */
6396 c
= *input_line_pointer
;
6397 *input_line_pointer
= 0;
6398 if (ignore_input ())
6400 *input_line_pointer
= c
;
6401 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6402 ++input_line_pointer
;
6403 demand_empty_rest_of_line ();
6406 *input_line_pointer
= c
;
6408 n
= push_mri_control (mri_if
);
6410 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6411 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6414 input_line_pointer
= s
+ 3;
6416 input_line_pointer
= s
+ 1;
6420 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6421 ++input_line_pointer
;
6424 demand_empty_rest_of_line ();
6427 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6428 structured IF, associate the ELSE with the IF. Otherwise, assume
6429 it is a conditional else. */
6432 s_mri_else (int qual
)
6439 && (mri_control_stack
== NULL
6440 || mri_control_stack
->type
!= mri_if
6441 || mri_control_stack
->else_seen
))
6447 c
= *input_line_pointer
;
6448 *input_line_pointer
= 0;
6449 if (ignore_input ())
6451 *input_line_pointer
= c
;
6452 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6453 ++input_line_pointer
;
6454 demand_empty_rest_of_line ();
6457 *input_line_pointer
= c
;
6459 if (mri_control_stack
== NULL
6460 || mri_control_stack
->type
!= mri_if
6461 || mri_control_stack
->else_seen
)
6463 as_bad (_("else without matching if"));
6464 ignore_rest_of_line ();
6468 mri_control_stack
->else_seen
= 1;
6470 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6471 q
[0] = TOLOWER (qual
);
6473 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6477 colon (mri_control_stack
->next
);
6481 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6482 ++input_line_pointer
;
6485 demand_empty_rest_of_line ();
6488 /* Handle the MRI ENDI pseudo-op. */
6491 s_mri_endi (int ignore ATTRIBUTE_UNUSED
)
6493 if (mri_control_stack
== NULL
6494 || mri_control_stack
->type
!= mri_if
)
6496 as_bad (_("endi without matching if"));
6497 ignore_rest_of_line ();
6501 /* ignore_input will not return true for ENDI, so we don't need to
6502 worry about checking it again here. */
6504 if (! mri_control_stack
->else_seen
)
6505 colon (mri_control_stack
->next
);
6506 colon (mri_control_stack
->bottom
);
6512 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6513 ++input_line_pointer
;
6516 demand_empty_rest_of_line ();
6519 /* Handle the MRI BREAK pseudo-op. */
6522 s_mri_break (int extent
)
6524 struct mri_control_info
*n
;
6528 n
= mri_control_stack
;
6530 && n
->type
!= mri_for
6531 && n
->type
!= mri_repeat
6532 && n
->type
!= mri_while
)
6536 as_bad (_("break outside of structured loop"));
6537 ignore_rest_of_line ();
6541 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6542 ex
[0] = TOLOWER (extent
);
6544 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6550 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6551 ++input_line_pointer
;
6554 demand_empty_rest_of_line ();
6557 /* Handle the MRI NEXT pseudo-op. */
6560 s_mri_next (int extent
)
6562 struct mri_control_info
*n
;
6566 n
= mri_control_stack
;
6568 && n
->type
!= mri_for
6569 && n
->type
!= mri_repeat
6570 && n
->type
!= mri_while
)
6574 as_bad (_("next outside of structured loop"));
6575 ignore_rest_of_line ();
6579 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6580 ex
[0] = TOLOWER (extent
);
6582 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6588 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6589 ++input_line_pointer
;
6592 demand_empty_rest_of_line ();
6595 /* Handle the MRI FOR pseudo-op. */
6598 s_mri_for (int qual
)
6600 const char *varstart
, *varstop
;
6601 const char *initstart
, *initstop
;
6602 const char *endstart
, *endstop
;
6603 const char *bystart
, *bystop
;
6607 struct mri_control_info
*n
;
6613 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6617 varstart
= input_line_pointer
;
6619 /* Look for the '='. */
6620 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6621 && *input_line_pointer
!= '=')
6622 ++input_line_pointer
;
6623 if (*input_line_pointer
!= '=')
6625 as_bad (_("missing ="));
6626 ignore_rest_of_line ();
6630 varstop
= input_line_pointer
;
6631 if (varstop
> varstart
6632 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6635 ++input_line_pointer
;
6637 initstart
= input_line_pointer
;
6639 /* Look for TO or DOWNTO. */
6642 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6644 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6645 && ! is_part_of_name (input_line_pointer
[2]))
6647 initstop
= input_line_pointer
;
6648 input_line_pointer
+= 2;
6651 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6652 && ! is_part_of_name (input_line_pointer
[6]))
6654 initstop
= input_line_pointer
;
6656 input_line_pointer
+= 6;
6659 ++input_line_pointer
;
6661 if (initstop
== NULL
)
6663 as_bad (_("missing to or downto"));
6664 ignore_rest_of_line ();
6667 if (initstop
> initstart
6668 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6672 endstart
= input_line_pointer
;
6674 /* Look for BY or DO. */
6677 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6679 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6680 && ! is_part_of_name (input_line_pointer
[2]))
6682 endstop
= input_line_pointer
;
6684 input_line_pointer
+= 2;
6687 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6688 && (input_line_pointer
[2] == '.'
6689 || ! is_part_of_name (input_line_pointer
[2])))
6691 endstop
= input_line_pointer
;
6692 input_line_pointer
+= 2;
6695 ++input_line_pointer
;
6697 if (endstop
== NULL
)
6699 as_bad (_("missing do"));
6700 ignore_rest_of_line ();
6703 if (endstop
> endstart
6704 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6710 bystop
= bystart
+ 2;
6715 bystart
= input_line_pointer
;
6719 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6721 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6722 && (input_line_pointer
[2] == '.'
6723 || ! is_part_of_name (input_line_pointer
[2])))
6725 bystop
= input_line_pointer
;
6726 input_line_pointer
+= 2;
6729 ++input_line_pointer
;
6733 as_bad (_("missing do"));
6734 ignore_rest_of_line ();
6737 if (bystop
> bystart
6738 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6742 if (*input_line_pointer
!= '.')
6746 extent
= input_line_pointer
[1];
6747 input_line_pointer
+= 2;
6750 /* We have fully parsed the FOR operands. Now build the loop. */
6751 n
= push_mri_control (mri_for
);
6753 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
6755 /* Move init,var. */
6762 *s
++ = TOLOWER (qual
);
6764 memcpy (s
, initstart
, initstop
- initstart
);
6765 s
+= initstop
- initstart
;
6767 memcpy (s
, varstart
, varstop
- varstart
);
6768 s
+= varstop
- varstart
;
6780 *s
++ = TOLOWER (qual
);
6782 memcpy (s
, endstart
, endstop
- endstart
);
6783 s
+= endstop
- endstart
;
6785 memcpy (s
, varstart
, varstop
- varstart
);
6786 s
+= varstop
- varstart
;
6791 ex
[0] = TOLOWER (extent
);
6794 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6796 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6799 /* Put together the add or sub instruction used by ENDF. */
6807 *s
++ = TOLOWER (qual
);
6809 memcpy (s
, bystart
, bystop
- bystart
);
6810 s
+= bystop
- bystart
;
6812 memcpy (s
, varstart
, varstop
- varstart
);
6813 s
+= varstop
- varstart
;
6819 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6820 ++input_line_pointer
;
6823 demand_empty_rest_of_line ();
6826 /* Handle the MRI ENDF pseudo-op. */
6829 s_mri_endf (int ignore ATTRIBUTE_UNUSED
)
6831 if (mri_control_stack
== NULL
6832 || mri_control_stack
->type
!= mri_for
)
6834 as_bad (_("endf without for"));
6835 ignore_rest_of_line ();
6839 colon (mri_control_stack
->next
);
6841 mri_assemble (mri_control_stack
->incr
);
6843 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
6844 mri_assemble (mri_control_stack
->incr
);
6846 free (mri_control_stack
->incr
);
6848 colon (mri_control_stack
->bottom
);
6854 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6855 ++input_line_pointer
;
6858 demand_empty_rest_of_line ();
6861 /* Handle the MRI REPEAT pseudo-op. */
6864 s_mri_repeat (int ignore ATTRIBUTE_UNUSED
)
6866 struct mri_control_info
*n
;
6868 n
= push_mri_control (mri_repeat
);
6872 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6873 ++input_line_pointer
;
6875 demand_empty_rest_of_line ();
6878 /* Handle the MRI UNTIL pseudo-op. */
6881 s_mri_until (int qual
)
6885 if (mri_control_stack
== NULL
6886 || mri_control_stack
->type
!= mri_repeat
)
6888 as_bad (_("until without repeat"));
6889 ignore_rest_of_line ();
6893 colon (mri_control_stack
->next
);
6895 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
6898 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
6899 mri_control_stack
->top
, '\0');
6901 colon (mri_control_stack
->bottom
);
6903 input_line_pointer
= s
;
6909 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6910 ++input_line_pointer
;
6913 demand_empty_rest_of_line ();
6916 /* Handle the MRI WHILE pseudo-op. */
6919 s_mri_while (int qual
)
6923 struct mri_control_info
*n
;
6925 s
= input_line_pointer
;
6926 /* We only accept '*' as introduction of comments if preceded by white space
6927 or at first column of a line (I think this can't actually happen here?)
6928 This is important when assembling:
6929 while d0 <ne> 12(a0,d0*2) do
6930 while d0 <ne> #CONST*20 do. */
6931 while (! (is_end_of_line
[(unsigned char) *s
]
6934 && (s
== input_line_pointer
6936 || *(s
-1) == '\t'))))
6939 while (*s
== ' ' || *s
== '\t')
6941 if (s
- input_line_pointer
> 1
6944 if (s
- input_line_pointer
< 2
6945 || strncasecmp (s
- 1, "DO", 2) != 0)
6947 as_bad (_("missing do"));
6948 ignore_rest_of_line ();
6952 n
= push_mri_control (mri_while
);
6956 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
6957 s
[1] == '.' ? s
[2] : '\0');
6959 input_line_pointer
= s
+ 1;
6960 if (*input_line_pointer
== '.')
6961 input_line_pointer
+= 2;
6965 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6966 ++input_line_pointer
;
6969 demand_empty_rest_of_line ();
6972 /* Handle the MRI ENDW pseudo-op. */
6975 s_mri_endw (int ignore ATTRIBUTE_UNUSED
)
6979 if (mri_control_stack
== NULL
6980 || mri_control_stack
->type
!= mri_while
)
6982 as_bad (_("endw without while"));
6983 ignore_rest_of_line ();
6987 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
6988 sprintf (buf
, "bra %s", mri_control_stack
->next
);
6992 colon (mri_control_stack
->bottom
);
6998 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6999 ++input_line_pointer
;
7002 demand_empty_rest_of_line ();
7006 Invocation line includes a switch not recognized by the base assembler.
7007 See if it's a processor-specific option. These are:
7009 -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
7010 -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
7011 Select the architecture. Instructions or features not
7012 supported by the selected architecture cause fatal
7013 errors. More than one may be specified. The default is
7014 -m68020 -m68851 -m68881. Note that -m68008 is a synonym
7015 for -m68000, and -m68882 is a synonym for -m68881.
7016 -[A]m[c]no-68851, -[A]m[c]no-68881
7017 Don't accept 688?1 instructions. (The "c" is kind of silly,
7018 so don't use or document it, but that's the way the parsing
7022 -k Indicates PIC. (Sun 3 only.)
7024 Never turn PC-relative branches into absolute jumps.
7026 Permit `|' to be used in expressions. */
7029 const char *md_shortopts
= "lSA:m:kQ:V";
7031 const char *md_shortopts
= "lSA:m:k";
7034 struct option md_longopts
[] = {
7035 #define OPTION_PIC (OPTION_MD_BASE)
7036 {"pic", no_argument
, NULL
, OPTION_PIC
},
7037 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7038 {"register-prefix-optional", no_argument
, NULL
,
7039 OPTION_REGISTER_PREFIX_OPTIONAL
},
7040 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7041 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
7042 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7043 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
7044 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7045 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
7046 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7047 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
7048 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7049 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
7050 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7051 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
7052 {NULL
, no_argument
, NULL
, 0}
7054 size_t md_longopts_size
= sizeof (md_longopts
);
7057 md_parse_option (int c
, char *arg
)
7061 case 'l': /* -l means keep external to 2 bit offset
7062 rather than 16 bit one. */
7063 flag_short_refs
= 1;
7066 case 'S': /* -S means that jbsr's always turn into
7068 flag_long_jumps
= 1;
7071 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
7072 branches into absolute jumps. */
7073 flag_keep_pcrel
= 1;
7079 /* Intentional fall-through. */
7082 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
7086 const char *oarg
= arg
;
7092 if (arg
[0] == 'c' && arg
[1] == '6')
7095 for (i
= 0; i
< n_archs
; i
++)
7096 if (!strcmp (arg
, archs
[i
].name
))
7101 arch
= archs
[i
].arch
;
7104 else if (arch
== m68851
)
7113 if (arg
[0] == 'c' && arg
[1] == '6')
7116 for (i
= 0; i
< n_archs
; i
++)
7117 if (!strcmp (arg
, archs
[i
].name
))
7119 unsigned long arch
= archs
[i
].arch
;
7121 if (cpu_of_arch (arch
))
7122 /* It's a cpu spec. */
7124 current_architecture
&= ~m68000up
;
7125 current_architecture
|= arch
;
7126 current_chip
= archs
[i
].chip
;
7128 else if (arch
== m68881
)
7130 current_architecture
|= m68881
;
7133 else if (arch
== m68851
)
7135 current_architecture
|= m68851
;
7145 as_bad (_("unrecognized architecture specification `%s'"), arg
);
7154 break; /* -pic, Position Independent Code. */
7156 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7157 flag_reg_prefix_optional
= 1;
7158 reg_prefix_optional_seen
= 1;
7161 /* -V: SVR4 argument to print version ID. */
7163 print_version_id ();
7166 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7167 should be emitted or not. FIXME: Not implemented. */
7171 case OPTION_BITWISE_OR
:
7176 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
7178 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7182 m68k_comment_chars
= n
;
7186 case OPTION_BASE_SIZE_DEFAULT_16
:
7187 m68k_index_width_default
= SIZE_WORD
;
7190 case OPTION_BASE_SIZE_DEFAULT_32
:
7191 m68k_index_width_default
= SIZE_LONG
;
7194 case OPTION_DISP_SIZE_DEFAULT_16
:
7196 m68k_rel32_from_cmdline
= 1;
7199 case OPTION_DISP_SIZE_DEFAULT_32
:
7201 m68k_rel32_from_cmdline
= 1;
7212 md_show_usage (FILE *stream
)
7214 const char *default_cpu
= TARGET_CPU
;
7216 unsigned int default_arch
;
7218 /* Get the canonical name for the default target CPU. */
7219 if (*default_cpu
== 'm')
7221 for (i
= 0; i
< n_archs
; i
++)
7223 if (strcasecmp (default_cpu
, archs
[i
].name
) == 0)
7225 default_arch
= archs
[i
].arch
;
7226 for (i
= 0; i
< n_archs
; i
++)
7228 if (archs
[i
].arch
== default_arch
7231 default_cpu
= archs
[i
].name
;
7238 fprintf (stream
, _("\
7240 -l use 1 word for refs to undefined symbols [default 2]\n\
7241 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7242 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
7243 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\
7244 -m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\
7245 specify variant of 680X0 architecture [default %s]\n\
7246 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7247 target has/lacks floating-point coprocessor\n\
7248 [default yes for 68020, 68030, and cpu32]\n"),
7250 fprintf (stream
, _("\
7251 -m68851 | -mno-68851\n\
7252 target has/lacks memory-management unit coprocessor\n\
7253 [default yes for 68020 and up]\n\
7254 -pic, -k generate position independent code\n\
7255 -S turn jbsr into jsr\n\
7256 --pcrel never turn PC-relative branches into absolute jumps\n\
7257 --register-prefix-optional\n\
7258 recognize register names without prefix character\n\
7259 --bitwise-or do not treat `|' as a comment character\n"));
7260 fprintf (stream
, _("\
7261 --base-size-default-16 base reg without size is 16 bits\n\
7262 --base-size-default-32 base reg without size is 32 bits (default)\n\
7263 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7264 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7269 /* TEST2: Test md_assemble() */
7270 /* Warning, this routine probably doesn't work anymore. */
7274 struct m68k_it the_ins
;
7282 if (!gets (buf
) || !*buf
)
7284 if (buf
[0] == '|' || buf
[1] == '.')
7286 for (cp
= buf
; *cp
; cp
++)
7291 memset (&the_ins
, '\0', sizeof (the_ins
));
7292 m68k_ip (&the_ins
, buf
);
7295 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7299 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7300 for (n
= 0; n
< the_ins
.numo
; n
++)
7301 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7303 print_the_insn (&the_ins
.opcode
[0], stdout
);
7304 (void) putchar ('\n');
7306 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7308 if (the_ins
.operands
[n
].error
)
7310 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7313 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
,
7314 the_ins
.operands
[n
].reg
);
7315 if (the_ins
.operands
[n
].b_const
)
7316 printf ("Constant: '%.*s', ",
7317 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
,
7318 the_ins
.operands
[n
].b_const
);
7319 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
,
7320 the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7321 if (the_ins
.operands
[n
].b_iadd
)
7322 printf ("Iadd: '%.*s',",
7323 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
,
7324 the_ins
.operands
[n
].b_iadd
);
7333 is_label (char *str
)
7337 while (*str
&& *str
!= ' ')
7339 if (str
[-1] == ':' || str
[1] == '=')
7346 /* Possible states for relaxation:
7348 0 0 branch offset byte (bra, etc)
7352 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7356 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7363 /* We have no need to default values of symbols. */
7366 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7371 /* Round up a section size to the appropriate boundary. */
7373 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7376 #ifdef BFD_ASSEMBLER
7377 /* For a.out, force the section size to be aligned. If we don't do
7378 this, BFD will align it for us, but it will not write out the
7379 final bytes of the section. This may be a bug in BFD, but it is
7380 easier to fix it here since that is how the other a.out targets
7384 align
= bfd_get_section_alignment (stdoutput
, segment
);
7385 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7392 /* Exactly what point is a PC-relative offset relative TO?
7393 On the 68k, it is relative to the address of the first extension
7394 word. The difference between the addresses of the offset and the
7395 first extension word is stored in fx_pcrel_adjust. */
7397 md_pcrel_from (fixS
*fixP
)
7401 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7402 sign extend the value here. */
7403 adjust
= ((fixP
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80;
7406 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7409 #ifndef BFD_ASSEMBLER
7413 tc_coff_symbol_emit_hook (symbolS
*ignore ATTRIBUTE_UNUSED
)
7418 tc_coff_sizemachdep (fragS
*frag
)
7420 switch (frag
->fr_subtype
& 0x3)
7439 m68k_elf_final_processing (void)
7441 /* Set file-specific flags if this is a cpu32 processor. */
7442 if (cpu_of_arch (current_architecture
) & cpu32
)
7443 elf_elfheader (stdoutput
)->e_flags
|= EF_CPU32
;
7444 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7445 && !(cpu_of_arch (current_architecture
) & m68020up
))
7446 elf_elfheader (stdoutput
)->e_flags
|= EF_M68000
;
7451 tc_m68k_regname_to_dw2regnum (const char *regname
)
7453 unsigned int regnum
;
7454 static const char *const regnames
[] =
7456 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7457 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7458 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7462 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
7463 if (strcmp (regname
, regnames
[regnum
]) == 0)
7470 tc_m68k_frame_initial_instructions (void)
7472 static int sp_regno
= -1;
7475 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
7477 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
7478 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);