1 /* tc-mep.c -- Assembler for the Toshiba Media Processor.
2 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007
3 Free Software Foundation. Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "dwarf2dbg.h"
27 #include "opcodes/mep-desc.h"
28 #include "opcodes/mep-opc.h"
30 #include "elf/common.h"
35 /* Structure to hold all of the different components describing
36 an individual instruction. */
39 const CGEN_INSN
* insn
;
40 const CGEN_INSN
* orig_insn
;
43 CGEN_INSN_INT buffer
[1];
44 #define INSN_VALUE(buf) (*(buf))
46 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
47 #define INSN_VALUE(buf) (buf)
52 fixS
* fixups
[GAS_CGEN_MAX_FIXUPS
];
53 int indices
[MAX_OPERAND_INSTANCES
];
56 static int mode
= CORE
; /* Start in core mode. */
57 static int pluspresent
= 0;
58 static int allow_disabled_registers
= 0;
59 static int library_flag
= 0;
60 static int mep_cop
= EF_MEP_COP_NONE
;
62 /* We're going to need to store all of the instructions along with
63 their fixups so that we can parallelization grouping rules. */
65 static mep_insn saved_insns
[MAX_SAVED_FIXUP_CHAINS
];
66 static int num_insns_saved
= 0;
68 const char comment_chars
[] = "#";
69 const char line_comment_chars
[] = ";#";
70 const char line_separator_chars
[] = ";";
71 const char EXP_CHARS
[] = "eE";
72 const char FLT_CHARS
[] = "dD";
74 static void mep_switch_to_vliw_mode (int);
75 static void mep_switch_to_core_mode (int);
76 static void mep_s_vtext (int);
77 static void mep_noregerr (int);
79 /* The target specific pseudo-ops which we support. */
80 const pseudo_typeS md_pseudo_table
[] =
83 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
84 { "loc", dwarf2_directive_loc
, 0 },
85 { "vliw", mep_switch_to_vliw_mode
, 0 },
86 { "core", mep_switch_to_core_mode
, 0 },
87 { "vtext", mep_s_vtext
, 0 },
88 { "noregerr", mep_noregerr
, 0 },
92 /* Relocations against symbols are done in two
93 parts, with a HI relocation and a LO relocation. Each relocation
94 has only 16 bits of space to store an addend. This means that in
95 order for the linker to handle carries correctly, it must be able
96 to locate both the HI and the LO relocation. This means that the
97 relocations must appear in order in the relocation table.
99 In order to implement this, we keep track of each unmatched HI
100 relocation. We then sort them so that they immediately precede the
101 corresponding LO relocation. */
105 struct mep_hi_fixup
* next
; /* Next HI fixup. */
106 fixS
* fixp
; /* This fixup. */
107 segT seg
; /* The section this fixup is in. */
110 /* The list of unmatched HI relocs. */
111 static struct mep_hi_fixup
* mep_hi_fixup_list
;
114 #define OPTION_EB (OPTION_MD_BASE + 0)
115 #define OPTION_EL (OPTION_MD_BASE + 1)
116 #define OPTION_CONFIG (OPTION_MD_BASE + 2)
117 #define OPTION_AVERAGE (OPTION_MD_BASE + 3)
118 #define OPTION_NOAVERAGE (OPTION_MD_BASE + 4)
119 #define OPTION_MULT (OPTION_MD_BASE + 5)
120 #define OPTION_NOMULT (OPTION_MD_BASE + 6)
121 #define OPTION_DIV (OPTION_MD_BASE + 7)
122 #define OPTION_NODIV (OPTION_MD_BASE + 8)
123 #define OPTION_BITOPS (OPTION_MD_BASE + 9)
124 #define OPTION_NOBITOPS (OPTION_MD_BASE + 10)
125 #define OPTION_LEADZ (OPTION_MD_BASE + 11)
126 #define OPTION_NOLEADZ (OPTION_MD_BASE + 12)
127 #define OPTION_ABSDIFF (OPTION_MD_BASE + 13)
128 #define OPTION_NOABSDIFF (OPTION_MD_BASE + 14)
129 #define OPTION_MINMAX (OPTION_MD_BASE + 15)
130 #define OPTION_NOMINMAX (OPTION_MD_BASE + 16)
131 #define OPTION_CLIP (OPTION_MD_BASE + 17)
132 #define OPTION_NOCLIP (OPTION_MD_BASE + 18)
133 #define OPTION_SATUR (OPTION_MD_BASE + 19)
134 #define OPTION_NOSATUR (OPTION_MD_BASE + 20)
135 #define OPTION_COP32 (OPTION_MD_BASE + 21)
136 #define OPTION_REPEAT (OPTION_MD_BASE + 25)
137 #define OPTION_NOREPEAT (OPTION_MD_BASE + 26)
138 #define OPTION_DEBUG (OPTION_MD_BASE + 27)
139 #define OPTION_NODEBUG (OPTION_MD_BASE + 28)
140 #define OPTION_UCI (OPTION_MD_BASE + 29)
141 #define OPTION_NOUCI (OPTION_MD_BASE + 30)
142 #define OPTION_DSP (OPTION_MD_BASE + 31)
143 #define OPTION_NODSP (OPTION_MD_BASE + 32)
144 #define OPTION_LIBRARY (OPTION_MD_BASE + 33)
146 struct option md_longopts
[] = {
147 { "EB", no_argument
, NULL
, OPTION_EB
},
148 { "EL", no_argument
, NULL
, OPTION_EL
},
149 { "mconfig", required_argument
, NULL
, OPTION_CONFIG
},
150 { "maverage", no_argument
, NULL
, OPTION_AVERAGE
},
151 { "mno-average", no_argument
, NULL
, OPTION_NOAVERAGE
},
152 { "mmult", no_argument
, NULL
, OPTION_MULT
},
153 { "mno-mult", no_argument
, NULL
, OPTION_NOMULT
},
154 { "mdiv", no_argument
, NULL
, OPTION_DIV
},
155 { "mno-div", no_argument
, NULL
, OPTION_NODIV
},
156 { "mbitops", no_argument
, NULL
, OPTION_BITOPS
},
157 { "mno-bitops", no_argument
, NULL
, OPTION_NOBITOPS
},
158 { "mleadz", no_argument
, NULL
, OPTION_LEADZ
},
159 { "mno-leadz", no_argument
, NULL
, OPTION_NOLEADZ
},
160 { "mabsdiff", no_argument
, NULL
, OPTION_ABSDIFF
},
161 { "mno-absdiff", no_argument
, NULL
, OPTION_NOABSDIFF
},
162 { "mminmax", no_argument
, NULL
, OPTION_MINMAX
},
163 { "mno-minmax", no_argument
, NULL
, OPTION_NOMINMAX
},
164 { "mclip", no_argument
, NULL
, OPTION_CLIP
},
165 { "mno-clip", no_argument
, NULL
, OPTION_NOCLIP
},
166 { "msatur", no_argument
, NULL
, OPTION_SATUR
},
167 { "mno-satur", no_argument
, NULL
, OPTION_NOSATUR
},
168 { "mcop32", no_argument
, NULL
, OPTION_COP32
},
169 { "mdebug", no_argument
, NULL
, OPTION_DEBUG
},
170 { "mno-debug", no_argument
, NULL
, OPTION_NODEBUG
},
171 { "muci", no_argument
, NULL
, OPTION_UCI
},
172 { "mno-uci", no_argument
, NULL
, OPTION_NOUCI
},
173 { "mdsp", no_argument
, NULL
, OPTION_DSP
},
174 { "mno-dsp", no_argument
, NULL
, OPTION_NODSP
},
175 { "mlibrary", no_argument
, NULL
, OPTION_LIBRARY
},
176 { NULL
, 0, NULL
, 0 } };
177 size_t md_longopts_size
= sizeof (md_longopts
);
179 const char * md_shortopts
= "";
180 static int optbits
= 0;
181 static int optbitset
= 0;
184 md_parse_option (int c
, char *arg ATTRIBUTE_UNUSED
)
190 target_big_endian
= 1;
193 target_big_endian
= 0;
197 for (i
=1; mep_config_map
[i
].name
; i
++)
198 if (strcmp (mep_config_map
[i
].name
, arg
) == 0)
205 fprintf (stderr
, "Error: unknown configuration %s\n", arg
);
208 mep_config_index
= idx
;
209 target_big_endian
= mep_config_map
[idx
].big_endian
;
212 optbits
|= 1 << CGEN_INSN_OPTIONAL_AVE_INSN
;
213 optbitset
|= 1 << CGEN_INSN_OPTIONAL_AVE_INSN
;
215 case OPTION_NOAVERAGE
:
216 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_AVE_INSN
);
217 optbitset
|= 1 << CGEN_INSN_OPTIONAL_AVE_INSN
;
220 optbits
|= 1 << CGEN_INSN_OPTIONAL_MUL_INSN
;
221 optbitset
|= 1 << CGEN_INSN_OPTIONAL_MUL_INSN
;
224 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_MUL_INSN
);
225 optbitset
|= 1 << CGEN_INSN_OPTIONAL_MUL_INSN
;
228 optbits
|= 1 << CGEN_INSN_OPTIONAL_DIV_INSN
;
229 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DIV_INSN
;
232 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_DIV_INSN
);
233 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DIV_INSN
;
236 optbits
|= 1 << CGEN_INSN_OPTIONAL_BIT_INSN
;
237 optbitset
|= 1 << CGEN_INSN_OPTIONAL_BIT_INSN
;
239 case OPTION_NOBITOPS
:
240 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_BIT_INSN
);
241 optbitset
|= 1 << CGEN_INSN_OPTIONAL_BIT_INSN
;
244 optbits
|= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN
;
245 optbitset
|= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN
;
248 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_LDZ_INSN
);
249 optbitset
|= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN
;
252 optbits
|= 1 << CGEN_INSN_OPTIONAL_ABS_INSN
;
253 optbitset
|= 1 << CGEN_INSN_OPTIONAL_ABS_INSN
;
255 case OPTION_NOABSDIFF
:
256 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_ABS_INSN
);
257 optbitset
|= 1 << CGEN_INSN_OPTIONAL_ABS_INSN
;
260 optbits
|= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN
;
261 optbitset
|= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN
;
263 case OPTION_NOMINMAX
:
264 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_MINMAX_INSN
);
265 optbitset
|= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN
;
268 optbits
|= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN
;
269 optbitset
|= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN
;
272 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_CLIP_INSN
);
273 optbitset
|= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN
;
276 optbits
|= 1 << CGEN_INSN_OPTIONAL_SAT_INSN
;
277 optbitset
|= 1 << CGEN_INSN_OPTIONAL_SAT_INSN
;
280 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_SAT_INSN
);
281 optbitset
|= 1 << CGEN_INSN_OPTIONAL_SAT_INSN
;
284 optbits
|= 1 << CGEN_INSN_OPTIONAL_CP_INSN
;
285 optbitset
|= 1 << CGEN_INSN_OPTIONAL_CP_INSN
;
288 optbits
|= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN
;
289 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN
;
292 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_DEBUG_INSN
);
293 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN
;
296 optbits
|= 1 << CGEN_INSN_OPTIONAL_UCI_INSN
;
297 optbitset
|= 1 << CGEN_INSN_OPTIONAL_UCI_INSN
;
300 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_UCI_INSN
);
301 optbitset
|= 1 << CGEN_INSN_OPTIONAL_UCI_INSN
;
304 optbits
|= 1 << CGEN_INSN_OPTIONAL_DSP_INSN
;
305 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DSP_INSN
;
308 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_DSP_INSN
);
309 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DSP_INSN
;
312 library_flag
= EF_MEP_LIBRARY
;
315 case OPTION_NOREPEAT
:
324 md_show_usage (FILE *stream
)
326 fprintf (stream
, _("MeP specific command line options:\n\
327 -EB assemble for a big endian system\n\
328 -EL assemble for a little endian system (default)\n\
329 -mconfig=<name> specify a chip configuration to use\n\
330 -maverage -mno-average -mmult -mno-mult -mdiv -mno-div\n\
331 -mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff\n\
332 -mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32\n\
333 enable/disable the given opcodes\n\
335 If -mconfig is given, the other -m options modify it. Otherwise,\n\
336 if no -m options are given, all core opcodes are enabled;\n\
337 if any enabling -m options are given, only those are enabled;\n\
338 if only disabling -m options are given, only those are disabled.\n\
340 if (mep_config_map
[1].name
)
343 fprintf (stream
, " -mconfig=STR specify the configuration to use\n");
344 fprintf (stream
, " Configurations:");
345 for (i
=0; mep_config_map
[i
].name
; i
++)
346 fprintf (stream
, " %s", mep_config_map
[i
].name
);
347 fprintf (stream
, "\n");
354 mep_check_for_disabled_registers (mep_insn
*insn
)
356 static int initted
= 0;
357 static int has_mul_div
= 0;
358 static int has_cop
= 0;
359 static int has_debug
= 0;
362 if (allow_disabled_registers
)
366 if (target_big_endian
)
367 b
= insn
->buffer
[0] * 256 + insn
->buffer
[1];
369 b
= insn
->buffer
[1] * 256 + insn
->buffer
[0];
374 if ((b
& 0xfffff00e) == 0x7008 /* stc */
375 || (b
& 0xfffff00e) == 0x700a /* ldc */)
380 if ((MEP_OMASK
& (1 << CGEN_INSN_OPTIONAL_MUL_INSN
))
381 || (MEP_OMASK
& (1 << CGEN_INSN_OPTIONAL_DIV_INSN
)))
383 if (MEP_OMASK
& (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN
))
385 if (MEP_OMASK
& (1 << CGEN_INSN_OPTIONAL_CP_INSN
))
389 r
= ((b
& 0x00f0) >> 4) | ((b
& 0x0001) << 4);
395 as_bad ("$hi and $lo are disabled when MUL and DIV are off");
402 as_bad ("$mb0, $me0, $mb1, and $me1 are disabled when COP is off");
407 as_bad ("$dbg and $depc are disabled when DEBUG is off");
416 switch (MEP_CPU
& EF_MEP_CPU_MASK
)
419 case EF_MEP_CPU_C2
: return bfd_mach_mep
;
420 case EF_MEP_CPU_C3
: return bfd_mach_mep
;
421 case EF_MEP_CPU_C4
: return bfd_mach_mep
;
422 case EF_MEP_CPU_C5
: return bfd_mach_mep_c5
;
423 case EF_MEP_CPU_H1
: return bfd_mach_mep_h1
;
429 /* The MeP version of the cgen parse_operand function. The only difference
430 from the standard version is that we want to avoid treating '$foo' and
431 '($foo...)' as references to a symbol called '$foo'. The chances are
432 that '$foo' is really a misspelt register. */
435 mep_parse_operand (CGEN_CPU_DESC cd
, enum cgen_parse_operand_type want
,
436 const char **strP
, int opindex
, int opinfo
,
437 enum cgen_parse_operand_result
*resultP
, bfd_vma
*valueP
)
439 if (want
== CGEN_PARSE_OPERAND_INTEGER
|| want
== CGEN_PARSE_OPERAND_ADDRESS
)
447 return "Not a valid literal";
449 return gas_cgen_parse_operand (cd
, want
, strP
, opindex
, opinfo
,
456 /* Initialize the `cgen' interface. */
458 /* If the user specifies no options, we default to allowing
459 everything. If the user specifies any enabling options, we
460 default to allowing only what is specified. If the user
461 specifies only disabling options, we only disable what is
462 specified. If the user specifies options and a config, the
463 options modify the config. */
464 if (optbits
&& mep_config_index
== 0)
467 MEP_OMASK
= (MEP_OMASK
& ~optbitset
) | optbits
;
469 mep_cop
= mep_config_map
[mep_config_index
].cpu_flag
& EF_MEP_COP_MASK
;
471 /* Set the machine number and endian. */
472 gas_cgen_cpu_desc
= mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS
, 0,
473 CGEN_CPU_OPEN_ENDIAN
,
476 : CGEN_ENDIAN_LITTLE
,
477 CGEN_CPU_OPEN_ISAS
, 0,
479 mep_cgen_init_asm (gas_cgen_cpu_desc
);
481 /* This is a callback from cgen to gas to parse operands. */
482 cgen_set_parse_operand_fn (gas_cgen_cpu_desc
, mep_parse_operand
);
484 /* Identify the architecture. */
485 bfd_default_set_arch_mach (stdoutput
, bfd_arch_mep
, mep_machine ());
487 /* Store the configuration number and core. */
488 bfd_set_private_flags (stdoutput
, MEP_CPU
| MEP_CONFIG
| library_flag
);
490 /* Initialize the array we'll be using to store fixups. */
491 gas_cgen_initialize_saved_fixups_array();
494 /* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a
495 coprocessor instruction, if possible, into FIELDS, BUF, and INSN. */
497 static const CGEN_INSN
*
498 mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd
,
501 CGEN_INSN_BYTES_PTR buf
,
502 const struct cgen_insn
*pinsn
)
505 CGEN_INSN_LIST
*ilist
;
506 const char *errmsg
= NULL
;
508 /* The instructions are stored in hashed lists. */
509 ilist
= CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc
,
510 CGEN_INSN_MNEMONIC (pinsn
));
513 for ( ; ilist
!= NULL
; ilist
= CGEN_ASM_NEXT_INSN (ilist
))
515 const CGEN_INSN
*insn
= ilist
->insn
;
516 if (strcmp (CGEN_INSN_MNEMONIC (ilist
->insn
),
517 CGEN_INSN_MNEMONIC (pinsn
)) == 0
518 && MEP_INSN_COP_P (ilist
->insn
)
519 && mep_cgen_insn_supported (cd
, insn
))
523 /* skip this insn if str doesn't look right lexically */
524 if (CGEN_INSN_RX (insn
) != NULL
&&
525 regexec ((regex_t
*) CGEN_INSN_RX (insn
), str
, 0, NULL
, 0) == REG_NOMATCH
)
528 /* Allow parse/insert handlers to obtain length of insn. */
529 CGEN_FIELDS_BITSIZE (fields
) = CGEN_INSN_BITSIZE (insn
);
531 errmsg
= CGEN_PARSE_FN (cd
, insn
) (cd
, insn
, & str
, fields
);
535 errmsg
= CGEN_INSERT_FN (cd
, insn
) (cd
, insn
, fields
, buf
,
547 mep_save_insn (mep_insn insn
)
549 /* Consider change MAX_SAVED_FIXUP_CHAINS to MAX_PARALLEL_INSNS. */
550 if (num_insns_saved
< 0 || num_insns_saved
>= MAX_SAVED_FIXUP_CHAINS
)
552 as_fatal("index into saved_insns[] out of bounds.");
555 saved_insns
[num_insns_saved
] = insn
;
556 gas_cgen_save_fixups(num_insns_saved
);
561 mep_check_parallel32_scheduling (void)
563 int insn0iscopro
, insn1iscopro
, insn0length
, insn1length
;
565 /* More than two instructions means that either someone is referring to
566 an internally parallel core or an internally parallel coprocessor,
567 neither of which are supported at this time. */
568 if ( num_insns_saved
> 2 )
569 as_fatal("Internally paralled cores and coprocessors not supported.");
571 /* If there are no insns saved, that's ok. Just return. This will
572 happen when mep_process_saved_insns is called when the end of the
573 source file is reached and there are no insns left to be processed. */
574 if (num_insns_saved
== 0)
577 /* Check some of the attributes of the first insn. */
578 insn0iscopro
= MEP_INSN_COP_P (saved_insns
[0].insn
);
579 insn0length
= CGEN_FIELDS_BITSIZE (& saved_insns
[0].fields
);
581 if (num_insns_saved
== 2)
583 /* Check some of the attributes of the first insn. */
584 insn1iscopro
= MEP_INSN_COP_P (saved_insns
[1].insn
);
585 insn1length
= CGEN_FIELDS_BITSIZE (& saved_insns
[1].fields
);
587 if ((insn0iscopro
&& !insn1iscopro
)
588 || (insn1iscopro
&& !insn0iscopro
))
590 /* We have one core and one copro insn. If their sizes
591 add up to 32, then the combination is valid. */
592 if (insn0length
+ insn1length
== 32)
595 as_bad ("core and copro insn lengths must total 32 bits.");
598 as_bad ("vliw group must consist of 1 core and 1 copro insn.");
602 /* If we arrive here, we have one saved instruction. There are a
603 number of possible cases:
605 1. The instruction is a 32 bit core or coprocessor insn and
606 can be executed by itself. Valid.
608 2. The instrucion is a core instruction for which a cop nop
609 exists. In this case, insert the cop nop into the saved
610 insn array after the core insn and return. Valid.
612 3. The instruction is a coprocessor insn for which a core nop
613 exists. In this case, move the coprocessor insn to the
614 second element of the array and put the nop in the first
615 element then return. Valid.
617 4. The instruction is a core or coprocessor instruction for
618 which there is no matching coprocessor or core nop to use
619 to form a valid vliw insn combination. In this case, we
622 if (insn0length
> 32)
623 as_fatal ("Cannot use 48- or 64-bit insns with a 32 bit datapath.");
625 if (insn0length
== 32)
628 /* Insn is smaller than datapath. If there are no matching
629 nops for this insn, then terminate assembly. */
630 if (CGEN_INSN_ATTR_VALUE (saved_insns
[0].insn
,
631 CGEN_INSN_VLIW32_NO_MATCHING_NOP
))
632 as_fatal ("No valid nop.");
634 /* At this point we know that we have a single 16-bit insn that has
635 a matching nop. We have to assemble it and put it into the saved
636 insn and fixup chain arrays. */
643 /* Move the insn and it's fixups to the second element of the
644 saved insns arrary and insert a 16 bit core nope into the
646 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "nop",
647 &insn
.fields
, insn
.buffer
,
651 as_bad ("%s", errmsg
);
655 /* Move the insn in element 0 to element 1 and insert the
656 nop into element 0. Move the fixups in element 0 to
657 element 1 and save the current fixups to element 0.
658 Really there aren't any fixups at this point because we're
659 inserting a nop but we might as well be general so that
660 if there's ever a need to insert a general insn, we'll
662 saved_insns
[1] = saved_insns
[0];
663 saved_insns
[0] = insn
;
665 gas_cgen_swap_fixups (0);
666 gas_cgen_save_fixups (1);
672 int insn_num
= saved_insns
[0].insn
->base
->num
;
674 /* Use 32 bit branches and skip the nop. */
675 if (insn_num
== MEP_INSN_BSR12
676 || insn_num
== MEP_INSN_BEQZ
677 || insn_num
== MEP_INSN_BNEZ
)
680 /* Insert a 16-bit coprocessor nop. Note that at the time */
681 /* this was done, no 16-bit coprocessor nop was defined. */
682 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "cpnop16",
683 &insn
.fields
, insn
.buffer
,
687 as_bad ("%s", errmsg
);
691 /* Now put the insn and fixups into the arrays. */
692 mep_save_insn (insn
);
698 mep_check_parallel64_scheduling (void)
700 int insn0iscopro
, insn1iscopro
, insn0length
, insn1length
;
702 /* More than two instructions means that someone is referring to an
703 internally parallel core or an internally parallel coprocessor. */
704 /* These are not currently supported. */
705 if (num_insns_saved
> 2)
706 as_fatal ("Internally parallel cores of coprocessors not supported.");
708 /* If there are no insns saved, that's ok. Just return. This will
709 happen when mep_process_saved_insns is called when the end of the
710 source file is reached and there are no insns left to be processed. */
711 if (num_insns_saved
== 0)
714 /* Check some of the attributes of the first insn. */
715 insn0iscopro
= MEP_INSN_COP_P (saved_insns
[0].insn
);
716 insn0length
= CGEN_FIELDS_BITSIZE (& saved_insns
[0].fields
);
718 if (num_insns_saved
== 2)
720 /* Check some of the attributes of the first insn. */
721 insn1iscopro
= MEP_INSN_COP_P (saved_insns
[1].insn
);
722 insn1length
= CGEN_FIELDS_BITSIZE (& saved_insns
[1].fields
);
724 if ((insn0iscopro
&& !insn1iscopro
)
725 || (insn1iscopro
&& !insn0iscopro
))
727 /* We have one core and one copro insn. If their sizes
728 add up to 64, then the combination is valid. */
729 if (insn0length
+ insn1length
== 64)
732 as_bad ("core and copro insn lengths must total 64 bits.");
735 as_bad ("vliw group must consist of 1 core and 1 copro insn.");
739 /* If we arrive here, we have one saved instruction. There are a
740 number of possible cases:
742 1. The instruction is a 64 bit coprocessor insn and can be
743 executed by itself. Valid.
745 2. The instrucion is a core instruction for which a cop nop
746 exists. In this case, insert the cop nop into the saved
747 insn array after the core insn and return. Valid.
749 3. The instruction is a coprocessor insn for which a core nop
750 exists. In this case, move the coprocessor insn to the
751 second element of the array and put the nop in the first
752 element then return. Valid.
754 4. The instruction is a core or coprocessor instruction for
755 which there is no matching coprocessor or core nop to use
756 to form a valid vliw insn combination. In this case, we
759 /* If the insn is 64 bits long, it can run alone. The size check
760 is done indepependantly of whether the insn is core or copro
761 in case 64 bit coprocessor insns are added later. */
762 if (insn0length
== 64)
765 /* Insn is smaller than datapath. If there are no matching
766 nops for this insn, then terminate assembly. */
767 if (CGEN_INSN_ATTR_VALUE (saved_insns
[0].insn
,
768 CGEN_INSN_VLIW64_NO_MATCHING_NOP
))
769 as_fatal ("No valid nop.");
776 /* Initialize the insn buffer. */
777 memset (insn
.buffer
, 0, sizeof(insn
.buffer
));
779 /* We have a coprocessor insn. At this point in time there
780 are is 32-bit core nop. There is only a 16-bit core
781 nop. The idea is to allow for a relatively arbitrary
782 coprocessor to be specified. We aren't looking at
783 trying to cover future changes in the core at this time
784 since it is assumed that the core will remain fairly
785 static. If there ever are 32 or 48 bit core nops added,
786 they will require entries below. */
788 if (insn0length
== 48)
790 /* Move the insn and fixups to the second element of the
791 arrays then assemble and insert a 16 bit core nop. */
792 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "nop",
793 & insn
.fields
, insn
.buffer
,
798 /* If this is reached, then we have a single coprocessor
799 insn that is not 48 bits long, but for which the assembler
800 thinks there is a matching core nop. If a 32-bit core
801 nop has been added, then make the necessary changes and
802 handle its assembly and insertion here. Otherwise,
803 go figure out why either:
805 1. The assembler thinks that there is a 32-bit core nop
806 to match a 32-bit coprocessor insn, or
807 2. The assembler thinks that there is a 48-bit core nop
808 to match a 16-bit coprocessor insn. */
810 as_fatal ("Assembler expects a non-existent core nop.");
815 as_bad ("%s", errmsg
);
819 /* Move the insn in element 0 to element 1 and insert the
820 nop into element 0. Move the fixups in element 0 to
821 element 1 and save the current fixups to element 0.
822 Really there aren't any fixups at this point because we're
823 inserting a nop but we might as well be general so that
824 if there's ever a need to insert a general insn, we'll
827 saved_insns
[1] = saved_insns
[0];
828 saved_insns
[0] = insn
;
830 gas_cgen_swap_fixups(0);
831 gas_cgen_save_fixups(1);
839 /* Initialize the insn buffer */
840 memset (insn
.buffer
, 0, sizeof(insn
.buffer
));
842 /* We have a core insn. We have to handle all possible nop
843 lengths. If a coprocessor doesn't have a nop of a certain
844 length but there exists core insns that when combined with
845 a nop of that length would fill the datapath, those core
846 insns will be flagged with the VLIW_NO_CORRESPONDING_NOP
847 attribute. That will ensure that when used in a way that
848 requires a nop to be inserted, assembly will terminate
849 before reaching this section of code. This guarantees
850 that cases below which would result in the attempted
851 insertion of nop that doesn't exist will never be entered. */
852 if (insn0length
== 16)
854 /* Insert 48 bit coprocessor nop. */
855 /* Assemble it and put it into the arrays. */
856 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "cpnop48",
857 &insn
.fields
, insn
.buffer
,
860 else if (insn0length
== 32)
862 /* Insert 32 bit coprocessor nop. */
863 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "cpnop32",
864 &insn
.fields
, insn
.buffer
,
867 else if (insn0length
== 48)
869 /* Insert 16 bit coprocessor nop. */
870 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "cpnop16",
871 &insn
.fields
, insn
.buffer
,
875 /* Core insn has an invalid length. Something has gone wrong. */
876 as_fatal ("Core insn has invalid length! Something is wrong!");
880 as_bad ("%s", errmsg
);
884 /* Now put the insn and fixups into the arrays. */
885 mep_save_insn (insn
);
890 #ifdef MEP_IVC2_SUPPORTED
892 /* IVC2 packing is different than other VLIW coprocessors. Many of
893 the COP insns can be placed in any of three different types of
894 slots, and each bundle can hold up to three insns - zero or one
895 core insns and one or two IVC2 insns. The insns in CGEN are tagged
896 with which slots they're allowed in, and we have to decide based on
897 that whether or not the user had given us a possible bundling. */
900 slot_ok (int idx
, int slot
)
902 const CGEN_INSN
*insn
= saved_insns
[idx
].insn
;
903 return CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn
)) & (1 << slot
);
907 mep_check_ivc2_scheduling (void)
911 V1 [-----core-----][--------p0s-------][------------p1------------]
912 V2 [-------------core-------------]xxxx[------------p1------------]
913 V3 1111[--p0--]0111[--------p0--------][------------p1------------]
916 int slots
[5]; /* Indexed off the SLOTS_ATTR enum. */
921 int e
= target_big_endian
? 0 : 1;
923 /* If there are no insns saved, that's ok. Just return. This will
924 happen when mep_process_saved_insns is called when the end of the
925 source file is reached and there are no insns left to be processed. */
926 if (num_insns_saved
== 0)
932 if (slot_ok (0, SLOTS_CORE
))
934 slots
[SLOTS_CORE
] = 0;
935 corelength
= CGEN_FIELDS_BITSIZE (& saved_insns
[0].fields
);
940 if (corelength
== 16)
942 /* V1 mode: we need a P0S slot and a P1 slot. */
943 switch (num_insns_saved
)
946 /* No other insns, fill with NOPs. */
950 if (slot_ok (1, SLOTS_P1
))
952 else if (slot_ok (1, SLOTS_P0S
))
953 slots
[SLOTS_P0S
] = 1;
955 as_bad ("cannot pack %s with a 16-bit insn",
956 CGEN_INSN_NAME (saved_insns
[1].insn
));
960 if (slot_ok (1, SLOTS_P0S
)
961 && slot_ok (2, SLOTS_P1
))
963 slots
[SLOTS_P0S
] = 1;
966 else if (slot_ok (1, SLOTS_P1
)
967 && slot_ok (2, SLOTS_P0S
))
970 slots
[SLOTS_P0S
] = 2;
973 as_bad ("cannot pack %s and %s together with a 16-bit insn",
974 CGEN_INSN_NAME (saved_insns
[1].insn
),
975 CGEN_INSN_NAME (saved_insns
[2].insn
));
979 as_bad ("too many IVC2 insns to pack with a 16-bit core insn");
983 else if (corelength
== 32)
985 /* V2 mode: we need a P1 slot. */
986 switch (num_insns_saved
)
989 /* No other insns, fill with NOPs. */
992 /* The other insn must allow P1. */
993 if (!slot_ok (1, SLOTS_P1
))
994 as_bad ("cannot pack %s into slot P1",
995 CGEN_INSN_NAME (saved_insns
[1].insn
));
1000 as_bad ("too many IVC2 insns to pack with a 32-bit core insn");
1004 else if (corelength
== 0)
1006 /* V3 mode: we need a P0 slot and a P1 slot, or a P0S+P1 with a
1008 switch (num_insns_saved
)
1011 if (slot_ok (0, SLOTS_P0
))
1012 slots
[SLOTS_P0
] = 0;
1013 else if (slot_ok (0, SLOTS_P1
))
1014 slots
[SLOTS_P1
] = 0;
1015 else if (slot_ok (0, SLOTS_P0S
))
1016 slots
[SLOTS_P0S
] = 0;
1018 as_bad ("unable to pack %s by itself?",
1019 CGEN_INSN_NAME (saved_insns
[0].insn
));
1023 if (slot_ok (0, SLOTS_P0
)
1024 && slot_ok (1, SLOTS_P1
))
1026 slots
[SLOTS_P0
] = 0;
1027 slots
[SLOTS_P1
] = 1;
1029 else if (slot_ok (0, SLOTS_P1
)
1030 && slot_ok (1, SLOTS_P0
))
1032 slots
[SLOTS_P1
] = 0;
1033 slots
[SLOTS_P0
] = 1;
1035 else if (slot_ok (0, SLOTS_P0S
)
1036 && slot_ok (1, SLOTS_P1
))
1038 slots
[SLOTS_P0S
] = 0;
1039 slots
[SLOTS_P1
] = 1;
1041 else if (slot_ok (0, SLOTS_P1
)
1042 && slot_ok (1, SLOTS_P0S
))
1044 slots
[SLOTS_P1
] = 0;
1045 slots
[SLOTS_P0S
] = 1;
1048 as_bad ("cannot pack %s and %s together",
1049 CGEN_INSN_NAME (saved_insns
[0].insn
),
1050 CGEN_INSN_NAME (saved_insns
[1].insn
));
1054 as_bad ("too many IVC2 insns to pack together");
1059 /* The core insn needs to be done normally so that fixups,
1060 relaxation, etc are done. Other IVC2 insns need only be resolved
1061 to bit patterns; there are no relocations for them. */
1062 if (slots
[SLOTS_CORE
] != -1)
1064 gas_cgen_restore_fixups (0);
1065 gas_cgen_finish_insn (saved_insns
[0].insn
, saved_insns
[0].buffer
,
1066 CGEN_FIELDS_BITSIZE (& saved_insns
[0].fields
),
1070 /* Allocate whatever bytes remain in our insn word. Adjust the
1071 pointer to point (as if it were) to the beginning of the whole
1072 word, so that we don't have to adjust for it elsewhere. */
1073 f
= (bfd_byte
*) frag_more (8 - corelength
/ 8);
1074 /* Unused slots are filled with NOPs, which happen to be all zeros. */
1075 memset (f
, 0, 8 - corelength
/ 8);
1076 f
-= corelength
/ 8;
1085 m
= & saved_insns
[slots
[i
]];
1088 cgen_put_insn_value (gas_cgen_cpu_desc
, (unsigned char *) temp
, 32,
1091 memcpy (temp
, m
->buffer
, byte_len
);
1099 f
[4^e
] |= temp
[3^e
] & 0xf0;
1102 f
[0^e
] = 0xf0 | temp
[0^e
] >> 4;
1103 f
[1^e
] = temp
[0^e
] << 4 | 0x07;
1106 f
[4^e
] |= temp
[3^e
] & 0xf0;
1109 f
[4^e
] |= temp
[0^e
] >> 4;
1110 f
[5^e
] = temp
[0^e
] << 4 | temp
[1^e
] >> 4;
1111 f
[6^e
] = temp
[1^e
] << 4 | temp
[2^e
] >> 4;
1112 f
[7^e
] = temp
[2^e
] << 4 | temp
[3^e
] >> 4;
1120 #endif /* MEP_IVC2_SUPPORTED */
1122 /* The scheduling functions are just filters for invalid combinations.
1123 If there is a violation, they terminate assembly. Otherise they
1124 just fall through. Succesful combinations cause no side effects
1125 other than valid nop insertion. */
1128 mep_check_parallel_scheduling (void)
1130 /* This is where we will eventually read the config information
1131 and choose which scheduling checking function to call. */
1132 #ifdef MEP_IVC2_SUPPORTED
1133 if (mep_cop
== EF_MEP_COP_IVC2
)
1134 mep_check_ivc2_scheduling ();
1136 #endif /* MEP_IVC2_SUPPORTED */
1138 mep_check_parallel64_scheduling ();
1140 mep_check_parallel32_scheduling ();
1144 mep_process_saved_insns (void)
1148 gas_cgen_save_fixups (MAX_SAVED_FIXUP_CHAINS
- 1);
1150 /* We have to check for valid scheduling here. */
1151 mep_check_parallel_scheduling ();
1153 /* IVC2 has to pack instructions in a funny way, so it does it
1155 if (mep_cop
!= EF_MEP_COP_IVC2
)
1157 /* If the last call didn't cause assembly to terminate, we have
1158 a valid vliw insn/insn pair saved. Restore this instructions'
1159 fixups and process the insns. */
1160 for (i
= 0;i
<num_insns_saved
;i
++)
1162 gas_cgen_restore_fixups (i
);
1163 gas_cgen_finish_insn (saved_insns
[i
].insn
, saved_insns
[i
].buffer
,
1164 CGEN_FIELDS_BITSIZE (& saved_insns
[i
].fields
),
1168 gas_cgen_restore_fixups (MAX_SAVED_FIXUP_CHAINS
- 1);
1170 /* Clear the fixups and reset the number insn saved to 0. */
1171 gas_cgen_initialize_saved_fixups_array ();
1172 num_insns_saved
= 0;
1173 listing_prev_line ();
1177 md_assemble (char * str
)
1179 static CGEN_BITSET
* isas
= NULL
;
1182 /* Initialize GAS's cgen interface for a new instruction. */
1183 gas_cgen_init_parse ();
1185 /* There are two possible modes: core and vliw. We have to assemble
1186 differently for each.
1188 Core Mode: We assemble normally. All instructions are on a
1189 single line and are made up of one mnemonic and one
1191 VLIW Mode: Vliw combinations are indicated as follows:
1196 We want to handle the general case where more than
1197 one instruction can be preceeded by a +. This will
1198 happen later if we add support for internally parallel
1199 coprocessors. We'll make the parsing nice and general
1200 so that it can handle an arbitrary number of insns
1201 with leading +'s. The actual checking for valid
1202 combinations is done elsewhere. */
1204 /* Initialize the isa to refer to the core. */
1206 isas
= cgen_bitset_copy (& MEP_CORE_ISA
);
1209 cgen_bitset_clear (isas
);
1210 cgen_bitset_union (isas
, & MEP_CORE_ISA
, isas
);
1212 gas_cgen_cpu_desc
->isas
= isas
;
1218 int thisInsnIsCopro
= 0;
1222 /* Initialize the insn buffer */
1224 if (! CGEN_INT_INSN_P
)
1225 for (i
=0; i
< CGEN_MAX_INSN_SIZE
; i
++)
1226 insn
.buffer
[i
]='\0';
1229 /* IVC2 has two sets of coprocessor opcodes, one for CORE mode
1230 and one for VLIW mode. They have the same names. To specify
1231 which one we want, we use the COP isas - the 32 bit ISA is
1232 for the core instructions (which are always 32 bits), and the
1233 other ISAs are for the VLIW ones (which always pack into 64
1234 bit insns). We use other attributes to determine slotting
1236 if (mep_cop
== EF_MEP_COP_IVC2
)
1238 cgen_bitset_union (isas
, & MEP_COP16_ISA
, isas
);
1239 cgen_bitset_union (isas
, & MEP_COP48_ISA
, isas
);
1240 cgen_bitset_union (isas
, & MEP_COP64_ISA
, isas
);
1244 /* Can't tell core / copro insns apart at parse time! */
1245 cgen_bitset_union (isas
, & MEP_COP_ISA
, isas
);
1248 /* Assemble the insn so we can examine its attributes. */
1249 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, str
,
1250 &insn
.fields
, insn
.buffer
,
1254 as_bad ("%s", errmsg
);
1257 mep_check_for_disabled_registers (&insn
);
1259 /* Check to see if it's a coprocessor instruction. */
1260 thisInsnIsCopro
= MEP_INSN_COP_P (insn
.insn
);
1262 if (!thisInsnIsCopro
)
1264 insn
.insn
= mep_cgen_assemble_cop_insn (gas_cgen_cpu_desc
, str
,
1265 &insn
.fields
, insn
.buffer
,
1267 thisInsnIsCopro
= MEP_INSN_COP_P (insn
.insn
);
1268 mep_check_for_disabled_registers (&insn
);
1273 /* A plus was present. */
1274 /* Check for a + with a core insn and abort if found. */
1275 if (!thisInsnIsCopro
)
1277 as_fatal("A core insn cannot be preceeded by a +.\n");
1281 if (num_insns_saved
> 0)
1283 /* There are insns in the queue. Add this one. */
1284 mep_save_insn (insn
);
1288 /* There are no insns in the queue and a plus is present.
1289 This is a syntax error. Let's not tolerate this.
1290 We can relax this later if necessary. */
1291 as_bad (_("Invalid use of parallelization operator."));
1297 /* No plus was present. */
1298 if (num_insns_saved
> 0)
1300 /* There are insns saved and we came across an insn without a
1301 leading +. That's the signal to process the saved insns
1302 before proceeding then treat the current insn as the first
1303 in a new vliw group. */
1304 mep_process_saved_insns ();
1305 num_insns_saved
= 0;
1306 /* mep_save_insn (insn); */
1308 mep_save_insn (insn
);
1313 /* Core Insn. Add it to the beginning of the queue. */
1314 mep_save_insn (insn
);
1315 /* gas_cgen_save_fixups(num_insns_saved); */
1326 /* Only single instructions are assembled in core mode. */
1329 /* See comment in the VLIW clause above about this. */
1330 if (mep_cop
& EF_MEP_COP_IVC2
)
1331 cgen_bitset_union (isas
, & MEP_COP32_ISA
, isas
);
1333 /* If a leading '+' was present, issue an error.
1334 That's not allowed in core mode. */
1337 as_bad (_("Leading plus sign not allowed in core mode"));
1341 insn
.insn
= mep_cgen_assemble_insn
1342 (gas_cgen_cpu_desc
, str
, & insn
.fields
, insn
.buffer
, & errmsg
);
1346 as_bad ("%s", errmsg
);
1349 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
1350 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1, NULL
);
1351 mep_check_for_disabled_registers (&insn
);
1356 md_section_align (segT segment
, valueT size
)
1358 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1359 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1364 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
1369 /* Interface to relax_segment. */
1372 const relax_typeS md_relax_table
[] =
1375 1) most positive reach of this state,
1376 2) most negative reach of this state,
1377 3) how many bytes this mode will have in the variable part of the frag
1378 4) which index into the table to try if we can't fit into this one. */
1379 /* Note that we use "beq" because "jmp" has a peculiarity - it cannot
1380 jump to addresses with any bits 27..24 set. So, we use beq as a
1381 17-bit pc-relative branch to avoid using jmp, just in case. */
1383 /* 0 */ { 0, 0, 0, 0 }, /* unused */
1384 /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */
1386 /* 2 */ { 2047, -2048, 0, 3 }, /* bsr12 */
1387 /* 3 */ { 0, 0, 2, 0 }, /* bsr16 */
1389 /* 4 */ { 2047, -2048, 0, 5 }, /* bra */
1390 /* 5 */ { 65535, -65536, 2, 6 }, /* beq $0,$0 */
1391 /* 6 */ { 0, 0, 2, 0 }, /* jmp24 */
1393 /* 7 */ { 65535, -65536, 0, 8 }, /* beqi */
1394 /* 8 */ { 0, 0, 4, 0 }, /* bnei/jmp */
1396 /* 9 */ { 127, -128, 0, 10 }, /* beqz */
1397 /* 10 */ { 65535, -65536, 2, 11 }, /* beqi */
1398 /* 11 */ { 0, 0, 4, 0 }, /* bnei/jmp */
1400 /* 12 */ { 65535, -65536, 0, 13 }, /* bnei */
1401 /* 13 */ { 0, 0, 4, 0 }, /* beqi/jmp */
1403 /* 14 */ { 127, -128, 0, 15 }, /* bnez */
1404 /* 15 */ { 65535, -65536, 2, 16 }, /* bnei */
1405 /* 16 */ { 0, 0, 4, 0 }, /* beqi/jmp */
1407 /* 17 */ { 65535, -65536, 0, 13 }, /* bgei */
1408 /* 18 */ { 0, 0, 4, 0 },
1409 /* 19 */ { 65535, -65536, 0, 13 }, /* blti */
1410 /* 20 */ { 0, 0, 4, 0 },
1411 /* 19 */ { 65535, -65536, 0, 13 }, /* bcpeq */
1412 /* 20 */ { 0, 0, 4, 0 },
1413 /* 19 */ { 65535, -65536, 0, 13 }, /* bcpne */
1414 /* 20 */ { 0, 0, 4, 0 },
1415 /* 19 */ { 65535, -65536, 0, 13 }, /* bcpat */
1416 /* 20 */ { 0, 0, 4, 0 },
1417 /* 19 */ { 65535, -65536, 0, 13 }, /* bcpaf */
1418 /* 20 */ { 0, 0, 4, 0 }
1421 /* Pseudo-values for 64 bit "insns" which are combinations of two 32
1425 MEP_PSEUDO64_16BITCC
,
1426 MEP_PSEUDO64_32BITCC
,
1427 } MepPseudo64Values
;
1432 int insn_for_extern
;
1433 } subtype_mappings
[] = {
1436 { MEP_INSN_BSR12
, 0, MEP_INSN_BSR24
},
1437 { MEP_INSN_BSR24
, 2, MEP_INSN_BSR24
},
1438 { MEP_INSN_BRA
, 0, MEP_INSN_BRA
},
1439 { MEP_INSN_BEQ
, 2, MEP_INSN_BEQ
},
1440 { MEP_INSN_JMP
, 2, MEP_INSN_JMP
},
1441 { MEP_INSN_BEQI
, 0, MEP_INSN_BEQI
},
1442 { -1, 4, MEP_PSEUDO64_32BITCC
},
1443 { MEP_INSN_BEQZ
, 0, MEP_INSN_BEQZ
},
1444 { MEP_INSN_BEQI
, 2, MEP_INSN_BEQI
},
1445 { -1, 4, MEP_PSEUDO64_16BITCC
},
1446 { MEP_INSN_BNEI
, 0, MEP_INSN_BNEI
},
1447 { -1, 4, MEP_PSEUDO64_32BITCC
},
1448 { MEP_INSN_BNEZ
, 0, MEP_INSN_BNEZ
},
1449 { MEP_INSN_BNEI
, 2, MEP_INSN_BNEI
},
1450 { -1, 4, MEP_PSEUDO64_16BITCC
},
1451 { MEP_INSN_BGEI
, 0, MEP_INSN_BGEI
},
1452 { -1, 4, MEP_PSEUDO64_32BITCC
},
1453 { MEP_INSN_BLTI
, 0, MEP_INSN_BLTI
},
1454 { -1, 4, MEP_PSEUDO64_32BITCC
},
1455 { MEP_INSN_BCPEQ
, 0, MEP_INSN_BCPEQ
},
1456 { -1, 4, MEP_PSEUDO64_32BITCC
},
1457 { MEP_INSN_BCPNE
, 0, MEP_INSN_BCPNE
},
1458 { -1, 4, MEP_PSEUDO64_32BITCC
},
1459 { MEP_INSN_BCPAT
, 0, MEP_INSN_BCPAT
},
1460 { -1, 4, MEP_PSEUDO64_32BITCC
},
1461 { MEP_INSN_BCPAF
, 0, MEP_INSN_BCPAF
},
1462 { -1, 4, MEP_PSEUDO64_32BITCC
}
1464 #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
1467 mep_prepare_relax_scan (fragS
*fragP
, offsetT
*aim
, relax_substateT this_state
)
1469 symbolS
*symbolP
= fragP
->fr_symbol
;
1470 if (symbolP
&& !S_IS_DEFINED (symbolP
))
1472 /* Adjust for MeP pcrel not being relative to the next opcode. */
1473 *aim
+= 2 + md_relax_table
[this_state
].rlx_length
;
1477 insn_to_subtype (int insn
)
1480 for (i
=0; i
<NUM_MAPPINGS
; i
++)
1481 if (insn
== subtype_mappings
[i
].insn
)
1486 /* Return an initial guess of the length by which a fragment must grow
1487 to hold a branch to reach its destination. Also updates fr_type
1488 and fr_subtype as necessary.
1490 Called just before doing relaxation. Any symbol that is now
1491 undefined will not become defined. The guess for fr_var is
1492 ACTUALLY the growth beyond fr_fix. Whatever we do to grow fr_fix
1493 or fr_var contributes to our returned value. Although it may not
1494 be explicit in the frag, pretend fr_var starts with a 0 value. */
1497 md_estimate_size_before_relax (fragS
* fragP
, segT segment
)
1499 if (fragP
->fr_subtype
== 1)
1500 fragP
->fr_subtype
= insn_to_subtype (fragP
->fr_cgen
.insn
->base
->num
);
1502 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1506 new_insn
= subtype_mappings
[fragP
->fr_subtype
].insn_for_extern
;
1507 fragP
->fr_subtype
= insn_to_subtype (new_insn
);
1510 if (MEP_VLIW
&& ! MEP_VLIW64
1511 && (bfd_get_section_flags (stdoutput
, segment
) & SEC_MEP_VLIW
))
1513 /* Use 32 bit branches for vliw32 so the vliw word is not split. */
1514 switch (fragP
->fr_cgen
.insn
->base
->num
)
1516 case MEP_INSN_BSR12
:
1517 fragP
->fr_subtype
= insn_to_subtype
1518 (subtype_mappings
[fragP
->fr_subtype
].insn_for_extern
);
1521 fragP
->fr_subtype
++;
1524 fragP
->fr_subtype
++;
1529 if (fragP
->fr_cgen
.insn
->base
1530 && fragP
->fr_cgen
.insn
->base
->num
1531 != subtype_mappings
[fragP
->fr_subtype
].insn
)
1533 int new_insn
= subtype_mappings
[fragP
->fr_subtype
].insn
;
1536 fragP
->fr_cgen
.insn
= (fragP
->fr_cgen
.insn
1537 - fragP
->fr_cgen
.insn
->base
->num
1542 return subtype_mappings
[fragP
->fr_subtype
].growth
;
1545 /* *fragP has been relaxed to its final size, and now needs to have
1546 the bytes inside it modified to conform to the new size.
1548 Called after relaxation is finished.
1549 fragP->fr_type == rs_machine_dependent.
1550 fragP->fr_subtype is the subtype of what the address relaxed to. */
1553 target_address_for (fragS
*frag
)
1555 int rv
= frag
->fr_offset
;
1556 symbolS
*sym
= frag
->fr_symbol
;
1559 rv
+= S_GET_VALUE (sym
);
1565 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
1566 segT sec ATTRIBUTE_UNUSED
,
1569 int addend
, rn
, bit
= 0;
1571 int where
= fragP
->fr_opcode
- fragP
->fr_literal
;
1572 int e
= target_big_endian
? 0 : 1;
1574 addend
= target_address_for (fragP
) - (fragP
->fr_address
+ where
);
1576 if (subtype_mappings
[fragP
->fr_subtype
].insn
== -1)
1578 fragP
->fr_fix
+= subtype_mappings
[fragP
->fr_subtype
].growth
;
1579 switch (subtype_mappings
[fragP
->fr_subtype
].insn_for_extern
)
1581 case MEP_PSEUDO64_16BITCC
:
1582 fragP
->fr_opcode
[1^e
] = ((fragP
->fr_opcode
[1^e
] & 1) ^ 1) | 0x06;
1583 fragP
->fr_opcode
[2^e
] = 0xd8;
1584 fragP
->fr_opcode
[3^e
] = 0x08;
1585 fragP
->fr_opcode
[4^e
] = 0;
1586 fragP
->fr_opcode
[5^e
] = 0;
1589 case MEP_PSEUDO64_32BITCC
:
1590 if (fragP
->fr_opcode
[0^e
] & 0x10)
1591 fragP
->fr_opcode
[1^e
] ^= 0x01;
1593 fragP
->fr_opcode
[1^e
] ^= 0x04;
1594 fragP
->fr_opcode
[2^e
] = 0;
1595 fragP
->fr_opcode
[3^e
] = 4;
1596 fragP
->fr_opcode
[4^e
] = 0xd8;
1597 fragP
->fr_opcode
[5^e
] = 0x08;
1598 fragP
->fr_opcode
[6^e
] = 0;
1599 fragP
->fr_opcode
[7^e
] = 0;
1605 fragP
->fr_cgen
.insn
= (fragP
->fr_cgen
.insn
1606 - fragP
->fr_cgen
.insn
->base
->num
1608 operand
= MEP_OPERAND_PCABS24A2
;
1611 switch (fragP
->fr_cgen
.insn
->base
->num
)
1613 case MEP_INSN_BSR12
:
1614 fragP
->fr_opcode
[0^e
] = 0xb0 | ((addend
>> 8) & 0x0f);
1615 fragP
->fr_opcode
[1^e
] = 0x01 | (addend
& 0xfe);
1616 operand
= MEP_OPERAND_PCREL12A2
;
1619 case MEP_INSN_BSR24
:
1621 fragP
->fr_opcode
[0^e
] = 0xd8 | ((addend
>> 5) & 0x07);
1622 fragP
->fr_opcode
[1^e
] = 0x09 | ((addend
<< 3) & 0xf0);
1623 fragP
->fr_opcode
[2^e
] = 0x00 | ((addend
>>16) & 0xff);
1624 fragP
->fr_opcode
[3^e
] = 0x00 | ((addend
>> 8) & 0xff);
1625 operand
= MEP_OPERAND_PCREL24A2
;
1629 fragP
->fr_opcode
[0^e
] = 0xb0 | ((addend
>> 8) & 0x0f);
1630 fragP
->fr_opcode
[1^e
] = 0x00 | (addend
& 0xfe);
1631 operand
= MEP_OPERAND_PCREL12A2
;
1635 /* The default relax_frag doesn't change the state if there is no
1636 growth, so we must manually handle converting out-of-range BEQ
1637 instructions to JMP. */
1638 if (addend
<= 65535 && addend
>= -65536)
1641 fragP
->fr_opcode
[0^e
] = 0xe0;
1642 fragP
->fr_opcode
[1^e
] = 0x01;
1643 fragP
->fr_opcode
[2^e
] = 0x00 | ((addend
>> 9) & 0xff);
1644 fragP
->fr_opcode
[3^e
] = 0x00 | ((addend
>> 1) & 0xff);
1645 operand
= MEP_OPERAND_PCREL17A2
;
1648 /* ...FALLTHROUGH... */
1651 addend
= target_address_for (fragP
);
1653 fragP
->fr_opcode
[0^e
] = 0xd8 | ((addend
>> 5) & 0x07);
1654 fragP
->fr_opcode
[1^e
] = 0x08 | ((addend
<< 3) & 0xf0);
1655 fragP
->fr_opcode
[2^e
] = 0x00 | ((addend
>>16) & 0xff);
1656 fragP
->fr_opcode
[3^e
] = 0x00 | ((addend
>> 8) & 0xff);
1657 operand
= MEP_OPERAND_PCABS24A2
;
1663 fragP
->fr_opcode
[1^e
] = bit
| (addend
& 0xfe);
1664 operand
= MEP_OPERAND_PCREL8A2
;
1670 if (subtype_mappings
[fragP
->fr_subtype
].growth
)
1672 fragP
->fr_fix
+= subtype_mappings
[fragP
->fr_subtype
].growth
;
1673 rn
= fragP
->fr_opcode
[0^e
] & 0x0f;
1674 fragP
->fr_opcode
[0^e
] = 0xe0 | rn
;
1675 fragP
->fr_opcode
[1^e
] = bit
;
1677 fragP
->fr_opcode
[2^e
] = 0x00 | ((addend
>> 9) & 0xff);
1678 fragP
->fr_opcode
[3^e
] = 0x00 | ((addend
>> 1) & 0xff);
1679 operand
= MEP_OPERAND_PCREL17A2
;
1684 case MEP_INSN_BCPEQ
:
1685 case MEP_INSN_BCPNE
:
1686 case MEP_INSN_BCPAT
:
1687 case MEP_INSN_BCPAF
:
1688 /* No opcode change needed, just operand. */
1689 fragP
->fr_opcode
[2^e
] = (addend
>> 9) & 0xff;
1690 fragP
->fr_opcode
[3^e
] = (addend
>> 1) & 0xff;
1691 operand
= MEP_OPERAND_PCREL17A2
;
1698 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
1699 || operand
== MEP_OPERAND_PCABS24A2
)
1701 gas_assert (fragP
->fr_cgen
.insn
!= 0);
1702 gas_cgen_record_fixup (fragP
,
1704 fragP
->fr_cgen
.insn
,
1705 (fragP
->fr_fix
- where
) * 8,
1706 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1708 fragP
->fr_cgen
.opinfo
,
1709 fragP
->fr_symbol
, fragP
->fr_offset
);
1714 /* Functions concerning relocs. */
1717 mep_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1719 /* If we already know the fixup value, adjust it in the same
1720 way that the linker would have done. */
1721 if (fixP
->fx_addsy
== 0)
1722 switch (fixP
->fx_cgen
.opinfo
)
1724 case BFD_RELOC_MEP_LOW16
:
1725 *valP
= ((long)(*valP
& 0xffff)) << 16 >> 16;
1727 case BFD_RELOC_MEP_HI16U
:
1730 case BFD_RELOC_MEP_HI16S
:
1731 *valP
= (*valP
+ 0x8000) >> 16;
1735 /* Now call cgen's md_aply_fix. */
1736 gas_cgen_md_apply_fix (fixP
, valP
, seg
);
1740 md_pcrel_from_section (fixS
*fixP
, segT sec
)
1742 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1743 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1744 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1745 /* The symbol is undefined (or is defined but not in this section).
1746 Let the linker figure it out. */
1749 /* Return the address of the opcode - cgen adjusts for opcode size
1750 itself, to be consistent with the disassembler, which must do
1752 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1755 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1756 Returns BFD_RELOC_NONE if no reloc type can be found.
1757 *FIXP may be modified if desired. */
1759 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1760 #define MAP(n) case MEP_OPERAND_##n: return BFD_RELOC_MEP_##n;
1762 #define MAP(n) case MEP_OPERAND_/**/n: return BFD_RELOC_MEP_/**/n;
1765 bfd_reloc_code_real_type
1766 md_cgen_lookup_reloc (const CGEN_INSN
*insn ATTRIBUTE_UNUSED
,
1767 const CGEN_OPERAND
*operand
,
1770 enum bfd_reloc_code_real reloc
= fixP
->fx_cgen
.opinfo
;
1771 static char printed
[MEP_OPERAND_MAX
] = { 0 };
1773 /* If there's a reloc here, it's because the parser saw a %foo() and
1774 is giving us the correct reloc to use, or because we converted to
1775 a different size reloc below and want to avoid "converting" more
1777 if (reloc
&& reloc
!= BFD_RELOC_NONE
)
1780 switch (operand
->type
)
1782 MAP (PCREL8A2
); /* beqz */
1783 MAP (PCREL12A2
); /* bsr16 */
1784 MAP (PCREL17A2
); /* beqi */
1785 MAP (PCREL24A2
); /* bsr24 */
1786 MAP (PCABS24A2
); /* jmp */
1787 MAP (UIMM24
); /* mov */
1788 MAP (ADDR24A4
); /* sw/lw */
1790 /* The rest of the relocs should be generated by the parser,
1791 for things such as %tprel(), etc. */
1792 case MEP_OPERAND_SIMM16
:
1793 #ifdef OBJ_COMPLEX_RELC
1794 /* coalescing this into RELOC_MEP_16 is actually a bug,
1795 since it's a signed operand. let the relc code handle it. */
1796 return BFD_RELOC_RELC
;
1799 case MEP_OPERAND_UIMM16
:
1800 case MEP_OPERAND_SDISP16
:
1801 case MEP_OPERAND_CODE16
:
1802 fixP
->fx_where
+= 2;
1803 /* to avoid doing the above add twice */
1804 fixP
->fx_cgen
.opinfo
= BFD_RELOC_MEP_16
;
1805 return BFD_RELOC_MEP_16
;
1808 #ifdef OBJ_COMPLEX_RELC
1809 /* this is not an error, yet.
1810 pass it to the linker. */
1811 return BFD_RELOC_RELC
;
1813 if (printed
[operand
->type
])
1814 return BFD_RELOC_NONE
;
1815 printed
[operand
->type
] = 1;
1817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1818 _("Don't know how to relocate plain operands of type %s"),
1821 /* Print some helpful hints for the user. */
1822 switch (operand
->type
)
1824 case MEP_OPERAND_UDISP7
:
1825 case MEP_OPERAND_UDISP7A2
:
1826 case MEP_OPERAND_UDISP7A4
:
1827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1828 _("Perhaps you are missing %%tpoff()?"));
1833 return BFD_RELOC_NONE
;
1837 /* Called while parsing an instruction to create a fixup.
1838 We need to check for HI16 relocs and queue them up for later sorting. */
1841 mep_cgen_record_fixup_exp (fragS
*frag
,
1843 const CGEN_INSN
*insn
,
1845 const CGEN_OPERAND
*operand
,
1849 fixS
* fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
1850 operand
, opinfo
, exp
);
1854 /* Return BFD reloc type from opinfo field in a fixS.
1855 It's tricky using fx_r_type in mep_frob_file because the values
1856 are BFD_RELOC_UNUSED + operand number. */
1857 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
1859 /* Sort any unmatched HI16 relocs so that they immediately precede
1860 the corresponding LO16 reloc. This is called before md_apply_fix and
1866 struct mep_hi_fixup
* l
;
1868 for (l
= mep_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1870 segment_info_type
* seginfo
;
1873 gas_assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_HI16
1874 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_LO16
);
1876 /* Check quickly whether the next fixup happens to be a matching low. */
1877 if (l
->fixp
->fx_next
!= NULL
1878 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_LO16
1879 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1880 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1883 /* Look through the fixups for this segment for a matching
1884 `low'. When we find one, move the high just in front of it.
1885 We do this in two passes. In the first pass, we try to find
1886 a unique `low'. In the second pass, we permit multiple
1887 high's relocs for a single `low'. */
1888 seginfo
= seg_info (l
->seg
);
1889 for (pass
= 0; pass
< 2; pass
++)
1895 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1897 /* Check whether this is a `low' fixup which matches l->fixp. */
1898 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_LO16
1899 && f
->fx_addsy
== l
->fixp
->fx_addsy
1900 && f
->fx_offset
== l
->fixp
->fx_offset
1903 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_HI16
)
1904 || prev
->fx_addsy
!= f
->fx_addsy
1905 || prev
->fx_offset
!= f
->fx_offset
))
1909 /* Move l->fixp before f. */
1910 for (pf
= &seginfo
->fix_root
;
1912 pf
= & (* pf
)->fx_next
)
1913 gas_assert (* pf
!= NULL
);
1915 * pf
= l
->fixp
->fx_next
;
1917 l
->fixp
->fx_next
= f
;
1919 seginfo
->fix_root
= l
->fixp
;
1921 prev
->fx_next
= l
->fixp
;
1933 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1934 _("Unmatched high relocation"));
1939 /* See whether we need to force a relocation into the output file. */
1942 mep_force_relocation (fixS
*fixp
)
1944 if ( fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1945 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1948 /* Allow branches to global symbols to be resolved at assembly time.
1949 This is consistent with way relaxable branches are handled, since
1950 branches to both global and local symbols are relaxed. It also
1951 corresponds to the assumptions made in md_pcrel_from_section. */
1952 return S_FORCE_RELOC (fixp
->fx_addsy
, !fixp
->fx_pcrel
);
1955 /* Write a value out to the object file, using the appropriate endianness. */
1958 md_number_to_chars (char *buf
, valueT val
, int n
)
1960 if (target_big_endian
)
1961 number_to_chars_bigendian (buf
, val
, n
);
1963 number_to_chars_littleendian (buf
, val
, n
);
1967 md_atof (int type
, char *litP
, int *sizeP
)
1969 return ieee_md_atof (type
, litP
, sizeP
, TRUE
);
1973 mep_fix_adjustable (fixS
*fixP
)
1975 bfd_reloc_code_real_type reloc_type
;
1977 if ((int) fixP
->fx_r_type
>= (int) BFD_RELOC_UNUSED
)
1979 const CGEN_INSN
*insn
= NULL
;
1980 int opindex
= (int) fixP
->fx_r_type
- (int) BFD_RELOC_UNUSED
;
1981 const CGEN_OPERAND
*operand
1982 = cgen_operand_lookup_by_num(gas_cgen_cpu_desc
, opindex
);
1983 reloc_type
= md_cgen_lookup_reloc (insn
, operand
, fixP
);
1986 reloc_type
= fixP
->fx_r_type
;
1988 if (fixP
->fx_addsy
== NULL
)
1991 /* Prevent all adjustments to global symbols. */
1992 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
1995 if (S_IS_WEAK (fixP
->fx_addsy
))
1998 /* We need the symbol name for the VTABLE entries */
1999 if (reloc_type
== BFD_RELOC_VTABLE_INHERIT
2000 || reloc_type
== BFD_RELOC_VTABLE_ENTRY
)
2007 mep_elf_section_letter (int letter
, char **ptrmsg
)
2010 return SHF_MEP_VLIW
;
2012 *ptrmsg
= _("Bad .section directive: want a,v,w,x,M,S in string");
2017 mep_elf_section_flags (flagword flags
, bfd_vma attr
, int type ATTRIBUTE_UNUSED
)
2019 if (attr
& SHF_MEP_VLIW
)
2020 flags
|= SEC_MEP_VLIW
;
2024 /* In vliw mode, the default section is .vtext. We have to be able
2025 to switch into .vtext using only the .vtext directive. */
2028 mep_vtext_section (void)
2030 static segT vtext_section
;
2032 if (! vtext_section
)
2034 flagword applicable
= bfd_applicable_section_flags (stdoutput
);
2035 vtext_section
= subseg_new (VTEXT_SECTION_NAME
, 0);
2036 bfd_set_section_flags (stdoutput
, vtext_section
,
2037 applicable
& (SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
2038 | SEC_CODE
| SEC_READONLY
2042 return vtext_section
;
2046 mep_s_vtext (int ignore ATTRIBUTE_UNUSED
)
2050 /* Record previous_section and previous_subsection. */
2051 obj_elf_section_change_hook ();
2053 temp
= get_absolute_expression ();
2054 subseg_set (mep_vtext_section (), (subsegT
) temp
);
2055 demand_empty_rest_of_line ();
2059 mep_switch_to_core_mode (int dummy ATTRIBUTE_UNUSED
)
2061 mep_process_saved_insns ();
2067 mep_switch_to_vliw_mode (int dummy ATTRIBUTE_UNUSED
)
2070 as_bad (_(".vliw unavailable when VLIW is disabled."));
2072 /* Switch into .vtext here too. */
2073 /* mep_s_vtext(); */
2076 /* This is an undocumented pseudo-op used to disable gas's
2077 "disabled_registers" check. Used for code which checks for those
2078 registers at runtime. */
2080 mep_noregerr (int i ATTRIBUTE_UNUSED
)
2082 allow_disabled_registers
= 1;
2085 /* mep_unrecognized_line: This is called when a line that can't be parsed
2086 is encountered. We use it to check for a leading '+' sign which indicates
2087 that the current instruction is a coprocessor instruction that is to be
2088 parallelized with a previous core insn. This function accepts the '+' and
2089 rejects all other characters that might indicate garbage at the beginning
2090 of the line. The '+' character gets lost as the calling loop continues,
2091 so we need to indicate that we saw it. */
2094 mep_unrecognized_line (int ch
)
2100 return 1; /* '+' indicates an instruction to be parallelized. */
2102 return 0; /* If it's not a '+', the line can't be parsed. */
2109 /* Take care of any insns left to be parallelized when the file ends.
2110 This is mainly here to handle the case where the file ends with an
2111 insn preceeded by a + or the file ends unexpectedly. */
2113 mep_process_saved_insns ();
2117 mep_flush_pending_output (void)
2121 mep_process_saved_insns ();