1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
68 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
72 /* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
78 #ifndef DEFAULT_RISCV_ISA_SPEC
79 #define DEFAULT_RISCV_ISA_SPEC "2.2"
82 #ifndef DEFAULT_RISCV_PRIV_SPEC
83 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
86 static const char default_arch
[] = DEFAULT_ARCH
;
87 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
88 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
89 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
91 static unsigned xlen
= 0; /* width of an x-register */
92 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
93 static bfd_boolean rve_abi
= FALSE
;
95 FLOAT_ABI_DEFAULT
= -1,
101 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
103 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
104 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
106 static unsigned elf_flags
= 0;
108 /* Set the default_isa_spec. Return 0 if the input spec string isn't
109 supported. Otherwise, return 1. */
112 riscv_set_default_isa_spec (const char *s
)
114 enum riscv_isa_spec_class
class;
115 if (!riscv_get_isa_spec_class (s
, &class))
117 as_bad ("Unknown default ISA spec `%s' set by "
118 "-misa-spec or --with-isa-spec", s
);
122 default_isa_spec
= class;
126 /* Set the default_priv_spec, assembler will find the suitable CSR address
127 according to default_priv_spec. We will try to check priv attributes if
128 the input string is NULL. Return 0 if the input priv spec string isn't
129 supported. Otherwise, return 1. */
132 riscv_set_default_priv_spec (const char *s
)
134 enum riscv_priv_spec_class
class;
135 unsigned major
, minor
, revision
;
138 /* Find the corresponding priv spec class. */
139 if (riscv_get_priv_spec_class (s
, &class))
141 default_priv_spec
= class;
147 as_bad (_("Unknown default privilege spec `%s' set by "
148 "-mpriv-spec or --with-priv-spec"), s
);
152 /* Try to set the default_priv_spec according to the priv attributes. */
153 attr
= elf_known_obj_attributes_proc (stdoutput
);
154 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
155 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
156 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
158 if (riscv_get_priv_spec_class_from_numbers (major
,
163 /* The priv attributes setting 0.0.0 is meaningless. We should have set
164 the default_priv_spec by md_parse_option and riscv_after_parse_args,
165 so just skip the following setting. */
166 if (class == PRIV_SPEC_CLASS_NONE
)
169 default_priv_spec
= class;
173 /* Still can not find the priv spec class. */
174 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
175 "privilege attributes"), major
, minor
, revision
);
179 /* This is the set of options which the .option pseudo-op may modify. */
181 struct riscv_set_options
183 int pic
; /* Generate position-independent code. */
184 int rvc
; /* Generate RVC code. */
185 int rve
; /* Generate RVE code. */
186 int relax
; /* Emit relocs the linker is allowed to relax. */
187 int arch_attr
; /* Emit arch attribute. */
188 int csr_check
; /* Enable the CSR checking. */
191 static struct riscv_set_options riscv_opts
=
197 DEFAULT_RISCV_ATTR
, /* arch_attr */
202 riscv_set_rvc (bfd_boolean rvc_value
)
205 elf_flags
|= EF_RISCV_RVC
;
207 riscv_opts
.rvc
= rvc_value
;
211 riscv_set_rve (bfd_boolean rve_value
)
213 riscv_opts
.rve
= rve_value
;
216 static riscv_subset_list_t riscv_subsets
;
219 riscv_subset_supports (const char *feature
)
221 struct riscv_subset_t
*subset
;
223 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
226 return riscv_lookup_subset (&riscv_subsets
, feature
, &subset
);
230 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
234 case INSN_CLASS_I
: return riscv_subset_supports ("i");
235 case INSN_CLASS_C
: return riscv_subset_supports ("c");
236 case INSN_CLASS_A
: return riscv_subset_supports ("a");
237 case INSN_CLASS_M
: return riscv_subset_supports ("m");
238 case INSN_CLASS_F
: return riscv_subset_supports ("f");
239 case INSN_CLASS_D
: return riscv_subset_supports ("d");
240 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
242 case INSN_CLASS_F_AND_C
:
243 return (riscv_subset_supports ("f")
244 && riscv_subset_supports ("c"));
245 case INSN_CLASS_D_AND_C
:
246 return (riscv_subset_supports ("d")
247 && riscv_subset_supports ("c"));
249 case INSN_CLASS_ZICSR
:
250 return riscv_subset_supports ("zicsr");
251 case INSN_CLASS_ZIFENCEI
:
252 return riscv_subset_supports ("zifencei");
255 return riscv_subset_supports ("zba");
257 return riscv_subset_supports ("zbb");
259 return riscv_subset_supports ("zbc");
260 case INSN_CLASS_ZBA_OR_ZBB
:
261 return (riscv_subset_supports ("zba")
262 || riscv_subset_supports ("zbb"));
265 as_fatal ("Unreachable");
270 /* Handle of the extension with version hash table. */
271 static htab_t ext_version_hash
= NULL
;
274 init_ext_version_hash (const struct riscv_ext_version
*table
)
277 htab_t hash
= str_htab_create ();
279 while (table
[i
].name
)
281 const char *name
= table
[i
].name
;
282 if (str_hash_insert (hash
, name
, &table
[i
], 0) != NULL
)
283 as_fatal (_("duplicate %s"), name
);
287 && strcmp (table
[i
].name
, name
) == 0)
295 riscv_get_default_ext_version (const char *name
,
299 struct riscv_ext_version
*ext
;
301 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
304 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
307 && strcmp (ext
->name
, name
) == 0)
309 if (ext
->isa_spec_class
== ISA_SPEC_CLASS_DRAFT
310 || ext
->isa_spec_class
== default_isa_spec
)
312 *major_version
= ext
->major_version
;
313 *minor_version
= ext
->minor_version
;
320 /* Set which ISA and extensions are available. */
323 riscv_set_arch (const char *s
)
325 riscv_parse_subset_t rps
;
326 rps
.subset_list
= &riscv_subsets
;
327 rps
.error_handler
= as_bad
;
329 rps
.get_default_version
= riscv_get_default_ext_version
;
334 riscv_release_subset_list (&riscv_subsets
);
335 riscv_parse_subset (&rps
, s
);
338 /* Indicate -mabi= option is explictly set. */
339 static bfd_boolean explicit_mabi
= FALSE
;
342 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
345 float_abi
= new_float_abi
;
349 /* If the -mabi option isn't set, then we set the abi according to the arch
350 string. Otherwise, check if there are conflicts between architecture
354 riscv_set_abi_by_arch (void)
358 if (riscv_subset_supports ("q"))
359 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, FALSE
);
360 else if (riscv_subset_supports ("d"))
361 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, FALSE
);
363 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, FALSE
);
367 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
369 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
370 else if (abi_xlen
< xlen
)
371 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
374 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
375 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
376 elf_flags
|= float_abi
<< 1;
379 elf_flags
|= EF_RISCV_RVE
;
382 /* Handle of the OPCODE hash table. */
383 static htab_t op_hash
= NULL
;
385 /* Handle of the type of .insn hash table. */
386 static htab_t insn_type_hash
= NULL
;
388 /* This array holds the chars that always start a comment. If the
389 pre-processor is disabled, these aren't very useful */
390 const char comment_chars
[] = "#";
392 /* This array holds the chars that only start a comment at the beginning of
393 a line. If the line seems to have the form '# 123 filename'
394 .line and .file directives will appear in the pre-processed output */
395 /* Note that input_file.c hand checks for '#' at the beginning of the
396 first line of the input file. This is because the compiler outputs
397 #NO_APP at the beginning of its output. */
398 /* Also note that C style comments are always supported. */
399 const char line_comment_chars
[] = "#";
401 /* This array holds machine specific line separator characters. */
402 const char line_separator_chars
[] = ";";
404 /* Chars that can be used to separate mant from exp in floating point nums */
405 const char EXP_CHARS
[] = "eE";
407 /* Chars that mean this number is a floating point constant */
410 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
412 /* Indicate we are already assemble any instructions or not. */
413 static bfd_boolean start_assemble
= FALSE
;
415 /* Indicate ELF attributes are explicitly set. */
416 static bfd_boolean explicit_attr
= FALSE
;
418 /* Indicate CSR or priv instructions are explicitly used. */
419 static bfd_boolean explicit_priv_attr
= FALSE
;
421 /* Macros for encoding relaxation state for RVC branches and far jumps. */
422 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
425 | ((uncond) ? 1 : 0) \
428 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
429 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
430 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
431 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
433 /* Is the given value a sign-extended 32-bit value? */
434 #define IS_SEXT_32BIT_NUM(x) \
435 (((x) &~ (offsetT) 0x7fffffff) == 0 \
436 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
438 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
439 #define IS_ZEXT_32BIT_NUM(x) \
440 (((x) &~ (offsetT) 0xffffffff) == 0 \
441 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
443 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
444 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
445 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
446 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
448 /* Determine if an instruction matches an opcode. */
449 #define OPCODE_MATCHES(OPCODE, OP) \
450 (((OPCODE) & MASK_##OP) == MATCH_##OP)
452 static char *expr_end
;
454 /* The default target format to use. */
457 riscv_target_format (void)
459 if (target_big_endian
)
460 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
462 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
465 /* Return the length of instruction INSN. */
467 static inline unsigned int
468 insn_length (const struct riscv_cl_insn
*insn
)
470 return riscv_insn_length (insn
->insn_opcode
);
473 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
476 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
479 insn
->insn_opcode
= mo
->match
;
485 /* Install INSN at the location specified by its "frag" and "where" fields. */
488 install_insn (const struct riscv_cl_insn
*insn
)
490 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
491 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
494 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
495 and install the opcode in the new location. */
498 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
502 if (insn
->fixp
!= NULL
)
504 insn
->fixp
->fx_frag
= frag
;
505 insn
->fixp
->fx_where
= where
;
510 /* Add INSN to the end of the output. */
513 add_fixed_insn (struct riscv_cl_insn
*insn
)
515 char *f
= frag_more (insn_length (insn
));
516 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
520 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
521 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
523 frag_grow (max_chars
);
524 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
525 frag_var (rs_machine_dependent
, max_chars
, var
,
526 subtype
, symbol
, offset
, NULL
);
529 /* Compute the length of a branch sequence, and adjust the stored length
530 accordingly. If FRAGP is NULL, the worst-case length is returned. */
533 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
535 int jump
, rvc
, length
= 8;
540 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
541 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
542 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
544 /* Assume jumps are in range; the linker will catch any that aren't. */
545 length
= jump
? 4 : 8;
547 if (fragp
->fr_symbol
!= NULL
548 && S_IS_DEFINED (fragp
->fr_symbol
)
549 && !S_IS_WEAK (fragp
->fr_symbol
)
550 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
552 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
553 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
554 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
556 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
558 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
560 else if (!jump
&& rvc
)
565 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
570 /* Information about an opcode name, mnemonics and its value. */
577 /* List for all supported opcode name. */
578 static const struct opcode_name_t opcode_name_list
[] =
623 /* Hash table for lookup opcode name. */
624 static htab_t opcode_names_hash
= NULL
;
626 /* Initialization for hash table of opcode name. */
628 init_opcode_names_hash (void)
630 const struct opcode_name_t
*opcode
;
632 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
633 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
634 as_fatal (_("duplicate %s"), opcode
->name
);
637 /* Find `s` is a valid opcode name or not,
638 return the opcode name info if found. */
639 static const struct opcode_name_t
*
640 opcode_name_lookup (char **s
)
644 struct opcode_name_t
*o
;
646 /* Find end of name. */
648 if (is_name_beginner (*e
))
650 while (is_part_of_name (*e
))
653 /* Terminate name. */
657 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
659 /* Advance to next token if one was recognized. */
678 static htab_t reg_names_hash
= NULL
;
679 static htab_t csr_extra_hash
= NULL
;
681 #define ENCODE_REG_HASH(cls, n) \
682 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
683 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
684 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
687 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
689 void *hash
= ENCODE_REG_HASH (class, n
);
690 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
691 as_fatal (_("duplicate %s"), name
);
695 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
699 for (i
= 0; i
< n
; i
++)
700 hash_reg_name (class, names
[i
], i
);
703 /* Init hash table csr_extra_hash to handle CSR. */
705 riscv_init_csr_hash (const char *name
,
707 enum riscv_csr_class
class,
708 enum riscv_priv_spec_class define_version
,
709 enum riscv_priv_spec_class abort_version
)
711 struct riscv_csr_extra
*entry
, *pre_entry
;
712 bfd_boolean need_enrty
= TRUE
;
715 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
716 while (need_enrty
&& entry
!= NULL
)
718 if (entry
->csr_class
== class
719 && entry
->address
== address
720 && entry
->define_version
== define_version
721 && entry
->abort_version
== abort_version
)
727 /* Duplicate setting for the CSR, just return and do nothing. */
731 entry
= XNEW (struct riscv_csr_extra
);
732 entry
->csr_class
= class;
733 entry
->address
= address
;
734 entry
->define_version
= define_version
;
735 entry
->abort_version
= abort_version
;
738 /* If the CSR hasn't been inserted in the hash table, then insert it.
739 Otherwise, attach the extra information to the entry which is already
740 in the hash table. */
741 if (pre_entry
== NULL
)
742 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
744 pre_entry
->next
= entry
;
747 /* Return the suitable CSR address after checking the ISA dependency and
748 priv spec versions. */
751 riscv_csr_address (const char *csr_name
,
752 struct riscv_csr_extra
*entry
)
754 struct riscv_csr_extra
*saved_entry
= entry
;
755 enum riscv_csr_class csr_class
= entry
->csr_class
;
756 bfd_boolean need_check_version
= TRUE
;
757 bfd_boolean result
= TRUE
;
762 result
= riscv_subset_supports ("i");
765 result
= (xlen
== 32 && riscv_subset_supports ("i"));
768 result
= riscv_subset_supports ("f");
769 need_check_version
= FALSE
;
771 case CSR_CLASS_DEBUG
:
772 need_check_version
= FALSE
;
775 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
778 /* Don't report the ISA conflict when -mcsr-check isn't set. */
779 if (riscv_opts
.csr_check
&& !result
)
780 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name
);
782 while (entry
!= NULL
)
784 if (!need_check_version
785 || (default_priv_spec
>= entry
->define_version
786 && default_priv_spec
< entry
->abort_version
))
788 /* Find the suitable CSR according to the specific version. */
789 return entry
->address
;
794 /* We can not find the suitable CSR address according to the privilege
795 version. Therefore, we use the last defined value. Report the warning
796 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
797 otherwise, you may get the unexpected CSR address. */
798 if (riscv_opts
.csr_check
)
800 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
802 if (priv_name
!= NULL
)
803 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
804 csr_name
, priv_name
);
807 return saved_entry
->address
;
810 /* Once the CSR is defined, including the old privilege spec, then we call
811 riscv_csr_class_check and riscv_csr_version_check to do the further checking
812 and get the corresponding address. Return -1 if the CSR is never been
813 defined. Otherwise, return the address. */
816 reg_csr_lookup_internal (const char *s
)
818 struct riscv_csr_extra
*r
=
819 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
824 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
825 the CSR was defined, but isn't allowed for the current ISA setting or
826 the privilege spec. If the CSR is never been defined, then assembler
827 will regard it as a "Unknown CSR" and report error. If user use number
828 to set the CSR, but over the range (> 0xfff), then assembler will report
829 "Improper CSR" error for it. */
830 return riscv_csr_address (s
, r
);
834 reg_lookup_internal (const char *s
, enum reg_class
class)
838 if (class == RCLASS_CSR
)
839 return reg_csr_lookup_internal (s
);
841 r
= str_hash_find (reg_names_hash
, s
);
842 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
845 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
848 return DECODE_REG_NUM (r
);
852 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
858 /* Find end of name. */
860 if (is_name_beginner (*e
))
862 while (is_part_of_name (*e
))
865 /* Terminate name. */
869 /* Look for the register. Advance to next token if one was recognized. */
870 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
880 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
882 const char *p
= strchr (*s
, ',');
883 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
888 for (i
= 0; i
< size
; i
++)
889 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
899 /* For consistency checking, verify that all bits are specified either
900 by the match/mask part of the instruction definition, or by the
903 `length` could be 0, 4 or 8, 0 for auto detection. */
905 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
907 const char *p
= opc
->args
;
909 insn_t used_bits
= opc
->mask
;
911 insn_t required_bits
;
914 insn_width
= 8 * riscv_insn_length (opc
->match
);
916 insn_width
= 8 * length
;
918 required_bits
= ~0ULL >> (64 - insn_width
);
920 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
922 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
923 opc
->name
, opc
->args
);
927 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
934 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
935 case 'c': break; /* RS1, constrained to equal sp */
936 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
937 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
938 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
939 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
940 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
941 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
942 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
943 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
944 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
945 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
946 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
947 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
948 case 'w': break; /* RS1S, constrained to equal RD */
949 case 'x': break; /* RS2S, constrained to equal RD */
950 case 'z': break; /* RS2S, contrained to be x0 */
951 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
952 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
953 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
954 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
955 case 'U': break; /* RS1, constrained to equal RD */
956 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
957 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
958 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
959 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
960 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
961 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
962 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
963 case 'F': /* funct */
966 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
967 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
968 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
969 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
971 as_bad (_("internal: bad RISC-V opcode"
972 " (unknown operand type `CF%c'): %s %s"),
973 c
, opc
->name
, opc
->args
);
978 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
979 c
, opc
->name
, opc
->args
);
986 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
987 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
989 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
990 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
991 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
993 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
994 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
995 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
996 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
997 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
998 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
999 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1000 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1001 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1002 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1003 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1005 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1006 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
1007 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
1008 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1009 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1015 case 'F': /* funct */
1018 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1019 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1020 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1022 as_bad (_("internal: bad RISC-V opcode"
1023 " (unknown operand type `F%c'): %s %s"),
1024 c
, opc
->name
, opc
->args
);
1028 case 'O': /* opcode */
1031 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1032 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1034 as_bad (_("internal: bad RISC-V opcode"
1035 " (unknown operand type `F%c'): %s %s"),
1036 c
, opc
->name
, opc
->args
);
1041 as_bad (_("internal: bad RISC-V opcode "
1042 "(unknown operand type `%c'): %s %s"),
1043 c
, opc
->name
, opc
->args
);
1047 if (used_bits
!= required_bits
)
1049 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1050 ~(unsigned long)(used_bits
& required_bits
),
1051 opc
->name
, opc
->args
);
1057 struct percent_op_match
1060 bfd_reloc_code_real_type reloc
;
1063 /* Common hash table initialization function for
1064 instruction and .insn directive. */
1066 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1067 bfd_boolean insn_directive_p
)
1071 htab_t hash
= str_htab_create ();
1072 while (opcodes
[i
].name
)
1074 const char *name
= opcodes
[i
].name
;
1075 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1076 as_fatal (_("duplicate %s"), name
);
1080 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1082 if (insn_directive_p
)
1083 length
= ((name
[0] == 'c') ? 2 : 4);
1085 length
= 0; /* Let assembler determine the length. */
1086 if (!validate_riscv_insn (&opcodes
[i
], length
))
1087 as_fatal (_("Broken assembler. No assembly attempted."));
1090 gas_assert (!insn_directive_p
);
1093 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1099 /* This function is called once, at assembler startup time. It should set up
1100 all the tables, etc. that the MD part of the assembler will need. */
1105 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1107 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1108 as_warn (_("Could not set architecture and machine"));
1110 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1111 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1113 reg_names_hash
= str_htab_create ();
1114 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1115 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1116 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1117 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1118 /* Add "fp" as an alias for "s0". */
1119 hash_reg_name (RCLASS_GPR
, "fp", 8);
1121 /* Create and insert CSR hash tables. */
1122 csr_extra_hash
= str_htab_create ();
1123 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1124 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1125 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1126 DECLARE_CSR(name, num, class, define_version, abort_version);
1127 #include "opcode/riscv-opc.h"
1130 opcode_names_hash
= str_htab_create ();
1131 init_opcode_names_hash ();
1133 /* Set the default alignment for the text section. */
1134 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1138 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1145 case BFD_RELOC_RISCV_HI20
:
1146 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1148 case BFD_RELOC_RISCV_LO12_S
:
1149 return ENCODE_STYPE_IMM (value
);
1151 case BFD_RELOC_RISCV_LO12_I
:
1152 return ENCODE_ITYPE_IMM (value
);
1159 /* Output an instruction. IP is the instruction information.
1160 ADDRESS_EXPR is an operand of the instruction to be used with
1164 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1165 bfd_reloc_code_real_type reloc_type
)
1167 dwarf2_emit_insn (0);
1169 if (reloc_type
!= BFD_RELOC_UNUSED
)
1171 reloc_howto_type
*howto
;
1173 gas_assert (address_expr
);
1174 if (reloc_type
== BFD_RELOC_12_PCREL
1175 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1177 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1178 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1179 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1181 if (now_seg
== absolute_section
)
1183 as_bad (_("relaxable branches not supported in absolute section"));
1187 add_relaxed_insn (ip
, worst_case
, best_case
,
1188 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1189 address_expr
->X_add_symbol
,
1190 address_expr
->X_add_number
);
1195 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1197 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1199 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1200 bfd_get_reloc_size (howto
),
1201 address_expr
, FALSE
, reloc_type
);
1203 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1207 add_fixed_insn (ip
);
1210 /* We need to start a new frag after any instruction that can be
1211 optimized away or compressed by the linker during relaxation, to prevent
1212 the assembler from computing static offsets across such an instruction.
1213 This is necessary to get correct EH info. */
1214 if (reloc_type
== BFD_RELOC_RISCV_HI20
1215 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1216 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1217 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1219 frag_wane (frag_now
);
1224 /* Build an instruction created by a macro expansion. This is passed
1225 a pointer to the count of instructions created so far, an
1226 expression, the name of the instruction to build, an operand format
1227 string, and corresponding arguments. */
1230 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1232 const struct riscv_opcode
*mo
;
1233 struct riscv_cl_insn insn
;
1234 bfd_reloc_code_real_type r
;
1237 va_start (args
, fmt
);
1239 r
= BFD_RELOC_UNUSED
;
1240 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1243 /* Find a non-RVC variant of the instruction. append_insn will compress
1245 while (riscv_insn_length (mo
->match
) < 4)
1247 gas_assert (strcmp (name
, mo
->name
) == 0);
1249 create_insn (&insn
, mo
);
1255 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1259 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1263 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1267 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1273 gas_assert (ep
!= NULL
);
1274 r
= va_arg (args
, int);
1282 as_fatal (_("internal error: invalid macro"));
1287 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1289 append_insn (&insn
, ep
, r
);
1292 /* Build an instruction created by a macro expansion. Like md_assemble but
1293 accept a printf-style format string and arguments. */
1296 md_assemblef (const char *format
, ...)
1302 va_start (ap
, format
);
1304 r
= vasprintf (&buf
, format
, ap
);
1307 as_fatal (_("internal error: vasprintf failed"));
1315 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1318 normalize_constant_expr (expressionS
*ex
)
1322 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1323 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1324 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1328 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1329 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1332 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1333 bfd_boolean maybe_csr
)
1335 if (ex
->X_op
== O_big
)
1336 as_bad (_("unsupported large constant"));
1337 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1338 as_bad (_("unknown CSR `%s'"),
1339 S_GET_NAME (ex
->X_add_symbol
));
1340 else if (ex
->X_op
!= O_constant
)
1341 as_bad (_("Instruction %s requires absolute expression"),
1343 normalize_constant_expr (ex
);
1347 make_internal_label (void)
1349 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1353 /* Load an entry from the GOT. */
1355 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1356 const char *lo_insn
, const char *lo_pattern
,
1357 bfd_reloc_code_real_type hi_reloc
,
1358 bfd_reloc_code_real_type lo_reloc
)
1361 ep2
.X_op
= O_symbol
;
1362 ep2
.X_add_symbol
= make_internal_label ();
1363 ep2
.X_add_number
= 0;
1365 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1366 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1370 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1371 bfd_reloc_code_real_type hi_reloc
,
1372 bfd_reloc_code_real_type lo_reloc
)
1374 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1378 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1379 bfd_reloc_code_real_type hi_reloc
,
1380 bfd_reloc_code_real_type lo_reloc
)
1382 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1385 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1387 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1388 bfd_reloc_code_real_type reloc
)
1390 /* Ensure the jalr is emitted to the same frag as the auipc. */
1392 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1393 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1394 /* See comment at end of append_insn. */
1395 frag_wane (frag_now
);
1399 /* Load an integer constant into a register. */
1402 load_const (int reg
, expressionS
*ep
)
1404 int shift
= RISCV_IMM_BITS
;
1405 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1406 expressionS upper
= *ep
, lower
= *ep
;
1407 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1408 upper
.X_add_number
-= lower
.X_add_number
;
1410 if (ep
->X_op
!= O_constant
)
1412 as_bad (_("unsupported large constant"));
1416 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1418 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1419 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1422 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1423 load_const (reg
, &upper
);
1425 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1426 if (lower
.X_add_number
!= 0)
1427 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1428 lower
.X_add_number
);
1432 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1435 if (upper
.X_add_number
!= 0)
1437 /* Discard low part and zero-extend upper immediate. */
1438 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1440 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1444 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1445 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1446 lower
.X_add_number
);
1450 /* Zero extend and sign extend byte/half-word/word. */
1453 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bfd_boolean sign
)
1457 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1458 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1462 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1463 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1467 /* Expand RISC-V assembly macros into one or more instructions. */
1470 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1471 bfd_reloc_code_real_type
*imm_reloc
)
1473 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1474 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1475 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1476 int mask
= ip
->insn_mo
->mask
;
1481 load_const (rd
, imm_expr
);
1486 /* Load the address of a symbol into a register. */
1487 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1488 as_bad (_("offset too large"));
1490 if (imm_expr
->X_op
== O_constant
)
1491 load_const (rd
, imm_expr
);
1492 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1493 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1494 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1495 else /* Local PIC symbol, or any non-PIC symbol */
1496 pcrel_load (rd
, rd
, imm_expr
, "addi",
1497 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1501 pcrel_load (rd
, rd
, imm_expr
, "addi",
1502 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1506 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1507 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1511 pcrel_load (rd
, rd
, imm_expr
, "lb",
1512 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1516 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1517 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1521 pcrel_load (rd
, rd
, imm_expr
, "lh",
1522 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1526 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1527 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1531 pcrel_load (rd
, rd
, imm_expr
, "lw",
1532 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1536 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1537 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1541 pcrel_load (rd
, rd
, imm_expr
, "ld",
1542 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1546 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1547 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1551 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1552 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1556 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1557 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1561 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1562 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1566 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1567 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1571 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1572 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1576 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1577 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1581 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1582 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1586 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1590 riscv_ext (rd
, rs1
, xlen
- 16, FALSE
);
1594 riscv_ext (rd
, rs1
, xlen
- 32, FALSE
);
1598 riscv_ext (rd
, rs1
, xlen
- 8, TRUE
);
1602 riscv_ext (rd
, rs1
, xlen
- 16, TRUE
);
1606 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1611 static const struct percent_op_match percent_op_utype
[] =
1613 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1614 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1615 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1616 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1617 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1618 {"%hi", BFD_RELOC_RISCV_HI20
},
1622 static const struct percent_op_match percent_op_itype
[] =
1624 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1625 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1626 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1630 static const struct percent_op_match percent_op_stype
[] =
1632 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1633 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1634 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1638 static const struct percent_op_match percent_op_rtype
[] =
1640 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1644 static const struct percent_op_match percent_op_null
[] =
1649 /* Return true if *STR points to a relocation operator. When returning true,
1650 move *STR over the operator and store its relocation code in *RELOC.
1651 Leave both *STR and *RELOC alone when returning false. */
1654 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1655 const struct percent_op_match
*percent_op
)
1657 for ( ; percent_op
->str
; percent_op
++)
1658 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1660 int len
= strlen (percent_op
->str
);
1662 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1665 *str
+= strlen (percent_op
->str
);
1666 *reloc
= percent_op
->reloc
;
1668 /* Check whether the output BFD supports this relocation.
1669 If not, issue an error and fall back on something safe. */
1670 if (*reloc
!= BFD_RELOC_UNUSED
1671 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1673 as_bad ("relocation %s isn't supported by the current ABI",
1675 *reloc
= BFD_RELOC_UNUSED
;
1683 my_getExpression (expressionS
*ep
, char *str
)
1687 save_in
= input_line_pointer
;
1688 input_line_pointer
= str
;
1690 expr_end
= input_line_pointer
;
1691 input_line_pointer
= save_in
;
1694 /* Parse string STR as a 16-bit relocatable operand. Store the
1695 expression in *EP and the relocation, if any, in RELOC.
1696 Return the number of relocation operators used (0 or 1).
1698 On exit, EXPR_END points to the first character after the expression. */
1701 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1702 char *str
, const struct percent_op_match
*percent_op
)
1705 unsigned crux_depth
, str_depth
, regno
;
1708 /* First, check for integer registers. No callers can accept a reg, but
1709 we need to avoid accidentally creating a useless undefined symbol below,
1710 if this is an instruction pattern that can't match. A glibc build fails
1711 if this is removed. */
1712 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1714 ep
->X_op
= O_register
;
1715 ep
->X_add_number
= regno
;
1720 /* Search for the start of the main expression.
1721 End the loop with CRUX pointing to the start
1722 of the main expression and with CRUX_DEPTH containing the number
1723 of open brackets at that point. */
1730 crux_depth
= str_depth
;
1732 /* Skip over whitespace and brackets, keeping count of the number
1734 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1740 && parse_relocation (&str
, reloc
, percent_op
));
1742 my_getExpression (ep
, crux
);
1745 /* Match every open bracket. */
1746 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1751 as_bad ("unclosed '('");
1758 /* Parse opcode name, could be an mnemonics or number. */
1760 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1761 char *str
, const struct percent_op_match
*percent_op
)
1763 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1767 ep
->X_op
= O_constant
;
1768 ep
->X_add_number
= o
->val
;
1772 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1775 /* Detect and handle implicitly zero load-store offsets. For example,
1776 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1777 an implicit offset was detected. */
1780 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1782 /* Check whether there is only a single bracketed expression left.
1783 If so, it must be the base register and the constant must be zero. */
1784 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1786 ep
->X_op
= O_constant
;
1787 ep
->X_add_number
= 0;
1794 /* All RISC-V CSR instructions belong to one of these classes. */
1804 /* Return which CSR instruction is checking. */
1806 static enum csr_insn_type
1807 riscv_csr_insn_type (insn_t insn
)
1809 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1810 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1812 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1813 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1815 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1816 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1819 return INSN_NOT_CSR
;
1822 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1823 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1824 CSR address is 0x3. */
1827 riscv_csr_read_only_check (insn_t insn
)
1829 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1830 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1831 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1832 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1835 && (((csr_insn
== INSN_CSRRS
1836 || csr_insn
== INSN_CSRRC
)
1838 || csr_insn
== INSN_CSRRW
))
1844 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1846 uret is actually a N-ext instruction. So it is better to regard it as
1847 an user instruction rather than the priv instruction.
1849 hret is used to return from traps in H-mode. H-mode is removed since
1850 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1851 Therefore, hret should be controlled by the hypervisor spec rather than
1852 priv spec in the future.
1854 dret is defined in the debug spec, so it should be checked in the future,
1858 riscv_is_priv_insn (insn_t insn
)
1860 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1861 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1862 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1863 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1864 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1865 check it here to keep the compatible. Maybe we should issue warning
1866 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1867 We already have a similar check for CSR, but not yet for instructions.
1868 It would be good if we could check the spec versions both for CSR and
1869 instructions, but not here. */
1870 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1873 /* This routine assembles an instruction into its binary format. As a
1874 side effect, it sets the global variable imm_reloc to the type of
1875 relocation to do if one of the operands is an address expression. */
1878 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1879 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1884 struct riscv_opcode
*insn
;
1889 const struct percent_op_match
*p
;
1890 const char *error
= "unrecognized opcode";
1891 /* Indicate we are assembling instruction with CSR. */
1892 bfd_boolean insn_with_csr
= FALSE
;
1894 /* Parse the name of the instruction. Terminate the string if whitespace
1895 is found so that str_hash_find only sees the name part of the string. */
1896 for (s
= str
; *s
!= '\0'; ++s
)
1904 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
1907 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1909 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1912 if (!riscv_multi_subset_supports (insn
->insn_class
))
1915 create_insn (ip
, insn
);
1918 imm_expr
->X_op
= O_absent
;
1919 *imm_reloc
= BFD_RELOC_UNUSED
;
1920 p
= percent_op_itype
;
1922 for (args
= insn
->args
;; ++args
)
1924 s
+= strspn (s
, " \t");
1927 case '\0': /* End of args. */
1928 if (insn
->pinfo
!= INSN_MACRO
)
1930 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1933 /* For .insn, insn->match and insn->mask are 0. */
1934 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1940 if (riscv_is_priv_insn (ip
->insn_opcode
))
1941 explicit_priv_attr
= TRUE
;
1943 /* Check if we write a read-only CSR by the CSR
1946 && riscv_opts
.csr_check
1947 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1949 /* Restore the character in advance, since we want to
1950 report the detailed warning message here. */
1952 *(argsStart
- 1) = save_c
;
1953 as_warn (_("Read-only CSR is written `%s'"), str
);
1954 insn_with_csr
= FALSE
;
1959 /* Successful assembly. */
1961 insn_with_csr
= FALSE
;
1967 case 's': /* RS1 x8-x15 */
1968 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1969 || !(regno
>= 8 && regno
<= 15))
1971 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1973 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1974 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1975 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1978 case 't': /* RS2 x8-x15 */
1979 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1980 || !(regno
>= 8 && regno
<= 15))
1982 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1984 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1985 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1986 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1989 case 'U': /* RS1, constrained to equal RD. */
1990 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1991 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1995 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1997 INSERT_OPERAND (CRS2
, *ip
, regno
);
1999 case 'c': /* RS1, constrained to equal sp. */
2000 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2004 case 'z': /* RS2, contrained to equal x0. */
2005 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2010 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2011 || imm_expr
->X_op
!= O_constant
2012 || imm_expr
->X_add_number
<= 0
2013 || imm_expr
->X_add_number
>= 64)
2015 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2018 imm_expr
->X_op
= O_absent
;
2021 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2022 || imm_expr
->X_op
!= O_constant
2023 || imm_expr
->X_add_number
<= 0
2024 || imm_expr
->X_add_number
>= 32
2025 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2027 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2030 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2031 || imm_expr
->X_op
!= O_constant
2032 || imm_expr
->X_add_number
< 0
2033 || imm_expr
->X_add_number
>= 256
2034 || !VALID_RVC_UIMM8 ((valueT
) imm_expr
->X_add_number
))
2036 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
2039 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2040 || imm_expr
->X_op
!= O_constant
2041 || imm_expr
->X_add_number
== 0
2042 || !VALID_RVC_SIMM3 ((valueT
) imm_expr
->X_add_number
))
2044 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
2047 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2048 || imm_expr
->X_op
!= O_constant
2049 || imm_expr
->X_add_number
== 0
2050 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2052 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2055 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2057 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2058 || imm_expr
->X_op
!= O_constant
2059 || !VALID_RVC_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2061 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
2064 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2066 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2067 || imm_expr
->X_op
!= O_constant
2068 || !VALID_RVC_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2070 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
2073 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2075 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2076 || imm_expr
->X_op
!= O_constant
2077 || !VALID_RVC_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2080 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
2083 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2085 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2086 || imm_expr
->X_op
!= O_constant
2087 || !VALID_RVC_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2090 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2093 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2094 || imm_expr
->X_op
!= O_constant
2095 /* C.addiw, c.li, and c.andi allow zero immediate.
2096 C.addi allows zero immediate as hint. Otherwise this
2098 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2100 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2103 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2104 || imm_expr
->X_op
!= O_constant
2105 || imm_expr
->X_add_number
== 0
2106 || !VALID_RVC_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2109 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2112 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2113 || imm_expr
->X_op
!= O_constant
2114 || imm_expr
->X_add_number
== 0
2115 || !VALID_RVC_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2118 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2121 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2123 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2124 || imm_expr
->X_op
!= O_constant
2125 || !VALID_RVC_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2128 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2131 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2133 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2134 || imm_expr
->X_op
!= O_constant
2135 || !VALID_RVC_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2138 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2141 p
= percent_op_utype
;
2142 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2145 if (imm_expr
->X_op
!= O_constant
2146 || imm_expr
->X_add_number
<= 0
2147 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2148 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2149 && (imm_expr
->X_add_number
<
2150 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2152 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2155 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2156 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2157 || ((int32_t)imm_expr
->X_add_number
2158 != imm_expr
->X_add_number
))
2160 imm_expr
->X_add_number
=
2161 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2167 case 'S': /* Floating-point RS1 x8-x15. */
2168 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2169 || !(regno
>= 8 && regno
<= 15))
2171 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2173 case 'D': /* Floating-point RS2 x8-x15. */
2174 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2175 || !(regno
>= 8 && regno
<= 15))
2177 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2179 case 'T': /* Floating-point RS2. */
2180 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2182 INSERT_OPERAND (CRS2
, *ip
, regno
);
2188 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2189 || imm_expr
->X_op
!= O_constant
2190 || imm_expr
->X_add_number
< 0
2191 || imm_expr
->X_add_number
>= 64)
2193 as_bad (_("bad value for funct6 field, "
2194 "value must be 0...64"));
2198 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2199 imm_expr
->X_op
= O_absent
;
2203 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2204 || imm_expr
->X_op
!= O_constant
2205 || imm_expr
->X_add_number
< 0
2206 || imm_expr
->X_add_number
>= 16)
2208 as_bad (_("bad value for funct4 field, "
2209 "value must be 0...15"));
2213 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2214 imm_expr
->X_op
= O_absent
;
2218 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2219 || imm_expr
->X_op
!= O_constant
2220 || imm_expr
->X_add_number
< 0
2221 || imm_expr
->X_add_number
>= 8)
2223 as_bad (_("bad value for funct3 field, "
2224 "value must be 0...7"));
2227 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2228 imm_expr
->X_op
= O_absent
;
2232 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2233 || imm_expr
->X_op
!= O_constant
2234 || imm_expr
->X_add_number
< 0
2235 || imm_expr
->X_add_number
>= 4)
2237 as_bad (_("bad value for funct2 field, "
2238 "value must be 0...3"));
2241 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2242 imm_expr
->X_op
= O_absent
;
2246 as_bad (_("bad compressed FUNCT field"
2247 " specifier 'CF%c'\n"),
2253 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2272 case '<': /* Shift amount, 0 - 31. */
2273 my_getExpression (imm_expr
, s
);
2274 check_absolute_expr (ip
, imm_expr
, FALSE
);
2275 if ((unsigned long) imm_expr
->X_add_number
> 31)
2276 as_bad (_("Improper shift amount (%lu)"),
2277 (unsigned long) imm_expr
->X_add_number
);
2278 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2279 imm_expr
->X_op
= O_absent
;
2283 case '>': /* Shift amount, 0 - (XLEN-1). */
2284 my_getExpression (imm_expr
, s
);
2285 check_absolute_expr (ip
, imm_expr
, FALSE
);
2286 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2287 as_bad (_("Improper shift amount (%lu)"),
2288 (unsigned long) imm_expr
->X_add_number
);
2289 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2290 imm_expr
->X_op
= O_absent
;
2294 case 'Z': /* CSRRxI immediate. */
2295 my_getExpression (imm_expr
, s
);
2296 check_absolute_expr (ip
, imm_expr
, FALSE
);
2297 if ((unsigned long) imm_expr
->X_add_number
> 31)
2298 as_bad (_("Improper CSRxI immediate (%lu)"),
2299 (unsigned long) imm_expr
->X_add_number
);
2300 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2301 imm_expr
->X_op
= O_absent
;
2305 case 'E': /* Control register. */
2306 insn_with_csr
= TRUE
;
2307 explicit_priv_attr
= TRUE
;
2308 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2309 INSERT_OPERAND (CSR
, *ip
, regno
);
2312 my_getExpression (imm_expr
, s
);
2313 check_absolute_expr (ip
, imm_expr
, TRUE
);
2314 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2315 as_bad (_("Improper CSR address (%lu)"),
2316 (unsigned long) imm_expr
->X_add_number
);
2317 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2318 imm_expr
->X_op
= O_absent
;
2323 case 'm': /* Rounding mode. */
2324 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2326 INSERT_OPERAND (RM
, *ip
, regno
);
2332 case 'Q': /* Fence predecessor/successor. */
2333 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2337 INSERT_OPERAND (PRED
, *ip
, regno
);
2339 INSERT_OPERAND (SUCC
, *ip
, regno
);
2344 case 'd': /* Destination register. */
2345 case 's': /* Source register. */
2346 case 't': /* Target register. */
2347 case 'r': /* rs3. */
2348 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2354 /* Now that we have assembled one operand, we use the args
2355 string to figure out where it goes in the instruction. */
2359 INSERT_OPERAND (RS1
, *ip
, regno
);
2362 INSERT_OPERAND (RD
, *ip
, regno
);
2365 INSERT_OPERAND (RS2
, *ip
, regno
);
2368 INSERT_OPERAND (RS3
, *ip
, regno
);
2375 case 'D': /* Floating point rd. */
2376 case 'S': /* Floating point rs1. */
2377 case 'T': /* Floating point rs2. */
2378 case 'U': /* Floating point rs1 and rs2. */
2379 case 'R': /* Floating point rs3. */
2380 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2388 INSERT_OPERAND (RD
, *ip
, regno
);
2391 INSERT_OPERAND (RS1
, *ip
, regno
);
2394 INSERT_OPERAND (RS1
, *ip
, regno
);
2397 INSERT_OPERAND (RS2
, *ip
, regno
);
2400 INSERT_OPERAND (RS3
, *ip
, regno
);
2409 my_getExpression (imm_expr
, s
);
2410 if (imm_expr
->X_op
!= O_big
2411 && imm_expr
->X_op
!= O_constant
)
2413 normalize_constant_expr (imm_expr
);
2418 my_getExpression (imm_expr
, s
);
2419 normalize_constant_expr (imm_expr
);
2420 /* The 'A' format specifier must be a symbol. */
2421 if (imm_expr
->X_op
!= O_symbol
)
2423 *imm_reloc
= BFD_RELOC_32
;
2428 my_getExpression (imm_expr
, s
);
2429 normalize_constant_expr (imm_expr
);
2430 /* The 'B' format specifier must be a symbol or a constant. */
2431 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2433 if (imm_expr
->X_op
== O_symbol
)
2434 *imm_reloc
= BFD_RELOC_32
;
2438 case 'j': /* Sign-extended immediate. */
2439 p
= percent_op_itype
;
2440 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2442 case 'q': /* Store displacement. */
2443 p
= percent_op_stype
;
2444 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2446 case 'o': /* Load displacement. */
2447 p
= percent_op_itype
;
2448 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2450 case '1': /* 4-operand add, must be %tprel_add. */
2451 p
= percent_op_rtype
;
2453 case '0': /* AMO "displacement," which must be zero. */
2454 p
= percent_op_null
;
2456 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2459 /* If this value won't fit into a 16 bit offset, then go
2460 find a macro that will generate the 32 bit offset
2462 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2464 normalize_constant_expr (imm_expr
);
2465 if (imm_expr
->X_op
!= O_constant
2466 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2468 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2469 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2476 case 'p': /* PC-relative offset. */
2478 *imm_reloc
= BFD_RELOC_12_PCREL
;
2479 my_getExpression (imm_expr
, s
);
2483 case 'u': /* Upper 20 bits. */
2484 p
= percent_op_utype
;
2485 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2487 if (imm_expr
->X_op
!= O_constant
)
2490 if (imm_expr
->X_add_number
< 0
2491 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2492 as_bad (_("lui expression not in range 0..1048575"));
2494 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2495 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2500 case 'a': /* 20-bit PC-relative offset. */
2502 my_getExpression (imm_expr
, s
);
2504 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2508 my_getExpression (imm_expr
, s
);
2510 if (strcmp (s
, "@plt") == 0)
2512 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2516 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2522 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2523 || imm_expr
->X_op
!= O_constant
2524 || imm_expr
->X_add_number
< 0
2525 || imm_expr
->X_add_number
>= 128
2526 || (imm_expr
->X_add_number
& 0x3) != 3)
2528 as_bad (_("bad value for opcode field, "
2529 "value must be 0...127 and "
2530 "lower 2 bits must be 0x3"));
2534 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2535 imm_expr
->X_op
= O_absent
;
2539 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2540 || imm_expr
->X_op
!= O_constant
2541 || imm_expr
->X_add_number
< 0
2542 || imm_expr
->X_add_number
>= 3)
2544 as_bad (_("bad value for opcode field, "
2545 "value must be 0...2"));
2549 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2550 imm_expr
->X_op
= O_absent
;
2554 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2562 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2563 || imm_expr
->X_op
!= O_constant
2564 || imm_expr
->X_add_number
< 0
2565 || imm_expr
->X_add_number
>= 128)
2567 as_bad (_("bad value for funct7 field, "
2568 "value must be 0...127"));
2572 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2573 imm_expr
->X_op
= O_absent
;
2577 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2578 || imm_expr
->X_op
!= O_constant
2579 || imm_expr
->X_add_number
< 0
2580 || imm_expr
->X_add_number
>= 8)
2582 as_bad (_("bad value for funct3 field, "
2583 "value must be 0...7"));
2587 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2588 imm_expr
->X_op
= O_absent
;
2592 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2593 || imm_expr
->X_op
!= O_constant
2594 || imm_expr
->X_add_number
< 0
2595 || imm_expr
->X_add_number
>= 4)
2597 as_bad (_("bad value for funct2 field, "
2598 "value must be 0...3"));
2602 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2603 imm_expr
->X_op
= O_absent
;
2608 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2613 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2614 || imm_expr
->X_op
!= O_constant
2615 || imm_expr
->X_add_number
!= 0)
2618 imm_expr
->X_op
= O_absent
;
2622 as_fatal (_("internal error: bad argument type %c"), *args
);
2627 error
= _("illegal operands");
2628 insn_with_csr
= FALSE
;
2632 /* Restore the character we might have clobbered above. */
2634 *(argsStart
- 1) = save_c
;
2640 md_assemble (char *str
)
2642 struct riscv_cl_insn insn
;
2643 expressionS imm_expr
;
2644 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2646 /* The arch and priv attributes should be set before assembling. */
2647 if (!start_assemble
)
2649 start_assemble
= TRUE
;
2650 riscv_set_abi_by_arch ();
2652 /* Set the default_priv_spec according to the priv attributes. */
2653 if (!riscv_set_default_priv_spec (NULL
))
2657 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2661 as_bad ("%s `%s'", error
, str
);
2665 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2666 macro (&insn
, &imm_expr
, &imm_reloc
);
2668 append_insn (&insn
, &imm_expr
, imm_reloc
);
2672 md_atof (int type
, char *litP
, int *sizeP
)
2674 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2678 md_number_to_chars (char *buf
, valueT val
, int n
)
2680 if (target_big_endian
)
2681 number_to_chars_bigendian (buf
, val
, n
);
2683 number_to_chars_littleendian (buf
, val
, n
);
2686 const char *md_shortopts
= "O::g::G:";
2690 OPTION_MARCH
= OPTION_MD_BASE
,
2697 OPTION_NO_ARCH_ATTR
,
2699 OPTION_NO_CSR_CHECK
,
2703 OPTION_LITTLE_ENDIAN
,
2707 struct option md_longopts
[] =
2709 {"march", required_argument
, NULL
, OPTION_MARCH
},
2710 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2711 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2712 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2713 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2714 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2715 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2716 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2717 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2718 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2719 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2720 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2721 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2722 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
2723 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
2725 {NULL
, no_argument
, NULL
, 0}
2727 size_t md_longopts_size
= sizeof (md_longopts
);
2730 md_parse_option (int c
, const char *arg
)
2735 /* riscv_after_parse_args will call riscv_set_arch to parse
2736 the architecture. */
2737 default_arch_with_ext
= arg
;
2741 riscv_opts
.pic
= FALSE
;
2745 riscv_opts
.pic
= TRUE
;
2749 if (strcmp (arg
, "ilp32") == 0)
2750 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2751 else if (strcmp (arg
, "ilp32e") == 0)
2752 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2753 else if (strcmp (arg
, "ilp32f") == 0)
2754 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2755 else if (strcmp (arg
, "ilp32d") == 0)
2756 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2757 else if (strcmp (arg
, "ilp32q") == 0)
2758 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2759 else if (strcmp (arg
, "lp64") == 0)
2760 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2761 else if (strcmp (arg
, "lp64f") == 0)
2762 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2763 else if (strcmp (arg
, "lp64d") == 0)
2764 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2765 else if (strcmp (arg
, "lp64q") == 0)
2766 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2769 explicit_mabi
= TRUE
;
2773 riscv_opts
.relax
= TRUE
;
2776 case OPTION_NO_RELAX
:
2777 riscv_opts
.relax
= FALSE
;
2780 case OPTION_ARCH_ATTR
:
2781 riscv_opts
.arch_attr
= TRUE
;
2784 case OPTION_NO_ARCH_ATTR
:
2785 riscv_opts
.arch_attr
= FALSE
;
2788 case OPTION_CSR_CHECK
:
2789 riscv_opts
.csr_check
= TRUE
;
2792 case OPTION_NO_CSR_CHECK
:
2793 riscv_opts
.csr_check
= FALSE
;
2796 case OPTION_MISA_SPEC
:
2797 return riscv_set_default_isa_spec (arg
);
2799 case OPTION_MPRIV_SPEC
:
2800 return riscv_set_default_priv_spec (arg
);
2802 case OPTION_BIG_ENDIAN
:
2803 target_big_endian
= 1;
2806 case OPTION_LITTLE_ENDIAN
:
2807 target_big_endian
= 0;
2818 riscv_after_parse_args (void)
2820 /* The --with-arch is optional for now, so we have to set the xlen
2821 according to the default_arch, which is set by the --targte, first.
2822 Then, we use the xlen to set the default_arch_with_ext if the
2823 -march and --with-arch are not set. */
2826 if (strcmp (default_arch
, "riscv32") == 0)
2828 else if (strcmp (default_arch
, "riscv64") == 0)
2831 as_bad ("unknown default architecture `%s'", default_arch
);
2833 if (default_arch_with_ext
== NULL
)
2834 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2836 /* Initialize the hash table for extensions with default version. */
2837 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2839 /* If the -misa-spec isn't set, then we set the default ISA spec according
2840 to DEFAULT_RISCV_ISA_SPEC. */
2841 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2842 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2844 /* Set the architecture according to -march or or --with-arch. */
2845 riscv_set_arch (default_arch_with_ext
);
2847 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2848 riscv_set_rvc (FALSE
);
2849 if (riscv_subset_supports ("c"))
2850 riscv_set_rvc (TRUE
);
2852 /* Enable RVE if specified by the -march option. */
2853 riscv_set_rve (FALSE
);
2854 if (riscv_subset_supports ("e"))
2855 riscv_set_rve (TRUE
);
2857 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2858 according to DEFAULT_PRIV_SPEC. */
2859 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2860 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2862 /* If the CIE to be produced has not been overridden on the command line,
2863 then produce version 3 by default. This allows us to use the full
2864 range of registers in a .cfi_return_column directive. */
2865 if (flag_dwarf_cie_version
== -1)
2866 flag_dwarf_cie_version
= 3;
2870 md_pcrel_from (fixS
*fixP
)
2872 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2875 /* Apply a fixup to the object file. */
2878 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2880 unsigned int subtype
;
2881 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2882 bfd_boolean relaxable
= FALSE
;
2886 /* Remember value for tc_gen_reloc. */
2887 fixP
->fx_addnumber
= *valP
;
2889 switch (fixP
->fx_r_type
)
2891 case BFD_RELOC_RISCV_HI20
:
2892 case BFD_RELOC_RISCV_LO12_I
:
2893 case BFD_RELOC_RISCV_LO12_S
:
2894 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2895 | bfd_getl32 (buf
), buf
);
2896 if (fixP
->fx_addsy
== NULL
)
2897 fixP
->fx_done
= TRUE
;
2901 case BFD_RELOC_RISCV_GOT_HI20
:
2902 case BFD_RELOC_RISCV_ADD8
:
2903 case BFD_RELOC_RISCV_ADD16
:
2904 case BFD_RELOC_RISCV_ADD32
:
2905 case BFD_RELOC_RISCV_ADD64
:
2906 case BFD_RELOC_RISCV_SUB6
:
2907 case BFD_RELOC_RISCV_SUB8
:
2908 case BFD_RELOC_RISCV_SUB16
:
2909 case BFD_RELOC_RISCV_SUB32
:
2910 case BFD_RELOC_RISCV_SUB64
:
2911 case BFD_RELOC_RISCV_RELAX
:
2914 case BFD_RELOC_RISCV_TPREL_HI20
:
2915 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2916 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2917 case BFD_RELOC_RISCV_TPREL_ADD
:
2921 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2922 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2923 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2924 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2925 if (fixP
->fx_addsy
!= NULL
)
2926 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2929 _("TLS relocation against a constant"));
2933 /* Use pc-relative relocation for FDE initial location.
2934 The symbol address in .eh_frame may be adjusted in
2935 _bfd_elf_discard_section_eh_frame, and the content of
2936 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2937 Therefore, we cannot insert a relocation whose addend symbol is
2938 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2939 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2940 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2941 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2942 && S_GET_VALUE (fixP
->fx_subsy
)
2943 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2945 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2946 fixP
->fx_subsy
= NULL
;
2953 case BFD_RELOC_RISCV_CFA
:
2954 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2956 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2957 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2958 fixP
->fx_next
->fx_subsy
= NULL
;
2959 fixP
->fx_next
->fx_offset
= 0;
2960 fixP
->fx_subsy
= NULL
;
2962 switch (fixP
->fx_r_type
)
2965 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2966 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2970 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2971 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2975 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2976 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2980 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2981 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2984 case BFD_RELOC_RISCV_CFA
:
2985 /* Load the byte to get the subtype. */
2986 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2987 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2990 case DW_CFA_advance_loc1
:
2991 fixP
->fx_where
= loc
+ 1;
2992 fixP
->fx_next
->fx_where
= loc
+ 1;
2993 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2994 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2997 case DW_CFA_advance_loc2
:
2999 fixP
->fx_next
->fx_size
= 2;
3000 fixP
->fx_where
= loc
+ 1;
3001 fixP
->fx_next
->fx_where
= loc
+ 1;
3002 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
3003 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3006 case DW_CFA_advance_loc4
:
3008 fixP
->fx_next
->fx_size
= 4;
3009 fixP
->fx_where
= loc
;
3010 fixP
->fx_next
->fx_where
= loc
;
3011 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3012 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3016 if (subtype
< 0x80 && (subtype
& 0x40))
3018 /* DW_CFA_advance_loc */
3019 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3020 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3021 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3022 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3025 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
3031 /* This case is unreachable. */
3038 /* If we are deleting this reloc entry, we must fill in the
3039 value now. This can happen if we have a .word which is not
3040 resolved when it appears but is later defined. */
3041 if (fixP
->fx_addsy
== NULL
)
3043 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3044 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3049 case BFD_RELOC_RISCV_JMP
:
3052 /* Fill in a tentative value to improve objdump readability. */
3053 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3054 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3055 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
3059 case BFD_RELOC_12_PCREL
:
3062 /* Fill in a tentative value to improve objdump readability. */
3063 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3064 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3065 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3069 case BFD_RELOC_RISCV_RVC_BRANCH
:
3072 /* Fill in a tentative value to improve objdump readability. */
3073 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3074 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3075 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3079 case BFD_RELOC_RISCV_RVC_JUMP
:
3082 /* Fill in a tentative value to improve objdump readability. */
3083 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3084 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3085 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3089 case BFD_RELOC_RISCV_CALL
:
3090 case BFD_RELOC_RISCV_CALL_PLT
:
3094 case BFD_RELOC_RISCV_PCREL_HI20
:
3095 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3096 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3097 relaxable
= riscv_opts
.relax
;
3100 case BFD_RELOC_RISCV_ALIGN
:
3104 /* We ignore generic BFD relocations we don't know about. */
3105 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3106 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3109 if (fixP
->fx_subsy
!= NULL
)
3110 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3111 _("unsupported symbol subtraction"));
3113 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3114 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3116 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3117 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3118 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3119 fixP
->fx_next
->fx_size
= 0;
3123 /* Because the value of .cfi_remember_state may changed after relaxation,
3124 we insert a fix to relocate it again in link-time. */
3127 riscv_pre_output_hook (void)
3129 const frchainS
*frch
;
3132 /* Save the current segment info. */
3134 subsegT subseg
= now_subseg
;
3136 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3137 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3141 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3143 if (frag
->fr_type
== rs_cfa
)
3146 expressionS
*symval
;
3148 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3149 exp
.X_op
= O_subtract
;
3150 exp
.X_add_symbol
= symval
->X_add_symbol
;
3151 exp
.X_add_number
= 0;
3152 exp
.X_op_symbol
= symval
->X_op_symbol
;
3154 /* We must set the segment before creating a frag after all
3155 frag chains have been chained together. */
3156 subseg_set (s
, frch
->frch_subseg
);
3158 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3159 BFD_RELOC_RISCV_CFA
);
3164 /* Restore the original segment info. */
3165 subseg_set (seg
, subseg
);
3169 /* This structure is used to hold a stack of .option values. */
3171 struct riscv_option_stack
3173 struct riscv_option_stack
*next
;
3174 struct riscv_set_options options
;
3177 static struct riscv_option_stack
*riscv_opts_stack
;
3179 /* Handle the .option pseudo-op. */
3182 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3184 char *name
= input_line_pointer
, ch
;
3186 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3187 ++input_line_pointer
;
3188 ch
= *input_line_pointer
;
3189 *input_line_pointer
= '\0';
3191 if (strcmp (name
, "rvc") == 0)
3192 riscv_set_rvc (TRUE
);
3193 else if (strcmp (name
, "norvc") == 0)
3194 riscv_set_rvc (FALSE
);
3195 else if (strcmp (name
, "pic") == 0)
3196 riscv_opts
.pic
= TRUE
;
3197 else if (strcmp (name
, "nopic") == 0)
3198 riscv_opts
.pic
= FALSE
;
3199 else if (strcmp (name
, "relax") == 0)
3200 riscv_opts
.relax
= TRUE
;
3201 else if (strcmp (name
, "norelax") == 0)
3202 riscv_opts
.relax
= FALSE
;
3203 else if (strcmp (name
, "csr-check") == 0)
3204 riscv_opts
.csr_check
= TRUE
;
3205 else if (strcmp (name
, "no-csr-check") == 0)
3206 riscv_opts
.csr_check
= FALSE
;
3207 else if (strcmp (name
, "push") == 0)
3209 struct riscv_option_stack
*s
;
3211 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3212 s
->next
= riscv_opts_stack
;
3213 s
->options
= riscv_opts
;
3214 riscv_opts_stack
= s
;
3216 else if (strcmp (name
, "pop") == 0)
3218 struct riscv_option_stack
*s
;
3220 s
= riscv_opts_stack
;
3222 as_bad (_(".option pop with no .option push"));
3225 riscv_opts
= s
->options
;
3226 riscv_opts_stack
= s
->next
;
3232 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3234 *input_line_pointer
= ch
;
3235 demand_empty_rest_of_line ();
3238 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3239 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3240 use in DWARF debug information. */
3243 s_dtprel (int bytes
)
3250 if (ex
.X_op
!= O_symbol
)
3252 as_bad (_("Unsupported use of %s"), (bytes
== 8
3255 ignore_rest_of_line ();
3258 p
= frag_more (bytes
);
3259 md_number_to_chars (p
, 0, bytes
);
3260 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3262 ? BFD_RELOC_RISCV_TLS_DTPREL64
3263 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3265 demand_empty_rest_of_line ();
3268 /* Handle the .bss pseudo-op. */
3271 s_bss (int ignore ATTRIBUTE_UNUSED
)
3273 subseg_set (bss_section
, 0);
3274 demand_empty_rest_of_line ();
3278 riscv_make_nops (char *buf
, bfd_vma bytes
)
3282 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3283 means we are not within a valid instruction sequence. It is thus safe
3284 to use a zero byte, even though that is not a valid instruction. */
3288 /* Use at most one 2-byte NOP. */
3289 if ((bytes
- i
) % 4 == 2)
3291 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3295 /* Fill the remainder with 4-byte NOPs. */
3296 for ( ; i
< bytes
; i
+= 4)
3297 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3300 /* Called from md_do_align. Used to create an alignment frag in a
3301 code section by emitting a worst-case NOP sequence that the linker
3302 will later relax to the correct number of NOPs. We can't compute
3303 the correct alignment now because of other linker relaxations. */
3306 riscv_frag_align_code (int n
)
3308 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3309 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3310 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3314 /* If we are moving to a smaller alignment than the instruction size, then no
3315 alignment is required. */
3316 if (bytes
<= insn_alignment
)
3319 /* When not relaxing, riscv_handle_align handles code alignment. */
3320 if (!riscv_opts
.relax
)
3323 nops
= frag_more (worst_case_bytes
);
3325 ex
.X_op
= O_constant
;
3326 ex
.X_add_number
= worst_case_bytes
;
3328 riscv_make_nops (nops
, worst_case_bytes
);
3330 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3331 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3336 /* Implement HANDLE_ALIGN. */
3339 riscv_handle_align (fragS
*fragP
)
3341 switch (fragP
->fr_type
)
3344 /* When relaxing, riscv_frag_align_code handles code alignment. */
3345 if (!riscv_opts
.relax
)
3347 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3348 - fragP
->fr_address
- fragP
->fr_fix
);
3349 /* We have 4 byte uncompressed nops. */
3350 bfd_signed_vma size
= 4;
3351 bfd_signed_vma excess
= bytes
% size
;
3352 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3357 /* Insert zeros or compressed nops to get 4 byte alignment. */
3360 riscv_make_nops (p
, excess
);
3361 fragP
->fr_fix
+= excess
;
3365 /* Insert variable number of 4 byte uncompressed nops. */
3366 riscv_make_nops (p
, size
);
3367 fragP
->fr_var
= size
;
3377 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3379 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3382 /* Translate internal representation of relocation info to BFD target
3386 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3388 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3390 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3391 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3392 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3393 reloc
->addend
= fixp
->fx_addnumber
;
3395 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3396 if (reloc
->howto
== NULL
)
3398 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3399 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3401 /* We don't have R_RISCV_8/16, but for this special case,
3402 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3406 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3407 _("cannot represent %s relocation in object file"),
3408 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3416 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3418 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3420 offsetT old_var
= fragp
->fr_var
;
3421 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3422 return fragp
->fr_var
- old_var
;
3428 /* Expand far branches to multi-instruction sequences. */
3431 md_convert_frag_branch (fragS
*fragp
)
3439 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3441 exp
.X_op
= O_symbol
;
3442 exp
.X_add_symbol
= fragp
->fr_symbol
;
3443 exp
.X_add_number
= fragp
->fr_offset
;
3445 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3447 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3449 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3453 /* Expand the RVC branch into a RISC-V one. */
3454 insn
= bfd_getl16 (buf
);
3455 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3456 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3458 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3459 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3460 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3461 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3462 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3463 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3466 bfd_putl32 (insn
, buf
);
3470 /* Invert the branch condition. Branch over the jump. */
3471 insn
= bfd_getl16 (buf
);
3472 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3473 insn
|= ENCODE_RVC_B_IMM (6);
3474 bfd_putl16 (insn
, buf
);
3479 /* Just keep the RVC branch. */
3480 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3481 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3482 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3483 2, &exp
, FALSE
, reloc
);
3492 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3495 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3497 /* Invert the branch condition. Branch over the jump. */
3498 insn
= bfd_getl32 (buf
);
3499 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3500 insn
|= ENCODE_SBTYPE_IMM (8);
3501 bfd_putl32 (insn
, buf
);
3505 /* Jump to the target. */
3506 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3507 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3508 bfd_putl32 (MATCH_JAL
, buf
);
3513 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3514 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3515 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3516 4, &exp
, FALSE
, reloc
);
3525 fixp
->fx_file
= fragp
->fr_file
;
3526 fixp
->fx_line
= fragp
->fr_line
;
3528 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3529 + fragp
->fr_fix
+ fragp
->fr_var
);
3531 fragp
->fr_fix
+= fragp
->fr_var
;
3534 /* Relax a machine dependent frag. This returns the amount by which
3535 the current size of the frag should change. */
3538 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3541 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3542 md_convert_frag_branch (fragp
);
3546 md_show_usage (FILE *stream
)
3548 fprintf (stream
, _("\
3550 -fpic generate position-independent code\n\
3551 -fno-pic don't generate position-independent code (default)\n\
3552 -march=ISA set the RISC-V architecture\n\
3553 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3554 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3555 -mabi=ABI set the RISC-V ABI\n\
3556 -mrelax enable relax (default)\n\
3557 -mno-relax disable relax\n\
3558 -march-attr generate RISC-V arch attribute\n\
3559 -mno-arch-attr don't generate RISC-V arch attribute\n\
3563 /* Standard calling conventions leave the CFA at SP on entry. */
3565 riscv_cfi_frame_initial_instructions (void)
3567 cfi_add_CFA_def_cfa_register (X_SP
);
3571 tc_riscv_regname_to_dw2regnum (char *regname
)
3575 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3578 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3581 /* CSRs are numbered 4096 -> 8191. */
3582 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3585 as_bad (_("unknown register `%s'"), regname
);
3590 riscv_elf_final_processing (void)
3592 riscv_set_abi_by_arch ();
3593 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3596 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3597 since these directives break relaxation when used with symbol deltas. */
3600 s_riscv_leb128 (int sign
)
3603 char *save_in
= input_line_pointer
;
3606 if (exp
.X_op
!= O_constant
)
3607 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3608 demand_empty_rest_of_line ();
3610 input_line_pointer
= save_in
;
3611 return s_leb128 (sign
);
3614 /* Parse the .insn directive. */
3617 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3619 char *str
= input_line_pointer
;
3620 struct riscv_cl_insn insn
;
3621 expressionS imm_expr
;
3622 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3625 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3626 ++input_line_pointer
;
3628 save_c
= *input_line_pointer
;
3629 *input_line_pointer
= '\0';
3631 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3632 &imm_reloc
, insn_type_hash
);
3636 as_bad ("%s `%s'", error
, str
);
3640 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3641 append_insn (&insn
, &imm_expr
, imm_reloc
);
3644 *input_line_pointer
= save_c
;
3645 demand_empty_rest_of_line ();
3648 /* Update arch and priv attributes. If we don't set the corresponding ELF
3649 attributes, then try to output the default ones. */
3652 riscv_write_out_attrs (void)
3654 const char *arch_str
, *priv_str
, *p
;
3655 /* versions[0] is major, versions[1] is minor,
3656 and versions[3] is revision. */
3657 unsigned versions
[3] = {0}, number
= 0;
3660 /* Re-write arch attribute to normalize the arch string. */
3661 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3662 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3663 xfree ((void *)arch_str
);
3665 /* For the file without any instruction, we don't set the default_priv_spec
3666 according to the priv attributes since the md_assemble isn't called.
3667 Call riscv_set_default_priv_spec here for the above case, although
3668 it seems strange. */
3670 && !riscv_set_default_priv_spec (NULL
))
3673 /* If we already have set elf priv attributes, then no need to do anything,
3674 assembler will generate them according to what you set. Otherwise, don't
3675 generate or update them when no CSR and priv instructions are used.
3676 Generate the priv attributes according to default_priv_spec, which can be
3677 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3678 priv attribute sets. */
3679 if (!explicit_priv_attr
)
3682 /* Re-write priv attributes by default_priv_spec. */
3683 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3685 for (i
= 0; *p
; ++p
)
3687 if (*p
== '.' && i
< 3)
3689 versions
[i
++] = number
;
3692 else if (ISDIGIT (*p
))
3693 number
= (number
* 10) + (*p
- '0');
3696 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3700 versions
[i
] = number
;
3702 /* Set the priv attributes. */
3703 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3704 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3705 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3708 /* Add the default contents for the .riscv.attributes section. If any
3709 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3710 to update the arch and priv attributes. */
3713 riscv_set_public_attributes (void)
3715 if (riscv_opts
.arch_attr
|| explicit_attr
)
3716 riscv_write_out_attrs ();
3719 /* Called after all assembly has been done. */
3724 riscv_set_public_attributes ();
3727 /* Given a symbolic attribute NAME, return the proper integer value.
3728 Returns -1 if the attribute is not known. */
3731 riscv_convert_symbolic_attribute (const char *name
)
3740 /* When you modify this table you should
3741 also modify the list in doc/c-riscv.texi. */
3742 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3746 T(priv_spec_revision
),
3747 T(unaligned_access
),
3757 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3758 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3759 return attribute_table
[i
].tag
;
3764 /* Parse a .attribute directive. */
3767 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3769 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3771 obj_attribute
*attr
;
3773 explicit_attr
= TRUE
;
3776 case Tag_RISCV_arch
:
3778 attr
= elf_known_obj_attributes_proc (stdoutput
);
3779 if (!start_assemble
)
3780 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3782 as_fatal (_(".attribute arch must set before any instructions"));
3784 if (old_xlen
!= xlen
)
3786 /* We must re-init bfd again if xlen is changed. */
3787 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3788 bfd_find_target (riscv_target_format (), stdoutput
);
3790 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3791 as_warn (_("Could not set architecture and machine"));
3795 case Tag_RISCV_priv_spec
:
3796 case Tag_RISCV_priv_spec_minor
:
3797 case Tag_RISCV_priv_spec_revision
:
3799 as_fatal (_(".attribute priv spec must set before any instructions"));
3807 /* Pseudo-op table. */
3809 static const pseudo_typeS riscv_pseudo_table
[] =
3811 /* RISC-V-specific pseudo-ops. */
3812 {"option", s_riscv_option
, 0},
3816 {"dtprelword", s_dtprel
, 4},
3817 {"dtpreldword", s_dtprel
, 8},
3819 {"uleb128", s_riscv_leb128
, 0},
3820 {"sleb128", s_riscv_leb128
, 1},
3821 {"insn", s_riscv_insn
, 0},
3822 {"attribute", s_riscv_attribute
, 0},
3828 riscv_pop_insert (void)
3830 extern void pop_insert (const pseudo_typeS
*);
3832 pop_insert (riscv_pseudo_table
);