1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2022 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
58 /* All RISC-V CSR belong to one of these classes. */
64 CSR_CLASS_I_32
, /* rv32 only */
65 CSR_CLASS_F
, /* f-ext only */
66 CSR_CLASS_ZKR
, /* zkr only */
67 CSR_CLASS_V
, /* rvv only */
68 CSR_CLASS_DEBUG
, /* debug CSR */
69 CSR_CLASS_H
, /* hypervisor */
70 CSR_CLASS_H_32
, /* hypervisor, rv32 only */
71 CSR_CLASS_SMSTATEEN
, /* Smstateen only */
72 CSR_CLASS_SMSTATEEN_AND_H
, /* Smstateen only (with H) */
73 CSR_CLASS_SMSTATEEN_32
, /* Smstateen RV32 only */
74 CSR_CLASS_SMSTATEEN_AND_H_32
, /* Smstateen RV32 only (with H) */
75 CSR_CLASS_SSCOFPMF
, /* Sscofpmf only */
76 CSR_CLASS_SSCOFPMF_32
, /* Sscofpmf RV32 only */
77 CSR_CLASS_SSTC
, /* Sstc only */
78 CSR_CLASS_SSTC_AND_H
, /* Sstc only (with H) */
79 CSR_CLASS_SSTC_32
, /* Sstc RV32 only */
80 CSR_CLASS_SSTC_AND_H_32
, /* Sstc RV32 only (with H) */
83 /* This structure holds all restricted conditions for a CSR. */
84 struct riscv_csr_extra
86 /* Class to which this CSR belongs. Used to decide whether or
87 not this CSR is legal in the current -march context. */
88 enum riscv_csr_class csr_class
;
90 /* CSR may have differnet numbers in the previous priv spec. */
93 /* Record the CSR is defined/valid in which versions. */
94 enum riscv_spec_class define_version
;
96 /* Record the CSR is aborted/invalid from which versions. If it isn't
97 aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */
98 enum riscv_spec_class abort_version
;
100 /* The CSR may have more than one setting. */
101 struct riscv_csr_extra
*next
;
104 /* This structure contains information about errors that occur within the
106 struct riscv_ip_error
108 /* General error message */
111 /* Statement that caused the error */
114 /* Missing extension that needs to be enabled */
115 const char* missing_ext
;
119 #define DEFAULT_ARCH "riscv64"
122 #ifndef DEFAULT_RISCV_ATTR
123 #define DEFAULT_RISCV_ATTR 0
126 /* Let riscv_after_parse_args set the default value according to xlen. */
127 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
128 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
131 /* Need to sync the version with RISC-V compiler. */
132 #ifndef DEFAULT_RISCV_ISA_SPEC
133 #define DEFAULT_RISCV_ISA_SPEC "20191213"
136 #ifndef DEFAULT_RISCV_PRIV_SPEC
137 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
140 static const char default_arch
[] = DEFAULT_ARCH
;
141 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
142 static enum riscv_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
143 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
145 static unsigned xlen
= 0; /* The width of an x-register. */
146 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
147 static bool rve_abi
= false;
150 FLOAT_ABI_DEFAULT
= -1,
156 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
158 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
159 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
161 static unsigned elf_flags
= 0;
163 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
164 Otherwise, return 1. */
167 riscv_set_default_isa_spec (const char *s
)
169 enum riscv_spec_class
class = ISA_SPEC_CLASS_NONE
;
170 RISCV_GET_ISA_SPEC_CLASS (s
, class);
171 if (class == ISA_SPEC_CLASS_NONE
)
173 as_bad ("unknown default ISA spec `%s' set by "
174 "-misa-spec or --with-isa-spec", s
);
178 default_isa_spec
= class;
182 /* Set the default_priv_spec. Find the privileged elf attributes when
183 the input string is NULL. Return 0 if the spec isn't supported.
184 Otherwise, return 1. */
187 riscv_set_default_priv_spec (const char *s
)
189 enum riscv_spec_class
class = PRIV_SPEC_CLASS_NONE
;
190 unsigned major
, minor
, revision
;
193 RISCV_GET_PRIV_SPEC_CLASS (s
, class);
194 if (class != PRIV_SPEC_CLASS_NONE
)
196 default_priv_spec
= class;
202 as_bad (_("unknown default privileged spec `%s' set by "
203 "-mpriv-spec or --with-priv-spec"), s
);
207 /* Set the default_priv_spec by the privileged elf attributes. */
208 attr
= elf_known_obj_attributes_proc (stdoutput
);
209 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
210 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
211 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
212 /* Version 0.0.0 is the default value and meningless. */
213 if (major
== 0 && minor
== 0 && revision
== 0)
216 riscv_get_priv_spec_class_from_numbers (major
, minor
, revision
, &class);
217 if (class != PRIV_SPEC_CLASS_NONE
)
219 default_priv_spec
= class;
223 /* Still can not find the privileged spec class. */
224 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
225 "privileged elf attributes"), major
, minor
, revision
);
229 /* This is the set of options which the .option pseudo-op may modify. */
230 struct riscv_set_options
232 int pic
; /* Generate position-independent code. */
233 int rvc
; /* Generate RVC code. */
234 int relax
; /* Emit relocs the linker is allowed to relax. */
235 int arch_attr
; /* Emit architecture and privileged elf attributes. */
236 int csr_check
; /* Enable the CSR checking. */
239 static struct riscv_set_options riscv_opts
=
244 DEFAULT_RISCV_ATTR
, /* arch_attr */
248 /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag
249 for elf_flags once we have enabled c extension. */
252 riscv_set_rvc (bool rvc_value
)
255 elf_flags
|= EF_RISCV_RVC
;
257 riscv_opts
.rvc
= rvc_value
;
260 /* Turn on the tso flag for elf_flags once we have enabled ztso extension. */
265 elf_flags
|= EF_RISCV_TSO
;
268 /* This linked list records all enabled extensions, which are parsed from
269 the architecture string. The architecture string can be set by the
270 -march option, the elf architecture attributes, and the --with-arch
272 static riscv_subset_list_t
*riscv_subsets
= NULL
;
273 static riscv_parse_subset_t riscv_rps_as
=
275 NULL
, /* subset_list, we will set it later once
276 riscv_opts_stack is created or updated. */
277 as_bad
, /* error_handler. */
279 &default_isa_spec
, /* isa_spec. */
280 true, /* check_unknown_prefixed_ext. */
283 /* This structure is used to hold a stack of .option values. */
284 struct riscv_option_stack
286 struct riscv_option_stack
*next
;
287 struct riscv_set_options options
;
288 riscv_subset_list_t
*subset_list
;
291 static struct riscv_option_stack
*riscv_opts_stack
= NULL
;
293 /* Set which ISA and extensions are available. */
296 riscv_set_arch (const char *s
)
298 if (s
!= NULL
&& strcmp (s
, "") == 0)
300 as_bad (_("the architecture string of -march and elf architecture "
301 "attributes cannot be empty"));
305 if (riscv_subsets
== NULL
)
307 riscv_subsets
= XNEW (riscv_subset_list_t
);
308 riscv_subsets
->head
= NULL
;
309 riscv_subsets
->tail
= NULL
;
310 riscv_rps_as
.subset_list
= riscv_subsets
;
312 riscv_release_subset_list (riscv_subsets
);
313 riscv_parse_subset (&riscv_rps_as
, s
);
315 riscv_set_rvc (false);
316 if (riscv_subset_supports (&riscv_rps_as
, "c"))
317 riscv_set_rvc (true);
319 if (riscv_subset_supports (&riscv_rps_as
, "ztso"))
323 /* Indicate -mabi option is explictly set. */
324 static bool explicit_mabi
= false;
326 /* Set the abi information. */
329 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bool rve
)
332 float_abi
= new_float_abi
;
336 /* If the -mabi option isn't set, then set the abi according to the
337 ISA string. Otherwise, check if there is any conflict. */
340 riscv_set_abi_by_arch (void)
344 if (riscv_subset_supports (&riscv_rps_as
, "q"))
345 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, false);
346 else if (riscv_subset_supports (&riscv_rps_as
, "d"))
347 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, false);
348 else if (riscv_subset_supports (&riscv_rps_as
, "e"))
349 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, true);
351 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, false);
355 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
357 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
358 else if (abi_xlen
< xlen
)
359 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
361 if (riscv_subset_supports (&riscv_rps_as
, "e") && !rve_abi
)
362 as_bad ("only the ilp32e ABI is supported for e extension");
364 if (float_abi
== FLOAT_ABI_SINGLE
365 && !riscv_subset_supports (&riscv_rps_as
, "f"))
366 as_bad ("ilp32f/lp64f ABI can't be used when f extension "
368 else if (float_abi
== FLOAT_ABI_DOUBLE
369 && !riscv_subset_supports (&riscv_rps_as
, "d"))
370 as_bad ("ilp32d/lp64d ABI can't be used when d extension "
372 else if (float_abi
== FLOAT_ABI_QUAD
373 && !riscv_subset_supports (&riscv_rps_as
, "q"))
374 as_bad ("ilp32q/lp64q ABI can't be used when q extension "
378 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
379 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
380 elf_flags
|= float_abi
<< 1;
383 elf_flags
|= EF_RISCV_RVE
;
386 /* Handle of the OPCODE hash table. */
387 static htab_t op_hash
= NULL
;
389 /* Handle of the type of .insn hash table. */
390 static htab_t insn_type_hash
= NULL
;
392 /* This array holds the chars that always start a comment. If the
393 pre-processor is disabled, these aren't very useful. */
394 const char comment_chars
[] = "#";
396 /* This array holds the chars that only start a comment at the beginning of
397 a line. If the line seems to have the form '# 123 filename'
398 .line and .file directives will appear in the pre-processed output
400 Note that input_file.c hand checks for '#' at the beginning of the
401 first line of the input file. This is because the compiler outputs
402 #NO_APP at the beginning of its output.
404 Also note that C style comments are always supported. */
405 const char line_comment_chars
[] = "#";
407 /* This array holds machine specific line separator characters. */
408 const char line_separator_chars
[] = ";";
410 /* Chars that can be used to separate mant from exp in floating point nums. */
411 const char EXP_CHARS
[] = "eE";
413 /* Chars that mean this number is a floating point constant.
414 As in 0f12.456 or 0d1.2345e12. */
415 const char FLT_CHARS
[] = "rRsSfFdDxXpPhH";
417 /* Indicate we are already assemble any instructions or not. */
418 static bool start_assemble
= false;
420 /* Indicate ELF attributes are explicitly set. */
421 static bool explicit_attr
= false;
423 /* Indicate CSR or priv instructions are explicitly used. */
424 static bool explicit_priv_attr
= false;
426 static char *expr_end
;
428 /* Macros for encoding relaxation state for RVC branches and far jumps. */
429 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
432 | ((uncond) ? 1 : 0) \
435 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
436 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
437 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
438 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
440 /* Is the given value a sign-extended 32-bit value? */
441 #define IS_SEXT_32BIT_NUM(x) \
442 (((x) &~ (offsetT) 0x7fffffff) == 0 \
443 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
445 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
446 #define IS_ZEXT_32BIT_NUM(x) \
447 (((x) &~ (offsetT) 0xffffffff) == 0 \
448 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
450 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
451 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
452 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
453 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
455 /* Determine if an instruction matches an opcode. */
456 #define OPCODE_MATCHES(OPCODE, OP) \
457 (((OPCODE) & MASK_##OP) == MATCH_##OP)
459 /* Create a new mapping symbol for the transition to STATE. */
462 make_mapping_symbol (enum riscv_seg_mstate state
,
479 symbolS
*symbol
= symbol_new (name
, now_seg
, frag
, value
);
480 symbol_get_bfdsym (symbol
)->flags
|= (BSF_NO_FLAGS
| BSF_LOCAL
);
482 /* If .fill or other data filling directive generates zero sized data,
483 or we are adding odd alignemnts, then the mapping symbol for the
484 following code will have the same value. */
487 if (frag
->tc_frag_data
.first_map_symbol
!= NULL
)
489 know (S_GET_VALUE (frag
->tc_frag_data
.first_map_symbol
)
490 == S_GET_VALUE (symbol
));
491 /* Remove the old one. */
492 symbol_remove (frag
->tc_frag_data
.first_map_symbol
,
493 &symbol_rootP
, &symbol_lastP
);
495 frag
->tc_frag_data
.first_map_symbol
= symbol
;
497 if (frag
->tc_frag_data
.last_map_symbol
!= NULL
)
499 /* The mapping symbols should be added in offset order. */
500 know (S_GET_VALUE (frag
->tc_frag_data
.last_map_symbol
)
501 <= S_GET_VALUE (symbol
));
502 /* Remove the old one. */
503 if (S_GET_VALUE (frag
->tc_frag_data
.last_map_symbol
)
504 == S_GET_VALUE (symbol
))
505 symbol_remove (frag
->tc_frag_data
.last_map_symbol
,
506 &symbol_rootP
, &symbol_lastP
);
508 frag
->tc_frag_data
.last_map_symbol
= symbol
;
511 /* Set the mapping state for frag_now. */
514 riscv_mapping_state (enum riscv_seg_mstate to_state
,
517 enum riscv_seg_mstate from_state
=
518 seg_info (now_seg
)->tc_segment_info_data
.map_state
;
520 if (!SEG_NORMAL (now_seg
)
521 /* For now I only add the mapping symbols to text sections.
522 Therefore, the dis-assembler only show the actual contents
523 distribution for text. Other sections will be shown as
524 data without the details. */
525 || !subseg_text_p (now_seg
))
528 /* The mapping symbol should be emitted if not in the right
530 if (from_state
== to_state
)
533 valueT value
= (valueT
) (frag_now_fix () - max_chars
);
534 seg_info (now_seg
)->tc_segment_info_data
.map_state
= to_state
;
535 make_mapping_symbol (to_state
, value
, frag_now
);
538 /* Add the odd bytes of paddings for riscv_handle_align. */
541 riscv_add_odd_padding_symbol (fragS
*frag
)
543 /* If there was already a mapping symbol, it should be
544 removed in the make_mapping_symbol. */
545 make_mapping_symbol (MAP_DATA
, frag
->fr_fix
, frag
);
546 make_mapping_symbol (MAP_INSN
, frag
->fr_fix
+ 1, frag
);
549 /* Remove any excess mapping symbols generated for alignment frags in
550 SEC. We may have created a mapping symbol before a zero byte
551 alignment; remove it if there's a mapping symbol after the
555 riscv_check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
,
557 void *dummy ATTRIBUTE_UNUSED
)
559 segment_info_type
*seginfo
= seg_info (sec
);
562 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
565 for (fragp
= seginfo
->frchainP
->frch_root
;
567 fragp
= fragp
->fr_next
)
569 symbolS
*last
= fragp
->tc_frag_data
.last_map_symbol
;
570 fragS
*next
= fragp
->fr_next
;
572 if (last
== NULL
|| next
== NULL
)
575 /* Check the last mapping symbol if it is at the boundary of
577 if (S_GET_VALUE (last
) < next
->fr_address
)
579 know (S_GET_VALUE (last
) == next
->fr_address
);
583 if (next
->tc_frag_data
.first_map_symbol
!= NULL
)
585 /* The last mapping symbol overlaps with another one
586 which at the start of the next frag. */
587 symbol_remove (last
, &symbol_rootP
, &symbol_lastP
);
591 if (next
->fr_next
== NULL
)
593 /* The last mapping symbol is at the end of the section. */
594 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
595 symbol_remove (last
, &symbol_rootP
, &symbol_lastP
);
599 /* Since we may have empty frags without any mapping symbols,
600 keep looking until the non-empty frag. */
601 if (next
->fr_address
!= next
->fr_next
->fr_address
)
604 next
= next
->fr_next
;
606 while (next
!= NULL
);
610 /* The default target format to use. */
613 riscv_target_format (void)
615 if (target_big_endian
)
616 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
618 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
621 /* Return the length of instruction INSN. */
623 static inline unsigned int
624 insn_length (const struct riscv_cl_insn
*insn
)
626 return riscv_insn_length (insn
->insn_opcode
);
629 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
632 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
635 insn
->insn_opcode
= mo
->match
;
641 /* Install INSN at the location specified by its "frag" and "where" fields. */
644 install_insn (const struct riscv_cl_insn
*insn
)
646 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
647 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
650 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
651 and install the opcode in the new location. */
654 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
658 if (insn
->fixp
!= NULL
)
660 insn
->fixp
->fx_frag
= frag
;
661 insn
->fixp
->fx_where
= where
;
666 /* Add INSN to the end of the output. */
669 add_fixed_insn (struct riscv_cl_insn
*insn
)
671 char *f
= frag_more (insn_length (insn
));
672 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
676 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
677 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
679 frag_grow (max_chars
);
680 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
681 frag_var (rs_machine_dependent
, max_chars
, var
,
682 subtype
, symbol
, offset
, NULL
);
685 /* Compute the length of a branch sequence, and adjust the stored length
686 accordingly. If FRAGP is NULL, the worst-case length is returned. */
689 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
691 int jump
, rvc
, length
= 8;
696 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
697 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
698 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
700 /* Assume jumps are in range; the linker will catch any that aren't. */
701 length
= jump
? 4 : 8;
703 if (fragp
->fr_symbol
!= NULL
704 && S_IS_DEFINED (fragp
->fr_symbol
)
705 && !S_IS_WEAK (fragp
->fr_symbol
)
706 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
708 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
709 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
710 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
712 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
714 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
716 else if (!jump
&& rvc
)
721 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
726 /* Information about an opcode name, mnemonics and its value. */
733 /* List for all supported opcode name. */
734 static const struct opcode_name_t opcode_name_list
[] =
779 /* Hash table for lookup opcode name. */
780 static htab_t opcode_names_hash
= NULL
;
782 /* Initialization for hash table of opcode name. */
785 init_opcode_names_hash (void)
787 const struct opcode_name_t
*opcode
;
789 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
790 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
791 as_fatal (_("internal: duplicate %s"), opcode
->name
);
794 /* Find `s` is a valid opcode name or not, return the opcode name info
797 static const struct opcode_name_t
*
798 opcode_name_lookup (char **s
)
802 struct opcode_name_t
*o
;
804 /* Find end of name. */
806 if (is_name_beginner (*e
))
808 while (is_part_of_name (*e
))
811 /* Terminate name. */
815 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
817 /* Advance to next token if one was recognized. */
827 /* All RISC-V registers belong to one of these classes. */
839 static htab_t reg_names_hash
= NULL
;
840 static htab_t csr_extra_hash
= NULL
;
842 #define ENCODE_REG_HASH(cls, n) \
843 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
844 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
845 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
848 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
850 void *hash
= ENCODE_REG_HASH (class, n
);
851 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
852 as_fatal (_("internal: duplicate %s"), name
);
856 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
860 for (i
= 0; i
< n
; i
++)
861 hash_reg_name (class, names
[i
], i
);
864 /* Init hash table csr_extra_hash to handle CSR. */
867 riscv_init_csr_hash (const char *name
,
869 enum riscv_csr_class
class,
870 enum riscv_spec_class define_version
,
871 enum riscv_spec_class abort_version
)
873 struct riscv_csr_extra
*entry
, *pre_entry
;
874 bool need_enrty
= true;
877 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
878 while (need_enrty
&& entry
!= NULL
)
880 if (entry
->csr_class
== class
881 && entry
->address
== address
882 && entry
->define_version
== define_version
883 && entry
->abort_version
== abort_version
)
893 entry
= notes_alloc (sizeof (*entry
));
894 entry
->csr_class
= class;
895 entry
->address
= address
;
896 entry
->define_version
= define_version
;
897 entry
->abort_version
= abort_version
;
900 if (pre_entry
== NULL
)
901 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
903 pre_entry
->next
= entry
;
906 /* Return the CSR address after checking the ISA dependency and
907 the privileged spec version.
909 There are one warning and two errors for CSR,
911 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
912 or the privileged spec, report warning only if -mcsr-check is set.
913 Unknown CSR: the CSR has never been defined, report error.
914 Improper CSR: the CSR number over the range (> 0xfff), report error. */
917 riscv_csr_address (const char *csr_name
,
918 struct riscv_csr_extra
*entry
)
920 struct riscv_csr_extra
*saved_entry
= entry
;
921 enum riscv_csr_class csr_class
= entry
->csr_class
;
922 bool need_check_version
= false;
923 bool is_rv32_only
= false;
924 bool is_h_required
= false;
925 const char* extension
= NULL
;
933 need_check_version
= true;
949 extension
= "zve32x";
951 case CSR_CLASS_SMSTATEEN
:
952 case CSR_CLASS_SMSTATEEN_AND_H
:
953 case CSR_CLASS_SMSTATEEN_32
:
954 case CSR_CLASS_SMSTATEEN_AND_H_32
:
955 is_rv32_only
= (csr_class
== CSR_CLASS_SMSTATEEN_32
956 || csr_class
== CSR_CLASS_SMSTATEEN_AND_H_32
);
957 is_h_required
= (csr_class
== CSR_CLASS_SMSTATEEN_AND_H
958 || csr_class
== CSR_CLASS_SMSTATEEN_AND_H_32
);
959 extension
= "smstateen";
961 case CSR_CLASS_SSCOFPMF_32
:
964 case CSR_CLASS_SSCOFPMF
:
965 extension
= "sscofpmf";
968 case CSR_CLASS_SSTC_AND_H
:
969 case CSR_CLASS_SSTC_32
:
970 case CSR_CLASS_SSTC_AND_H_32
:
971 is_rv32_only
= (csr_class
== CSR_CLASS_SSTC_32
972 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
973 is_h_required
= (csr_class
== CSR_CLASS_SSTC_AND_H
974 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
977 case CSR_CLASS_DEBUG
:
980 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
983 if (riscv_opts
.csr_check
)
985 if (is_rv32_only
&& xlen
!= 32)
986 as_warn (_("invalid CSR `%s', needs rv32i extension"), csr_name
);
987 if (is_h_required
&& !riscv_subset_supports (&riscv_rps_as
, "h"))
988 as_warn (_("invalid CSR `%s', needs `h' extension"), csr_name
);
990 if (extension
!= NULL
991 && !riscv_subset_supports (&riscv_rps_as
, extension
))
992 as_warn (_("invalid CSR `%s', needs `%s' extension"),
993 csr_name
, extension
);
996 while (entry
!= NULL
)
998 if (!need_check_version
999 || (default_priv_spec
>= entry
->define_version
1000 && default_priv_spec
< entry
->abort_version
))
1002 /* Find the CSR according to the specific version. */
1003 return entry
->address
;
1005 entry
= entry
->next
;
1008 /* Can not find the CSR address from the chosen privileged version,
1009 so use the newly defined value. */
1010 if (riscv_opts
.csr_check
)
1012 const char *priv_name
= NULL
;
1013 RISCV_GET_PRIV_SPEC_NAME (priv_name
, default_priv_spec
);
1014 if (priv_name
!= NULL
)
1015 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
1016 csr_name
, priv_name
);
1019 return saved_entry
->address
;
1022 /* Return -1 if the CSR has never been defined. Otherwise, return
1026 reg_csr_lookup_internal (const char *s
)
1028 struct riscv_csr_extra
*r
=
1029 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
1034 return riscv_csr_address (s
, r
);
1038 reg_lookup_internal (const char *s
, enum reg_class
class)
1042 if (class == RCLASS_CSR
)
1043 return reg_csr_lookup_internal (s
);
1045 r
= str_hash_find (reg_names_hash
, s
);
1046 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
1049 if (riscv_subset_supports (&riscv_rps_as
, "e")
1050 && class == RCLASS_GPR
1051 && DECODE_REG_NUM (r
) > 15)
1054 return DECODE_REG_NUM (r
);
1058 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
1064 /* Find end of name. */
1066 if (is_name_beginner (*e
))
1068 while (is_part_of_name (*e
))
1071 /* Terminate name. */
1075 /* Look for the register. Advance to next token if one was recognized. */
1076 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
1086 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
1088 const char *p
= strchr (*s
, ',');
1089 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
1094 for (i
= 0; i
< size
; i
++)
1095 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
1105 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1107 /* For consistency checking, verify that all bits are specified either
1108 by the match/mask part of the instruction definition, or by the
1109 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
1112 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
1114 const char *oparg
, *opargStart
;
1115 insn_t used_bits
= opc
->mask
;
1117 insn_t required_bits
;
1120 insn_width
= 8 * riscv_insn_length (opc
->match
);
1122 insn_width
= 8 * length
;
1124 required_bits
= ~0ULL >> (64 - insn_width
);
1126 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
1128 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1129 opc
->name
, opc
->args
);
1133 for (oparg
= opc
->args
; *oparg
; ++oparg
)
1141 case 'U': break; /* CRS1, constrained to equal RD. */
1142 case 'c': break; /* CRS1, constrained to equal sp. */
1143 case 'T': /* CRS2, floating point. */
1144 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1145 case 'S': /* CRS1S, floating point. */
1146 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1147 case 'w': break; /* CRS1S, constrained to equal RD. */
1148 case 'D': /* CRS2S, floating point. */
1149 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1150 case 'x': break; /* CRS2S, constrained to equal RD. */
1151 case 'z': break; /* CRS2S, constrained to be x0. */
1152 case '>': /* CITYPE immediate, compressed shift. */
1153 case 'u': /* CITYPE immediate, compressed lui. */
1154 case 'v': /* CITYPE immediate, li to compressed lui. */
1155 case 'o': /* CITYPE immediate, allow zero. */
1156 case 'j': used_bits
|= ENCODE_CITYPE_IMM (-1U); break;
1157 case 'L': used_bits
|= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1158 case 'm': used_bits
|= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1159 case 'n': used_bits
|= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1160 case '6': used_bits
|= ENCODE_CSSTYPE_IMM (-1U); break;
1161 case 'M': used_bits
|= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1162 case 'N': used_bits
|= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1163 case '8': used_bits
|= ENCODE_CIWTYPE_IMM (-1U); break;
1164 case 'K': used_bits
|= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1165 /* CLTYPE and CSTYPE have the same immediate encoding. */
1166 case '5': used_bits
|= ENCODE_CLTYPE_IMM (-1U); break;
1167 case 'k': used_bits
|= ENCODE_CLTYPE_LW_IMM (-1U); break;
1168 case 'l': used_bits
|= ENCODE_CLTYPE_LD_IMM (-1U); break;
1169 case 'p': used_bits
|= ENCODE_CBTYPE_IMM (-1U); break;
1170 case 'a': used_bits
|= ENCODE_CJTYPE_IMM (-1U); break;
1171 case 'F': /* Compressed funct for .insn directive. */
1174 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
1175 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
1176 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
1177 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
1179 goto unknown_validate_operand
;
1183 goto unknown_validate_operand
;
1185 break; /* end RVC */
1190 case 'f': USE_BITS (OP_MASK_VD
, OP_SH_VD
); break;
1191 case 'e': USE_BITS (OP_MASK_VWD
, OP_SH_VWD
); break;
1192 case 's': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
); break;
1193 case 't': USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1194 case 'u': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1195 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1196 case 'v': USE_BITS (OP_MASK_VD
, OP_SH_VD
);
1197 USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1198 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1200 case 'b': used_bits
|= ENCODE_RVV_VB_IMM (-1U); break;
1201 case 'c': used_bits
|= ENCODE_RVV_VC_IMM (-1U); break;
1204 case 'k': USE_BITS (OP_MASK_VIMM
, OP_SH_VIMM
); break;
1205 case 'm': USE_BITS (OP_MASK_VMASK
, OP_SH_VMASK
); break;
1207 goto unknown_validate_operand
;
1209 break; /* end RVV */
1213 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
1214 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
1215 case 'A': break; /* Macro operand, must be symbol. */
1216 case 'B': break; /* Macro operand, must be symbol or constant. */
1217 case 'I': break; /* Macro operand, must be constant. */
1218 case 'D': /* RD, floating point. */
1219 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1220 case 'y': USE_BITS (OP_MASK_BS
, OP_SH_BS
); break;
1221 case 'Y': USE_BITS (OP_MASK_RNUM
, OP_SH_RNUM
); break;
1222 case 'Z': /* RS1, CSR number. */
1223 case 'S': /* RS1, floating point. */
1224 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1225 case 'U': /* RS1 and RS2 are the same, floating point. */
1226 USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
1228 case 'T': /* RS2, floating point. */
1229 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1230 case 'R': /* RS3, floating point. */
1231 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1232 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1233 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
1234 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1235 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1236 case 'o': /* ITYPE immediate, load displacement. */
1237 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1238 case 'a': used_bits
|= ENCODE_JTYPE_IMM (-1U); break;
1239 case 'p': used_bits
|= ENCODE_BTYPE_IMM (-1U); break;
1240 case 'f': /* Fall through. */
1241 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1242 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1243 case 'z': break; /* Zero immediate. */
1244 case '[': break; /* Unused operand. */
1245 case ']': break; /* Unused operand. */
1246 case '0': break; /* AMO displacement, must to zero. */
1247 case '1': break; /* Relaxation operand. */
1248 case 'F': /* Funct for .insn directive. */
1251 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1252 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1253 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1255 goto unknown_validate_operand
;
1258 case 'O': /* Opcode for .insn directive. */
1261 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1262 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1264 goto unknown_validate_operand
;
1268 unknown_validate_operand
:
1269 as_bad (_("internal: bad RISC-V opcode "
1270 "(unknown operand type `%s'): %s %s"),
1271 opargStart
, opc
->name
, opc
->args
);
1276 if (used_bits
!= required_bits
)
1278 as_bad (_("internal: bad RISC-V opcode "
1279 "(bits 0x%lx undefined): %s %s"),
1280 ~(unsigned long)(used_bits
& required_bits
),
1281 opc
->name
, opc
->args
);
1289 struct percent_op_match
1292 bfd_reloc_code_real_type reloc
;
1295 /* Common hash table initialization function for instruction and .insn
1299 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1300 bool insn_directive_p
)
1304 htab_t hash
= str_htab_create ();
1305 while (opcodes
[i
].name
)
1307 const char *name
= opcodes
[i
].name
;
1308 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1309 as_fatal (_("internal: duplicate %s"), name
);
1313 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1315 if (insn_directive_p
)
1316 length
= ((name
[0] == 'c') ? 2 : 4);
1318 length
= 0; /* Let assembler determine the length. */
1319 if (!validate_riscv_insn (&opcodes
[i
], length
))
1320 as_fatal (_("internal: broken assembler. "
1321 "No assembly attempted"));
1324 gas_assert (!insn_directive_p
);
1327 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1333 /* This function is called once, at assembler startup time. It should set up
1334 all the tables, etc. that the MD part of the assembler will need. */
1339 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1341 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1342 as_warn (_("could not set architecture and machine"));
1344 op_hash
= init_opcode_hash (riscv_opcodes
, false);
1345 insn_type_hash
= init_opcode_hash (riscv_insn_types
, true);
1347 reg_names_hash
= str_htab_create ();
1348 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1349 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1350 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1351 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1352 hash_reg_names (RCLASS_VECR
, riscv_vecr_names_numeric
, NVECR
);
1353 hash_reg_names (RCLASS_VECM
, riscv_vecm_names_numeric
, NVECM
);
1354 /* Add "fp" as an alias for "s0". */
1355 hash_reg_name (RCLASS_GPR
, "fp", 8);
1357 /* Create and insert CSR hash tables. */
1358 csr_extra_hash
= str_htab_create ();
1359 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1360 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1361 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1362 DECLARE_CSR(name, num, class, define_version, abort_version);
1363 #include "opcode/riscv-opc.h"
1366 opcode_names_hash
= str_htab_create ();
1367 init_opcode_names_hash ();
1369 /* Set the default alignment for the text section. */
1370 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1374 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1381 case BFD_RELOC_RISCV_HI20
:
1382 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1384 case BFD_RELOC_RISCV_LO12_S
:
1385 return ENCODE_STYPE_IMM (value
);
1387 case BFD_RELOC_RISCV_LO12_I
:
1388 return ENCODE_ITYPE_IMM (value
);
1395 /* Output an instruction. IP is the instruction information.
1396 ADDRESS_EXPR is an operand of the instruction to be used with
1400 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1401 bfd_reloc_code_real_type reloc_type
)
1403 dwarf2_emit_insn (0);
1405 if (reloc_type
!= BFD_RELOC_UNUSED
)
1407 reloc_howto_type
*howto
;
1409 gas_assert (address_expr
);
1410 if (reloc_type
== BFD_RELOC_12_PCREL
1411 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1413 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1414 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1415 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1417 if (now_seg
== absolute_section
)
1419 as_bad (_("relaxable branches not supported in absolute section"));
1423 add_relaxed_insn (ip
, worst_case
, best_case
,
1424 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1425 address_expr
->X_add_symbol
,
1426 address_expr
->X_add_number
);
1431 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1433 as_bad (_("internal: unsupported RISC-V relocation number %d"),
1436 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1437 bfd_get_reloc_size (howto
),
1438 address_expr
, false, reloc_type
);
1440 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1444 add_fixed_insn (ip
);
1447 /* We need to start a new frag after any instruction that can be
1448 optimized away or compressed by the linker during relaxation, to prevent
1449 the assembler from computing static offsets across such an instruction.
1450 This is necessary to get correct EH info. */
1451 if (reloc_type
== BFD_RELOC_RISCV_HI20
1452 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1453 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1454 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1456 frag_wane (frag_now
);
1461 /* Build an instruction created by a macro expansion. This is passed
1462 a pointer to the count of instructions created so far, an expression,
1463 the name of the instruction to build, an operand format string, and
1464 corresponding arguments. */
1467 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1469 const struct riscv_opcode
*mo
;
1470 struct riscv_cl_insn insn
;
1471 bfd_reloc_code_real_type r
;
1473 const char *fmtStart
;
1475 va_start (args
, fmt
);
1477 r
= BFD_RELOC_UNUSED
;
1478 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1481 /* Find a non-RVC variant of the instruction. append_insn will compress
1483 while (riscv_insn_length (mo
->match
) < 4)
1485 gas_assert (strcmp (name
, mo
->name
) == 0);
1487 create_insn (&insn
, mo
);
1497 INSERT_OPERAND (VD
, insn
, va_arg (args
, int));
1500 INSERT_OPERAND (VS1
, insn
, va_arg (args
, int));
1503 INSERT_OPERAND (VS2
, insn
, va_arg (args
, int));
1507 int reg
= va_arg (args
, int);
1510 INSERT_OPERAND (VMASK
, insn
, 1);
1515 INSERT_OPERAND (VMASK
, insn
, 0);
1519 goto unknown_macro_argument
;
1522 goto unknown_macro_argument
;
1527 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1530 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1533 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1539 gas_assert (ep
!= NULL
);
1540 r
= va_arg (args
, int);
1548 unknown_macro_argument
:
1549 as_fatal (_("internal: invalid macro argument `%s'"), fmtStart
);
1554 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1556 append_insn (&insn
, ep
, r
);
1559 /* Build an instruction created by a macro expansion. Like md_assemble but
1560 accept a printf-style format string and arguments. */
1563 md_assemblef (const char *format
, ...)
1569 va_start (ap
, format
);
1571 r
= vasprintf (&buf
, format
, ap
);
1574 as_fatal (_("internal: vasprintf failed"));
1582 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1586 normalize_constant_expr (expressionS
*ex
)
1590 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1591 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1592 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1596 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1597 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1600 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1603 if (ex
->X_op
== O_big
)
1604 as_bad (_("unsupported large constant"));
1605 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1606 as_bad (_("unknown CSR `%s'"),
1607 S_GET_NAME (ex
->X_add_symbol
));
1608 else if (ex
->X_op
!= O_constant
)
1609 as_bad (_("instruction %s requires absolute expression"),
1611 normalize_constant_expr (ex
);
1615 make_internal_label (void)
1617 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1621 /* Load an entry from the GOT. */
1624 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1625 const char *lo_insn
, const char *lo_pattern
,
1626 bfd_reloc_code_real_type hi_reloc
,
1627 bfd_reloc_code_real_type lo_reloc
)
1630 ep2
.X_op
= O_symbol
;
1631 ep2
.X_add_symbol
= make_internal_label ();
1632 ep2
.X_add_number
= 0;
1634 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1635 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1639 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1640 bfd_reloc_code_real_type hi_reloc
,
1641 bfd_reloc_code_real_type lo_reloc
)
1643 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1647 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1648 bfd_reloc_code_real_type hi_reloc
,
1649 bfd_reloc_code_real_type lo_reloc
)
1651 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1654 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1657 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1658 bfd_reloc_code_real_type reloc
)
1660 /* Ensure the jalr is emitted to the same frag as the auipc. */
1662 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1663 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1664 /* See comment at end of append_insn. */
1665 frag_wane (frag_now
);
1669 /* Load an integer constant into a register. */
1672 load_const (int reg
, expressionS
*ep
)
1674 int shift
= RISCV_IMM_BITS
;
1675 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1676 expressionS upper
= *ep
, lower
= *ep
;
1677 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1678 upper
.X_add_number
-= lower
.X_add_number
;
1680 if (ep
->X_op
!= O_constant
)
1682 as_bad (_("unsupported large constant"));
1686 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1688 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1689 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1692 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1693 load_const (reg
, &upper
);
1695 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1696 if (lower
.X_add_number
!= 0)
1697 md_assemblef ("addi x%d, x%d, %" PRId64
, reg
, reg
,
1698 (int64_t) lower
.X_add_number
);
1702 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1705 if (upper
.X_add_number
!= 0)
1707 /* Discard low part and zero-extend upper immediate. */
1708 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1710 md_assemblef ("lui x%d, 0x%" PRIx64
, reg
, (uint64_t) upper_imm
);
1714 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1715 md_assemblef ("%s x%d, x%d, %" PRId64
, ADD32_INSN
, reg
, hi_reg
,
1716 (int64_t) lower
.X_add_number
);
1720 /* Zero extend and sign extend byte/half-word/word. */
1723 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bool sign
)
1727 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1728 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1732 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1733 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1737 /* Expand RISC-V Vector macros into one or more instructions. */
1740 vector_macro (struct riscv_cl_insn
*ip
)
1742 int vd
= (ip
->insn_opcode
>> OP_SH_VD
) & OP_MASK_VD
;
1743 int vs1
= (ip
->insn_opcode
>> OP_SH_VS1
) & OP_MASK_VS1
;
1744 int vs2
= (ip
->insn_opcode
>> OP_SH_VS2
) & OP_MASK_VS2
;
1745 int vm
= (ip
->insn_opcode
>> OP_SH_VMASK
) & OP_MASK_VMASK
;
1746 int vtemp
= (ip
->insn_opcode
>> OP_SH_VFUNCT6
) & OP_MASK_VFUNCT6
;
1747 int mask
= ip
->insn_mo
->mask
;
1755 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1756 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
1761 /* Masked. Have vtemp to avoid overlap constraints. */
1764 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1765 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
1769 /* Preserve the value of vd if not updating by vm. */
1770 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1771 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
1772 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1773 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
1778 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
1779 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
1780 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1783 as_bad (_("must provide temp if destination overlaps mask"));
1790 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1791 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
1796 /* Masked. Have vtemp to avoid overlap constraints. */
1799 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1800 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
1804 /* Preserve the value of vd if not updating by vm. */
1805 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1806 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
1807 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1808 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
1813 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
1814 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
1815 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1818 as_bad (_("must provide temp if destination overlaps mask"));
1826 /* Expand RISC-V assembly macros into one or more instructions. */
1829 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1830 bfd_reloc_code_real_type
*imm_reloc
)
1832 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1833 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1834 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1835 int mask
= ip
->insn_mo
->mask
;
1840 load_const (rd
, imm_expr
);
1845 /* Load the address of a symbol into a register. */
1846 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1847 as_bad (_("offset too large"));
1849 if (imm_expr
->X_op
== O_constant
)
1850 load_const (rd
, imm_expr
);
1851 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
1852 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1853 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1854 else /* Local PIC symbol, or any non-PIC symbol. */
1855 pcrel_load (rd
, rd
, imm_expr
, "addi",
1856 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1860 pcrel_load (rd
, rd
, imm_expr
, "addi",
1861 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1865 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1866 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1870 pcrel_load (rd
, rd
, imm_expr
, "lb",
1871 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1875 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1876 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1880 pcrel_load (rd
, rd
, imm_expr
, "lh",
1881 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1885 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1886 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1890 pcrel_load (rd
, rd
, imm_expr
, "lw",
1891 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1895 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1896 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1900 pcrel_load (rd
, rd
, imm_expr
, "ld",
1901 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1905 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1906 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1910 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1911 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1915 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1916 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1920 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1921 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1925 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1926 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1930 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1931 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1935 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1936 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1940 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1941 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1945 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1949 riscv_ext (rd
, rs1
, xlen
- 16, false);
1953 riscv_ext (rd
, rs1
, xlen
- 32, false);
1957 riscv_ext (rd
, rs1
, xlen
- 8, true);
1961 riscv_ext (rd
, rs1
, xlen
- 16, true);
1970 pcrel_load (rd
, rs1
, imm_expr
, "flh",
1971 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1974 pcrel_store (rs2
, rs1
, imm_expr
, "fsh",
1975 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1979 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
1984 static const struct percent_op_match percent_op_utype
[] =
1986 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1987 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1988 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1989 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1990 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1991 {"%hi", BFD_RELOC_RISCV_HI20
},
1995 static const struct percent_op_match percent_op_itype
[] =
1997 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1998 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1999 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
2003 static const struct percent_op_match percent_op_stype
[] =
2005 {"%lo", BFD_RELOC_RISCV_LO12_S
},
2006 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
2007 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
2011 static const struct percent_op_match percent_op_rtype
[] =
2013 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
2017 static const struct percent_op_match percent_op_null
[] =
2022 /* Return true if *STR points to a relocation operator. When returning true,
2023 move *STR over the operator and store its relocation code in *RELOC.
2024 Leave both *STR and *RELOC alone when returning false. */
2027 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
2028 const struct percent_op_match
*percent_op
)
2030 for ( ; percent_op
->str
; percent_op
++)
2031 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
2033 int len
= strlen (percent_op
->str
);
2035 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
2038 *str
+= strlen (percent_op
->str
);
2039 *reloc
= percent_op
->reloc
;
2041 /* Check whether the output BFD supports this relocation.
2042 If not, issue an error and fall back on something safe. */
2043 if (*reloc
!= BFD_RELOC_UNUSED
2044 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
2046 as_bad ("internal: relocation %s isn't supported by the "
2047 "current ABI", percent_op
->str
);
2048 *reloc
= BFD_RELOC_UNUSED
;
2056 my_getExpression (expressionS
*ep
, char *str
)
2060 save_in
= input_line_pointer
;
2061 input_line_pointer
= str
;
2063 expr_end
= input_line_pointer
;
2064 input_line_pointer
= save_in
;
2067 /* Parse string STR as a 16-bit relocatable operand. Store the
2068 expression in *EP and the relocation, if any, in RELOC.
2069 Return the number of relocation operators used (0 or 1).
2071 On exit, EXPR_END points to the first character after the expression. */
2074 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2075 char *str
, const struct percent_op_match
*percent_op
)
2078 unsigned crux_depth
, str_depth
, regno
;
2081 /* First, check for integer registers. No callers can accept a reg, but
2082 we need to avoid accidentally creating a useless undefined symbol below,
2083 if this is an instruction pattern that can't match. A glibc build fails
2084 if this is removed. */
2085 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
2087 ep
->X_op
= O_register
;
2088 ep
->X_add_number
= regno
;
2093 /* Search for the start of the main expression.
2095 End the loop with CRUX pointing to the start of the main expression and
2096 with CRUX_DEPTH containing the number of open brackets at that point. */
2103 crux_depth
= str_depth
;
2105 /* Skip over whitespace and brackets, keeping count of the number
2107 while (*str
== ' ' || *str
== '\t' || *str
== '(')
2113 && parse_relocation (&str
, reloc
, percent_op
));
2115 my_getExpression (ep
, crux
);
2118 /* Match every open bracket. */
2119 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
2124 as_bad ("unclosed '('");
2131 /* Parse opcode name, could be an mnemonics or number. */
2134 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2135 char *str
, const struct percent_op_match
*percent_op
)
2137 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
2141 ep
->X_op
= O_constant
;
2142 ep
->X_add_number
= o
->val
;
2146 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
2149 /* Parse string STR as a vsetvli operand. Store the expression in *EP.
2150 On exit, EXPR_END points to the first character after the expression. */
2153 my_getVsetvliExpression (expressionS
*ep
, char *str
)
2155 unsigned int vsew_value
= 0, vlmul_value
= 0;
2156 unsigned int vta_value
= 0, vma_value
= 0;
2157 bfd_boolean vsew_found
= FALSE
, vlmul_found
= FALSE
;
2158 bfd_boolean vta_found
= FALSE
, vma_found
= FALSE
;
2160 if (arg_lookup (&str
, riscv_vsew
, ARRAY_SIZE (riscv_vsew
), &vsew_value
))
2165 as_bad (_("multiple vsew constants"));
2168 if (arg_lookup (&str
, riscv_vlmul
, ARRAY_SIZE (riscv_vlmul
), &vlmul_value
))
2173 as_bad (_("multiple vlmul constants"));
2176 if (arg_lookup (&str
, riscv_vta
, ARRAY_SIZE (riscv_vta
), &vta_value
))
2181 as_bad (_("multiple vta constants"));
2184 if (arg_lookup (&str
, riscv_vma
, ARRAY_SIZE (riscv_vma
), &vma_value
))
2189 as_bad (_("multiple vma constants"));
2193 if (vsew_found
|| vlmul_found
|| vta_found
|| vma_found
)
2195 ep
->X_op
= O_constant
;
2196 ep
->X_add_number
= (vlmul_value
<< OP_SH_VLMUL
)
2197 | (vsew_value
<< OP_SH_VSEW
)
2198 | (vta_value
<< OP_SH_VTA
)
2199 | (vma_value
<< OP_SH_VMA
);
2204 my_getExpression (ep
, str
);
2209 /* Detect and handle implicitly zero load-store offsets. For example,
2210 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return true if such
2211 an implicit offset was detected. */
2214 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
2216 /* Check whether there is only a single bracketed expression left.
2217 If so, it must be the base register and the constant must be zero. */
2218 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
2220 ep
->X_op
= O_constant
;
2221 ep
->X_add_number
= 0;
2228 /* All RISC-V CSR instructions belong to one of these classes. */
2237 /* Return which CSR instruction is checking. */
2239 static enum csr_insn_type
2240 riscv_csr_insn_type (insn_t insn
)
2242 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
2243 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
2245 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
2246 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
2248 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
2249 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
2252 return INSN_NOT_CSR
;
2255 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
2256 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
2257 CSR address is 0x3. */
2260 riscv_csr_read_only_check (insn_t insn
)
2262 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
2263 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
2264 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
2265 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
2268 && (((csr_insn
== INSN_CSRRS
2269 || csr_insn
== INSN_CSRRC
)
2271 || csr_insn
== INSN_CSRRW
))
2277 /* Return true if it is a privileged instruction. Otherwise, return false.
2279 uret is actually a N-ext instruction. So it is better to regard it as
2280 an user instruction rather than the priv instruction.
2282 hret is used to return from traps in H-mode. H-mode is removed since
2283 the v1.10 priv spec, but probably be added in the new hypervisor spec.
2284 Therefore, hret should be controlled by the hypervisor spec rather than
2285 priv spec in the future.
2287 dret is defined in the debug spec, so it should be checked in the future,
2291 riscv_is_priv_insn (insn_t insn
)
2293 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
2294 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
2295 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
2296 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
2297 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
2298 check it here to keep the compatible. */
2299 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
2302 /* This routine assembles an instruction into its binary format. As a
2303 side effect, it sets the global variable imm_reloc to the type of
2304 relocation to do if one of the operands is an address expression. */
2306 static struct riscv_ip_error
2307 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
2308 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
2310 /* The operand string defined in the riscv_opcodes. */
2311 const char *oparg
, *opargStart
;
2312 /* The parsed operands from assembly. */
2313 char *asarg
, *asargStart
;
2315 struct riscv_opcode
*insn
;
2317 const struct percent_op_match
*p
;
2318 struct riscv_ip_error error
;
2319 error
.msg
= "unrecognized opcode";
2320 error
.statement
= str
;
2321 error
.missing_ext
= NULL
;
2322 /* Indicate we are assembling instruction with CSR. */
2323 bool insn_with_csr
= false;
2325 /* Parse the name of the instruction. Terminate the string if whitespace
2326 is found so that str_hash_find only sees the name part of the string. */
2327 for (asarg
= str
; *asarg
!= '\0'; ++asarg
)
2328 if (ISSPACE (*asarg
))
2335 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
2338 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
2340 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
2343 if (!riscv_multi_subset_supports (&riscv_rps_as
, insn
->insn_class
))
2345 error
.missing_ext
= riscv_multi_subset_supports_ext (&riscv_rps_as
,
2350 /* Reset error message of the previous round. */
2351 error
.msg
= _("illegal operands");
2352 error
.missing_ext
= NULL
;
2353 create_insn (ip
, insn
);
2355 imm_expr
->X_op
= O_absent
;
2356 *imm_reloc
= BFD_RELOC_UNUSED
;
2357 p
= percent_op_itype
;
2359 for (oparg
= insn
->args
;; ++oparg
)
2362 asarg
+= strspn (asarg
, " \t");
2365 case '\0': /* End of args. */
2366 if (insn
->pinfo
!= INSN_MACRO
)
2368 if (!insn
->match_func (insn
, ip
->insn_opcode
))
2371 /* For .insn, insn->match and insn->mask are 0. */
2372 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
2378 if (riscv_is_priv_insn (ip
->insn_opcode
))
2379 explicit_priv_attr
= true;
2381 /* Check if we write a read-only CSR by the CSR
2384 && riscv_opts
.csr_check
2385 && !riscv_csr_read_only_check (ip
->insn_opcode
))
2387 /* Restore the character in advance, since we want to
2388 report the detailed warning message here. */
2390 *(asargStart
- 1) = save_c
;
2391 as_warn (_("read-only CSR is written `%s'"), str
);
2392 insn_with_csr
= false;
2395 /* The (segmant) load and store with EEW 64 cannot be used
2396 when zve32x is enabled. */
2397 if (ip
->insn_mo
->pinfo
& INSN_V_EEW64
2398 && riscv_subset_supports (&riscv_rps_as
, "zve32x")
2399 && !riscv_subset_supports (&riscv_rps_as
, "zve64x"))
2401 error
.msg
= _("illegal opcode for zve32x");
2407 /* Successful assembly. */
2409 insn_with_csr
= false;
2415 case 's': /* RS1 x8-x15. */
2416 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2417 || !(regno
>= 8 && regno
<= 15))
2419 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2421 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2422 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2423 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
2426 case 't': /* RS2 x8-x15. */
2427 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2428 || !(regno
>= 8 && regno
<= 15))
2430 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2432 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2433 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2434 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
2437 case 'U': /* RS1, constrained to equal RD. */
2438 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2439 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
2443 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
2445 INSERT_OPERAND (CRS2
, *ip
, regno
);
2447 case 'c': /* RS1, constrained to equal sp. */
2448 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2452 case 'z': /* RS2, constrained to equal x0. */
2453 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2457 case '>': /* Shift amount, 0 - (XLEN-1). */
2458 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2459 || imm_expr
->X_op
!= O_constant
2460 || (unsigned long) imm_expr
->X_add_number
>= xlen
)
2462 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2465 imm_expr
->X_op
= O_absent
;
2468 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2469 || imm_expr
->X_op
!= O_constant
2470 || imm_expr
->X_add_number
< 0
2471 || imm_expr
->X_add_number
>= 32
2472 || !VALID_CLTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2474 ip
->insn_opcode
|= ENCODE_CLTYPE_IMM (imm_expr
->X_add_number
);
2477 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2478 || imm_expr
->X_op
!= O_constant
2479 || imm_expr
->X_add_number
< 0
2480 || imm_expr
->X_add_number
>= 64
2481 || !VALID_CSSTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2483 ip
->insn_opcode
|= ENCODE_CSSTYPE_IMM (imm_expr
->X_add_number
);
2486 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2487 || imm_expr
->X_op
!= O_constant
2488 || imm_expr
->X_add_number
< 0
2489 || imm_expr
->X_add_number
>= 256
2490 || !VALID_CIWTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2492 ip
->insn_opcode
|= ENCODE_CIWTYPE_IMM (imm_expr
->X_add_number
);
2495 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2496 || imm_expr
->X_op
!= O_constant
2497 || imm_expr
->X_add_number
== 0
2498 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2500 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2503 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2505 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2506 || imm_expr
->X_op
!= O_constant
2507 || !VALID_CLTYPE_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2509 ip
->insn_opcode
|= ENCODE_CLTYPE_LW_IMM (imm_expr
->X_add_number
);
2512 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2514 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2515 || imm_expr
->X_op
!= O_constant
2516 || !VALID_CLTYPE_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2518 ip
->insn_opcode
|= ENCODE_CLTYPE_LD_IMM (imm_expr
->X_add_number
);
2521 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2523 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2524 || imm_expr
->X_op
!= O_constant
2525 || !VALID_CITYPE_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2528 ENCODE_CITYPE_LWSP_IMM (imm_expr
->X_add_number
);
2531 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2533 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2534 || imm_expr
->X_op
!= O_constant
2535 || !VALID_CITYPE_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2538 ENCODE_CITYPE_LDSP_IMM (imm_expr
->X_add_number
);
2541 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2542 || imm_expr
->X_op
!= O_constant
2543 /* C.addiw, c.li, and c.andi allow zero immediate.
2544 C.addi allows zero immediate as hint. Otherwise this
2546 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2548 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2551 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2552 || imm_expr
->X_op
!= O_constant
2553 || imm_expr
->X_add_number
== 0
2554 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2557 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2560 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2561 || imm_expr
->X_op
!= O_constant
2562 || !VALID_CITYPE_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2565 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr
->X_add_number
);
2568 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2570 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2571 || imm_expr
->X_op
!= O_constant
2572 || !VALID_CSSTYPE_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2575 ENCODE_CSSTYPE_SWSP_IMM (imm_expr
->X_add_number
);
2578 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2580 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2581 || imm_expr
->X_op
!= O_constant
2582 || !VALID_CSSTYPE_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2585 ENCODE_CSSTYPE_SDSP_IMM (imm_expr
->X_add_number
);
2588 p
= percent_op_utype
;
2589 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
2592 if (imm_expr
->X_op
!= O_constant
2593 || imm_expr
->X_add_number
<= 0
2594 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2595 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2596 && (imm_expr
->X_add_number
<
2597 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2599 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2602 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2603 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2604 || ((int32_t)imm_expr
->X_add_number
2605 != imm_expr
->X_add_number
))
2607 imm_expr
->X_add_number
=
2608 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2614 case 'S': /* Floating-point RS1 x8-x15. */
2615 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2616 || !(regno
>= 8 && regno
<= 15))
2618 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2620 case 'D': /* Floating-point RS2 x8-x15. */
2621 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2622 || !(regno
>= 8 && regno
<= 15))
2624 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2626 case 'T': /* Floating-point RS2. */
2627 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
))
2629 INSERT_OPERAND (CRS2
, *ip
, regno
);
2635 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2636 || imm_expr
->X_op
!= O_constant
2637 || imm_expr
->X_add_number
< 0
2638 || imm_expr
->X_add_number
>= 64)
2640 as_bad (_("bad value for compressed funct6 "
2641 "field, value must be 0...63"));
2644 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2645 imm_expr
->X_op
= O_absent
;
2650 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2651 || imm_expr
->X_op
!= O_constant
2652 || imm_expr
->X_add_number
< 0
2653 || imm_expr
->X_add_number
>= 16)
2655 as_bad (_("bad value for compressed funct4 "
2656 "field, value must be 0...15"));
2659 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2660 imm_expr
->X_op
= O_absent
;
2665 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2666 || imm_expr
->X_op
!= O_constant
2667 || imm_expr
->X_add_number
< 0
2668 || imm_expr
->X_add_number
>= 8)
2670 as_bad (_("bad value for compressed funct3 "
2671 "field, value must be 0...7"));
2674 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2675 imm_expr
->X_op
= O_absent
;
2680 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2681 || imm_expr
->X_op
!= O_constant
2682 || imm_expr
->X_add_number
< 0
2683 || imm_expr
->X_add_number
>= 4)
2685 as_bad (_("bad value for compressed funct2 "
2686 "field, value must be 0...3"));
2689 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2690 imm_expr
->X_op
= O_absent
;
2695 goto unknown_riscv_ip_operand
;
2700 goto unknown_riscv_ip_operand
;
2702 break; /* end RVC */
2708 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2710 INSERT_OPERAND (VD
, *ip
, regno
);
2713 case 'e': /* AMO VD */
2714 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
) && regno
== 0)
2715 INSERT_OPERAND (VWD
, *ip
, 0);
2716 else if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2718 INSERT_OPERAND (VWD
, *ip
, 1);
2719 INSERT_OPERAND (VD
, *ip
, regno
);
2725 case 'f': /* AMO VS3 */
2726 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2728 if (!EXTRACT_OPERAND (VWD
, ip
->insn_opcode
))
2729 INSERT_OPERAND (VD
, *ip
, regno
);
2732 /* VS3 must match VD. */
2733 if (EXTRACT_OPERAND (VD
, ip
->insn_opcode
) != regno
)
2739 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2741 INSERT_OPERAND (VS1
, *ip
, regno
);
2745 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2747 INSERT_OPERAND (VS2
, *ip
, regno
);
2750 case 'u': /* VS1 == VS2 */
2751 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2753 INSERT_OPERAND (VS1
, *ip
, regno
);
2754 INSERT_OPERAND (VS2
, *ip
, regno
);
2757 case 'v': /* VD == VS1 == VS2 */
2758 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2760 INSERT_OPERAND (VD
, *ip
, regno
);
2761 INSERT_OPERAND (VS1
, *ip
, regno
);
2762 INSERT_OPERAND (VS2
, *ip
, regno
);
2765 /* The `V0` is carry-in register for v[m]adc and v[m]sbc,
2766 and is used to choose vs1/rs1/frs1/imm or vs2 for
2767 v[f]merge. It use the same encoding as the vector mask
2770 if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
) && regno
== 0)
2774 case 'b': /* vtypei for vsetivli */
2775 my_getVsetvliExpression (imm_expr
, asarg
);
2776 check_absolute_expr (ip
, imm_expr
, FALSE
);
2777 if (!VALID_RVV_VB_IMM (imm_expr
->X_add_number
))
2778 as_bad (_("bad value for vsetivli immediate field, "
2779 "value must be 0..1023"));
2781 |= ENCODE_RVV_VB_IMM (imm_expr
->X_add_number
);
2782 imm_expr
->X_op
= O_absent
;
2786 case 'c': /* vtypei for vsetvli */
2787 my_getVsetvliExpression (imm_expr
, asarg
);
2788 check_absolute_expr (ip
, imm_expr
, FALSE
);
2789 if (!VALID_RVV_VC_IMM (imm_expr
->X_add_number
))
2790 as_bad (_("bad value for vsetvli immediate field, "
2791 "value must be 0..2047"));
2793 |= ENCODE_RVV_VC_IMM (imm_expr
->X_add_number
);
2794 imm_expr
->X_op
= O_absent
;
2798 case 'i': /* vector arith signed immediate */
2799 my_getExpression (imm_expr
, asarg
);
2800 check_absolute_expr (ip
, imm_expr
, FALSE
);
2801 if (imm_expr
->X_add_number
> 15
2802 || imm_expr
->X_add_number
< -16)
2803 as_bad (_("bad value for vector immediate field, "
2804 "value must be -16...15"));
2805 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
2806 imm_expr
->X_op
= O_absent
;
2810 case 'j': /* vector arith unsigned immediate */
2811 my_getExpression (imm_expr
, asarg
);
2812 check_absolute_expr (ip
, imm_expr
, FALSE
);
2813 if (imm_expr
->X_add_number
< 0
2814 || imm_expr
->X_add_number
>= 32)
2815 as_bad (_("bad value for vector immediate field, "
2816 "value must be 0...31"));
2817 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
2818 imm_expr
->X_op
= O_absent
;
2822 case 'k': /* vector arith signed immediate, minus 1 */
2823 my_getExpression (imm_expr
, asarg
);
2824 check_absolute_expr (ip
, imm_expr
, FALSE
);
2825 if (imm_expr
->X_add_number
> 16
2826 || imm_expr
->X_add_number
< -15)
2827 as_bad (_("bad value for vector immediate field, "
2828 "value must be -15...16"));
2829 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
- 1);
2830 imm_expr
->X_op
= O_absent
;
2834 case 'm': /* optional vector mask */
2837 INSERT_OPERAND (VMASK
, *ip
, 1);
2840 else if (*asarg
== ',' && asarg
++
2841 && reg_lookup (&asarg
, RCLASS_VECM
, ®no
)
2844 INSERT_OPERAND (VMASK
, *ip
, 0);
2849 case 'M': /* required vector mask */
2850 if (reg_lookup (&asarg
, RCLASS_VECM
, ®no
) && regno
== 0)
2852 INSERT_OPERAND (VMASK
, *ip
, 0);
2857 case 'T': /* vector macro temporary register */
2858 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
) || regno
== 0)
2860 /* Store it in the FUNCT6 field as we don't have anyplace
2861 else to store it. */
2862 INSERT_OPERAND (VFUNCT6
, *ip
, regno
);
2866 goto unknown_riscv_ip_operand
;
2868 break; /* end RVV */
2871 if (*asarg
++ == *oparg
)
2880 if (*asarg
++ == *oparg
)
2884 case '<': /* Shift amount, 0 - 31. */
2885 my_getExpression (imm_expr
, asarg
);
2886 check_absolute_expr (ip
, imm_expr
, false);
2887 if ((unsigned long) imm_expr
->X_add_number
> 31)
2888 as_bad (_("improper shift amount (%lu)"),
2889 (unsigned long) imm_expr
->X_add_number
);
2890 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2891 imm_expr
->X_op
= O_absent
;
2895 case '>': /* Shift amount, 0 - (XLEN-1). */
2896 my_getExpression (imm_expr
, asarg
);
2897 check_absolute_expr (ip
, imm_expr
, false);
2898 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2899 as_bad (_("improper shift amount (%lu)"),
2900 (unsigned long) imm_expr
->X_add_number
);
2901 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2902 imm_expr
->X_op
= O_absent
;
2906 case 'Z': /* CSRRxI immediate. */
2907 my_getExpression (imm_expr
, asarg
);
2908 check_absolute_expr (ip
, imm_expr
, false);
2909 if ((unsigned long) imm_expr
->X_add_number
> 31)
2910 as_bad (_("improper CSRxI immediate (%lu)"),
2911 (unsigned long) imm_expr
->X_add_number
);
2912 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2913 imm_expr
->X_op
= O_absent
;
2917 case 'E': /* Control register. */
2918 insn_with_csr
= true;
2919 explicit_priv_attr
= true;
2920 if (reg_lookup (&asarg
, RCLASS_CSR
, ®no
))
2921 INSERT_OPERAND (CSR
, *ip
, regno
);
2924 my_getExpression (imm_expr
, asarg
);
2925 check_absolute_expr (ip
, imm_expr
, true);
2926 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2927 as_bad (_("improper CSR address (%lu)"),
2928 (unsigned long) imm_expr
->X_add_number
);
2929 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2930 imm_expr
->X_op
= O_absent
;
2935 case 'm': /* Rounding mode. */
2936 if (arg_lookup (&asarg
, riscv_rm
,
2937 ARRAY_SIZE (riscv_rm
), ®no
))
2939 INSERT_OPERAND (RM
, *ip
, regno
);
2945 case 'Q': /* Fence predecessor/successor. */
2946 if (arg_lookup (&asarg
, riscv_pred_succ
,
2947 ARRAY_SIZE (riscv_pred_succ
), ®no
))
2950 INSERT_OPERAND (PRED
, *ip
, regno
);
2952 INSERT_OPERAND (SUCC
, *ip
, regno
);
2957 case 'd': /* Destination register. */
2958 case 's': /* Source register. */
2959 case 't': /* Target register. */
2961 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
2967 /* Now that we have assembled one operand, we use the args
2968 string to figure out where it goes in the instruction. */
2972 INSERT_OPERAND (RS1
, *ip
, regno
);
2975 INSERT_OPERAND (RD
, *ip
, regno
);
2978 INSERT_OPERAND (RS2
, *ip
, regno
);
2981 INSERT_OPERAND (RS3
, *ip
, regno
);
2988 case 'D': /* Floating point RD. */
2989 case 'S': /* Floating point RS1. */
2990 case 'T': /* Floating point RS2. */
2991 case 'U': /* Floating point RS1 and RS2. */
2992 case 'R': /* Floating point RS3. */
2993 if (reg_lookup (&asarg
,
2994 (riscv_subset_supports (&riscv_rps_as
, "zfinx")
2995 ? RCLASS_GPR
: RCLASS_FPR
), ®no
))
3003 INSERT_OPERAND (RD
, *ip
, regno
);
3006 INSERT_OPERAND (RS1
, *ip
, regno
);
3009 INSERT_OPERAND (RS1
, *ip
, regno
);
3012 INSERT_OPERAND (RS2
, *ip
, regno
);
3015 INSERT_OPERAND (RS3
, *ip
, regno
);
3023 my_getExpression (imm_expr
, asarg
);
3024 if (imm_expr
->X_op
!= O_big
3025 && imm_expr
->X_op
!= O_constant
)
3027 normalize_constant_expr (imm_expr
);
3032 my_getExpression (imm_expr
, asarg
);
3033 normalize_constant_expr (imm_expr
);
3034 /* The 'A' format specifier must be a symbol. */
3035 if (imm_expr
->X_op
!= O_symbol
)
3037 *imm_reloc
= BFD_RELOC_32
;
3042 my_getExpression (imm_expr
, asarg
);
3043 normalize_constant_expr (imm_expr
);
3044 /* The 'B' format specifier must be a symbol or a constant. */
3045 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
3047 if (imm_expr
->X_op
== O_symbol
)
3048 *imm_reloc
= BFD_RELOC_32
;
3052 case 'j': /* Sign-extended immediate. */
3053 p
= percent_op_itype
;
3054 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3056 case 'q': /* Store displacement. */
3057 p
= percent_op_stype
;
3058 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
3060 case 'o': /* Load displacement. */
3061 p
= percent_op_itype
;
3062 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3065 /* This is used for TLS, where the fourth operand is
3066 %tprel_add, to get a relocation applied to an add
3067 instruction, for relaxation to use. */
3068 p
= percent_op_rtype
;
3070 case '0': /* AMO displacement, which must be zero. */
3071 p
= percent_op_null
;
3073 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3076 /* If this value won't fit into a 16 bit offset, then go
3077 find a macro that will generate the 32 bit offset
3079 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3081 normalize_constant_expr (imm_expr
);
3082 if (imm_expr
->X_op
!= O_constant
3083 || (*oparg
== '0' && imm_expr
->X_add_number
!= 0)
3085 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
3086 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
3092 case 'p': /* PC-relative offset. */
3094 *imm_reloc
= BFD_RELOC_12_PCREL
;
3095 my_getExpression (imm_expr
, asarg
);
3099 case 'u': /* Upper 20 bits. */
3100 p
= percent_op_utype
;
3101 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3103 if (imm_expr
->X_op
!= O_constant
)
3106 if (imm_expr
->X_add_number
< 0
3107 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
3108 as_bad (_("lui expression not in range 0..1048575"));
3110 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
3111 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
3116 case 'a': /* 20-bit PC-relative offset. */
3118 my_getExpression (imm_expr
, asarg
);
3120 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
3124 my_getExpression (imm_expr
, asarg
);
3126 if (strcmp (asarg
, "@plt") == 0)
3128 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
3135 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
, p
)
3136 || imm_expr
->X_op
!= O_constant
3137 || imm_expr
->X_add_number
< 0
3138 || imm_expr
->X_add_number
>= 128
3139 || (imm_expr
->X_add_number
& 0x3) != 3)
3141 as_bad (_("bad value for opcode field, "
3142 "value must be 0...127 and "
3143 "lower 2 bits must be 0x3"));
3146 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
3147 imm_expr
->X_op
= O_absent
;
3152 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
, p
)
3153 || imm_expr
->X_op
!= O_constant
3154 || imm_expr
->X_add_number
< 0
3155 || imm_expr
->X_add_number
>= 3)
3157 as_bad (_("bad value for opcode field, "
3158 "value must be 0...2"));
3161 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
3162 imm_expr
->X_op
= O_absent
;
3167 goto unknown_riscv_ip_operand
;
3175 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3176 || imm_expr
->X_op
!= O_constant
3177 || imm_expr
->X_add_number
< 0
3178 || imm_expr
->X_add_number
>= 128)
3180 as_bad (_("bad value for funct7 field, "
3181 "value must be 0...127"));
3184 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
3185 imm_expr
->X_op
= O_absent
;
3190 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3191 || imm_expr
->X_op
!= O_constant
3192 || imm_expr
->X_add_number
< 0
3193 || imm_expr
->X_add_number
>= 8)
3195 as_bad (_("bad value for funct3 field, "
3196 "value must be 0...7"));
3199 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
3200 imm_expr
->X_op
= O_absent
;
3205 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3206 || imm_expr
->X_op
!= O_constant
3207 || imm_expr
->X_add_number
< 0
3208 || imm_expr
->X_add_number
>= 4)
3210 as_bad (_("bad value for funct2 field, "
3211 "value must be 0...3"));
3214 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
3215 imm_expr
->X_op
= O_absent
;
3220 goto unknown_riscv_ip_operand
;
3224 case 'y': /* bs immediate */
3225 my_getExpression (imm_expr
, asarg
);
3226 check_absolute_expr (ip
, imm_expr
, FALSE
);
3227 if ((unsigned long)imm_expr
->X_add_number
> 3)
3228 as_bad(_("Improper bs immediate (%lu)"),
3229 (unsigned long)imm_expr
->X_add_number
);
3230 INSERT_OPERAND(BS
, *ip
, imm_expr
->X_add_number
);
3231 imm_expr
->X_op
= O_absent
;
3235 case 'Y': /* rnum immediate */
3236 my_getExpression (imm_expr
, asarg
);
3237 check_absolute_expr (ip
, imm_expr
, FALSE
);
3238 if ((unsigned long)imm_expr
->X_add_number
> 10)
3239 as_bad(_("Improper rnum immediate (%lu)"),
3240 (unsigned long)imm_expr
->X_add_number
);
3241 INSERT_OPERAND(RNUM
, *ip
, imm_expr
->X_add_number
);
3242 imm_expr
->X_op
= O_absent
;
3247 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3248 || imm_expr
->X_op
!= O_constant
3249 || imm_expr
->X_add_number
!= 0)
3252 imm_expr
->X_op
= O_absent
;
3255 case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */
3256 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3258 my_getExpression (imm_expr
, asarg
);
3259 check_absolute_expr (ip
, imm_expr
, false);
3260 if (((unsigned) (imm_expr
->X_add_number
) & 0x1fU
)
3261 || imm_expr
->X_add_number
>= (signed) RISCV_IMM_REACH
/ 2
3262 || imm_expr
->X_add_number
< -(signed) RISCV_IMM_REACH
/ 2)
3263 as_bad (_("improper prefetch offset (%ld)"),
3264 (long) imm_expr
->X_add_number
);
3266 ENCODE_STYPE_IMM ((unsigned) (imm_expr
->X_add_number
) &
3268 imm_expr
->X_op
= O_absent
;
3273 unknown_riscv_ip_operand
:
3274 as_fatal (_("internal: unknown argument type `%s'"),
3280 insn_with_csr
= false;
3284 /* Restore the character we might have clobbered above. */
3286 *(asargStart
- 1) = save_c
;
3291 /* Similar to riscv_ip, but assembles an instruction according to the
3292 hardcode values of .insn directive. */
3295 riscv_ip_hardcode (char *str
,
3296 struct riscv_cl_insn
*ip
,
3297 expressionS
*imm_expr
,
3300 struct riscv_opcode
*insn
;
3301 insn_t values
[2] = {0, 0};
3302 unsigned int num
= 0;
3304 input_line_pointer
= str
;
3307 expression (imm_expr
);
3308 if (imm_expr
->X_op
!= O_constant
)
3310 /* The first value isn't constant, so it should be
3311 .insn <type> <operands>. We have been parsed it
3315 return _("values must be constant");
3317 values
[num
++] = (insn_t
) imm_expr
->X_add_number
;
3319 while (*input_line_pointer
++ == ',' && num
< 2);
3321 input_line_pointer
--;
3322 if (*input_line_pointer
!= '\0')
3323 return _("unrecognized values");
3325 insn
= XNEW (struct riscv_opcode
);
3326 insn
->match
= values
[num
- 1];
3327 create_insn (ip
, insn
);
3328 unsigned int bytes
= riscv_insn_length (insn
->match
);
3329 if ((bytes
< sizeof(values
[0]) && values
[num
- 1] >> (8 * bytes
) != 0)
3330 || (num
== 2 && values
[0] != bytes
))
3331 return _("value conflicts with instruction length");
3337 md_assemble (char *str
)
3339 struct riscv_cl_insn insn
;
3340 expressionS imm_expr
;
3341 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3343 /* The architecture and privileged elf attributes should be set
3344 before assembling. */
3345 if (!start_assemble
)
3347 start_assemble
= true;
3349 riscv_set_abi_by_arch ();
3350 if (!riscv_set_default_priv_spec (NULL
))
3354 riscv_mapping_state (MAP_INSN
, 0);
3356 const struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
3357 &imm_reloc
, op_hash
);
3361 if (error
.missing_ext
)
3362 as_bad ("%s `%s', extension `%s' required", error
.msg
,
3363 error
.statement
, error
.missing_ext
);
3365 as_bad ("%s `%s'", error
.msg
, error
.statement
);
3369 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3370 macro (&insn
, &imm_expr
, &imm_reloc
);
3372 append_insn (&insn
, &imm_expr
, imm_reloc
);
3376 md_atof (int type
, char *litP
, int *sizeP
)
3378 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
3382 md_number_to_chars (char *buf
, valueT val
, int n
)
3384 if (target_big_endian
)
3385 number_to_chars_bigendian (buf
, val
, n
);
3387 number_to_chars_littleendian (buf
, val
, n
);
3390 const char *md_shortopts
= "O::g::G:";
3394 OPTION_MARCH
= OPTION_MD_BASE
,
3401 OPTION_NO_ARCH_ATTR
,
3403 OPTION_NO_CSR_CHECK
,
3407 OPTION_LITTLE_ENDIAN
,
3411 struct option md_longopts
[] =
3413 {"march", required_argument
, NULL
, OPTION_MARCH
},
3414 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
3415 {"fpic", no_argument
, NULL
, OPTION_PIC
},
3416 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
3417 {"mabi", required_argument
, NULL
, OPTION_MABI
},
3418 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
3419 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
3420 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
3421 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
3422 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
3423 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
3424 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
3425 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
3426 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
3427 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
3429 {NULL
, no_argument
, NULL
, 0}
3431 size_t md_longopts_size
= sizeof (md_longopts
);
3434 md_parse_option (int c
, const char *arg
)
3439 default_arch_with_ext
= arg
;
3443 riscv_opts
.pic
= false;
3447 riscv_opts
.pic
= true;
3451 if (strcmp (arg
, "ilp32") == 0)
3452 riscv_set_abi (32, FLOAT_ABI_SOFT
, false);
3453 else if (strcmp (arg
, "ilp32e") == 0)
3454 riscv_set_abi (32, FLOAT_ABI_SOFT
, true);
3455 else if (strcmp (arg
, "ilp32f") == 0)
3456 riscv_set_abi (32, FLOAT_ABI_SINGLE
, false);
3457 else if (strcmp (arg
, "ilp32d") == 0)
3458 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, false);
3459 else if (strcmp (arg
, "ilp32q") == 0)
3460 riscv_set_abi (32, FLOAT_ABI_QUAD
, false);
3461 else if (strcmp (arg
, "lp64") == 0)
3462 riscv_set_abi (64, FLOAT_ABI_SOFT
, false);
3463 else if (strcmp (arg
, "lp64f") == 0)
3464 riscv_set_abi (64, FLOAT_ABI_SINGLE
, false);
3465 else if (strcmp (arg
, "lp64d") == 0)
3466 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, false);
3467 else if (strcmp (arg
, "lp64q") == 0)
3468 riscv_set_abi (64, FLOAT_ABI_QUAD
, false);
3471 explicit_mabi
= true;
3475 riscv_opts
.relax
= true;
3478 case OPTION_NO_RELAX
:
3479 riscv_opts
.relax
= false;
3482 case OPTION_ARCH_ATTR
:
3483 riscv_opts
.arch_attr
= true;
3486 case OPTION_NO_ARCH_ATTR
:
3487 riscv_opts
.arch_attr
= false;
3490 case OPTION_CSR_CHECK
:
3491 riscv_opts
.csr_check
= true;
3494 case OPTION_NO_CSR_CHECK
:
3495 riscv_opts
.csr_check
= false;
3498 case OPTION_MISA_SPEC
:
3499 return riscv_set_default_isa_spec (arg
);
3501 case OPTION_MPRIV_SPEC
:
3502 return riscv_set_default_priv_spec (arg
);
3504 case OPTION_BIG_ENDIAN
:
3505 target_big_endian
= 1;
3508 case OPTION_LITTLE_ENDIAN
:
3509 target_big_endian
= 0;
3520 riscv_after_parse_args (void)
3522 /* The --with-arch is optional for now, so we still need to set the xlen
3523 according to the default_arch, which is set by the --target. */
3526 if (strcmp (default_arch
, "riscv32") == 0)
3528 else if (strcmp (default_arch
, "riscv64") == 0)
3531 as_bad ("unknown default architecture `%s'", default_arch
);
3534 /* Set default specs. */
3535 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
3536 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
3537 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
3538 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
3540 riscv_set_arch (default_arch_with_ext
);
3542 /* If the CIE to be produced has not been overridden on the command line,
3543 then produce version 3 by default. This allows us to use the full
3544 range of registers in a .cfi_return_column directive. */
3545 if (flag_dwarf_cie_version
== -1)
3546 flag_dwarf_cie_version
= 3;
3550 md_pcrel_from (fixS
*fixP
)
3552 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3555 /* Apply a fixup to the object file. */
3558 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
3560 unsigned int subtype
;
3561 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
3562 bool relaxable
= false;
3566 /* Remember value for tc_gen_reloc. */
3567 fixP
->fx_addnumber
= *valP
;
3569 switch (fixP
->fx_r_type
)
3571 case BFD_RELOC_RISCV_HI20
:
3572 case BFD_RELOC_RISCV_LO12_I
:
3573 case BFD_RELOC_RISCV_LO12_S
:
3574 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
3575 | bfd_getl32 (buf
), buf
);
3576 if (fixP
->fx_addsy
== NULL
)
3577 fixP
->fx_done
= true;
3581 case BFD_RELOC_RISCV_GOT_HI20
:
3582 case BFD_RELOC_RISCV_ADD8
:
3583 case BFD_RELOC_RISCV_ADD16
:
3584 case BFD_RELOC_RISCV_ADD32
:
3585 case BFD_RELOC_RISCV_ADD64
:
3586 case BFD_RELOC_RISCV_SUB6
:
3587 case BFD_RELOC_RISCV_SUB8
:
3588 case BFD_RELOC_RISCV_SUB16
:
3589 case BFD_RELOC_RISCV_SUB32
:
3590 case BFD_RELOC_RISCV_SUB64
:
3591 case BFD_RELOC_RISCV_RELAX
:
3594 case BFD_RELOC_RISCV_TPREL_HI20
:
3595 case BFD_RELOC_RISCV_TPREL_LO12_I
:
3596 case BFD_RELOC_RISCV_TPREL_LO12_S
:
3597 case BFD_RELOC_RISCV_TPREL_ADD
:
3601 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
3602 case BFD_RELOC_RISCV_TLS_GD_HI20
:
3603 case BFD_RELOC_RISCV_TLS_DTPREL32
:
3604 case BFD_RELOC_RISCV_TLS_DTPREL64
:
3605 if (fixP
->fx_addsy
!= NULL
)
3606 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3609 _("TLS relocation against a constant"));
3613 /* Use pc-relative relocation for FDE initial location.
3614 The symbol address in .eh_frame may be adjusted in
3615 _bfd_elf_discard_section_eh_frame, and the content of
3616 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3617 Therefore, we cannot insert a relocation whose addend symbol is
3618 in .eh_frame. Othrewise, the value may be adjusted twice. */
3619 if (fixP
->fx_addsy
&& fixP
->fx_subsy
3620 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
3621 && strcmp (sub_segment
->name
, ".eh_frame") == 0
3622 && S_GET_VALUE (fixP
->fx_subsy
)
3623 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
3625 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
3626 fixP
->fx_subsy
= NULL
;
3633 case BFD_RELOC_RISCV_CFA
:
3634 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
3636 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3637 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
3638 fixP
->fx_next
->fx_subsy
= NULL
;
3639 fixP
->fx_next
->fx_offset
= 0;
3640 fixP
->fx_subsy
= NULL
;
3642 switch (fixP
->fx_r_type
)
3645 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
3646 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
3650 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
3651 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3655 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
3656 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3660 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
3661 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3664 case BFD_RELOC_RISCV_CFA
:
3665 /* Load the byte to get the subtype. */
3666 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
3667 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
3670 case DW_CFA_advance_loc1
:
3671 fixP
->fx_where
= loc
+ 1;
3672 fixP
->fx_next
->fx_where
= loc
+ 1;
3673 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
3674 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3677 case DW_CFA_advance_loc2
:
3679 fixP
->fx_next
->fx_size
= 2;
3680 fixP
->fx_where
= loc
+ 1;
3681 fixP
->fx_next
->fx_where
= loc
+ 1;
3682 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
3683 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3686 case DW_CFA_advance_loc4
:
3688 fixP
->fx_next
->fx_size
= 4;
3689 fixP
->fx_where
= loc
;
3690 fixP
->fx_next
->fx_where
= loc
;
3691 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3692 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3696 if (subtype
< 0x80 && (subtype
& 0x40))
3698 /* DW_CFA_advance_loc */
3699 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3700 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3701 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3702 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3705 as_fatal (_("internal: bad CFA value #%d"), subtype
);
3711 /* This case is unreachable. */
3718 /* If we are deleting this reloc entry, we must fill in the
3719 value now. This can happen if we have a .word which is not
3720 resolved when it appears but is later defined. */
3721 if (fixP
->fx_addsy
== NULL
)
3723 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3724 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3729 case BFD_RELOC_RISCV_JMP
:
3732 /* Fill in a tentative value to improve objdump readability. */
3733 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3734 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3735 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_JTYPE_IMM (delta
), buf
);
3739 case BFD_RELOC_12_PCREL
:
3742 /* Fill in a tentative value to improve objdump readability. */
3743 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3744 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3745 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_BTYPE_IMM (delta
), buf
);
3749 case BFD_RELOC_RISCV_RVC_BRANCH
:
3752 /* Fill in a tentative value to improve objdump readability. */
3753 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3754 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3755 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CBTYPE_IMM (delta
), buf
);
3759 case BFD_RELOC_RISCV_RVC_JUMP
:
3762 /* Fill in a tentative value to improve objdump readability. */
3763 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3764 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3765 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CJTYPE_IMM (delta
), buf
);
3769 case BFD_RELOC_RISCV_CALL
:
3770 case BFD_RELOC_RISCV_CALL_PLT
:
3774 case BFD_RELOC_RISCV_PCREL_HI20
:
3775 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3776 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3777 relaxable
= riscv_opts
.relax
;
3780 case BFD_RELOC_RISCV_ALIGN
:
3784 /* We ignore generic BFD relocations we don't know about. */
3785 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3786 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
3789 if (fixP
->fx_subsy
!= NULL
)
3790 as_bad_subtract (fixP
);
3792 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3793 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3795 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3796 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3797 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3798 fixP
->fx_next
->fx_size
= 0;
3802 /* Because the value of .cfi_remember_state may changed after relaxation,
3803 we insert a fix to relocate it again in link-time. */
3806 riscv_pre_output_hook (void)
3808 const frchainS
*frch
;
3811 /* Save the current segment info. */
3813 subsegT subseg
= now_subseg
;
3815 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3816 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3820 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3822 if (frag
->fr_type
== rs_cfa
)
3825 expressionS
*symval
;
3827 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3828 exp
.X_op
= O_subtract
;
3829 exp
.X_add_symbol
= symval
->X_add_symbol
;
3830 exp
.X_add_number
= 0;
3831 exp
.X_op_symbol
= symval
->X_op_symbol
;
3833 /* We must set the segment before creating a frag after all
3834 frag chains have been chained together. */
3835 subseg_set (s
, frch
->frch_subseg
);
3837 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3838 BFD_RELOC_RISCV_CFA
);
3843 /* Restore the original segment info. */
3844 subseg_set (seg
, subseg
);
3847 /* Handle the .option pseudo-op. */
3850 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3852 char *name
= input_line_pointer
, ch
;
3854 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3855 ++input_line_pointer
;
3856 ch
= *input_line_pointer
;
3857 *input_line_pointer
= '\0';
3859 if (strcmp (name
, "rvc") == 0)
3861 riscv_update_subset (&riscv_rps_as
, "+c");
3862 riscv_set_rvc (true);
3864 else if (strcmp (name
, "norvc") == 0)
3866 riscv_update_subset (&riscv_rps_as
, "-c");
3867 riscv_set_rvc (false);
3869 else if (strcmp (name
, "pic") == 0)
3870 riscv_opts
.pic
= true;
3871 else if (strcmp (name
, "nopic") == 0)
3872 riscv_opts
.pic
= false;
3873 else if (strcmp (name
, "relax") == 0)
3874 riscv_opts
.relax
= true;
3875 else if (strcmp (name
, "norelax") == 0)
3876 riscv_opts
.relax
= false;
3877 else if (strcmp (name
, "csr-check") == 0)
3878 riscv_opts
.csr_check
= true;
3879 else if (strcmp (name
, "no-csr-check") == 0)
3880 riscv_opts
.csr_check
= false;
3881 else if (strncmp (name
, "arch,", 5) == 0)
3884 if (ISSPACE (*name
) && *name
!= '\0')
3886 riscv_update_subset (&riscv_rps_as
, name
);
3888 riscv_set_rvc (false);
3889 if (riscv_subset_supports (&riscv_rps_as
, "c"))
3890 riscv_set_rvc (true);
3892 if (riscv_subset_supports (&riscv_rps_as
, "ztso"))
3895 else if (strcmp (name
, "push") == 0)
3897 struct riscv_option_stack
*s
;
3899 s
= XNEW (struct riscv_option_stack
);
3900 s
->next
= riscv_opts_stack
;
3901 s
->options
= riscv_opts
;
3902 s
->subset_list
= riscv_subsets
;
3903 riscv_opts_stack
= s
;
3904 riscv_subsets
= riscv_copy_subset_list (s
->subset_list
);
3905 riscv_rps_as
.subset_list
= riscv_subsets
;
3907 else if (strcmp (name
, "pop") == 0)
3909 struct riscv_option_stack
*s
;
3911 s
= riscv_opts_stack
;
3913 as_bad (_(".option pop with no .option push"));
3916 riscv_subset_list_t
*release_subsets
= riscv_subsets
;
3917 riscv_opts_stack
= s
->next
;
3918 riscv_opts
= s
->options
;
3919 riscv_subsets
= s
->subset_list
;
3920 riscv_rps_as
.subset_list
= riscv_subsets
;
3921 riscv_release_subset_list (release_subsets
);
3927 as_warn (_("unrecognized .option directive: %s\n"), name
);
3929 *input_line_pointer
= ch
;
3930 demand_empty_rest_of_line ();
3933 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3934 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3935 use in DWARF debug information. */
3938 s_dtprel (int bytes
)
3945 if (ex
.X_op
!= O_symbol
)
3947 as_bad (_("unsupported use of %s"), (bytes
== 8
3950 ignore_rest_of_line ();
3953 p
= frag_more (bytes
);
3954 md_number_to_chars (p
, 0, bytes
);
3955 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, false,
3957 ? BFD_RELOC_RISCV_TLS_DTPREL64
3958 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3960 demand_empty_rest_of_line ();
3963 /* Handle the .bss pseudo-op. */
3966 s_bss (int ignore ATTRIBUTE_UNUSED
)
3968 subseg_set (bss_section
, 0);
3969 demand_empty_rest_of_line ();
3973 riscv_make_nops (char *buf
, bfd_vma bytes
)
3977 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3978 means we are not within a valid instruction sequence. It is thus safe
3979 to use a zero byte, even though that is not a valid instruction. */
3983 /* Use at most one 2-byte NOP. */
3984 if ((bytes
- i
) % 4 == 2)
3986 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3990 /* Fill the remainder with 4-byte NOPs. */
3991 for ( ; i
< bytes
; i
+= 4)
3992 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3995 /* Called from md_do_align. Used to create an alignment frag in a
3996 code section by emitting a worst-case NOP sequence that the linker
3997 will later relax to the correct number of NOPs. We can't compute
3998 the correct alignment now because of other linker relaxations. */
4001 riscv_frag_align_code (int n
)
4003 bfd_vma bytes
= (bfd_vma
) 1 << n
;
4004 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
4005 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
4009 /* If we are moving to a smaller alignment than the instruction size, then no
4010 alignment is required. */
4011 if (bytes
<= insn_alignment
)
4014 /* When not relaxing, riscv_handle_align handles code alignment. */
4015 if (!riscv_opts
.relax
)
4018 nops
= frag_more (worst_case_bytes
);
4020 ex
.X_op
= O_constant
;
4021 ex
.X_add_number
= worst_case_bytes
;
4023 riscv_make_nops (nops
, worst_case_bytes
);
4025 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
4026 &ex
, false, BFD_RELOC_RISCV_ALIGN
);
4028 riscv_mapping_state (MAP_INSN
, worst_case_bytes
);
4030 /* We need to start a new frag after the alignment which may be removed by
4031 the linker, to prevent the assembler from computing static offsets.
4032 This is necessary to get correct EH info. */
4033 frag_wane (frag_now
);
4039 /* Implement HANDLE_ALIGN. */
4042 riscv_handle_align (fragS
*fragP
)
4044 switch (fragP
->fr_type
)
4047 /* When relaxing, riscv_frag_align_code handles code alignment. */
4048 if (!riscv_opts
.relax
)
4050 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
4051 - fragP
->fr_address
- fragP
->fr_fix
);
4052 /* We have 4 byte uncompressed nops. */
4053 bfd_signed_vma size
= 4;
4054 bfd_signed_vma excess
= bytes
% size
;
4055 bfd_boolean odd_padding
= (excess
% 2 == 1);
4056 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
4061 /* Insert zeros or compressed nops to get 4 byte alignment. */
4065 riscv_add_odd_padding_symbol (fragP
);
4066 riscv_make_nops (p
, excess
);
4067 fragP
->fr_fix
+= excess
;
4071 /* The frag will be changed to `rs_fill` later. The function
4072 `write_contents` will try to fill the remaining spaces
4073 according to the patterns we give. In this case, we give
4074 a 4 byte uncompressed nop as the pattern, and set the size
4075 of the pattern into `fr_var`. The nop will be output to the
4076 file `fr_offset` times. However, `fr_offset` could be zero
4077 if we don't need to pad the boundary finally. */
4078 riscv_make_nops (p
, size
);
4079 fragP
->fr_var
= size
;
4088 /* This usually called from frag_var. */
4091 riscv_init_frag (fragS
* fragP
, int max_chars
)
4093 /* Do not add mapping symbol to debug sections. */
4094 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
4097 switch (fragP
->fr_type
)
4102 riscv_mapping_state (MAP_DATA
, max_chars
);
4105 riscv_mapping_state (MAP_INSN
, max_chars
);
4113 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
4115 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false));
4118 /* Translate internal representation of relocation info to BFD target
4122 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
4124 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4126 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4127 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4128 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4129 reloc
->addend
= fixp
->fx_addnumber
;
4131 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4132 if (reloc
->howto
== NULL
)
4134 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
4135 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
4137 /* We don't have R_RISCV_8/16, but for this special case,
4138 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
4142 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4143 _("cannot represent %s relocation in object file"),
4144 bfd_get_reloc_code_name (fixp
->fx_r_type
));
4152 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
4154 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
4156 offsetT old_var
= fragp
->fr_var
;
4157 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
4158 return fragp
->fr_var
- old_var
;
4164 /* Expand far branches to multi-instruction sequences. */
4167 md_convert_frag_branch (fragS
*fragp
)
4175 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
4177 exp
.X_op
= O_symbol
;
4178 exp
.X_add_symbol
= fragp
->fr_symbol
;
4179 exp
.X_add_number
= fragp
->fr_offset
;
4181 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
4183 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
4185 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4189 /* Expand the RVC branch into a RISC-V one. */
4190 insn
= bfd_getl16 (buf
);
4191 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
4192 if ((insn
& MASK_C_J
) == MATCH_C_J
)
4194 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
4195 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
4196 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
4197 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
4198 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
4199 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
4202 bfd_putl32 (insn
, buf
);
4206 /* Invert the branch condition. Branch over the jump. */
4207 insn
= bfd_getl16 (buf
);
4208 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
4209 insn
|= ENCODE_CBTYPE_IMM (6);
4210 bfd_putl16 (insn
, buf
);
4215 /* Just keep the RVC branch. */
4216 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4217 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
4218 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4219 2, &exp
, false, reloc
);
4228 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4231 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
4233 /* Invert the branch condition. Branch over the jump. */
4234 insn
= bfd_getl32 (buf
);
4235 insn
^= MATCH_BEQ
^ MATCH_BNE
;
4236 insn
|= ENCODE_BTYPE_IMM (8);
4237 bfd_putl32 (insn
, buf
);
4241 /* Jump to the target. */
4242 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4243 4, &exp
, false, BFD_RELOC_RISCV_JMP
);
4244 bfd_putl32 (MATCH_JAL
, buf
);
4249 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4250 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
4251 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4252 4, &exp
, false, reloc
);
4261 fixp
->fx_file
= fragp
->fr_file
;
4262 fixp
->fx_line
= fragp
->fr_line
;
4264 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
4265 + fragp
->fr_fix
+ fragp
->fr_var
);
4267 fragp
->fr_fix
+= fragp
->fr_var
;
4270 /* Relax a machine dependent frag. This returns the amount by which
4271 the current size of the frag should change. */
4274 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
4277 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
4278 md_convert_frag_branch (fragp
);
4282 md_show_usage (FILE *stream
)
4284 fprintf (stream
, _("\
4286 -fpic or -fPIC generate position-independent code\n\
4287 -fno-pic don't generate position-independent code (default)\n\
4288 -march=ISA set the RISC-V architecture\n\
4289 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
4290 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\
4291 -mabi=ABI set the RISC-V ABI\n\
4292 -mrelax enable relax (default)\n\
4293 -mno-relax disable relax\n\
4294 -march-attr generate RISC-V arch attribute\n\
4295 -mno-arch-attr don't generate RISC-V arch attribute\n\
4296 -mcsr-check enable the csr ISA and privilege spec version checks\n\
4297 -mno-csr-check disable the csr ISA and privilege spec version checks (default)\n\
4298 -mbig-endian assemble for big-endian\n\
4299 -mlittle-endian assemble for little-endian\n\
4303 /* Standard calling conventions leave the CFA at SP on entry. */
4306 riscv_cfi_frame_initial_instructions (void)
4308 cfi_add_CFA_def_cfa_register (X_SP
);
4312 tc_riscv_regname_to_dw2regnum (char *regname
)
4316 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
4319 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
4322 /* CSRs are numbered 4096 -> 8191. */
4323 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
4326 as_bad (_("unknown register `%s'"), regname
);
4331 riscv_elf_final_processing (void)
4333 riscv_set_abi_by_arch ();
4334 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
4337 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
4338 since these directives break relaxation when used with symbol deltas. */
4341 s_riscv_leb128 (int sign
)
4344 char *save_in
= input_line_pointer
;
4347 if (exp
.X_op
!= O_constant
)
4348 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
4349 demand_empty_rest_of_line ();
4351 input_line_pointer
= save_in
;
4352 return s_leb128 (sign
);
4355 /* Parse the .insn directive. There are three formats,
4356 Format 1: .insn <type> <operand1>, <operand2>, ...
4357 Format 2: .insn <length>, <value>
4358 Format 3: .insn <value>. */
4361 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
4363 char *str
= input_line_pointer
;
4364 struct riscv_cl_insn insn
;
4365 expressionS imm_expr
;
4366 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
4369 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4370 ++input_line_pointer
;
4372 save_c
= *input_line_pointer
;
4373 *input_line_pointer
= '\0';
4375 riscv_mapping_state (MAP_INSN
, 0);
4377 struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
4378 &imm_reloc
, insn_type_hash
);
4381 char *save_in
= input_line_pointer
;
4382 error
.msg
= riscv_ip_hardcode (str
, &insn
, &imm_expr
, error
.msg
);
4383 input_line_pointer
= save_in
;
4388 if (error
.missing_ext
)
4389 as_bad ("%s `%s', extension `%s' required", error
.msg
, error
.statement
,
4392 as_bad ("%s `%s'", error
.msg
, error
.statement
);
4396 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
4397 append_insn (&insn
, &imm_expr
, imm_reloc
);
4400 *input_line_pointer
= save_c
;
4401 demand_empty_rest_of_line ();
4404 /* Update architecture and privileged elf attributes. If we don't set
4405 them, then try to output the default ones. */
4408 riscv_write_out_attrs (void)
4410 const char *arch_str
, *priv_str
, *p
;
4411 /* versions[0]: major version.
4412 versions[1]: minor version.
4413 versions[2]: revision version. */
4414 unsigned versions
[3] = {0}, number
= 0;
4417 /* Re-write architecture elf attribute. */
4418 arch_str
= riscv_arch_str (xlen
, riscv_subsets
);
4419 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
4420 xfree ((void *) arch_str
);
4422 /* For the file without any instruction, we don't set the default_priv_spec
4423 according to the privileged elf attributes since the md_assemble isn't
4426 && !riscv_set_default_priv_spec (NULL
))
4429 /* If we already have set privileged elf attributes, then no need to do
4430 anything. Otherwise, don't generate or update them when no CSR and
4431 privileged instructions are used. */
4432 if (!explicit_priv_attr
)
4435 RISCV_GET_PRIV_SPEC_NAME (priv_str
, default_priv_spec
);
4437 for (i
= 0; *p
; ++p
)
4439 if (*p
== '.' && i
< 3)
4441 versions
[i
++] = number
;
4444 else if (ISDIGIT (*p
))
4445 number
= (number
* 10) + (*p
- '0');
4448 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
4452 versions
[i
] = number
;
4454 /* Re-write privileged elf attributes. */
4455 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
4456 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
4457 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
4460 /* Add the default contents for the .riscv.attributes section. */
4463 riscv_set_public_attributes (void)
4465 if (riscv_opts
.arch_attr
|| explicit_attr
)
4466 riscv_write_out_attrs ();
4469 /* Called after all assembly has been done. */
4472 riscv_md_finish (void)
4474 riscv_set_public_attributes ();
4477 /* Adjust the symbol table. */
4480 riscv_adjust_symtab (void)
4482 bfd_map_over_sections (stdoutput
, riscv_check_mapping_symbols
, (char *) 0);
4483 elf_adjust_symtab ();
4486 /* Given a symbolic attribute NAME, return the proper integer value.
4487 Returns -1 if the attribute is not known. */
4490 riscv_convert_symbolic_attribute (const char *name
)
4499 /* When you modify this table you should
4500 also modify the list in doc/c-riscv.texi. */
4501 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
4505 T(priv_spec_revision
),
4506 T(unaligned_access
),
4515 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
4516 if (strcmp (name
, attribute_table
[i
].name
) == 0)
4517 return attribute_table
[i
].tag
;
4522 /* Parse a .attribute directive. */
4525 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
4527 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4529 obj_attribute
*attr
;
4531 explicit_attr
= true;
4534 case Tag_RISCV_arch
:
4536 attr
= elf_known_obj_attributes_proc (stdoutput
);
4537 if (!start_assemble
)
4538 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
4540 as_fatal (_("architecture elf attributes must set before "
4541 "any instructions"));
4543 if (old_xlen
!= xlen
)
4545 /* We must re-init bfd again if xlen is changed. */
4546 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
4547 bfd_find_target (riscv_target_format (), stdoutput
);
4549 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
4550 as_warn (_("could not set architecture and machine"));
4554 case Tag_RISCV_priv_spec
:
4555 case Tag_RISCV_priv_spec_minor
:
4556 case Tag_RISCV_priv_spec_revision
:
4558 as_fatal (_("privileged elf attributes must set before "
4559 "any instructions"));
4567 /* Mark symbol that it follows a variant CC convention. */
4570 s_variant_cc (int ignored ATTRIBUTE_UNUSED
)
4576 elf_symbol_type
*elfsym
;
4578 c
= get_symbol_name (&name
);
4580 as_bad (_("missing symbol name for .variant_cc directive"));
4581 sym
= symbol_find_or_make (name
);
4582 restore_line_pointer (c
);
4583 demand_empty_rest_of_line ();
4585 bfdsym
= symbol_get_bfdsym (sym
);
4586 elfsym
= elf_symbol_from (bfdsym
);
4587 gas_assert (elfsym
);
4588 elfsym
->internal_elf_sym
.st_other
|= STO_RISCV_VARIANT_CC
;
4591 /* Same as elf_copy_symbol_attributes, but without copying st_other.
4592 This is needed so RISC-V specific st_other values can be independently
4593 specified for an IFUNC resolver (that is called by the dynamic linker)
4594 and the symbol it resolves (aliased to the resolver). In particular,
4595 if a function symbol has special st_other value set via directives,
4596 then attaching an IFUNC resolver to that symbol should not override
4597 the st_other setting. Requiring the directive on the IFUNC resolver
4598 symbol would be unexpected and problematic in C code, where the two
4599 symbols appear as two independent function declarations. */
4602 riscv_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
4604 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
4605 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
4606 /* If size is unset, copy size from src. Because we don't track whether
4607 .size has been used, we can't differentiate .size dest, 0 from the case
4608 where dest's size is unset. */
4609 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
4613 destelf
->size
= XNEW (expressionS
);
4614 *destelf
->size
= *srcelf
->size
;
4616 S_SET_SIZE (dest
, S_GET_SIZE (src
));
4620 /* RISC-V pseudo-ops table. */
4621 static const pseudo_typeS riscv_pseudo_table
[] =
4623 {"option", s_riscv_option
, 0},
4627 {"dtprelword", s_dtprel
, 4},
4628 {"dtpreldword", s_dtprel
, 8},
4630 {"uleb128", s_riscv_leb128
, 0},
4631 {"sleb128", s_riscv_leb128
, 1},
4632 {"insn", s_riscv_insn
, 0},
4633 {"attribute", s_riscv_attribute
, 0},
4634 {"variant_cc", s_variant_cc
, 0},
4635 {"float16", float_cons
, 'h'},
4641 riscv_pop_insert (void)
4643 extern void pop_insert (const pseudo_typeS
*);
4645 pop_insert (riscv_pseudo_table
);