1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
68 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
72 /* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
78 #ifndef DEFAULT_RISCV_ISA_SPEC
79 #define DEFAULT_RISCV_ISA_SPEC "2.2"
82 #ifndef DEFAULT_RISCV_PRIV_SPEC
83 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
86 static const char default_arch
[] = DEFAULT_ARCH
;
87 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
88 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
89 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
91 static unsigned xlen
= 0; /* width of an x-register */
92 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
93 static bfd_boolean rve_abi
= FALSE
;
95 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
96 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
98 static unsigned elf_flags
= 0;
100 /* Set the default_isa_spec. Return 0 if the input spec string isn't
101 supported. Otherwise, return 1. */
104 riscv_set_default_isa_spec (const char *s
)
106 enum riscv_isa_spec_class
class;
107 if (!riscv_get_isa_spec_class (s
, &class))
109 as_bad ("Unknown default ISA spec `%s' set by "
110 "-misa-spec or --with-isa-spec", s
);
114 default_isa_spec
= class;
118 /* Set the default_priv_spec, assembler will find the suitable CSR address
119 according to default_priv_spec. We will try to check priv attributes if
120 the input string is NULL. Return 0 if the input priv spec string isn't
121 supported. Otherwise, return 1. */
124 riscv_set_default_priv_spec (const char *s
)
126 enum riscv_priv_spec_class
class;
127 unsigned major
, minor
, revision
;
130 /* Find the corresponding priv spec class. */
131 if (riscv_get_priv_spec_class (s
, &class))
133 default_priv_spec
= class;
139 as_bad (_("Unknown default privilege spec `%s' set by "
140 "-mpriv-spec or --with-priv-spec"), s
);
144 /* Try to set the default_priv_spec according to the priv attributes. */
145 attr
= elf_known_obj_attributes_proc (stdoutput
);
146 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
147 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
148 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
150 if (riscv_get_priv_spec_class_from_numbers (major
,
155 /* The priv attributes setting 0.0.0 is meaningless. We should have set
156 the default_priv_spec by md_parse_option and riscv_after_parse_args,
157 so just skip the following setting. */
158 if (class == PRIV_SPEC_CLASS_NONE
)
161 default_priv_spec
= class;
165 /* Still can not find the priv spec class. */
166 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
167 "privilege attributes"), major
, minor
, revision
);
171 /* This is the set of options which the .option pseudo-op may modify. */
173 struct riscv_set_options
175 int pic
; /* Generate position-independent code. */
176 int rvc
; /* Generate RVC code. */
177 int rve
; /* Generate RVE code. */
178 int relax
; /* Emit relocs the linker is allowed to relax. */
179 int arch_attr
; /* Emit arch attribute. */
180 int csr_check
; /* Enable the CSR checking. */
183 static struct riscv_set_options riscv_opts
=
189 DEFAULT_RISCV_ATTR
, /* arch_attr */
194 riscv_set_rvc (bfd_boolean rvc_value
)
197 elf_flags
|= EF_RISCV_RVC
;
199 riscv_opts
.rvc
= rvc_value
;
203 riscv_set_rve (bfd_boolean rve_value
)
205 riscv_opts
.rve
= rve_value
;
208 static riscv_subset_list_t riscv_subsets
;
211 riscv_subset_supports (const char *feature
)
213 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
216 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
220 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
224 case INSN_CLASS_I
: return riscv_subset_supports ("i");
225 case INSN_CLASS_C
: return riscv_subset_supports ("c");
226 case INSN_CLASS_A
: return riscv_subset_supports ("a");
227 case INSN_CLASS_M
: return riscv_subset_supports ("m");
228 case INSN_CLASS_F
: return riscv_subset_supports ("f");
229 case INSN_CLASS_D
: return riscv_subset_supports ("d");
230 case INSN_CLASS_D_AND_C
:
231 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
233 case INSN_CLASS_F_AND_C
:
234 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
236 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
239 as_fatal ("Unreachable");
244 /* Handle of the extension with version hash table. */
245 static struct hash_control
*ext_version_hash
= NULL
;
247 static struct hash_control
*
248 init_ext_version_hash (const struct riscv_ext_version
*table
)
251 struct hash_control
*hash
= hash_new ();
253 while (table
[i
].name
)
255 const char *name
= table
[i
].name
;
256 const char *hash_error
=
257 hash_insert (hash
, name
, (void *) &table
[i
]);
259 if (hash_error
!= NULL
)
261 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
262 table
[i
].name
, hash_error
);
263 /* Probably a memory allocation problem? Give up now. */
264 as_fatal (_("Broken assembler. No assembly attempted."));
270 && strcmp (table
[i
].name
, name
) == 0)
278 riscv_get_default_ext_version (const char *name
,
279 unsigned int *major_version
,
280 unsigned int *minor_version
)
282 struct riscv_ext_version
*ext
;
287 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
290 ext
= (struct riscv_ext_version
*) hash_find (ext_version_hash
, name
);
293 && strcmp (ext
->name
, name
) == 0)
295 if (ext
->isa_spec_class
== default_isa_spec
)
297 *major_version
= ext
->major_version
;
298 *minor_version
= ext
->minor_version
;
305 /* Set which ISA and extensions are available. */
308 riscv_set_arch (const char *s
)
310 riscv_parse_subset_t rps
;
311 rps
.subset_list
= &riscv_subsets
;
312 rps
.error_handler
= as_fatal
;
314 rps
.get_default_version
= riscv_get_default_ext_version
;
319 riscv_release_subset_list (&riscv_subsets
);
320 riscv_parse_subset (&rps
, s
);
323 /* Handle of the OPCODE hash table. */
324 static struct hash_control
*op_hash
= NULL
;
326 /* Handle of the type of .insn hash table. */
327 static struct hash_control
*insn_type_hash
= NULL
;
329 /* This array holds the chars that always start a comment. If the
330 pre-processor is disabled, these aren't very useful */
331 const char comment_chars
[] = "#";
333 /* This array holds the chars that only start a comment at the beginning of
334 a line. If the line seems to have the form '# 123 filename'
335 .line and .file directives will appear in the pre-processed output */
336 /* Note that input_file.c hand checks for '#' at the beginning of the
337 first line of the input file. This is because the compiler outputs
338 #NO_APP at the beginning of its output. */
339 /* Also note that C style comments are always supported. */
340 const char line_comment_chars
[] = "#";
342 /* This array holds machine specific line separator characters. */
343 const char line_separator_chars
[] = ";";
345 /* Chars that can be used to separate mant from exp in floating point nums */
346 const char EXP_CHARS
[] = "eE";
348 /* Chars that mean this number is a floating point constant */
351 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
353 /* Indicate we are already assemble any instructions or not. */
354 static bfd_boolean start_assemble
= FALSE
;
356 /* Indicate ELF attributes are explictly set. */
357 static bfd_boolean explicit_attr
= FALSE
;
359 /* Indicate CSR are explictly used. */
360 static bfd_boolean explicit_csr
= FALSE
;
362 /* Macros for encoding relaxation state for RVC branches and far jumps. */
363 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
366 | ((uncond) ? 1 : 0) \
369 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
370 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
371 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
372 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
374 /* Is the given value a sign-extended 32-bit value? */
375 #define IS_SEXT_32BIT_NUM(x) \
376 (((x) &~ (offsetT) 0x7fffffff) == 0 \
377 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
379 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
380 #define IS_ZEXT_32BIT_NUM(x) \
381 (((x) &~ (offsetT) 0xffffffff) == 0 \
382 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
384 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
385 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
386 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
387 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
389 /* Determine if an instruction matches an opcode. */
390 #define OPCODE_MATCHES(OPCODE, OP) \
391 (((OPCODE) & MASK_##OP) == MATCH_##OP)
393 static char *expr_end
;
395 /* The default target format to use. */
398 riscv_target_format (void)
400 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
403 /* Return the length of instruction INSN. */
405 static inline unsigned int
406 insn_length (const struct riscv_cl_insn
*insn
)
408 return riscv_insn_length (insn
->insn_opcode
);
411 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
414 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
417 insn
->insn_opcode
= mo
->match
;
423 /* Install INSN at the location specified by its "frag" and "where" fields. */
426 install_insn (const struct riscv_cl_insn
*insn
)
428 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
429 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
432 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
433 and install the opcode in the new location. */
436 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
440 if (insn
->fixp
!= NULL
)
442 insn
->fixp
->fx_frag
= frag
;
443 insn
->fixp
->fx_where
= where
;
448 /* Add INSN to the end of the output. */
451 add_fixed_insn (struct riscv_cl_insn
*insn
)
453 char *f
= frag_more (insn_length (insn
));
454 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
458 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
459 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
461 frag_grow (max_chars
);
462 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
463 frag_var (rs_machine_dependent
, max_chars
, var
,
464 subtype
, symbol
, offset
, NULL
);
467 /* Compute the length of a branch sequence, and adjust the stored length
468 accordingly. If FRAGP is NULL, the worst-case length is returned. */
471 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
473 int jump
, rvc
, length
= 8;
478 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
479 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
480 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
482 /* Assume jumps are in range; the linker will catch any that aren't. */
483 length
= jump
? 4 : 8;
485 if (fragp
->fr_symbol
!= NULL
486 && S_IS_DEFINED (fragp
->fr_symbol
)
487 && !S_IS_WEAK (fragp
->fr_symbol
)
488 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
490 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
491 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
492 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
494 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
496 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
498 else if (!jump
&& rvc
)
503 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
508 /* Information about an opcode name, mnemonics and its value. */
515 /* List for all supported opcode name. */
516 static const struct opcode_name_t opcode_name_list
[] =
561 /* Hash table for lookup opcode name. */
562 static struct hash_control
*opcode_names_hash
= NULL
;
564 /* Initialization for hash table of opcode name. */
566 init_opcode_names_hash (void)
569 const struct opcode_name_t
*opcode
;
571 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
573 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
576 as_fatal (_("internal error: can't hash `%s': %s"),
577 opcode
->name
, retval
);
581 /* Find `s` is a valid opcode name or not,
582 return the opcode name info if found. */
583 static const struct opcode_name_t
*
584 opcode_name_lookup (char **s
)
588 struct opcode_name_t
*o
;
590 /* Find end of name. */
592 if (is_name_beginner (*e
))
594 while (is_part_of_name (*e
))
597 /* Terminate name. */
601 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
603 /* Advance to next token if one was recognized. */
622 static struct hash_control
*reg_names_hash
= NULL
;
623 static struct hash_control
*csr_extra_hash
= NULL
;
625 #define ENCODE_REG_HASH(cls, n) \
626 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
627 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
628 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
631 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
633 void *hash
= ENCODE_REG_HASH (class, n
);
634 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
637 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
641 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
645 for (i
= 0; i
< n
; i
++)
646 hash_reg_name (class, names
[i
], i
);
649 /* Init hash table csr_extra_hash to handle CSR. */
651 riscv_init_csr_hash (const char *name
,
653 enum riscv_csr_class
class,
654 enum riscv_priv_spec_class define_version
,
655 enum riscv_priv_spec_class abort_version
)
657 struct riscv_csr_extra
*entry
, *pre_entry
;
658 const char *hash_error
= NULL
;
659 bfd_boolean need_enrty
= TRUE
;
662 entry
= (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, name
);
663 while (need_enrty
&& entry
!= NULL
)
665 if (entry
->csr_class
== class
666 && entry
->address
== address
667 && entry
->define_version
== define_version
668 && entry
->abort_version
== abort_version
)
674 /* Duplicate setting for the CSR, just return and do nothing. */
678 entry
= XNEW (struct riscv_csr_extra
);
679 entry
->csr_class
= class;
680 entry
->address
= address
;
681 entry
->define_version
= define_version
;
682 entry
->abort_version
= abort_version
;
685 /* If the CSR hasn't been inserted in the hash table, then insert it.
686 Otherwise, attach the extra information to the entry which is already
687 in the hash table. */
688 if (pre_entry
== NULL
)
690 hash_error
= hash_insert (csr_extra_hash
, name
, (void *) entry
);
691 if (hash_error
!= NULL
)
693 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
695 /* Probably a memory allocation problem? Give up now. */
696 as_fatal (_("Broken assembler. No assembly attempted."));
700 pre_entry
->next
= entry
;
703 /* Check wether the CSR is valid according to the ISA. */
706 riscv_csr_class_check (const char *s
,
707 enum riscv_csr_class csr_class
)
709 bfd_boolean result
= TRUE
;
711 /* Don't check the ISA dependency when -mcsr-check isn't set. */
712 if (!riscv_opts
.csr_check
)
718 result
= riscv_subset_supports ("i");
721 result
= riscv_subset_supports ("f");
724 result
= (xlen
== 32 && riscv_subset_supports ("i"));
727 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
731 as_warn (_("Invalid CSR `%s' for the current ISA"), s
);
734 /* Check and find the CSR address according to the privilege spec version. */
737 riscv_csr_version_check (const char *csr_name
,
738 struct riscv_csr_extra
**entryP
)
740 struct riscv_csr_extra
*entry
= *entryP
;
742 while (entry
!= NULL
)
744 if (default_priv_spec
>= entry
->define_version
745 && default_priv_spec
< entry
->abort_version
)
747 /* Find the suitable CSR according to the specific version. */
754 /* We can not find the suitable CSR address according to the privilege
755 version. Therefore, we use the last defined value. Report the warning
756 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
757 otherwise, you may get the unexpected CSR address. */
758 if (riscv_opts
.csr_check
)
760 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
762 if (priv_name
!= NULL
)
763 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
764 csr_name
, priv_name
);
768 /* Once the CSR is defined, including the old privilege spec, then we call
769 riscv_csr_class_check and riscv_csr_version_check to do the further checking
770 and get the corresponding address. Return -1 if the CSR is never been
771 defined. Otherwise, return the address. */
774 reg_csr_lookup_internal (const char *s
)
776 struct riscv_csr_extra
*r
=
777 (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, s
);
782 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
783 the CSR was defined, but isn't allowed for the current ISA setting or
784 the privilege spec. If the CSR is never been defined, then assembler
785 will regard it as a "Unknown CSR" and report error. If user use number
786 to set the CSR, but over the range (> 0xfff), then assembler will report
787 "Improper CSR" error for it. */
788 riscv_csr_class_check (s
, r
->csr_class
);
789 riscv_csr_version_check (s
, &r
);
795 reg_lookup_internal (const char *s
, enum reg_class
class)
799 if (class == RCLASS_CSR
)
800 return reg_csr_lookup_internal (s
);
802 r
= hash_find (reg_names_hash
, s
);
803 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
806 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
809 return DECODE_REG_NUM (r
);
813 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
819 /* Find end of name. */
821 if (is_name_beginner (*e
))
823 while (is_part_of_name (*e
))
826 /* Terminate name. */
830 /* Look for the register. Advance to next token if one was recognized. */
831 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
841 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
843 const char *p
= strchr (*s
, ',');
844 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
849 for (i
= 0; i
< size
; i
++)
850 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
860 /* For consistency checking, verify that all bits are specified either
861 by the match/mask part of the instruction definition, or by the
864 `length` could be 0, 4 or 8, 0 for auto detection. */
866 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
868 const char *p
= opc
->args
;
870 insn_t used_bits
= opc
->mask
;
872 insn_t required_bits
;
875 insn_width
= 8 * riscv_insn_length (opc
->match
);
877 insn_width
= 8 * length
;
879 required_bits
= ~0ULL >> (64 - insn_width
);
881 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
883 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
884 opc
->name
, opc
->args
);
888 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
895 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
896 case 'c': break; /* RS1, constrained to equal sp */
897 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
898 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
899 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
900 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
901 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
902 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
903 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
904 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
905 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
906 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
907 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
908 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
909 case 'w': break; /* RS1S, constrained to equal RD */
910 case 'x': break; /* RS2S, constrained to equal RD */
911 case 'z': break; /* RS2S, contrained to be x0 */
912 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
913 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
914 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
915 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
916 case 'U': break; /* RS1, constrained to equal RD */
917 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
918 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
919 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
920 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
921 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
922 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
923 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
924 case 'F': /* funct */
927 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
928 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
929 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
930 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
932 as_bad (_("internal: bad RISC-V opcode"
933 " (unknown operand type `CF%c'): %s %s"),
934 c
, opc
->name
, opc
->args
);
939 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
940 c
, opc
->name
, opc
->args
);
947 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
948 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
950 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
951 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
952 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
954 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
955 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
956 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
957 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
958 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
959 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
960 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
961 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
962 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
963 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
964 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
966 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
967 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
968 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
969 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
970 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
976 case 'F': /* funct */
979 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
980 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
981 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
983 as_bad (_("internal: bad RISC-V opcode"
984 " (unknown operand type `F%c'): %s %s"),
985 c
, opc
->name
, opc
->args
);
989 case 'O': /* opcode */
992 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
993 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
995 as_bad (_("internal: bad RISC-V opcode"
996 " (unknown operand type `F%c'): %s %s"),
997 c
, opc
->name
, opc
->args
);
1002 as_bad (_("internal: bad RISC-V opcode "
1003 "(unknown operand type `%c'): %s %s"),
1004 c
, opc
->name
, opc
->args
);
1008 if (used_bits
!= required_bits
)
1010 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1011 ~(unsigned long)(used_bits
& required_bits
),
1012 opc
->name
, opc
->args
);
1018 struct percent_op_match
1021 bfd_reloc_code_real_type reloc
;
1024 /* Common hash table initialization function for
1025 instruction and .insn directive. */
1026 static struct hash_control
*
1027 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1028 bfd_boolean insn_directive_p
)
1032 struct hash_control
*hash
= hash_new ();
1033 while (opcodes
[i
].name
)
1035 const char *name
= opcodes
[i
].name
;
1036 const char *hash_error
=
1037 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
1039 if (hash_error
!= NULL
)
1041 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1042 opcodes
[i
].name
, hash_error
);
1043 /* Probably a memory allocation problem? Give up now. */
1044 as_fatal (_("Broken assembler. No assembly attempted."));
1049 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1051 if (insn_directive_p
)
1052 length
= ((name
[0] == 'c') ? 2 : 4);
1054 length
= 0; /* Let assembler determine the length. */
1055 if (!validate_riscv_insn (&opcodes
[i
], length
))
1056 as_fatal (_("Broken assembler. No assembly attempted."));
1059 gas_assert (!insn_directive_p
);
1062 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1068 /* This function is called once, at assembler startup time. It should set up
1069 all the tables, etc. that the MD part of the assembler will need. */
1074 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1076 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1077 as_warn (_("Could not set architecture and machine"));
1079 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1080 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1082 reg_names_hash
= hash_new ();
1083 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1084 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1085 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1086 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1087 /* Add "fp" as an alias for "s0". */
1088 hash_reg_name (RCLASS_GPR
, "fp", 8);
1090 /* Create and insert CSR hash tables. */
1091 csr_extra_hash
= hash_new ();
1092 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1093 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1094 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1095 DECLARE_CSR(name, num, class, define_version, abort_version);
1096 #include "opcode/riscv-opc.h"
1099 opcode_names_hash
= hash_new ();
1100 init_opcode_names_hash ();
1102 /* Set the default alignment for the text section. */
1103 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1107 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1114 case BFD_RELOC_RISCV_HI20
:
1115 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1117 case BFD_RELOC_RISCV_LO12_S
:
1118 return ENCODE_STYPE_IMM (value
);
1120 case BFD_RELOC_RISCV_LO12_I
:
1121 return ENCODE_ITYPE_IMM (value
);
1128 /* Output an instruction. IP is the instruction information.
1129 ADDRESS_EXPR is an operand of the instruction to be used with
1133 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1134 bfd_reloc_code_real_type reloc_type
)
1136 dwarf2_emit_insn (0);
1138 if (reloc_type
!= BFD_RELOC_UNUSED
)
1140 reloc_howto_type
*howto
;
1142 gas_assert (address_expr
);
1143 if (reloc_type
== BFD_RELOC_12_PCREL
1144 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1146 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1147 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1148 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1149 add_relaxed_insn (ip
, worst_case
, best_case
,
1150 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1151 address_expr
->X_add_symbol
,
1152 address_expr
->X_add_number
);
1157 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1159 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1161 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1162 bfd_get_reloc_size (howto
),
1163 address_expr
, FALSE
, reloc_type
);
1165 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1169 add_fixed_insn (ip
);
1172 /* We need to start a new frag after any instruction that can be
1173 optimized away or compressed by the linker during relaxation, to prevent
1174 the assembler from computing static offsets across such an instruction.
1175 This is necessary to get correct EH info. */
1176 if (reloc_type
== BFD_RELOC_RISCV_CALL
1177 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
1178 || reloc_type
== BFD_RELOC_RISCV_HI20
1179 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1180 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1181 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1183 frag_wane (frag_now
);
1188 /* Build an instruction created by a macro expansion. This is passed
1189 a pointer to the count of instructions created so far, an
1190 expression, the name of the instruction to build, an operand format
1191 string, and corresponding arguments. */
1194 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1196 const struct riscv_opcode
*mo
;
1197 struct riscv_cl_insn insn
;
1198 bfd_reloc_code_real_type r
;
1201 va_start (args
, fmt
);
1203 r
= BFD_RELOC_UNUSED
;
1204 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
1207 /* Find a non-RVC variant of the instruction. append_insn will compress
1209 while (riscv_insn_length (mo
->match
) < 4)
1211 gas_assert (strcmp (name
, mo
->name
) == 0);
1213 create_insn (&insn
, mo
);
1219 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1223 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1227 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1231 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1237 gas_assert (ep
!= NULL
);
1238 r
= va_arg (args
, int);
1246 as_fatal (_("internal error: invalid macro"));
1251 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1253 append_insn (&insn
, ep
, r
);
1256 /* Build an instruction created by a macro expansion. Like md_assemble but
1257 accept a printf-style format string and arguments. */
1260 md_assemblef (const char *format
, ...)
1266 va_start (ap
, format
);
1268 r
= vasprintf (&buf
, format
, ap
);
1271 as_fatal (_("internal error: vasprintf failed"));
1279 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1282 normalize_constant_expr (expressionS
*ex
)
1286 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1287 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1288 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1292 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1293 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1296 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1297 bfd_boolean maybe_csr
)
1299 if (ex
->X_op
== O_big
)
1300 as_bad (_("unsupported large constant"));
1301 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1302 as_bad (_("unknown CSR `%s'"),
1303 S_GET_NAME (ex
->X_add_symbol
));
1304 else if (ex
->X_op
!= O_constant
)
1305 as_bad (_("Instruction %s requires absolute expression"),
1307 normalize_constant_expr (ex
);
1311 make_internal_label (void)
1313 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1314 (valueT
) frag_now_fix (), frag_now
);
1317 /* Load an entry from the GOT. */
1319 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1320 const char *lo_insn
, const char *lo_pattern
,
1321 bfd_reloc_code_real_type hi_reloc
,
1322 bfd_reloc_code_real_type lo_reloc
)
1325 ep2
.X_op
= O_symbol
;
1326 ep2
.X_add_symbol
= make_internal_label ();
1327 ep2
.X_add_number
= 0;
1329 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1330 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1334 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1335 bfd_reloc_code_real_type hi_reloc
,
1336 bfd_reloc_code_real_type lo_reloc
)
1338 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1342 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1343 bfd_reloc_code_real_type hi_reloc
,
1344 bfd_reloc_code_real_type lo_reloc
)
1346 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1349 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1351 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1352 bfd_reloc_code_real_type reloc
)
1354 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1355 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1358 /* Load an integer constant into a register. */
1361 load_const (int reg
, expressionS
*ep
)
1363 int shift
= RISCV_IMM_BITS
;
1364 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1365 expressionS upper
= *ep
, lower
= *ep
;
1366 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1367 upper
.X_add_number
-= lower
.X_add_number
;
1369 if (ep
->X_op
!= O_constant
)
1371 as_bad (_("unsupported large constant"));
1375 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1377 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1378 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1381 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1382 load_const (reg
, &upper
);
1384 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1385 if (lower
.X_add_number
!= 0)
1386 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1387 lower
.X_add_number
);
1391 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1394 if (upper
.X_add_number
!= 0)
1396 /* Discard low part and zero-extend upper immediate. */
1397 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1399 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1403 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1404 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1405 lower
.X_add_number
);
1409 /* Expand RISC-V assembly macros into one or more instructions. */
1411 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1412 bfd_reloc_code_real_type
*imm_reloc
)
1414 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1415 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1416 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1417 int mask
= ip
->insn_mo
->mask
;
1422 load_const (rd
, imm_expr
);
1427 /* Load the address of a symbol into a register. */
1428 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1429 as_bad (_("offset too large"));
1431 if (imm_expr
->X_op
== O_constant
)
1432 load_const (rd
, imm_expr
);
1433 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1434 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1435 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1436 else /* Local PIC symbol, or any non-PIC symbol */
1437 pcrel_load (rd
, rd
, imm_expr
, "addi",
1438 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1442 pcrel_load (rd
, rd
, imm_expr
, "addi",
1443 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1447 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1448 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1452 pcrel_load (rd
, rd
, imm_expr
, "lb",
1453 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1457 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1458 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1462 pcrel_load (rd
, rd
, imm_expr
, "lh",
1463 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1467 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1468 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1472 pcrel_load (rd
, rd
, imm_expr
, "lw",
1473 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1477 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1478 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1482 pcrel_load (rd
, rd
, imm_expr
, "ld",
1483 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1487 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1488 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1492 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1493 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1497 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1498 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1502 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1503 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1507 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1508 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1512 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1513 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1517 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1518 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1522 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1523 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1527 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1531 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1536 static const struct percent_op_match percent_op_utype
[] =
1538 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1539 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1540 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1541 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1542 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1543 {"%hi", BFD_RELOC_RISCV_HI20
},
1547 static const struct percent_op_match percent_op_itype
[] =
1549 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1550 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1551 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1555 static const struct percent_op_match percent_op_stype
[] =
1557 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1558 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1559 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1563 static const struct percent_op_match percent_op_rtype
[] =
1565 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1569 static const struct percent_op_match percent_op_null
[] =
1574 /* Return true if *STR points to a relocation operator. When returning true,
1575 move *STR over the operator and store its relocation code in *RELOC.
1576 Leave both *STR and *RELOC alone when returning false. */
1579 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1580 const struct percent_op_match
*percent_op
)
1582 for ( ; percent_op
->str
; percent_op
++)
1583 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1585 int len
= strlen (percent_op
->str
);
1587 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1590 *str
+= strlen (percent_op
->str
);
1591 *reloc
= percent_op
->reloc
;
1593 /* Check whether the output BFD supports this relocation.
1594 If not, issue an error and fall back on something safe. */
1595 if (*reloc
!= BFD_RELOC_UNUSED
1596 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1598 as_bad ("relocation %s isn't supported by the current ABI",
1600 *reloc
= BFD_RELOC_UNUSED
;
1608 my_getExpression (expressionS
*ep
, char *str
)
1612 save_in
= input_line_pointer
;
1613 input_line_pointer
= str
;
1615 expr_end
= input_line_pointer
;
1616 input_line_pointer
= save_in
;
1619 /* Parse string STR as a 16-bit relocatable operand. Store the
1620 expression in *EP and the relocation, if any, in RELOC.
1621 Return the number of relocation operators used (0 or 1).
1623 On exit, EXPR_END points to the first character after the expression. */
1626 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1627 char *str
, const struct percent_op_match
*percent_op
)
1630 unsigned crux_depth
, str_depth
, regno
;
1633 /* First, check for integer registers. No callers can accept a reg, but
1634 we need to avoid accidentally creating a useless undefined symbol below,
1635 if this is an instruction pattern that can't match. A glibc build fails
1636 if this is removed. */
1637 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1639 ep
->X_op
= O_register
;
1640 ep
->X_add_number
= regno
;
1645 /* Search for the start of the main expression.
1646 End the loop with CRUX pointing to the start
1647 of the main expression and with CRUX_DEPTH containing the number
1648 of open brackets at that point. */
1655 crux_depth
= str_depth
;
1657 /* Skip over whitespace and brackets, keeping count of the number
1659 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1665 && parse_relocation (&str
, reloc
, percent_op
));
1667 my_getExpression (ep
, crux
);
1670 /* Match every open bracket. */
1671 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1676 as_bad ("unclosed '('");
1683 /* Parse opcode name, could be an mnemonics or number. */
1685 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1686 char *str
, const struct percent_op_match
*percent_op
)
1688 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1692 ep
->X_op
= O_constant
;
1693 ep
->X_add_number
= o
->val
;
1697 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1700 /* Detect and handle implicitly zero load-store offsets. For example,
1701 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1702 an implicit offset was detected. */
1705 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1707 /* Check whether there is only a single bracketed expression left.
1708 If so, it must be the base register and the constant must be zero. */
1709 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1711 ep
->X_op
= O_constant
;
1712 ep
->X_add_number
= 0;
1719 /* All RISC-V CSR instructions belong to one of these classes. */
1729 /* Return which CSR instruction is checking. */
1731 static enum csr_insn_type
1732 riscv_csr_insn_type (insn_t insn
)
1734 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1735 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1737 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1738 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1740 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1741 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1744 return INSN_NOT_CSR
;
1747 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1748 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1749 CSR address is 0x3. */
1752 riscv_csr_read_only_check (insn_t insn
)
1754 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1755 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1756 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1757 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1760 && (((csr_insn
== INSN_CSRRS
1761 || csr_insn
== INSN_CSRRC
)
1763 || csr_insn
== INSN_CSRRW
))
1769 /* This routine assembles an instruction into its binary format. As a
1770 side effect, it sets the global variable imm_reloc to the type of
1771 relocation to do if one of the operands is an address expression. */
1774 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1775 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1780 struct riscv_opcode
*insn
;
1785 const struct percent_op_match
*p
;
1786 const char *error
= "unrecognized opcode";
1787 /* Indicate we are assembling instruction with CSR. */
1788 bfd_boolean insn_with_csr
= FALSE
;
1790 /* Parse the name of the instruction. Terminate the string if whitespace
1791 is found so that hash_find only sees the name part of the string. */
1792 for (s
= str
; *s
!= '\0'; ++s
)
1800 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1803 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1805 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1808 if (!riscv_multi_subset_supports (insn
->insn_class
))
1811 create_insn (ip
, insn
);
1814 imm_expr
->X_op
= O_absent
;
1815 *imm_reloc
= BFD_RELOC_UNUSED
;
1816 p
= percent_op_itype
;
1818 for (args
= insn
->args
;; ++args
)
1820 s
+= strspn (s
, " \t");
1823 case '\0': /* End of args. */
1824 if (insn
->pinfo
!= INSN_MACRO
)
1826 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1829 /* For .insn, insn->match and insn->mask are 0. */
1830 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1836 /* Check if we write a read-only CSR by the CSR
1839 && riscv_opts
.csr_check
1840 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1842 /* Restore the character in advance, since we want to
1843 report the detailed warning message here. */
1845 *(argsStart
- 1) = save_c
;
1846 as_warn (_("Read-only CSR is written `%s'"), str
);
1847 insn_with_csr
= FALSE
;
1852 /* Successful assembly. */
1854 insn_with_csr
= FALSE
;
1860 case 's': /* RS1 x8-x15 */
1861 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1862 || !(regno
>= 8 && regno
<= 15))
1864 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1866 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1867 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1868 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1871 case 't': /* RS2 x8-x15 */
1872 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1873 || !(regno
>= 8 && regno
<= 15))
1875 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1877 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1878 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1879 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1882 case 'U': /* RS1, constrained to equal RD. */
1883 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1884 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1888 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1890 INSERT_OPERAND (CRS2
, *ip
, regno
);
1892 case 'c': /* RS1, constrained to equal sp. */
1893 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1897 case 'z': /* RS2, contrained to equal x0. */
1898 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1903 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1904 || imm_expr
->X_op
!= O_constant
1905 || imm_expr
->X_add_number
<= 0
1906 || imm_expr
->X_add_number
>= 64)
1908 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1911 imm_expr
->X_op
= O_absent
;
1914 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1915 || imm_expr
->X_op
!= O_constant
1916 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1917 || imm_expr
->X_add_number
<= 0
1918 || imm_expr
->X_add_number
>= 32)
1920 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1923 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1924 || imm_expr
->X_op
!= O_constant
1925 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1926 || imm_expr
->X_add_number
< 0
1927 || imm_expr
->X_add_number
>= 256)
1929 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1932 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1933 || imm_expr
->X_op
!= O_constant
1934 || imm_expr
->X_add_number
== 0
1935 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1937 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1940 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1941 || imm_expr
->X_op
!= O_constant
1942 || imm_expr
->X_add_number
== 0
1943 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1945 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1948 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1950 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1951 || imm_expr
->X_op
!= O_constant
1952 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1954 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1957 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1959 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1960 || imm_expr
->X_op
!= O_constant
1961 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1963 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1966 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1968 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1969 || imm_expr
->X_op
!= O_constant
1970 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1973 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1976 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1978 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1979 || imm_expr
->X_op
!= O_constant
1980 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1983 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1986 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1987 || imm_expr
->X_op
!= O_constant
1988 /* C.addiw, c.li, and c.andi allow zero immediate.
1989 C.addi allows zero immediate as hint. Otherwise this
1991 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1993 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1996 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1997 || imm_expr
->X_op
!= O_constant
1998 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1999 || imm_expr
->X_add_number
== 0)
2002 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2005 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2006 || imm_expr
->X_op
!= O_constant
2007 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
2008 || imm_expr
->X_add_number
== 0)
2011 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2014 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2016 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2017 || imm_expr
->X_op
!= O_constant
2018 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
2021 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2024 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2026 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2027 || imm_expr
->X_op
!= O_constant
2028 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
2031 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2034 p
= percent_op_utype
;
2035 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2038 if (imm_expr
->X_op
!= O_constant
2039 || imm_expr
->X_add_number
<= 0
2040 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2041 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2042 && (imm_expr
->X_add_number
<
2043 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2045 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2048 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2049 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2050 || ((int32_t)imm_expr
->X_add_number
2051 != imm_expr
->X_add_number
))
2053 imm_expr
->X_add_number
=
2054 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2060 case 'S': /* Floating-point RS1 x8-x15. */
2061 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2062 || !(regno
>= 8 && regno
<= 15))
2064 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2066 case 'D': /* Floating-point RS2 x8-x15. */
2067 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2068 || !(regno
>= 8 && regno
<= 15))
2070 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2072 case 'T': /* Floating-point RS2. */
2073 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2075 INSERT_OPERAND (CRS2
, *ip
, regno
);
2081 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2082 || imm_expr
->X_op
!= O_constant
2083 || imm_expr
->X_add_number
< 0
2084 || imm_expr
->X_add_number
>= 64)
2086 as_bad (_("bad value for funct6 field, "
2087 "value must be 0...64"));
2091 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2092 imm_expr
->X_op
= O_absent
;
2096 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2097 || imm_expr
->X_op
!= O_constant
2098 || imm_expr
->X_add_number
< 0
2099 || imm_expr
->X_add_number
>= 16)
2101 as_bad (_("bad value for funct4 field, "
2102 "value must be 0...15"));
2106 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2107 imm_expr
->X_op
= O_absent
;
2111 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2112 || imm_expr
->X_op
!= O_constant
2113 || imm_expr
->X_add_number
< 0
2114 || imm_expr
->X_add_number
>= 8)
2116 as_bad (_("bad value for funct3 field, "
2117 "value must be 0...7"));
2120 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2121 imm_expr
->X_op
= O_absent
;
2125 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2126 || imm_expr
->X_op
!= O_constant
2127 || imm_expr
->X_add_number
< 0
2128 || imm_expr
->X_add_number
>= 4)
2130 as_bad (_("bad value for funct2 field, "
2131 "value must be 0...3"));
2134 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2135 imm_expr
->X_op
= O_absent
;
2139 as_bad (_("bad compressed FUNCT field"
2140 " specifier 'CF%c'\n"),
2146 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2165 case '<': /* Shift amount, 0 - 31. */
2166 my_getExpression (imm_expr
, s
);
2167 check_absolute_expr (ip
, imm_expr
, FALSE
);
2168 if ((unsigned long) imm_expr
->X_add_number
> 31)
2169 as_bad (_("Improper shift amount (%lu)"),
2170 (unsigned long) imm_expr
->X_add_number
);
2171 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2172 imm_expr
->X_op
= O_absent
;
2176 case '>': /* Shift amount, 0 - (XLEN-1). */
2177 my_getExpression (imm_expr
, s
);
2178 check_absolute_expr (ip
, imm_expr
, FALSE
);
2179 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2180 as_bad (_("Improper shift amount (%lu)"),
2181 (unsigned long) imm_expr
->X_add_number
);
2182 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2183 imm_expr
->X_op
= O_absent
;
2187 case 'Z': /* CSRRxI immediate. */
2188 my_getExpression (imm_expr
, s
);
2189 check_absolute_expr (ip
, imm_expr
, FALSE
);
2190 if ((unsigned long) imm_expr
->X_add_number
> 31)
2191 as_bad (_("Improper CSRxI immediate (%lu)"),
2192 (unsigned long) imm_expr
->X_add_number
);
2193 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2194 imm_expr
->X_op
= O_absent
;
2198 case 'E': /* Control register. */
2199 insn_with_csr
= TRUE
;
2200 explicit_csr
= TRUE
;
2201 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2202 INSERT_OPERAND (CSR
, *ip
, regno
);
2205 my_getExpression (imm_expr
, s
);
2206 check_absolute_expr (ip
, imm_expr
, TRUE
);
2207 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2208 as_bad (_("Improper CSR address (%lu)"),
2209 (unsigned long) imm_expr
->X_add_number
);
2210 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2211 imm_expr
->X_op
= O_absent
;
2216 case 'm': /* Rounding mode. */
2217 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2219 INSERT_OPERAND (RM
, *ip
, regno
);
2225 case 'Q': /* Fence predecessor/successor. */
2226 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2230 INSERT_OPERAND (PRED
, *ip
, regno
);
2232 INSERT_OPERAND (SUCC
, *ip
, regno
);
2237 case 'd': /* Destination register. */
2238 case 's': /* Source register. */
2239 case 't': /* Target register. */
2240 case 'r': /* rs3. */
2241 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2247 /* Now that we have assembled one operand, we use the args
2248 string to figure out where it goes in the instruction. */
2252 INSERT_OPERAND (RS1
, *ip
, regno
);
2255 INSERT_OPERAND (RD
, *ip
, regno
);
2258 INSERT_OPERAND (RS2
, *ip
, regno
);
2261 INSERT_OPERAND (RS3
, *ip
, regno
);
2268 case 'D': /* Floating point rd. */
2269 case 'S': /* Floating point rs1. */
2270 case 'T': /* Floating point rs2. */
2271 case 'U': /* Floating point rs1 and rs2. */
2272 case 'R': /* Floating point rs3. */
2273 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2281 INSERT_OPERAND (RD
, *ip
, regno
);
2284 INSERT_OPERAND (RS1
, *ip
, regno
);
2287 INSERT_OPERAND (RS1
, *ip
, regno
);
2290 INSERT_OPERAND (RS2
, *ip
, regno
);
2293 INSERT_OPERAND (RS3
, *ip
, regno
);
2302 my_getExpression (imm_expr
, s
);
2303 if (imm_expr
->X_op
!= O_big
2304 && imm_expr
->X_op
!= O_constant
)
2306 normalize_constant_expr (imm_expr
);
2311 my_getExpression (imm_expr
, s
);
2312 normalize_constant_expr (imm_expr
);
2313 /* The 'A' format specifier must be a symbol. */
2314 if (imm_expr
->X_op
!= O_symbol
)
2316 *imm_reloc
= BFD_RELOC_32
;
2321 my_getExpression (imm_expr
, s
);
2322 normalize_constant_expr (imm_expr
);
2323 /* The 'B' format specifier must be a symbol or a constant. */
2324 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2326 if (imm_expr
->X_op
== O_symbol
)
2327 *imm_reloc
= BFD_RELOC_32
;
2331 case 'j': /* Sign-extended immediate. */
2332 p
= percent_op_itype
;
2333 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2335 case 'q': /* Store displacement. */
2336 p
= percent_op_stype
;
2337 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2339 case 'o': /* Load displacement. */
2340 p
= percent_op_itype
;
2341 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2343 case '1': /* 4-operand add, must be %tprel_add. */
2344 p
= percent_op_rtype
;
2346 case '0': /* AMO "displacement," which must be zero. */
2347 p
= percent_op_null
;
2349 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2352 /* If this value won't fit into a 16 bit offset, then go
2353 find a macro that will generate the 32 bit offset
2355 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2357 normalize_constant_expr (imm_expr
);
2358 if (imm_expr
->X_op
!= O_constant
2359 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2361 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2362 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2369 case 'p': /* PC-relative offset. */
2371 *imm_reloc
= BFD_RELOC_12_PCREL
;
2372 my_getExpression (imm_expr
, s
);
2376 case 'u': /* Upper 20 bits. */
2377 p
= percent_op_utype
;
2378 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2380 if (imm_expr
->X_op
!= O_constant
)
2383 if (imm_expr
->X_add_number
< 0
2384 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2385 as_bad (_("lui expression not in range 0..1048575"));
2387 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2388 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2393 case 'a': /* 20-bit PC-relative offset. */
2395 my_getExpression (imm_expr
, s
);
2397 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2401 my_getExpression (imm_expr
, s
);
2403 if (strcmp (s
, "@plt") == 0)
2405 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2409 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2415 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2416 || imm_expr
->X_op
!= O_constant
2417 || imm_expr
->X_add_number
< 0
2418 || imm_expr
->X_add_number
>= 128
2419 || (imm_expr
->X_add_number
& 0x3) != 3)
2421 as_bad (_("bad value for opcode field, "
2422 "value must be 0...127 and "
2423 "lower 2 bits must be 0x3"));
2427 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2428 imm_expr
->X_op
= O_absent
;
2432 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2433 || imm_expr
->X_op
!= O_constant
2434 || imm_expr
->X_add_number
< 0
2435 || imm_expr
->X_add_number
>= 3)
2437 as_bad (_("bad value for opcode field, "
2438 "value must be 0...2"));
2442 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2443 imm_expr
->X_op
= O_absent
;
2447 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2455 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2456 || imm_expr
->X_op
!= O_constant
2457 || imm_expr
->X_add_number
< 0
2458 || imm_expr
->X_add_number
>= 128)
2460 as_bad (_("bad value for funct7 field, "
2461 "value must be 0...127"));
2465 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2466 imm_expr
->X_op
= O_absent
;
2470 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2471 || imm_expr
->X_op
!= O_constant
2472 || imm_expr
->X_add_number
< 0
2473 || imm_expr
->X_add_number
>= 8)
2475 as_bad (_("bad value for funct3 field, "
2476 "value must be 0...7"));
2480 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2481 imm_expr
->X_op
= O_absent
;
2485 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2486 || imm_expr
->X_op
!= O_constant
2487 || imm_expr
->X_add_number
< 0
2488 || imm_expr
->X_add_number
>= 4)
2490 as_bad (_("bad value for funct2 field, "
2491 "value must be 0...3"));
2495 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2496 imm_expr
->X_op
= O_absent
;
2501 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2506 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2507 || imm_expr
->X_op
!= O_constant
2508 || imm_expr
->X_add_number
!= 0)
2511 imm_expr
->X_op
= O_absent
;
2515 as_fatal (_("internal error: bad argument type %c"), *args
);
2520 error
= _("illegal operands");
2521 insn_with_csr
= FALSE
;
2525 /* Restore the character we might have clobbered above. */
2527 *(argsStart
- 1) = save_c
;
2533 md_assemble (char *str
)
2535 struct riscv_cl_insn insn
;
2536 expressionS imm_expr
;
2537 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2539 /* The arch and priv attributes should be set before assembling. */
2540 if (!start_assemble
)
2542 start_assemble
= TRUE
;
2544 /* Set the default_priv_spec according to the priv attributes. */
2545 if (!riscv_set_default_priv_spec (NULL
))
2549 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2553 as_bad ("%s `%s'", error
, str
);
2557 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2558 macro (&insn
, &imm_expr
, &imm_reloc
);
2560 append_insn (&insn
, &imm_expr
, imm_reloc
);
2564 md_atof (int type
, char *litP
, int *sizeP
)
2566 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2570 md_number_to_chars (char *buf
, valueT val
, int n
)
2572 number_to_chars_littleendian (buf
, val
, n
);
2575 const char *md_shortopts
= "O::g::G:";
2579 OPTION_MARCH
= OPTION_MD_BASE
,
2586 OPTION_NO_ARCH_ATTR
,
2588 OPTION_NO_CSR_CHECK
,
2594 struct option md_longopts
[] =
2596 {"march", required_argument
, NULL
, OPTION_MARCH
},
2597 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2598 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2599 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2600 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2601 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2602 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2603 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2604 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2605 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2606 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2607 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2608 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2610 {NULL
, no_argument
, NULL
, 0}
2612 size_t md_longopts_size
= sizeof (md_longopts
);
2615 FLOAT_ABI_DEFAULT
= -1,
2621 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2624 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2626 abi_xlen
= new_xlen
;
2627 float_abi
= new_float_abi
;
2632 md_parse_option (int c
, const char *arg
)
2637 /* riscv_after_parse_args will call riscv_set_arch to parse
2638 the architecture. */
2639 default_arch_with_ext
= arg
;
2643 riscv_opts
.pic
= FALSE
;
2647 riscv_opts
.pic
= TRUE
;
2651 if (strcmp (arg
, "ilp32") == 0)
2652 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2653 else if (strcmp (arg
, "ilp32e") == 0)
2654 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2655 else if (strcmp (arg
, "ilp32f") == 0)
2656 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2657 else if (strcmp (arg
, "ilp32d") == 0)
2658 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2659 else if (strcmp (arg
, "ilp32q") == 0)
2660 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2661 else if (strcmp (arg
, "lp64") == 0)
2662 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2663 else if (strcmp (arg
, "lp64f") == 0)
2664 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2665 else if (strcmp (arg
, "lp64d") == 0)
2666 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2667 else if (strcmp (arg
, "lp64q") == 0)
2668 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2674 riscv_opts
.relax
= TRUE
;
2677 case OPTION_NO_RELAX
:
2678 riscv_opts
.relax
= FALSE
;
2681 case OPTION_ARCH_ATTR
:
2682 riscv_opts
.arch_attr
= TRUE
;
2685 case OPTION_NO_ARCH_ATTR
:
2686 riscv_opts
.arch_attr
= FALSE
;
2689 case OPTION_CSR_CHECK
:
2690 riscv_opts
.csr_check
= TRUE
;
2693 case OPTION_NO_CSR_CHECK
:
2694 riscv_opts
.csr_check
= FALSE
;
2697 case OPTION_MISA_SPEC
:
2698 return riscv_set_default_isa_spec (arg
);
2700 case OPTION_MPRIV_SPEC
:
2701 return riscv_set_default_priv_spec (arg
);
2711 riscv_after_parse_args (void)
2713 /* The --with-arch is optional for now, so we have to set the xlen
2714 according to the default_arch, which is set by the --targte, first.
2715 Then, we use the xlen to set the default_arch_with_ext if the
2716 -march and --with-arch are not set. */
2719 if (strcmp (default_arch
, "riscv32") == 0)
2721 else if (strcmp (default_arch
, "riscv64") == 0)
2724 as_bad ("unknown default architecture `%s'", default_arch
);
2726 if (default_arch_with_ext
== NULL
)
2727 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2729 /* Initialize the hash table for extensions with default version. */
2730 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2732 /* If the -misa-spec isn't set, then we set the default ISA spec according
2733 to DEFAULT_RISCV_ISA_SPEC. */
2734 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2735 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2737 /* Set the architecture according to -march or or --with-arch. */
2738 riscv_set_arch (default_arch_with_ext
);
2740 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2741 riscv_set_rvc (FALSE
);
2742 if (riscv_subset_supports ("c"))
2743 riscv_set_rvc (TRUE
);
2745 /* Enable RVE if specified by the -march option. */
2746 riscv_set_rve (FALSE
);
2747 if (riscv_subset_supports ("e"))
2748 riscv_set_rve (TRUE
);
2750 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2751 according to DEFAULT_PRIV_SPEC. */
2752 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2753 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2755 /* Infer ABI from ISA if not specified on command line. */
2758 else if (abi_xlen
> xlen
)
2759 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2760 else if (abi_xlen
< xlen
)
2761 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2763 if (float_abi
== FLOAT_ABI_DEFAULT
)
2765 riscv_subset_t
*subset
;
2767 /* Assume soft-float unless D extension is present. */
2768 float_abi
= FLOAT_ABI_SOFT
;
2770 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2772 if (strcasecmp (subset
->name
, "D") == 0)
2773 float_abi
= FLOAT_ABI_DOUBLE
;
2774 if (strcasecmp (subset
->name
, "Q") == 0)
2775 float_abi
= FLOAT_ABI_QUAD
;
2780 elf_flags
|= EF_RISCV_RVE
;
2782 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2783 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2785 /* If the CIE to be produced has not been overridden on the command line,
2786 then produce version 3 by default. This allows us to use the full
2787 range of registers in a .cfi_return_column directive. */
2788 if (flag_dwarf_cie_version
== -1)
2789 flag_dwarf_cie_version
= 3;
2793 md_pcrel_from (fixS
*fixP
)
2795 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2798 /* Apply a fixup to the object file. */
2801 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2803 unsigned int subtype
;
2804 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2805 bfd_boolean relaxable
= FALSE
;
2809 /* Remember value for tc_gen_reloc. */
2810 fixP
->fx_addnumber
= *valP
;
2812 switch (fixP
->fx_r_type
)
2814 case BFD_RELOC_RISCV_HI20
:
2815 case BFD_RELOC_RISCV_LO12_I
:
2816 case BFD_RELOC_RISCV_LO12_S
:
2817 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2818 | bfd_getl32 (buf
), buf
);
2819 if (fixP
->fx_addsy
== NULL
)
2820 fixP
->fx_done
= TRUE
;
2824 case BFD_RELOC_RISCV_GOT_HI20
:
2825 case BFD_RELOC_RISCV_ADD8
:
2826 case BFD_RELOC_RISCV_ADD16
:
2827 case BFD_RELOC_RISCV_ADD32
:
2828 case BFD_RELOC_RISCV_ADD64
:
2829 case BFD_RELOC_RISCV_SUB6
:
2830 case BFD_RELOC_RISCV_SUB8
:
2831 case BFD_RELOC_RISCV_SUB16
:
2832 case BFD_RELOC_RISCV_SUB32
:
2833 case BFD_RELOC_RISCV_SUB64
:
2834 case BFD_RELOC_RISCV_RELAX
:
2837 case BFD_RELOC_RISCV_TPREL_HI20
:
2838 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2839 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2840 case BFD_RELOC_RISCV_TPREL_ADD
:
2844 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2845 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2846 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2847 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2848 if (fixP
->fx_addsy
!= NULL
)
2849 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2852 _("TLS relocation against a constant"));
2856 /* Use pc-relative relocation for FDE initial location.
2857 The symbol address in .eh_frame may be adjusted in
2858 _bfd_elf_discard_section_eh_frame, and the content of
2859 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2860 Therefore, we cannot insert a relocation whose addend symbol is
2861 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2862 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2863 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2864 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2865 && S_GET_VALUE (fixP
->fx_subsy
)
2866 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2868 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2869 fixP
->fx_subsy
= NULL
;
2876 case BFD_RELOC_RISCV_CFA
:
2877 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2879 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2880 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2881 fixP
->fx_next
->fx_subsy
= NULL
;
2882 fixP
->fx_next
->fx_offset
= 0;
2883 fixP
->fx_subsy
= NULL
;
2885 switch (fixP
->fx_r_type
)
2888 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2889 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2893 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2894 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2898 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2899 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2903 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2904 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2907 case BFD_RELOC_RISCV_CFA
:
2908 /* Load the byte to get the subtype. */
2909 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2910 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2913 case DW_CFA_advance_loc1
:
2914 fixP
->fx_where
= loc
+ 1;
2915 fixP
->fx_next
->fx_where
= loc
+ 1;
2916 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2917 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2920 case DW_CFA_advance_loc2
:
2922 fixP
->fx_next
->fx_size
= 2;
2923 fixP
->fx_where
= loc
+ 1;
2924 fixP
->fx_next
->fx_where
= loc
+ 1;
2925 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2926 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2929 case DW_CFA_advance_loc4
:
2931 fixP
->fx_next
->fx_size
= 4;
2932 fixP
->fx_where
= loc
;
2933 fixP
->fx_next
->fx_where
= loc
;
2934 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2935 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2939 if (subtype
< 0x80 && (subtype
& 0x40))
2941 /* DW_CFA_advance_loc */
2942 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2943 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2944 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2945 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2948 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2954 /* This case is unreachable. */
2961 /* If we are deleting this reloc entry, we must fill in the
2962 value now. This can happen if we have a .word which is not
2963 resolved when it appears but is later defined. */
2964 if (fixP
->fx_addsy
== NULL
)
2966 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2967 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2972 case BFD_RELOC_RISCV_JMP
:
2975 /* Fill in a tentative value to improve objdump readability. */
2976 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2977 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2978 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2982 case BFD_RELOC_12_PCREL
:
2985 /* Fill in a tentative value to improve objdump readability. */
2986 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2987 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2988 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2992 case BFD_RELOC_RISCV_RVC_BRANCH
:
2995 /* Fill in a tentative value to improve objdump readability. */
2996 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2997 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2998 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3002 case BFD_RELOC_RISCV_RVC_JUMP
:
3005 /* Fill in a tentative value to improve objdump readability. */
3006 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3007 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3008 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3012 case BFD_RELOC_RISCV_CALL
:
3013 case BFD_RELOC_RISCV_CALL_PLT
:
3017 case BFD_RELOC_RISCV_PCREL_HI20
:
3018 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3019 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3020 relaxable
= riscv_opts
.relax
;
3023 case BFD_RELOC_RISCV_ALIGN
:
3027 /* We ignore generic BFD relocations we don't know about. */
3028 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3029 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3032 if (fixP
->fx_subsy
!= NULL
)
3033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3034 _("unsupported symbol subtraction"));
3036 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3037 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3039 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3040 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3041 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3045 /* Because the value of .cfi_remember_state may changed after relaxation,
3046 we insert a fix to relocate it again in link-time. */
3049 riscv_pre_output_hook (void)
3051 const frchainS
*frch
;
3054 /* Save the current segment info. */
3056 subsegT subseg
= now_subseg
;
3058 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3059 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3063 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3065 if (frag
->fr_type
== rs_cfa
)
3068 expressionS
*symval
;
3070 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3071 exp
.X_op
= O_subtract
;
3072 exp
.X_add_symbol
= symval
->X_add_symbol
;
3073 exp
.X_add_number
= 0;
3074 exp
.X_op_symbol
= symval
->X_op_symbol
;
3076 /* We must set the segment before creating a frag after all
3077 frag chains have been chained together. */
3078 subseg_set (s
, frch
->frch_subseg
);
3080 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3081 BFD_RELOC_RISCV_CFA
);
3086 /* Restore the original segment info. */
3087 subseg_set (seg
, subseg
);
3091 /* This structure is used to hold a stack of .option values. */
3093 struct riscv_option_stack
3095 struct riscv_option_stack
*next
;
3096 struct riscv_set_options options
;
3099 static struct riscv_option_stack
*riscv_opts_stack
;
3101 /* Handle the .option pseudo-op. */
3104 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3106 char *name
= input_line_pointer
, ch
;
3108 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3109 ++input_line_pointer
;
3110 ch
= *input_line_pointer
;
3111 *input_line_pointer
= '\0';
3113 if (strcmp (name
, "rvc") == 0)
3114 riscv_set_rvc (TRUE
);
3115 else if (strcmp (name
, "norvc") == 0)
3116 riscv_set_rvc (FALSE
);
3117 else if (strcmp (name
, "pic") == 0)
3118 riscv_opts
.pic
= TRUE
;
3119 else if (strcmp (name
, "nopic") == 0)
3120 riscv_opts
.pic
= FALSE
;
3121 else if (strcmp (name
, "relax") == 0)
3122 riscv_opts
.relax
= TRUE
;
3123 else if (strcmp (name
, "norelax") == 0)
3124 riscv_opts
.relax
= FALSE
;
3125 else if (strcmp (name
, "csr-check") == 0)
3126 riscv_opts
.csr_check
= TRUE
;
3127 else if (strcmp (name
, "no-csr-check") == 0)
3128 riscv_opts
.csr_check
= FALSE
;
3129 else if (strcmp (name
, "push") == 0)
3131 struct riscv_option_stack
*s
;
3133 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3134 s
->next
= riscv_opts_stack
;
3135 s
->options
= riscv_opts
;
3136 riscv_opts_stack
= s
;
3138 else if (strcmp (name
, "pop") == 0)
3140 struct riscv_option_stack
*s
;
3142 s
= riscv_opts_stack
;
3144 as_bad (_(".option pop with no .option push"));
3147 riscv_opts
= s
->options
;
3148 riscv_opts_stack
= s
->next
;
3154 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3156 *input_line_pointer
= ch
;
3157 demand_empty_rest_of_line ();
3160 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3161 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3162 use in DWARF debug information. */
3165 s_dtprel (int bytes
)
3172 if (ex
.X_op
!= O_symbol
)
3174 as_bad (_("Unsupported use of %s"), (bytes
== 8
3177 ignore_rest_of_line ();
3180 p
= frag_more (bytes
);
3181 md_number_to_chars (p
, 0, bytes
);
3182 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3184 ? BFD_RELOC_RISCV_TLS_DTPREL64
3185 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3187 demand_empty_rest_of_line ();
3190 /* Handle the .bss pseudo-op. */
3193 s_bss (int ignore ATTRIBUTE_UNUSED
)
3195 subseg_set (bss_section
, 0);
3196 demand_empty_rest_of_line ();
3200 riscv_make_nops (char *buf
, bfd_vma bytes
)
3204 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3205 means we are not within a valid instruction sequence. It is thus safe
3206 to use a zero byte, even though that is not a valid instruction. */
3210 /* Use at most one 2-byte NOP. */
3211 if ((bytes
- i
) % 4 == 2)
3213 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
3217 /* Fill the remainder with 4-byte NOPs. */
3218 for ( ; i
< bytes
; i
+= 4)
3219 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
3222 /* Called from md_do_align. Used to create an alignment frag in a
3223 code section by emitting a worst-case NOP sequence that the linker
3224 will later relax to the correct number of NOPs. We can't compute
3225 the correct alignment now because of other linker relaxations. */
3228 riscv_frag_align_code (int n
)
3230 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3231 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3232 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3236 /* If we are moving to a smaller alignment than the instruction size, then no
3237 alignment is required. */
3238 if (bytes
<= insn_alignment
)
3241 /* When not relaxing, riscv_handle_align handles code alignment. */
3242 if (!riscv_opts
.relax
)
3245 nops
= frag_more (worst_case_bytes
);
3247 ex
.X_op
= O_constant
;
3248 ex
.X_add_number
= worst_case_bytes
;
3250 riscv_make_nops (nops
, worst_case_bytes
);
3252 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3253 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3258 /* Implement HANDLE_ALIGN. */
3261 riscv_handle_align (fragS
*fragP
)
3263 switch (fragP
->fr_type
)
3266 /* When relaxing, riscv_frag_align_code handles code alignment. */
3267 if (!riscv_opts
.relax
)
3269 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3270 - fragP
->fr_address
- fragP
->fr_fix
);
3271 /* We have 4 byte uncompressed nops. */
3272 bfd_signed_vma size
= 4;
3273 bfd_signed_vma excess
= bytes
% size
;
3274 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3279 /* Insert zeros or compressed nops to get 4 byte alignment. */
3282 riscv_make_nops (p
, excess
);
3283 fragP
->fr_fix
+= excess
;
3287 /* Insert variable number of 4 byte uncompressed nops. */
3288 riscv_make_nops (p
, size
);
3289 fragP
->fr_var
= size
;
3299 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3301 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3304 /* Translate internal representation of relocation info to BFD target
3308 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3310 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3312 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3313 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3314 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3315 reloc
->addend
= fixp
->fx_addnumber
;
3317 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3318 if (reloc
->howto
== NULL
)
3320 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3321 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3323 /* We don't have R_RISCV_8/16, but for this special case,
3324 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3328 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3329 _("cannot represent %s relocation in object file"),
3330 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3338 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3340 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3342 offsetT old_var
= fragp
->fr_var
;
3343 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3344 return fragp
->fr_var
- old_var
;
3350 /* Expand far branches to multi-instruction sequences. */
3353 md_convert_frag_branch (fragS
*fragp
)
3361 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3363 exp
.X_op
= O_symbol
;
3364 exp
.X_add_symbol
= fragp
->fr_symbol
;
3365 exp
.X_add_number
= fragp
->fr_offset
;
3367 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3369 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3371 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3375 /* Expand the RVC branch into a RISC-V one. */
3376 insn
= bfd_getl16 (buf
);
3377 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3378 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3380 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3381 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3382 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3383 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3384 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3385 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3388 bfd_putl32 (insn
, buf
);
3392 /* Invert the branch condition. Branch over the jump. */
3393 insn
= bfd_getl16 (buf
);
3394 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3395 insn
|= ENCODE_RVC_B_IMM (6);
3396 bfd_putl16 (insn
, buf
);
3401 /* Just keep the RVC branch. */
3402 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3403 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3404 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3405 2, &exp
, FALSE
, reloc
);
3414 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3417 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3419 /* Invert the branch condition. Branch over the jump. */
3420 insn
= bfd_getl32 (buf
);
3421 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3422 insn
|= ENCODE_SBTYPE_IMM (8);
3423 md_number_to_chars ((char *) buf
, insn
, 4);
3427 /* Jump to the target. */
3428 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3429 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3430 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3435 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3436 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3437 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3438 4, &exp
, FALSE
, reloc
);
3447 fixp
->fx_file
= fragp
->fr_file
;
3448 fixp
->fx_line
= fragp
->fr_line
;
3450 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3451 + fragp
->fr_fix
+ fragp
->fr_var
);
3453 fragp
->fr_fix
+= fragp
->fr_var
;
3456 /* Relax a machine dependent frag. This returns the amount by which
3457 the current size of the frag should change. */
3460 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3463 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3464 md_convert_frag_branch (fragp
);
3468 md_show_usage (FILE *stream
)
3470 fprintf (stream
, _("\
3472 -fpic generate position-independent code\n\
3473 -fno-pic don't generate position-independent code (default)\n\
3474 -march=ISA set the RISC-V architecture\n\
3475 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3476 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3477 -mabi=ABI set the RISC-V ABI\n\
3478 -mrelax enable relax (default)\n\
3479 -mno-relax disable relax\n\
3480 -march-attr generate RISC-V arch attribute\n\
3481 -mno-arch-attr don't generate RISC-V arch attribute\n\
3485 /* Standard calling conventions leave the CFA at SP on entry. */
3487 riscv_cfi_frame_initial_instructions (void)
3489 cfi_add_CFA_def_cfa_register (X_SP
);
3493 tc_riscv_regname_to_dw2regnum (char *regname
)
3497 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3500 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3503 /* CSRs are numbered 4096 -> 8191. */
3504 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3507 as_bad (_("unknown register `%s'"), regname
);
3512 riscv_elf_final_processing (void)
3514 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3517 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3518 since these directives break relaxation when used with symbol deltas. */
3521 s_riscv_leb128 (int sign
)
3524 char *save_in
= input_line_pointer
;
3527 if (exp
.X_op
!= O_constant
)
3528 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3529 demand_empty_rest_of_line ();
3531 input_line_pointer
= save_in
;
3532 return s_leb128 (sign
);
3535 /* Parse the .insn directive. */
3538 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3540 char *str
= input_line_pointer
;
3541 struct riscv_cl_insn insn
;
3542 expressionS imm_expr
;
3543 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3546 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3547 ++input_line_pointer
;
3549 save_c
= *input_line_pointer
;
3550 *input_line_pointer
= '\0';
3552 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3553 &imm_reloc
, insn_type_hash
);
3557 as_bad ("%s `%s'", error
, str
);
3561 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3562 append_insn (&insn
, &imm_expr
, imm_reloc
);
3565 *input_line_pointer
= save_c
;
3566 demand_empty_rest_of_line ();
3569 /* Update arch and priv attributes. If we don't set the corresponding ELF
3570 attributes, then try to output the default ones. */
3573 riscv_write_out_attrs (void)
3575 const char *arch_str
, *priv_str
, *p
;
3576 /* versions[0] is major, versions[1] is minor,
3577 and versions[3] is revision. */
3578 unsigned versions
[3] = {0}, number
= 0;
3581 /* Re-write arch attribute to normalize the arch string. */
3582 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3583 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3584 xfree ((void *)arch_str
);
3586 /* For the file without any instruction, we don't set the default_priv_spec
3587 according to the priv attributes since the md_assemble isn't called.
3588 Call riscv_set_default_priv_spec here for the above case, although
3589 it seems strange. */
3591 && !riscv_set_default_priv_spec (NULL
))
3594 /* If we already have set elf priv attributes, then generate them.
3595 Otherwise, don't generate them when no CSR are used. */
3599 /* Re-write priv attributes by default_priv_spec. */
3600 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3602 for (i
= 0; *p
; ++p
)
3604 if (*p
== '.' && i
< 3)
3606 versions
[i
++] = number
;
3609 else if (ISDIGIT (*p
))
3610 number
= (number
* 10) + (*p
- '0');
3613 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3617 versions
[i
] = number
;
3619 /* Set the priv attributes. */
3620 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3621 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3622 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3625 /* Add the default contents for the .riscv.attributes section. If any
3626 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3627 to update the arch and priv attributes. */
3630 riscv_set_public_attributes (void)
3632 if (riscv_opts
.arch_attr
|| explicit_attr
)
3633 riscv_write_out_attrs ();
3636 /* Called after all assembly has been done. */
3641 riscv_set_public_attributes ();
3644 /* Given a symbolic attribute NAME, return the proper integer value.
3645 Returns -1 if the attribute is not known. */
3648 riscv_convert_symbolic_attribute (const char *name
)
3657 /* When you modify this table you should
3658 also modify the list in doc/c-riscv.texi. */
3659 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3663 T(priv_spec_revision
),
3664 T(unaligned_access
),
3674 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3675 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3676 return attribute_table
[i
].tag
;
3681 /* Parse a .attribute directive. */
3684 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3686 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3688 obj_attribute
*attr
;
3690 explicit_attr
= TRUE
;
3693 case Tag_RISCV_arch
:
3695 attr
= elf_known_obj_attributes_proc (stdoutput
);
3696 if (!start_assemble
)
3697 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3699 as_fatal (_(".attribute arch must set before any instructions"));
3701 if (old_xlen
!= xlen
)
3703 /* We must re-init bfd again if xlen is changed. */
3704 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3705 bfd_find_target (riscv_target_format (), stdoutput
);
3707 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3708 as_warn (_("Could not set architecture and machine"));
3712 case Tag_RISCV_priv_spec
:
3713 case Tag_RISCV_priv_spec_minor
:
3714 case Tag_RISCV_priv_spec_revision
:
3716 as_fatal (_(".attribute priv spec must set before any instructions"));
3724 /* Pseudo-op table. */
3726 static const pseudo_typeS riscv_pseudo_table
[] =
3728 /* RISC-V-specific pseudo-ops. */
3729 {"option", s_riscv_option
, 0},
3733 {"dtprelword", s_dtprel
, 4},
3734 {"dtpreldword", s_dtprel
, 8},
3736 {"uleb128", s_riscv_leb128
, 0},
3737 {"sleb128", s_riscv_leb128
, 1},
3738 {"insn", s_riscv_insn
, 0},
3739 {"attribute", s_riscv_attribute
, 0},
3745 riscv_pop_insert (void)
3747 extern void pop_insert (const pseudo_typeS
*);
3749 pop_insert (riscv_pseudo_table
);