1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
32 #include "elf/xtensa.h"
34 /* Provide default values for new configuration settings. */
40 #define uint32 unsigned int
43 #define int32 signed int
48 Naming conventions (used somewhat inconsistently):
49 The xtensa_ functions are exported
50 The xg_ functions are internal
52 We also have a couple of different extensibility mechanisms.
53 1) The idiom replacement:
54 This is used when a line is first parsed to
55 replace an instruction pattern with another instruction
56 It is currently limited to replacements of instructions
57 with constant operands.
58 2) The xtensa-relax.c mechanism that has stronger instruction
59 replacement patterns. When an instruction's immediate field
60 does not fit the next instruction sequence is attempted.
61 In addition, "narrow" opcodes are supported this way. */
64 /* Define characters with special meanings to GAS. */
65 const char comment_chars
[] = "#";
66 const char line_comment_chars
[] = "#";
67 const char line_separator_chars
[] = ";";
68 const char EXP_CHARS
[] = "eE";
69 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
72 /* Flags to indicate whether the hardware supports the density and
73 absolute literals options. */
75 bfd_boolean density_supported
;
76 bfd_boolean absolute_literals_supported
;
78 static vliw_insn cur_vinsn
;
80 unsigned xtensa_num_pipe_stages
;
81 unsigned xtensa_fetch_width
;
83 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
85 /* Some functions are only valid in the front end. This variable
86 allows us to assert that we haven't crossed over into the
88 static bfd_boolean past_xtensa_end
= FALSE
;
90 /* Flags for properties of the last instruction in a segment. */
91 #define FLAG_IS_A0_WRITER 0x1
92 #define FLAG_IS_BAD_LOOPEND 0x2
95 /* We define a special segment names ".literal" to place literals
96 into. The .fini and .init sections are special because they
97 contain code that is moved together by the linker. We give them
98 their own special .fini.literal and .init.literal sections. */
100 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
101 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
102 #define INIT_SECTION_NAME xtensa_section_rename (".init")
103 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. If lit_prefix is set, it is
108 used to determine the literal section names; otherwise, the literal
109 sections are determined based on the current text section. The
110 lit_seg and lit4_seg fields cache these literal sections, with the
111 current_text_seg field used a tag to indicate whether the cached
114 typedef struct lit_state_struct
117 segT current_text_seg
;
122 static lit_state default_lit_sections
;
125 /* We keep a list of literal segments. The seg_list type is the node
126 for this list. The literal_head pointer is the head of the list,
127 with the literal_head_h dummy node at the start. */
129 typedef struct seg_list_struct
131 struct seg_list_struct
*next
;
135 static seg_list literal_head_h
;
136 static seg_list
*literal_head
= &literal_head_h
;
139 /* Lists of symbols. We keep a list of symbols that label the current
140 instruction, so that we can adjust the symbols when inserting alignment
141 for various instructions. We also keep a list of all the symbols on
142 literals, so that we can fix up those symbols when the literals are
143 later moved into the text sections. */
145 typedef struct sym_list_struct
147 struct sym_list_struct
*next
;
151 static sym_list
*insn_labels
= NULL
;
152 static sym_list
*free_insn_labels
= NULL
;
153 static sym_list
*saved_insn_labels
= NULL
;
155 static sym_list
*literal_syms
;
158 /* Flags to determine whether to prefer const16 or l32r
159 if both options are available. */
160 int prefer_const16
= 0;
163 /* Global flag to indicate when we are emitting literals. */
164 int generating_literals
= 0;
166 /* The following PROPERTY table definitions are copied from
167 <elf/xtensa.h> and must be kept in sync with the code there. */
169 /* Flags in the property tables to specify whether blocks of memory
170 are literals, instructions, data, or unreachable. For
171 instructions, blocks that begin loop targets and branch targets are
172 designated. Blocks that do not allow density, instruction
173 reordering or transformation are also specified. Finally, for
174 branch targets, branch target alignment priority is included.
175 Alignment of the next block is specified in the current block
176 and the size of the current block does not include any fill required
177 to align to the next block. */
179 #define XTENSA_PROP_LITERAL 0x00000001
180 #define XTENSA_PROP_INSN 0x00000002
181 #define XTENSA_PROP_DATA 0x00000004
182 #define XTENSA_PROP_UNREACHABLE 0x00000008
183 /* Instruction only properties at beginning of code. */
184 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
185 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
186 /* Instruction only properties about code. */
187 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
188 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
189 /* Historically, NO_TRANSFORM was a property of instructions,
190 but it should apply to literals under certain circumstances. */
191 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
193 /* Branch target alignment information. This transmits information
194 to the linker optimization about the priority of aligning a
195 particular block for branch target alignment: None, low priority,
196 high priority, or required. These only need to be checked in
197 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
200 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
201 case XTENSA_PROP_BT_ALIGN_NONE:
202 case XTENSA_PROP_BT_ALIGN_LOW:
203 case XTENSA_PROP_BT_ALIGN_HIGH:
204 case XTENSA_PROP_BT_ALIGN_REQUIRE:
206 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
208 /* No branch target alignment. */
209 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
210 /* Low priority branch target alignment. */
211 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
212 /* High priority branch target alignment. */
213 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
214 /* Required branch target alignment. */
215 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
217 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
218 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
219 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
222 /* Alignment is specified in the block BEFORE the one that needs
223 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
224 get the required alignment specified as a power of 2. Use
225 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
226 alignment. Be careful of side effects since the SET will evaluate
227 flags twice. Also, note that the SIZE of a block in the property
228 table does not include the alignment size, so the alignment fill
229 must be calculated to determine if two blocks are contiguous.
230 TEXT_ALIGN is not currently implemented but is a placeholder for a
231 possible future implementation. */
233 #define XTENSA_PROP_ALIGN 0x00000800
235 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
237 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
238 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
239 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
241 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
244 /* Structure for saving instruction and alignment per-fragment data
245 that will be written to the object file. This structure is
246 equivalent to the actual data that will be written out to the file
247 but is easier to use. We provide a conversion to file flags
248 in frag_flags_to_number. */
250 typedef struct frag_flags_struct frag_flags
;
252 struct frag_flags_struct
254 /* is_literal should only be used after xtensa_move_literals.
255 If you need to check if you are generating a literal fragment,
256 then use the generating_literals global. */
258 unsigned is_literal
: 1;
259 unsigned is_insn
: 1;
260 unsigned is_data
: 1;
261 unsigned is_unreachable
: 1;
263 /* is_specific_opcode implies no_transform. */
264 unsigned is_no_transform
: 1;
268 unsigned is_loop_target
: 1;
269 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
270 unsigned bt_align_priority
: 2;
272 unsigned is_no_density
: 1;
273 /* no_longcalls flag does not need to be placed in the object file. */
275 unsigned is_no_reorder
: 1;
277 /* Uses absolute literal addressing for l32r. */
278 unsigned is_abslit
: 1;
280 unsigned is_align
: 1;
281 unsigned alignment
: 5;
285 /* Structure for saving information about a block of property data
286 for frags that have the same flags. */
287 struct xtensa_block_info_struct
293 struct xtensa_block_info_struct
*next
;
297 /* Structure for saving the current state before emitting literals. */
298 typedef struct emit_state_struct
303 int generating_literals
;
307 /* Opcode placement information */
309 typedef unsigned long long bitfield
;
310 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
311 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
312 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
314 #define MAX_FORMATS 32
316 typedef struct op_placement_info_struct
319 /* A number describing how restrictive the issue is for this
320 opcode. For example, an opcode that fits lots of different
321 formats has a high freedom, as does an opcode that fits
322 only one format but many slots in that format. The most
323 restrictive is the opcode that fits only one slot in one
326 xtensa_format narrowest
;
330 /* formats is a bitfield with the Nth bit set
331 if the opcode fits in the Nth xtensa_format. */
334 /* slots[N]'s Mth bit is set if the op fits in the
335 Mth slot of the Nth xtensa_format. */
336 bitfield slots
[MAX_FORMATS
];
338 /* A count of the number of slots in a given format
339 an op can fit (i.e., the bitcount of the slot field above). */
340 char slots_in_format
[MAX_FORMATS
];
342 } op_placement_info
, *op_placement_info_table
;
344 op_placement_info_table op_placement_table
;
347 /* Extra expression types. */
349 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
350 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
351 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
352 #define O_pcrel O_md4 /* value is a PC-relative offset */
353 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
354 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
355 #define O_tlscall O_md7 /* TLS_CALL relocation */
356 #define O_tpoff O_md8 /* TPOFF relocation */
357 #define O_dtpoff O_md9 /* DTPOFF relocation */
359 struct suffix_reloc_map
363 bfd_reloc_code_real_type reloc
;
367 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
369 static struct suffix_reloc_map suffix_relocs
[] =
371 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
372 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
373 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
374 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
375 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
376 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
377 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
378 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
379 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
393 directive_literal_prefix
,
395 directive_absolute_literals
,
396 directive_last_directive
402 bfd_boolean can_be_negated
;
405 const directive_infoS directive_info
[] =
408 { "literal", FALSE
},
410 { "transform", TRUE
},
411 { "freeregs", FALSE
},
412 { "longcalls", TRUE
},
413 { "literal_prefix", FALSE
},
414 { "schedule", TRUE
},
415 { "absolute-literals", TRUE
}
418 bfd_boolean directive_state
[] =
423 TRUE
, /* transform */
424 FALSE
, /* freeregs */
425 FALSE
, /* longcalls */
426 FALSE
, /* literal_prefix */
427 FALSE
, /* schedule */
428 FALSE
/* absolute_literals */
431 /* A circular list of all potential and actual literal pool locations
435 struct litpool_frag
*next
;
436 struct litpool_frag
*prev
;
439 short priority
; /* 1, 2, or 3 -- 1 is highest */
440 short original_priority
;
443 /* Map a segment to its litpool_frag list. */
446 struct litpool_seg
*next
;
448 struct litpool_frag frag_list
;
449 int frag_count
; /* since last litpool location */
452 static struct litpool_seg litpool_seg_list
;
455 /* Directive functions. */
457 static void xtensa_begin_directive (int);
458 static void xtensa_end_directive (int);
459 static void xtensa_literal_prefix (void);
460 static void xtensa_literal_position (int);
461 static void xtensa_literal_pseudo (int);
462 static void xtensa_frequency_pseudo (int);
463 static void xtensa_elf_cons (int);
464 static void xtensa_leb128 (int);
466 /* Parsing and Idiom Translation. */
468 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
470 /* Various Other Internal Functions. */
472 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
473 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
474 static void xtensa_mark_literal_pool_location (void);
475 static addressT
get_expanded_loop_offset (xtensa_opcode
);
476 static fragS
*get_literal_pool_location (segT
);
477 static void set_literal_pool_location (segT
, fragS
*);
478 static void xtensa_set_frag_assembly_state (fragS
*);
479 static void finish_vinsn (vliw_insn
*);
480 static bfd_boolean
emit_single_op (TInsn
*);
481 static int total_frag_text_expansion (fragS
*);
482 static bfd_boolean use_trampolines
= TRUE
;
483 static void xtensa_check_frag_count (void);
484 static void xtensa_create_trampoline_frag (bfd_boolean
);
485 static void xtensa_maybe_create_trampoline_frag (void);
486 struct trampoline_frag
;
487 static int init_trampoline_frag (struct trampoline_frag
*);
488 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean
, bfd_boolean
);
489 static bfd_boolean auto_litpools
= FALSE
;
490 static int auto_litpool_limit
= 10000;
492 /* Alignment Functions. */
494 static int get_text_align_power (unsigned);
495 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
496 static int branch_align_power (segT
);
498 /* Helpers for xtensa_relax_frag(). */
500 static long relax_frag_add_nop (fragS
*);
502 /* Accessors for additional per-subsegment information. */
504 static unsigned get_last_insn_flags (segT
, subsegT
);
505 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
506 static float get_subseg_total_freq (segT
, subsegT
);
507 static float get_subseg_target_freq (segT
, subsegT
);
508 static void set_subseg_freq (segT
, subsegT
, float, float);
510 /* Segment list functions. */
512 static void xtensa_move_literals (void);
513 static void xtensa_reorder_segments (void);
514 static void xtensa_switch_to_literal_fragment (emit_state
*);
515 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
516 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
517 static void xtensa_restore_emit_state (emit_state
*);
518 static segT
cache_literal_section (bfd_boolean
);
520 /* op_placement_info functions. */
522 static void init_op_placement_info_table (void);
523 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
524 static int xg_get_single_size (xtensa_opcode
);
525 static xtensa_format
xg_get_single_format (xtensa_opcode
);
526 static int xg_get_single_slot (xtensa_opcode
);
528 /* TInsn and IStack functions. */
530 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
531 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
532 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
533 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
534 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
535 static void tinsn_from_chars (TInsn
*, char *, int);
536 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
537 static int get_num_stack_text_bytes (IStack
*);
538 static int get_num_stack_literal_bytes (IStack
*);
539 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
541 /* vliw_insn functions. */
543 static void xg_init_vinsn (vliw_insn
*);
544 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
545 static void xg_clear_vinsn (vliw_insn
*);
546 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
547 static void xg_free_vinsn (vliw_insn
*);
548 static bfd_boolean vinsn_to_insnbuf
549 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
550 static void vinsn_from_chars (vliw_insn
*, char *);
552 /* Expression Utilities. */
554 bfd_boolean
expr_is_const (const expressionS
*);
555 offsetT
get_expr_const (const expressionS
*);
556 void set_expr_const (expressionS
*, offsetT
);
557 bfd_boolean
expr_is_register (const expressionS
*);
558 offsetT
get_expr_register (const expressionS
*);
559 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
560 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
561 static void copy_expr (expressionS
*, const expressionS
*);
563 /* Section renaming. */
565 static void build_section_rename (const char *);
568 /* ISA imported from bfd. */
569 extern xtensa_isa xtensa_default_isa
;
571 extern int target_big_endian
;
573 static xtensa_opcode xtensa_addi_opcode
;
574 static xtensa_opcode xtensa_addmi_opcode
;
575 static xtensa_opcode xtensa_call0_opcode
;
576 static xtensa_opcode xtensa_call4_opcode
;
577 static xtensa_opcode xtensa_call8_opcode
;
578 static xtensa_opcode xtensa_call12_opcode
;
579 static xtensa_opcode xtensa_callx0_opcode
;
580 static xtensa_opcode xtensa_callx4_opcode
;
581 static xtensa_opcode xtensa_callx8_opcode
;
582 static xtensa_opcode xtensa_callx12_opcode
;
583 static xtensa_opcode xtensa_const16_opcode
;
584 static xtensa_opcode xtensa_entry_opcode
;
585 static xtensa_opcode xtensa_extui_opcode
;
586 static xtensa_opcode xtensa_movi_opcode
;
587 static xtensa_opcode xtensa_movi_n_opcode
;
588 static xtensa_opcode xtensa_isync_opcode
;
589 static xtensa_opcode xtensa_j_opcode
;
590 static xtensa_opcode xtensa_jx_opcode
;
591 static xtensa_opcode xtensa_l32r_opcode
;
592 static xtensa_opcode xtensa_loop_opcode
;
593 static xtensa_opcode xtensa_loopnez_opcode
;
594 static xtensa_opcode xtensa_loopgtz_opcode
;
595 static xtensa_opcode xtensa_nop_opcode
;
596 static xtensa_opcode xtensa_nop_n_opcode
;
597 static xtensa_opcode xtensa_or_opcode
;
598 static xtensa_opcode xtensa_ret_opcode
;
599 static xtensa_opcode xtensa_ret_n_opcode
;
600 static xtensa_opcode xtensa_retw_opcode
;
601 static xtensa_opcode xtensa_retw_n_opcode
;
602 static xtensa_opcode xtensa_rsr_lcount_opcode
;
603 static xtensa_opcode xtensa_waiti_opcode
;
604 static int config_max_slots
= 0;
607 /* Command-line Options. */
609 bfd_boolean use_literal_section
= TRUE
;
610 enum flix_level produce_flix
= FLIX_ALL
;
611 static bfd_boolean align_targets
= TRUE
;
612 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
613 static bfd_boolean has_a0_b_retw
= FALSE
;
614 static bfd_boolean workaround_a0_b_retw
= FALSE
;
615 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
616 static bfd_boolean workaround_short_loop
= FALSE
;
617 static bfd_boolean maybe_has_short_loop
= FALSE
;
618 static bfd_boolean workaround_close_loop_end
= FALSE
;
619 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
620 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
622 /* When workaround_short_loops is TRUE, all loops with early exits must
623 have at least 3 instructions. workaround_all_short_loops is a modifier
624 to the workaround_short_loop flag. In addition to the
625 workaround_short_loop actions, all straightline loopgtz and loopnez
626 must have at least 3 instructions. */
628 static bfd_boolean workaround_all_short_loops
= FALSE
;
632 xtensa_setup_hw_workarounds (int earliest
, int latest
)
634 if (earliest
> latest
)
635 as_fatal (_("illegal range of target hardware versions"));
637 /* Enable all workarounds for pre-T1050.0 hardware. */
638 if (earliest
< 105000 || latest
< 105000)
640 workaround_a0_b_retw
|= TRUE
;
641 workaround_b_j_loop_end
|= TRUE
;
642 workaround_short_loop
|= TRUE
;
643 workaround_close_loop_end
|= TRUE
;
644 workaround_all_short_loops
|= TRUE
;
645 enforce_three_byte_loop_align
= TRUE
;
652 option_density
= OPTION_MD_BASE
,
656 option_no_generate_flix
,
663 option_no_link_relax
,
671 option_text_section_literals
,
672 option_no_text_section_literals
,
674 option_absolute_literals
,
675 option_no_absolute_literals
,
677 option_align_targets
,
678 option_no_align_targets
,
680 option_warn_unaligned_targets
,
685 option_workaround_a0_b_retw
,
686 option_no_workaround_a0_b_retw
,
688 option_workaround_b_j_loop_end
,
689 option_no_workaround_b_j_loop_end
,
691 option_workaround_short_loop
,
692 option_no_workaround_short_loop
,
694 option_workaround_all_short_loops
,
695 option_no_workaround_all_short_loops
,
697 option_workaround_close_loop_end
,
698 option_no_workaround_close_loop_end
,
700 option_no_workarounds
,
702 option_rename_section_name
,
705 option_prefer_const16
,
707 option_target_hardware
,
710 option_no_trampolines
,
712 option_auto_litpools
,
713 option_no_auto_litpools
,
714 option_auto_litpool_limit
,
717 const char *md_shortopts
= "";
719 struct option md_longopts
[] =
721 { "density", no_argument
, NULL
, option_density
},
722 { "no-density", no_argument
, NULL
, option_no_density
},
724 { "flix", no_argument
, NULL
, option_flix
},
725 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
726 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
728 /* Both "relax" and "generics" are deprecated and treated as equivalent
729 to the "transform" option. */
730 { "relax", no_argument
, NULL
, option_relax
},
731 { "no-relax", no_argument
, NULL
, option_no_relax
},
732 { "generics", no_argument
, NULL
, option_generics
},
733 { "no-generics", no_argument
, NULL
, option_no_generics
},
735 { "transform", no_argument
, NULL
, option_transform
},
736 { "no-transform", no_argument
, NULL
, option_no_transform
},
737 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
738 { "no-text-section-literals", no_argument
, NULL
,
739 option_no_text_section_literals
},
740 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
741 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
742 /* This option was changed from -align-target to -target-align
743 because it conflicted with the "-al" option. */
744 { "target-align", no_argument
, NULL
, option_align_targets
},
745 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
746 { "warn-unaligned-targets", no_argument
, NULL
,
747 option_warn_unaligned_targets
},
748 { "longcalls", no_argument
, NULL
, option_longcalls
},
749 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
751 { "no-workaround-a0-b-retw", no_argument
, NULL
,
752 option_no_workaround_a0_b_retw
},
753 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
755 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
756 option_no_workaround_b_j_loop_end
},
757 { "workaround-b-j-loop-end", no_argument
, NULL
,
758 option_workaround_b_j_loop_end
},
760 { "no-workaround-short-loops", no_argument
, NULL
,
761 option_no_workaround_short_loop
},
762 { "workaround-short-loops", no_argument
, NULL
,
763 option_workaround_short_loop
},
765 { "no-workaround-all-short-loops", no_argument
, NULL
,
766 option_no_workaround_all_short_loops
},
767 { "workaround-all-short-loop", no_argument
, NULL
,
768 option_workaround_all_short_loops
},
770 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
771 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
773 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
775 { "no-workaround-close-loop-end", no_argument
, NULL
,
776 option_no_workaround_close_loop_end
},
777 { "workaround-close-loop-end", no_argument
, NULL
,
778 option_workaround_close_loop_end
},
780 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
782 { "link-relax", no_argument
, NULL
, option_link_relax
},
783 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
785 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
787 { "trampolines", no_argument
, NULL
, option_trampolines
},
788 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
790 { "auto-litpools", no_argument
, NULL
, option_auto_litpools
},
791 { "no-auto-litpools", no_argument
, NULL
, option_no_auto_litpools
},
792 { "auto-litpool-limit", required_argument
, NULL
, option_auto_litpool_limit
},
794 { NULL
, no_argument
, NULL
, 0 }
797 size_t md_longopts_size
= sizeof md_longopts
;
801 md_parse_option (int c
, const char *arg
)
806 as_warn (_("--density option is ignored"));
808 case option_no_density
:
809 as_warn (_("--no-density option is ignored"));
811 case option_link_relax
:
814 case option_no_link_relax
:
818 produce_flix
= FLIX_ALL
;
820 case option_no_generate_flix
:
821 produce_flix
= FLIX_NO_GENERATE
;
824 produce_flix
= FLIX_NONE
;
826 case option_generics
:
827 as_warn (_("--generics is deprecated; use --transform instead"));
828 return md_parse_option (option_transform
, arg
);
829 case option_no_generics
:
830 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
831 return md_parse_option (option_no_transform
, arg
);
833 as_warn (_("--relax is deprecated; use --transform instead"));
834 return md_parse_option (option_transform
, arg
);
835 case option_no_relax
:
836 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
837 return md_parse_option (option_no_transform
, arg
);
838 case option_longcalls
:
839 directive_state
[directive_longcalls
] = TRUE
;
841 case option_no_longcalls
:
842 directive_state
[directive_longcalls
] = FALSE
;
844 case option_text_section_literals
:
845 use_literal_section
= FALSE
;
847 case option_no_text_section_literals
:
848 use_literal_section
= TRUE
;
850 case option_absolute_literals
:
851 if (!absolute_literals_supported
)
853 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
856 directive_state
[directive_absolute_literals
] = TRUE
;
858 case option_no_absolute_literals
:
859 directive_state
[directive_absolute_literals
] = FALSE
;
862 case option_workaround_a0_b_retw
:
863 workaround_a0_b_retw
= TRUE
;
865 case option_no_workaround_a0_b_retw
:
866 workaround_a0_b_retw
= FALSE
;
868 case option_workaround_b_j_loop_end
:
869 workaround_b_j_loop_end
= TRUE
;
871 case option_no_workaround_b_j_loop_end
:
872 workaround_b_j_loop_end
= FALSE
;
875 case option_workaround_short_loop
:
876 workaround_short_loop
= TRUE
;
878 case option_no_workaround_short_loop
:
879 workaround_short_loop
= FALSE
;
882 case option_workaround_all_short_loops
:
883 workaround_all_short_loops
= TRUE
;
885 case option_no_workaround_all_short_loops
:
886 workaround_all_short_loops
= FALSE
;
889 case option_workaround_close_loop_end
:
890 workaround_close_loop_end
= TRUE
;
892 case option_no_workaround_close_loop_end
:
893 workaround_close_loop_end
= FALSE
;
896 case option_no_workarounds
:
897 workaround_a0_b_retw
= FALSE
;
898 workaround_b_j_loop_end
= FALSE
;
899 workaround_short_loop
= FALSE
;
900 workaround_all_short_loops
= FALSE
;
901 workaround_close_loop_end
= FALSE
;
904 case option_align_targets
:
905 align_targets
= TRUE
;
907 case option_no_align_targets
:
908 align_targets
= FALSE
;
911 case option_warn_unaligned_targets
:
912 warn_unaligned_branch_targets
= TRUE
;
915 case option_rename_section_name
:
916 build_section_rename (arg
);
920 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
921 should be emitted or not. FIXME: Not implemented. */
924 case option_prefer_l32r
:
926 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
930 case option_prefer_const16
:
932 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
936 case option_target_hardware
:
938 int earliest
, latest
= 0;
940 if (*arg
== 0 || *arg
== '-')
941 as_fatal (_("invalid target hardware version"));
943 earliest
= strtol (arg
, &end
, 0);
947 else if (*end
== '-')
950 as_fatal (_("invalid target hardware version"));
951 latest
= strtol (end
, &end
, 0);
954 as_fatal (_("invalid target hardware version"));
956 xtensa_setup_hw_workarounds (earliest
, latest
);
960 case option_transform
:
961 /* This option has no affect other than to use the defaults,
962 which are already set. */
965 case option_no_transform
:
966 /* This option turns off all transformations of any kind.
967 However, because we want to preserve the state of other
968 directives, we only change its own field. Thus, before
969 you perform any transformation, always check if transform
970 is available. If you use the functions we provide for this
971 purpose, you will be ok. */
972 directive_state
[directive_transform
] = FALSE
;
975 case option_trampolines
:
976 use_trampolines
= TRUE
;
979 case option_no_trampolines
:
980 use_trampolines
= FALSE
;
983 case option_auto_litpools
:
984 auto_litpools
= TRUE
;
985 use_literal_section
= FALSE
;
988 case option_no_auto_litpools
:
989 auto_litpools
= FALSE
;
990 auto_litpool_limit
= -1;
993 case option_auto_litpool_limit
:
997 if (auto_litpool_limit
< 0)
998 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
999 if (*arg
== 0 || *arg
== '-')
1000 as_fatal (_("invalid auto-litpool-limit argument"));
1001 value
= strtol (arg
, &end
, 10);
1003 as_fatal (_("invalid auto-litpool-limit argument"));
1004 if (value
< 100 || value
> 10000)
1005 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1006 auto_litpool_limit
= value
;
1007 auto_litpools
= TRUE
;
1008 use_literal_section
= FALSE
;
1019 md_show_usage (FILE *stream
)
1023 --[no-]text-section-literals\n\
1024 [Do not] put literals in the text section\n\
1025 --[no-]absolute-literals\n\
1026 [Do not] default to use non-PC-relative literals\n\
1027 --[no-]target-align [Do not] try to align branch targets\n\
1028 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1029 --[no-]transform [Do not] transform instructions\n\
1030 --flix both allow hand-written and generate flix bundles\n\
1031 --no-generate-flix allow hand-written but do not generate\n\
1033 --no-allow-flix neither allow hand-written nor generate\n\
1035 --rename-section old=new Rename section 'old' to 'new'\n\
1036 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
1037 when jumps do not reach their targets\n\
1038 --[no-]auto-litpools [Do not] automatically create literal pools\n\
1039 --auto-litpool-limit=<value>\n\
1040 (range 100-10000) Maximum number of blocks of\n\
1041 instructions to emit between literal pool\n\
1042 locations; implies --auto-litpools flag\n", stream
);
1046 /* Functions related to the list of current label symbols. */
1049 xtensa_add_insn_label (symbolS
*sym
)
1053 if (!free_insn_labels
)
1054 l
= XNEW (sym_list
);
1057 l
= free_insn_labels
;
1058 free_insn_labels
= l
->next
;
1062 l
->next
= insn_labels
;
1068 xtensa_clear_insn_labels (void)
1072 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1080 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1084 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1086 symbolS
*lit_sym
= lit
->sym
;
1087 S_SET_VALUE (lit_sym
, new_offset
);
1088 symbol_set_frag (lit_sym
, new_frag
);
1093 /* Directive data and functions. */
1095 typedef struct state_stackS_struct
1097 directiveE directive
;
1098 bfd_boolean negated
;
1099 bfd_boolean old_state
;
1103 struct state_stackS_struct
*prev
;
1106 state_stackS
*directive_state_stack
;
1108 const pseudo_typeS md_pseudo_table
[] =
1110 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1111 { "literal_position", xtensa_literal_position
, 0 },
1112 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1113 { "long", xtensa_elf_cons
, 4 },
1114 { "word", xtensa_elf_cons
, 4 },
1115 { "4byte", xtensa_elf_cons
, 4 },
1116 { "short", xtensa_elf_cons
, 2 },
1117 { "2byte", xtensa_elf_cons
, 2 },
1118 { "sleb128", xtensa_leb128
, 1},
1119 { "uleb128", xtensa_leb128
, 0},
1120 { "begin", xtensa_begin_directive
, 0 },
1121 { "end", xtensa_end_directive
, 0 },
1122 { "literal", xtensa_literal_pseudo
, 0 },
1123 { "frequency", xtensa_frequency_pseudo
, 0 },
1129 use_transform (void)
1131 /* After md_end, you should be checking frag by frag, rather
1132 than state directives. */
1133 gas_assert (!past_xtensa_end
);
1134 return directive_state
[directive_transform
];
1139 do_align_targets (void)
1141 /* Do not use this function after md_end; just look at align_targets
1142 instead. There is no target-align directive, so alignment is either
1143 enabled for all frags or not done at all. */
1144 gas_assert (!past_xtensa_end
);
1145 return align_targets
&& use_transform ();
1150 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1154 state_stackS
*stack
= XNEW (state_stackS
);
1156 file
= as_where (&line
);
1158 stack
->directive
= directive
;
1159 stack
->negated
= negated
;
1160 stack
->old_state
= directive_state
[directive
];
1163 stack
->datum
= datum
;
1164 stack
->prev
= directive_state_stack
;
1165 directive_state_stack
= stack
;
1167 directive_state
[directive
] = !negated
;
1172 directive_pop (directiveE
*directive
,
1173 bfd_boolean
*negated
,
1178 state_stackS
*top
= directive_state_stack
;
1180 if (!directive_state_stack
)
1182 as_bad (_("unmatched .end directive"));
1183 *directive
= directive_none
;
1187 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1188 *directive
= top
->directive
;
1189 *negated
= top
->negated
;
1192 *datum
= top
->datum
;
1193 directive_state_stack
= top
->prev
;
1199 directive_balance (void)
1201 while (directive_state_stack
)
1203 directiveE directive
;
1204 bfd_boolean negated
;
1209 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1210 as_warn_where ((char *) file
, line
,
1211 _(".begin directive with no matching .end directive"));
1217 inside_directive (directiveE dir
)
1219 state_stackS
*top
= directive_state_stack
;
1221 while (top
&& top
->directive
!= dir
)
1224 return (top
!= NULL
);
1229 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1233 const char *directive_string
;
1235 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1240 input_line_pointer
+= 3;
1243 len
= strspn (input_line_pointer
,
1244 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1246 /* This code is a hack to make .begin [no-][generics|relax] exactly
1247 equivalent to .begin [no-]transform. We should remove it when
1248 we stop accepting those options. */
1250 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1252 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1253 directive_string
= "transform";
1255 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1257 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1258 directive_string
= "transform";
1261 directive_string
= input_line_pointer
;
1263 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1265 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1267 input_line_pointer
+= len
;
1268 *directive
= (directiveE
) i
;
1269 if (*negated
&& !directive_info
[i
].can_be_negated
)
1270 as_bad (_("directive %s cannot be negated"),
1271 directive_info
[i
].name
);
1276 as_bad (_("unknown directive"));
1277 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1282 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1284 directiveE directive
;
1285 bfd_boolean negated
;
1289 get_directive (&directive
, &negated
);
1290 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1292 discard_rest_of_line ();
1296 if (cur_vinsn
.inside_bundle
)
1297 as_bad (_("directives are not valid inside bundles"));
1301 case directive_literal
:
1302 if (!inside_directive (directive_literal
))
1304 /* Previous labels go with whatever follows this directive, not with
1305 the literal, so save them now. */
1306 saved_insn_labels
= insn_labels
;
1309 as_warn (_(".begin literal is deprecated; use .literal instead"));
1310 state
= XNEW (emit_state
);
1311 xtensa_switch_to_literal_fragment (state
);
1312 directive_push (directive_literal
, negated
, state
);
1315 case directive_literal_prefix
:
1316 /* Have to flush pending output because a movi relaxed to an l32r
1317 might produce a literal. */
1318 md_flush_pending_output ();
1319 /* Check to see if the current fragment is a literal
1320 fragment. If it is, then this operation is not allowed. */
1321 if (generating_literals
)
1323 as_bad (_("cannot set literal_prefix inside literal fragment"));
1327 /* Allocate the literal state for this section and push
1328 onto the directive stack. */
1329 ls
= XNEW (lit_state
);
1332 *ls
= default_lit_sections
;
1333 directive_push (directive_literal_prefix
, negated
, ls
);
1335 /* Process the new prefix. */
1336 xtensa_literal_prefix ();
1339 case directive_freeregs
:
1340 /* This information is currently unused, but we'll accept the statement
1341 and just discard the rest of the line. This won't check the syntax,
1342 but it will accept every correct freeregs directive. */
1343 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1344 directive_push (directive_freeregs
, negated
, 0);
1347 case directive_schedule
:
1348 md_flush_pending_output ();
1349 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1350 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1351 directive_push (directive_schedule
, negated
, 0);
1352 xtensa_set_frag_assembly_state (frag_now
);
1355 case directive_density
:
1356 as_warn (_(".begin [no-]density is ignored"));
1359 case directive_absolute_literals
:
1360 md_flush_pending_output ();
1361 if (!absolute_literals_supported
&& !negated
)
1363 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1366 xtensa_set_frag_assembly_state (frag_now
);
1367 directive_push (directive
, negated
, 0);
1371 md_flush_pending_output ();
1372 xtensa_set_frag_assembly_state (frag_now
);
1373 directive_push (directive
, negated
, 0);
1377 demand_empty_rest_of_line ();
1382 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1384 directiveE begin_directive
, end_directive
;
1385 bfd_boolean begin_negated
, end_negated
;
1389 emit_state
**state_ptr
;
1392 if (cur_vinsn
.inside_bundle
)
1393 as_bad (_("directives are not valid inside bundles"));
1395 get_directive (&end_directive
, &end_negated
);
1397 md_flush_pending_output ();
1399 switch ((int) end_directive
)
1401 case XTENSA_UNDEFINED
:
1402 discard_rest_of_line ();
1405 case (int) directive_density
:
1406 as_warn (_(".end [no-]density is ignored"));
1407 demand_empty_rest_of_line ();
1410 case (int) directive_absolute_literals
:
1411 if (!absolute_literals_supported
&& !end_negated
)
1413 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1414 demand_empty_rest_of_line ();
1423 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1424 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1425 (const void **) state_ptr
);
1427 if (begin_directive
!= directive_none
)
1429 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1431 as_bad (_("does not match begin %s%s at %s:%d"),
1432 begin_negated
? "no-" : "",
1433 directive_info
[begin_directive
].name
, file
, line
);
1437 switch (end_directive
)
1439 case directive_literal
:
1440 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1441 xtensa_restore_emit_state (state
);
1442 xtensa_set_frag_assembly_state (frag_now
);
1444 if (!inside_directive (directive_literal
))
1446 /* Restore the list of current labels. */
1447 xtensa_clear_insn_labels ();
1448 insn_labels
= saved_insn_labels
;
1452 case directive_literal_prefix
:
1453 /* Restore the default collection sections from saved state. */
1454 s
= (lit_state
*) state
;
1456 default_lit_sections
= *s
;
1458 /* Free the state storage. */
1459 free (s
->lit_prefix
);
1463 case directive_schedule
:
1464 case directive_freeregs
:
1468 xtensa_set_frag_assembly_state (frag_now
);
1474 demand_empty_rest_of_line ();
1478 /* Place an aligned literal fragment at the current location. */
1481 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1483 md_flush_pending_output ();
1485 if (inside_directive (directive_literal
))
1486 as_warn (_(".literal_position inside literal directive; ignoring"));
1487 xtensa_mark_literal_pool_location ();
1489 demand_empty_rest_of_line ();
1490 xtensa_clear_insn_labels ();
1494 /* Support .literal label, expr, ... */
1497 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1500 char *p
, *base_name
;
1504 if (inside_directive (directive_literal
))
1506 as_bad (_(".literal not allowed inside .begin literal region"));
1507 ignore_rest_of_line ();
1511 md_flush_pending_output ();
1513 /* Previous labels go with whatever follows this directive, not with
1514 the literal, so save them now. */
1515 saved_insn_labels
= insn_labels
;
1518 /* If we are using text-section literals, then this is the right value... */
1521 base_name
= input_line_pointer
;
1523 xtensa_switch_to_literal_fragment (&state
);
1525 /* ...but if we aren't using text-section-literals, then we
1526 need to put them in the section we just switched to. */
1527 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1530 /* FIXME, despite the previous comments, dest_seg is unused... */
1533 /* All literals are aligned to four-byte boundaries. */
1534 frag_align (2, 0, 0);
1535 record_alignment (now_seg
, 2);
1537 c
= get_symbol_name (&base_name
);
1538 /* Just after name is now '\0'. */
1539 p
= input_line_pointer
;
1541 SKIP_WHITESPACE_AFTER_NAME ();
1543 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1545 as_bad (_("expected comma or colon after symbol name; "
1546 "rest of line ignored"));
1547 ignore_rest_of_line ();
1548 xtensa_restore_emit_state (&state
);
1556 input_line_pointer
++; /* skip ',' or ':' */
1558 xtensa_elf_cons (4);
1560 xtensa_restore_emit_state (&state
);
1562 /* Restore the list of current labels. */
1563 xtensa_clear_insn_labels ();
1564 insn_labels
= saved_insn_labels
;
1569 xtensa_literal_prefix (void)
1574 /* Parse the new prefix from the input_line_pointer. */
1576 len
= strspn (input_line_pointer
,
1577 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1578 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1580 /* Get a null-terminated copy of the name. */
1581 name
= xmemdup0 (input_line_pointer
, len
);
1583 /* Skip the name in the input line. */
1584 input_line_pointer
+= len
;
1586 default_lit_sections
.lit_prefix
= name
;
1588 /* Clear cached literal sections, since the prefix has changed. */
1589 default_lit_sections
.lit_seg
= NULL
;
1590 default_lit_sections
.lit4_seg
= NULL
;
1594 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1597 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1599 float fall_through_f
, target_f
;
1601 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1602 if (fall_through_f
< 0)
1604 as_bad (_("fall through frequency must be greater than 0"));
1605 ignore_rest_of_line ();
1609 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1612 as_bad (_("branch target frequency must be greater than 0"));
1613 ignore_rest_of_line ();
1617 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1619 demand_empty_rest_of_line ();
1623 /* Like normal .long/.short/.word, except support @plt, etc.
1624 Clobbers input_line_pointer, checks end-of-line. */
1627 xtensa_elf_cons (int nbytes
)
1630 bfd_reloc_code_real_type reloc
;
1632 md_flush_pending_output ();
1634 if (cur_vinsn
.inside_bundle
)
1635 as_bad (_("directives are not valid inside bundles"));
1637 if (is_it_end_of_statement ())
1639 demand_empty_rest_of_line ();
1646 if (exp
.X_op
== O_symbol
1647 && *input_line_pointer
== '@'
1648 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1651 reloc_howto_type
*reloc_howto
=
1652 bfd_reloc_type_lookup (stdoutput
, reloc
);
1654 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1655 as_bad (_("unsupported relocation"));
1656 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1657 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1658 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1659 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1660 as_bad (_("opcode-specific %s relocation used outside "
1661 "an instruction"), reloc_howto
->name
);
1662 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1663 as_bad (ngettext ("%s relocations do not fit in %d byte",
1664 "%s relocations do not fit in %d bytes",
1666 reloc_howto
->name
, nbytes
);
1667 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1668 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1669 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1670 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1673 char *p
= frag_more ((int) nbytes
);
1674 xtensa_set_frag_assembly_state (frag_now
);
1675 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1676 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1681 xtensa_set_frag_assembly_state (frag_now
);
1682 emit_expr (&exp
, (unsigned int) nbytes
);
1685 while (*input_line_pointer
++ == ',');
1687 input_line_pointer
--; /* Put terminator back into stream. */
1688 demand_empty_rest_of_line ();
1691 static bfd_boolean is_leb128_expr
;
1694 xtensa_leb128 (int sign
)
1696 is_leb128_expr
= TRUE
;
1698 is_leb128_expr
= FALSE
;
1702 /* Parsing and Idiom Translation. */
1704 /* Parse @plt, etc. and return the desired relocation. */
1705 static bfd_reloc_code_real_type
1706 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1716 return BFD_RELOC_NONE
;
1718 for (ch
= *str
, str2
= ident
;
1719 (str2
< ident
+ sizeof (ident
) - 1
1720 && (ISALNUM (ch
) || ch
== '@'));
1723 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1730 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1731 if (ch
== suffix_relocs
[i
].suffix
[0]
1732 && len
== suffix_relocs
[i
].length
1733 && memcmp (ident
, suffix_relocs
[i
].suffix
, suffix_relocs
[i
].length
) == 0)
1735 /* Now check for "identifier@suffix+constant". */
1736 if (*str
== '-' || *str
== '+')
1738 char *orig_line
= input_line_pointer
;
1739 expressionS new_exp
;
1741 input_line_pointer
= str
;
1742 expression (&new_exp
);
1743 if (new_exp
.X_op
== O_constant
)
1745 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1746 str
= input_line_pointer
;
1749 if (&input_line_pointer
!= str_p
)
1750 input_line_pointer
= orig_line
;
1754 return suffix_relocs
[i
].reloc
;
1757 return BFD_RELOC_UNUSED
;
1761 /* Find the matching operator type. */
1763 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1765 operatorT
operator = O_illegal
;
1768 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1770 if (suffix_relocs
[i
].reloc
== reloc
)
1772 operator = suffix_relocs
[i
].operator;
1776 gas_assert (operator != O_illegal
);
1781 /* Find the matching reloc type. */
1782 static bfd_reloc_code_real_type
1783 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1786 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1788 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1790 if (suffix_relocs
[i
].operator == operator)
1792 reloc
= suffix_relocs
[i
].reloc
;
1799 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1800 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1801 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1802 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1805 if (reloc
== BFD_RELOC_UNUSED
)
1806 return BFD_RELOC_32
;
1813 expression_end (const char *name
)
1836 #define ERROR_REG_NUM ((unsigned) -1)
1839 tc_get_register (const char *prefix
)
1842 const char *next_expr
;
1843 const char *old_line_pointer
;
1846 old_line_pointer
= input_line_pointer
;
1848 if (*input_line_pointer
== '$')
1849 ++input_line_pointer
;
1851 /* Accept "sp" as a synonym for "a1". */
1852 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1853 && expression_end (input_line_pointer
+ 2))
1855 input_line_pointer
+= 2;
1856 return 1; /* AR[1] */
1859 while (*input_line_pointer
++ == *prefix
++)
1861 --input_line_pointer
;
1866 as_bad (_("bad register name: %s"), old_line_pointer
);
1867 return ERROR_REG_NUM
;
1870 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1872 as_bad (_("bad register number: %s"), input_line_pointer
);
1873 return ERROR_REG_NUM
;
1878 while (ISDIGIT ((int) *input_line_pointer
))
1879 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1881 if (!(next_expr
= expression_end (input_line_pointer
)))
1883 as_bad (_("bad register name: %s"), old_line_pointer
);
1884 return ERROR_REG_NUM
;
1887 input_line_pointer
= (char *) next_expr
;
1894 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1896 xtensa_isa isa
= xtensa_default_isa
;
1898 /* Check if this is an immediate operand. */
1899 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1901 bfd_reloc_code_real_type reloc
;
1902 segT t
= expression (tok
);
1904 if (t
== absolute_section
1905 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1907 gas_assert (tok
->X_op
== O_constant
);
1908 tok
->X_op
= O_symbol
;
1909 tok
->X_add_symbol
= &abs_symbol
;
1912 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1913 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1918 case BFD_RELOC_LO16
:
1919 if (tok
->X_op
== O_constant
)
1921 tok
->X_add_number
&= 0xffff;
1925 case BFD_RELOC_HI16
:
1926 if (tok
->X_op
== O_constant
)
1928 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1932 case BFD_RELOC_UNUSED
:
1933 as_bad (_("unsupported relocation"));
1935 case BFD_RELOC_32_PCREL
:
1936 as_bad (_("pcrel relocation not allowed in an instruction"));
1941 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1946 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1947 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1949 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1952 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1953 as_bad (_("register number out of range"));
1956 tok
->X_op
= O_register
;
1957 tok
->X_add_symbol
= 0;
1958 tok
->X_add_number
= reg
;
1963 /* Split up the arguments for an opcode or pseudo-op. */
1966 tokenize_arguments (char **args
, char *str
)
1968 char *old_input_line_pointer
;
1969 bfd_boolean saw_comma
= FALSE
;
1970 bfd_boolean saw_arg
= FALSE
;
1971 bfd_boolean saw_colon
= FALSE
;
1973 char *arg_end
, *arg
;
1976 /* Save and restore input_line_pointer around this function. */
1977 old_input_line_pointer
= input_line_pointer
;
1978 input_line_pointer
= str
;
1980 while (*input_line_pointer
)
1983 switch (*input_line_pointer
)
1990 input_line_pointer
++;
1991 if (saw_comma
|| saw_colon
|| !saw_arg
)
1997 input_line_pointer
++;
1998 if (saw_comma
|| saw_colon
|| !saw_arg
)
2004 if (!saw_comma
&& !saw_colon
&& saw_arg
)
2007 arg_end
= input_line_pointer
+ 1;
2008 while (!expression_end (arg_end
))
2011 arg_len
= arg_end
- input_line_pointer
;
2012 arg
= XNEWVEC (char, (saw_colon
? 1 : 0) + arg_len
+ 1);
2013 args
[num_args
] = arg
;
2017 strncpy (arg
, input_line_pointer
, arg_len
);
2018 arg
[arg_len
] = '\0';
2020 input_line_pointer
= arg_end
;
2030 if (saw_comma
|| saw_colon
)
2032 input_line_pointer
= old_input_line_pointer
;
2037 as_bad (_("extra comma"));
2039 as_bad (_("extra colon"));
2041 as_bad (_("missing argument"));
2043 as_bad (_("missing comma or colon"));
2044 input_line_pointer
= old_input_line_pointer
;
2049 /* Parse the arguments to an opcode. Return TRUE on error. */
2052 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2054 expressionS
*tok
, *last_tok
;
2055 xtensa_opcode opcode
= insn
->opcode
;
2056 bfd_boolean had_error
= TRUE
;
2057 xtensa_isa isa
= xtensa_default_isa
;
2058 int n
, num_regs
= 0;
2059 int opcode_operand_count
;
2060 int opnd_cnt
, last_opnd_cnt
;
2061 unsigned int next_reg
= 0;
2062 char *old_input_line_pointer
;
2064 if (insn
->insn_type
== ITYPE_LITERAL
)
2065 opcode_operand_count
= 1;
2067 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2070 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2072 /* Save and restore input_line_pointer around this function. */
2073 old_input_line_pointer
= input_line_pointer
;
2079 /* Skip invisible operands. */
2080 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2086 for (n
= 0; n
< num_args
; n
++)
2088 input_line_pointer
= arg_strings
[n
];
2089 if (*input_line_pointer
== ':')
2091 xtensa_regfile opnd_rf
;
2092 input_line_pointer
++;
2095 gas_assert (opnd_cnt
> 0);
2097 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2099 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2100 as_warn (_("incorrect register number, ignoring"));
2105 if (opnd_cnt
>= opcode_operand_count
)
2107 as_warn (_("too many arguments"));
2110 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2112 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2113 next_reg
= tok
->X_add_number
+ 1;
2115 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2117 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2119 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2120 /* minus 1 because we are seeing one right now */
2126 last_opnd_cnt
= opnd_cnt
;
2127 demand_empty_rest_of_line ();
2134 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2138 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2141 insn
->ntok
= tok
- insn
->tok
;
2145 input_line_pointer
= old_input_line_pointer
;
2151 get_invisible_operands (TInsn
*insn
)
2153 xtensa_isa isa
= xtensa_default_isa
;
2154 static xtensa_insnbuf slotbuf
= NULL
;
2156 xtensa_opcode opc
= insn
->opcode
;
2157 int slot
, opnd
, fmt_found
;
2161 slotbuf
= xtensa_insnbuf_alloc (isa
);
2163 /* Find format/slot where this can be encoded. */
2166 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2168 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2170 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2176 if (fmt_found
) break;
2181 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2185 /* First encode all the visible operands
2186 (to deal with shared field operands). */
2187 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2189 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2190 && (insn
->tok
[opnd
].X_op
== O_register
2191 || insn
->tok
[opnd
].X_op
== O_constant
))
2193 val
= insn
->tok
[opnd
].X_add_number
;
2194 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2195 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2199 /* Then pull out the values for the invisible ones. */
2200 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2202 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2204 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2205 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2206 insn
->tok
[opnd
].X_add_number
= val
;
2207 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2208 insn
->tok
[opnd
].X_op
= O_register
;
2210 insn
->tok
[opnd
].X_op
= O_constant
;
2219 xg_reverse_shift_count (char **cnt_argp
)
2221 char *cnt_arg
, *new_arg
;
2222 cnt_arg
= *cnt_argp
;
2224 /* replace the argument with "31-(argument)" */
2225 new_arg
= concat ("31-(", cnt_arg
, ")", (char *) NULL
);
2228 *cnt_argp
= new_arg
;
2232 /* If "arg" is a constant expression, return non-zero with the value
2236 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2239 char *save_ptr
= input_line_pointer
;
2241 input_line_pointer
= arg
;
2243 input_line_pointer
= save_ptr
;
2245 if (exp
.X_op
== O_constant
)
2247 *valp
= exp
.X_add_number
;
2256 xg_replace_opname (char **popname
, const char *newop
)
2259 *popname
= xstrdup (newop
);
2264 xg_check_num_args (int *pnum_args
,
2269 int num_args
= *pnum_args
;
2271 if (num_args
< expected_num
)
2273 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2274 num_args
, opname
, expected_num
);
2278 if (num_args
> expected_num
)
2280 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2281 num_args
, opname
, expected_num
);
2282 while (num_args
-- > expected_num
)
2284 free (arg_strings
[num_args
]);
2285 arg_strings
[num_args
] = 0;
2287 *pnum_args
= expected_num
;
2295 /* If the register is not specified as part of the opcode,
2296 then get it from the operand and move it to the opcode. */
2299 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2301 xtensa_isa isa
= xtensa_default_isa
;
2303 char *opname
, *new_opname
;
2304 const char *sr_name
;
2305 int is_user
, is_write
;
2310 is_user
= (opname
[1] == 'u');
2311 is_write
= (opname
[0] == 'w');
2313 /* Opname == [rw]ur or [rwx]sr... */
2315 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2318 /* Check if the argument is a symbolic register name. */
2319 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2320 /* Handle WSR to "INTSET" as a special case. */
2321 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2322 && !strcasecmp (arg_strings
[1], "intset"))
2323 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2324 if (sr
== XTENSA_UNDEFINED
2325 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2327 /* Maybe it's a register number.... */
2329 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2331 as_bad (_("invalid register '%s' for '%s' instruction"),
2332 arg_strings
[1], opname
);
2335 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2336 if (sr
== XTENSA_UNDEFINED
)
2338 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2339 (long) val
, opname
);
2344 /* Remove the last argument, which is now part of the opcode. */
2345 free (arg_strings
[1]);
2349 /* Translate the opcode. */
2350 sr_name
= xtensa_sysreg_name (isa
, sr
);
2351 /* Another special case for "WSR.INTSET".... */
2352 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2354 new_opname
= concat (*popname
, ".", sr_name
, (char *) NULL
);
2356 *popname
= new_opname
;
2363 xtensa_translate_old_userreg_ops (char **popname
)
2365 xtensa_isa isa
= xtensa_default_isa
;
2367 char *opname
, *new_opname
;
2368 const char *sr_name
;
2369 bfd_boolean has_underbar
= FALSE
;
2372 if (opname
[0] == '_')
2374 has_underbar
= TRUE
;
2378 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2379 if (sr
!= XTENSA_UNDEFINED
)
2381 /* The new default name ("nnn") is different from the old default
2382 name ("URnnn"). The old default is handled below, and we don't
2383 want to recognize [RW]nnn, so do nothing if the name is the (new)
2385 static char namebuf
[10];
2386 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2387 if (strcmp (namebuf
, opname
+ 1) == 0)
2395 /* Only continue if the reg name is "URnnn". */
2396 if (opname
[1] != 'u' || opname
[2] != 'r')
2398 val
= strtoul (opname
+ 3, &end
, 10);
2402 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2403 if (sr
== XTENSA_UNDEFINED
)
2405 as_bad (_("invalid register number (%ld) for '%s'"),
2406 (long) val
, opname
);
2411 /* Translate the opcode. */
2412 sr_name
= xtensa_sysreg_name (isa
, sr
);
2413 new_opname
= XNEWVEC (char, strlen (sr_name
) + 6);
2414 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2415 opname
[0], sr_name
);
2417 *popname
= new_opname
;
2424 xtensa_translate_zero_immed (const char *old_op
,
2434 gas_assert (opname
[0] != '_');
2436 if (strcmp (opname
, old_op
) != 0)
2439 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2441 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2443 xg_replace_opname (popname
, new_op
);
2444 free (arg_strings
[1]);
2445 arg_strings
[1] = arg_strings
[2];
2454 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2455 Returns non-zero if an error was found. */
2458 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2460 char *opname
= *popname
;
2461 bfd_boolean has_underbar
= FALSE
;
2465 has_underbar
= TRUE
;
2469 if (strcmp (opname
, "mov") == 0)
2471 if (use_transform () && !has_underbar
&& density_supported
)
2472 xg_replace_opname (popname
, "mov.n");
2475 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2477 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2478 arg_strings
[2] = xstrdup (arg_strings
[1]);
2484 if (strcmp (opname
, "bbsi.l") == 0)
2486 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2488 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2489 if (target_big_endian
)
2490 xg_reverse_shift_count (&arg_strings
[1]);
2494 if (strcmp (opname
, "bbci.l") == 0)
2496 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2498 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2499 if (target_big_endian
)
2500 xg_reverse_shift_count (&arg_strings
[1]);
2504 /* Don't do anything special with NOPs inside FLIX instructions. They
2505 are handled elsewhere. Real NOP instructions are always available
2506 in configurations with FLIX, so this should never be an issue but
2507 check for it anyway. */
2508 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2509 && strcmp (opname
, "nop") == 0)
2511 if (use_transform () && !has_underbar
&& density_supported
)
2512 xg_replace_opname (popname
, "nop.n");
2515 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2517 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2518 arg_strings
[0] = xstrdup ("a1");
2519 arg_strings
[1] = xstrdup ("a1");
2520 arg_strings
[2] = xstrdup ("a1");
2526 /* Recognize [RW]UR and [RWX]SR. */
2527 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2528 && (opname
[1] == 'u' || opname
[1] == 's'))
2529 || (opname
[0] == 'x' && opname
[1] == 's'))
2531 && opname
[3] == '\0')
2532 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2534 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2535 [RW]<name> if <name> is the non-default name of a user register. */
2536 if ((opname
[0] == 'r' || opname
[0] == 'w')
2537 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2538 return xtensa_translate_old_userreg_ops (popname
);
2540 /* Relax branches that don't allow comparisons against an immediate value
2541 of zero to the corresponding branches with implicit zero immediates. */
2542 if (!has_underbar
&& use_transform ())
2544 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2545 pnum_args
, arg_strings
))
2548 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2549 pnum_args
, arg_strings
))
2552 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2553 pnum_args
, arg_strings
))
2556 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2557 pnum_args
, arg_strings
))
2565 /* Functions for dealing with the Xtensa ISA. */
2567 /* Currently the assembler only allows us to use a single target per
2568 fragment. Because of this, only one operand for a given
2569 instruction may be symbolic. If there is a PC-relative operand,
2570 the last one is chosen. Otherwise, the result is the number of the
2571 last immediate operand, and if there are none of those, we fail and
2575 get_relaxable_immed (xtensa_opcode opcode
)
2577 int last_immed
= -1;
2580 if (opcode
== XTENSA_UNDEFINED
)
2583 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2584 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2586 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2588 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2590 if (last_immed
== -1
2591 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2598 static xtensa_opcode
2599 get_opcode_from_buf (const char *buf
, int slot
)
2601 static xtensa_insnbuf insnbuf
= NULL
;
2602 static xtensa_insnbuf slotbuf
= NULL
;
2603 xtensa_isa isa
= xtensa_default_isa
;
2608 insnbuf
= xtensa_insnbuf_alloc (isa
);
2609 slotbuf
= xtensa_insnbuf_alloc (isa
);
2612 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2613 fmt
= xtensa_format_decode (isa
, insnbuf
);
2614 if (fmt
== XTENSA_UNDEFINED
)
2615 return XTENSA_UNDEFINED
;
2617 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2618 return XTENSA_UNDEFINED
;
2620 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2621 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2625 #ifdef TENSILICA_DEBUG
2627 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2630 xtensa_print_insn_table (void)
2632 int num_opcodes
, num_operands
;
2633 xtensa_opcode opcode
;
2634 xtensa_isa isa
= xtensa_default_isa
;
2636 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2637 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2640 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2641 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2642 for (opn
= 0; opn
< num_operands
; opn
++)
2644 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2646 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2648 xtensa_regfile opnd_rf
=
2649 xtensa_operand_regfile (isa
, opcode
, opn
);
2650 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2652 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2653 fputs ("[lLr] ", stderr
);
2655 fputs ("i ", stderr
);
2657 fprintf (stderr
, "\n");
2663 print_vliw_insn (xtensa_insnbuf vbuf
)
2665 xtensa_isa isa
= xtensa_default_isa
;
2666 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2667 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2670 fprintf (stderr
, "format = %d\n", f
);
2672 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2674 xtensa_opcode opcode
;
2678 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2679 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2680 opname
= xtensa_opcode_name (isa
, opcode
);
2682 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2683 fprintf (stderr
, " operands = ");
2685 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2689 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2691 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2692 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2693 fprintf (stderr
, "%d ", val
);
2695 fprintf (stderr
, "\n");
2697 xtensa_insnbuf_free (isa
, sbuf
);
2700 #endif /* TENSILICA_DEBUG */
2704 is_direct_call_opcode (xtensa_opcode opcode
)
2706 xtensa_isa isa
= xtensa_default_isa
;
2707 int n
, num_operands
;
2709 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2712 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2713 for (n
= 0; n
< num_operands
; n
++)
2715 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2716 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2723 /* Convert from BFD relocation type code to slot and operand number.
2724 Returns non-zero on failure. */
2727 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2729 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2730 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2732 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2735 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2736 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2738 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2748 /* Convert from slot number to BFD relocation type code for the
2749 standard PC-relative relocations. Return BFD_RELOC_NONE on
2752 static bfd_reloc_code_real_type
2753 encode_reloc (int slot
)
2755 if (slot
< 0 || slot
> 14)
2756 return BFD_RELOC_NONE
;
2758 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2762 /* Convert from slot numbers to BFD relocation type code for the
2763 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2765 static bfd_reloc_code_real_type
2766 encode_alt_reloc (int slot
)
2768 if (slot
< 0 || slot
> 14)
2769 return BFD_RELOC_NONE
;
2771 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2776 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2779 xtensa_opcode opcode
,
2785 uint32 valbuf
= value
;
2787 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2789 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2791 as_bad_where ((char *) file
, line
,
2792 _("operand %d of '%s' has out of range value '%u'"),
2794 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2797 as_bad_where ((char *) file
, line
,
2798 _("operand %d of '%s' has invalid value '%u'"),
2800 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2805 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2811 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2814 xtensa_opcode opcode
,
2818 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2819 fmt
, slot
, slotbuf
, &val
);
2820 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2825 /* Checks for rules from xtensa-relax tables. */
2827 /* The routine xg_instruction_matches_option_term must return TRUE
2828 when a given option term is true. The meaning of all of the option
2829 terms is given interpretation by this function. */
2832 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2834 if (strcmp (option
->option_name
, "realnop") == 0
2835 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2837 /* These conditions were evaluated statically when building the
2838 relaxation table. There's no need to reevaluate them now. */
2841 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2842 return insn
->extra_arg
.X_op
== O_register
;
2845 as_fatal (_("internal error: unknown option name '%s'"),
2846 option
->option_name
);
2852 xg_instruction_matches_or_options (TInsn
*insn
,
2853 const ReqOrOptionList
*or_option
)
2855 const ReqOrOption
*option
;
2856 /* Must match each of the AND terms. */
2857 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2859 if (xg_instruction_matches_option_term (insn
, option
))
2867 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2869 const ReqOption
*req_options
;
2870 /* Must match each of the AND terms. */
2871 for (req_options
= options
;
2872 req_options
!= NULL
;
2873 req_options
= req_options
->next
)
2875 /* Must match one of the OR clauses. */
2876 if (!xg_instruction_matches_or_options (insn
,
2877 req_options
->or_option_terms
))
2884 /* Return the transition rule that matches or NULL if none matches. */
2887 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2889 PreconditionList
*condition_l
;
2891 if (rule
->opcode
!= insn
->opcode
)
2894 for (condition_l
= rule
->conditions
;
2895 condition_l
!= NULL
;
2896 condition_l
= condition_l
->next
)
2900 Precondition
*cond
= condition_l
->precond
;
2905 /* The expression must be the constant. */
2906 gas_assert (cond
->op_num
< insn
->ntok
);
2907 exp1
= &insn
->tok
[cond
->op_num
];
2908 if (expr_is_const (exp1
))
2913 if (get_expr_const (exp1
) != cond
->op_data
)
2917 if (get_expr_const (exp1
) == cond
->op_data
)
2924 else if (expr_is_register (exp1
))
2929 if (get_expr_register (exp1
) != cond
->op_data
)
2933 if (get_expr_register (exp1
) == cond
->op_data
)
2945 gas_assert (cond
->op_num
< insn
->ntok
);
2946 gas_assert (cond
->op_data
< insn
->ntok
);
2947 exp1
= &insn
->tok
[cond
->op_num
];
2948 exp2
= &insn
->tok
[cond
->op_data
];
2953 if (!expr_is_equal (exp1
, exp2
))
2957 if (expr_is_equal (exp1
, exp2
))
2969 if (!xg_instruction_matches_options (insn
, rule
->options
))
2977 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2979 bfd_boolean a_greater
= FALSE
;
2980 bfd_boolean b_greater
= FALSE
;
2982 ReqOptionList
*l_a
= a
->options
;
2983 ReqOptionList
*l_b
= b
->options
;
2985 /* We only care if they both are the same except for
2986 a const16 vs. an l32r. */
2988 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2990 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2991 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2992 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2994 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2996 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2998 /* This is the case we care about. */
2999 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
3000 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
3007 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
3008 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
3018 l_or_a
= l_or_a
->next
;
3019 l_or_b
= l_or_b
->next
;
3021 if (l_or_a
|| l_or_b
)
3030 /* Incomparable if the substitution was used differently in two cases. */
3031 if (a_greater
&& b_greater
)
3043 static TransitionRule
*
3044 xg_instruction_match (TInsn
*insn
)
3046 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3048 gas_assert (insn
->opcode
< table
->num_opcodes
);
3050 /* Walk through all of the possible transitions. */
3051 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3053 TransitionRule
*rule
= l
->rule
;
3054 if (xg_instruction_matches_rule (insn
, rule
))
3061 /* Various Other Internal Functions. */
3064 is_unique_insn_expansion (TransitionRule
*r
)
3066 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3068 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3074 /* Check if there is exactly one relaxation for INSN that converts it to
3075 another instruction of equal or larger size. If so, and if TARG is
3076 non-null, go ahead and generate the relaxed instruction into TARG. If
3077 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3078 instruction, i.e., ignore relaxations that convert to an instruction of
3079 equal size. In some contexts where this function is used, only
3080 a single widening is allowed and the NARROW_ONLY argument is used to
3081 exclude cases like ADDI being "widened" to an ADDMI, which may
3082 later be relaxed to an ADDMI/ADDI pair. */
3085 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3087 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3089 TransitionRule
*match
= 0;
3091 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3092 gas_assert (insn
->opcode
< table
->num_opcodes
);
3094 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3096 TransitionRule
*rule
= l
->rule
;
3098 if (xg_instruction_matches_rule (insn
, rule
)
3099 && is_unique_insn_expansion (rule
)
3100 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3101 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3112 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3117 /* Return the maximum number of bytes this opcode can expand to. */
3120 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3122 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3124 int max_size
= xg_get_single_size (opcode
);
3126 gas_assert (opcode
< table
->num_opcodes
);
3128 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3130 TransitionRule
*rule
= l
->rule
;
3131 BuildInstr
*build_list
;
3136 build_list
= rule
->to_instr
;
3137 if (is_unique_insn_expansion (rule
))
3139 gas_assert (build_list
->typ
== INSTR_INSTR
);
3140 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3143 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3145 switch (build_list
->typ
)
3148 this_size
+= xg_get_single_size (build_list
->opcode
);
3150 case INSTR_LITERAL_DEF
:
3151 case INSTR_LABEL_DEF
:
3156 if (this_size
> max_size
)
3157 max_size
= this_size
;
3163 /* Return the maximum number of literal bytes this opcode can generate. */
3166 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3168 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3172 gas_assert (opcode
< table
->num_opcodes
);
3174 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3176 TransitionRule
*rule
= l
->rule
;
3177 BuildInstr
*build_list
;
3182 build_list
= rule
->to_instr
;
3183 if (is_unique_insn_expansion (rule
))
3185 gas_assert (build_list
->typ
== INSTR_INSTR
);
3186 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3189 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3191 switch (build_list
->typ
)
3193 case INSTR_LITERAL_DEF
:
3194 /* Hard-coded 4-byte literal. */
3198 case INSTR_LABEL_DEF
:
3203 if (this_size
> max_size
)
3204 max_size
= this_size
;
3211 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3213 int steps_taken
= 0;
3214 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3217 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3218 gas_assert (insn
->opcode
< table
->num_opcodes
);
3220 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3222 TransitionRule
*rule
= l
->rule
;
3224 if (xg_instruction_matches_rule (insn
, rule
))
3226 if (steps_taken
== lateral_steps
)
3236 get_special_literal_symbol (void)
3238 static symbolS
*sym
= NULL
;
3241 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3247 get_special_label_symbol (void)
3249 static symbolS
*sym
= NULL
;
3252 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3258 xg_valid_literal_expression (const expressionS
*exp
)
3280 /* This will check to see if the value can be converted into the
3281 operand type. It will return TRUE if it does not fit. */
3284 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3286 uint32 valbuf
= value
;
3287 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3293 /* Assumes: All immeds are constants. Check that all constants fit
3294 into their immeds; return FALSE if not. */
3297 xg_immeds_fit (const TInsn
*insn
)
3299 xtensa_isa isa
= xtensa_default_isa
;
3303 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3304 for (i
= 0; i
< n
; ++i
)
3306 const expressionS
*exp
= &insn
->tok
[i
];
3308 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3315 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3320 /* The symbol should have a fixup associated with it. */
3329 /* This should only be called after we have an initial
3330 estimate of the addresses. */
3333 xg_symbolic_immeds_fit (const TInsn
*insn
,
3339 xtensa_isa isa
= xtensa_default_isa
;
3347 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3349 for (i
= 0; i
< n
; ++i
)
3351 const expressionS
*exp
= &insn
->tok
[i
];
3353 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3360 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3366 /* Check for the worst case. */
3367 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3372 /* We only allow symbols for PC-relative references.
3373 If pc_frag == 0, then we don't have frag locations yet. */
3375 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3378 /* If it is a weak symbol or a symbol in a different section,
3379 it cannot be known to fit at assembly time. */
3380 if (S_IS_WEAK (exp
->X_add_symbol
)
3381 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3383 /* For a direct call with --no-longcalls, be optimistic and
3384 assume it will be in range. If the symbol is weak and
3385 undefined, it may remain undefined at link-time, in which
3386 case it will have a zero value and almost certainly be out
3387 of range for a direct call; thus, relax for undefined weak
3388 symbols even if longcalls is not enabled. */
3389 if (is_direct_call_opcode (insn
->opcode
)
3390 && ! pc_frag
->tc_frag_data
.use_longcalls
3391 && (! S_IS_WEAK (exp
->X_add_symbol
)
3392 || S_IS_DEFINED (exp
->X_add_symbol
)))
3398 symbolP
= exp
->X_add_symbol
;
3399 sym_frag
= symbol_get_frag (symbolP
);
3400 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3401 pc
= pc_frag
->fr_address
+ pc_offset
;
3403 /* If frag has yet to be reached on this pass, assume it
3404 will move by STRETCH just as we did. If this is not so,
3405 it will be because some frag between grows, and that will
3406 force another pass. Beware zero-length frags. There
3407 should be a faster way to do this. */
3410 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3411 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3416 new_offset
= target
;
3417 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3418 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3423 /* The symbol should have a fixup associated with it. */
3432 /* Return TRUE on success. */
3435 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3441 targ
->debug_line
= insn
->debug_line
;
3442 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3447 targ
->opcode
= bi
->opcode
;
3448 targ
->insn_type
= ITYPE_INSN
;
3449 targ
->is_specific_opcode
= FALSE
;
3451 for (; op
!= NULL
; op
= op
->next
)
3453 int op_num
= op
->op_num
;
3454 int op_data
= op
->op_data
;
3456 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3458 if (targ
->ntok
<= op_num
)
3459 targ
->ntok
= op_num
+ 1;
3464 set_expr_const (&targ
->tok
[op_num
], op_data
);
3467 gas_assert (op_data
< insn
->ntok
);
3468 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3471 if (insn
->extra_arg
.X_op
!= O_register
)
3473 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3476 sym
= get_special_literal_symbol ();
3477 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3478 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3479 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3480 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3483 sym
= get_special_label_symbol ();
3484 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3486 case OP_OPERAND_HI16U
:
3487 case OP_OPERAND_LOW16U
:
3488 gas_assert (op_data
< insn
->ntok
);
3489 if (expr_is_const (&insn
->tok
[op_data
]))
3492 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3493 val
= xg_apply_userdef_op_fn (op
->typ
,
3496 targ
->tok
[op_num
].X_add_number
= val
;
3500 /* For const16 we can create relocations for these. */
3501 if (targ
->opcode
== XTENSA_UNDEFINED
3502 || (targ
->opcode
!= xtensa_const16_opcode
))
3504 gas_assert (op_data
< insn
->ntok
);
3505 /* Need to build a O_lo16 or O_hi16. */
3506 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3507 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3509 if (op
->typ
== OP_OPERAND_HI16U
)
3510 targ
->tok
[op_num
].X_op
= O_hi16
;
3511 else if (op
->typ
== OP_OPERAND_LOW16U
)
3512 targ
->tok
[op_num
].X_op
= O_lo16
;
3519 /* currently handles:
3522 OP_OPERAND_F32MINUS */
3523 if (xg_has_userdef_op_fn (op
->typ
))
3525 gas_assert (op_data
< insn
->ntok
);
3526 if (expr_is_const (&insn
->tok
[op_data
]))
3529 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3530 val
= xg_apply_userdef_op_fn (op
->typ
,
3533 targ
->tok
[op_num
].X_add_number
= val
;
3536 return FALSE
; /* We cannot use a relocation for this. */
3545 case INSTR_LITERAL_DEF
:
3547 targ
->opcode
= XTENSA_UNDEFINED
;
3548 targ
->insn_type
= ITYPE_LITERAL
;
3549 targ
->is_specific_opcode
= FALSE
;
3550 for (; op
!= NULL
; op
= op
->next
)
3552 int op_num
= op
->op_num
;
3553 int op_data
= op
->op_data
;
3554 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3556 if (targ
->ntok
<= op_num
)
3557 targ
->ntok
= op_num
+ 1;
3562 gas_assert (op_data
< insn
->ntok
);
3563 /* We can only pass resolvable literals through. */
3564 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3566 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3578 case INSTR_LABEL_DEF
:
3580 targ
->opcode
= XTENSA_UNDEFINED
;
3581 targ
->insn_type
= ITYPE_LABEL
;
3582 targ
->is_specific_opcode
= FALSE
;
3583 /* Literal with no ops is a label? */
3584 gas_assert (op
== NULL
);
3595 /* Return TRUE on success. */
3598 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3600 for (; bi
!= NULL
; bi
= bi
->next
)
3602 TInsn
*next_insn
= istack_push_space (istack
);
3604 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3611 /* Return TRUE on valid expansion. */
3614 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3616 int stack_size
= istack
->ninsn
;
3617 int steps_taken
= 0;
3618 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3621 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3622 gas_assert (insn
->opcode
< table
->num_opcodes
);
3624 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3626 TransitionRule
*rule
= l
->rule
;
3628 if (xg_instruction_matches_rule (insn
, rule
))
3630 if (lateral_steps
== steps_taken
)
3634 /* This is it. Expand the rule to the stack. */
3635 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3638 /* Check to see if it fits. */
3639 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3641 TInsn
*tinsn
= &istack
->insn
[i
];
3643 if (tinsn
->insn_type
== ITYPE_INSN
3644 && !tinsn_has_symbolic_operands (tinsn
)
3645 && !xg_immeds_fit (tinsn
))
3647 istack
->ninsn
= stack_size
;
3660 /* Relax the assembly instruction at least "min_steps".
3661 Return the number of steps taken.
3663 For relaxation to correctly terminate, every relaxation chain must
3664 terminate in one of two ways:
3666 1. If the chain from one instruction to the next consists entirely of
3667 single instructions, then the chain *must* handle all possible
3668 immediates without failing. It must not ever fail because an
3669 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3670 chain is one example. L32R loads 32 bits, and there cannot be an
3671 immediate larger than 32 bits, so it satisfies this condition.
3672 Single instruction relaxation chains are as defined by
3673 xg_is_single_relaxable_instruction.
3675 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3676 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3678 Strictly speaking, in most cases you can violate condition 1 and be OK
3679 -- in particular when the last two instructions have the same single
3680 size. But nevertheless, you should guarantee the above two conditions.
3682 We could fix this so that single-instruction expansions correctly
3683 terminate when they can't handle the range, but the error messages are
3684 worse, and it actually turns out that in every case but one (18-bit wide
3685 branches), you need a multi-instruction expansion to get the full range
3686 anyway. And because 18-bit branches are handled identically to 15-bit
3687 branches, there isn't any point in changing it. */
3690 xg_assembly_relax (IStack
*istack
,
3693 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3694 offsetT pc_offset
, /* offset in fragment */
3695 int min_steps
, /* minimum conversion steps */
3696 long stretch
) /* number of bytes stretched so far */
3698 int steps_taken
= 0;
3700 /* Some of its immeds don't fit. Try to build a relaxed version.
3701 This may go through a couple of stages of single instruction
3702 transformations before we get there. */
3704 TInsn single_target
;
3706 int lateral_steps
= 0;
3707 int istack_size
= istack
->ninsn
;
3709 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3710 && steps_taken
>= min_steps
)
3712 istack_push (istack
, insn
);
3715 current_insn
= *insn
;
3717 /* Walk through all of the single instruction expansions. */
3718 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3721 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3724 if (steps_taken
>= min_steps
)
3726 istack_push (istack
, &single_target
);
3730 current_insn
= single_target
;
3733 /* Now check for a multi-instruction expansion. */
3734 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3736 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3739 if (steps_taken
>= min_steps
)
3741 istack_push (istack
, ¤t_insn
);
3746 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3748 if (steps_taken
>= min_steps
)
3752 istack
->ninsn
= istack_size
;
3755 /* It's not going to work -- use the original. */
3756 istack_push (istack
, insn
);
3762 xg_finish_frag (char *last_insn
,
3763 enum xtensa_relax_statesE frag_state
,
3764 enum xtensa_relax_statesE slot0_state
,
3766 bfd_boolean is_insn
)
3768 /* Finish off this fragment so that it has at LEAST the desired
3769 max_growth. If it doesn't fit in this fragment, close this one
3770 and start a new one. In either case, return a pointer to the
3771 beginning of the growth area. */
3775 frag_grow (max_growth
);
3776 old_frag
= frag_now
;
3778 frag_now
->fr_opcode
= last_insn
;
3780 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3782 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3783 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3785 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3786 xtensa_set_frag_assembly_state (frag_now
);
3788 /* Just to make sure that we did not split it up. */
3789 gas_assert (old_frag
->fr_next
== frag_now
);
3793 /* Return TRUE if the target frag is one of the next non-empty frags. */
3796 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3801 for (; fragP
; fragP
= fragP
->fr_next
)
3803 if (fragP
== target
)
3805 if (fragP
->fr_fix
!= 0)
3807 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3809 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3810 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3812 if (fragP
->fr_type
== rs_space
)
3820 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3822 xtensa_isa isa
= xtensa_default_isa
;
3824 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3829 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3830 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3833 for (i
= 0; i
< num_ops
; i
++)
3835 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3841 if (target_op
== -1)
3844 if (insn
->ntok
<= target_op
)
3847 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3850 sym
= insn
->tok
[target_op
].X_add_symbol
;
3854 if (insn
->tok
[target_op
].X_add_number
!= 0)
3857 target_frag
= symbol_get_frag (sym
);
3858 if (target_frag
== NULL
)
3861 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3862 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3870 xg_add_branch_and_loop_targets (TInsn
*insn
)
3872 xtensa_isa isa
= xtensa_default_isa
;
3873 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3875 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3878 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3879 && insn
->tok
[i
].X_op
== O_symbol
)
3880 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3884 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3885 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3889 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3891 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3892 && insn
->tok
[i
].X_op
== O_symbol
)
3894 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3895 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3896 if (S_IS_DEFINED (sym
))
3897 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3904 /* Return FALSE if no error. */
3907 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3912 switch (instr_spec
->typ
)
3915 new_insn
->insn_type
= ITYPE_INSN
;
3916 new_insn
->opcode
= instr_spec
->opcode
;
3918 case INSTR_LITERAL_DEF
:
3919 new_insn
->insn_type
= ITYPE_LITERAL
;
3920 new_insn
->opcode
= XTENSA_UNDEFINED
;
3922 case INSTR_LABEL_DEF
:
3925 new_insn
->is_specific_opcode
= FALSE
;
3926 new_insn
->debug_line
= old_insn
->debug_line
;
3927 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3929 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3932 const expressionS
*src_exp
;
3938 /* The expression must be the constant. */
3939 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3940 exp
= &new_insn
->tok
[b_op
->op_num
];
3941 set_expr_const (exp
, b_op
->op_data
);
3945 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3946 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3947 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3948 exp
= &new_insn
->tok
[b_op
->op_num
];
3949 copy_expr (exp
, src_exp
);
3954 as_bad (_("can't handle generation of literal/labels yet"));
3958 as_bad (_("can't handle undefined OP TYPE"));
3963 new_insn
->ntok
= num_ops
;
3968 /* Return TRUE if it was simplified. */
3971 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3973 TransitionRule
*rule
;
3974 BuildInstr
*insn_spec
;
3976 if (old_insn
->is_specific_opcode
|| !density_supported
)
3979 rule
= xg_instruction_match (old_insn
);
3983 insn_spec
= rule
->to_instr
;
3984 /* There should only be one. */
3985 gas_assert (insn_spec
!= NULL
);
3986 gas_assert (insn_spec
->next
== NULL
);
3987 if (insn_spec
->next
!= NULL
)
3990 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3996 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3997 l32i.n. (2) Check the number of operands. (3) Place the instruction
3998 tokens into the stack or relax it and place multiple
3999 instructions/literals onto the stack. Return FALSE if no error. */
4002 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
4006 bfd_boolean do_expand
;
4008 tinsn_init (&new_insn
);
4010 /* Narrow it if we can. xg_simplify_insn now does all the
4011 appropriate checking (e.g., for the density option). */
4012 if (xg_simplify_insn (orig_insn
, &new_insn
))
4013 orig_insn
= &new_insn
;
4015 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
4017 if (orig_insn
->ntok
< noperands
)
4019 as_bad (ngettext ("found %d operand for '%s': Expected %d",
4020 "found %d operands for '%s': Expected %d",
4023 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4027 if (orig_insn
->ntok
> noperands
)
4028 as_warn (ngettext ("found %d operand for '%s': Expected %d",
4029 "found %d operands for '%s': Expected %d",
4032 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4035 /* If there are not enough operands, we will assert above. If there
4036 are too many, just cut out the extras here. */
4037 orig_insn
->ntok
= noperands
;
4039 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4042 /* Special case for extui opcode which has constraints not handled
4043 by the ordinary operand encoding checks. The number of operands
4044 and related syntax issues have already been checked. */
4045 if (orig_insn
->opcode
== xtensa_extui_opcode
)
4047 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
4048 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4049 if (shiftimm
+ maskimm
> 32)
4051 as_bad (_("immediate operands sum to greater than 32"));
4056 /* If the instruction will definitely need to be relaxed, it is better
4057 to expand it now for better scheduling. Decide whether to expand
4059 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4061 /* Calls should be expanded to longcalls only in the backend relaxation
4062 so that the assembly scheduler will keep the L32R/CALLX instructions
4064 if (is_direct_call_opcode (orig_insn
->opcode
))
4067 if (tinsn_has_symbolic_operands (orig_insn
))
4069 /* The values of symbolic operands are not known yet, so only expand
4070 now if an operand is "complex" (e.g., difference of symbols) and
4071 will have to be stored as a literal regardless of the value. */
4072 if (!tinsn_has_complex_operands (orig_insn
))
4075 else if (xg_immeds_fit (orig_insn
))
4079 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4081 istack_push (istack
, orig_insn
);
4087 /* Return TRUE if the section flags are marked linkonce
4088 or the name is .gnu.linkonce.*. */
4090 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4093 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4095 flagword flags
, link_once_flags
;
4097 flags
= bfd_get_section_flags (abfd
, sec
);
4098 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4100 /* Flags might not be set yet. */
4101 if (!link_once_flags
4102 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4103 link_once_flags
= SEC_LINK_ONCE
;
4105 return (link_once_flags
!= 0);
4110 xtensa_add_literal_sym (symbolS
*sym
)
4114 l
= XNEW (sym_list
);
4116 l
->next
= literal_syms
;
4122 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4124 static int lit_num
= 0;
4125 static char name
[256];
4128 sprintf (name
, ".L_lit_sym%d", lit_num
);
4130 /* Create a local symbol. If it is in a linkonce section, we have to
4131 be careful to make sure that if it is used in a relocation that the
4132 symbol will be in the output file. */
4133 if (get_is_linkonce_section (stdoutput
, sec
))
4135 symbolP
= symbol_new (name
, sec
, 0, frag
);
4136 S_CLEAR_EXTERNAL (symbolP
);
4137 /* symbolP->local = 1; */
4140 symbolP
= symbol_new (name
, sec
, 0, frag
);
4142 xtensa_add_literal_sym (symbolP
);
4149 /* Currently all literals that are generated here are 32-bit L32R targets. */
4152 xg_assemble_literal (/* const */ TInsn
*insn
)
4155 symbolS
*lit_sym
= NULL
;
4156 bfd_reloc_code_real_type reloc
;
4157 bfd_boolean pcrel
= FALSE
;
4160 /* size = 4 for L32R. It could easily be larger when we move to
4161 larger constants. Add a parameter later. */
4162 offsetT litsize
= 4;
4163 offsetT litalign
= 2; /* 2^2 = 4 */
4164 expressionS saved_loc
;
4165 expressionS
* emit_val
;
4167 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4169 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4170 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4172 xtensa_switch_to_literal_fragment (&state
);
4174 emit_val
= &insn
->tok
[0];
4175 if (emit_val
->X_op
== O_big
)
4177 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4180 /* This happens when someone writes a "movi a2, big_number". */
4181 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4182 _("invalid immediate"));
4183 xtensa_restore_emit_state (&state
);
4188 /* Force a 4-byte align here. Note that this opens a new frag, so all
4189 literals done with this function have a frag to themselves. That's
4190 important for the way text section literals work. */
4191 frag_align (litalign
, 0, 0);
4192 record_alignment (now_seg
, litalign
);
4194 switch (emit_val
->X_op
)
4204 p
= frag_more (litsize
);
4205 xtensa_set_frag_assembly_state (frag_now
);
4206 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4207 if (emit_val
->X_add_symbol
)
4208 emit_val
->X_op
= O_symbol
;
4210 emit_val
->X_op
= O_constant
;
4211 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4212 litsize
, emit_val
, pcrel
, reloc
);
4216 emit_expr (emit_val
, litsize
);
4220 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4221 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4222 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4223 lit_sym
= frag_now
->fr_symbol
;
4226 xtensa_restore_emit_state (&state
);
4232 xg_assemble_literal_space (/* const */ int size
, int slot
)
4235 /* We might have to do something about this alignment. It only
4236 takes effect if something is placed here. */
4237 offsetT litalign
= 2; /* 2^2 = 4 */
4238 fragS
*lit_saved_frag
;
4240 gas_assert (size
% 4 == 0);
4242 xtensa_switch_to_literal_fragment (&state
);
4244 /* Force a 4-byte align here. */
4245 frag_align (litalign
, 0, 0);
4246 record_alignment (now_seg
, litalign
);
4250 lit_saved_frag
= frag_now
;
4251 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4252 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4253 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4256 xtensa_restore_emit_state (&state
);
4257 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4261 /* Put in a fixup record based on the opcode.
4262 Return TRUE on success. */
4265 xg_add_opcode_fix (TInsn
*tinsn
,
4273 xtensa_opcode opcode
= tinsn
->opcode
;
4274 bfd_reloc_code_real_type reloc
;
4275 reloc_howto_type
*howto
;
4279 reloc
= BFD_RELOC_NONE
;
4281 /* First try the special cases for "alternate" relocs. */
4282 if (opcode
== xtensa_l32r_opcode
)
4284 if (fragP
->tc_frag_data
.use_absolute_literals
)
4285 reloc
= encode_alt_reloc (slot
);
4287 else if (opcode
== xtensa_const16_opcode
)
4289 if (exp
->X_op
== O_lo16
)
4291 reloc
= encode_reloc (slot
);
4292 exp
->X_op
= O_symbol
;
4294 else if (exp
->X_op
== O_hi16
)
4296 reloc
= encode_alt_reloc (slot
);
4297 exp
->X_op
= O_symbol
;
4301 if (opnum
!= get_relaxable_immed (opcode
))
4303 as_bad (_("invalid relocation for operand %i of '%s'"),
4304 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4308 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4309 into the symbol table where the generic portions of the assembler
4310 won't know what to do with them. */
4311 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4313 as_bad (_("invalid expression for operand %i of '%s'"),
4314 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4318 /* Next try the generic relocs. */
4319 if (reloc
== BFD_RELOC_NONE
)
4320 reloc
= encode_reloc (slot
);
4321 if (reloc
== BFD_RELOC_NONE
)
4323 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4327 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4330 as_bad (_("undefined symbol for opcode \"%s\""),
4331 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4335 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4336 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4337 howto
->pc_relative
, reloc
);
4338 the_fix
->fx_no_overflow
= 1;
4339 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4340 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4341 the_fix
->tc_fix_data
.slot
= slot
;
4348 xg_emit_insn_to_buf (TInsn
*tinsn
,
4352 bfd_boolean build_fix
)
4354 static xtensa_insnbuf insnbuf
= NULL
;
4355 bfd_boolean has_symbolic_immed
= FALSE
;
4356 bfd_boolean ok
= TRUE
;
4359 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4361 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4362 if (has_symbolic_immed
&& build_fix
)
4365 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4366 int slot
= xg_get_single_slot (tinsn
->opcode
);
4367 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4368 expressionS
*exp
= &tinsn
->tok
[opnum
];
4370 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4373 fragP
->tc_frag_data
.is_insn
= TRUE
;
4374 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4375 (unsigned char *) buf
, 0);
4381 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4383 symbolS
*sym
= get_special_literal_symbol ();
4387 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4388 for (i
= 0; i
< insn
->ntok
; i
++)
4389 if (insn
->tok
[i
].X_add_symbol
== sym
)
4390 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4396 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4398 symbolS
*sym
= get_special_label_symbol ();
4400 for (i
= 0; i
< insn
->ntok
; i
++)
4401 if (insn
->tok
[i
].X_add_symbol
== sym
)
4402 insn
->tok
[i
].X_add_symbol
= label_sym
;
4407 /* Return TRUE if the instruction can write to the specified
4408 integer register. */
4411 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4415 xtensa_isa isa
= xtensa_default_isa
;
4417 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4419 for (i
= 0; i
< num_ops
; i
++)
4422 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4423 if ((inout
== 'o' || inout
== 'm')
4424 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4426 xtensa_regfile opnd_rf
=
4427 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4428 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4430 if ((insn
->tok
[i
].X_op
== O_register
)
4431 && (insn
->tok
[i
].X_add_number
== regnum
))
4441 is_bad_loopend_opcode (const TInsn
*tinsn
)
4443 xtensa_opcode opcode
= tinsn
->opcode
;
4445 if (opcode
== XTENSA_UNDEFINED
)
4448 if (opcode
== xtensa_call0_opcode
4449 || opcode
== xtensa_callx0_opcode
4450 || opcode
== xtensa_call4_opcode
4451 || opcode
== xtensa_callx4_opcode
4452 || opcode
== xtensa_call8_opcode
4453 || opcode
== xtensa_callx8_opcode
4454 || opcode
== xtensa_call12_opcode
4455 || opcode
== xtensa_callx12_opcode
4456 || opcode
== xtensa_isync_opcode
4457 || opcode
== xtensa_ret_opcode
4458 || opcode
== xtensa_ret_n_opcode
4459 || opcode
== xtensa_retw_opcode
4460 || opcode
== xtensa_retw_n_opcode
4461 || opcode
== xtensa_waiti_opcode
4462 || opcode
== xtensa_rsr_lcount_opcode
)
4469 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4470 This allows the debugger to add unaligned labels.
4471 Also, the assembler generates stabs labels that need
4472 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4475 is_unaligned_label (symbolS
*sym
)
4477 const char *name
= S_GET_NAME (sym
);
4478 static size_t fake_size
= 0;
4482 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4485 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4487 fake_size
= strlen (FAKE_LABEL_NAME
);
4490 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4491 && (name
[fake_size
] == 'F'
4492 || name
[fake_size
] == 'L'
4493 || (name
[fake_size
] == 'e'
4494 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4502 next_non_empty_frag (const fragS
*fragP
)
4504 fragS
*next_fragP
= fragP
->fr_next
;
4506 /* Sometimes an empty will end up here due storage allocation issues.
4507 So we have to skip until we find something legit. */
4508 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4509 next_fragP
= next_fragP
->fr_next
;
4511 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4519 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4521 xtensa_opcode out_opcode
;
4522 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4524 if (next_fragP
== NULL
)
4527 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4528 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4530 *opcode
= out_opcode
;
4538 frag_format_size (const fragS
*fragP
)
4540 static xtensa_insnbuf insnbuf
= NULL
;
4541 xtensa_isa isa
= xtensa_default_isa
;
4546 insnbuf
= xtensa_insnbuf_alloc (isa
);
4549 return XTENSA_UNDEFINED
;
4551 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4552 (unsigned char *) fragP
->fr_literal
, 0);
4554 fmt
= xtensa_format_decode (isa
, insnbuf
);
4555 if (fmt
== XTENSA_UNDEFINED
)
4556 return XTENSA_UNDEFINED
;
4557 fmt_size
= xtensa_format_length (isa
, fmt
);
4559 /* If the next format won't be changing due to relaxation, just
4560 return the length of the first format. */
4561 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4564 /* If during relaxation we have to pull an instruction out of a
4565 multi-slot instruction, we will return the more conservative
4566 number. This works because alignment on bigger instructions
4567 is more restrictive than alignment on smaller instructions.
4568 This is more conservative than we would like, but it happens
4571 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4574 /* If we aren't doing one of our own relaxations or it isn't
4575 slot-based, then the insn size won't change. */
4576 if (fragP
->fr_type
!= rs_machine_dependent
)
4578 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4581 /* If an instruction is about to grow, return the longer size. */
4582 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4583 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4584 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4586 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4587 instruction in the relaxed version is of length 3. (The case
4588 where we have to pull the instruction out of a FLIX bundle
4589 is handled conservatively above.) However, frags with opcodes
4590 that are expanding to wide branches end up having formats that
4591 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4592 we can't tell directly what format the relaxer picked. This
4593 is a wart in the design of the relaxer that should someday be
4594 fixed, but would require major changes, or at least should
4595 be accompanied by major changes to make use of that data.
4597 In any event, we can tell that we are expanding from a single-slot
4598 format to a wider one with the logic below. */
4601 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4603 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4605 if (relaxed_size
== xtensa_format_length (isa
, i
))
4606 return relaxed_size
;
4612 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4613 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4620 next_frag_format_size (const fragS
*fragP
)
4622 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4623 return frag_format_size (next_fragP
);
4627 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4628 required two-byte instructions to be treated as three-byte instructions
4629 for loop instruction alignment. This restriction was removed beginning
4630 with Xtensa LX. Now the only requirement on loop instruction alignment
4631 is that the first instruction of the loop must appear at an address that
4632 does not cross a fetch boundary. */
4635 get_loop_align_size (int insn_size
)
4637 if (insn_size
== XTENSA_UNDEFINED
)
4638 return xtensa_fetch_width
;
4640 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4647 /* If the next legit fragment is an end-of-loop marker,
4648 switch its state so it will instantiate a NOP. */
4651 update_next_frag_state (fragS
*fragP
)
4653 fragS
*next_fragP
= fragP
->fr_next
;
4654 fragS
*new_target
= NULL
;
4658 /* We are guaranteed there will be one of these... */
4659 while (!(next_fragP
->fr_type
== rs_machine_dependent
4660 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4661 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4662 next_fragP
= next_fragP
->fr_next
;
4664 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4665 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4666 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4668 /* ...and one of these. */
4669 new_target
= next_fragP
->fr_next
;
4670 while (!(new_target
->fr_type
== rs_machine_dependent
4671 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4672 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4673 new_target
= new_target
->fr_next
;
4675 gas_assert (new_target
->fr_type
== rs_machine_dependent
4676 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4677 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4680 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4682 if (next_fragP
->fr_type
== rs_machine_dependent
4683 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4685 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4689 next_fragP
= next_fragP
->fr_next
;
4695 next_frag_is_branch_target (const fragS
*fragP
)
4697 /* Sometimes an empty will end up here due to storage allocation issues,
4698 so we have to skip until we find something legit. */
4699 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4701 if (fragP
->tc_frag_data
.is_branch_target
)
4703 if (fragP
->fr_fix
!= 0)
4711 next_frag_is_loop_target (const fragS
*fragP
)
4713 /* Sometimes an empty will end up here due storage allocation issues.
4714 So we have to skip until we find something legit. */
4715 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4717 if (fragP
->tc_frag_data
.is_loop_target
)
4719 if (fragP
->fr_fix
!= 0)
4726 /* As specified in the relaxation table, when a loop instruction is
4727 relaxed, there are 24 bytes between the loop instruction itself and
4728 the first instruction in the loop. */
4730 #define RELAXED_LOOP_INSN_BYTES 24
4733 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4735 const fragS
*next_fragp
= fragp
->fr_next
;
4736 xtensa_opcode next_opcode
;
4738 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4741 /* Sometimes an empty will end up here due to storage allocation issues,
4742 so we have to skip until we find something legit. */
4743 while (next_fragp
->fr_fix
== 0)
4744 next_fragp
= next_fragp
->fr_next
;
4746 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4749 /* There is some implicit knowledge encoded in here.
4750 The LOOP instructions that are NOT RELAX_IMMED have
4751 been relaxed. Note that we can assume that the LOOP
4752 instruction is in slot 0 because loops aren't bundleable. */
4753 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4754 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4760 /* Mark a location where we can later insert literal frags. Update
4761 the section's literal_pool_loc, so subsequent literals can be
4762 placed nearest to their use. */
4765 xtensa_mark_literal_pool_location (void)
4767 /* Any labels pointing to the current location need
4768 to be adjusted to after the literal pool. */
4770 fragS
*pool_location
;
4772 if (use_literal_section
)
4775 /* We stash info in these frags so we can later move the literal's
4776 fixes into this frchain's fix list. */
4777 pool_location
= frag_now
;
4778 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4779 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4780 /* Just record this frag. */
4781 xtensa_maybe_create_literal_pool_frag (FALSE
, FALSE
);
4782 frag_variant (rs_machine_dependent
, 0, 0,
4783 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4784 xtensa_set_frag_assembly_state (frag_now
);
4785 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4786 frag_variant (rs_machine_dependent
, 0, 0,
4787 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4788 xtensa_set_frag_assembly_state (frag_now
);
4790 /* Now put a frag into the literal pool that points to this location. */
4791 set_literal_pool_location (now_seg
, pool_location
);
4792 xtensa_switch_to_non_abs_literal_fragment (&s
);
4793 frag_align (2, 0, 0);
4794 record_alignment (now_seg
, 2);
4796 /* Close whatever frag is there. */
4797 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4798 xtensa_set_frag_assembly_state (frag_now
);
4799 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4800 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4801 xtensa_restore_emit_state (&s
);
4802 xtensa_set_frag_assembly_state (frag_now
);
4806 /* Build a nop of the correct size into tinsn. */
4809 build_nop (TInsn
*tinsn
, int size
)
4815 tinsn
->opcode
= xtensa_nop_n_opcode
;
4817 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4818 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4822 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4824 tinsn
->opcode
= xtensa_or_opcode
;
4825 set_expr_const (&tinsn
->tok
[0], 1);
4826 set_expr_const (&tinsn
->tok
[1], 1);
4827 set_expr_const (&tinsn
->tok
[2], 1);
4831 tinsn
->opcode
= xtensa_nop_opcode
;
4833 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4838 /* Assemble a NOP of the requested size in the buffer. User must have
4839 allocated "buf" with at least "size" bytes. */
4842 assemble_nop (int size
, char *buf
)
4844 static xtensa_insnbuf insnbuf
= NULL
;
4847 build_nop (&tinsn
, size
);
4850 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4852 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4853 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4854 (unsigned char *) buf
, 0);
4858 /* Return the number of bytes for the offset of the expanded loop
4859 instruction. This should be incorporated into the relaxation
4860 specification but is hard-coded here. This is used to auto-align
4861 the loop instruction. It is invalid to call this function if the
4862 configuration does not have loops or if the opcode is not a loop
4866 get_expanded_loop_offset (xtensa_opcode opcode
)
4868 /* This is the OFFSET of the loop instruction in the expanded loop.
4869 This MUST correspond directly to the specification of the loop
4870 expansion. It will be validated on fragment conversion. */
4871 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4872 if (opcode
== xtensa_loop_opcode
)
4874 if (opcode
== xtensa_loopnez_opcode
)
4876 if (opcode
== xtensa_loopgtz_opcode
)
4878 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4884 get_literal_pool_location (segT seg
)
4886 struct litpool_seg
*lps
= litpool_seg_list
.next
;
4887 struct litpool_frag
*lpf
;
4888 for ( ; lps
&& lps
->seg
->id
!= seg
->id
; lps
= lps
->next
)
4892 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4893 { /* Skip "candidates" for now. */
4894 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
4898 /* Must convert a lower-priority pool. */
4899 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4901 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
4904 /* Still no match -- try for a low priority pool. */
4905 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4907 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
4911 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4916 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4918 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4922 /* Set frag assembly state should be called when a new frag is
4923 opened and after a frag has been closed. */
4926 xtensa_set_frag_assembly_state (fragS
*fragP
)
4928 if (!density_supported
)
4929 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4931 /* This function is called from subsegs_finish, which is called
4932 after xtensa_end, so we can't use "use_transform" or
4933 "use_schedule" here. */
4934 if (!directive_state
[directive_transform
])
4935 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4936 if (directive_state
[directive_longcalls
])
4937 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4938 fragP
->tc_frag_data
.use_absolute_literals
=
4939 directive_state
[directive_absolute_literals
];
4940 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4945 relaxable_section (asection
*sec
)
4947 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4948 && strcmp (sec
->name
, ".eh_frame") != 0);
4953 xtensa_mark_frags_for_org (void)
4957 /* Walk over each fragment of all of the current segments. If we find
4958 a .org frag in any of the segments, mark all frags prior to it as
4959 "no transform", which will prevent linker optimizations from messing
4960 up the .org distance. This should be done after
4961 xtensa_find_unmarked_state_frags, because we don't want to worry here
4962 about that function trashing the data we save here. */
4964 for (seclist
= &stdoutput
->sections
;
4965 seclist
&& *seclist
;
4966 seclist
= &(*seclist
)->next
)
4968 segT sec
= *seclist
;
4969 segment_info_type
*seginfo
;
4972 flags
= bfd_get_section_flags (stdoutput
, sec
);
4973 if (flags
& SEC_DEBUGGING
)
4975 if (!(flags
& SEC_ALLOC
))
4978 seginfo
= seg_info (sec
);
4979 if (seginfo
&& seginfo
->frchainP
)
4981 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4982 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4983 fragP
= fragP
->fr_next
)
4985 /* cvt_frag_to_fill has changed the fr_type of org frags to
4986 rs_fill, so use the value as cached in rs_subtype here. */
4987 if (fragP
->fr_subtype
== RELAX_ORG
)
4989 while (last_fragP
!= fragP
->fr_next
)
4991 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4992 last_fragP
= last_fragP
->fr_next
;
5002 xtensa_find_unmarked_state_frags (void)
5006 /* Walk over each fragment of all of the current segments. For each
5007 unmarked fragment, mark it with the same info as the previous
5009 for (seclist
= &stdoutput
->sections
;
5010 seclist
&& *seclist
;
5011 seclist
= &(*seclist
)->next
)
5013 segT sec
= *seclist
;
5014 segment_info_type
*seginfo
;
5017 flags
= bfd_get_section_flags (stdoutput
, sec
);
5018 if (flags
& SEC_DEBUGGING
)
5020 if (!(flags
& SEC_ALLOC
))
5023 seginfo
= seg_info (sec
);
5024 if (seginfo
&& seginfo
->frchainP
)
5026 fragS
*last_fragP
= 0;
5027 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5028 fragP
= fragP
->fr_next
)
5030 if (fragP
->fr_fix
!= 0
5031 && !fragP
->tc_frag_data
.is_assembly_state_set
)
5033 if (last_fragP
== 0)
5035 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5036 _("assembly state not set for first frag in section %s"),
5041 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
5042 fragP
->tc_frag_data
.is_no_density
=
5043 last_fragP
->tc_frag_data
.is_no_density
;
5044 fragP
->tc_frag_data
.is_no_transform
=
5045 last_fragP
->tc_frag_data
.is_no_transform
;
5046 fragP
->tc_frag_data
.use_longcalls
=
5047 last_fragP
->tc_frag_data
.use_longcalls
;
5048 fragP
->tc_frag_data
.use_absolute_literals
=
5049 last_fragP
->tc_frag_data
.use_absolute_literals
;
5052 if (fragP
->tc_frag_data
.is_assembly_state_set
)
5061 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
5063 void *unused ATTRIBUTE_UNUSED
)
5065 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5066 segment_info_type
*seginfo
= seg_info (sec
);
5067 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5069 if (flags
& SEC_CODE
)
5071 xtensa_isa isa
= xtensa_default_isa
;
5072 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5073 while (frag
!= NULL
)
5075 if (frag
->tc_frag_data
.is_branch_target
)
5078 addressT branch_align
, frag_addr
;
5081 xtensa_insnbuf_from_chars
5082 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5083 fmt
= xtensa_format_decode (isa
, insnbuf
);
5084 op_size
= xtensa_format_length (isa
, fmt
);
5085 branch_align
= 1 << branch_align_power (sec
);
5086 frag_addr
= frag
->fr_address
% branch_align
;
5087 if (frag_addr
+ op_size
> branch_align
)
5088 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5089 _("unaligned branch target: %d bytes at 0x%lx"),
5090 op_size
, (long) frag
->fr_address
);
5092 frag
= frag
->fr_next
;
5094 xtensa_insnbuf_free (isa
, insnbuf
);
5100 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5102 void *unused ATTRIBUTE_UNUSED
)
5104 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5105 segment_info_type
*seginfo
= seg_info (sec
);
5106 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5107 xtensa_isa isa
= xtensa_default_isa
;
5109 if (flags
& SEC_CODE
)
5111 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5112 while (frag
!= NULL
)
5114 if (frag
->tc_frag_data
.is_first_loop_insn
)
5120 if (frag
->fr_fix
== 0)
5121 frag
= next_non_empty_frag (frag
);
5125 xtensa_insnbuf_from_chars
5126 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5127 fmt
= xtensa_format_decode (isa
, insnbuf
);
5128 op_size
= xtensa_format_length (isa
, fmt
);
5129 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5131 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5132 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5133 _("unaligned loop: %d bytes at 0x%lx"),
5134 op_size
, (long) frag
->fr_address
);
5137 frag
= frag
->fr_next
;
5139 xtensa_insnbuf_free (isa
, insnbuf
);
5145 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5147 xtensa_isa isa
= xtensa_default_isa
;
5148 static xtensa_insnbuf insnbuf
= NULL
;
5149 static xtensa_insnbuf slotbuf
= NULL
;
5152 bfd_boolean alt_reloc
;
5153 xtensa_opcode opcode
;
5154 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5156 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5158 as_fatal (_("unexpected fix"));
5162 insnbuf
= xtensa_insnbuf_alloc (isa
);
5163 slotbuf
= xtensa_insnbuf_alloc (isa
);
5166 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5167 fmt
= xtensa_format_decode (isa
, insnbuf
);
5168 if (fmt
== XTENSA_UNDEFINED
)
5169 as_fatal (_("undecodable fix"));
5170 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5171 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5172 if (opcode
== XTENSA_UNDEFINED
)
5173 as_fatal (_("undecodable fix"));
5175 /* CONST16 immediates are not PC-relative, despite the fact that we
5176 reuse the normal PC-relative operand relocations for the low part
5177 of a CONST16 operand. */
5178 if (opcode
== xtensa_const16_opcode
)
5181 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5182 get_relaxable_immed (opcode
), val
,
5183 fixP
->fx_file
, fixP
->fx_line
);
5185 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5186 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5192 /* External Functions and Other GAS Hooks. */
5195 xtensa_target_format (void)
5197 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5202 xtensa_file_arch_init (bfd
*abfd
)
5204 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5209 md_number_to_chars (char *buf
, valueT val
, int n
)
5211 if (target_big_endian
)
5212 number_to_chars_bigendian (buf
, val
, n
);
5214 number_to_chars_littleendian (buf
, val
, n
);
5218 xg_init_global_config (void)
5220 target_big_endian
= XCHAL_HAVE_BE
;
5222 density_supported
= XCHAL_HAVE_DENSITY
;
5223 absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
5224 xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
5226 directive_state
[directive_density
] = XCHAL_HAVE_DENSITY
;
5227 directive_state
[directive_absolute_literals
] = XSHAL_USE_ABSOLUTE_LITERALS
;
5231 xtensa_init (int argc ATTRIBUTE_UNUSED
, char **argv ATTRIBUTE_UNUSED
)
5233 xg_init_global_config ();
5236 /* This function is called once, at assembler startup time. It should
5237 set up all the tables, etc. that the MD part of the assembler will
5243 segT current_section
= now_seg
;
5244 int current_subsec
= now_subseg
;
5248 xtensa_default_isa
= xtensa_isa_init (0, 0);
5249 isa
= xtensa_default_isa
;
5253 /* Set up the literal sections. */
5254 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5256 subseg_set (current_section
, current_subsec
);
5258 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5259 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5260 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5261 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5262 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5263 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5264 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5265 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5266 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5267 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5268 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5269 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5270 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5271 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5272 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5273 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5274 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5275 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5276 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5277 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5278 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5279 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5280 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5281 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5282 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5283 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5284 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5285 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5286 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5287 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5288 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5290 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5292 int format_slots
= xtensa_format_num_slots (isa
, i
);
5293 if (format_slots
> config_max_slots
)
5294 config_max_slots
= format_slots
;
5297 xg_init_vinsn (&cur_vinsn
);
5299 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5301 init_op_placement_info_table ();
5303 /* Set up the assembly state. */
5304 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5305 xtensa_set_frag_assembly_state (frag_now
);
5309 /* TC_INIT_FIX_DATA hook */
5312 xtensa_init_fix_data (fixS
*x
)
5314 x
->tc_fix_data
.slot
= 0;
5315 x
->tc_fix_data
.X_add_symbol
= NULL
;
5316 x
->tc_fix_data
.X_add_number
= 0;
5320 /* tc_frob_label hook */
5323 xtensa_frob_label (symbolS
*sym
)
5327 if (cur_vinsn
.inside_bundle
)
5329 as_bad (_("labels are not valid inside bundles"));
5333 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5335 /* Since the label was already attached to a frag associated with the
5336 previous basic block, it now needs to be reset to the current frag. */
5337 symbol_set_frag (sym
, frag_now
);
5338 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5340 if (generating_literals
)
5341 xtensa_add_literal_sym (sym
);
5343 xtensa_add_insn_label (sym
);
5345 if (symbol_get_tc (sym
)->is_loop_target
)
5347 if ((get_last_insn_flags (now_seg
, now_subseg
)
5348 & FLAG_IS_BAD_LOOPEND
) != 0)
5349 as_bad (_("invalid last instruction for a zero-overhead loop"));
5351 xtensa_set_frag_assembly_state (frag_now
);
5352 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5353 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5355 xtensa_set_frag_assembly_state (frag_now
);
5356 xtensa_move_labels (frag_now
, 0);
5359 /* No target aligning in the absolute section. */
5360 if (now_seg
!= absolute_section
5361 && !is_unaligned_label (sym
)
5362 && !generating_literals
)
5364 xtensa_set_frag_assembly_state (frag_now
);
5366 if (do_align_targets ())
5367 frag_var (rs_machine_dependent
, 0, (int) freq
,
5368 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5369 frag_now
->fr_offset
, NULL
);
5371 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5372 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5373 xtensa_set_frag_assembly_state (frag_now
);
5374 xtensa_move_labels (frag_now
, 0);
5377 /* We need to mark the following properties even if we aren't aligning. */
5379 /* If the label is already known to be a branch target, i.e., a
5380 forward branch, mark the frag accordingly. Backward branches
5381 are handled by xg_add_branch_and_loop_targets. */
5382 if (symbol_get_tc (sym
)->is_branch_target
)
5383 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5385 /* Loops only go forward, so they can be identified here. */
5386 if (symbol_get_tc (sym
)->is_loop_target
)
5387 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5389 dwarf2_emit_label (sym
);
5393 /* tc_unrecognized_line hook */
5396 xtensa_unrecognized_line (int ch
)
5401 if (cur_vinsn
.inside_bundle
== 0)
5403 /* PR8110: Cannot emit line number info inside a FLIX bundle
5404 when using --gstabs. Temporarily disable debug info. */
5405 generate_lineno_debug ();
5406 if (debug_type
== DEBUG_STABS
)
5408 xt_saved_debug_type
= debug_type
;
5409 debug_type
= DEBUG_NONE
;
5412 cur_vinsn
.inside_bundle
= 1;
5416 as_bad (_("extra opening brace"));
5422 if (cur_vinsn
.inside_bundle
)
5423 finish_vinsn (&cur_vinsn
);
5426 as_bad (_("extra closing brace"));
5431 as_bad (_("syntax error"));
5438 /* md_flush_pending_output hook */
5441 xtensa_flush_pending_output (void)
5443 /* This line fixes a bug where automatically generated gstabs info
5444 separates a function label from its entry instruction, ending up
5445 with the literal position between the function label and the entry
5446 instruction and crashing code. It only happens with --gstabs and
5447 --text-section-literals, and when several other obscure relaxation
5448 conditions are met. */
5449 if (outputting_stabs_line_debug
)
5452 if (cur_vinsn
.inside_bundle
)
5453 as_bad (_("missing closing brace"));
5455 /* If there is a non-zero instruction fragment, close it. */
5456 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5458 frag_wane (frag_now
);
5460 xtensa_set_frag_assembly_state (frag_now
);
5462 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5464 xtensa_clear_insn_labels ();
5468 /* We had an error while parsing an instruction. The string might look
5469 like this: "insn arg1, arg2 }". If so, we need to see the closing
5470 brace and reset some fields. Otherwise, the vinsn never gets closed
5471 and the num_slots field will grow past the end of the array of slots,
5472 and bad things happen. */
5475 error_reset_cur_vinsn (void)
5477 if (cur_vinsn
.inside_bundle
)
5479 if (*input_line_pointer
== '}'
5480 || *(input_line_pointer
- 1) == '}'
5481 || *(input_line_pointer
- 2) == '}')
5482 xg_clear_vinsn (&cur_vinsn
);
5488 md_assemble (char *str
)
5490 xtensa_isa isa
= xtensa_default_isa
;
5493 bfd_boolean has_underbar
= FALSE
;
5494 char *arg_strings
[MAX_INSN_ARGS
];
5496 TInsn orig_insn
; /* Original instruction from the input. */
5498 tinsn_init (&orig_insn
);
5500 /* Split off the opcode. */
5501 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5502 opname
= xstrndup (str
, opnamelen
);
5504 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5507 as_bad (_("syntax error"));
5511 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5514 /* Check for an underbar prefix. */
5517 has_underbar
= TRUE
;
5521 orig_insn
.insn_type
= ITYPE_INSN
;
5523 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5524 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5526 /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its
5527 extra argument and set the opcode to "CALLXn". */
5528 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5529 && strncasecmp (opname
, "callx", 5) == 0)
5531 unsigned long window_size
;
5534 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5535 if (suffix
!= opname
+ 5
5536 && (window_size
== 0
5539 || window_size
== 12)
5540 && strcasecmp (suffix
, ".tls") == 0)
5542 switch (window_size
)
5544 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5545 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5546 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5547 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5551 as_bad (_("wrong number of operands for '%s'"), opname
);
5554 bfd_reloc_code_real_type reloc
;
5555 char *old_input_line_pointer
;
5556 expressionS
*tok
= &orig_insn
.extra_arg
;
5558 old_input_line_pointer
= input_line_pointer
;
5559 input_line_pointer
= arg_strings
[num_args
- 1];
5562 if (tok
->X_op
== O_symbol
5563 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5564 == BFD_RELOC_XTENSA_TLS_CALL
))
5565 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5567 as_bad (_("bad relocation expression for '%s'"), opname
);
5569 input_line_pointer
= old_input_line_pointer
;
5575 /* Special case: Check for "j.l" pseudo op. */
5576 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5577 && strncasecmp (opname
, "j.l", 3) == 0)
5580 as_bad (_("wrong number of operands for '%s'"), opname
);
5583 char *old_input_line_pointer
;
5584 expressionS
*tok
= &orig_insn
.extra_arg
;
5586 old_input_line_pointer
= input_line_pointer
;
5587 input_line_pointer
= arg_strings
[num_args
- 1];
5589 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5590 input_line_pointer
= old_input_line_pointer
;
5593 orig_insn
.opcode
= xtensa_j_opcode
;
5597 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5599 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5600 if (fmt
== XTENSA_UNDEFINED
)
5602 as_bad (_("unknown opcode or format name '%s'"), opname
);
5603 error_reset_cur_vinsn ();
5606 if (!cur_vinsn
.inside_bundle
)
5608 as_bad (_("format names only valid inside bundles"));
5609 error_reset_cur_vinsn ();
5612 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5613 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5615 cur_vinsn
.format
= fmt
;
5616 free (has_underbar
? opname
- 1 : opname
);
5617 error_reset_cur_vinsn ();
5621 /* Parse the arguments. */
5622 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5624 as_bad (_("syntax error"));
5625 error_reset_cur_vinsn ();
5629 /* Free the opcode and argument strings, now that they've been parsed. */
5630 free (has_underbar
? opname
- 1 : opname
);
5632 while (num_args
-- > 0)
5633 free (arg_strings
[num_args
]);
5635 /* Get expressions for invisible operands. */
5636 if (get_invisible_operands (&orig_insn
))
5638 error_reset_cur_vinsn ();
5642 /* Check for the right number and type of arguments. */
5643 if (tinsn_check_arguments (&orig_insn
))
5645 error_reset_cur_vinsn ();
5649 /* Record the line number for each TInsn, because a FLIX bundle may be
5650 spread across multiple input lines and individual instructions may be
5651 moved around in some cases. */
5652 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5653 dwarf2_where (&orig_insn
.debug_line
);
5654 dwarf2_consume_line_info ();
5656 xg_add_branch_and_loop_targets (&orig_insn
);
5658 /* Check that immediate value for ENTRY is >= 16. */
5659 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5661 expressionS
*exp
= &orig_insn
.tok
[2];
5662 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5663 as_warn (_("entry instruction with stack decrement < 16"));
5667 assemble_tokens (opcode, tok, ntok);
5668 expand the tokens from the orig_insn into the
5669 stack of instructions that will not expand
5670 unless required at relaxation time. */
5672 if (!cur_vinsn
.inside_bundle
)
5673 emit_single_op (&orig_insn
);
5674 else /* We are inside a bundle. */
5676 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5677 cur_vinsn
.num_slots
++;
5678 if (*input_line_pointer
== '}'
5679 || *(input_line_pointer
- 1) == '}'
5680 || *(input_line_pointer
- 2) == '}')
5681 finish_vinsn (&cur_vinsn
);
5684 /* We've just emitted a new instruction so clear the list of labels. */
5685 xtensa_clear_insn_labels ();
5687 xtensa_check_frag_count ();
5691 /* HANDLE_ALIGN hook */
5693 /* For a .align directive, we mark the previous block with the alignment
5694 information. This will be placed in the object file in the
5695 property section corresponding to this section. */
5698 xtensa_handle_align (fragS
*fragP
)
5701 && ! fragP
->tc_frag_data
.is_literal
5702 && (fragP
->fr_type
== rs_align
5703 || fragP
->fr_type
== rs_align_code
)
5704 && fragP
->fr_offset
> 0
5705 && now_seg
!= bss_section
)
5707 fragP
->tc_frag_data
.is_align
= TRUE
;
5708 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5711 if (fragP
->fr_type
== rs_align_test
)
5714 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5716 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5717 _("unaligned entry instruction"));
5720 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5721 fragP
->fr_subtype
= RELAX_ORG
;
5725 /* TC_FRAG_INIT hook */
5728 xtensa_frag_init (fragS
*frag
)
5730 xtensa_set_frag_assembly_state (frag
);
5735 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5741 /* Round up a section size to the appropriate boundary. */
5744 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5746 return size
; /* Byte alignment is fine. */
5751 md_pcrel_from (fixS
*fixP
)
5754 static xtensa_insnbuf insnbuf
= NULL
;
5755 static xtensa_insnbuf slotbuf
= NULL
;
5758 xtensa_opcode opcode
;
5761 xtensa_isa isa
= xtensa_default_isa
;
5762 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5763 bfd_boolean alt_reloc
;
5765 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5768 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5773 insnbuf
= xtensa_insnbuf_alloc (isa
);
5774 slotbuf
= xtensa_insnbuf_alloc (isa
);
5777 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5778 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5779 fmt
= xtensa_format_decode (isa
, insnbuf
);
5781 if (fmt
== XTENSA_UNDEFINED
)
5782 as_fatal (_("bad instruction format"));
5784 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5785 as_fatal (_("invalid relocation"));
5787 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5788 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5790 /* Check for "alternate" relocations (operand not specified). None
5791 of the current uses for these are really PC-relative. */
5792 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5794 if (opcode
!= xtensa_l32r_opcode
5795 && opcode
!= xtensa_const16_opcode
)
5796 as_fatal (_("invalid relocation for '%s' instruction"),
5797 xtensa_opcode_name (isa
, opcode
));
5801 opnum
= get_relaxable_immed (opcode
);
5803 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5804 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5806 as_bad_where (fixP
->fx_file
,
5808 _("invalid relocation for operand %d of '%s'"),
5809 opnum
, xtensa_opcode_name (isa
, opcode
));
5812 return 0 - opnd_value
;
5816 /* TC_FORCE_RELOCATION hook */
5819 xtensa_force_relocation (fixS
*fix
)
5821 switch (fix
->fx_r_type
)
5823 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5824 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5825 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5826 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5827 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5828 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5829 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5830 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5831 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5832 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5833 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5834 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5835 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5836 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5837 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5838 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5844 if (linkrelax
&& fix
->fx_addsy
5845 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5848 return generic_force_reloc (fix
);
5852 /* TC_VALIDATE_FIX_SUB hook */
5855 xtensa_validate_fix_sub (fixS
*fix
)
5857 segT add_symbol_segment
, sub_symbol_segment
;
5859 /* The difference of two symbols should be resolved by the assembler when
5860 linkrelax is not set. If the linker may relax the section containing
5861 the symbols, then an Xtensa DIFF relocation must be generated so that
5862 the linker knows to adjust the difference value. */
5863 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5866 /* Make sure both symbols are in the same segment, and that segment is
5867 "normal" and relaxable. If the segment is not "normal", then the
5868 fix is not valid. If the segment is not "relaxable", then the fix
5869 should have been handled earlier. */
5870 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5871 if (! SEG_NORMAL (add_symbol_segment
) ||
5872 ! relaxable_section (add_symbol_segment
))
5874 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5875 return (sub_symbol_segment
== add_symbol_segment
);
5879 /* NO_PSEUDO_DOT hook */
5881 /* This function has nothing to do with pseudo dots, but this is the
5882 nearest macro to where the check needs to take place. FIXME: This
5886 xtensa_check_inside_bundle (void)
5888 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5889 as_bad (_("directives are not valid inside bundles"));
5891 /* This function must always return FALSE because it is called via a
5892 macro that has nothing to do with bundling. */
5897 /* md_elf_section_change_hook */
5900 xtensa_elf_section_change_hook (void)
5902 /* Set up the assembly state. */
5903 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5904 xtensa_set_frag_assembly_state (frag_now
);
5908 /* tc_fix_adjustable hook */
5911 xtensa_fix_adjustable (fixS
*fixP
)
5913 /* We need the symbol name for the VTABLE entries. */
5914 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5915 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5922 /* tc_symbol_new_hook */
5924 symbolS
*expr_symbols
= NULL
;
5927 xtensa_symbol_new_hook (symbolS
*sym
)
5929 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5931 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5938 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5940 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5943 /* Subtracted symbols are only allowed for a few relocation types, and
5944 unless linkrelax is enabled, they should not make it to this point. */
5945 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5946 || fixP
->fx_r_type
== BFD_RELOC_16
5947 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5950 switch (fixP
->fx_r_type
)
5952 case BFD_RELOC_32_PCREL
:
5958 switch (fixP
->fx_r_type
)
5961 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5962 fixP
->fx_signed
= 0;
5965 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5966 fixP
->fx_signed
= 0;
5969 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5970 fixP
->fx_signed
= 0;
5976 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5977 - S_GET_VALUE (fixP
->fx_subsy
));
5979 /* The difference value gets written out, and the DIFF reloc
5980 identifies the address of the subtracted symbol (i.e., the one
5981 with the lowest address). */
5983 fixP
->fx_offset
-= val
;
5984 fixP
->fx_subsy
= NULL
;
5986 else if (! fixP
->fx_addsy
)
5993 case BFD_RELOC_XTENSA_PLT
:
5994 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5995 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5998 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5999 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
6000 case BFD_RELOC_XTENSA_TLS_TPOFF
:
6001 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
6002 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6003 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
6004 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6007 case BFD_RELOC_XTENSA_SLOT0_OP
:
6008 case BFD_RELOC_XTENSA_SLOT1_OP
:
6009 case BFD_RELOC_XTENSA_SLOT2_OP
:
6010 case BFD_RELOC_XTENSA_SLOT3_OP
:
6011 case BFD_RELOC_XTENSA_SLOT4_OP
:
6012 case BFD_RELOC_XTENSA_SLOT5_OP
:
6013 case BFD_RELOC_XTENSA_SLOT6_OP
:
6014 case BFD_RELOC_XTENSA_SLOT7_OP
:
6015 case BFD_RELOC_XTENSA_SLOT8_OP
:
6016 case BFD_RELOC_XTENSA_SLOT9_OP
:
6017 case BFD_RELOC_XTENSA_SLOT10_OP
:
6018 case BFD_RELOC_XTENSA_SLOT11_OP
:
6019 case BFD_RELOC_XTENSA_SLOT12_OP
:
6020 case BFD_RELOC_XTENSA_SLOT13_OP
:
6021 case BFD_RELOC_XTENSA_SLOT14_OP
:
6024 /* Write the tentative value of a PC-relative relocation to a
6025 local symbol into the instruction. The value will be ignored
6026 by the linker, and it makes the object file disassembly
6027 readable when all branch targets are encoded in relocations. */
6029 gas_assert (fixP
->fx_addsy
);
6030 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
6031 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
6033 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6034 - md_pcrel_from (fixP
));
6035 (void) xg_apply_fix_value (fixP
, val
);
6038 else if (! fixP
->fx_addsy
)
6041 if (xg_apply_fix_value (fixP
, val
))
6046 case BFD_RELOC_XTENSA_ASM_EXPAND
:
6047 case BFD_RELOC_XTENSA_TLS_FUNC
:
6048 case BFD_RELOC_XTENSA_TLS_ARG
:
6049 case BFD_RELOC_XTENSA_TLS_CALL
:
6050 case BFD_RELOC_XTENSA_SLOT0_ALT
:
6051 case BFD_RELOC_XTENSA_SLOT1_ALT
:
6052 case BFD_RELOC_XTENSA_SLOT2_ALT
:
6053 case BFD_RELOC_XTENSA_SLOT3_ALT
:
6054 case BFD_RELOC_XTENSA_SLOT4_ALT
:
6055 case BFD_RELOC_XTENSA_SLOT5_ALT
:
6056 case BFD_RELOC_XTENSA_SLOT6_ALT
:
6057 case BFD_RELOC_XTENSA_SLOT7_ALT
:
6058 case BFD_RELOC_XTENSA_SLOT8_ALT
:
6059 case BFD_RELOC_XTENSA_SLOT9_ALT
:
6060 case BFD_RELOC_XTENSA_SLOT10_ALT
:
6061 case BFD_RELOC_XTENSA_SLOT11_ALT
:
6062 case BFD_RELOC_XTENSA_SLOT12_ALT
:
6063 case BFD_RELOC_XTENSA_SLOT13_ALT
:
6064 case BFD_RELOC_XTENSA_SLOT14_ALT
:
6065 /* These all need to be resolved at link-time. Do nothing now. */
6068 case BFD_RELOC_VTABLE_INHERIT
:
6069 case BFD_RELOC_VTABLE_ENTRY
:
6074 as_bad (_("unhandled local relocation fix %s"),
6075 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6081 md_atof (int type
, char *litP
, int *sizeP
)
6083 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
6088 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
6090 return total_frag_text_expansion (fragP
);
6094 /* Translate internal representation of relocation info to BFD target
6098 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6102 reloc
= XNEW (arelent
);
6103 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
6104 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6105 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6107 /* Make sure none of our internal relocations make it this far.
6108 They'd better have been fully resolved by this point. */
6109 gas_assert ((int) fixp
->fx_r_type
> 0);
6111 reloc
->addend
= fixp
->fx_offset
;
6113 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6114 if (reloc
->howto
== NULL
)
6116 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6117 _("cannot represent `%s' relocation in object file"),
6118 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6119 free (reloc
->sym_ptr_ptr
);
6124 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6125 as_fatal (_("internal error; cannot generate `%s' relocation"),
6126 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6132 /* Checks for resource conflicts between instructions. */
6134 /* The func unit stuff could be implemented as bit-vectors rather
6135 than the iterative approach here. If it ends up being too
6136 slow, we will switch it. */
6139 new_resource_table (void *data
,
6142 unit_num_copies_func uncf
,
6143 opcode_num_units_func onuf
,
6144 opcode_funcUnit_use_unit_func ouuf
,
6145 opcode_funcUnit_use_stage_func ousf
)
6148 resource_table
*rt
= XNEW (resource_table
);
6150 rt
->cycles
= cycles
;
6151 rt
->allocated_cycles
= cycles
;
6153 rt
->unit_num_copies
= uncf
;
6154 rt
->opcode_num_units
= onuf
;
6155 rt
->opcode_unit_use
= ouuf
;
6156 rt
->opcode_unit_stage
= ousf
;
6158 rt
->units
= XCNEWVEC (unsigned char *, cycles
);
6159 for (i
= 0; i
< cycles
; i
++)
6160 rt
->units
[i
] = XCNEWVEC (unsigned char, nu
);
6167 clear_resource_table (resource_table
*rt
)
6170 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6171 for (j
= 0; j
< rt
->num_units
; j
++)
6172 rt
->units
[i
][j
] = 0;
6176 /* We never shrink it, just fake it into thinking so. */
6179 resize_resource_table (resource_table
*rt
, int cycles
)
6183 rt
->cycles
= cycles
;
6184 if (cycles
<= rt
->allocated_cycles
)
6187 old_cycles
= rt
->allocated_cycles
;
6188 rt
->allocated_cycles
= cycles
;
6190 rt
->units
= XRESIZEVEC (unsigned char *, rt
->units
, rt
->allocated_cycles
);
6191 for (i
= 0; i
< old_cycles
; i
++)
6192 rt
->units
[i
] = XRESIZEVEC (unsigned char, rt
->units
[i
], rt
->num_units
);
6193 for (i
= old_cycles
; i
< cycles
; i
++)
6194 rt
->units
[i
] = XCNEWVEC (unsigned char, rt
->num_units
);
6199 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6202 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6204 for (i
= 0; i
< uses
; i
++)
6206 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6207 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6208 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6209 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6210 if (copies_in_use
>= copies
)
6218 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6221 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6223 for (i
= 0; i
< uses
; i
++)
6225 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6226 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6227 /* Note that this allows resources to be oversubscribed. That's
6228 essential to the way the optional scheduler works.
6229 resources_available reports when a resource is over-subscribed,
6230 so it's easy to tell. */
6231 rt
->units
[stage
+ cycle
][unit
]++;
6237 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6240 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6242 for (i
= 0; i
< uses
; i
++)
6244 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6245 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6246 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6247 rt
->units
[stage
+ cycle
][unit
]--;
6252 /* Wrapper functions make parameterized resource reservation
6256 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6258 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6264 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6266 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6271 /* Note that this function does not check issue constraints, but
6272 solely whether the hardware is available to execute the given
6273 instructions together. It also doesn't check if the tinsns
6274 write the same state, or access the same tieports. That is
6275 checked by check_t1_t2_reads_and_writes. */
6278 resources_conflict (vliw_insn
*vinsn
)
6281 static resource_table
*rt
= NULL
;
6283 /* This is the most common case by far. Optimize it. */
6284 if (vinsn
->num_slots
== 1)
6289 xtensa_isa isa
= xtensa_default_isa
;
6290 rt
= new_resource_table
6291 (isa
, xtensa_num_pipe_stages
,
6292 xtensa_isa_num_funcUnits (isa
),
6293 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6294 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6295 opcode_funcUnit_use_unit
,
6296 opcode_funcUnit_use_stage
);
6299 clear_resource_table (rt
);
6301 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6303 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6305 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6312 /* finish_vinsn, emit_single_op and helper functions. */
6314 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6315 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6316 static void xg_assemble_vliw_tokens (vliw_insn
*);
6319 /* We have reached the end of a bundle; emit into the frag. */
6322 finish_vinsn (vliw_insn
*vinsn
)
6327 if (find_vinsn_conflicts (vinsn
))
6329 xg_clear_vinsn (vinsn
);
6333 /* First, find a format that works. */
6334 if (vinsn
->format
== XTENSA_UNDEFINED
)
6335 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6337 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6338 && produce_flix
== FLIX_NONE
)
6340 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6341 xg_clear_vinsn (vinsn
);
6345 if (vinsn
->format
== XTENSA_UNDEFINED
)
6347 as_bad (_("couldn't find a valid instruction format"));
6348 fprintf (stderr
, _(" ops were: "));
6349 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6350 fprintf (stderr
, _(" %s;"),
6351 xtensa_opcode_name (xtensa_default_isa
,
6352 vinsn
->slots
[i
].opcode
));
6353 fprintf (stderr
, _("\n"));
6354 xg_clear_vinsn (vinsn
);
6358 if (vinsn
->num_slots
6359 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6362 int slots
= xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
);
6364 msg
= concat (ngettext ("format '%s' allows %d slot, ",
6365 "format '%s' allows %d slots, ",
6367 ngettext ("but there is %d opcode",
6368 "but there are %d opcodes",
6372 as_bad (msg
, xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6373 slots
, vinsn
->num_slots
);
6375 xg_clear_vinsn (vinsn
);
6379 if (resources_conflict (vinsn
))
6381 as_bad (_("illegal resource usage in bundle"));
6382 fprintf (stderr
, " ops were: ");
6383 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6384 fprintf (stderr
, " %s;",
6385 xtensa_opcode_name (xtensa_default_isa
,
6386 vinsn
->slots
[i
].opcode
));
6387 fprintf (stderr
, "\n");
6388 xg_clear_vinsn (vinsn
);
6392 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6394 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6396 symbolS
*lit_sym
= NULL
;
6398 bfd_boolean e
= FALSE
;
6399 bfd_boolean saved_density
= density_supported
;
6401 /* We don't want to narrow ops inside multi-slot bundles. */
6402 if (vinsn
->num_slots
> 1)
6403 density_supported
= FALSE
;
6405 istack_init (&slotstack
);
6406 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6408 vinsn
->slots
[i
].opcode
=
6409 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6411 vinsn
->slots
[i
].ntok
= 0;
6414 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6420 density_supported
= saved_density
;
6424 xg_clear_vinsn (vinsn
);
6428 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6430 TInsn
*insn
= &slotstack
.insn
[j
];
6431 if (insn
->insn_type
== ITYPE_LITERAL
)
6433 gas_assert (lit_sym
== NULL
);
6434 lit_sym
= xg_assemble_literal (insn
);
6438 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6440 xg_resolve_literals (insn
, lit_sym
);
6441 if (j
!= slotstack
.ninsn
- 1)
6442 emit_single_op (insn
);
6446 if (vinsn
->num_slots
> 1)
6448 if (opcode_fits_format_slot
6449 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6452 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6456 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6457 if (vinsn
->format
== XTENSA_UNDEFINED
)
6458 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6460 vinsn
->slots
[i
].opcode
6461 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6464 vinsn
->slots
[i
].ntok
= 0;
6469 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6470 vinsn
->format
= XTENSA_UNDEFINED
;
6475 /* Now check resource conflicts on the modified bundle. */
6476 if (resources_conflict (vinsn
))
6478 as_bad (_("illegal resource usage in bundle"));
6479 fprintf (stderr
, " ops were: ");
6480 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6481 fprintf (stderr
, " %s;",
6482 xtensa_opcode_name (xtensa_default_isa
,
6483 vinsn
->slots
[i
].opcode
));
6484 fprintf (stderr
, "\n");
6485 xg_clear_vinsn (vinsn
);
6489 /* First, find a format that works. */
6490 if (vinsn
->format
== XTENSA_UNDEFINED
)
6491 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6493 xg_assemble_vliw_tokens (vinsn
);
6495 xg_clear_vinsn (vinsn
);
6497 xtensa_check_frag_count ();
6501 /* Given an vliw instruction, what conflicts are there in register
6502 usage and in writes to states and queues?
6504 This function does two things:
6505 1. Reports an error when a vinsn contains illegal combinations
6506 of writes to registers states or queues.
6507 2. Marks individual tinsns as not relaxable if the combination
6508 contains antidependencies.
6510 Job 2 handles things like swap semantics in instructions that need
6511 to be relaxed. For example,
6515 normally would be relaxed to
6520 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6522 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6524 then we can't relax it into
6527 { add a0, a1, a0 ; add a2, a0, a4 ; }
6529 because the value of a0 is trashed before the second add can read it. */
6531 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6534 find_vinsn_conflicts (vliw_insn
*vinsn
)
6538 xtensa_isa isa
= xtensa_default_isa
;
6540 gas_assert (!past_xtensa_end
);
6542 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6544 TInsn
*op1
= &vinsn
->slots
[i
];
6545 if (op1
->is_specific_opcode
)
6546 op1
->keep_wide
= TRUE
;
6548 op1
->keep_wide
= FALSE
;
6551 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6553 TInsn
*op1
= &vinsn
->slots
[i
];
6555 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6558 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6562 TInsn
*op2
= &vinsn
->slots
[j
];
6563 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6564 switch (conflict_type
)
6567 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6568 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6569 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6572 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6573 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6574 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6577 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6578 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6579 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6582 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6583 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6584 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6587 /* Everything is OK. */
6590 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6591 || conflict_type
== 'a');
6598 as_bad (_("multiple branches or jumps in the same bundle"));
6606 /* Check how the state used by t1 and t2 relate.
6609 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6610 case B: no relationship between what is read and written (both could
6611 read the same reg though)
6612 case C: t1 writes a register t2 writes (a register conflict within a
6614 case D: t1 writes a state that t2 also writes
6615 case E: t1 writes a tie queue that t2 also writes
6616 case F: two volatile queue accesses
6620 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6622 xtensa_isa isa
= xtensa_default_isa
;
6623 xtensa_regfile t1_regfile
, t2_regfile
;
6625 int t1_base_reg
, t1_last_reg
;
6626 int t2_base_reg
, t2_last_reg
;
6627 char t1_inout
, t2_inout
;
6629 char conflict
= 'b';
6634 bfd_boolean t1_volatile
= FALSE
;
6635 bfd_boolean t2_volatile
= FALSE
;
6637 /* Check registers. */
6638 for (j
= 0; j
< t2
->ntok
; j
++)
6640 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6643 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6644 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6645 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6647 for (i
= 0; i
< t1
->ntok
; i
++)
6649 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6652 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6654 if (t1_regfile
!= t2_regfile
)
6657 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6658 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6660 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6661 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6663 if (t1_inout
== 'm' || t1_inout
== 'o'
6664 || t2_inout
== 'm' || t2_inout
== 'o')
6671 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6672 t1_last_reg
= (t1_base_reg
6673 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6675 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6677 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6679 if (t1_reg
!= t2_reg
)
6682 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6688 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6694 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6702 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6703 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6704 for (j
= 0; j
< t2_states
; j
++)
6706 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6707 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6708 for (i
= 0; i
< t1_states
; i
++)
6710 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6711 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6712 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6715 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6721 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6727 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6732 /* Check tieports. */
6733 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6734 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6735 for (j
= 0; j
< t2_interfaces
; j
++)
6737 xtensa_interface t2_int
6738 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6739 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6741 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6742 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6745 for (i
= 0; i
< t1_interfaces
; i
++)
6747 xtensa_interface t1_int
6748 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6749 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6751 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6752 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6755 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6758 if (t1_int
!= t2_int
)
6761 if (t2_inout
== 'i' && t1_inout
== 'o')
6767 if (t1_inout
== 'i' && t2_inout
== 'o')
6773 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6782 static xtensa_format
6783 xg_find_narrowest_format (vliw_insn
*vinsn
)
6785 /* Right now we assume that the ops within the vinsn are properly
6786 ordered for the slots that the programmer wanted them in. In
6787 other words, we don't rearrange the ops in hopes of finding a
6788 better format. The scheduler handles that. */
6790 xtensa_isa isa
= xtensa_default_isa
;
6791 xtensa_format format
;
6792 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6794 if (vinsn
->num_slots
== 1)
6795 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6797 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6800 xg_copy_vinsn (&v_copy
, vinsn
);
6801 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6805 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6807 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6809 v_copy
.slots
[slot
].opcode
=
6810 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6811 v_copy
.slots
[slot
].ntok
= 0;
6814 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6817 else if (v_copy
.num_slots
> 1)
6820 /* Try the widened version. */
6821 if (!v_copy
.slots
[slot
].keep_wide
6822 && !v_copy
.slots
[slot
].is_specific_opcode
6823 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6825 && opcode_fits_format_slot (widened
.opcode
,
6828 v_copy
.slots
[slot
] = widened
;
6833 if (fit
== v_copy
.num_slots
)
6835 xg_copy_vinsn (vinsn
, &v_copy
);
6836 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6837 vinsn
->format
= format
;
6843 if (format
== xtensa_isa_num_formats (isa
))
6844 return XTENSA_UNDEFINED
;
6850 /* Return the additional space needed in a frag
6851 for possible relaxations of any ops in a VLIW insn.
6852 Also fill out the relaxations that might be required of
6853 each tinsn in the vinsn. */
6856 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6858 bfd_boolean finish_frag
= FALSE
;
6859 int extra_space
= 0;
6862 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6864 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6865 if (!tinsn_has_symbolic_operands (tinsn
))
6867 /* A narrow instruction could be widened later to help
6868 alignment issues. */
6869 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6870 && !tinsn
->is_specific_opcode
6871 && vinsn
->num_slots
== 1)
6873 /* Difference in bytes between narrow and wide insns... */
6875 tinsn
->subtype
= RELAX_NARROW
;
6880 if (workaround_b_j_loop_end
6881 && tinsn
->opcode
== xtensa_jx_opcode
6882 && use_transform ())
6884 /* Add 2 of these. */
6885 extra_space
+= 3; /* for the nop size */
6886 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6889 /* Need to assemble it with space for the relocation. */
6890 if (xg_is_relaxable_insn (tinsn
, 0)
6891 && !tinsn
->is_specific_opcode
)
6893 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6894 int max_literal_size
=
6895 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6897 tinsn
->literal_space
= max_literal_size
;
6899 tinsn
->subtype
= RELAX_IMMED
;
6900 extra_space
+= max_size
;
6904 /* A fix record will be added for this instruction prior
6905 to relaxation, so make it end the frag. */
6910 *pfinish_frag
= finish_frag
;
6916 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6918 xtensa_isa isa
= xtensa_default_isa
;
6919 int slot
, chosen_slot
;
6921 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6922 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6923 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6925 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6926 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6928 if (slot
== chosen_slot
)
6929 vinsn
->slots
[slot
] = *tinsn
;
6932 vinsn
->slots
[slot
].opcode
=
6933 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6934 vinsn
->slots
[slot
].ntok
= 0;
6935 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6942 emit_single_op (TInsn
*orig_insn
)
6945 IStack istack
; /* put instructions into here */
6946 symbolS
*lit_sym
= NULL
;
6947 symbolS
*label_sym
= NULL
;
6949 istack_init (&istack
);
6951 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6952 Because the scheduling and bundling characteristics of movi and
6953 l32r or const16 are so different, we can do much better if we relax
6954 it prior to scheduling and bundling, rather than after. */
6955 if ((orig_insn
->opcode
== xtensa_movi_opcode
6956 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6957 && !cur_vinsn
.inside_bundle
6958 && (orig_insn
->tok
[1].X_op
== O_symbol
6959 || orig_insn
->tok
[1].X_op
== O_pltrel
6960 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6961 || orig_insn
->tok
[1].X_op
== O_tlsarg
6962 || orig_insn
->tok
[1].X_op
== O_tpoff
6963 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6964 && !orig_insn
->is_specific_opcode
&& use_transform ())
6965 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6967 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6970 for (i
= 0; i
< istack
.ninsn
; i
++)
6972 TInsn
*insn
= &istack
.insn
[i
];
6973 switch (insn
->insn_type
)
6976 gas_assert (lit_sym
== NULL
);
6977 lit_sym
= xg_assemble_literal (insn
);
6981 static int relaxed_sym_idx
= 0;
6982 char *label
= XNEWVEC (char, strlen (FAKE_LABEL_NAME
) + 12);
6983 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6985 gas_assert (label_sym
== NULL
);
6986 label_sym
= symbol_find_or_make (label
);
6987 gas_assert (label_sym
);
6995 xg_resolve_literals (insn
, lit_sym
);
6997 xg_resolve_labels (insn
, label_sym
);
6999 bundle_tinsn (insn
, &v
);
7014 total_frag_text_expansion (fragS
*fragP
)
7017 int total_expansion
= 0;
7019 for (slot
= 0; slot
< config_max_slots
; slot
++)
7020 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
7022 return total_expansion
;
7026 /* Emit a vliw instruction to the current fragment. */
7029 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
7031 bfd_boolean finish_frag
;
7032 bfd_boolean is_jump
= FALSE
;
7033 bfd_boolean is_branch
= FALSE
;
7034 xtensa_isa isa
= xtensa_default_isa
;
7039 struct dwarf2_line_info debug_line
;
7040 bfd_boolean loc_directive_seen
= FALSE
;
7043 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
7045 if (generating_literals
)
7047 static int reported
= 0;
7049 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
7050 _("cannot assemble into a literal fragment"));
7057 if (frag_now_fix () != 0
7058 && (! frag_now
->tc_frag_data
.is_insn
7059 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7060 || (!use_transform ()) != frag_now
->tc_frag_data
.is_no_transform
7061 || (directive_state
[directive_longcalls
]
7062 != frag_now
->tc_frag_data
.use_longcalls
)
7063 || (directive_state
[directive_absolute_literals
]
7064 != frag_now
->tc_frag_data
.use_absolute_literals
)))
7066 frag_wane (frag_now
);
7068 xtensa_set_frag_assembly_state (frag_now
);
7071 if (workaround_a0_b_retw
7072 && vinsn
->num_slots
== 1
7073 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
7074 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
7075 && use_transform ())
7077 has_a0_b_retw
= TRUE
;
7079 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7080 After the first assembly pass we will check all of them and
7081 add a nop if needed. */
7082 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7083 frag_var (rs_machine_dependent
, 4, 4,
7084 RELAX_ADD_NOP_IF_A0_B_RETW
,
7085 frag_now
->fr_symbol
,
7086 frag_now
->fr_offset
,
7088 xtensa_set_frag_assembly_state (frag_now
);
7089 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7090 frag_var (rs_machine_dependent
, 4, 4,
7091 RELAX_ADD_NOP_IF_A0_B_RETW
,
7092 frag_now
->fr_symbol
,
7093 frag_now
->fr_offset
,
7095 xtensa_set_frag_assembly_state (frag_now
);
7098 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7100 tinsn
= &vinsn
->slots
[slot
];
7102 /* See if the instruction implies an aligned section. */
7103 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7104 record_alignment (now_seg
, 2);
7106 /* Determine the best line number for debug info. */
7107 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7108 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7109 || tinsn
->debug_line
.line
< debug_line
.line
7110 || tinsn
->debug_line
.column
< debug_line
.column
))
7111 debug_line
= tinsn
->debug_line
;
7112 if (tinsn
->loc_directive_seen
)
7113 loc_directive_seen
= TRUE
;
7116 /* Special cases for instructions that force an alignment... */
7117 /* None of these opcodes are bundle-able. */
7118 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7122 /* Remember the symbol that marks the end of the loop in the frag
7123 that marks the start of the loop. This way we can easily find
7124 the end of the loop at the beginning, without adding special code
7125 to mark the loop instructions themselves. */
7126 symbolS
*target_sym
= NULL
;
7127 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7128 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7130 xtensa_set_frag_assembly_state (frag_now
);
7131 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7133 max_fill
= get_text_align_max_fill_size
7134 (get_text_align_power (xtensa_fetch_width
),
7135 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7137 if (use_transform ())
7138 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7139 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7141 frag_var (rs_machine_dependent
, 0, 0,
7142 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7143 xtensa_set_frag_assembly_state (frag_now
);
7146 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7147 && !vinsn
->slots
[0].is_specific_opcode
)
7149 xtensa_mark_literal_pool_location ();
7150 xtensa_move_labels (frag_now
, 0);
7151 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7154 if (vinsn
->num_slots
== 1)
7156 if (workaround_a0_b_retw
&& use_transform ())
7157 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7158 is_register_writer (&vinsn
->slots
[0], "a", 0));
7160 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7161 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7164 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7166 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7168 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7170 /* vinsn_to_insnbuf will produce the error. */
7171 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7173 f
= frag_more (insn_size
+ extra_space
);
7174 xtensa_set_frag_assembly_state (frag_now
);
7175 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7178 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7179 if (vinsn
->format
== XTENSA_UNDEFINED
)
7182 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7184 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7185 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7188 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7190 tinsn
= &vinsn
->slots
[slot
];
7191 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7192 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7193 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7194 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7195 if (tinsn
->opcode
== xtensa_l32r_opcode
)
7197 frag_now
->tc_frag_data
.literal_frags
[slot
] =
7198 tinsn
->tok
[1].X_add_symbol
->sy_frag
;
7200 if (tinsn
->literal_space
!= 0)
7201 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7202 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7204 if (tinsn
->subtype
== RELAX_NARROW
)
7205 gas_assert (vinsn
->num_slots
== 1);
7206 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7208 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7211 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7212 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7216 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7217 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7221 frag_variant (rs_machine_dependent
,
7222 extra_space
, extra_space
, RELAX_SLOTS
,
7223 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7224 xtensa_set_frag_assembly_state (frag_now
);
7227 /* Special cases for loops:
7228 close_loop_end should be inserted AFTER short_loop.
7229 Make sure that CLOSE loops are processed BEFORE short_loops
7230 when converting them. */
7232 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7233 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7234 && !vinsn
->slots
[0].is_specific_opcode
)
7236 if (workaround_short_loop
&& use_transform ())
7238 maybe_has_short_loop
= TRUE
;
7239 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7240 frag_var (rs_machine_dependent
, 4, 4,
7241 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7242 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7243 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7244 frag_var (rs_machine_dependent
, 4, 4,
7245 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7246 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7249 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7250 loop at least 12 bytes away from another loop's end. */
7251 if (workaround_close_loop_end
&& use_transform ())
7253 maybe_has_close_loop_end
= TRUE
;
7254 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7255 frag_var (rs_machine_dependent
, 12, 12,
7256 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7257 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7261 if (use_transform ())
7265 gas_assert (finish_frag
);
7266 frag_var (rs_machine_dependent
,
7267 xtensa_fetch_width
, xtensa_fetch_width
,
7269 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7270 xtensa_set_frag_assembly_state (frag_now
);
7271 xtensa_maybe_create_trampoline_frag ();
7272 /* Always create one here. */
7273 xtensa_maybe_create_literal_pool_frag (TRUE
, FALSE
);
7275 else if (is_branch
&& do_align_targets ())
7277 gas_assert (finish_frag
);
7278 frag_var (rs_machine_dependent
,
7279 xtensa_fetch_width
, xtensa_fetch_width
,
7280 RELAX_MAYBE_UNREACHABLE
,
7281 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7282 xtensa_set_frag_assembly_state (frag_now
);
7283 frag_var (rs_machine_dependent
,
7285 RELAX_MAYBE_DESIRE_ALIGN
,
7286 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7287 xtensa_set_frag_assembly_state (frag_now
);
7291 /* Now, if the original opcode was a call... */
7292 if (do_align_targets ()
7293 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7295 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7296 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7297 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7298 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7299 xtensa_set_frag_assembly_state (frag_now
);
7302 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7304 frag_wane (frag_now
);
7306 xtensa_set_frag_assembly_state (frag_now
);
7311 /* xtensa_end and helper functions. */
7313 static void xtensa_cleanup_align_frags (void);
7314 static void xtensa_fix_target_frags (void);
7315 static void xtensa_mark_narrow_branches (void);
7316 static void xtensa_mark_zcl_first_insns (void);
7317 static void xtensa_mark_difference_of_two_symbols (void);
7318 static void xtensa_fix_a0_b_retw_frags (void);
7319 static void xtensa_fix_b_j_loop_end_frags (void);
7320 static void xtensa_fix_close_loop_end_frags (void);
7321 static void xtensa_fix_short_loop_frags (void);
7322 static void xtensa_sanity_check (void);
7323 static void xtensa_add_config_info (void);
7328 directive_balance ();
7329 xtensa_flush_pending_output ();
7331 past_xtensa_end
= TRUE
;
7333 xtensa_move_literals ();
7335 xtensa_reorder_segments ();
7336 xtensa_cleanup_align_frags ();
7337 xtensa_fix_target_frags ();
7338 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7339 xtensa_fix_a0_b_retw_frags ();
7340 if (workaround_b_j_loop_end
)
7341 xtensa_fix_b_j_loop_end_frags ();
7343 /* "close_loop_end" should be processed BEFORE "short_loop". */
7344 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7345 xtensa_fix_close_loop_end_frags ();
7347 if (workaround_short_loop
&& maybe_has_short_loop
)
7348 xtensa_fix_short_loop_frags ();
7350 xtensa_mark_narrow_branches ();
7351 xtensa_mark_zcl_first_insns ();
7353 xtensa_sanity_check ();
7355 xtensa_add_config_info ();
7357 xtensa_check_frag_count ();
7361 struct trampoline_frag
7363 struct trampoline_frag
*next
;
7364 bfd_boolean needs_jump_around
;
7369 struct trampoline_seg
7371 struct trampoline_seg
*next
;
7373 struct trampoline_frag trampoline_list
;
7376 static struct trampoline_seg trampoline_seg_list
;
7377 #define J_RANGE (128 * 1024)
7379 static int unreachable_count
= 0;
7383 xtensa_maybe_create_trampoline_frag (void)
7385 if (!use_trampolines
)
7388 /* We create an area for possible trampolines every 10 unreachable frags.
7389 These are preferred over the ones not preceded by an unreachable frag,
7390 because we don't have to jump around them. This function is called after
7391 each RELAX_UNREACHABLE frag is created. */
7393 if (++unreachable_count
> 10)
7395 xtensa_create_trampoline_frag (FALSE
);
7396 clear_frag_count ();
7397 unreachable_count
= 0;
7402 xtensa_check_frag_count (void)
7404 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7407 /* We create an area for possible trampolines every 8000 frags or so. This
7408 is an estimate based on the max range of a "j" insn (+/-128K) divided
7409 by a typical frag byte count (16), minus a few for safety. This function
7410 is called after each source line is processed. */
7412 if (get_frag_count () > 8000)
7414 xtensa_create_trampoline_frag (TRUE
);
7415 clear_frag_count ();
7416 unreachable_count
= 0;
7419 /* We create an area for a possible literal pool every N (default 5000)
7421 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
7424 static xtensa_insnbuf trampoline_buf
= NULL
;
7425 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7427 static xtensa_insnbuf litpool_buf
= NULL
;
7428 static xtensa_insnbuf litpool_slotbuf
= NULL
;
7430 #define TRAMPOLINE_FRAG_SIZE 3000
7433 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7435 /* Emit a frag where we can place intermediate jump instructions,
7436 in case we need to jump farther than 128K bytes.
7437 Each jump instruction takes three bytes.
7438 We allocate enough for 1000 trampolines in each frag.
7439 If that's not enough, oh well. */
7441 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7442 struct trampoline_frag
*tf
;
7445 int size
= TRAMPOLINE_FRAG_SIZE
;
7447 for ( ; ts
; ts
= ts
->next
)
7449 if (ts
->seg
== now_seg
)
7455 ts
= XCNEW(struct trampoline_seg
);
7456 ts
->next
= trampoline_seg_list
.next
;
7457 trampoline_seg_list
.next
= ts
;
7461 frag_wane (frag_now
);
7463 xtensa_set_frag_assembly_state (frag_now
);
7464 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7465 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7466 if (trampoline_buf
== NULL
)
7468 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7469 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7471 tf
= XNEW (struct trampoline_frag
);
7472 tf
->next
= ts
->trampoline_list
.next
;
7473 ts
->trampoline_list
.next
= tf
;
7474 tf
->needs_jump_around
= needs_jump_around
;
7480 static struct trampoline_seg
*
7481 find_trampoline_seg (asection
*seg
)
7483 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7485 for ( ; ts
; ts
= ts
->next
)
7495 void dump_trampolines (void);
7498 dump_trampolines (void)
7500 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7502 for ( ; ts
; ts
= ts
->next
)
7504 asection
*seg
= ts
->seg
;
7508 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7509 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
7510 for ( ; tf
; tf
= tf
->next
)
7512 if (tf
->fragP
== NULL
)
7514 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7515 (int)tf
->fragP
->fr_address
, (int)tf
->fragP
->fr_fix
,
7516 tf
->needs_jump_around
? "T" : "F");
7521 static void dump_litpools (void) __attribute__ ((unused
));
7524 dump_litpools (void)
7526 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7527 struct litpool_frag
*lpf
;
7529 for ( ; lps
; lps
= lps
->next
)
7531 printf("litpool seg %s\n", lps
->seg
->name
);
7532 for ( lpf
= lps
->frag_list
.next
; lpf
->fragP
; lpf
= lpf
->next
)
7534 fragS
*litfrag
= lpf
->fragP
->fr_next
;
7536 while (litfrag
&& litfrag
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
7538 if (litfrag
->fr_fix
== 4)
7540 litfrag
= litfrag
->fr_next
;
7542 printf(" %ld <%d:%d> (%d) [%d]: ",
7543 lpf
->addr
, lpf
->priority
, lpf
->original_priority
,
7544 lpf
->fragP
->fr_line
, count
);
7545 //dump_frag(lpf->fragP);
7551 xtensa_maybe_create_literal_pool_frag (bfd_boolean create
,
7552 bfd_boolean only_if_needed
)
7554 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7556 struct litpool_frag
*lpf
;
7557 bfd_boolean needed
= FALSE
;
7559 if (use_literal_section
|| !auto_litpools
)
7562 for ( ; lps
; lps
= lps
->next
)
7564 if (lps
->seg
== now_seg
)
7570 lps
= XCNEW (struct litpool_seg
);
7571 lps
->next
= litpool_seg_list
.next
;
7572 litpool_seg_list
.next
= lps
;
7574 lps
->frag_list
.next
= &lps
->frag_list
;
7575 lps
->frag_list
.prev
= &lps
->frag_list
;
7576 /* Put candidate literal pool at the beginning of every section,
7577 so that even when section starts with literal load there's a
7578 literal pool available. */
7579 lps
->frag_count
= auto_litpool_limit
;
7588 if (past_xtensa_end
|| !use_transform() ||
7589 frag_now
->tc_frag_data
.is_no_transform
)
7593 if (auto_litpool_limit
<= 0)
7595 /* Don't create a litpool based only on frag count. */
7598 else if (lps
->frag_count
> auto_litpool_limit
)
7615 int size
= (only_if_needed
) ? 3 : 0; /* Space for a "j" insn. */
7616 /* Create a potential site for a literal pool. */
7617 frag_wane (frag_now
);
7619 xtensa_set_frag_assembly_state (frag_now
);
7621 fragP
->tc_frag_data
.lit_frchain
= frchain_now
;
7622 fragP
->tc_frag_data
.literal_frag
= fragP
;
7623 frag_var (rs_machine_dependent
, size
, size
,
7625 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
7626 RELAX_LITERAL_POOL_BEGIN
,
7628 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
7629 frag_variant (rs_machine_dependent
, 0, 0,
7630 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
7631 xtensa_set_frag_assembly_state (frag_now
);
7635 /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7636 just record it here. */
7640 lpf
= XNEW (struct litpool_frag
);
7641 /* Insert at tail of circular list. */
7643 lps
->frag_list
.prev
->next
= lpf
;
7644 lpf
->next
= &lps
->frag_list
;
7645 lpf
->prev
= lps
->frag_list
.prev
;
7646 lps
->frag_list
.prev
= lpf
;
7648 lpf
->priority
= (needed
) ? (only_if_needed
) ? 3 : 2 : 1;
7649 lpf
->original_priority
= lpf
->priority
;
7651 lps
->frag_count
= 0;
7655 xtensa_cleanup_align_frags (void)
7660 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7661 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7664 /* Walk over all of the fragments in a subsection. */
7665 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7667 if ((fragP
->fr_type
== rs_align
7668 || fragP
->fr_type
== rs_align_code
7669 || (fragP
->fr_type
== rs_machine_dependent
7670 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7671 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7672 && fragP
->fr_fix
== 0)
7674 fragS
*next
= fragP
->fr_next
;
7677 && next
->fr_fix
== 0
7678 && next
->fr_type
== rs_machine_dependent
7679 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7682 next
= next
->fr_next
;
7685 /* If we don't widen branch targets, then they
7686 will be easier to align. */
7687 if (fragP
->tc_frag_data
.is_branch_target
7688 && fragP
->fr_opcode
== fragP
->fr_literal
7689 && fragP
->fr_type
== rs_machine_dependent
7690 && fragP
->fr_subtype
== RELAX_SLOTS
7691 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7693 if (fragP
->fr_type
== rs_machine_dependent
7694 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7695 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7701 /* Re-process all of the fragments looking to convert all of the
7702 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7703 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7704 Otherwise, convert to a .fill 0. */
7707 xtensa_fix_target_frags (void)
7712 /* When this routine is called, all of the subsections are still intact
7713 so we walk over subsections instead of sections. */
7714 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7715 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7719 /* Walk over all of the fragments in a subsection. */
7720 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7722 if (fragP
->fr_type
== rs_machine_dependent
7723 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7725 if (next_frag_is_branch_target (fragP
))
7726 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7735 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7738 xtensa_mark_narrow_branches (void)
7743 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7744 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7747 /* Walk over all of the fragments in a subsection. */
7748 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7750 if (fragP
->fr_type
== rs_machine_dependent
7751 && fragP
->fr_subtype
== RELAX_SLOTS
7752 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7756 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7757 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7759 if (vinsn
.num_slots
== 1
7760 && xtensa_opcode_is_branch (xtensa_default_isa
,
7761 vinsn
.slots
[0].opcode
) == 1
7762 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7763 && is_narrow_branch_guaranteed_in_range (fragP
,
7766 fragP
->fr_subtype
= RELAX_SLOTS
;
7767 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7768 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7776 /* A branch is typically widened only when its target is out of
7777 range. However, we would like to widen them to align a subsequent
7778 branch target when possible.
7780 Because the branch relaxation code is so convoluted, the optimal solution
7781 (combining the two cases) is difficult to get right in all circumstances.
7782 We therefore go with an "almost as good" solution, where we only
7783 use for alignment narrow branches that definitely will not expand to a
7784 jump and a branch. These functions find and mark these cases. */
7786 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7787 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7788 We start counting beginning with the frag after the 2-byte branch, so the
7789 maximum offset is (4 - 2) + 63 = 65. */
7790 #define MAX_IMMED6 65
7792 static offsetT
unrelaxed_frag_max_size (fragS
*);
7795 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7797 const expressionS
*exp
= &tinsn
->tok
[1];
7798 symbolS
*symbolP
= exp
->X_add_symbol
;
7799 offsetT max_distance
= exp
->X_add_number
;
7802 if (exp
->X_op
!= O_symbol
)
7805 target_frag
= symbol_get_frag (symbolP
);
7807 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7808 if (is_branch_jmp_to_next (tinsn
, fragP
))
7811 /* The branch doesn't branch over it's own frag,
7812 but over the subsequent ones. */
7813 fragP
= fragP
->fr_next
;
7814 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7816 max_distance
+= unrelaxed_frag_max_size (fragP
);
7817 fragP
= fragP
->fr_next
;
7819 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7826 xtensa_mark_zcl_first_insns (void)
7831 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7832 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7835 /* Walk over all of the fragments in a subsection. */
7836 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7838 if (fragP
->fr_type
== rs_machine_dependent
7839 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7840 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7842 /* Find the loop frag. */
7843 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7844 /* Find the first insn frag. */
7845 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
7847 /* Handle a corner case that comes up in hardware
7848 diagnostics. The original assembly looks like this:
7851 <empty_frag>--not found by next_non_empty_frag
7854 Depending on the start address, the assembler may or
7855 may not change it to look something like this:
7858 nop--frag isn't empty anymore
7861 So set up to check the alignment of the nop if it
7863 while (loop_frag
!= targ_frag
)
7865 if (loop_frag
->fr_type
== rs_machine_dependent
7866 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7867 || loop_frag
->fr_subtype
7868 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7869 targ_frag
= loop_frag
;
7871 loop_frag
= loop_frag
->fr_next
;
7874 /* Of course, sometimes (mostly for toy test cases) a
7875 zero-cost loop instruction is the last in a section. */
7878 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7879 /* Do not widen a frag that is the first instruction of a
7880 zero-cost loop. It makes that loop harder to align. */
7881 if (targ_frag
->fr_type
== rs_machine_dependent
7882 && targ_frag
->fr_subtype
== RELAX_SLOTS
7883 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7886 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7887 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7890 frag_wane (targ_frag
);
7891 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7895 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7903 /* When a difference-of-symbols expression is encoded as a uleb128 or
7904 sleb128 value, the linker is unable to adjust that value to account for
7905 link-time relaxation. Mark all the code between such symbols so that
7906 its size cannot be changed by linker relaxation. */
7909 xtensa_mark_difference_of_two_symbols (void)
7913 for (expr_sym
= expr_symbols
; expr_sym
;
7914 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7916 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7918 if (exp
->X_op
== O_subtract
)
7920 symbolS
*left
= exp
->X_add_symbol
;
7921 symbolS
*right
= exp
->X_op_symbol
;
7923 /* Difference of two symbols not in the same section
7924 are handled with relocations in the linker. */
7925 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7931 if (symbol_get_frag (left
)->fr_address
7932 <= symbol_get_frag (right
)->fr_address
)
7934 start
= symbol_get_frag (left
);
7935 end
= symbol_get_frag (right
);
7939 start
= symbol_get_frag (right
);
7940 end
= symbol_get_frag (left
);
7943 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7944 walk
= start
->tc_frag_data
.no_transform_end
;
7949 walk
->tc_frag_data
.is_no_transform
= 1;
7950 walk
= walk
->fr_next
;
7952 while (walk
&& walk
->fr_address
< end
->fr_address
);
7954 start
->tc_frag_data
.no_transform_end
= walk
;
7961 /* Re-process all of the fragments looking to convert all of the
7962 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7963 conditional branch or a retw/retw.n, convert this frag to one that
7964 will generate a NOP. In any case close it off with a .fill 0. */
7966 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7969 xtensa_fix_a0_b_retw_frags (void)
7974 /* When this routine is called, all of the subsections are still intact
7975 so we walk over subsections instead of sections. */
7976 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7977 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7981 /* Walk over all of the fragments in a subsection. */
7982 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7984 if (fragP
->fr_type
== rs_machine_dependent
7985 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7987 if (next_instrs_are_b_retw (fragP
))
7989 if (fragP
->tc_frag_data
.is_no_transform
)
7990 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7992 relax_frag_add_nop (fragP
);
8002 next_instrs_are_b_retw (fragS
*fragP
)
8004 xtensa_opcode opcode
;
8006 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
8007 static xtensa_insnbuf insnbuf
= NULL
;
8008 static xtensa_insnbuf slotbuf
= NULL
;
8009 xtensa_isa isa
= xtensa_default_isa
;
8012 bfd_boolean branch_seen
= FALSE
;
8016 insnbuf
= xtensa_insnbuf_alloc (isa
);
8017 slotbuf
= xtensa_insnbuf_alloc (isa
);
8020 if (next_fragP
== NULL
)
8023 /* Check for the conditional branch. */
8024 xtensa_insnbuf_from_chars
8025 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8026 fmt
= xtensa_format_decode (isa
, insnbuf
);
8027 if (fmt
== XTENSA_UNDEFINED
)
8030 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8032 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
8033 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
8035 branch_seen
= (branch_seen
8036 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
8042 offset
+= xtensa_format_length (isa
, fmt
);
8043 if (offset
== next_fragP
->fr_fix
)
8045 next_fragP
= next_non_empty_frag (next_fragP
);
8049 if (next_fragP
== NULL
)
8052 /* Check for the retw/retw.n. */
8053 xtensa_insnbuf_from_chars
8054 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8055 fmt
= xtensa_format_decode (isa
, insnbuf
);
8057 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8058 have no problems. */
8059 if (fmt
== XTENSA_UNDEFINED
8060 || xtensa_format_num_slots (isa
, fmt
) != 1)
8063 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
8064 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
8066 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
8073 /* Re-process all of the fragments looking to convert all of the
8074 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8075 loop end label, convert this frag to one that will generate a NOP.
8076 In any case close it off with a .fill 0. */
8078 static bfd_boolean
next_instr_is_loop_end (fragS
*);
8081 xtensa_fix_b_j_loop_end_frags (void)
8086 /* When this routine is called, all of the subsections are still intact
8087 so we walk over subsections instead of sections. */
8088 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8089 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8093 /* Walk over all of the fragments in a subsection. */
8094 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8096 if (fragP
->fr_type
== rs_machine_dependent
8097 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
8099 if (next_instr_is_loop_end (fragP
))
8101 if (fragP
->tc_frag_data
.is_no_transform
)
8102 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8104 relax_frag_add_nop (fragP
);
8114 next_instr_is_loop_end (fragS
*fragP
)
8116 const fragS
*next_fragP
;
8118 if (next_frag_is_loop_target (fragP
))
8121 next_fragP
= next_non_empty_frag (fragP
);
8122 if (next_fragP
== NULL
)
8125 if (!next_frag_is_loop_target (next_fragP
))
8128 /* If the size is >= 3 then there is more than one instruction here.
8129 The hardware bug will not fire. */
8130 if (next_fragP
->fr_fix
> 3)
8137 /* Re-process all of the fragments looking to convert all of the
8138 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8139 not MY loop's loop end within 12 bytes, add enough nops here to
8140 make it at least 12 bytes away. In any case close it off with a
8143 static offsetT min_bytes_to_other_loop_end
8144 (fragS
*, fragS
*, offsetT
);
8147 xtensa_fix_close_loop_end_frags (void)
8152 /* When this routine is called, all of the subsections are still intact
8153 so we walk over subsections instead of sections. */
8154 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8155 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8159 fragS
*current_target
= NULL
;
8161 /* Walk over all of the fragments in a subsection. */
8162 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8164 if (fragP
->fr_type
== rs_machine_dependent
8165 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8166 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8167 current_target
= symbol_get_frag (fragP
->fr_symbol
);
8170 && fragP
->fr_type
== rs_machine_dependent
8171 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
8174 int bytes_added
= 0;
8176 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8177 /* Max out at 12. */
8178 min_bytes
= min_bytes_to_other_loop_end
8179 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
8181 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
8183 if (fragP
->tc_frag_data
.is_no_transform
)
8184 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8187 while (min_bytes
+ bytes_added
8188 < REQUIRED_LOOP_DIVIDING_BYTES
)
8192 if (fragP
->fr_var
< length
)
8193 as_fatal (_("fr_var %lu < length %d"),
8194 (long) fragP
->fr_var
, length
);
8197 assemble_nop (length
,
8198 fragP
->fr_literal
+ fragP
->fr_fix
);
8199 fragP
->fr_fix
+= length
;
8200 fragP
->fr_var
-= length
;
8202 bytes_added
+= length
;
8208 gas_assert (fragP
->fr_type
!= rs_machine_dependent
8209 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
8215 static offsetT
unrelaxed_frag_min_size (fragS
*);
8218 min_bytes_to_other_loop_end (fragS
*fragP
,
8219 fragS
*current_target
,
8223 fragS
*current_fragP
;
8225 for (current_fragP
= fragP
;
8227 current_fragP
= current_fragP
->fr_next
)
8229 if (current_fragP
->tc_frag_data
.is_loop_target
8230 && current_fragP
!= current_target
)
8233 offset
+= unrelaxed_frag_min_size (current_fragP
);
8235 if (offset
>= max_size
)
8243 unrelaxed_frag_min_size (fragS
*fragP
)
8245 offsetT size
= fragP
->fr_fix
;
8247 /* Add fill size. */
8248 if (fragP
->fr_type
== rs_fill
)
8249 size
+= fragP
->fr_offset
;
8256 unrelaxed_frag_max_size (fragS
*fragP
)
8258 offsetT size
= fragP
->fr_fix
;
8259 switch (fragP
->fr_type
)
8262 /* Empty frags created by the obstack allocation scheme
8263 end up with type 0. */
8268 size
+= fragP
->fr_offset
;
8276 /* No further adjustments needed. */
8278 case rs_machine_dependent
:
8279 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8280 size
+= fragP
->fr_var
;
8283 /* We had darn well better know how big it is. */
8292 /* Re-process all of the fragments looking to convert all
8293 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8296 1) the instruction size count to the loop end label
8297 is too short (<= 2 instructions),
8298 2) loop has a jump or branch in it
8301 1) workaround_all_short_loops is TRUE
8302 2) The generating loop was a 'loopgtz' or 'loopnez'
8303 3) the instruction size count to the loop end label is too short
8305 then convert this frag (and maybe the next one) to generate a NOP.
8306 In any case close it off with a .fill 0. */
8308 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8309 static bfd_boolean
branch_before_loop_end (fragS
*);
8312 xtensa_fix_short_loop_frags (void)
8317 /* When this routine is called, all of the subsections are still intact
8318 so we walk over subsections instead of sections. */
8319 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8320 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8323 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8325 /* Walk over all of the fragments in a subsection. */
8326 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8328 if (fragP
->fr_type
== rs_machine_dependent
8329 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8330 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8333 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8334 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8335 current_opcode
= t_insn
.opcode
;
8336 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8337 current_opcode
) == 1);
8340 if (fragP
->fr_type
== rs_machine_dependent
8341 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8343 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8344 && (branch_before_loop_end (fragP
->fr_next
)
8345 || (workaround_all_short_loops
8346 && current_opcode
!= XTENSA_UNDEFINED
8347 && current_opcode
!= xtensa_loop_opcode
)))
8349 if (fragP
->tc_frag_data
.is_no_transform
)
8350 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8352 relax_frag_add_nop (fragP
);
8361 static int unrelaxed_frag_min_insn_count (fragS
*);
8364 count_insns_to_loop_end (fragS
*base_fragP
,
8365 bfd_boolean count_relax_add
,
8368 fragS
*fragP
= NULL
;
8373 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8375 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8376 if (insn_count
>= max_count
)
8379 if (count_relax_add
)
8381 if (fragP
->fr_type
== rs_machine_dependent
8382 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8384 /* In order to add the appropriate number of
8385 NOPs, we count an instruction for downstream
8388 if (insn_count
>= max_count
)
8398 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8400 xtensa_isa isa
= xtensa_default_isa
;
8401 static xtensa_insnbuf insnbuf
= NULL
;
8405 if (!fragP
->tc_frag_data
.is_insn
)
8409 insnbuf
= xtensa_insnbuf_alloc (isa
);
8411 /* Decode the fixed instructions. */
8412 while (offset
< fragP
->fr_fix
)
8416 xtensa_insnbuf_from_chars
8417 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8418 fmt
= xtensa_format_decode (isa
, insnbuf
);
8420 if (fmt
== XTENSA_UNDEFINED
)
8422 as_fatal (_("undecodable instruction in instruction frag"));
8425 offset
+= xtensa_format_length (isa
, fmt
);
8433 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8436 branch_before_loop_end (fragS
*base_fragP
)
8440 for (fragP
= base_fragP
;
8441 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8442 fragP
= fragP
->fr_next
)
8444 if (unrelaxed_frag_has_b_j (fragP
))
8452 unrelaxed_frag_has_b_j (fragS
*fragP
)
8454 static xtensa_insnbuf insnbuf
= NULL
;
8455 xtensa_isa isa
= xtensa_default_isa
;
8458 if (!fragP
->tc_frag_data
.is_insn
)
8462 insnbuf
= xtensa_insnbuf_alloc (isa
);
8464 /* Decode the fixed instructions. */
8465 while (offset
< fragP
->fr_fix
)
8470 xtensa_insnbuf_from_chars
8471 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8472 fmt
= xtensa_format_decode (isa
, insnbuf
);
8473 if (fmt
== XTENSA_UNDEFINED
)
8476 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8478 xtensa_opcode opcode
=
8479 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8480 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8481 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8484 offset
+= xtensa_format_length (isa
, fmt
);
8490 /* Checks to be made after initial assembly but before relaxation. */
8492 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8493 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8496 xtensa_sanity_check (void)
8498 const char *file_name
;
8503 file_name
= as_where (&line
);
8504 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8505 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8509 /* Walk over all of the fragments in a subsection. */
8510 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8512 if (fragP
->fr_type
== rs_machine_dependent
8513 && fragP
->fr_subtype
== RELAX_SLOTS
8514 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8516 static xtensa_insnbuf insnbuf
= NULL
;
8519 if (fragP
->fr_opcode
!= NULL
)
8522 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8523 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8524 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8526 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8527 t_insn
.opcode
) == 1)
8529 if (is_empty_loop (&t_insn
, fragP
))
8531 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8532 as_bad (_("invalid empty loop"));
8534 if (!is_local_forward_loop (&t_insn
, fragP
))
8536 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8537 as_bad (_("loop target does not follow "
8538 "loop instruction in section"));
8545 new_logical_line (file_name
, line
);
8549 #define LOOP_IMMED_OPN 1
8551 /* Return TRUE if the loop target is the next non-zero fragment. */
8554 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8556 const expressionS
*exp
;
8560 if (insn
->insn_type
!= ITYPE_INSN
)
8563 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8566 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8569 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8571 if (exp
->X_op
!= O_symbol
)
8574 symbolP
= exp
->X_add_symbol
;
8578 if (symbol_get_frag (symbolP
) == NULL
)
8581 if (S_GET_VALUE (symbolP
) != 0)
8584 /* Walk through the zero-size fragments from this one. If we find
8585 the target fragment, then this is a zero-size loop. */
8587 for (next_fragP
= fragP
->fr_next
;
8589 next_fragP
= next_fragP
->fr_next
)
8591 if (next_fragP
== symbol_get_frag (symbolP
))
8593 if (next_fragP
->fr_fix
!= 0)
8601 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8603 const expressionS
*exp
;
8607 if (insn
->insn_type
!= ITYPE_INSN
)
8610 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8613 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8616 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8618 if (exp
->X_op
!= O_symbol
)
8621 symbolP
= exp
->X_add_symbol
;
8625 if (symbol_get_frag (symbolP
) == NULL
)
8628 /* Walk through fragments until we find the target.
8629 If we do not find the target, then this is an invalid loop. */
8631 for (next_fragP
= fragP
->fr_next
;
8633 next_fragP
= next_fragP
->fr_next
)
8635 if (next_fragP
== symbol_get_frag (symbolP
))
8643 #define XTINFO_NAME "Xtensa_Info"
8644 #define XTINFO_NAMESZ 12
8645 #define XTINFO_TYPE 1
8648 xtensa_add_config_info (void)
8654 info_sec
= subseg_new (".xtensa.info", 0);
8655 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8657 data
= XNEWVEC (char, 100);
8658 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8659 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8660 sz
= strlen (data
) + 1;
8662 /* Add enough null terminators to pad to a word boundary. */
8665 while ((sz
& 3) != 0);
8667 /* Follow the standard note section layout:
8668 First write the length of the name string. */
8670 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8672 /* Next comes the length of the "descriptor", i.e., the actual data. */
8674 md_number_to_chars (p
, (valueT
) sz
, 4);
8676 /* Write the note type. */
8678 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8680 /* Write the name field. */
8681 p
= frag_more (XTINFO_NAMESZ
);
8682 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8684 /* Finally, write the descriptor. */
8686 memcpy (p
, data
, sz
);
8692 /* Alignment Functions. */
8695 get_text_align_power (unsigned target_size
)
8697 if (target_size
<= 4)
8700 if (target_size
<= 8)
8703 if (target_size
<= 16)
8706 if (target_size
<= 32)
8709 if (target_size
<= 64)
8712 if (target_size
<= 128)
8715 if (target_size
<= 256)
8718 if (target_size
<= 512)
8721 if (target_size
<= 1024)
8730 get_text_align_max_fill_size (int align_pow
,
8731 bfd_boolean use_nops
,
8732 bfd_boolean use_no_density
)
8735 return (1 << align_pow
);
8737 return 3 * (1 << align_pow
);
8739 return 1 + (1 << align_pow
);
8743 /* Calculate the minimum bytes of fill needed at "address" to align a
8744 target instruction of size "target_size" so that it does not cross a
8745 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8746 the fill can be an arbitrary number of bytes. Otherwise, the space must
8747 be filled by NOP instructions. */
8750 get_text_align_fill_size (addressT address
,
8753 bfd_boolean use_nops
,
8754 bfd_boolean use_no_density
)
8756 addressT alignment
, fill
, fill_limit
, fill_step
;
8757 bfd_boolean skip_one
= FALSE
;
8759 alignment
= (1 << align_pow
);
8760 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8764 fill_limit
= alignment
;
8767 else if (!use_no_density
)
8769 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8770 fill_limit
= alignment
* 2;
8776 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8777 fill_limit
= alignment
* 3;
8781 /* Try all fill sizes until finding one that works. */
8782 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8784 if (skip_one
&& fill
== 1)
8786 if ((address
+ fill
) >> align_pow
8787 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8796 branch_align_power (segT sec
)
8798 /* If the Xtensa processor has a fetch width of X, and
8799 the section is aligned to at least that boundary, then a branch
8800 target need only fit within that aligned block of memory to avoid
8801 a stall. Otherwise, try to fit branch targets within 4-byte
8802 aligned blocks (which may be insufficient, e.g., if the section
8803 has no alignment, but it's good enough). */
8804 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
8805 int sec_align
= get_recorded_alignment (sec
);
8807 if (sec_align
>= fetch_align
)
8814 /* This will assert if it is not possible. */
8817 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8823 gas_assert (fill_size
% 3 == 0);
8824 return (fill_size
/ 3);
8827 gas_assert (fill_size
!= 1); /* Bad argument. */
8829 while (fill_size
> 1)
8832 if (fill_size
== 2 || fill_size
== 4)
8834 fill_size
-= insn_size
;
8837 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8843 get_text_align_nth_nop_size (offsetT fill_size
,
8845 bfd_boolean use_no_density
)
8852 gas_assert (fill_size
!= 1); /* Bad argument. */
8854 while (fill_size
> 1)
8857 if (fill_size
== 2 || fill_size
== 4)
8859 fill_size
-= insn_size
;
8869 /* For the given fragment, find the appropriate address
8870 for it to begin at if we are using NOPs to align it. */
8873 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8875 /* The rule is: get next fragment's FIRST instruction. Find
8876 the smallest number of bytes that need to be added to
8877 ensure that the next fragment's FIRST instruction will fit
8880 E.G., 2 bytes : 0, 1, 2 mod 4
8883 If the FIRST instruction MIGHT be relaxed,
8884 assume that it will become a 3-byte instruction.
8886 Note again here that LOOP instructions are not bundleable,
8887 and this relaxation only applies to LOOP opcodes. */
8890 int first_insn_size
;
8892 addressT pre_opcode_bytes
;
8895 xtensa_opcode opcode
;
8896 bfd_boolean is_loop
;
8898 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8899 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8901 /* Find the loop frag. */
8902 first_insn
= next_non_empty_frag (fragP
);
8903 /* Now find the first insn frag. */
8904 first_insn
= next_non_empty_frag (first_insn
);
8906 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8907 gas_assert (is_loop
);
8908 loop_insn_size
= xg_get_single_size (opcode
);
8910 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8911 pre_opcode_bytes
+= loop_insn_size
;
8913 /* For loops, the alignment depends on the size of the
8914 instruction following the loop, not the LOOP instruction. */
8916 if (first_insn
== NULL
)
8917 first_insn_size
= xtensa_fetch_width
;
8919 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8921 /* If it was 8, then we'll need a larger alignment for the section. */
8922 align_power
= get_text_align_power (first_insn_size
);
8923 record_alignment (now_seg
, align_power
);
8925 fill_size
= get_text_align_fill_size
8926 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8927 fragP
->tc_frag_data
.is_no_density
);
8929 return address
+ fill_size
;
8933 /* 3 mechanisms for relaxing an alignment:
8935 Align to a power of 2.
8936 Align so the next fragment's instruction does not cross a word boundary.
8937 Align the current instruction so that if the next instruction
8938 were 3 bytes, it would not cross a word boundary.
8942 zeros - This is easy; always insert zeros.
8943 nops - 3-byte and 2-byte instructions
8947 >=5 : 3-byte instruction + fn (n-3)
8948 widening - widen previous instructions. */
8951 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8953 addressT target_address
, loop_insn_offset
;
8955 xtensa_opcode loop_opcode
;
8956 bfd_boolean is_loop
;
8959 offsetT branch_align
;
8962 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8963 switch (fragP
->fr_subtype
)
8965 case RELAX_DESIRE_ALIGN
:
8966 target_size
= next_frag_format_size (fragP
);
8967 if (target_size
== XTENSA_UNDEFINED
)
8969 align_power
= branch_align_power (now_seg
);
8970 branch_align
= 1 << align_power
;
8971 /* Don't count on the section alignment being as large as the target. */
8972 if (target_size
> branch_align
)
8973 target_size
= branch_align
;
8974 opt_diff
= get_text_align_fill_size (address
, align_power
,
8975 target_size
, FALSE
, FALSE
);
8977 *max_diff
= (opt_diff
+ branch_align
8978 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8979 gas_assert (*max_diff
>= opt_diff
);
8982 case RELAX_ALIGN_NEXT_OPCODE
:
8983 /* The next non-empty frag after this one holds the LOOP instruction
8984 that needs to be aligned. The required alignment depends on the
8985 size of the next non-empty frag after the loop frag, i.e., the
8986 first instruction in the loop. */
8987 loop_frag
= next_non_empty_frag (fragP
);
8988 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8989 loop_insn_offset
= 0;
8990 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8991 gas_assert (is_loop
);
8993 /* If the loop has been expanded then the LOOP instruction
8994 could be at an offset from this fragment. */
8995 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8996 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8998 /* In an ideal world, which is what we are shooting for here,
8999 we wouldn't need to use any NOPs immediately prior to the
9000 LOOP instruction. If this approach fails, relax_frag_loop_align
9001 will call get_noop_aligned_address. */
9003 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
9004 align_power
= get_text_align_power (target_size
);
9005 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
9006 target_size
, FALSE
, FALSE
);
9008 *max_diff
= xtensa_fetch_width
9009 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
9010 - target_size
+ opt_diff
;
9011 gas_assert (*max_diff
>= opt_diff
);
9022 /* md_relax_frag Hook and Helper Functions. */
9024 static long relax_frag_loop_align (fragS
*, long);
9025 static long relax_frag_for_align (fragS
*, long);
9026 static long relax_frag_immed
9027 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
9029 typedef struct cached_fixup cached_fixupS
;
9038 typedef struct fixup_cache fixup_cacheS
;
9041 cached_fixupS
*fixups
;
9049 static int fixup_order (const void *a
, const void *b
)
9051 const cached_fixupS
*pa
= a
;
9052 const cached_fixupS
*pb
= b
;
9054 if (pa
->addr
== pb
->addr
)
9056 if (pa
->target
== pb
->target
)
9058 if (pa
->fixP
->fx_r_type
== pb
->fixP
->fx_r_type
)
9060 return pa
->fixP
->fx_r_type
< pb
->fixP
->fx_r_type
? -1 : 1;
9062 return pa
->target
- pb
->target
;
9064 return pa
->addr
- pb
->addr
;
9067 static bfd_boolean
xtensa_make_cached_fixup (cached_fixupS
*o
, fixS
*fixP
)
9069 xtensa_isa isa
= xtensa_default_isa
;
9070 int addr
= fixP
->fx_frag
->fr_address
;
9073 symbolS
*s
= fixP
->fx_addsy
;
9076 xtensa_opcode opcode
;
9078 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
9079 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
9081 target
= S_GET_VALUE (s
);
9082 delta
= target
- addr
;
9084 if (abs(delta
) < J_RANGE
/ 2)
9087 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
9088 (unsigned char *) fixP
->fx_frag
->fr_literal
+
9090 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
9091 gas_assert (fmt
!= XTENSA_UNDEFINED
);
9092 slot
= fixP
->tc_fix_data
.slot
;
9093 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
9094 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
9095 if (opcode
!= xtensa_j_opcode
)
9106 static void xtensa_realloc_fixup_cache (fixup_cacheS
*cache
, unsigned add
)
9108 if (cache
->n_fixups
+ add
> cache
->n_max
)
9110 cache
->n_max
= (cache
->n_fixups
+ add
) * 2;
9111 cache
->fixups
= XRESIZEVEC (cached_fixupS
, cache
->fixups
, cache
->n_max
);
9115 static void xtensa_cache_relaxable_fixups (fixup_cacheS
*cache
,
9116 segment_info_type
*seginfo
)
9120 cache
->n_fixups
= 0;
9122 for (fixP
= seginfo
->fix_root
; fixP
; fixP
= fixP
->fx_next
)
9124 xtensa_realloc_fixup_cache (cache
, 1);
9126 if (xtensa_make_cached_fixup (cache
->fixups
+ cache
->n_fixups
, fixP
))
9129 qsort (cache
->fixups
, cache
->n_fixups
, sizeof (*cache
->fixups
), fixup_order
);
9132 static unsigned xtensa_find_first_cached_fixup (const fixup_cacheS
*cache
,
9136 unsigned b
= cache
->n_fixups
;
9140 unsigned c
= (a
+ b
) / 2;
9142 if (cache
->fixups
[c
].addr
< addr
)
9150 static void xtensa_delete_cached_fixup (fixup_cacheS
*cache
, unsigned i
)
9152 memmove (cache
->fixups
+ i
, cache
->fixups
+ i
+ 1,
9153 (cache
->n_fixups
- i
- 1) * sizeof (*cache
->fixups
));
9157 static bfd_boolean
xtensa_add_cached_fixup (fixup_cacheS
*cache
, fixS
*fixP
)
9162 if (!xtensa_make_cached_fixup (&o
, fixP
))
9164 xtensa_realloc_fixup_cache (cache
, 1);
9165 i
= xtensa_find_first_cached_fixup (cache
, o
.addr
);
9166 if (i
< cache
->n_fixups
)
9169 memmove (cache
->fixups
+ i
+ 1, cache
->fixups
+ i
,
9170 (cache
->n_fixups
- i
) * sizeof (*cache
->fixups
));
9172 cache
->fixups
[i
] = o
;
9177 /* Return the number of bytes added to this fragment, given that the
9178 input has been stretched already by "stretch". */
9181 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
9183 xtensa_isa isa
= xtensa_default_isa
;
9184 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
9185 long new_stretch
= 0;
9186 const char *file_name
;
9189 static xtensa_insnbuf vbuf
= NULL
;
9190 int slot
, num_slots
;
9193 file_name
= as_where (&line
);
9194 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
9196 fragP
->tc_frag_data
.unreported_expansion
= 0;
9198 switch (fragP
->fr_subtype
)
9200 case RELAX_ALIGN_NEXT_OPCODE
:
9201 /* Always convert. */
9202 if (fragP
->tc_frag_data
.relax_seen
)
9203 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
9206 case RELAX_LOOP_END
:
9210 case RELAX_LOOP_END_ADD_NOP
:
9211 /* Add a NOP and switch to .fill 0. */
9212 new_stretch
= relax_frag_add_nop (fragP
);
9216 case RELAX_DESIRE_ALIGN
:
9217 /* Do nothing. The narrowing before this frag will either align
9222 case RELAX_LITERAL_FINAL
:
9225 case RELAX_LITERAL_NR
:
9227 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
9228 gas_assert (unreported
== lit_size
);
9229 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
9230 fragP
->fr_var
-= lit_size
;
9231 fragP
->fr_fix
+= lit_size
;
9237 vbuf
= xtensa_insnbuf_alloc (isa
);
9239 xtensa_insnbuf_from_chars
9240 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
9241 fmt
= xtensa_format_decode (isa
, vbuf
);
9242 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9244 for (slot
= 0; slot
< num_slots
; slot
++)
9246 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
9249 if (fragP
->tc_frag_data
.relax_seen
)
9250 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9254 case RELAX_IMMED_STEP1
:
9255 case RELAX_IMMED_STEP2
:
9256 case RELAX_IMMED_STEP3
:
9257 /* Place the immediate. */
9258 new_stretch
+= relax_frag_immed
9259 (now_seg
, fragP
, stretch
,
9260 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9261 fmt
, slot
, stretched_p
, FALSE
);
9265 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9271 case RELAX_LITERAL_POOL_BEGIN
:
9272 if (fragP
->fr_var
!= 0)
9274 /* We have a converted "candidate" literal pool;
9275 assemble a jump around it. */
9277 if (!litpool_slotbuf
)
9279 litpool_buf
= xtensa_insnbuf_alloc (isa
);
9280 litpool_slotbuf
= xtensa_insnbuf_alloc (isa
);
9283 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9284 fragP
->tc_frag_data
.is_insn
= TRUE
;
9286 insn
.insn_type
= ITYPE_INSN
;
9287 insn
.opcode
= xtensa_j_opcode
;
9289 set_expr_symbol_offset (&insn
.tok
[0], fragP
->fr_symbol
,
9291 fmt
= xg_get_single_format (xtensa_j_opcode
);
9292 tinsn_to_slotbuf (fmt
, 0, &insn
, litpool_slotbuf
);
9293 xtensa_format_set_slot (isa
, fmt
, 0, litpool_buf
, litpool_slotbuf
);
9294 xtensa_insnbuf_to_chars (isa
, litpool_buf
,
9295 (unsigned char *)fragP
->fr_literal
+
9300 fix_new (fragP
, 0, 3, fragP
->fr_symbol
, 0, TRUE
,
9301 BFD_RELOC_XTENSA_SLOT0_OP
);
9305 case RELAX_LITERAL_POOL_END
:
9306 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
9307 case RELAX_MAYBE_UNREACHABLE
:
9308 case RELAX_MAYBE_DESIRE_ALIGN
:
9309 /* No relaxation required. */
9312 case RELAX_FILL_NOP
:
9313 case RELAX_UNREACHABLE
:
9314 if (fragP
->tc_frag_data
.relax_seen
)
9315 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9318 case RELAX_TRAMPOLINE
:
9319 if (fragP
->tc_frag_data
.relax_seen
)
9321 static fixup_cacheS fixup_cache
;
9322 segment_info_type
*seginfo
= seg_info (now_seg
);
9323 int trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9324 int searchaddr
= trampaddr
< J_RANGE
? 0 : trampaddr
- J_RANGE
;
9327 if (now_seg
!= fixup_cache
.seg
||
9328 fragP
== fixup_cache
.first_frag
||
9329 fixup_cache
.first_frag
== NULL
)
9331 xtensa_cache_relaxable_fixups (&fixup_cache
, seginfo
);
9332 fixup_cache
.seg
= now_seg
;
9333 fixup_cache
.first_frag
= fragP
;
9336 /* Scan for jumps that will not reach. */
9337 for (i
= xtensa_find_first_cached_fixup (&fixup_cache
, searchaddr
);
9338 i
< fixup_cache
.n_fixups
; ++i
)
9341 fixS
*fixP
= fixup_cache
.fixups
[i
].fixP
;
9342 int target
= fixup_cache
.fixups
[i
].target
;
9343 int addr
= fixup_cache
.fixups
[i
].addr
;
9344 int delta
= fixup_cache
.fixups
[i
].delta
+ stretch
;
9346 trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9348 if (addr
+ J_RANGE
< trampaddr
)
9350 if (addr
> trampaddr
+ J_RANGE
)
9352 if (abs (delta
) < J_RANGE
)
9355 slot
= fixP
->tc_fix_data
.slot
;
9357 if (delta
> J_RANGE
|| delta
< -1 * J_RANGE
)
9358 { /* Found an out-of-range jump; scan the list of trampolines for the best match. */
9359 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9360 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9361 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9362 int lower
= (target
< addr
) ? target
: addr
;
9363 int upper
= (target
> addr
) ? target
: addr
;
9364 int midpoint
= lower
+ (upper
- lower
) / 2;
9366 if ((upper
- lower
) > 2 * J_RANGE
)
9368 /* One trampoline won't suffice; we need multiple jumps.
9369 Jump to the trampoline that's farthest, but still in
9370 range relative to the original "j" instruction. */
9371 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9373 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9374 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0 ;
9379 if (this_addr
- addr
< J_RANGE
)
9384 /* Backward jump. */
9385 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9392 struct trampoline_frag
*best_tf
= NULL
;
9395 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9397 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9398 int this_delta
= abs (this_addr
- midpoint
);
9400 if (!best_tf
|| this_delta
< best_delta
)
9403 best_delta
= this_delta
;
9408 if (tf
->fragP
== fragP
)
9410 if (abs (addr
- trampaddr
) < J_RANGE
)
9411 { /* The trampoline is in range of original; fix it! */
9416 fragS
*fP
; /* The out-of-range jump. */
9418 new_stretch
+= init_trampoline_frag (tf
);
9419 offset
= fragP
->fr_fix
; /* Where to assemble the j insn. */
9420 lsym
= fragP
->fr_symbol
;
9422 /* Assemble a jump to the target label here. */
9424 insn
.insn_type
= ITYPE_INSN
;
9425 insn
.opcode
= xtensa_j_opcode
;
9427 set_expr_symbol_offset (&insn
.tok
[0], lsym
, offset
);
9428 fmt
= xg_get_single_format (xtensa_j_opcode
);
9429 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9430 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9431 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fragP
->fr_literal
+ offset
, 3);
9434 /* Add a fix-up for the original j insn. */
9435 newfixP
= fix_new (fP
, fixP
->fx_where
, fixP
->fx_size
, lsym
, fragP
->fr_fix
- 3, TRUE
, fixP
->fx_r_type
);
9436 newfixP
->fx_no_overflow
= 1;
9437 newfixP
->tc_fix_data
.X_add_symbol
= lsym
;
9438 newfixP
->tc_fix_data
.X_add_number
= offset
;
9439 newfixP
->tc_fix_data
.slot
= slot
;
9441 xtensa_delete_cached_fixup (&fixup_cache
, i
);
9442 xtensa_add_cached_fixup (&fixup_cache
, newfixP
);
9444 /* Move the fix-up from the original j insn to this one. */
9445 fixP
->fx_frag
= fragP
;
9446 fixP
->fx_where
= fragP
->fr_fix
- 3;
9448 fixP
->tc_fix_data
.slot
= 0;
9449 fixP
->fx_r_type
= BFD_RELOC_XTENSA_SLOT0_OP
;
9451 xtensa_add_cached_fixup (&fixup_cache
, fixP
);
9453 /* re-do current fixup */
9456 /* Adjust the jump around this trampoline (if present). */
9457 if (tf
->fixP
!= NULL
)
9459 tf
->fixP
->fx_offset
+= 3;
9462 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9463 /* Do we have room for more? */
9464 if (fragP
->fr_var
< 3)
9465 { /* No, convert to fill. */
9467 fragP
->fr_subtype
= 0;
9468 /* Remove from the trampoline_list. */
9469 prev
->next
= tf
->next
;
9470 if (fragP
== fixup_cache
.first_frag
)
9471 fixup_cache
.first_frag
= NULL
;
9482 as_bad (_("bad relaxation state"));
9485 /* Tell gas we need another relaxation pass. */
9486 if (! fragP
->tc_frag_data
.relax_seen
)
9488 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9492 new_logical_line (file_name
, line
);
9498 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9500 addressT old_address
, old_next_address
, old_size
;
9501 addressT new_address
, new_next_address
, new_size
;
9504 /* All the frags with relax_frag_for_alignment prior to this one in the
9505 section have been done, hopefully eliminating the need for a NOP here.
9506 But, this will put it in if necessary. */
9508 /* Calculate the old address of this fragment and the next fragment. */
9509 old_address
= fragP
->fr_address
- stretch
;
9510 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9511 fragP
->tc_frag_data
.text_expansion
[0]);
9512 old_size
= old_next_address
- old_address
;
9514 /* Calculate the new address of this fragment and the next fragment. */
9515 new_address
= fragP
->fr_address
;
9517 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9518 new_size
= new_next_address
- new_address
;
9520 growth
= new_size
- old_size
;
9522 /* Fix up the text_expansion field and return the new growth. */
9523 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9528 /* Add a NOP instruction. */
9531 relax_frag_add_nop (fragS
*fragP
)
9533 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9534 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9535 assemble_nop (length
, nop_buf
);
9536 fragP
->tc_frag_data
.is_insn
= TRUE
;
9538 if (fragP
->fr_var
< length
)
9540 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9544 fragP
->fr_fix
+= length
;
9545 fragP
->fr_var
-= length
;
9550 static long future_alignment_required (fragS
*, long);
9553 relax_frag_for_align (fragS
*fragP
, long stretch
)
9555 /* Overview of the relaxation procedure for alignment:
9556 We can widen with NOPs or by widening instructions or by filling
9557 bytes after jump instructions. Find the opportune places and widen
9558 them if necessary. */
9563 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9564 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9565 || (fragP
->fr_subtype
== RELAX_SLOTS
9566 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9568 stretch_me
= future_alignment_required (fragP
, stretch
);
9569 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9575 /* We expanded on a previous pass. Can we shrink now? */
9576 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9577 if (shrink
<= stretch
&& stretch
> 0)
9579 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9585 /* Below here, diff > 0. */
9586 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9592 /* Return the address of the next frag that should be aligned.
9594 By "address" we mean the address it _would_ be at if there
9595 is no action taken to align it between here and the target frag.
9596 In other words, if no narrows and no fill nops are used between
9597 here and the frag to align, _even_if_ some of the frags we use
9598 to align targets have already expanded on a previous relaxation
9601 Also, count each frag that may be used to help align the target.
9603 Return 0 if there are no frags left in the chain that need to be
9607 find_address_of_next_align_frag (fragS
**fragPP
,
9611 bfd_boolean
*paddable
)
9613 fragS
*fragP
= *fragPP
;
9614 addressT address
= fragP
->fr_address
;
9616 /* Do not reset the counts to 0. */
9620 /* Limit this to a small search. */
9621 if (*widens
>= (int) xtensa_fetch_width
)
9626 address
+= fragP
->fr_fix
;
9628 if (fragP
->fr_type
== rs_fill
)
9629 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9630 else if (fragP
->fr_type
== rs_machine_dependent
)
9632 switch (fragP
->fr_subtype
)
9634 case RELAX_UNREACHABLE
:
9638 case RELAX_FILL_NOP
:
9640 if (!fragP
->tc_frag_data
.is_no_density
)
9645 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9650 address
+= total_frag_text_expansion (fragP
);
9654 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9657 case RELAX_ALIGN_NEXT_OPCODE
:
9658 case RELAX_DESIRE_ALIGN
:
9662 case RELAX_MAYBE_UNREACHABLE
:
9663 case RELAX_MAYBE_DESIRE_ALIGN
:
9668 /* Just punt if we don't know the type. */
9675 /* Just punt if we don't know the type. */
9679 fragP
= fragP
->fr_next
;
9687 static long bytes_to_stretch (fragS
*, int, int, int, int);
9690 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9692 fragS
*this_frag
= fragP
;
9696 int narrow_nops
= 0;
9697 bfd_boolean paddable
= FALSE
;
9698 offsetT local_opt_diff
;
9701 int stretch_amount
= 0;
9702 int local_stretch_amount
;
9703 int global_stretch_amount
;
9705 address
= find_address_of_next_align_frag
9706 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9710 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9711 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9713 frag_wane (this_frag
);
9717 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9718 opt_diff
= local_opt_diff
;
9719 gas_assert (opt_diff
>= 0);
9720 gas_assert (max_diff
>= opt_diff
);
9725 fragP
= fragP
->fr_next
;
9727 while (fragP
&& opt_diff
< max_diff
&& address
)
9729 /* We only use these to determine if we can exit early
9730 because there will be plenty of ways to align future
9732 int glob_widens
= 0;
9735 bfd_boolean glob_pad
= 0;
9736 address
= find_address_of_next_align_frag
9737 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9738 /* If there is a padable portion, then skip. */
9739 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9744 offsetT next_m_diff
;
9745 offsetT next_o_diff
;
9747 /* Downrange frags haven't had stretch added to them yet. */
9750 /* The address also includes any text expansion from this
9751 frag in a previous pass, but we don't want that. */
9752 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9754 /* Assume we are going to move at least opt_diff. In
9755 reality, we might not be able to, but assuming that
9756 we will helps catch cases where moving opt_diff pushes
9757 the next target from aligned to unaligned. */
9758 address
+= opt_diff
;
9760 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9762 /* Now cleanup for the adjustments to address. */
9763 next_o_diff
+= opt_diff
;
9764 next_m_diff
+= opt_diff
;
9765 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9766 opt_diff
= next_o_diff
;
9767 if (next_m_diff
< max_diff
)
9768 max_diff
= next_m_diff
;
9769 fragP
= fragP
->fr_next
;
9773 /* If there are enough wideners in between, do it. */
9776 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9778 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9783 local_stretch_amount
9784 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9785 num_widens
, local_opt_diff
);
9786 global_stretch_amount
9787 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9788 num_widens
, opt_diff
);
9789 /* If the condition below is true, then the frag couldn't
9790 stretch the correct amount for the global case, so we just
9791 optimize locally. We'll rely on the subsequent frags to get
9792 the correct alignment in the global case. */
9793 if (global_stretch_amount
< local_stretch_amount
)
9794 stretch_amount
= local_stretch_amount
;
9796 stretch_amount
= global_stretch_amount
;
9798 if (this_frag
->fr_subtype
== RELAX_SLOTS
9799 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9800 gas_assert (stretch_amount
<= 1);
9801 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9803 if (this_frag
->tc_frag_data
.is_no_density
)
9804 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9806 gas_assert (stretch_amount
<= 3);
9809 return stretch_amount
;
9813 /* The idea: widen everything you can to get a target or loop aligned,
9814 then start using NOPs.
9816 wide_nops = the number of wide NOPs available for aligning
9817 narrow_nops = the number of narrow NOPs available for aligning
9818 (a subset of wide_nops)
9819 widens = the number of narrow instructions that should be widened
9824 bytes_to_stretch (fragS
*this_frag
,
9833 int bytes_short
= desired_diff
- num_widens
;
9835 gas_assert (desired_diff
>= 0
9836 && desired_diff
< (signed) xtensa_fetch_width
);
9837 if (desired_diff
== 0)
9840 gas_assert (wide_nops
> 0 || num_widens
> 0);
9842 /* Always prefer widening to NOP-filling. */
9843 if (bytes_short
< 0)
9845 /* There are enough RELAX_NARROW frags after this one
9846 to align the target without widening this frag in any way. */
9850 if (bytes_short
== 0)
9852 /* Widen every narrow between here and the align target
9853 and the align target will be properly aligned. */
9854 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9860 /* From here we will need at least one NOP to get an alignment.
9861 However, we may not be able to align at all, in which case,
9863 nops_needed
= desired_diff
/ 3;
9865 /* If there aren't enough nops, don't widen. */
9866 if (nops_needed
> wide_nops
)
9869 /* First try it with all wide nops. */
9870 nop_bytes
= nops_needed
* 3;
9871 extra_bytes
= desired_diff
- nop_bytes
;
9873 if (nop_bytes
+ num_widens
>= desired_diff
)
9875 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9877 else if (num_widens
== extra_bytes
)
9882 /* Add a narrow nop. */
9886 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
9889 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
9891 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9892 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9893 else if (num_widens
== extra_bytes
)
9898 /* Replace a wide nop with a narrow nop--we can get here if
9899 extra_bytes was negative in the previous conditional. */
9900 if (narrow_nops
== 1)
9904 if (nop_bytes
+ num_widens
>= desired_diff
)
9906 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9907 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9908 else if (num_widens
== extra_bytes
)
9913 /* If we can't satisfy any of the above cases, then we can't align
9914 using padding or fill nops. */
9919 static struct trampoline_frag
*
9920 search_trampolines (TInsn
*tinsn
, fragS
*fragP
, bfd_boolean unreachable_only
)
9922 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9923 struct trampoline_frag
*tf
= (ts
) ? ts
->trampoline_list
.next
: NULL
;
9924 struct trampoline_frag
*best_tf
= NULL
;
9927 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
9928 offsetT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
9929 offsetT addr
= fragP
->fr_address
;
9930 offsetT lower
= (addr
< target
) ? addr
: target
;
9931 offsetT upper
= (addr
> target
) ? addr
: target
;
9932 int delta
= upper
- lower
;
9933 offsetT midpoint
= lower
+ delta
/ 2;
9934 int this_delta
= -1;
9937 if (delta
> 2 * J_RANGE
)
9939 /* One trampoline won't do; we need multiple.
9940 Choose the farthest trampoline that's still in range of the original
9941 and let a later pass finish the job. */
9942 for ( ; tf
; tf
= tf
->next
)
9944 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0;
9946 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9950 if (this_addr
- addr
< J_RANGE
)
9955 /* Backward jump. */
9956 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9960 if (abs (addr
- this_addr
) < J_RANGE
)
9965 for ( ; tf
; tf
= tf
->next
)
9967 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9968 this_delta
= abs (this_addr
- midpoint
);
9969 if (unreachable_only
&& tf
->needs_jump_around
)
9971 if (!best_tf
|| this_delta
< best_delta
)
9974 best_delta
= this_delta
;
9975 best_addr
= this_addr
;
9980 best_delta
< J_RANGE
&&
9981 abs(best_addr
- lower
) < J_RANGE
&&
9982 abs(best_addr
- upper
) < J_RANGE
)
9985 return NULL
; /* No suitable trampoline found. */
9989 static struct trampoline_frag
*
9990 get_best_trampoline (TInsn
*tinsn
, fragS
*fragP
)
9992 struct trampoline_frag
*tf
= NULL
;
9994 tf
= search_trampolines (tinsn
, fragP
, TRUE
); /* Try unreachable first. */
9997 tf
= search_trampolines (tinsn
, fragP
, FALSE
); /* Try ones needing a jump-around, too. */
10004 check_and_update_trampolines (void)
10006 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
10007 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
10008 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
10010 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
10012 if (tf
->fragP
->fr_var
< 3)
10014 frag_wane (tf
->fragP
);
10015 prev
->next
= tf
->next
;
10023 init_trampoline_frag (struct trampoline_frag
*trampP
)
10025 fragS
*fp
= trampP
->fragP
;
10028 if (fp
->fr_fix
== 0)
10031 char label
[10 + 2 * sizeof(fp
)];
10032 sprintf (label
, ".L0_TR_%p", fp
);
10034 lsym
= (symbolS
*)local_symbol_make (label
, now_seg
, 0, fp
);
10035 fp
->fr_symbol
= lsym
;
10036 if (trampP
->needs_jump_around
)
10038 /* Add a jump around this block of jumps, in case
10039 control flows into this block. */
10043 xtensa_isa isa
= xtensa_default_isa
;
10045 fp
->tc_frag_data
.is_insn
= 1;
10046 /* Assemble a jump insn. */
10047 tinsn_init (&insn
);
10048 insn
.insn_type
= ITYPE_INSN
;
10049 insn
.opcode
= xtensa_j_opcode
;
10051 set_expr_symbol_offset (&insn
.tok
[0], lsym
, 3);
10052 fmt
= xg_get_single_format (xtensa_j_opcode
);
10053 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10054 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10055 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fp
->fr_literal
, 3);
10059 fixP
= fix_new (fp
, 0, 3, lsym
, 3, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
10060 trampP
->fixP
= fixP
;
10068 add_jump_to_trampoline (struct trampoline_frag
*trampP
, fragS
*origfrag
)
10070 fragS
*tramp
= trampP
->fragP
;
10072 int offset
= tramp
->fr_fix
; /* Where to assemble the j insn. */
10078 xtensa_isa isa
= xtensa_default_isa
;
10082 for (i
= 0; i
< MAX_SLOTS
; ++i
)
10083 if (origfrag
->tc_frag_data
.slot_symbols
[i
])
10085 gas_assert (slot
== -1);
10089 gas_assert (slot
>= 0 && slot
< MAX_SLOTS
);
10091 lsym
= tramp
->fr_symbol
;
10092 /* Assemble a jump to the target label in the trampoline frag. */
10093 tsym
= origfrag
->tc_frag_data
.slot_symbols
[slot
];
10094 toffset
= origfrag
-> tc_frag_data
.slot_offsets
[slot
];
10095 tinsn_init (&insn
);
10096 insn
.insn_type
= ITYPE_INSN
;
10097 insn
.opcode
= xtensa_j_opcode
;
10099 set_expr_symbol_offset (&insn
.tok
[0], tsym
, toffset
);
10100 fmt
= xg_get_single_format (xtensa_j_opcode
);
10101 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10102 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10103 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)tramp
->fr_literal
+ offset
, 3);
10104 tramp
->fr_fix
+= 3;
10105 tramp
->fr_var
-= 3;
10107 /* add a fix-up for the trampoline jump. */
10108 fixP
= fix_new (tramp
, tramp
->fr_fix
- 3, 3, tsym
, toffset
, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
10109 /* Modify the jump at the start of this trampoline to point past the newly-added jump. */
10110 fixP
= trampP
->fixP
;
10112 fixP
->fx_offset
+= 3;
10113 /* Modify the original j to point here. */
10114 origfrag
->tc_frag_data
.slot_symbols
[slot
] = lsym
;
10115 origfrag
->tc_frag_data
.slot_offsets
[slot
] = tramp
->fr_fix
- 3;
10116 /* If trampoline is full, remove it from the list. */
10117 check_and_update_trampolines ();
10124 relax_frag_immed (segT segP
,
10131 bfd_boolean estimate_only
)
10135 bfd_boolean negatable_branch
= FALSE
;
10136 bfd_boolean branch_jmp_to_next
= FALSE
;
10137 bfd_boolean from_wide_insn
= FALSE
;
10138 xtensa_isa isa
= xtensa_default_isa
;
10140 offsetT frag_offset
;
10142 int num_text_bytes
, num_literal_bytes
;
10143 int literal_diff
, total_text_diff
, this_text_diff
;
10145 gas_assert (fragP
->fr_opcode
!= NULL
);
10147 xg_clear_vinsn (&cur_vinsn
);
10148 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
10149 if (cur_vinsn
.num_slots
> 1)
10150 from_wide_insn
= TRUE
;
10152 tinsn
= cur_vinsn
.slots
[slot
];
10153 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
10155 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
10158 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10159 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
10161 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
10163 old_size
= xtensa_format_length (isa
, fmt
);
10165 /* Special case: replace a branch to the next instruction with a NOP.
10166 This is required to work around a hardware bug in T1040.0 and also
10167 serves as an optimization. */
10169 if (branch_jmp_to_next
10170 && ((old_size
== 2) || (old_size
== 3))
10171 && !next_frag_is_loop_target (fragP
))
10174 /* Here is the fun stuff: Get the immediate field from this
10175 instruction. If it fits, we are done. If not, find the next
10176 instruction sequence that fits. */
10178 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10179 istack_init (&istack
);
10180 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
10181 min_steps
, stretch
);
10182 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10184 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
10186 /* Figure out the number of bytes needed. */
10187 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10189 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10190 num_text_bytes
= get_num_stack_text_bytes (&istack
);
10192 if (from_wide_insn
)
10195 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
10198 num_text_bytes
+= old_size
;
10199 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
10200 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
10203 /* The first instruction in the relaxed sequence will go after
10204 the current wide instruction, and thus its symbolic immediates
10207 istack_init (&istack
);
10208 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
10209 frag_offset
+ old_size
,
10210 min_steps
, stretch
+ old_size
);
10211 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10213 fragP
->tc_frag_data
.slot_subtypes
[slot
]
10214 = (int) RELAX_IMMED
+ num_steps
;
10216 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10218 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10220 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
10224 total_text_diff
= num_text_bytes
- old_size
;
10225 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
10227 /* It MUST get larger. If not, we could get an infinite loop. */
10228 gas_assert (num_text_bytes
>= 0);
10229 gas_assert (literal_diff
>= 0);
10230 gas_assert (total_text_diff
>= 0);
10232 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
10233 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
10234 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
10235 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
10237 /* Find the associated expandable literal for this. */
10238 if (literal_diff
!= 0)
10240 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
10243 gas_assert (literal_diff
== 4);
10244 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
10246 /* We expect that the literal section state has NOT been
10248 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
10249 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
10250 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
10252 /* We need to mark this section for another iteration
10258 if (negatable_branch
&& istack
.ninsn
> 1)
10259 update_next_frag_state (fragP
);
10261 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
10262 if (istack
.ninsn
> 2 &&
10263 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
10264 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
10265 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
10267 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
10269 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
, total_text_diff
))
10271 struct trampoline_frag
*tf
= get_best_trampoline (jinsn
, fragP
);
10275 this_text_diff
+= init_trampoline_frag (tf
);
10276 this_text_diff
+= add_jump_to_trampoline (tf
, fragP
);
10280 /* If target symbol is undefined, assume it will reach once linked. */
10281 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
10283 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
10285 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10286 _("jump target out of range; no usable trampoline found"));
10292 return this_text_diff
;
10296 /* md_convert_frag Hook and Helper Functions. */
10298 static void convert_frag_align_next_opcode (fragS
*);
10299 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
10300 static void convert_frag_fill_nop (fragS
*);
10301 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
10304 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
10306 static xtensa_insnbuf vbuf
= NULL
;
10307 xtensa_isa isa
= xtensa_default_isa
;
10311 const char *file_name
;
10314 file_name
= as_where (&line
);
10315 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
10317 switch (fragp
->fr_subtype
)
10319 case RELAX_ALIGN_NEXT_OPCODE
:
10320 /* Always convert. */
10321 convert_frag_align_next_opcode (fragp
);
10324 case RELAX_DESIRE_ALIGN
:
10325 /* Do nothing. If not aligned already, too bad. */
10328 case RELAX_LITERAL
:
10329 case RELAX_LITERAL_FINAL
:
10334 vbuf
= xtensa_insnbuf_alloc (isa
);
10336 xtensa_insnbuf_from_chars
10337 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
10338 fmt
= xtensa_format_decode (isa
, vbuf
);
10339 num_slots
= xtensa_format_num_slots (isa
, fmt
);
10341 for (slot
= 0; slot
< num_slots
; slot
++)
10343 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
10346 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
10350 case RELAX_IMMED_STEP1
:
10351 case RELAX_IMMED_STEP2
:
10352 case RELAX_IMMED_STEP3
:
10353 /* Place the immediate. */
10356 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
10361 /* This is OK because some slots could have
10362 relaxations and others have none. */
10368 case RELAX_UNREACHABLE
:
10369 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
10370 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
10371 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
10375 case RELAX_MAYBE_UNREACHABLE
:
10376 case RELAX_MAYBE_DESIRE_ALIGN
:
10380 case RELAX_FILL_NOP
:
10381 convert_frag_fill_nop (fragp
);
10384 case RELAX_LITERAL_NR
:
10385 if (use_literal_section
)
10387 /* This should have been handled during relaxation. When
10388 relaxing a code segment, literals sometimes need to be
10389 added to the corresponding literal segment. If that
10390 literal segment has already been relaxed, then we end up
10391 in this situation. Marking the literal segments as data
10392 would make this happen less often (since GAS always relaxes
10393 code before data), but we could still get into trouble if
10394 there are instructions in a segment that is not marked as
10395 containing code. Until we can implement a better solution,
10396 cheat and adjust the addresses of all the following frags.
10397 This could break subsequent alignments, but the linker's
10398 literal coalescing will do that anyway. */
10401 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
10402 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
10403 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
10404 fragp
->fr_var
-= 4;
10405 fragp
->fr_fix
+= 4;
10406 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
10407 f
->fr_address
+= 4;
10410 as_bad (_("invalid relaxation fragment result"));
10413 case RELAX_TRAMPOLINE
:
10418 new_logical_line (file_name
, line
);
10423 convert_frag_align_next_opcode (fragS
*fragp
)
10425 char *nop_buf
; /* Location for Writing. */
10426 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
10427 addressT aligned_address
;
10429 int nop
, nop_count
;
10431 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
10433 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
10434 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
10435 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10437 for (nop
= 0; nop
< nop_count
; nop
++)
10440 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
10442 assemble_nop (nop_size
, nop_buf
);
10443 nop_buf
+= nop_size
;
10446 fragp
->fr_fix
+= fill_size
;
10447 fragp
->fr_var
-= fill_size
;
10452 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
10454 TInsn tinsn
, single_target
;
10455 int size
, old_size
, diff
;
10456 offsetT frag_offset
;
10458 gas_assert (slot
== 0);
10459 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10461 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10463 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10464 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10465 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10470 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10472 /* No conversion. */
10477 gas_assert (fragP
->fr_opcode
!= NULL
);
10479 /* Frags in this relaxation state should only contain
10480 single instruction bundles. */
10481 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10483 /* Just convert it to a wide form.... */
10485 old_size
= xg_get_single_size (tinsn
.opcode
);
10487 tinsn_init (&single_target
);
10488 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10490 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10492 as_bad (_("unable to widen instruction"));
10496 size
= xg_get_single_size (single_target
.opcode
);
10497 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10498 frag_offset
, TRUE
);
10500 diff
= size
- old_size
;
10501 gas_assert (diff
>= 0);
10502 gas_assert (diff
<= fragP
->fr_var
);
10503 fragP
->fr_var
-= diff
;
10504 fragP
->fr_fix
+= diff
;
10512 convert_frag_fill_nop (fragS
*fragP
)
10514 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10515 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10516 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10517 - fragP
->fr_address
- fragP
->fr_fix
));
10520 /* No conversion. */
10524 assemble_nop (size
, loc
);
10525 fragP
->tc_frag_data
.is_insn
= TRUE
;
10526 fragP
->fr_var
-= size
;
10527 fragP
->fr_fix
+= size
;
10532 static fixS
*fix_new_exp_in_seg
10533 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10534 bfd_reloc_code_real_type
);
10535 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
10538 convert_frag_immed (segT segP
,
10544 char *immed_instr
= fragP
->fr_opcode
;
10546 bfd_boolean expanded
= FALSE
;
10547 bfd_boolean branch_jmp_to_next
= FALSE
;
10548 char *fr_opcode
= fragP
->fr_opcode
;
10549 xtensa_isa isa
= xtensa_default_isa
;
10550 bfd_boolean from_wide_insn
= FALSE
;
10552 bfd_boolean is_loop
;
10554 gas_assert (fr_opcode
!= NULL
);
10556 xg_clear_vinsn (&cur_vinsn
);
10558 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10559 if (cur_vinsn
.num_slots
> 1)
10560 from_wide_insn
= TRUE
;
10562 orig_tinsn
= cur_vinsn
.slots
[slot
];
10563 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10565 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10567 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10568 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10570 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10572 /* Conversion just inserts a NOP and marks the fix as completed. */
10573 bytes
= xtensa_format_length (isa
, fmt
);
10576 cur_vinsn
.slots
[slot
].opcode
=
10577 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10578 cur_vinsn
.slots
[slot
].ntok
= 0;
10582 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10583 gas_assert (bytes
== 2 || bytes
== 3);
10584 build_nop (&cur_vinsn
.slots
[0], bytes
);
10585 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10587 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10588 xtensa_insnbuf_to_chars
10589 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10594 /* Here is the fun stuff: Get the immediate field from this
10595 instruction. If it fits, we're done. If not, find the next
10596 instruction sequence that fits. */
10600 symbolS
*lit_sym
= NULL
;
10601 int total_size
= 0;
10602 int target_offset
= 0;
10605 symbolS
*gen_label
= NULL
;
10606 offsetT frag_offset
;
10607 bfd_boolean first
= TRUE
;
10609 /* It does not fit. Find something that does and
10610 convert immediately. */
10611 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10612 istack_init (&istack
);
10613 xg_assembly_relax (&istack
, &orig_tinsn
,
10614 segP
, fragP
, frag_offset
, min_steps
, 0);
10616 old_size
= xtensa_format_length (isa
, fmt
);
10618 /* Assemble this right inline. */
10620 /* First, create the mapping from a label name to the REAL label. */
10622 for (i
= 0; i
< istack
.ninsn
; i
++)
10624 TInsn
*tinsn
= &istack
.insn
[i
];
10627 switch (tinsn
->insn_type
)
10629 case ITYPE_LITERAL
:
10630 if (lit_sym
!= NULL
)
10631 as_bad (_("multiple literals in expansion"));
10632 /* First find the appropriate space in the literal pool. */
10633 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10634 if (lit_frag
== NULL
)
10635 as_bad (_("no registered fragment for literal"));
10636 if (tinsn
->ntok
!= 1)
10637 as_bad (_("number of literal tokens != 1"));
10639 /* Set the literal symbol and add a fixup. */
10640 lit_sym
= lit_frag
->fr_symbol
;
10644 if (align_targets
&& !is_loop
)
10646 fragS
*unreach
= fragP
->fr_next
;
10647 while (!(unreach
->fr_type
== rs_machine_dependent
10648 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10649 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10651 unreach
= unreach
->fr_next
;
10654 gas_assert (unreach
->fr_type
== rs_machine_dependent
10655 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10656 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10658 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10660 gas_assert (gen_label
== NULL
);
10661 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10662 fr_opcode
- fragP
->fr_literal
10663 + target_offset
, fragP
);
10667 if (first
&& from_wide_insn
)
10669 target_offset
+= xtensa_format_length (isa
, fmt
);
10671 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10672 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10675 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10682 for (i
= 0; i
< istack
.ninsn
; i
++)
10684 TInsn
*tinsn
= &istack
.insn
[i
];
10688 bfd_reloc_code_real_type reloc_type
;
10690 switch (tinsn
->insn_type
)
10692 case ITYPE_LITERAL
:
10693 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10694 /* Already checked. */
10695 gas_assert (lit_frag
!= NULL
);
10696 gas_assert (lit_sym
!= NULL
);
10697 gas_assert (tinsn
->ntok
== 1);
10699 target_seg
= S_GET_SEGMENT (lit_sym
);
10700 gas_assert (target_seg
);
10701 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10702 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10703 &tinsn
->tok
[0], FALSE
, reloc_type
);
10710 xg_resolve_labels (tinsn
, gen_label
);
10711 xg_resolve_literals (tinsn
, lit_sym
);
10712 if (from_wide_insn
&& first
)
10715 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10717 cur_vinsn
.slots
[slot
] = *tinsn
;
10721 cur_vinsn
.slots
[slot
].opcode
=
10722 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10723 cur_vinsn
.slots
[slot
].ntok
= 0;
10725 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10726 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10727 (unsigned char *) immed_instr
, 0);
10728 fragP
->tc_frag_data
.is_insn
= TRUE
;
10729 size
= xtensa_format_length (isa
, fmt
);
10730 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10732 xg_emit_insn_to_buf
10733 (tinsn
, immed_instr
+ size
, fragP
,
10734 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10735 size
+= xg_get_single_size (tinsn
->opcode
);
10740 size
= xg_get_single_size (tinsn
->opcode
);
10741 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10742 immed_instr
- fragP
->fr_literal
, TRUE
);
10744 immed_instr
+= size
;
10745 total_size
+= size
;
10750 diff
= total_size
- old_size
;
10751 gas_assert (diff
>= 0);
10754 gas_assert (diff
<= fragP
->fr_var
);
10755 fragP
->fr_var
-= diff
;
10756 fragP
->fr_fix
+= diff
;
10759 /* Check for undefined immediates in LOOP instructions. */
10763 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10764 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10766 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10769 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10770 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10772 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10777 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
10778 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
10780 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10782 /* Add an expansion note on the expanded instruction. */
10783 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10784 &orig_tinsn
.tok
[0], TRUE
,
10785 BFD_RELOC_XTENSA_ASM_EXPAND
);
10790 /* Add a new fix expression into the desired segment. We have to
10791 switch to that segment to do this. */
10794 fix_new_exp_in_seg (segT new_seg
,
10795 subsegT new_subseg
,
10801 bfd_reloc_code_real_type r_type
)
10804 segT seg
= now_seg
;
10805 subsegT subseg
= now_subseg
;
10807 gas_assert (new_seg
!= 0);
10808 subseg_set (new_seg
, new_subseg
);
10810 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10811 subseg_set (seg
, subseg
);
10816 /* Relax a loop instruction so that it can span loop >256 bytes.
10822 addi as, as, lo8 (label-.L1)
10823 addmi as, as, mid8 (label-.L1)
10834 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
10839 unsigned long target
;
10840 static xtensa_insnbuf insnbuf
= NULL
;
10841 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
10842 xtensa_isa isa
= xtensa_default_isa
;
10843 addressT loop_offset
;
10844 addressT addi_offset
= 9;
10845 addressT addmi_offset
= 12;
10850 insnbuf
= xtensa_insnbuf_alloc (isa
);
10852 /* Get the loop offset. */
10853 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
10855 /* Validate that there really is a LOOP at the loop_offset. Because
10856 loops are not bundleable, we can assume that the instruction will be
10858 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
10859 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
10861 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
10862 addi_offset
+= loop_offset
;
10863 addmi_offset
+= loop_offset
;
10865 gas_assert (tinsn
->ntok
== 2);
10866 if (tinsn
->tok
[1].X_op
== O_constant
)
10867 target
= tinsn
->tok
[1].X_add_number
;
10868 else if (tinsn
->tok
[1].X_op
== O_symbol
)
10870 /* Find the fragment. */
10871 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
10872 gas_assert (S_GET_SEGMENT (sym
) == segP
10873 || S_GET_SEGMENT (sym
) == absolute_section
);
10874 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
10878 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
10882 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
10883 loop_length_hi
= loop_length
& ~0x0ff;
10884 loop_length_lo
= loop_length
& 0x0ff;
10885 if (loop_length_lo
>= 128)
10887 loop_length_lo
-= 256;
10888 loop_length_hi
+= 256;
10891 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
10892 32512. If the loop is larger than that, then we just fail. */
10893 if (loop_length_hi
> 32512)
10894 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10895 _("loop too long for LOOP instruction"));
10897 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
10898 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
10900 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
10901 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
10903 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
10904 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
10906 fragP
->tc_frag_data
.is_insn
= TRUE
;
10907 xtensa_insnbuf_to_chars
10908 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
10910 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
10911 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
10912 xtensa_insnbuf_to_chars
10913 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
10915 /* Walk through all of the frags from here to the loop end
10916 and mark them as no_transform to keep them from being modified
10917 by the linker. If we ever have a relocation for the
10918 addi/addmi of the difference of two symbols we can remove this. */
10921 for (next_fragP
= fragP
; next_fragP
!= NULL
;
10922 next_fragP
= next_fragP
->fr_next
)
10924 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
10925 if (next_fragP
->tc_frag_data
.is_loop_target
)
10927 if (target_count
== 2)
10933 /* A map that keeps information on a per-subsegment basis. This is
10934 maintained during initial assembly, but is invalid once the
10935 subsegments are smashed together. I.E., it cannot be used during
10938 typedef struct subseg_map_struct
10946 float total_freq
; /* fall-through + branch target frequency */
10947 float target_freq
; /* branch target frequency alone */
10949 struct subseg_map_struct
*next
;
10953 static subseg_map
*sseg_map
= NULL
;
10955 static subseg_map
*
10956 get_subseg_info (segT seg
, subsegT subseg
)
10958 subseg_map
*subseg_e
;
10960 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
10962 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
10969 static subseg_map
*
10970 add_subseg_info (segT seg
, subsegT subseg
)
10972 subseg_map
*subseg_e
= XNEW (subseg_map
);
10973 memset (subseg_e
, 0, sizeof (subseg_map
));
10974 subseg_e
->seg
= seg
;
10975 subseg_e
->subseg
= subseg
;
10976 subseg_e
->flags
= 0;
10977 /* Start off considering every branch target very important. */
10978 subseg_e
->target_freq
= 1.0;
10979 subseg_e
->total_freq
= 1.0;
10980 subseg_e
->next
= sseg_map
;
10981 sseg_map
= subseg_e
;
10987 get_last_insn_flags (segT seg
, subsegT subseg
)
10989 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10991 return subseg_e
->flags
;
10997 set_last_insn_flags (segT seg
,
11002 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11004 subseg_e
= add_subseg_info (seg
, subseg
);
11006 subseg_e
->flags
|= fl
;
11008 subseg_e
->flags
&= ~fl
;
11013 get_subseg_total_freq (segT seg
, subsegT subseg
)
11015 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11017 return subseg_e
->total_freq
;
11023 get_subseg_target_freq (segT seg
, subsegT subseg
)
11025 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11027 return subseg_e
->target_freq
;
11033 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
11035 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11037 subseg_e
= add_subseg_info (seg
, subseg
);
11038 subseg_e
->total_freq
= total_f
;
11039 subseg_e
->target_freq
= target_f
;
11043 /* Segment Lists and emit_state Stuff. */
11046 xtensa_move_seg_list_to_beginning (seg_list
*head
)
11051 segT literal_section
= head
->seg
;
11053 /* Move the literal section to the front of the section list. */
11054 gas_assert (literal_section
);
11055 if (literal_section
!= stdoutput
->sections
)
11057 bfd_section_list_remove (stdoutput
, literal_section
);
11058 bfd_section_list_prepend (stdoutput
, literal_section
);
11065 static void mark_literal_frags (seg_list
*);
11068 xg_promote_candidate_litpool (struct litpool_seg
*lps
,
11069 struct litpool_frag
*lp
)
11074 char label
[10 + 2 * sizeof (fragS
*)];
11076 poolbeg
= lp
->fragP
;
11078 poolbeg
->fr_subtype
= RELAX_LITERAL_POOL_BEGIN
;
11079 poolend
= poolbeg
->fr_next
;
11080 gas_assert (poolend
->fr_type
== rs_machine_dependent
&&
11081 poolend
->fr_subtype
== RELAX_LITERAL_POOL_END
);
11082 /* Create a local symbol pointing to the
11083 end of the pool. */
11084 sprintf (label
, ".L0_LT_%p", poolbeg
);
11085 lsym
= (symbolS
*)local_symbol_make (label
, lps
->seg
,
11087 poolbeg
->fr_symbol
= lsym
;
11088 /* Rest is done in xtensa_relax_frag. */
11092 xtensa_move_literals (void)
11095 frchainS
*frchain_from
, *frchain_to
;
11096 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
11097 fragS
**frag_splice
;
11100 fixS
*fix
, *next_fix
, **fix_splice
;
11102 struct litpool_seg
*lps
;
11103 const char *init_name
= INIT_SECTION_NAME
;
11104 const char *fini_name
= FINI_SECTION_NAME
;
11105 int init_name_len
= strlen(init_name
);
11106 int fini_name_len
= strlen(fini_name
);
11108 mark_literal_frags (literal_head
->next
);
11110 if (use_literal_section
)
11113 /* Assign addresses (rough estimates) to the potential literal pool locations
11114 and create new ones if the gaps are too large. */
11116 for (lps
= litpool_seg_list
.next
; lps
; lps
= lps
->next
)
11118 frchainS
*frchP
= seg_info (lps
->seg
)->frchainP
;
11119 struct litpool_frag
*lpf
= lps
->frag_list
.next
;
11122 for ( ; frchP
; frchP
= frchP
->frch_next
)
11125 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11127 if (lpf
&& fragP
== lpf
->fragP
)
11129 gas_assert(fragP
->fr_type
== rs_machine_dependent
&&
11130 (fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
||
11131 fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
));
11132 /* Found a litpool location. */
11136 if (fragP
->fr_type
== rs_machine_dependent
&&
11137 fragP
->fr_subtype
== RELAX_SLOTS
)
11140 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
11142 if (fragP
->tc_frag_data
.literal_frags
[slot
])
11144 /* L32R; point its literal to the nearest litpool
11145 preferring non-"candidate" positions to avoid
11146 the jump-around. */
11147 fragS
*litfrag
= fragP
->tc_frag_data
.literal_frags
[slot
];
11148 struct litpool_frag
*lp
= lpf
->prev
;
11153 while (lp
->fragP
->fr_subtype
==
11154 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11157 if (lp
->fragP
== NULL
)
11159 /* End of list; have to bite the bullet.
11160 Take the nearest. */
11164 /* Does it (conservatively) reach? */
11165 if (addr
- lp
->addr
<= 128 * 1024)
11167 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
11169 /* Found a good one. */
11172 else if (lp
->prev
->fragP
&&
11173 addr
- lp
->prev
->addr
> 128 * 1024)
11175 /* This is still a "candidate" but the next one
11176 will be too far away, so revert to the nearest
11177 one, convert it and add the jump around. */
11184 /* Convert candidate and add the jump around. */
11185 if (lp
->fragP
->fr_subtype
==
11186 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11187 xg_promote_candidate_litpool (lps
, lp
);
11189 if (! litfrag
->tc_frag_data
.literal_frag
)
11191 /* Take earliest use of this literal to avoid
11193 litfrag
->tc_frag_data
.literal_frag
= lp
->fragP
;
11198 addr
+= fragP
->fr_fix
;
11199 if (fragP
->fr_type
== rs_fill
)
11200 addr
+= fragP
->fr_offset
;
11205 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
11207 const char *seg_name
= segment_name (segment
->seg
);
11209 /* Keep the literals for .init and .fini in separate sections. */
11210 if ((!memcmp (seg_name
, init_name
, init_name_len
) &&
11211 !strcmp (seg_name
+ init_name_len
, ".literal")) ||
11212 (!memcmp (seg_name
, fini_name
, fini_name_len
) &&
11213 !strcmp (seg_name
+ fini_name_len
, ".literal")))
11216 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11217 search_frag
= frchain_from
->frch_root
;
11218 literal_pool
= NULL
;
11220 frag_splice
= &(frchain_from
->frch_root
);
11222 while (search_frag
&& !search_frag
->tc_frag_data
.literal_frag
)
11224 gas_assert (search_frag
->fr_fix
== 0
11225 || search_frag
->fr_type
== rs_align
);
11226 search_frag
= search_frag
->fr_next
;
11231 search_frag
= frchain_from
->frch_root
;
11232 as_bad_where (search_frag
->fr_file
, search_frag
->fr_line
,
11233 _("literal pool location required for text-section-literals; specify with .literal_position"));
11237 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
11238 == RELAX_LITERAL_POOL_BEGIN
);
11239 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
11241 /* Make sure that all the frags in this series are closed, and
11242 that there is at least one left over of zero-size. This
11243 prevents us from making a segment with an frchain without any
11245 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11246 xtensa_set_frag_assembly_state (frag_now
);
11247 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11248 xtensa_set_frag_assembly_state (frag_now
);
11250 while (search_frag
!= frag_now
)
11252 next_frag
= search_frag
->fr_next
;
11253 if (search_frag
->tc_frag_data
.literal_frag
)
11255 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
11256 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
11257 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
11258 gas_assert (frchain_to
);
11261 if (search_frag
->fr_type
== rs_fill
&& search_frag
->fr_fix
== 0)
11263 /* Skip empty fill frags. */
11264 *frag_splice
= next_frag
;
11265 search_frag
= next_frag
;
11269 if (search_frag
->fr_type
== rs_align
)
11271 /* Skip alignment frags, because the pool as a whole will be
11272 aligned if used, and we don't want to force alignment if the
11274 *frag_splice
= next_frag
;
11275 search_frag
= next_frag
;
11279 /* First, move the frag out of the literal section and
11280 to the appropriate place. */
11282 /* Insert an alignment frag at start of pool. */
11283 if (literal_pool
->fr_next
->fr_type
== rs_machine_dependent
&&
11284 literal_pool
->fr_next
->fr_subtype
== RELAX_LITERAL_POOL_END
)
11286 segT pool_seg
= literal_pool
->fr_next
->tc_frag_data
.lit_seg
;
11287 emit_state prev_state
;
11290 xtensa_switch_section_emit_state (&prev_state
, pool_seg
, 0);
11291 prev_frag
= frag_now
;
11292 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11293 align_frag
= frag_now
;
11294 frag_align (2, 0, 0);
11295 /* Splice it into the right place. */
11296 prev_frag
->fr_next
= align_frag
->fr_next
;
11297 align_frag
->fr_next
= literal_pool
->fr_next
;
11298 literal_pool
->fr_next
= align_frag
;
11299 /* Insert after this one. */
11300 literal_pool
->tc_frag_data
.literal_frag
= align_frag
;
11301 xtensa_restore_emit_state (&prev_state
);
11303 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
11304 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
11305 /* Skip align frag. */
11306 if (insert_after
->fr_next
->fr_type
== rs_align
)
11308 insert_after
= insert_after
->fr_next
;
11311 *frag_splice
= next_frag
;
11312 search_frag
->fr_next
= insert_after
->fr_next
;
11313 insert_after
->fr_next
= search_frag
;
11314 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
11315 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
11317 /* Now move any fixups associated with this frag to the
11319 fix
= frchain_from
->fix_root
;
11320 fix_splice
= &(frchain_from
->fix_root
);
11323 next_fix
= fix
->fx_next
;
11324 if (fix
->fx_frag
== search_frag
)
11326 *fix_splice
= next_fix
;
11327 fix
->fx_next
= frchain_to
->fix_root
;
11328 frchain_to
->fix_root
= fix
;
11329 if (frchain_to
->fix_tail
== NULL
)
11330 frchain_to
->fix_tail
= fix
;
11333 fix_splice
= &(fix
->fx_next
);
11336 search_frag
= next_frag
;
11339 if (frchain_from
->fix_root
!= NULL
)
11341 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11342 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
11344 gas_assert (frchain_from
->fix_root
== NULL
);
11346 frchain_from
->fix_tail
= NULL
;
11347 xtensa_restore_emit_state (&state
);
11350 /* Now fix up the SEGMENT value for all the literal symbols. */
11351 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
11353 symbolS
*lit_sym
= lit
->sym
;
11354 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
11356 S_SET_SEGMENT (lit_sym
, dseg
);
11361 /* Walk over all the frags for segments in a list and mark them as
11362 containing literals. As clunky as this is, we can't rely on frag_var
11363 and frag_variant to get called in all situations. */
11366 mark_literal_frags (seg_list
*segment
)
11368 frchainS
*frchain_from
;
11369 fragS
*search_frag
;
11373 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11374 search_frag
= frchain_from
->frch_root
;
11375 while (search_frag
)
11377 search_frag
->tc_frag_data
.is_literal
= TRUE
;
11378 search_frag
= search_frag
->fr_next
;
11380 segment
= segment
->next
;
11386 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
11388 /* Move all of the sections in the section list to come
11389 after "after" in the gnu segment list. */
11394 segT literal_section
= head
->seg
;
11396 /* Move the literal section after "after". */
11397 gas_assert (literal_section
);
11398 if (literal_section
!= after
)
11400 bfd_section_list_remove (stdoutput
, literal_section
);
11401 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
11409 /* Push all the literal segments to the end of the gnu list. */
11412 xtensa_reorder_segments (void)
11419 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11425 /* Now that we have the last section, push all the literal
11426 sections to the end. */
11427 xtensa_reorder_seg_list (literal_head
, last_sec
);
11429 /* Now perform the final error check. */
11430 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11432 gas_assert (new_count
== old_count
);
11436 /* Change the emit state (seg, subseg, and frag related stuff) to the
11437 correct location. Return a emit_state which can be passed to
11438 xtensa_restore_emit_state to return to current fragment. */
11441 xtensa_switch_to_literal_fragment (emit_state
*result
)
11443 if (directive_state
[directive_absolute_literals
])
11445 segT lit4_seg
= cache_literal_section (TRUE
);
11446 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
11449 xtensa_switch_to_non_abs_literal_fragment (result
);
11451 /* Do a 4-byte align here. */
11452 frag_align (2, 0, 0);
11453 record_alignment (now_seg
, 2);
11458 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
11460 fragS
*pool_location
= get_literal_pool_location (now_seg
);
11462 bfd_boolean is_init
=
11463 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
11464 bfd_boolean is_fini
=
11465 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
11467 if (pool_location
== NULL
11468 && !use_literal_section
11469 && !is_init
&& ! is_fini
)
11471 if (!auto_litpools
)
11473 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11475 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
11476 pool_location
= get_literal_pool_location (now_seg
);
11479 lit_seg
= cache_literal_section (FALSE
);
11480 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
11482 if (!use_literal_section
11483 && !is_init
&& !is_fini
11484 && get_literal_pool_location (now_seg
) != pool_location
)
11486 /* Close whatever frag is there. */
11487 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11488 xtensa_set_frag_assembly_state (frag_now
);
11489 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
11490 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11491 xtensa_set_frag_assembly_state (frag_now
);
11496 /* Call this function before emitting data into the literal section.
11497 This is a helper function for xtensa_switch_to_literal_fragment.
11498 This is similar to a .section new_now_seg subseg. */
11501 xtensa_switch_section_emit_state (emit_state
*state
,
11503 subsegT new_now_subseg
)
11505 state
->name
= now_seg
->name
;
11506 state
->now_seg
= now_seg
;
11507 state
->now_subseg
= now_subseg
;
11508 state
->generating_literals
= generating_literals
;
11509 generating_literals
++;
11510 subseg_set (new_now_seg
, new_now_subseg
);
11514 /* Use to restore the emitting into the normal place. */
11517 xtensa_restore_emit_state (emit_state
*state
)
11519 generating_literals
= state
->generating_literals
;
11520 subseg_set (state
->now_seg
, state
->now_subseg
);
11524 /* Predicate function used to look up a section in a particular group. */
11527 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
11529 const char *gname
= inf
;
11530 const char *group_name
= elf_group_name (sec
);
11532 return (group_name
== gname
11533 || (group_name
!= NULL
11535 && strcmp (group_name
, gname
) == 0));
11539 /* Get the literal section to be used for the current text section.
11540 The result may be cached in the default_lit_sections structure. */
11543 cache_literal_section (bfd_boolean use_abs_literals
)
11545 const char *text_name
, *group_name
= 0;
11546 const char *base_name
, *suffix
;
11549 segT seg
, current_section
;
11550 int current_subsec
;
11551 bfd_boolean linkonce
= FALSE
;
11553 /* Save the current section/subsection. */
11554 current_section
= now_seg
;
11555 current_subsec
= now_subseg
;
11557 /* Clear the cached values if they are no longer valid. */
11558 if (now_seg
!= default_lit_sections
.current_text_seg
)
11560 default_lit_sections
.current_text_seg
= now_seg
;
11561 default_lit_sections
.lit_seg
= NULL
;
11562 default_lit_sections
.lit4_seg
= NULL
;
11565 /* Check if the literal section is already cached. */
11566 if (use_abs_literals
)
11567 pcached
= &default_lit_sections
.lit4_seg
;
11569 pcached
= &default_lit_sections
.lit_seg
;
11574 text_name
= default_lit_sections
.lit_prefix
;
11575 if (! text_name
|| ! *text_name
)
11577 text_name
= segment_name (current_section
);
11578 group_name
= elf_group_name (current_section
);
11579 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
11582 base_name
= use_abs_literals
? ".lit4" : ".literal";
11585 name
= concat (base_name
, ".", group_name
, (char *) NULL
);
11587 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
11589 suffix
= strchr (text_name
+ linkonce_len
, '.');
11591 name
= concat (".gnu.linkonce", base_name
, suffix
? suffix
: "",
11597 /* If the section name begins or ends with ".text", then replace
11598 that portion instead of appending an additional suffix. */
11599 size_t len
= strlen (text_name
);
11601 && (strcmp (text_name
+ len
- 5, ".text") == 0
11602 || strncmp (text_name
, ".text", 5) == 0))
11605 name
= XNEWVEC (char, len
+ strlen (base_name
) + 1);
11606 if (strncmp (text_name
, ".text", 5) == 0)
11608 strcpy (name
, base_name
);
11609 strcat (name
, text_name
+ 5);
11613 strcpy (name
, text_name
);
11614 strcpy (name
+ len
, base_name
);
11618 /* Canonicalize section names to allow renaming literal sections.
11619 The group name, if any, came from the current text section and
11620 has already been canonicalized. */
11621 name
= tc_canonicalize_symbol_name (name
);
11623 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11624 (void *) group_name
);
11629 seg
= subseg_force_new (name
, 0);
11631 if (! use_abs_literals
)
11633 /* Add the newly created literal segment to the list. */
11634 seg_list
*n
= XNEW (seg_list
);
11636 n
->next
= literal_head
->next
;
11637 literal_head
->next
= n
;
11640 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11641 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11642 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11644 elf_group_name (seg
) = group_name
;
11646 bfd_set_section_flags (stdoutput
, seg
, flags
);
11647 bfd_set_section_alignment (stdoutput
, seg
, 2);
11651 subseg_set (current_section
, current_subsec
);
11656 /* Property Tables Stuff. */
11658 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11659 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11660 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11662 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11663 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11665 static bfd_boolean
get_frag_is_literal (const fragS
*);
11666 static void xtensa_create_property_segments
11667 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11668 static void xtensa_create_xproperty_segments
11669 (frag_flags_fn
, const char *, xt_section_type
);
11670 static bfd_boolean
exclude_section_from_property_tables (segT
);
11671 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11672 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11673 static void add_xt_block_frags
11674 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11675 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11676 static void xtensa_frag_flags_init (frag_flags
*);
11677 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11678 static flagword
frag_flags_to_number (const frag_flags
*);
11679 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11681 /* Set up property tables after relaxation. */
11684 xtensa_post_relax_hook (void)
11686 xtensa_move_seg_list_to_beginning (literal_head
);
11688 xtensa_find_unmarked_state_frags ();
11689 xtensa_mark_frags_for_org ();
11690 xtensa_mark_difference_of_two_symbols ();
11692 xtensa_create_property_segments (get_frag_is_literal
,
11694 XTENSA_LIT_SEC_NAME
,
11696 xtensa_create_xproperty_segments (get_frag_property_flags
,
11697 XTENSA_PROP_SEC_NAME
,
11700 if (warn_unaligned_branch_targets
)
11701 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11702 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11706 /* This function is only meaningful after xtensa_move_literals. */
11709 get_frag_is_literal (const fragS
*fragP
)
11711 gas_assert (fragP
!= NULL
);
11712 return fragP
->tc_frag_data
.is_literal
;
11717 xtensa_create_property_segments (frag_predicate property_function
,
11718 frag_predicate end_property_function
,
11719 const char *section_name_base
,
11720 xt_section_type sec_type
)
11724 /* Walk over all of the current segments.
11725 Walk over each fragment
11726 For each non-empty fragment,
11727 Build a property record (append where possible). */
11729 for (seclist
= &stdoutput
->sections
;
11730 seclist
&& *seclist
;
11731 seclist
= &(*seclist
)->next
)
11733 segT sec
= *seclist
;
11735 if (exclude_section_from_property_tables (sec
))
11738 if (section_has_property (sec
, property_function
))
11740 segment_info_type
*xt_seg_info
;
11741 xtensa_block_info
**xt_blocks
;
11742 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11744 prop_sec
->output_section
= prop_sec
;
11745 subseg_set (prop_sec
, 0);
11746 xt_seg_info
= seg_info (prop_sec
);
11747 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11749 /* Walk over all of the frchains here and add new sections. */
11750 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11751 end_property_function
);
11755 /* Now we fill them out.... */
11757 for (seclist
= &stdoutput
->sections
;
11758 seclist
&& *seclist
;
11759 seclist
= &(*seclist
)->next
)
11761 segment_info_type
*seginfo
;
11762 xtensa_block_info
*block
;
11763 segT sec
= *seclist
;
11765 seginfo
= seg_info (sec
);
11766 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11770 xtensa_block_info
*cur_block
;
11772 bfd_size_type rec_size
;
11774 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11777 rec_size
= num_recs
* 8;
11778 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11785 subseg_set (sec
, 0);
11786 frag_data
= frag_more (rec_size
);
11788 for (i
= 0; i
< num_recs
; i
++)
11792 /* Write the fixup. */
11793 gas_assert (cur_block
);
11794 fix
= fix_new (frag_now
, i
* 8, 4,
11795 section_symbol (cur_block
->sec
),
11797 FALSE
, BFD_RELOC_32
);
11798 fix
->fx_file
= "<internal>";
11801 /* Write the length. */
11802 md_number_to_chars (&frag_data
[4 + i
* 8],
11803 cur_block
->size
, 4);
11804 cur_block
= cur_block
->next
;
11806 frag_wane (frag_now
);
11808 frag_wane (frag_now
);
11816 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11817 const char *section_name_base
,
11818 xt_section_type sec_type
)
11822 /* Walk over all of the current segments.
11823 Walk over each fragment.
11824 For each fragment that has instructions,
11825 build an instruction record (append where possible). */
11827 for (seclist
= &stdoutput
->sections
;
11828 seclist
&& *seclist
;
11829 seclist
= &(*seclist
)->next
)
11831 segT sec
= *seclist
;
11833 if (exclude_section_from_property_tables (sec
))
11836 if (section_has_xproperty (sec
, flag_fn
))
11838 segment_info_type
*xt_seg_info
;
11839 xtensa_block_info
**xt_blocks
;
11840 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11842 prop_sec
->output_section
= prop_sec
;
11843 subseg_set (prop_sec
, 0);
11844 xt_seg_info
= seg_info (prop_sec
);
11845 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11847 /* Walk over all of the frchains here and add new sections. */
11848 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
11852 /* Now we fill them out.... */
11854 for (seclist
= &stdoutput
->sections
;
11855 seclist
&& *seclist
;
11856 seclist
= &(*seclist
)->next
)
11858 segment_info_type
*seginfo
;
11859 xtensa_block_info
*block
;
11860 segT sec
= *seclist
;
11862 seginfo
= seg_info (sec
);
11863 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11867 xtensa_block_info
*cur_block
;
11869 bfd_size_type rec_size
;
11871 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11874 rec_size
= num_recs
* (8 + 4);
11875 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11876 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11883 subseg_set (sec
, 0);
11884 frag_data
= frag_more (rec_size
);
11886 for (i
= 0; i
< num_recs
; i
++)
11890 /* Write the fixup. */
11891 gas_assert (cur_block
);
11892 fix
= fix_new (frag_now
, i
* 12, 4,
11893 section_symbol (cur_block
->sec
),
11895 FALSE
, BFD_RELOC_32
);
11896 fix
->fx_file
= "<internal>";
11899 /* Write the length. */
11900 md_number_to_chars (&frag_data
[4 + i
* 12],
11901 cur_block
->size
, 4);
11902 md_number_to_chars (&frag_data
[8 + i
* 12],
11903 frag_flags_to_number (&cur_block
->flags
),
11904 sizeof (flagword
));
11905 cur_block
= cur_block
->next
;
11907 frag_wane (frag_now
);
11909 frag_wane (frag_now
);
11917 exclude_section_from_property_tables (segT sec
)
11919 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
11921 /* Sections that don't contribute to the memory footprint are excluded. */
11922 if ((flags
& SEC_DEBUGGING
)
11923 || !(flags
& SEC_ALLOC
)
11924 || (flags
& SEC_MERGE
))
11927 /* Linker cie and fde optimizations mess up property entries for
11928 eh_frame sections, but there is nothing inside them relevant to
11929 property tables anyway. */
11930 if (strcmp (sec
->name
, ".eh_frame") == 0)
11938 section_has_property (segT sec
, frag_predicate property_function
)
11940 segment_info_type
*seginfo
= seg_info (sec
);
11943 if (seginfo
&& seginfo
->frchainP
)
11945 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11947 if (property_function (fragP
)
11948 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11957 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
11959 segment_info_type
*seginfo
= seg_info (sec
);
11962 if (seginfo
&& seginfo
->frchainP
)
11964 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11966 frag_flags prop_flags
;
11967 property_function (fragP
, &prop_flags
);
11968 if (!xtensa_frag_flags_is_empty (&prop_flags
))
11976 /* Two types of block sections exist right now: literal and insns. */
11979 add_xt_block_frags (segT sec
,
11980 xtensa_block_info
**xt_block
,
11981 frag_predicate property_function
,
11982 frag_predicate end_property_function
)
11986 /* Build it if needed. */
11987 while (*xt_block
!= NULL
)
11988 xt_block
= &(*xt_block
)->next
;
11989 /* We are either at NULL at the beginning or at the end. */
11991 /* Walk through the frags. */
11992 if (seg_info (sec
)->frchainP
)
11994 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
11996 fragP
= fragP
->fr_next
)
11998 if (property_function (fragP
)
11999 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
12001 if (*xt_block
!= NULL
)
12003 if ((*xt_block
)->offset
+ (*xt_block
)->size
12004 == fragP
->fr_address
)
12005 (*xt_block
)->size
+= fragP
->fr_fix
;
12007 xt_block
= &((*xt_block
)->next
);
12009 if (*xt_block
== NULL
)
12011 xtensa_block_info
*new_block
= XNEW (xtensa_block_info
);
12012 new_block
->sec
= sec
;
12013 new_block
->offset
= fragP
->fr_address
;
12014 new_block
->size
= fragP
->fr_fix
;
12015 new_block
->next
= NULL
;
12016 xtensa_frag_flags_init (&new_block
->flags
);
12017 *xt_block
= new_block
;
12019 if (end_property_function
12020 && end_property_function (fragP
))
12022 xt_block
= &((*xt_block
)->next
);
12030 /* Break the encapsulation of add_xt_prop_frags here. */
12033 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
12035 if (prop_flags
->is_literal
12036 || prop_flags
->is_insn
12037 || prop_flags
->is_data
12038 || prop_flags
->is_unreachable
)
12045 xtensa_frag_flags_init (frag_flags
*prop_flags
)
12047 memset (prop_flags
, 0, sizeof (frag_flags
));
12052 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
12054 xtensa_frag_flags_init (prop_flags
);
12055 if (fragP
->tc_frag_data
.is_literal
)
12056 prop_flags
->is_literal
= TRUE
;
12057 if (fragP
->tc_frag_data
.is_specific_opcode
12058 || fragP
->tc_frag_data
.is_no_transform
)
12060 prop_flags
->is_no_transform
= TRUE
;
12061 if (xtensa_frag_flags_is_empty (prop_flags
))
12062 prop_flags
->is_data
= TRUE
;
12064 if (fragP
->tc_frag_data
.is_unreachable
)
12065 prop_flags
->is_unreachable
= TRUE
;
12066 else if (fragP
->tc_frag_data
.is_insn
)
12068 prop_flags
->is_insn
= TRUE
;
12069 if (fragP
->tc_frag_data
.is_loop_target
)
12070 prop_flags
->insn
.is_loop_target
= TRUE
;
12071 if (fragP
->tc_frag_data
.is_branch_target
)
12072 prop_flags
->insn
.is_branch_target
= TRUE
;
12073 if (fragP
->tc_frag_data
.is_no_density
)
12074 prop_flags
->insn
.is_no_density
= TRUE
;
12075 if (fragP
->tc_frag_data
.use_absolute_literals
)
12076 prop_flags
->insn
.is_abslit
= TRUE
;
12078 if (fragP
->tc_frag_data
.is_align
)
12080 prop_flags
->is_align
= TRUE
;
12081 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
12082 if (xtensa_frag_flags_is_empty (prop_flags
))
12083 prop_flags
->is_data
= TRUE
;
12089 frag_flags_to_number (const frag_flags
*prop_flags
)
12092 if (prop_flags
->is_literal
)
12093 num
|= XTENSA_PROP_LITERAL
;
12094 if (prop_flags
->is_insn
)
12095 num
|= XTENSA_PROP_INSN
;
12096 if (prop_flags
->is_data
)
12097 num
|= XTENSA_PROP_DATA
;
12098 if (prop_flags
->is_unreachable
)
12099 num
|= XTENSA_PROP_UNREACHABLE
;
12100 if (prop_flags
->insn
.is_loop_target
)
12101 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
12102 if (prop_flags
->insn
.is_branch_target
)
12104 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
12105 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
12108 if (prop_flags
->insn
.is_no_density
)
12109 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
12110 if (prop_flags
->is_no_transform
)
12111 num
|= XTENSA_PROP_NO_TRANSFORM
;
12112 if (prop_flags
->insn
.is_no_reorder
)
12113 num
|= XTENSA_PROP_INSN_NO_REORDER
;
12114 if (prop_flags
->insn
.is_abslit
)
12115 num
|= XTENSA_PROP_INSN_ABSLIT
;
12117 if (prop_flags
->is_align
)
12119 num
|= XTENSA_PROP_ALIGN
;
12120 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
12128 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
12129 const frag_flags
*prop_flags_2
)
12131 /* Cannot combine with an end marker. */
12133 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
12135 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
12137 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
12140 if (prop_flags_1
->is_insn
)
12142 /* Properties of the beginning of the frag. */
12143 if (prop_flags_2
->insn
.is_loop_target
)
12145 if (prop_flags_2
->insn
.is_branch_target
)
12147 if (prop_flags_1
->insn
.is_no_density
!=
12148 prop_flags_2
->insn
.is_no_density
)
12150 if (prop_flags_1
->is_no_transform
!=
12151 prop_flags_2
->is_no_transform
)
12153 if (prop_flags_1
->insn
.is_no_reorder
!=
12154 prop_flags_2
->insn
.is_no_reorder
)
12156 if (prop_flags_1
->insn
.is_abslit
!=
12157 prop_flags_2
->insn
.is_abslit
)
12161 if (prop_flags_1
->is_align
)
12169 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
12172 unsigned align_bits
;
12174 if (!xt_block
->flags
.is_align
)
12175 return xt_block
->size
;
12177 end_addr
= xt_block
->offset
+ xt_block
->size
;
12178 align_bits
= xt_block
->flags
.alignment
;
12179 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
12180 return end_addr
- xt_block
->offset
;
12185 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
12186 const xtensa_block_info
*xt_block_2
)
12188 if (xt_block
->sec
!= xt_block_2
->sec
)
12190 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
12191 != xt_block_2
->offset
)
12194 if (xt_block_2
->size
== 0
12195 && (!xt_block_2
->flags
.is_unreachable
12196 || xt_block
->flags
.is_unreachable
))
12198 if (xt_block_2
->flags
.is_align
12199 && xt_block
->flags
.is_align
)
12201 /* Nothing needed. */
12202 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
12207 if (xt_block_2
->flags
.is_align
)
12209 /* Push alignment to previous entry. */
12210 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
12211 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12216 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
12217 &xt_block_2
->flags
))
12220 xt_block
->size
+= xt_block_2
->size
;
12222 if (xt_block_2
->flags
.is_align
)
12224 xt_block
->flags
.is_align
= TRUE
;
12225 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12233 add_xt_prop_frags (segT sec
,
12234 xtensa_block_info
**xt_block
,
12235 frag_flags_fn property_function
)
12239 /* Build it if needed. */
12240 while (*xt_block
!= NULL
)
12242 xt_block
= &(*xt_block
)->next
;
12244 /* We are either at NULL at the beginning or at the end. */
12246 /* Walk through the frags. */
12247 if (seg_info (sec
)->frchainP
)
12249 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
12250 fragP
= fragP
->fr_next
)
12252 xtensa_block_info tmp_block
;
12253 tmp_block
.sec
= sec
;
12254 tmp_block
.offset
= fragP
->fr_address
;
12255 tmp_block
.size
= fragP
->fr_fix
;
12256 tmp_block
.next
= NULL
;
12257 property_function (fragP
, &tmp_block
.flags
);
12259 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
12260 /* && fragP->fr_fix != 0) */
12262 if ((*xt_block
) == NULL
12263 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
12265 xtensa_block_info
*new_block
;
12266 if ((*xt_block
) != NULL
)
12267 xt_block
= &(*xt_block
)->next
;
12268 new_block
= XNEW (xtensa_block_info
);
12269 *new_block
= tmp_block
;
12270 *xt_block
= new_block
;
12278 /* op_placement_info_table */
12280 /* op_placement_info makes it easier to determine which
12281 ops can go in which slots. */
12284 init_op_placement_info_table (void)
12286 xtensa_isa isa
= xtensa_default_isa
;
12287 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
12288 xtensa_opcode opcode
;
12291 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
12293 op_placement_table
= XNEWVEC (op_placement_info
, num_opcodes
);
12294 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
12296 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
12298 op_placement_info
*opi
= &op_placement_table
[opcode
];
12299 /* FIXME: Make tinsn allocation dynamic. */
12300 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
12301 as_fatal (_("too many operands in instruction"));
12302 opi
->narrowest
= XTENSA_UNDEFINED
;
12303 opi
->narrowest_size
= 0x7F;
12304 opi
->narrowest_slot
= 0;
12306 opi
->num_formats
= 0;
12308 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
12310 opi
->slots
[fmt
] = 0;
12311 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
12313 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
12315 int fmt_length
= xtensa_format_length (isa
, fmt
);
12317 set_bit (fmt
, opi
->formats
);
12318 set_bit (slot
, opi
->slots
[fmt
]);
12319 if (fmt_length
< opi
->narrowest_size
12320 || (fmt_length
== opi
->narrowest_size
12321 && (xtensa_format_num_slots (isa
, fmt
)
12322 < xtensa_format_num_slots (isa
,
12325 opi
->narrowest
= fmt
;
12326 opi
->narrowest_size
= fmt_length
;
12327 opi
->narrowest_slot
= slot
;
12332 opi
->num_formats
++;
12335 xtensa_insnbuf_free (isa
, ibuf
);
12340 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
12342 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
12346 /* If the opcode is available in a single slot format, return its size. */
12349 xg_get_single_size (xtensa_opcode opcode
)
12351 return op_placement_table
[opcode
].narrowest_size
;
12355 static xtensa_format
12356 xg_get_single_format (xtensa_opcode opcode
)
12358 return op_placement_table
[opcode
].narrowest
;
12363 xg_get_single_slot (xtensa_opcode opcode
)
12365 return op_placement_table
[opcode
].narrowest_slot
;
12369 /* Instruction Stack Functions (from "xtensa-istack.h"). */
12372 istack_init (IStack
*stack
)
12379 istack_empty (IStack
*stack
)
12381 return (stack
->ninsn
== 0);
12386 istack_full (IStack
*stack
)
12388 return (stack
->ninsn
== MAX_ISTACK
);
12392 /* Return a pointer to the top IStack entry.
12393 It is an error to call this if istack_empty () is TRUE. */
12396 istack_top (IStack
*stack
)
12398 int rec
= stack
->ninsn
- 1;
12399 gas_assert (!istack_empty (stack
));
12400 return &stack
->insn
[rec
];
12404 /* Add a new TInsn to an IStack.
12405 It is an error to call this if istack_full () is TRUE. */
12408 istack_push (IStack
*stack
, TInsn
*insn
)
12410 int rec
= stack
->ninsn
;
12411 gas_assert (!istack_full (stack
));
12412 stack
->insn
[rec
] = *insn
;
12417 /* Clear space for the next TInsn on the IStack and return a pointer
12418 to it. It is an error to call this if istack_full () is TRUE. */
12421 istack_push_space (IStack
*stack
)
12423 int rec
= stack
->ninsn
;
12425 gas_assert (!istack_full (stack
));
12426 insn
= &stack
->insn
[rec
];
12433 /* Remove the last pushed instruction. It is an error to call this if
12434 istack_empty () returns TRUE. */
12437 istack_pop (IStack
*stack
)
12439 int rec
= stack
->ninsn
- 1;
12440 gas_assert (!istack_empty (stack
));
12442 tinsn_init (&stack
->insn
[rec
]);
12446 /* TInsn functions. */
12449 tinsn_init (TInsn
*dst
)
12451 memset (dst
, 0, sizeof (TInsn
));
12455 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12458 tinsn_has_symbolic_operands (const TInsn
*insn
)
12461 int n
= insn
->ntok
;
12463 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12465 for (i
= 0; i
< n
; ++i
)
12467 switch (insn
->tok
[i
].X_op
)
12481 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
12483 xtensa_isa isa
= xtensa_default_isa
;
12485 int n
= insn
->ntok
;
12487 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12489 for (i
= 0; i
< n
; ++i
)
12491 switch (insn
->tok
[i
].X_op
)
12499 /* Errors for these types are caught later. */
12504 /* Symbolic immediates are only allowed on the last immediate
12505 operand. At this time, CONST16 is the only opcode where we
12506 support non-PC-relative relocations. */
12507 if (i
!= get_relaxable_immed (insn
->opcode
)
12508 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
12509 && insn
->opcode
!= xtensa_const16_opcode
))
12511 as_bad (_("invalid symbolic operand"));
12520 /* For assembly code with complex expressions (e.g. subtraction),
12521 we have to build them in the literal pool so that
12522 their results are calculated correctly after relaxation.
12523 The relaxation only handles expressions that
12524 boil down to SYMBOL + OFFSET. */
12527 tinsn_has_complex_operands (const TInsn
*insn
)
12530 int n
= insn
->ntok
;
12531 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12532 for (i
= 0; i
< n
; ++i
)
12534 switch (insn
->tok
[i
].X_op
)
12550 /* Encode a TInsn opcode and its constant operands into slotbuf.
12551 Return TRUE if there is a symbol in the immediate field. This
12552 function assumes that:
12553 1) The number of operands are correct.
12554 2) The insn_type is ITYPE_INSN.
12555 3) The opcode can be encoded in the specified format and slot.
12556 4) Operands are either O_constant or O_symbol, and all constants fit. */
12559 tinsn_to_slotbuf (xtensa_format fmt
,
12562 xtensa_insnbuf slotbuf
)
12564 xtensa_isa isa
= xtensa_default_isa
;
12565 xtensa_opcode opcode
= tinsn
->opcode
;
12566 bfd_boolean has_fixup
= FALSE
;
12567 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12570 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
12571 if (noperands
!= tinsn
->ntok
)
12572 as_fatal (_("operand number mismatch"));
12574 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
12576 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12577 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
12581 for (i
= 0; i
< noperands
; i
++)
12583 expressionS
*exp
= &tinsn
->tok
[i
];
12586 const char *file_name
;
12592 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12594 /* The register number has already been checked in
12595 expression_maybe_register, so we don't need to check here. */
12596 opnd_value
= exp
->X_add_number
;
12597 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12598 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
12601 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
12605 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12607 file_name
= as_where (&line
);
12608 /* It is a constant and we called this function
12609 then we have to try to fit it. */
12610 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
12611 exp
->X_add_number
, file_name
, line
);
12624 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12625 into a multi-slot instruction, fill the other slots with NOPs.
12626 Return TRUE if there is a symbol in the immediate field. See also the
12627 assumptions listed for tinsn_to_slotbuf. */
12630 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12632 static xtensa_insnbuf slotbuf
= 0;
12633 static vliw_insn vinsn
;
12634 xtensa_isa isa
= xtensa_default_isa
;
12635 bfd_boolean has_fixup
= FALSE
;
12640 slotbuf
= xtensa_insnbuf_alloc (isa
);
12641 xg_init_vinsn (&vinsn
);
12644 xg_clear_vinsn (&vinsn
);
12646 bundle_tinsn (tinsn
, &vinsn
);
12648 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12650 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12652 /* Only one slot may have a fix-up because the rest contains NOPs. */
12654 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12655 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12662 /* Check the instruction arguments. Return TRUE on failure. */
12665 tinsn_check_arguments (const TInsn
*insn
)
12667 xtensa_isa isa
= xtensa_default_isa
;
12668 xtensa_opcode opcode
= insn
->opcode
;
12669 xtensa_regfile t1_regfile
, t2_regfile
;
12670 int t1_reg
, t2_reg
;
12671 int t1_base_reg
, t1_last_reg
;
12672 int t2_base_reg
, t2_last_reg
;
12673 char t1_inout
, t2_inout
;
12676 if (opcode
== XTENSA_UNDEFINED
)
12678 as_bad (_("invalid opcode"));
12682 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12684 as_bad (_("too few operands"));
12688 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12690 as_bad (_("too many operands"));
12694 /* Check registers. */
12695 for (j
= 0; j
< insn
->ntok
; j
++)
12697 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12700 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12701 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12703 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12705 for (i
= 0; i
< insn
->ntok
; i
++)
12710 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12713 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12715 if (t1_regfile
!= t2_regfile
)
12718 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12719 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12721 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12722 t1_last_reg
= (t1_base_reg
12723 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12725 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12727 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12729 if (t1_reg
!= t2_reg
)
12732 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12734 as_bad (_("multiple writes to the same register"));
12745 /* Load an instruction from its encoded form. */
12748 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12752 xg_init_vinsn (&vinsn
);
12753 vinsn_from_chars (&vinsn
, f
);
12755 *tinsn
= vinsn
.slots
[slot
];
12756 xg_free_vinsn (&vinsn
);
12761 tinsn_from_insnbuf (TInsn
*tinsn
,
12762 xtensa_insnbuf slotbuf
,
12767 xtensa_isa isa
= xtensa_default_isa
;
12769 /* Find the immed. */
12770 tinsn_init (tinsn
);
12771 tinsn
->insn_type
= ITYPE_INSN
;
12772 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12773 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12774 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12775 for (i
= 0; i
< tinsn
->ntok
; i
++)
12777 set_expr_const (&tinsn
->tok
[i
],
12778 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12779 tinsn
->opcode
, i
));
12784 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12787 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12789 xtensa_opcode opcode
= tinsn
->opcode
;
12792 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12794 opnum
= get_relaxable_immed (opcode
);
12795 gas_assert (opnum
>= 0);
12796 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12797 fragP
->tc_frag_data
.slot_symbols
[slot
],
12798 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12800 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12805 get_num_stack_text_bytes (IStack
*istack
)
12808 int text_bytes
= 0;
12810 for (i
= 0; i
< istack
->ninsn
; i
++)
12812 TInsn
*tinsn
= &istack
->insn
[i
];
12813 if (tinsn
->insn_type
== ITYPE_INSN
)
12814 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12821 get_num_stack_literal_bytes (IStack
*istack
)
12826 for (i
= 0; i
< istack
->ninsn
; i
++)
12828 TInsn
*tinsn
= &istack
->insn
[i
];
12829 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12836 /* vliw_insn functions. */
12839 xg_init_vinsn (vliw_insn
*v
)
12842 xtensa_isa isa
= xtensa_default_isa
;
12844 xg_clear_vinsn (v
);
12846 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12847 if (v
->insnbuf
== NULL
)
12848 as_fatal (_("out of memory"));
12850 for (i
= 0; i
< config_max_slots
; i
++)
12852 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12853 if (v
->slotbuf
[i
] == NULL
)
12854 as_fatal (_("out of memory"));
12860 xg_clear_vinsn (vliw_insn
*v
)
12864 memset (v
, 0, offsetof (vliw_insn
, slots
)
12865 + sizeof(TInsn
) * config_max_slots
);
12867 v
->format
= XTENSA_UNDEFINED
;
12869 v
->inside_bundle
= FALSE
;
12871 if (xt_saved_debug_type
!= DEBUG_NONE
)
12872 debug_type
= xt_saved_debug_type
;
12874 for (i
= 0; i
< config_max_slots
; i
++)
12875 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12880 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
12883 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
12884 dst
->insnbuf
= src
->insnbuf
;
12885 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
12890 vinsn_has_specific_opcodes (vliw_insn
*v
)
12894 for (i
= 0; i
< v
->num_slots
; i
++)
12896 if (v
->slots
[i
].is_specific_opcode
)
12904 xg_free_vinsn (vliw_insn
*v
)
12907 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
12908 for (i
= 0; i
< config_max_slots
; i
++)
12909 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
12913 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
12914 operands. See also the assumptions listed for tinsn_to_slotbuf. */
12917 vinsn_to_insnbuf (vliw_insn
*vinsn
,
12920 bfd_boolean record_fixup
)
12922 xtensa_isa isa
= xtensa_default_isa
;
12923 xtensa_format fmt
= vinsn
->format
;
12924 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
12926 bfd_boolean has_fixup
= FALSE
;
12928 xtensa_format_encode (isa
, fmt
, insnbuf
);
12930 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
12932 TInsn
*tinsn
= &vinsn
->slots
[slot
];
12933 expressionS
*extra_arg
= &tinsn
->extra_arg
;
12934 bfd_boolean tinsn_has_fixup
=
12935 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
12936 vinsn
->slotbuf
[slot
]);
12938 xtensa_format_set_slot (isa
, fmt
, slot
,
12939 insnbuf
, vinsn
->slotbuf
[slot
]);
12940 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
12942 if (vinsn
->num_slots
!= 1)
12943 as_bad (_("TLS relocation not allowed in FLIX bundle"));
12944 else if (record_fixup
)
12945 /* Instructions that generate TLS relocations should always be
12946 relaxed in the front-end. If "record_fixup" is set, then this
12947 function is being called during back-end relaxation, so flag
12948 the unexpected behavior as an error. */
12949 as_bad (_("unexpected TLS relocation"));
12951 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
12952 xtensa_format_length (isa
, fmt
),
12953 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
12954 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
12956 if (tinsn_has_fixup
)
12959 xtensa_opcode opcode
= tinsn
->opcode
;
12960 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12963 for (i
= 0; i
< noperands
; i
++)
12965 expressionS
* exp
= &tinsn
->tok
[i
];
12971 if (get_relaxable_immed (opcode
) == i
)
12973 /* Add a fix record for the instruction, except if this
12974 function is being called prior to relaxation, i.e.,
12975 if record_fixup is false, and the instruction might
12976 be relaxed later. */
12978 || tinsn
->is_specific_opcode
12979 || !xg_is_relaxable_insn (tinsn
, 0))
12981 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
12982 frag_offset
- fragP
->fr_literal
);
12986 if (exp
->X_op
!= O_symbol
)
12987 as_bad (_("invalid operand"));
12988 tinsn
->symbol
= exp
->X_add_symbol
;
12989 tinsn
->offset
= exp
->X_add_number
;
12993 as_bad (_("symbolic operand not allowed"));
13001 as_bad (_("expression too complex"));
13013 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
13015 static xtensa_insnbuf insnbuf
= NULL
;
13016 static xtensa_insnbuf slotbuf
= NULL
;
13019 xtensa_isa isa
= xtensa_default_isa
;
13023 insnbuf
= xtensa_insnbuf_alloc (isa
);
13024 slotbuf
= xtensa_insnbuf_alloc (isa
);
13027 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
13028 fmt
= xtensa_format_decode (isa
, insnbuf
);
13029 if (fmt
== XTENSA_UNDEFINED
)
13030 as_fatal (_("cannot decode instruction format"));
13031 vinsn
->format
= fmt
;
13032 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
13034 for (i
= 0; i
< vinsn
->num_slots
; i
++)
13036 TInsn
*tinsn
= &vinsn
->slots
[i
];
13037 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
13038 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
13043 /* Expression utilities. */
13045 /* Return TRUE if the expression is an integer constant. */
13048 expr_is_const (const expressionS
*s
)
13050 return (s
->X_op
== O_constant
);
13054 /* Get the expression constant.
13055 Calling this is illegal if expr_is_const () returns TRUE. */
13058 get_expr_const (const expressionS
*s
)
13060 gas_assert (expr_is_const (s
));
13061 return s
->X_add_number
;
13065 /* Set the expression to a constant value. */
13068 set_expr_const (expressionS
*s
, offsetT val
)
13070 s
->X_op
= O_constant
;
13071 s
->X_add_number
= val
;
13072 s
->X_add_symbol
= NULL
;
13073 s
->X_op_symbol
= NULL
;
13078 expr_is_register (const expressionS
*s
)
13080 return (s
->X_op
== O_register
);
13084 /* Get the expression constant.
13085 Calling this is illegal if expr_is_const () returns TRUE. */
13088 get_expr_register (const expressionS
*s
)
13090 gas_assert (expr_is_register (s
));
13091 return s
->X_add_number
;
13095 /* Set the expression to a symbol + constant offset. */
13098 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
13100 s
->X_op
= O_symbol
;
13101 s
->X_add_symbol
= sym
;
13102 s
->X_op_symbol
= NULL
; /* unused */
13103 s
->X_add_number
= offset
;
13107 /* Return TRUE if the two expressions are equal. */
13110 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
13112 if (s1
->X_op
!= s2
->X_op
)
13114 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
13116 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
13118 if (s1
->X_add_number
!= s2
->X_add_number
)
13125 copy_expr (expressionS
*dst
, const expressionS
*src
)
13127 memcpy (dst
, src
, sizeof (expressionS
));
13131 /* Support for the "--rename-section" option. */
13133 struct rename_section_struct
13135 const char *old_name
;
13137 struct rename_section_struct
*next
;
13140 static struct rename_section_struct
*section_rename
;
13143 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13144 entries to the section_rename list. Note: Specifying multiple
13145 renamings separated by colons is not documented and is retained only
13146 for backward compatibility. */
13149 build_section_rename (const char *arg
)
13151 struct rename_section_struct
*r
;
13152 char *this_arg
= NULL
;
13153 char *next_arg
= NULL
;
13155 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
13157 char *old_name
, *new_name
;
13161 next_arg
= strchr (this_arg
, ':');
13169 old_name
= this_arg
;
13170 new_name
= strchr (this_arg
, '=');
13172 if (*old_name
== '\0')
13174 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13177 if (!new_name
|| new_name
[1] == '\0')
13179 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13186 /* Check for invalid section renaming. */
13187 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13189 if (strcmp (r
->old_name
, old_name
) == 0)
13190 as_bad (_("section %s renamed multiple times"), old_name
);
13191 if (strcmp (r
->new_name
, new_name
) == 0)
13192 as_bad (_("multiple sections remapped to output section %s"),
13197 r
= XNEW (struct rename_section_struct
);
13198 r
->old_name
= xstrdup (old_name
);
13199 r
->new_name
= xstrdup (new_name
);
13200 r
->next
= section_rename
;
13201 section_rename
= r
;
13207 xtensa_section_rename (const char *name
)
13209 struct rename_section_struct
*r
= section_rename
;
13211 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13213 if (strcmp (r
->old_name
, name
) == 0)
13214 return r
->new_name
;
13217 return (char *) name
;