1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2 @c 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa626te} (Faraday FA626TE processor),
106 @code{fa726te} (Faraday FA726TE processor),
125 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
126 @code{i80200} (Intel XScale processor)
127 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
130 The special name @code{all} may be used to allow the
131 assembler to accept instructions valid for any ARM processor.
133 In addition to the basic instruction set, the assembler can be told to
134 accept various extension mnemonics that extend the processor using the
135 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
136 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
137 are currently supported:
143 @cindex @code{-march=} command line option, ARM
144 @item -march=@var{architecture}[+@var{extension}@dots{}]
145 This option specifies the target architecture. The assembler will issue
146 an error message if an attempt is made to assemble an instruction which
147 will not execute on the target architecture. The following architecture
148 names are recognized:
177 If both @code{-mcpu} and
178 @code{-march} are specified, the assembler will use
179 the setting for @code{-mcpu}.
181 The architecture option can be extended with the same instruction set
182 extension options as the @code{-mcpu} option.
184 @cindex @code{-mfpu=} command line option, ARM
185 @item -mfpu=@var{floating-point-format}
187 This option specifies the floating point format to assemble for. The
188 assembler will issue an error message if an attempt is made to assemble
189 an instruction which will not execute on the target floating point unit.
190 The following format options are recognized:
210 @code{vfpv3-d16-fp16},
224 In addition to determining which instructions are assembled, this option
225 also affects the way in which the @code{.double} assembler directive behaves
226 when assembling little-endian code.
228 The default is dependent on the processor selected. For Architecture 5 or
229 later, the default is to assembler for VFP instructions; for earlier
230 architectures the default is to assemble for FPA instructions.
232 @cindex @code{-mthumb} command line option, ARM
234 This option specifies that the assembler should start assembling Thumb
235 instructions; that is, it should behave as though the file starts with a
236 @code{.code 16} directive.
238 @cindex @code{-mthumb-interwork} command line option, ARM
239 @item -mthumb-interwork
240 This option specifies that the output generated by the assembler should
241 be marked as supporting interworking.
243 @cindex @code{-mimplicit-it} command line option, ARM
244 @item -mimplicit-it=never
245 @itemx -mimplicit-it=always
246 @itemx -mimplicit-it=arm
247 @itemx -mimplicit-it=thumb
248 The @code{-mimplicit-it} option controls the behavior of the assembler when
249 conditional instructions are not enclosed in IT blocks.
250 There are four possible behaviors.
251 If @code{never} is specified, such constructs cause a warning in ARM
252 code and an error in Thumb-2 code.
253 If @code{always} is specified, such constructs are accepted in both
254 ARM and Thumb-2 code, where the IT instruction is added implicitly.
255 If @code{arm} is specified, such constructs are accepted in ARM code
256 and cause an error in Thumb-2 code.
257 If @code{thumb} is specified, such constructs cause a warning in ARM
258 code and are accepted in Thumb-2 code. If you omit this option, the
259 behavior is equivalent to @code{-mimplicit-it=arm}.
261 @cindex @code{-mapcs-26} command line option, ARM
262 @cindex @code{-mapcs-32} command line option, ARM
265 These options specify that the output generated by the assembler should
266 be marked as supporting the indicated version of the Arm Procedure.
269 @cindex @code{-matpcs} command line option, ARM
271 This option specifies that the output generated by the assembler should
272 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
273 enabled this option will cause the assembler to create an empty
274 debugging section in the object file called .arm.atpcs. Debuggers can
275 use this to determine the ABI being used by.
277 @cindex @code{-mapcs-float} command line option, ARM
279 This indicates the floating point variant of the APCS should be
280 used. In this variant floating point arguments are passed in FP
281 registers rather than integer registers.
283 @cindex @code{-mapcs-reentrant} command line option, ARM
284 @item -mapcs-reentrant
285 This indicates that the reentrant variant of the APCS should be used.
286 This variant supports position independent code.
288 @cindex @code{-mfloat-abi=} command line option, ARM
289 @item -mfloat-abi=@var{abi}
290 This option specifies that the output generated by the assembler should be
291 marked as using specified floating point ABI.
292 The following values are recognized:
298 @cindex @code{-eabi=} command line option, ARM
299 @item -meabi=@var{ver}
300 This option specifies which EABI version the produced object files should
302 The following values are recognized:
308 @cindex @code{-EB} command line option, ARM
310 This option specifies that the output generated by the assembler should
311 be marked as being encoded for a big-endian processor.
313 @cindex @code{-EL} command line option, ARM
315 This option specifies that the output generated by the assembler should
316 be marked as being encoded for a little-endian processor.
318 @cindex @code{-k} command line option, ARM
319 @cindex PIC code generation for ARM
321 This option specifies that the output of the assembler should be marked
322 as position-independent code (PIC).
324 @cindex @code{--fix-v4bx} command line option, ARM
326 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
327 the linker option of the same name.
329 @cindex @code{-mwarn-deprecated} command line option, ARM
330 @item -mwarn-deprecated
331 @itemx -mno-warn-deprecated
332 Enable or disable warnings about using deprecated options or
333 features. The default is to warn.
341 * ARM-Instruction-Set:: Instruction Set
342 * ARM-Chars:: Special Characters
343 * ARM-Regs:: Register Names
344 * ARM-Relocations:: Relocations
345 * ARM-Neon-Alignment:: NEON Alignment Specifiers
348 @node ARM-Instruction-Set
349 @subsection Instruction Set Syntax
350 Two slightly different syntaxes are support for ARM and THUMB
351 instructions. The default, @code{divided}, uses the old style where
352 ARM and THUMB instructions had their own, separate syntaxes. The new,
353 @code{unified} syntax, which can be selected via the @code{.syntax}
354 directive, and has the following main features:
358 Immediate operands do not require a @code{#} prefix.
361 The @code{IT} instruction may appear, and if it does it is validated
362 against subsequent conditional affixes. In ARM mode it does not
363 generate machine code, in THUMB mode it does.
366 For ARM instructions the conditional affixes always appear at the end
367 of the instruction. For THUMB instructions conditional affixes can be
368 used, but only inside the scope of an @code{IT} instruction.
371 All of the instructions new to the V6T2 architecture (and later) are
372 available. (Only a few such instructions can be written in the
373 @code{divided} syntax).
376 The @code{.N} and @code{.W} suffixes are recognized and honored.
379 All instructions set the flags if and only if they have an @code{s}
384 @subsection Special Characters
386 @cindex line comment character, ARM
387 @cindex ARM line comment character
388 The presence of a @samp{@@} on a line indicates the start of a comment
389 that extends to the end of the current line. If a @samp{#} appears as
390 the first character of a line, the whole line is treated as a comment.
392 @cindex line separator, ARM
393 @cindex statement separator, ARM
394 @cindex ARM line separator
395 The @samp{;} character can be used instead of a newline to separate
398 @cindex immediate character, ARM
399 @cindex ARM immediate character
400 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
402 @cindex identifiers, ARM
403 @cindex ARM identifiers
404 *TODO* Explain about /data modifier on symbols.
407 @subsection Register Names
409 @cindex ARM register names
410 @cindex register names, ARM
411 *TODO* Explain about ARM register naming, and the predefined names.
413 @node ARM-Neon-Alignment
414 @subsection NEON Alignment Specifiers
416 @cindex alignment for NEON instructions
417 Some NEON load/store instructions allow an optional address
419 The ARM documentation specifies that this is indicated by
420 @samp{@@ @var{align}}. However GAS already interprets
421 the @samp{@@} character as a "line comment" start,
422 so @samp{: @var{align}} is used instead. For example:
425 vld1.8 @{q0@}, [r0, :128]
428 @node ARM Floating Point
429 @section Floating Point
431 @cindex floating point, ARM (@sc{ieee})
432 @cindex ARM floating point (@sc{ieee})
433 The ARM family uses @sc{ieee} floating-point numbers.
435 @node ARM-Relocations
436 @subsection ARM relocation generation
438 @cindex data relocations, ARM
439 @cindex ARM data relocations
440 Specific data relocations can be generated by putting the relocation name
441 in parentheses after the symbol name. For example:
447 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
449 The following relocations are supported:
463 For compatibility with older toolchains the assembler also accepts
464 @code{(PLT)} after branch targets. This will generate the deprecated
465 @samp{R_ARM_PLT32} relocation.
467 @cindex MOVW and MOVT relocations, ARM
468 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
469 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
470 respectively. For example to load the 32-bit address of foo into r0:
473 MOVW r0, #:lower16:foo
474 MOVT r0, #:upper16:foo
478 @section ARM Machine Directives
480 @cindex machine directives, ARM
481 @cindex ARM machine directives
484 @c AAAAAAAAAAAAAAAAAAAAAAAAA
486 @cindex @code{.2byte} directive, ARM
487 @cindex @code{.4byte} directive, ARM
488 @cindex @code{.8byte} directive, ARM
489 @item .2byte @var{expression} [, @var{expression}]*
490 @itemx .4byte @var{expression} [, @var{expression}]*
491 @itemx .8byte @var{expression} [, @var{expression}]*
492 These directives write 2, 4 or 8 byte values to the output section.
494 @cindex @code{.align} directive, ARM
495 @item .align @var{expression} [, @var{expression}]
496 This is the generic @var{.align} directive. For the ARM however if the
497 first argument is zero (ie no alignment is needed) the assembler will
498 behave as if the argument had been 2 (ie pad to the next four byte
499 boundary). This is for compatibility with ARM's own assembler.
501 @cindex @code{.arch} directive, ARM
502 @item .arch @var{name}
503 Select the target architecture. Valid values for @var{name} are the same as
504 for the @option{-march} commandline option.
506 @cindex @code{.arm} directive, ARM
508 This performs the same action as @var{.code 32}.
511 @cindex @code{.pad} directive, ARM
512 @item .pad #@var{count}
513 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
514 A positive value indicates the function prologue allocated stack space by
515 decrementing the stack pointer.
517 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
519 @cindex @code{.bss} directive, ARM
521 This directive switches to the @code{.bss} section.
523 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
525 @cindex @code{.cantunwind} directive, ARM
527 Prevents unwinding through the current function. No personality routine
528 or exception table data is required or permitted.
530 @cindex @code{.code} directive, ARM
531 @item .code @code{[16|32]}
532 This directive selects the instruction set being generated. The value 16
533 selects Thumb, with the value 32 selecting ARM.
535 @cindex @code{.cpu} directive, ARM
536 @item .cpu @var{name}
537 Select the target processor. Valid values for @var{name} are the same as
538 for the @option{-mcpu} commandline option.
540 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
542 @cindex @code{.dn} and @code{.qn} directives, ARM
543 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
544 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
546 The @code{dn} and @code{qn} directives are used to create typed
547 and/or indexed register aliases for use in Advanced SIMD Extension
548 (Neon) instructions. The former should be used to create aliases
549 of double-precision registers, and the latter to create aliases of
550 quad-precision registers.
552 If these directives are used to create typed aliases, those aliases can
553 be used in Neon instructions instead of writing types after the mnemonic
554 or after each operand. For example:
563 This is equivalent to writing the following:
569 Aliases created using @code{dn} or @code{qn} can be destroyed using
572 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
574 @cindex @code{.eabi_attribute} directive, ARM
575 @item .eabi_attribute @var{tag}, @var{value}
576 Set the EABI object attribute @var{tag} to @var{value}.
578 The @var{tag} is either an attribute number, or one of the following:
579 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
580 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
581 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
582 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
583 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
584 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
585 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
586 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
587 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
588 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
589 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
590 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
591 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
592 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
593 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
594 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
595 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
596 @code{Tag_conformance}, @code{Tag_T2EE_use},
597 @code{Tag_Virtualization_use}
599 The @var{value} is either a @code{number}, @code{"string"}, or
600 @code{number, "string"} depending on the tag.
602 Note - the following legacy values are also accepted by @var{tag}:
603 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
604 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
606 @cindex @code{.even} directive, ARM
608 This directive aligns to an even-numbered address.
610 @cindex @code{.extend} directive, ARM
611 @cindex @code{.ldouble} directive, ARM
612 @item .extend @var{expression} [, @var{expression}]*
613 @itemx .ldouble @var{expression} [, @var{expression}]*
614 These directives write 12byte long double floating-point values to the
615 output section. These are not compatible with current ARM processors
618 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
621 @cindex @code{.fnend} directive, ARM
623 Marks the end of a function with an unwind table entry. The unwind index
624 table entry is created when this directive is processed.
626 If no personality routine has been specified then standard personality
627 routine 0 or 1 will be used, depending on the number of unwind opcodes
631 @cindex @code{.fnstart} directive, ARM
633 Marks the start of a function with an unwind table entry.
635 @cindex @code{.force_thumb} directive, ARM
637 This directive forces the selection of Thumb instructions, even if the
638 target processor does not support those instructions
640 @cindex @code{.fpu} directive, ARM
641 @item .fpu @var{name}
642 Select the floating-point unit to assemble for. Valid values for @var{name}
643 are the same as for the @option{-mfpu} commandline option.
645 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
646 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
648 @cindex @code{.handlerdata} directive, ARM
650 Marks the end of the current function, and the start of the exception table
651 entry for that function. Anything between this directive and the
652 @code{.fnend} directive will be added to the exception table entry.
654 Must be preceded by a @code{.personality} or @code{.personalityindex}
657 @c IIIIIIIIIIIIIIIIIIIIIIIIII
659 @cindex @code{.inst} directive, ARM
660 @item .inst @var{opcode} [ , @dots{} ]
661 @itemx .inst.n @var{opcode} [ , @dots{} ]
662 @itemx .inst.w @var{opcode} [ , @dots{} ]
663 Generates the instruction corresponding to the numerical value @var{opcode}.
664 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
665 specified explicitly, overriding the normal encoding rules.
667 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
668 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
669 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
671 @item .ldouble @var{expression} [, @var{expression}]*
674 @cindex @code{.ltorg} directive, ARM
676 This directive causes the current contents of the literal pool to be
677 dumped into the current section (which is assumed to be the .text
678 section) at the current location (aligned to a word boundary).
679 @code{GAS} maintains a separate literal pool for each section and each
680 sub-section. The @code{.ltorg} directive will only affect the literal
681 pool of the current section and sub-section. At the end of assembly
682 all remaining, un-empty literal pools will automatically be dumped.
684 Note - older versions of @code{GAS} would dump the current literal
685 pool any time a section change occurred. This is no longer done, since
686 it prevents accurate control of the placement of literal pools.
688 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
690 @cindex @code{.movsp} directive, ARM
691 @item .movsp @var{reg} [, #@var{offset}]
692 Tell the unwinder that @var{reg} contains an offset from the current
693 stack pointer. If @var{offset} is not specified then it is assumed to be
696 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
697 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
699 @cindex @code{.object_arch} directive, ARM
700 @item .object_arch @var{name}
701 Override the architecture recorded in the EABI object attribute section.
702 Valid values for @var{name} are the same as for the @code{.arch} directive.
703 Typically this is useful when code uses runtime detection of CPU features.
705 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
707 @cindex @code{.packed} directive, ARM
708 @item .packed @var{expression} [, @var{expression}]*
709 This directive writes 12-byte packed floating-point values to the
710 output section. These are not compatible with current ARM processors
713 @cindex @code{.pad} directive, ARM
714 @item .pad #@var{count}
715 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
716 A positive value indicates the function prologue allocated stack space by
717 decrementing the stack pointer.
719 @cindex @code{.personality} directive, ARM
720 @item .personality @var{name}
721 Sets the personality routine for the current function to @var{name}.
723 @cindex @code{.personalityindex} directive, ARM
724 @item .personalityindex @var{index}
725 Sets the personality routine for the current function to the EABI standard
726 routine number @var{index}
728 @cindex @code{.pool} directive, ARM
730 This is a synonym for .ltorg.
732 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
733 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
735 @cindex @code{.req} directive, ARM
736 @item @var{name} .req @var{register name}
737 This creates an alias for @var{register name} called @var{name}. For
744 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
747 @cindex @code{.save} directive, ARM
748 @item .save @var{reglist}
749 Generate unwinder annotations to restore the registers in @var{reglist}.
750 The format of @var{reglist} is the same as the corresponding store-multiple
754 @exdent @emph{core registers}
755 .save @{r4, r5, r6, lr@}
756 stmfd sp!, @{r4, r5, r6, lr@}
757 @exdent @emph{FPA registers}
760 @exdent @emph{VFP registers}
761 .save @{d8, d9, d10@}
762 fstmdx sp!, @{d8, d9, d10@}
763 @exdent @emph{iWMMXt registers}
765 wstrd wr11, [sp, #-8]!
766 wstrd wr10, [sp, #-8]!
769 wstrd wr11, [sp, #-8]!
771 wstrd wr10, [sp, #-8]!
775 @cindex @code{.setfp} directive, ARM
776 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
777 Make all unwinder annotations relative to a frame pointer. Without this
778 the unwinder will use offsets from the stack pointer.
780 The syntax of this directive is the same as the @code{add} or @code{mov}
781 instruction used to set the frame pointer. @var{spreg} must be either
782 @code{sp} or mentioned in a previous @code{.movsp} directive.
792 @cindex @code{.secrel32} directive, ARM
793 @item .secrel32 @var{expression} [, @var{expression}]*
794 This directive emits relocations that evaluate to the section-relative
795 offset of each expression's symbol. This directive is only supported
798 @cindex @code{.syntax} directive, ARM
799 @item .syntax [@code{unified} | @code{divided}]
800 This directive sets the Instruction Set Syntax as described in the
801 @ref{ARM-Instruction-Set} section.
803 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
805 @cindex @code{.thumb} directive, ARM
807 This performs the same action as @var{.code 16}.
809 @cindex @code{.thumb_func} directive, ARM
811 This directive specifies that the following symbol is the name of a
812 Thumb encoded function. This information is necessary in order to allow
813 the assembler and linker to generate correct code for interworking
814 between Arm and Thumb instructions and should be used even if
815 interworking is not going to be performed. The presence of this
816 directive also implies @code{.thumb}
818 This directive is not neccessary when generating EABI objects. On these
819 targets the encoding is implicit when generating Thumb code.
821 @cindex @code{.thumb_set} directive, ARM
823 This performs the equivalent of a @code{.set} directive in that it
824 creates a symbol which is an alias for another symbol (possibly not yet
825 defined). This directive also has the added property in that it marks
826 the aliased symbol as being a thumb function entry point, in the same
827 way that the @code{.thumb_func} directive does.
829 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
831 @cindex @code{.unreq} directive, ARM
832 @item .unreq @var{alias-name}
833 This undefines a register alias which was previously defined using the
834 @code{req}, @code{dn} or @code{qn} directives. For example:
841 An error occurs if the name is undefined. Note - this pseudo op can
842 be used to delete builtin in register name aliases (eg 'r0'). This
843 should only be done if it is really necessary.
845 @cindex @code{.unwind_raw} directive, ARM
846 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
847 Insert one of more arbitary unwind opcode bytes, which are known to adjust
848 the stack pointer by @var{offset} bytes.
850 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
853 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
855 @cindex @code{.vsave} directive, ARM
856 @item .vsave @var{vfp-reglist}
857 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
858 using FLDMD. Also works for VFPv3 registers
859 that are to be restored using VLDM.
860 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
864 @exdent @emph{VFP registers}
865 .vsave @{d8, d9, d10@}
866 fstmdd sp!, @{d8, d9, d10@}
867 @exdent @emph{VFPv3 registers}
868 .vsave @{d15, d16, d17@}
869 vstm sp!, @{d15, d16, d17@}
872 Since FLDMX and FSTMX are now deprecated, this directive should be
873 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
875 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
876 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
877 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
878 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
886 @cindex opcodes for ARM
887 @code{@value{AS}} implements all the standard ARM opcodes. It also
888 implements several pseudo opcodes, including several synthetic load
893 @cindex @code{NOP} pseudo op, ARM
899 This pseudo op will always evaluate to a legal ARM instruction that does
900 nothing. Currently it will evaluate to MOV r0, r0.
902 @cindex @code{LDR reg,=<label>} pseudo op, ARM
905 ldr <register> , = <expression>
908 If expression evaluates to a numeric constant then a MOV or MVN
909 instruction will be used in place of the LDR instruction, if the
910 constant can be generated by either of these instructions. Otherwise
911 the constant will be placed into the nearest literal pool (if it not
912 already there) and a PC relative LDR instruction will be generated.
914 @cindex @code{ADR reg,<label>} pseudo op, ARM
917 adr <register> <label>
920 This instruction will load the address of @var{label} into the indicated
921 register. The instruction will evaluate to a PC relative ADD or SUB
922 instruction depending upon where the label is located. If the label is
923 out of range, or if it is not defined in the same file (and section) as
924 the ADR instruction, then an error will be generated. This instruction
925 will not make use of the literal pool.
927 @cindex @code{ADRL reg,<label>} pseudo op, ARM
930 adrl <register> <label>
933 This instruction will load the address of @var{label} into the indicated
934 register. The instruction will evaluate to one or two PC relative ADD
935 or SUB instructions depending upon where the label is located. If a
936 second instruction is not needed a NOP instruction will be generated in
937 its place, so that this instruction is always 8 bytes long.
939 If the label is out of range, or if it is not defined in the same file
940 (and section) as the ADRL instruction, then an error will be generated.
941 This instruction will not make use of the literal pool.
945 For information on the ARM or Thumb instruction sets, see @cite{ARM
946 Software Development Toolkit Reference Manual}, Advanced RISC Machines
949 @node ARM Mapping Symbols
950 @section Mapping Symbols
952 The ARM ELF specification requires that special symbols be inserted
953 into object files to mark certain features:
959 At the start of a region of code containing ARM instructions.
963 At the start of a region of code containing THUMB instructions.
967 At the start of a region of data.
971 The assembler will automatically insert these symbols for you - there
972 is no need to code them yourself. Support for tagging symbols ($b,
973 $f, $p and $m) which is also mentioned in the current ARM ELF
974 specification is not implemented. This is because they have been
975 dropped from the new EABI and so tools cannot rely upon their
978 @node ARM Unwinding Tutorial
981 The ABI for the ARM Architecture specifies a standard format for
982 exception unwind information. This information is used when an
983 exception is thrown to determine where control should be transferred.
984 In particular, the unwind information is used to determine which
985 function called the function that threw the exception, and which
986 function called that one, and so forth. This information is also used
987 to restore the values of callee-saved registers in the function
988 catching the exception.
990 If you are writing functions in assembly code, and those functions
991 call other functions that throw exceptions, you must use assembly
992 pseudo ops to ensure that appropriate exception unwind information is
993 generated. Otherwise, if one of the functions called by your assembly
994 code throws an exception, the run-time library will be unable to
995 unwind the stack through your assembly code and your program will not
998 To illustrate the use of these pseudo ops, we will examine the code
999 that G++ generates for the following C++ input:
1002 void callee (int *);
1013 This example does not show how to throw or catch an exception from
1014 assembly code. That is a much more complex operation and should
1015 always be done in a high-level language, such as C++, that directly
1016 supports exceptions.
1018 The code generated by one particular version of G++ when compiling the
1025 @ Function supports interworking.
1026 @ args = 0, pretend = 0, frame = 8
1027 @ frame_needed = 1, uses_anonymous_args = 0
1049 Of course, the sequence of instructions varies based on the options
1050 you pass to GCC and on the version of GCC in use. The exact
1051 instructions are not important since we are focusing on the pseudo ops
1052 that are used to generate unwind information.
1054 An important assumption made by the unwinder is that the stack frame
1055 does not change during the body of the function. In particular, since
1056 we assume that the assembly code does not itself throw an exception,
1057 the only point where an exception can be thrown is from a call, such
1058 as the @code{bl} instruction above. At each call site, the same saved
1059 registers (including @code{lr}, which indicates the return address)
1060 must be located in the same locations relative to the frame pointer.
1062 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1063 op appears immediately before the first instruction of the function
1064 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1065 op appears immediately after the last instruction of the function.
1066 These pseudo ops specify the range of the function.
1068 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1069 @code{.pad}) matters; their exact locations are irrelevant. In the
1070 example above, the compiler emits the pseudo ops with particular
1071 instructions. That makes it easier to understand the code, but it is
1072 not required for correctness. It would work just as well to emit all
1073 of the pseudo ops other than @code{.fnend} in the same order, but
1074 immediately after @code{.fnstart}.
1076 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1077 indicates registers that have been saved to the stack so that they can
1078 be restored before the function returns. The argument to the
1079 @code{.save} pseudo op is a list of registers to save. If a register
1080 is ``callee-saved'' (as specified by the ABI) and is modified by the
1081 function you are writing, then your code must save the value before it
1082 is modified and restore the original value before the function
1083 returns. If an exception is thrown, the run-time library restores the
1084 values of these registers from their locations on the stack before
1085 returning control to the exception handler. (Of course, if an
1086 exception is not thrown, the function that contains the @code{.save}
1087 pseudo op restores these registers in the function epilogue, as is
1088 done with the @code{ldmfd} instruction above.)
1090 You do not have to save callee-saved registers at the very beginning
1091 of the function and you do not need to use the @code{.save} pseudo op
1092 immediately following the point at which the registers are saved.
1093 However, if you modify a callee-saved register, you must save it on
1094 the stack before modifying it and before calling any functions which
1095 might throw an exception. And, you must use the @code{.save} pseudo
1096 op to indicate that you have done so.
1098 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1099 modification of the stack pointer that does not save any registers.
1100 The argument is the number of bytes (in decimal) that are subtracted
1101 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1102 subtracting from the stack pointer increases the size of the stack.)
1104 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1105 indicates the register that contains the frame pointer. The first
1106 argument is the register that is set, which is typically @code{fp}.
1107 The second argument indicates the register from which the frame
1108 pointer takes its value. The third argument, if present, is the value
1109 (in decimal) added to the register specified by the second argument to
1110 compute the value of the frame pointer. You should not modify the
1111 frame pointer in the body of the function.
1113 If you do not use a frame pointer, then you should not use the
1114 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1115 should avoid modifying the stack pointer outside of the function
1116 prologue. Otherwise, the run-time library will be unable to find
1117 saved registers when it is unwinding the stack.
1119 The pseudo ops described above are sufficient for writing assembly
1120 code that calls functions which may throw exceptions. If you need to
1121 know more about the object-file format used to represent unwind
1122 information, you may consult the @cite{Exception Handling ABI for the
1123 ARM Architecture} available from @uref{http://infocenter.arm.com}.