1 2020-05-01 Andreas Tobler <andreast@gcc.gnu.org>
3 * config/i386/i386.h: Define a new macro: SUBTARGET_SHADOW_OFFSET.
4 * config/i386/i386.c (ix86_asan_shadow_offset): Use this macro.
5 * config/i386/darwin.h: Override the SUBTARGET_SHADOW_OFFSET macro.
6 * config/i386/freebsd.h: Likewise.
7 * config/freebsd.h (LIBASAN_EARLY_SPEC): Define.
8 LIBTSAN_EARLY_SPEC): Likewise. (LIBLSAN_EARLY_SPEC): Likewise.
10 2020-04-30 Alexandre Oliva <oliva@adacore.com>
12 * doc/sourcebuild.texi (Effective-Target Keywords): Document
13 the newly-introduced fileio effective target.
15 2020-04-30 Richard Sandiford <richard.sandiford@arm.com>
17 PR rtl-optimization/94740
18 * cse.c (cse_process_notes_1): Replace with...
19 (cse_process_note_1): ...this new function, acting as a
20 simplify_replace_fn_rtx callback to process_note. Handle only
21 REGs and MEMs directly. Validate the MEM if cse_process_note
23 (cse_process_notes): Replace with...
24 (cse_process_note): ...this new function.
25 (cse_extended_basic_block): Update accordingly, iterating over
26 the register notes and passing individual notes to cse_process_note.
28 2020-04-30 Carl Love <cel@us.ibm.com>
30 * config/rs6000/emmintrin.h (_mm_movemask_epi8): Fix comment.
32 2020-04-30 Martin Jambor <mjambor@suse.cz>
35 * cgraph.c (clone_of_p): Also consider thunks whih had their bodies
36 saved by the inliner and thunks which had their call inlined.
37 * ipa-inline-transform.c (save_inline_function_body): Fill in
38 former_clone_of of new body holders.
40 2020-04-30 Jakub Jelinek <jakub@redhat.com>
42 * BASE-VER: Set to 11.0.0.
44 2020-04-30 Jonathan Wakely <jwakely@redhat.com>
46 * pretty-print.c (pp_take_prefix): Fix spelling in comment.
48 2020-04-30 Marek Polacek <polacek@redhat.com>
51 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
52 (check_aligned_type): Check if TYPE_USER_ALIGN match.
54 2020-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
56 * config/aarch64/aarch64.h (TARGET_OUTLINE_ATOMICS): Define.
57 * config/aarch64/aarch64.opt (moutline-atomics): Change to Int variable.
58 * doc/invoke.texi (moutline-atomics): Document as on by default.
60 2020-04-30 Szabolcs Nagy <szabolcs.nagy@arm.com>
63 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Remove
64 the check for NOTE_INSN_DELETED_LABEL.
66 2020-04-30 Jakub Jelinek <jakub@redhat.com>
68 * configure.ac (--with-documentation-root-url,
69 --with-changes-root-url): Diagnose URL not ending with /,
70 use AC_DEFINE_UNQUOTED instead of AC_SUBST.
71 * opts.h (get_changes_url): Remove.
72 * opts.c (get_changes_url): Remove.
73 * Makefile.in (CFLAGS-opts.o): Don't add -DDOCUMENTATION_ROOT_URL
74 or -DCHANGES_ROOT_URL.
75 * doc/install.texi (--with-documentation-root-url,
76 --with-changes-root-url): Document.
77 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Don't call
78 get_changes_url and free, change url variable type to const char * and
79 set it to CHANGES_ROOT_URL "gcc-10/changes.html#empty_base".
80 * config/s390/s390.c (s390_function_arg_vector,
81 s390_function_arg_float): Likewise.
82 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
84 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
86 * config.in: Regenerate.
87 * configure: Regenerate.
89 2020-04-30 Christophe Lyon <christophe.lyon@linaro.org>
92 * config/arm/arm.c (isr_attribute_args): Remove duplicate entries.
94 2020-04-30 Andreas Krebbel <krebbel@linux.ibm.com>
96 * config/s390/constraints.md ("j>f", "jb4"): New constraints.
97 * config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix
99 * config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a
101 ("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst.
102 Change constraint for vlrl/vstrl to jb4.
104 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
106 * var-tracking.c (vt_initialize): Move variables pre and post
107 into inner block and initialize both in order to fix warning
108 about uninitialized use. Remove unnecessary checks for
109 frame_pointer_needed.
111 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
113 * toplev.c (output_stack_usage_1): Ensure that first
114 argument to fprintf is not null.
116 2020-04-29 Jakub Jelinek <jakub@redhat.com>
118 * configure.ac (-with-changes-root-url): New configure option,
119 defaulting to https://gcc.gnu.org/.
120 * Makefile.in (CFLAGS-opts.o): Define CHANGES_ROOT_URL for
122 * pretty-print.c (get_end_url_string): New function.
123 (pp_format): Handle %{ and %} for URLs.
124 (pp_begin_url): Use pp_string instead of pp_printf.
125 (pp_end_url): Use get_end_url_string.
126 * opts.h (get_changes_url): Declare.
127 * opts.c (get_changes_url): New function.
128 * config/rs6000/rs6000-call.c: Include opts.h.
129 (rs6000_discover_homogeneous_aggregate): Use %{in GCC 10.1%} instead
130 of just in GCC 10.1 in diagnostics and add URL.
131 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Likewise.
132 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
134 * config/s390/s390.c (s390_function_arg_vector,
135 s390_function_arg_float): Likewise.
136 * configure: Regenerated.
139 * config/s390/s390.c (s390_function_arg_vector,
140 s390_function_arg_float): Use DECL_FIELD_ABI_IGNORED instead of
141 cxx17_empty_base_field_p. In -Wpsabi diagnostics use the type
142 passed to the function rather than the type of the single element.
143 Rename cxx17_empty_base_seen variable to empty_base_seen, change
144 type to int, and adjust diagnostics depending on if the field
145 has [[no_unique_attribute]] or not.
148 * config/i386/avx512bwintrin.h (_mm512_alignr_epi8,
149 _mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands
150 used in casts into parens.
151 * config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph,
152 _mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph,
153 _mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph,
154 _mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask,
155 _mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask,
156 _mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask,
157 _mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise.
158 * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8,
159 _mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8,
160 _mm256_mask_cmp_epu8_mask): Likewise.
161 * config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph,
162 _mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise.
163 * config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise.
164 * config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise.
167 * config/i386/avx2intrin.h (_mm_mask_i32gather_pd,
168 _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd,
169 _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps,
170 _mm256_mask_i32gather_ps, _mm_mask_i64gather_ps,
171 _mm256_mask_i64gather_ps, _mm_i32gather_epi64,
172 _mm_mask_i32gather_epi64, _mm256_i32gather_epi64,
173 _mm256_mask_i32gather_epi64, _mm_i64gather_epi64,
174 _mm_mask_i64gather_epi64, _mm256_i64gather_epi64,
175 _mm256_mask_i64gather_epi64, _mm_i32gather_epi32,
176 _mm_mask_i32gather_epi32, _mm256_i32gather_epi32,
177 _mm256_mask_i32gather_epi32, _mm_i64gather_epi32,
178 _mm_mask_i64gather_epi32, _mm256_i64gather_epi32,
179 _mm256_mask_i64gather_epi32): Surround macro parameter uses with
181 (_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd,
182 _mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps,
183 _mm_i64gather_ps, _mm256_i64gather_ps): Likewise. Don't use
184 as mask vector containing -1.0 or -1.0f elts, but instead vector
185 with all bits set using _mm*_cmpeq_p? with zero operands.
186 * config/i386/avx512fintrin.h (_mm512_i32gather_ps,
187 _mm512_mask_i32gather_ps, _mm512_i32gather_pd,
188 _mm512_mask_i32gather_pd, _mm512_i64gather_ps,
189 _mm512_mask_i64gather_ps, _mm512_i64gather_pd,
190 _mm512_mask_i64gather_pd, _mm512_i32gather_epi32,
191 _mm512_mask_i32gather_epi32, _mm512_i32gather_epi64,
192 _mm512_mask_i32gather_epi64, _mm512_i64gather_epi32,
193 _mm512_mask_i64gather_epi32, _mm512_i64gather_epi64,
194 _mm512_mask_i64gather_epi64, _mm512_i32scatter_ps,
195 _mm512_mask_i32scatter_ps, _mm512_i32scatter_pd,
196 _mm512_mask_i32scatter_pd, _mm512_i64scatter_ps,
197 _mm512_mask_i64scatter_ps, _mm512_i64scatter_pd,
198 _mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32,
199 _mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64,
200 _mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32,
201 _mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64,
202 _mm512_mask_i64scatter_epi64): Surround macro parameter uses with
204 * config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd,
205 _mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd,
206 _mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd,
207 _mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd,
208 _mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd,
209 _mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd,
210 _mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd,
211 _mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd,
212 _mm512_mask_prefetch_i64scatter_ps): Likewise.
213 * config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps,
214 _mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd,
215 _mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps,
216 _mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd,
217 _mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32,
218 _mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64,
219 _mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32,
220 _mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64,
221 _mm_mmask_i64gather_epi64, _mm256_i32scatter_ps,
222 _mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps,
223 _mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd,
224 _mm_mask_i32scatter_pd, _mm256_i64scatter_ps,
225 _mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps,
226 _mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd,
227 _mm_mask_i64scatter_pd, _mm256_i32scatter_epi32,
228 _mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32,
229 _mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64,
230 _mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64,
231 _mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32,
232 _mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32,
233 _mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64,
234 _mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64,
235 _mm_mask_i64scatter_epi64): Likewise.
237 2020-04-29 Jeff Law <law@redhat.com>
239 * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific
240 division instructions are 4 bytes long.
242 2020-04-29 Jakub Jelinek <jakub@redhat.com>
245 * config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use
246 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
247 fenv_var, fenv_clear and old_fenv variables. For fenv_addr
248 take address of TARGET_EXPR of fenv_var with void_node initializer.
251 2020-04-29 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
253 PR tree-optimization/94774
254 * gimple-ssa-sprintf.c (try_substitute_return_value): Initialize
257 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
259 * calls.h (cxx17_empty_base_field_p): Turn into a function declaration.
260 * calls.c (cxx17_empty_base_field_p): New function. Check
261 DECL_ARTIFICIAL and RECORD_OR_UNION_TYPE_P in addition to the
264 2020-04-29 H.J. Lu <hongjiu.lu@intel.com>
267 * config/i386/i386-options.c (ix86_set_indirect_branch_type):
268 Allow -fcf-protection with -mindirect-branch=thunk-extern and
269 -mfunction-return=thunk-extern.
270 * doc/invoke.texi: Update notes for -fcf-protection=branch with
271 -mindirect-branch=thunk-extern and -mindirect-return=thunk-extern.
273 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
275 * doc/sourcebuild.texi: Add missing arm_arch_v8a_hard_ok anchor.
277 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
279 * config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
280 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
281 fenv_var and new_fenv_var.
283 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
285 * doc/sourcebuild.texi (arm_arch_v8a_hard_ok): Document new
286 effective-target keyword.
287 (arm_arch_v8a_hard_multilib): Likewise.
288 (arm_arch_v8a_hard): Document new dg-add-options keyword.
289 * config/arm/arm.c (arm_return_in_memory): Note that the APCS
290 code is deprecated and has not been updated to handle
291 DECL_FIELD_ABI_IGNORED.
292 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
293 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
294 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
295 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
296 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
297 something actually is a HFA or HVA. Record whether we see a
298 [[no_unique_address]] field that previous GCCs would not have
300 (aapcs_vfp_is_call_or_return_candidate): Update the calls to
301 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
302 [[no_unique_address]] case. Use TYPE_MAIN_VARIANT in the
304 (arm_needs_doubleword_align): Add a comment explaining why we
305 consider even zero-sized fields.
307 2020-04-29 Richard Biener <rguenther@suse.de>
308 Li Zekun <lizekun1@huawei.com>
311 * tree.c (component_ref_size): Guard against error_mark_node
312 DECL_INITIAL as it happens with LTO.
314 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
316 * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add a
317 comment explaining why we consider even zero-sized fields.
318 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
319 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
320 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
321 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
322 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
323 something actually is a HFA or HVA. Record whether we see a
324 [[no_unique_address]] field that previous GCCs would not have
326 (aarch64_vfp_is_call_or_return_candidate): Add a parameter to say
327 whether diagnostics should be suppressed. Update the calls to
328 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
329 [[no_unique_address]] case.
330 (aarch64_return_in_msb): Update call accordingly, never silencing
332 (aarch64_function_value): Likewise.
333 (aarch64_return_in_memory_1): Likewise.
334 (aarch64_init_cumulative_args): Likewise.
335 (aarch64_gimplify_va_arg_expr): Likewise.
336 (aarch64_pass_by_reference_1): Take a CUMULATIVE_ARGS pointer and
337 use it to decide whether arch64_vfp_is_call_or_return_candidate
339 (aarch64_pass_by_reference): Update calls accordingly.
340 (aarch64_vfp_is_call_candidate): Use the CUMULATIVE_ARGS argument
341 to decide whether arch64_vfp_is_call_or_return_candidate should be
344 2020-04-29 Haijian Zhang <z.zhanghaijian@huawei.com>
347 * config/aarch64/aarch64-builtins.c
348 (aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of
349 MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and
352 2020-04-29 Thomas Schwinge <thomas@codesourcery.com>
354 * configure.ac <$enable_offload_targets>: Do parsing as done
356 * configure: Regenerate.
358 * configure.ac <$enable_offload_targets>: 'amdgcn' is 'gcn'.
359 * configure: Regenerate.
362 * rtlanal.c (set_noop_p): Handle non-constant selectors.
365 * common/config/gcn/gcn-common.c (gcn_except_unwind_info): New
367 (TARGET_EXCEPT_UNWIND_INFO): Define.
369 2020-04-29 Jakub Jelinek <jakub@redhat.com>
372 * config/gcn/gcn.md (*mov<mode>_insn): Use
373 'reg_overlap_mentioned_p' to check for overlap.
376 * config/ia64/ia64.c (hfa_element_mode): Use DECL_FIELD_ABI_IGNORED
377 instead of cxx17_empty_base_field_p.
380 * tree-core.h (tree_decl_common): Note decl_flag_0 used for
381 DECL_FIELD_ABI_IGNORED.
382 * tree.h (DECL_FIELD_ABI_IGNORED): Define.
383 * calls.h (cxx17_empty_base_field_p): Change into a temporary
384 macro, check DECL_FIELD_ABI_IGNORED flag with no "no_unique_address"
386 * calls.c (cxx17_empty_base_field_p): Remove.
387 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Handle
388 DECL_FIELD_ABI_IGNORED.
389 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
390 * lto-streamer-out.c (hash_tree): Likewise.
391 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Rename
392 cxx17_empty_base_seen to empty_base_seen, change type to int *,
393 adjust recursive calls, use DECL_FIELD_ABI_IGNORED instead of
394 cxx17_empty_base_field_p, if "no_unique_address" attribute is
395 present, propagate that to the caller too.
396 (rs6000_discover_homogeneous_aggregate): Adjust
397 rs6000_aggregate_candidate caller, emit different diagnostics
398 when c++17 empty base fields are present and when empty
399 [[no_unique_address]] fields are present.
400 * config/rs6000/rs6000.c (rs6000_special_round_type_align,
401 darwin_rs6000_special_round_type_align): Skip DECL_FIELD_ABI_IGNORED
404 2020-04-29 Richard Biener <rguenther@suse.de>
406 * tree-ssa-loop-im.c (ref_always_accessed::operator ()):
407 Just check whether the stmt stores.
409 2020-04-28 Alexandre Oliva <oliva@adacore.com>
412 * gcc/config/rs6000/rs6000.md (rs6000_mffsl): Copy result to
413 output operand in emulation. Don't overwrite pseudos.
415 2020-04-28 Jeff Law <law@redhat.com>
417 * config/h8300/h8300.md (H8/SX mult patterns): All H8/SX specific
418 multiply patterns are 4 bytes long.
420 2020-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
422 * config/arm/arm-cpus.in (cortex-m55): Remove +nofp option.
423 * doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option.
425 2020-04-28 Matthew Malcomson <matthew.malcomson@arm.com>
426 Jakub Jelinek <jakub@redhat.com>
429 * config/arm/arm.c (aapcs_vfp_sub_candidate): Account for C++17 empty
430 base class artificial fields.
431 (aapcs_vfp_is_call_or_return_candidate): Warn when PCS ABI
432 decision is different after this fix.
434 2020-04-28 David Malcolm <dmalcolm@redhat.com>
440 * doc/invoke.texi (Static Analyzer Options): Remove
441 -Wanalyzer-use-of-uninitialized-value.
442 (-Wno-analyzer-use-of-uninitialized-value): Remove item.
444 2020-04-28 Jakub Jelinek <jakub@redhat.com>
446 PR tree-optimization/94809
447 * tree.c (build_call_expr_internal_loc_array): Call
448 process_call_operands.
450 2020-04-27 Anton Youdkevitch <anton.youdkevitch@bell-sw.com>
452 * config/aarch64/aarch64-cores.def (thunderx3t110): Add the chip name.
453 * config/aarch64/aarch64-tune.md: Regenerate.
454 * config/aarch64/aarch64.c (thunderx3t110_addrcost_table): Define.
455 (thunderx3t110_regmove_cost): Likewise.
456 (thunderx3t110_vector_cost): Likewise.
457 (thunderx3t110_prefetch_tune): Likewise.
458 (thunderx3t110_tunings): Likewise.
459 * config/aarch64/aarch64-cost-tables.h (thunderx3t110_extra_costs):
461 * config/aarch64/thunderx3t110.md: New file.
462 * config/aarch64/aarch64.md: Include thunderx3t110.md.
463 * doc/invoke.texi (AArch64 options): Add thunderx3t110.
465 2020-04-28 Jakub Jelinek <jakub@redhat.com>
468 * config/s390/s390.c (s390_function_arg_vector,
469 s390_function_arg_float): Emit -Wpsabi diagnostics if the ABI changed.
471 2020-04-28 Richard Sandiford <richard.sandiford@arm.com>
473 PR tree-optimization/94727
474 * tree-vect-stmts.c (vect_is_simple_cond): If both comparison
475 operands are invariant booleans, use the mask type associated with the
476 STMT_VINFO_VECTYPE. Use !slp_node instead of !vectype to exclude SLP.
477 (vectorizable_condition): Pass vectype unconditionally to
480 2020-04-27 Jakub Jelinek <jakub@redhat.com>
483 * config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use
484 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
485 sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var.
487 2020-04-27 David Malcolm <dmalcolm@redhat.com>
490 * configure.ac (DOCUMENTATION_ROOT_URL): Drop trailing "gcc/" from
491 default value, so that it can by supplied by get_option_html_page.
492 * configure: Regenerate.
493 * opts.c: Include "selftest.h".
494 (get_option_html_page): New function.
495 (get_option_url): Use it. Reformat to place comments next to the
496 expressions they refer to.
497 (selftest::test_get_option_html_page): New.
498 (selftest::opts_c_tests): New.
499 * selftest-run-tests.c (selftest::run_tests): Call
500 selftest::opts_c_tests.
501 * selftest.h (selftest::opts_c_tests): New decl.
503 2020-04-27 Richard Sandiford <richard.sandiford@arm.com>
505 * config/arm/arm-builtins.c (arm_expand_builtin_args): Only apply
506 UINTVAL to CONST_INTs.
508 2020-04-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
510 * config/arm/constraints.md (e): Remove constraint.
511 (Te): Define constraint.
512 * config/arm/mve.md (vaddvq_<supf><mode>): Modify constraint in
513 operand 0 from "e" to "Te".
514 (vaddvaq_<supf><mode>): Likewise.
515 (vaddvq_p_<supf><mode>): Likewise.
516 (vmladavq_<supf><mode>): Likewise.
517 (vmladavxq_s<mode>): Likewise.
518 (vmlsdavq_s<mode>): Likewise.
519 (vmlsdavxq_s<mode>): Likewise.
520 (vaddvaq_p_<supf><mode>): Likewise.
521 (vmladavaq_<supf><mode>): Likewise.
522 (vmladavq_p_<supf><mode>): Likewise.
523 (vmladavxq_p_s<mode>): Likewise.
524 (vmlsdavq_p_s<mode>): Likewise.
525 (vmlsdavxq_p_s<mode>): Likewise.
526 (vmlsdavaxq_s<mode>): Likewise.
527 (vmlsdavaq_s<mode>): Likewise.
528 (vmladavaxq_s<mode>): Likewise.
529 (vmladavaq_p_<supf><mode>): Likewise.
530 (vmladavaxq_p_s<mode>): Likewise.
531 (vmlsdavaq_p_s<mode>): Likewise.
532 (vmlsdavaxq_p_s<mode>): Likewise.
534 2020-04-27 Andre Vieira <andre.simoesdiasvieira@arm.com>
536 * config/arm/arm.c (output_move_neon): Only get the first operand if
539 2020-04-27 Felix Yang <felix.yang@huawei.com>
541 PR tree-optimization/94784
542 * tree-ssa-forwprop.c (simplify_vector_constructor): Flip the
543 assert around so that it checks that the two vectors have equal
544 TYPE_VECTOR_SUBPARTS and that converting the corresponding element
545 types is a useless_type_conversion_p.
547 2020-04-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
550 * dwarf2cfi.c (struct GTY): Add ra_mangled.
551 (cfi_row_equal_p): Check ra_mangled.
552 (dwarf2out_frame_debug_cfa_window_save): Remove the argument,
553 this only handles the sparc logic now.
554 (dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for
555 the aarch64 specific logic.
556 (dwarf2out_frame_debug): Update to use the new subroutines.
557 (change_cfi_row): Check ra_mangled.
559 2020-04-27 Jakub Jelinek <jakub@redhat.com>
562 * config/s390/s390.c (s390_function_arg_vector,
563 s390_function_arg_float): Ignore cxx17_empty_base_field_p fields.
565 2020-04-27 Jiufu Guo <guojiufu@cn.ibm.com>
567 * common/config/rs6000/rs6000-common.c
568 (rs6000_option_optimization_table) [OPT_LEVELS_ALL]: Remove turn off
570 * config/rs6000/rs6000.c (rs6000_option_override_internal): Avoid to
573 2020-04-27 Martin Liska <mliska@suse.cz>
576 * cgraph.h (cgraph_node::can_remove_if_no_direct_calls_and_refs_p):
577 Do not remove ifunc_resolvers in remove unreachable nodes in LTO.
579 2020-04-27 Xiong Hu Luo <luoxhu@linux.ibm.com>
582 * config/rs6000/rs6000-logue.c (frame_pointer_needed_indeed):
584 (rs6000_emit_prologue_components):
585 Check with frame_pointer_needed_indeed.
586 (rs6000_emit_epilogue_components): Likewise.
587 (rs6000_emit_prologue): Likewise.
588 (rs6000_emit_epilogue): Set frame_pointer_needed_indeed.
590 2020-04-25 David Edelsohn <dje.gcc@gmail.com>
592 * config/rs6000/rs6000-logue.c (rs6000_stack_info): Don't push a
593 stack frame when debugging and flag_compare_debug is enabled.
595 2020-04-25 Michael Meissner <meissner@linux.ibm.com>
597 * config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Define to
598 enable PC-relative addressing for -mcpu=future.
599 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Move
600 after OTHER_FUTURE_MASKS. Use OTHER_FUTURE_MASKS.
601 * config/rs6000/rs6000.c (PCREL_SUPPORTED_BY_OS): If not defined,
602 suppress PC-relative addressing.
603 (rs6000_option_override_internal): Split up error messages
604 checking for -mprefixed and -mpcrel. Enable -mpcrel if the target
607 2020-04-25 Jakub Jelinek <jakub@redhat.com>
608 Richard Biener <rguenther@suse.de>
610 PR tree-optimization/94734
611 PR tree-optimization/89430
612 * tree-ssa-phiopt.c: Include tree-eh.h.
613 (cond_store_replacement): Return false if an automatic variable
614 access could trap. If -fstore-data-races, don't return false
615 just because an automatic variable is addressable.
617 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
619 * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge
621 (add<mode>_sext_dup2_exec): Likewise.
623 2020-04-24 Segher Boessenkool <segher@kernel.crashing.org>
626 * config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little
627 endian byteshift_val calculation.
629 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
631 * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.
633 2020-04-24 Richard Sandiford <richard.sandiford@arm.com>
635 * config/aarch64/arm_sve.h: Add a comment.
637 2020-04-24 Haijian Zhang <z.zhanghaijian@huawei.com>
639 PR rtl-optimization/94708
640 * combine.c (simplify_if_then_else): Add check for
641 !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode).
643 2020-04-23 Martin Sebor <msebor@redhat.com>
646 * common.opt (-Wno-frame-larger-than): New option.
647 (-Wno-larger-than, -Wno-stack-usage): Same.
649 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
651 * config/gcn/gcn-valu.md (mov<mode>_exec): Swap the numbers on operands
653 (mov<mode>_exec): Likewise.
654 (trunc<vndi><mode>2_exec): Swap parameters to gen_mov<mode>_exec.
655 (<convop><mode><vndi>2_exec): Likewise.
657 2019-04-23 Eric Botcazou <ebotcazou@adacore.com>
659 PR tree-optimization/94717
660 * gimple-ssa-store-merging.c (try_coalesce_bswap): Return false if one
661 of the stores doesn't have the same landing pad number as the first.
662 (coalesce_immediate_stores): Do not try to coalesce the store using
663 bswap if it doesn't have the same landing pad number as the first.
665 2020-04-23 Bill Schmidt <wschmidt@linux.ibm.com>
667 * gcc/doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
668 Replace outdated link to ELFv2 ABI.
670 2020-04-23 Jakub Jelinek <jakub@redhat.com>
673 * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx
677 * tree.c (get_narrower): Instead of creating COMPOUND_EXPRs
678 temporarily with non-final second operand and updating it later,
679 push COMPOUND_EXPRs into a vector and process it in reverse,
680 creating COMPOUND_EXPRs with the final operands.
682 2020-04-23 Szabolcs Nagy <szabolcs.nagy@arm.com>
685 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Swap
686 bti c and bti j handling.
688 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
689 Thomas Schwinge <thomas@codesourcery.com>
693 * omp-expand.c (expand_omp_target): Use force_gimple_operand_gsi on
694 t_async and the wait arguments.
696 2020-04-23 Richard Sandiford <richard.sandiford@arm.com>
698 PR tree-optimization/94727
699 * tree-vect-stmts.c (vectorizable_comparison): Use mask_type when
700 comparing invariant scalar booleans.
702 2020-04-23 Matthew Malcomson <matthew.malcomson@arm.com>
703 Jakub Jelinek <jakub@redhat.com>
706 * config/aarch64/aarch64.c (aapcs_vfp_sub_candidate): Account for C++17
707 empty base class artificial fields.
708 (aarch64_vfp_is_call_or_return_candidate): Warn when ABI PCS decision is
709 different after this fix.
711 2020-04-23 Jakub Jelinek <jakub@redhat.com>
714 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
715 Use TYPE_UID (TYPE_MAIN_VARIANT (type)) instead of type to check
716 if the same type has been diagnosed most recently already.
718 2020-04-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
720 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's
722 (__arm_vbicq_n_s16): Likewise.
723 (__arm_vbicq_n_u32): Likewise.
724 (__arm_vbicq_n_s32): Likewise.
725 (__arm_vbicq): Likewise.
726 (__arm_vbicq_n_s16): Modify MVE polymorphic variant argument's datatype.
727 (__arm_vbicq_n_s32): Likewise.
728 (__arm_vbicq_n_u16): Likewise.
729 (__arm_vbicq_n_u32): Likewise.
730 (__arm_vdupq_m_n_s8): Likewise.
731 (__arm_vdupq_m_n_s16): Likewise.
732 (__arm_vdupq_m_n_s32): Likewise.
733 (__arm_vdupq_m_n_u8): Likewise.
734 (__arm_vdupq_m_n_u16): Likewise.
735 (__arm_vdupq_m_n_u32): Likewise.
736 (__arm_vdupq_m_n_f16): Likewise.
737 (__arm_vdupq_m_n_f32): Likewise.
738 (__arm_vldrhq_gather_offset_s16): Likewise.
739 (__arm_vldrhq_gather_offset_s32): Likewise.
740 (__arm_vldrhq_gather_offset_u16): Likewise.
741 (__arm_vldrhq_gather_offset_u32): Likewise.
742 (__arm_vldrhq_gather_offset_f16): Likewise.
743 (__arm_vldrhq_gather_offset_z_s16): Likewise.
744 (__arm_vldrhq_gather_offset_z_s32): Likewise.
745 (__arm_vldrhq_gather_offset_z_u16): Likewise.
746 (__arm_vldrhq_gather_offset_z_u32): Likewise.
747 (__arm_vldrhq_gather_offset_z_f16): Likewise.
748 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
749 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
750 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
751 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
752 (__arm_vldrhq_gather_shifted_offset_f16): Likewise.
753 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
754 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
755 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
756 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
757 (__arm_vldrhq_gather_shifted_offset_z_f16): Likewise.
758 (__arm_vldrwq_gather_offset_s32): Likewise.
759 (__arm_vldrwq_gather_offset_u32): Likewise.
760 (__arm_vldrwq_gather_offset_f32): Likewise.
761 (__arm_vldrwq_gather_offset_z_s32): Likewise.
762 (__arm_vldrwq_gather_offset_z_u32): Likewise.
763 (__arm_vldrwq_gather_offset_z_f32): Likewise.
764 (__arm_vldrwq_gather_shifted_offset_s32): Likewise.
765 (__arm_vldrwq_gather_shifted_offset_u32): Likewise.
766 (__arm_vldrwq_gather_shifted_offset_f32): Likewise.
767 (__arm_vldrwq_gather_shifted_offset_z_s32): Likewise.
768 (__arm_vldrwq_gather_shifted_offset_z_u32): Likewise.
769 (__arm_vldrwq_gather_shifted_offset_z_f32): Likewise.
770 (__arm_vdwdupq_x_n_u8): Likewise.
771 (__arm_vdwdupq_x_n_u16): Likewise.
772 (__arm_vdwdupq_x_n_u32): Likewise.
773 (__arm_viwdupq_x_n_u8): Likewise.
774 (__arm_viwdupq_x_n_u16): Likewise.
775 (__arm_viwdupq_x_n_u32): Likewise.
776 (__arm_vidupq_x_n_u8): Likewise.
777 (__arm_vddupq_x_n_u8): Likewise.
778 (__arm_vidupq_x_n_u16): Likewise.
779 (__arm_vddupq_x_n_u16): Likewise.
780 (__arm_vidupq_x_n_u32): Likewise.
781 (__arm_vddupq_x_n_u32): Likewise.
782 (__arm_vldrdq_gather_offset_s64): Likewise.
783 (__arm_vldrdq_gather_offset_u64): Likewise.
784 (__arm_vldrdq_gather_offset_z_s64): Likewise.
785 (__arm_vldrdq_gather_offset_z_u64): Likewise.
786 (__arm_vldrdq_gather_shifted_offset_s64): Likewise.
787 (__arm_vldrdq_gather_shifted_offset_u64): Likewise.
788 (__arm_vldrdq_gather_shifted_offset_z_s64): Likewise.
789 (__arm_vldrdq_gather_shifted_offset_z_u64): Likewise.
790 (__arm_vidupq_m_n_u8): Likewise.
791 (__arm_vidupq_m_n_u16): Likewise.
792 (__arm_vidupq_m_n_u32): Likewise.
793 (__arm_vddupq_m_n_u8): Likewise.
794 (__arm_vddupq_m_n_u16): Likewise.
795 (__arm_vddupq_m_n_u32): Likewise.
796 (__arm_vidupq_n_u16): Likewise.
797 (__arm_vidupq_n_u32): Likewise.
798 (__arm_vidupq_n_u8): Likewise.
799 (__arm_vddupq_n_u16): Likewise.
800 (__arm_vddupq_n_u32): Likewise.
801 (__arm_vddupq_n_u8): Likewise.
803 2020-04-23 Iain Buclaw <ibuclaw@gdcproject.org>
805 * doc/install.texi (D-Specific Options): Document
806 --enable-libphobos-checking and --with-libphobos-druntime-only.
808 2020-04-23 Jakub Jelinek <jakub@redhat.com>
811 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add
812 cxx17_empty_base_seen argument. Pass it to recursive calls.
813 Ignore cxx17_empty_base_field_p fields after setting
814 *cxx17_empty_base_seen to true.
815 (rs6000_discover_homogeneous_aggregate): Adjust
816 rs6000_aggregate_candidate caller. With -Wpsabi, diagnose homogeneous
817 aggregates with C++17 empty base fields.
820 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
821 if last_decl is error_mark_node or has such a TREE_TYPE.
824 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
825 if last_decl is error_mark_node or has such a TREE_TYPE.
827 2020-04-22 Felix Yang <felix.yang@huawei.com>
830 * config/aarch64/aarch64.h (TARGET_SVE):
831 Add && !TARGET_GENERAL_REGS_ONLY.
832 (TARGET_SVE2): Add && TARGET_SVE.
833 (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3,
834 TARGET_SVE2_SM4): Add && TARGET_SVE2.
835 * config/aarch64/aarch64-sve-builtins.h
836 (sve_switcher::m_old_general_regs_only): New member.
837 * config/aarch64/aarch64-sve-builtins.cc (check_required_registers):
839 (reported_missing_registers_p): New variable.
840 (check_required_extensions): Call check_required_registers before
841 return if all required extenstions are present.
842 (sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in
843 m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in
844 global_options.x_target_flags.
845 (sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in
846 global_options.x_target_flags if m_old_general_regs_only is true.
848 2020-04-22 Zackery Spytz <zspytz@gmail.com>
850 * doc/extend.exi: Add "free" to list of other builtin functions
853 2020-04-20 Aaron Sawdey <acsawdey@linux.ibm.com>
856 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed"
858 (store_quadpti): Ditto.
859 (atomic_load<mode>): Do not swap doublewords if TARGET_PREFIXED as
860 plq will be used and doesn't need it.
861 (atomic_store<mode>): Ditto, for pstq.
863 2020-04-22 Erick Ochoa <erick.ochoa@theobroma-systems.com>
865 * doc/invoke.texi: Update flags turned on by -O3.
867 2020-04-22 Jakub Jelinek <jakub@redhat.com>
870 * config/ia64/ia64.c (hfa_element_mode): Ignore
871 cxx17_empty_base_field_p fields.
874 * calls.h (cxx17_empty_base_field_p): Declare.
875 * calls.c (cxx17_empty_base_field_p): Define.
877 2020-04-22 Christophe Lyon <christophe.lyon@linaro.org>
879 * doc/sourcebuild.texi (arm_softfp_ok, arm_hard_ok): Document.
881 2020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
882 Andre Vieira <andre.simoesdiasvieira@arm.com>
883 Mihail Ionescu <mihail.ionescu@arm.com>
885 * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu.
886 * config/arm/arm-cpus.in (quirk_no_asmcpu): Define.
887 (ALL_QUIRKS): Add quirk_no_asmcpu.
888 (cortex-m55): Define new cpu.
889 * config/arm/arm-tables.opt: Regenerate.
890 * config/arm/arm-tune.md: Likewise.
891 * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.
893 2020-04-22 Richard Sandiford <richard.sandiford@arm.com>
895 PR tree-optimization/94700
896 * tree-ssa-forwprop.c (simplify_vector_constructor): When processing
897 an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures
898 of similarly-structured but distinct vector types.
900 2020-04-21 Martin Sebor <msebor@redhat.com>
903 * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Correct
904 the computation of the lower bound of the source access size.
905 (builtin_access::generic_overlap): Remove a hack for setting ranges
908 2020-04-21 John David Anglin <danglin@gcc.gnu.org>
910 * config/pa/som.h (ASM_WEAKEN_LABEL): Delete.
911 (ASM_WEAKEN_DECL): New define.
912 (HAVE_GAS_WEAKREF): Undefine.
914 2020-04-21 Richard Sandiford <richard.sandiford@arm.com>
916 PR tree-optimization/94683
917 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a
918 VIEW_CONVERT_EXPR to handle mixtures of similarly-structured
919 but distinct vector types.
921 2020-04-21 Jakub Jelinek <jakub@redhat.com>
924 * stor-layout.c (place_field, finalize_record_size): Don't emit
925 -Wpadded warning on TYPE_ARTIFICIAL rli->t.
926 * ubsan.c (ubsan_get_type_descriptor_type,
927 ubsan_get_source_location_type, ubsan_create_data): Set
929 * asan.c (asan_global_struct): Likewise.
931 2020-04-21 Duan bo <duanbo3@huawei.com>
934 * config/aarch64/aarch64.c: Add an error message for option conflict.
935 * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is
936 incompatible with -fpic, -fPIC and -mabi=ilp32.
938 2020-04-21 Frederik Harwath <frederik@codesourcery.com>
941 * omp-low.c (new_omp_context): Remove assignments to
942 ctx->outer_reduction_clauses and ctx->local_reduction_clauses.
944 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
946 * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx")
947 ("popcountv2di2_vx"): Use simplify_gen_subreg.
949 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
952 * config/s390/s390-builtin-types.def: Add 3 new function modes.
953 * config/s390/s390-builtins.def: Add mode dependent low-level
954 builtin and map the overloaded builtins to these.
955 * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
956 ("vsel<V_HW"): ... this and rewrite the pattern with bitops.
958 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
960 * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo
961 has a variable VF, prefer new_loop_vinfo if it is cheaper for the
962 estimated VF and is no worse at double the estimated VF.
964 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
967 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix
968 order of arguments to rtx_vector_builder.
969 (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise.
970 When extending the trailing constants to a full vector, replace any
971 variables with zeros.
973 2020-04-20 Jan Hubicka <hubicka@ucw.cz>
976 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local
979 2020-04-20 Martin Liska <mliska@suse.cz>
981 * symtab.c (symtab_node::dump_references): Add space after
983 (symtab_node::dump_referring): Likewise.
985 2020-04-18 Jeff Law <law@redhat.com>
988 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking
991 2020-04-18 Iain Buclaw <ibuclaw@gdcproject.org>
993 * doc/sourcebuild.texi (Effective-Target Keywords, Environment
994 attributes): Document d_runtime_has_std_library.
996 2020-04-17 Jeff Law <law@redhat.com>
998 PR rtl-optimization/90275
999 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels
1000 when the destination has a REG_UNUSED note.
1002 2020-04-17 Tobias Burnus <tobias@codesourcery.com>
1005 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to
1008 2020-04-17 Richard Sandiford <richard.sandiford@arm.com>
1010 * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function.
1011 (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the
1012 cost of load and store insns if one loop iteration has enough scalar
1013 elements to use an Advanced SIMD LDP or STP.
1014 (aarch64_add_stmt_cost): Update call accordingly.
1016 2020-04-17 Jakub Jelinek <jakub@redhat.com>
1017 Jeff Law <law@redhat.com>
1020 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than
1021 CCNOmode in ix86_match_ccmode if len is equal to <MODE>mode precision,
1022 or pos + len >= 32, or pos + len is equal to operands[2] precision
1023 and operands[2] is not a register operand. During splitting perform
1024 SImode AND if operands[0] doesn't have CCZmode and pos + len is
1025 equal to mode precision.
1027 2020-04-17 Richard Biener <rguenther@suse.de>
1030 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate
1032 * dwarf2out.c (dw_val_equal_p): Fix pasto in
1033 dw_val_class_vms_delta comparison.
1034 * optabs.c (expand_binop_directly): Fix pasto in commutation
1036 * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in
1039 2020-04-17 Jakub Jelinek <jakub@redhat.com>
1041 PR rtl-optimization/94618
1042 * cfgrtl.c (delete_insn_and_edges): Set purge not just when
1043 insn is the BB_END of its block, but also when it is only followed
1044 by DEBUG_INSNs in its block.
1046 PR tree-optimization/94621
1047 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN.
1048 Move id->adjust_array_error_bounds check first in the condition.
1050 2020-04-17 Martin Liska <mliska@suse.cz>
1051 Jonathan Yong <10walls@gmail.com>
1053 PR gcov-profile/94570
1054 * coverage.c (coverage_init): Use separator properly.
1056 2020-04-16 Peter Bergner <bergner@linux.ibm.com>
1058 PR rtl-optimization/93974
1059 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define.
1060 (rs6000_cannot_substitute_mem_equiv_p): New function.
1062 2020-04-16 Martin Jambor <mjambor@suse.cz>
1065 * ipa-inline.h (ipa_saved_clone_sources): Declare.
1066 * ipa-inline-transform.c (ipa_saved_clone_sources): New variable.
1067 (save_inline_function_body): Link the new body holder with the
1069 * cgraph.c: Include ipa-inline.h.
1070 (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from
1071 the statement in ipa_saved_clone_sources.
1072 * cgraphunit.c: Include ipa-inline.h.
1073 (expand_all_functions): Free ipa_saved_clone_sources.
1075 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
1078 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
1079 the VNx16BI lowpart of the recursively-generated constant.
1081 2020-04-16 Martin Liska <mliska@suse.cz>
1082 Jakub Jelinek <jakub@redhat.com>
1085 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop
1086 DECL_IS_REPLACEABLE_OPERATOR during cloning.
1087 * tree-ssa-dce.c (valid_new_delete_pair_p): New function.
1088 (propagate_necessity): Check operator names.
1090 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
1092 PR rtl-optimization/94605
1093 * early-remat.c (early_remat::process_block): Handle insns that
1094 set multiple candidate registers.
1095 2020-04-16 Jan Hubicka <hubicka@ucw.cz>
1097 PR gcov-profile/93401
1098 * common.opt (profile-prefix-path): New option.
1099 * coverae.c: Include diagnostics.h.
1100 (coverage_init): Strip profile prefix path.
1101 * doc/invoke.texi (-fprofile-prefix-path): Document.
1103 2020-04-16 Richard Biener <rguenther@suse.de>
1106 * expr.c (emit_move_multi_word): Do not generate code when
1107 the destination part is undefined_operand_subword_p.
1108 * lower-subreg.c (resolve_clobber): Look through a paradoxica
1111 2020-04-16 Martin Jambor <mjambor@suse.cz>
1113 PR tree-optimization/94598
1114 * tree-sra.c (verify_sra_access_forest): Fix verification of total
1115 scalarization accesses under access to one-element arrays.
1117 2020-04-16 Jakub Jelinek <jakub@redhat.com>
1120 * function.c (assign_parm_find_data_types): Add workaround for
1121 BROKEN_VALUE_INITIALIZATION compilers.
1123 2020-04-16 Richard Biener <rguenther@suse.de>
1125 * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME
1128 2020-04-15 Uroš Bizjak <ubizjak@gmail.com>
1131 * config/i386/i386-builtin.def (__builtin_ia32_movq128):
1132 Require OPTION_MASK_ISA_SSE2.
1134 2020-04-15 Gustavo Romero <gromero@linux.ibm.com>
1137 * dumpfile.c (selftest::temp_dump_context::temp_dump_context):
1138 Don't construct a dump_context temporary to call static method.
1140 2020-04-15 Andrea Corallo <andrea.corallo@arm.com>
1142 * config/aarch64/falkor-tag-collision-avoidance.c
1143 (valid_src_p): Check for aarch64_address_info type before
1144 accessing base field.
1146 2020-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
1148 * config/arm/mve.md (mve_vec_duplicate<mode>): New pattern.
1149 (V_sz_elem2): Remove unused mode attribute.
1151 2020-04-15 Matthew Malcomson <matthew.malcomson@arm.com>
1153 * config/arm/arm.md (arm_movdi): Disallow for MVE.
1155 2020-04-15 Richard Biener <rguenther@suse.de>
1158 * tree-ssa-alias.c (same_type_for_tbaa): Defer to
1159 alias_sets_conflict_p for pointers.
1161 2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
1164 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
1165 (extendhisi2_internal): Add %v1 before the load instructions.
1167 2020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com>
1170 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to
1171 use PC-relative addressing for TLS references.
1173 2020-04-14 Martin Jambor <mjambor@suse.cz>
1176 * ipa-sra.c: Include internal-fn.h.
1177 (enum isra_scan_context): Update comment.
1178 (scan_function): Treat calls to internal_functions like loads or stores.
1180 2020-04-14 Yang Yang <yangyang305@huawei.com>
1182 PR tree-optimization/94574
1183 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing
1184 whether a vector-insert is rewritable using a BIT_INSERT_EXPR.
1186 2020-04-14 H.J. Lu <hongjiu.lu@intel.com>
1189 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check.
1191 2020-04-13 Martin Sebor <msebor@redhat.com>
1193 * doc/extend.texi (-Wall): Mention -Wformat-overflow and
1194 -Wformat-truncation. Move -Wzero-length-bounds last.
1195 (-Wrestrict): Document positive form of option enabled by -Wall.
1197 2020-04-13 Zachary Spytz <zspytz@gmail.com>
1199 * doc/extend.texi: Add realloc to list of built-in functions
1200 are recognized by the compiler.
1202 2020-04-13 H.J. Lu <hongjiu.lu@intel.com>
1205 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame
1206 pointer in word_mode for eh_return epilogues.
1208 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
1210 * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to
1211 memory references in %B, %C and %D operand selectors when the inner
1212 operand is a post increment address.
1214 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
1216 * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory
1217 reference by 4 bytes, and %D memory reference by 6 bytes.
1219 2020-04-11 Uroš Bizjak <ubizjak@gmail.com>
1222 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2
1223 condition for V4SI, V8HI and V16QI modes.
1225 2020-04-11 Jakub Jelinek <jakub@redhat.com>
1229 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on
1232 2020-04-10 Thomas Schwinge <thomas@codesourcery.com>
1236 * omp-general.c (oacc_verify_routine_clauses): Diagnose if
1237 "#pragma omp declare target" has also been applied.
1239 2020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com>
1241 * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn
1242 when to emit the epilogue_helper insn.
1243 * config/msp430/msp430.md (epilogue_helper): Add a return insn to the
1246 2020-04-09 Jakub Jelinek <jakub@redhat.com>
1249 * cselib.h (cselib_record_sp_cfa_base_equiv,
1250 cselib_sp_derived_value_p): Declare.
1251 * cselib.c (cselib_record_sp_cfa_base_equiv,
1252 cselib_sp_derived_value_p): New functions.
1253 * var-tracking.c (add_stores): Don't record MO_VAL_SET for
1254 cselib_sp_derived_value_p values.
1255 (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the
1256 start of extended basic blocks other than the first one
1257 for !frame_pointer_needed functions.
1259 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
1261 * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw)
1262 (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw)
1263 (aarch64_sve2048_hw): Document.
1264 * config/aarch64/aarch64-protos.h
1265 (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare.
1266 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
1267 __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled.
1268 * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New
1270 (find_type_suffix_for_scalar_type): Use it instead of comparing
1272 (function_resolver::infer_vector_or_tuple_type): Likewise.
1273 (function_resolver::require_vector_type): Likewise.
1274 (handle_arm_sve_vector_bits_attribute): New function.
1275 * config/aarch64/aarch64.c (pure_scalable_type_info): New class.
1276 (aarch64_attribute_table): Add arm_sve_vector_bits.
1277 (aarch64_return_in_memory_1):
1278 (pure_scalable_type_info::piece::get_rtx): New function.
1279 (pure_scalable_type_info::num_zr): Likewise.
1280 (pure_scalable_type_info::num_pr): Likewise.
1281 (pure_scalable_type_info::get_rtx): Likewise.
1282 (pure_scalable_type_info::analyze): Likewise.
1283 (pure_scalable_type_info::analyze_registers): Likewise.
1284 (pure_scalable_type_info::analyze_array): Likewise.
1285 (pure_scalable_type_info::analyze_record): Likewise.
1286 (pure_scalable_type_info::add_piece): Likewise.
1287 (aarch64_some_values_include_pst_objects_p): Likewise.
1288 (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info
1289 to analyze whether the type is returned in SVE registers.
1290 (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type
1291 is passed in SVE registers.
1292 (aarch64_pass_by_reference_1): New function, extracted from...
1293 (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info
1294 to analyze whether the type is a pure scalable type and, if so,
1295 whether it should be passed by reference.
1296 (aarch64_return_in_msb): Return false for pure scalable types.
1297 (aarch64_function_value_1): Fold back into...
1298 (aarch64_function_value): ...this function. Use
1299 pure_scalable_type_info to analyze whether the type is a pure
1300 scalable type and, if so, which registers it should use. Handle
1301 types that include pure scalable types but are not themselves
1302 pure scalable types.
1303 (aarch64_return_in_memory_1): New function, split out from...
1304 (aarch64_return_in_memory): ...here. Use pure_scalable_type_info
1305 to analyze whether the type is a pure scalable type and, if so,
1306 whether it should be returned by reference.
1307 (aarch64_layout_arg): Remove orig_mode argument. Use
1308 pure_scalable_type_info to analyze whether the type is a pure
1309 scalable type and, if so, which registers it should use. Handle
1310 types that include pure scalable types but are not themselves
1311 pure scalable types.
1312 (aarch64_function_arg): Update call accordingly.
1313 (aarch64_function_arg_advance): Likewise.
1314 (aarch64_pad_reg_upward): On big-endian targets, return false for
1315 pure scalable types that are smaller than 16 bytes.
1316 (aarch64_member_type_forces_blk): New function.
1317 (aapcs_vfp_sub_candidate): Exit early for built-in SVE types.
1318 (aarch64_short_vector_p): Return false for VECTOR_TYPEs that
1319 correspond to built-in SVE types. Do not rely on a vector mode
1320 if the type includes an pure scalable type. When returning true,
1321 assert that the mode is not an SVE mode.
1322 (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE
1323 built-in types here. When returning true, assert that the type
1324 does not have an SVE mode.
1325 (aarch64_can_change_mode_class): Don't allow anything to change
1326 between a predicate mode and a non-predicate mode. Also don't
1327 allow changes between SVE vector modes and other modes that
1328 might be bigger than 128 bits.
1329 (aarch64_invalid_binary_op): Reject binary operations that mix
1330 SVE and GNU vector types.
1331 (TARGET_MEMBER_TYPE_FORCES_BLK): Define.
1333 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
1335 * config/aarch64/aarch64.c (aarch64_attribute_table): Add
1336 "SVE sizeless type".
1337 * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless)
1338 (sizeless_type_p): New functions.
1339 (register_builtin_types): Apply make_type_sizeless to the type.
1340 (register_tuple_type): Likewise.
1341 (verify_type_context): Use sizeless_type_p instead of builin_type_p.
1343 2020-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
1345 * config/arm/arm_cde.h: Remove `extern "C"` when compiling for
1348 2020-04-09 Martin Jambor <mjambor@suse.cz>
1349 Richard Biener <rguenther@suse.de>
1351 PR tree-optimization/94482
1352 * tree-sra.c (create_access_replacement): Dump new replacement with
1354 (sra_modify_expr): Fix handling of cases when the original EXPR writes
1355 to only part of the replacement.
1356 * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
1357 the first operand of combinations into REAL/IMAGPART_EXPR and
1360 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
1362 * doc/sourcebuild.texi (check-function-bodies): Treat the third
1363 parameter as a list of option regexps and require each regexp
1366 2020-04-09 Andrea Corallo <andrea.corallo@arm.com>
1369 * config/aarch64/falkor-tag-collision-avoidance.c
1370 (valid_src_p): Fix missing rtx type check.
1372 2020-04-09 Bin Cheng <bin.cheng@linux.alibaba.com>
1373 Richard Biener <rguenther@suse.de>
1375 PR tree-optimization/93674
1376 * tree-ssa-loop-ivopts.c (langhooks.h): New include.
1377 (add_iv_candidate_for_use): For iv_use of non integer or pointer type,
1378 or non-mode precision type, add candidate in unsigned type with the
1381 2020-04-08 Clement Chigot <clement.chigot@atos.net>
1383 * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128.
1384 * config/rs6000/aix71.h (LIB_SPEC): Likewise.
1385 * config/rs6000/aix72.h (LIB_SPEC): Likewise.
1387 2020-04-08 Jakub Jelinek <jakub@redhat.com>
1390 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P
1392 * reload1.c (eliminate_regs_1): Avoid creating
1393 (plus (reg) (const_int 0)) in DEBUG_INSNs.
1395 PR tree-optimization/94524
1396 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
1397 negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
1398 op1 rather than op1 itself at the end. Punt for signed modulo by
1399 most negative constant.
1400 * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
1401 modulo by most negative constant.
1403 2020-04-08 Richard Biener <rguenther@suse.de>
1405 PR rtl-optimization/93946
1406 * cse.c (cse_insn): Record the tabled expression in
1407 src_related. Verify a redundant store removal is valid.
1409 2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
1412 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert
1413 ENDBR at function entry if function will be called indirectly.
1415 2020-04-08 Jakub Jelinek <jakub@redhat.com>
1418 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
1421 2020-04-08 Martin Liska <mliska@suse.cz>
1424 * gimple.c (gimple_call_operator_delete_p): Rename to...
1425 (gimple_call_replaceable_operator_delete_p): ... this.
1426 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
1427 * gimple.h (gimple_call_operator_delete_p): Rename to ...
1428 (gimple_call_replaceable_operator_delete_p): ... this.
1429 * tree-core.h (tree_function_decl): Add replaceable_operator
1431 * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1):
1432 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
1433 (propagate_necessity): Use gimple_call_replaceable_operator_delete_p.
1434 (eliminate_unnecessary_stmts): Likewise.
1435 * tree-streamer-in.c (unpack_ts_function_decl_value_fields):
1436 Pack DECL_IS_REPLACEABLE_OPERATOR.
1437 * tree-streamer-out.c (pack_ts_function_decl_value_fields):
1438 Unpack the field here.
1439 * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New.
1440 (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New.
1441 (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New.
1442 * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable.
1443 * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare
1444 replaceable operator flags.
1446 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
1447 Matthew Malcomson <matthew.malcomson@arm.com>
1449 * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro.
1450 (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise.
1451 (CX_TERNARY_QUALIFIERS): Likewise.
1452 (ARM_BUILTIN_CDE_PATTERN_START): Likewise.
1453 (ARM_BUILTIN_CDE_PATTERN_END): Likewise.
1454 (arm_init_acle_builtins): Initialize CDE builtins.
1455 (arm_expand_acle_builtin): Check CDE constant operands.
1456 * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range
1457 of CDE constant operand.
1458 * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for
1460 (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise.
1461 * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface.
1462 (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise.
1463 (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise.
1464 (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise.
1465 (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise.
1466 * config/arm/arm_cde_builtins.def: New file.
1467 * config/arm/iterators.md (V_reg): New attribute of SI.
1468 * config/arm/predicates.md (const_int_coproc_operand): New.
1469 (const_int_vcde1_operand, const_int_vcde2_operand): New.
1470 (const_int_vcde3_operand): New.
1471 * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New.
1472 * config/arm/vfp.md (arm_vcx1<mode>): New entry.
1473 (arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise.
1474 (arm_vcx3<mode>, arm_vcx3a<mode>): Likewise.
1476 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
1478 * config.gcc: Add arm_cde.h.
1479 * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
1480 __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
1481 * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
1482 * config/arm/arm.c (arm_option_reconfigure_globals): Configure
1483 arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
1484 * config/arm/arm.h (TARGET_CDE): New macro.
1485 * config/arm/arm_cde.h: New file.
1486 * doc/invoke.texi: Document CDE options +cdecp[0-7].
1487 * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
1489 (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
1491 2020-04-08 Jakub Jelinek <jakub@redhat.com>
1493 PR rtl-optimization/94516
1494 * postreload.c: Include rtl-iter.h.
1495 (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR
1496 looking for all MEMs with RTX_AUTOINC operand.
1497 (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling.
1499 2020-04-08 Tobias Burnus <tobias@codesourcery.com>
1501 * omp-grid.c (grid_eliminate_combined_simd_part): Use
1502 OMP_CLAUSE_CODE to access the omp clause code.
1504 2020-04-07 Jeff Law <law@redhat.com>
1506 PR rtl-optimization/92264
1507 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when
1508 the destination is the stack pointer.
1510 2020-04-07 Jakub Jelinek <jakub@redhat.com>
1512 PR rtl-optimization/94291
1513 PR rtl-optimization/84169
1514 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST
1515 must be a REG or SUBREG of REG; if it is not one of these, don't
1518 2020-04-07 Richard Biener <rguenther@suse.de>
1521 * gimplify.c (gimplify_addr_expr): Also consider generated
1524 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
1526 * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.
1528 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
1530 * config/arm/arm_mve.h: Cast some pointers to expected types.
1532 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
1534 * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
1535 same with '__arm_' prefix.
1537 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
1539 * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.
1541 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
1543 * config/arm/arm.c (arm_mve_immediate_check): Removed.
1544 * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
1545 (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
1546 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
1547 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
1548 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
1549 mve_vqshruntq_m_n_s*): Fixed immediate constraints.
1551 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
1553 * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.
1555 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
1557 * config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
1558 * config/arm/mve/md: Fix v[id]wdup patterns.
1560 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
1562 * config/arm/arm.c (output_move_neon): Deal with label + offset cases.
1563 * config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
1565 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
1567 * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
1568 and remove const_ptr enums.
1570 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
1572 * config/arm/arm_mve.h (vsubq_n): Merge with...
1574 (vmulq_n): Merge with...
1576 (__ARM_mve_typeid): Simplify scalar and constant detection.
1578 2020-04-07 Jakub Jelinek <jakub@redhat.com>
1581 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
1582 for inter-lane permutation for 64-byte modes.
1585 * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
1586 ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
1587 Assume it is a REG after that instead of testing it and doing FAIL
1588 otherwise. Formatting fix.
1590 2020-04-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
1592 * config/rs6000/t-rtems: Delete mcpu=8540 multilib.
1594 2020-04-07 Jakub Jelinek <jakub@redhat.com>
1597 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
1598 handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes.
1600 2020-04-06 Jakub Jelinek <jakub@redhat.com>
1602 * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
1603 + const0_rtx return the SP_DERIVED_VALUE_P.
1605 2020-04-06 Richard Sandiford <richard.sandiford@arm.com>
1607 PR rtl-optimization/92989
1608 * lra-lives.c (process_bb_lives): Do not treat eh_return data
1609 registers as being live at the beginning of the EH receiver.
1611 2020-04-05 Zachary Spytz <zspytz@gmail.com>
1613 * extend.texi: Add free to list of ISO C90 functions that
1614 are recognized by the compiler.
1616 2020-04-05 Nagaraju Mekala <nmekala@xilix.com>
1618 * config/microblaze/microblaze.c (microblaze_must_save_register): Check
1621 * config/microblaze/microblaze.md (trap): Update output pattern.
1623 2020-04-04 Hannes Domani <ssbssa@yahoo.de>
1624 Jakub Jelinek <jakub@redhat.com>
1627 * dwarf2out.c (gen_subprogram_die): Look through references, pointers,
1628 arrays, pointer-to-members, function types and qualifiers when
1629 checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
1630 to emit type again on definition.
1632 2020-04-04 Jan Hubicka <hubicka@ucw.cz>
1635 * ipa-fnsummary.c (vrp_will_run_p): New function.
1636 (fre_will_run_p): New function.
1637 (evaluate_properties_for_edge): Use it.
1638 * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline
1639 !optimize_debug to optimize_debug.
1641 2020-04-04 Jakub Jelinek <jakub@redhat.com>
1643 PR rtl-optimization/94468
1644 * cselib.c (references_value_p): Formatting fix.
1645 (cselib_useless_value_p): New function.
1646 (discard_useless_locs, discard_useless_values,
1647 cselib_invalidate_regno_val, cselib_invalidate_mem,
1648 cselib_record_set): Use it instead of
1649 v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx).
1652 * tree-iterator.h (expr_single): Declare.
1653 * tree-iterator.c (expr_single): New function.
1654 * tree.h (protected_set_expr_location_if_unset): Declare.
1655 * tree.c (protected_set_expr_location): Use expr_single.
1656 (protected_set_expr_location_if_unset): New function.
1658 2020-04-03 Jeff Law <law@redhat.com>
1660 PR rtl-optimization/92264
1661 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle
1662 reloading of auto-increment addressing modes.
1664 2020-04-03 H.J. Lu <hongjiu.lu@intel.com>
1667 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand
1670 2020-04-03 Jeff Law <law@redhat.com>
1672 PR rtl-optimization/92264
1673 * config/m32r/m32r.c (m32r_output_block_move): Properly account for
1674 post-increment addressing of source operands as well as residuals
1675 when computing any adjustments to the input pointer.
1677 2020-04-03 Jakub Jelinek <jakub@redhat.com>
1680 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
1681 avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
1682 second half of first lane from first lane of second operand and
1683 first half of second lane from second lane of first operand.
1685 2020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com>
1687 * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE.
1689 2020-04-03 Tamar Christina <tamar.christina@arm.com>
1692 * common/config/aarch64/aarch64-common.c
1693 (aarch64_get_extension_string_for_isa_flags): Handle default flags.
1695 2020-04-03 Richard Biener <rguenther@suse.de>
1698 * tree.c (array_ref_low_bound): Deal with released SSA names
1701 2020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com>
1703 * config/gcn/gcn.c (print_operand): Handle unordered comparison
1705 * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered
1706 comparison operators.
1708 2020-04-03 Kewen Lin <linkw@gcc.gnu.org>
1710 PR tree-optimization/94443
1711 * tree-vect-loop.c (vectorizable_live_operation): Use
1712 gsi_insert_seq_before to replace gsi_insert_before.
1714 2020-04-03 Martin Liska <mliska@suse.cz>
1717 * ipa-icf-gimple.c (func_checker::compare_gimple_call):
1718 Compare type attributes for gimple_call_fntypes.
1720 2020-04-02 Sandra Loosemore <sandra@codesourcery.com>
1722 * alias.c (get_alias_set): Fix comment typos.
1724 2020-04-02 Fritz Reese <foreese@gcc.gnu.org>
1727 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
1728 attribute checking used by TYPE.
1730 2020-04-02 Martin Jambor <mjambor@suse.cz>
1733 * ipa-sra.c (struct caller_issues): New fields candidate and
1734 call_from_outside_comdat.
1735 (check_for_caller_issues): Check for calls from outsied of
1736 candidate's same_comdat_group.
1737 (check_all_callers_for_issues): Set up issues.candidate, check result
1739 (mark_callers_calls_comdat_local): New function.
1740 (process_isra_node_results): Set calls_comdat_local of callers if
1743 2020-04-02 Richard Biener <rguenther@suse.de>
1746 * common.opt (ffinite-loops): Initialize to zero.
1747 * opts.c (default_options_table): Remove OPT_ffinite_loops
1749 * cfgloop.h (loop::finite_p): New member.
1750 * cfgloopmanip.c (copy_loop_info): Copy finite_p.
1751 * ipa-icf-gimple.c (func_checker::compare_loops): Compare
1753 * lto-streamer-in.c (input_cfg): Stream finite_p.
1754 * lto-streamer-out.c (output_cfg): Likewise.
1755 * tree-cfg.c (replace_loop_annotate): Initialize finite_p
1756 from flag_finite_loops at CFG build time.
1757 * tree-ssa-loop-niter.c (finite_loop_p): Check the loops
1758 finite_p flag instead of flag_finite_loops.
1759 * doc/invoke.texi (ffinite-loops): Adjust documentation of
1762 2020-04-02 Richard Biener <rguenther@suse.de>
1765 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting
1766 DW_TAG_imported_unit.
1768 2020-04-02 Maciej W. Rozycki <macro@wdc.com>
1770 * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
1771 <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
1774 2020-04-02 Kewen Lin <linkw@gcc.gnu.org>
1776 PR tree-optimization/94401
1777 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE
1778 access type when loading halves of vector to avoid peeling for gaps.
1780 2020-04-02 Jakub Jelinek <jakub@redhat.com>
1782 * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in
1783 between a string literal and MIPS_SYSVERSION_SPEC macro.
1785 2020-04-02 Martin Jambor <mjambor@suse.cz>
1787 * doc/invoke.texi (Optimize Options): Document sra-max-propagations.
1789 2020-04-02 Jakub Jelinek <jakub@redhat.com>
1791 PR rtl-optimization/92264
1792 * params.opt (-param=max-find-base-term-values=): Decrease default
1795 PR rtl-optimization/92264
1796 * rtl.h (struct rtx_def): Mention that call bit is used as
1797 SP_DERIVED_VALUE_P in cselib.c.
1798 * cselib.c (SP_DERIVED_VALUE_P): Define.
1799 (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier.
1800 (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P
1801 val_rtx and sp based expression where offsets cancel each other.
1802 (preserve_constants_and_equivs): Formatting fix.
1803 (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P
1804 locs list for cfa_base_preserved_val if needed. Formatting fix.
1805 (autoinc_split): If the to be returned value is a REG, MEM or
1806 VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its
1807 locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off.
1808 (rtx_equal_for_cselib_1): Call autoinc_split even if both
1809 expressions are PLUS in Pmode with CONST_INT second operands.
1810 Handle SP_DERIVED_VALUE_P cases.
1811 (cselib_hash_plus_const_int): New function.
1812 (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT
1813 second operand, as well as for PRE_DEC etc. that ought to be
1814 hashed the same way.
1815 (cselib_subst_to_values): Substitute PLUS with Pmode and
1816 CONST_INT operand if the first operand is a VALUE which has
1817 SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the
1818 SP_DERIVED_VALUE_P + adjusted offset.
1819 (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx,
1820 set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding
1821 SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location.
1822 * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv
1823 on the sp value before calling cselib_add_permanent_equiv on the
1825 * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC
1826 in the insn without REG_INC note.
1827 (replace_read): Punt on RTX_AUTOINC in the *loc being replaced.
1828 Punt on invalid insns added by copy_to_mode_reg. Formatting fixes.
1831 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
1832 y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
1834 2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1837 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
1838 (LDRGBWBXU_Z_QUALIFIERS): Likewise.
1839 * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
1840 intrinsic defintion by adding a new builtin call to writeback into base
1842 (__arm_vldrdq_gather_base_wb_u64): Likewise.
1843 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
1844 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
1845 (__arm_vldrwq_gather_base_wb_s32): Likewise.
1846 (__arm_vldrwq_gather_base_wb_u32): Likewise.
1847 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
1848 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
1849 (__arm_vldrwq_gather_base_wb_f32): Likewise.
1850 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
1851 * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
1852 builtin's qualifier.
1853 (vldrdq_gather_base_wb_z_u): Likewise.
1854 (vldrwq_gather_base_wb_u): Likewise.
1855 (vldrdq_gather_base_wb_u): Likewise.
1856 (vldrwq_gather_base_wb_z_s): Likewise.
1857 (vldrwq_gather_base_wb_z_f): Likewise.
1858 (vldrdq_gather_base_wb_z_s): Likewise.
1859 (vldrwq_gather_base_wb_s): Likewise.
1860 (vldrwq_gather_base_wb_f): Likewise.
1861 (vldrdq_gather_base_wb_s): Likewise.
1862 (vldrwq_gather_base_nowb_z_u): Define builtin.
1863 (vldrdq_gather_base_nowb_z_u): Likewise.
1864 (vldrwq_gather_base_nowb_u): Likewise.
1865 (vldrdq_gather_base_nowb_u): Likewise.
1866 (vldrwq_gather_base_nowb_z_s): Likewise.
1867 (vldrwq_gather_base_nowb_z_f): Likewise.
1868 (vldrdq_gather_base_nowb_z_s): Likewise.
1869 (vldrwq_gather_base_nowb_s): Likewise.
1870 (vldrwq_gather_base_nowb_f): Likewise.
1871 (vldrdq_gather_base_nowb_s): Likewise.
1872 * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
1874 (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
1875 (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
1876 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
1877 (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
1878 (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
1879 (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
1880 (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
1881 (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
1882 (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern.
1883 (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
1884 (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern.
1886 2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
1888 * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
1889 ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
1890 ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
1891 ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
1892 ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
1893 ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
1894 ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
1895 ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
1896 ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
1898 ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
1899 ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
1900 Remove constraints from expander.
1901 * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
1902 ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
1903 ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
1904 ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
1905 ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
1906 ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.
1908 2020-04-01 Peter Bergner <bergner@linux.ibm.com>
1910 PR rtl-optimization/94123
1911 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for
1912 flag_split_wide_types_early.
1914 2020-04-01 Joerg Sonnenberger <joerg@bec.de>
1916 * doc/extend.texi (Common Function Attributes): Fix typo.
1918 2020-04-01 Segher Boessenkool <segher@kernel.crashing.org>
1921 * config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
1924 2020-04-01 Zackery Spytz <zspytz@gmail.com>
1926 * doc/extend.texi: Fix a typo in the documentation of the
1927 copy function attribute.
1929 2020-04-01 Jakub Jelinek <jakub@redhat.com>
1932 * tree-object-size.c (pass_object_sizes::execute): Don't call
1933 replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
1934 call replace_call_with_value.
1936 2020-04-01 Kewen Lin <linkw@gcc.gnu.org>
1938 PR tree-optimization/94043
1939 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed
1940 phi for vec_lhs and use it for lane extraction.
1942 2020-03-31 Felix Yang <felix.yang@huawei.com>
1944 PR tree-optimization/94398
1945 * tree-vect-stmts.c (vectorizable_store): Instead of calling
1946 vect_supportable_dr_alignment, set alignment_support_scheme to
1947 dr_unaligned_supported for gather-scatter accesses.
1948 (vectorizable_load): Likewise.
1950 2020-03-31 Andrew Stubbs <ams@codesourcery.com>
1952 * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
1954 (vnsi, VnSI, vndi, VnDI): New mode attributes.
1955 (mov<mode>): Use <VnDI> in place of V64DI.
1956 (mov<mode>_exec): Likewise.
1957 (mov<mode>_sgprbase): Likewise.
1958 (reload_out<mode>): Likewise.
1959 (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
1960 (gather_load<mode>v64si): Rename to ...
1961 (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
1962 and <VnDI> in place of V64DI.
1963 (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
1964 (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
1965 (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
1966 (scatter_store<mode>v64si): Rename to ...
1967 (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
1968 (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
1969 (scatter<mode>_insn_1offset<exec_scatter>): Likewise.
1970 (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
1971 (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
1972 (ds_bpermute<mode>): Use <VnSI>.
1973 (addv64si3_vcc<exec_vcc>): Rename to ...
1974 (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
1975 (addv64si3_vcc_dup<exec_vcc>): Rename to ...
1976 (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
1977 (addcv64si3<exec_vcc>): Rename to ...
1978 (addc<mode>3<exec_vcc>): ... this, and use V_SI.
1979 (subv64si3_vcc<exec_vcc>): Rename to ...
1980 (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
1981 (subcv64si3<exec_vcc>): Rename to ...
1982 (subc<mode>3<exec_vcc>): ... this, and use V_SI.
1983 (addv64di3): Rename to ...
1984 (add<mode>3): ... this, and use V_DI.
1985 (addv64di3_exec): Rename to ...
1986 (add<mode>3_exec): ... this, and use V_DI.
1987 (subv64di3): Rename to ...
1988 (sub<mode>3): ... this, and use V_DI.
1989 (subv64di3_exec): Rename to ...
1990 (sub<mode>3_exec): ... this, and use V_DI.
1991 (addv64di3_zext): Rename to ...
1992 (add<mode>3_zext): ... this, and use V_DI and <VnSI>.
1993 (addv64di3_zext_exec): Rename to ...
1994 (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
1995 (addv64di3_zext_dup): Rename to ...
1996 (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
1997 (addv64di3_zext_dup_exec): Rename to ...
1998 (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
1999 (addv64di3_zext_dup2): Rename to ...
2000 (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
2001 (addv64di3_zext_dup2_exec): Rename to ...
2002 (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
2003 (addv64di3_sext_dup2): Rename to ...
2004 (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
2005 (addv64di3_sext_dup2_exec): Rename to ...
2006 (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
2007 (<su>mulv64si3_highpart<exec>): Rename to ...
2008 (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
2009 (mulv64di3): Rename to ...
2010 (mul<mode>3): ... this, and use V_DI and <VnSI>.
2011 (mulv64di3_exec): Rename to ...
2012 (mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
2013 (mulv64di3_zext): Rename to ...
2014 (mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
2015 (mulv64di3_zext_exec): Rename to ...
2016 (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
2017 (mulv64di3_zext_dup2): Rename to ...
2018 (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
2019 (mulv64di3_zext_dup2_exec): Rename to ...
2020 (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
2021 (<expander>v64di3): Rename to ...
2022 (<expander><mode>3): ... this, and use V_DI and <VnSI>.
2023 (<expander>v64di3_exec): Rename to ...
2024 (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
2025 (<expander>v64si3<exec>): Rename to ...
2026 (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
2027 (v<expander>v64si3<exec>): Rename to ...
2028 (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
2029 (<expander>v64si3<exec>): Rename to ...
2030 (<expander><vnsi>3<exec>): ... this, and use V_SI.
2031 (subv64df3<exec>): Rename to ...
2032 (sub<mode>3<exec>): ... this, and use V_DF.
2033 (truncv64di<mode>2): Rename to ...
2034 (trunc<vndi><mode>2): ... this, and use <VnDI>.
2035 (truncv64di<mode>2_exec): Rename to ...
2036 (trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
2037 (<convop><mode>v64di2): Rename to ...
2038 (<convop><mode><vndi>2): ... this, and use <VnDI>.
2039 (<convop><mode>v64di2_exec): Rename to ...
2040 (<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
2041 (vec_cmp<u>v64qidi): Rename to ...
2042 (vec_cmp<u><mode>di): ... this, and use <VnSI>.
2043 (vec_cmp<u>v64qidi_exec): Rename to ...
2044 (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
2045 (vcond_mask_<mode>di): Use <VnDI>.
2046 (maskload<mode>di): Likewise.
2047 (maskstore<mode>di): Likewise.
2048 (mask_gather_load<mode>v64si): Rename to ...
2049 (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
2050 (mask_scatter_store<mode>v64si): Rename to ...
2051 (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
2052 (*<reduc_op>_dpp_shr_v64di): Rename to ...
2053 (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
2054 (*plus_carry_in_dpp_shr_v64si): Rename to ...
2055 (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
2056 (*plus_carry_dpp_shr_v64di): Rename to ...
2057 (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
2058 (vec_seriesv64si): Rename to ...
2059 (vec_series<mode>): ... this, and use V_SI.
2060 (vec_seriesv64di): Rename to ...
2061 (vec_series<mode>): ... this, and use V_DI.
2063 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
2065 * config/arc/arc.c (arc_print_operand): Use
2066 HOST_WIDE_INT_PRINT_DEC macro.
2068 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
2070 * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
2072 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2074 * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
2076 (__arm_vbicq): Likewise.
2078 2020-03-31 Vineet Gupta <vgupta@synopsys.com>
2080 * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.
2082 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2084 * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
2085 common section of both MVE Integer and MVE Floating Point.
2087 (vaddlvq_p): Likewise.
2088 (vaddvaq): Likewise.
2089 (vaddvq_p): Likewise.
2090 (vcmpcsq): Likewise.
2091 (vmlsdavxq): Likewise.
2092 (vmlsdavq): Likewise.
2093 (vmladavxq): Likewise.
2094 (vmladavq): Likewise.
2096 (vminavq): Likewise.
2098 (vmaxavq): Likewise.
2099 (vmlaldavq): Likewise.
2100 (vcmphiq): Likewise.
2101 (vaddlvaq): Likewise.
2102 (vrmlaldavhq): Likewise.
2103 (vrmlaldavhxq): Likewise.
2104 (vrmlsldavhq): Likewise.
2105 (vrmlsldavhxq): Likewise.
2106 (vmlsldavxq): Likewise.
2107 (vmlsldavq): Likewise.
2109 (vrmlaldavhaq): Likewise.
2110 (vcmpgeq_m_n): Likewise.
2111 (vmlsdavxq_p): Likewise.
2112 (vmlsdavq_p): Likewise.
2113 (vmlsdavaxq): Likewise.
2114 (vmlsdavaq): Likewise.
2115 (vaddvaq_p): Likewise.
2116 (vcmpcsq_m_n): Likewise.
2117 (vcmpcsq_m): Likewise.
2118 (vmladavxq_p): Likewise.
2119 (vmladavq_p): Likewise.
2120 (vmladavaxq): Likewise.
2121 (vmladavaq): Likewise.
2122 (vminvq_p): Likewise.
2123 (vminavq_p): Likewise.
2124 (vmaxvq_p): Likewise.
2125 (vmaxavq_p): Likewise.
2126 (vcmphiq_m): Likewise.
2127 (vaddlvaq_p): Likewise.
2128 (vmlaldavaq): Likewise.
2129 (vmlaldavaxq): Likewise.
2130 (vmlaldavq_p): Likewise.
2131 (vmlaldavxq_p): Likewise.
2132 (vmlsldavaq): Likewise.
2133 (vmlsldavaxq): Likewise.
2134 (vmlsldavq_p): Likewise.
2135 (vmlsldavxq_p): Likewise.
2136 (vrmlaldavhaxq): Likewise.
2137 (vrmlaldavhq_p): Likewise.
2138 (vrmlaldavhxq_p): Likewise.
2139 (vrmlsldavhaq): Likewise.
2140 (vrmlsldavhaxq): Likewise.
2141 (vrmlsldavhq_p): Likewise.
2142 (vrmlsldavhxq_p): Likewise.
2143 (vabavq_p): Likewise.
2144 (vmladavaq_p): Likewise.
2145 (vstrbq_scatter_offset): Likewise.
2146 (vstrbq_p): Likewise.
2147 (vstrbq_scatter_offset_p): Likewise.
2148 (vstrdq_scatter_base_p): Likewise.
2149 (vstrdq_scatter_base): Likewise.
2150 (vstrdq_scatter_offset_p): Likewise.
2151 (vstrdq_scatter_offset): Likewise.
2152 (vstrdq_scatter_shifted_offset_p): Likewise.
2153 (vstrdq_scatter_shifted_offset): Likewise.
2154 (vmaxq_x): Likewise.
2155 (vminq_x): Likewise.
2156 (vmovlbq_x): Likewise.
2157 (vmovltq_x): Likewise.
2158 (vmulhq_x): Likewise.
2159 (vmullbq_int_x): Likewise.
2160 (vmullbq_poly_x): Likewise.
2161 (vmulltq_int_x): Likewise.
2162 (vmulltq_poly_x): Likewise.
2165 2020-03-31 Jakub Jelinek <jakub@redhat.com>
2168 * config/aarch64/constraints.md (Uph): New constraint.
2169 * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
2170 (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
2173 2020-03-31 Marc Glisse <marc.glisse@inria.fr>
2174 Jakub Jelinek <jakub@redhat.com>
2177 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
2178 ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.
2180 2020-03-31 Jakub Jelinek <jakub@redhat.com>
2182 PR tree-optimization/94403
2183 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
2184 ENUMERAL_TYPE lhs_type.
2186 PR rtl-optimization/94344
2187 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
2188 conversions, either on both operands of |^+ or just one. Handle
2189 also extra same precision conversion on RSHIFT_EXPR first operand
2190 provided RSHIFT_EXPR is performed in unsigned type.
2192 2020-03-30 David Malcolm <dmalcolm@redhat.com>
2194 * lra.c (finish_insn_code_data_once): Set the array elements
2195 to NULL after freeing them.
2197 2020-03-30 Andreas Schwab <schwab@suse.de>
2199 * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
2202 2020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com>
2204 * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
2205 to skip defining builtins based on builtin_mask.
2207 2020-03-30 Jakub Jelinek <jakub@redhat.com>
2210 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
2211 !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
2212 operand is a register. Don't enable masked variants for V*[QH]Imode.
2215 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
2216 <store_mask_constraint> instead of m in output operand constraint.
2217 (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
2220 2020-03-30 Alan Modra <amodra@gmail.com>
2222 * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
2223 (rs6000_indirect_call_template_1): Adjust to suit.
2224 * config/rs6000/rs6000.md (call_local): Merge call_local32,
2225 call_local64, and call_local_aix.
2226 (call_value_local): Simlarly.
2227 (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
2228 and disable pattern when CALL_LONG.
2229 (call_indirect_aix, call_value_indirect_aix): Adjust rtl.
2230 (call_indirect_elfv2, call_indirect_pcrel): Likewise.
2231 (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
2233 2020-03-29 H.J. Lu <hongjiu.lu@intel.com>
2236 * doc/invoke.texi: Update -falign-functions, -falign-loops and
2237 -falign-jumps documentation.
2239 2020-03-29 Martin Liska <mliska@suse.cz>
2242 * cgraphunit.c (process_function_and_variable_attributes): Remove
2243 double 'attribute' words.
2245 2020-03-29 John David Anglin <dave.anglin@bell.net>
2247 * gcc/config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
2250 2020-03-28 Jakub Jelinek <jakub@redhat.com>
2253 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const
2254 to true after setting size to integer_one_node.
2256 PR tree-optimization/94329
2257 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
2258 on the last stmt in a bb, make sure gsi_prev isn't done immediately
2261 2020-03-27 Alan Modra <amodra@gmail.com>
2264 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
2265 for PLT16_LO and PLT_PCREL.
2266 * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
2267 (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
2268 (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.
2270 2020-03-27 Martin Sebor <msebor@redhat.com>
2273 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes.
2275 2020-03-27 Andrew Stubbs <ams@codesourcery.com>
2277 * config/gcn/gcn-valu.md:
2278 (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout.
2279 (VEC_1REG_MODE): Delete.
2280 (VEC_1REG_ALT): Delete.
2281 (VEC_ALL1REG_MODE): Rename to V_1REG throughout.
2282 (VEC_1REG_INT_MODE): Delete.
2283 (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout.
2284 (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout.
2285 (VEC_2REG_MODE): Rename to V_2REG throughout.
2286 (VEC_REG_MODE): Rename to V_noHI throughout.
2287 (VEC_ALLREG_MODE): Rename to V_ALL throughout.
2288 (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout.
2289 (VEC_ALLREG_INT_MODE): Rename to V_INT throughout.
2290 (VEC_INT_MODE): Delete.
2291 (VEC_FP_MODE): Rename to V_FP throughout and move to top.
2292 (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top.
2293 (FP_MODE): Delete and replace with FP throughout.
2294 (FP_1REG_MODE): Delete and replace with FP_1REG throughout.
2295 (VCMP_MODE): Rename to V_noQI throughout and move to top.
2296 (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top.
2297 * config/gcn/gcn.md (FP): New mode iterator.
2298 (FP_1REG): New mode iterator.
2300 2020-03-27 David Malcolm <dmalcolm@redhat.com>
2302 * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this
2303 now emits two .dot files.
2304 * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD.
2305 (graphviz_out::end_tr): Only close a TR, not a TD.
2306 (graphviz_out::begin_td): New.
2307 (graphviz_out::end_td): New.
2308 (graphviz_out::begin_trtd): New, replacing the old implementation
2309 of graphviz_out::begin_tr.
2310 (graphviz_out::end_tdtr): New, replacing the old implementation
2311 of graphviz_out::end_tr.
2312 * graphviz.h (graphviz_out::begin_td): New decl.
2313 (graphviz_out::end_td): New decl.
2314 (graphviz_out::begin_trtd): New decl.
2315 (graphviz_out::end_tdtr): New decl.
2317 2020-03-27 Richard Biener <rguenther@suse.de>
2320 * dwarf2out.c (should_emit_struct_debug): Return false for
2323 2020-03-27 Richard Biener <rguenther@suse.de>
2325 PR tree-optimization/94352
2326 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the
2328 (ssa_propagation_engine::ssa_propagate): ... here after
2329 initializing curr_order.
2331 2020-03-27 Kewen Lin <linkw@gcc.gnu.org>
2333 PR tree-optimization/90332
2334 * tree-vect-stmts.c (vector_vector_composition_type): New function.
2335 (get_group_load_store_type): Adjust to call
2336 vector_vector_composition_type, extend it to construct with scalar
2338 (vectorizable_load): Likewise.
2340 2020-03-27 Roman Zhuykov <zhroma@ispras.ru>
2342 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions.
2343 (create_ddg_dep_no_link): Likewise.
2344 (add_cross_iteration_register_deps): Move debug instruction check.
2345 Other minor refactoring.
2346 (add_intra_loop_mem_dep): Do not check for debug instructions.
2347 (add_inter_loop_mem_dep): Likewise.
2348 (build_intra_loop_deps): Likewise.
2349 (create_ddg): Do not include debug insns into the graph.
2350 * ddg.h (struct ddg): Remove num_debug field.
2351 * modulo-sched.c (doloop_register_get): Adjust condition.
2352 (res_MII): Remove DDG num_debug field usage.
2353 (sms_schedule_by_order): Use assertion against debug insns.
2354 (ps_has_conflicts): Drop debug insn check.
2356 2020-03-26 Jakub Jelinek <jakub@redhat.com>
2359 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST
2360 that contains exactly one non-DEBUG_BEGIN_STMT statement.
2363 * gimple.h (gimple_seq_first_nondebug_stmt): New function.
2364 (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains
2365 a single non-debug stmt followed by one or more debug stmts.
2366 * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt
2367 instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt
2368 and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and
2369 gimple_seq_last to check if outer_stmt gbind could be reused and
2370 if yes and it is surrounded by any debug stmts, move them into the
2373 PR rtl-optimization/92264
2374 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even
2375 for sp based values in !frame_pointer_needed
2376 && !ACCUMULATE_OUTGOING_ARGS functions.
2378 2020-03-26 Felix Yang <felix.yang@huawei.com>
2380 PR tree-optimization/94269
2381 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict
2383 operation to single basic block.
2385 2020-03-25 Jeff Law <law@redhat.com>
2387 PR rtl-optimization/90275
2388 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the
2391 2020-03-25 Jakub Jelinek <jakub@redhat.com>
2394 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to
2395 mode rather than VOIDmode.
2397 2020-03-25 Martin Sebor <msebor@redhat.com>
2400 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings
2401 even for alloca calls resulting from system macro expansion.
2402 Include inlining context in all warnings.
2404 2020-03-25 Richard Sandiford <richard.sandiford@arm.com>
2407 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow
2408 FPRs to change between SDmode and DDmode.
2410 2020-03-25 Martin Sebor <msebor@redhat.com>
2412 PR tree-optimization/94131
2413 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length
2415 * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming
2416 types have constant sizes.
2418 2020-03-25 Martin Liska <mliska@suse.cz>
2421 * configure.ac: Report error only when --with-zstd
2423 * configure: Regenerate.
2425 2020-03-25 Jakub Jelinek <jakub@redhat.com>
2428 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
2429 INSN_CODE (insn) to -1 when changing the pattern.
2431 2020-03-25 Martin Liska <mliska@suse.cz>
2435 * config/i386/i386-features.c (make_resolver_func): Drop
2436 public flag for resolver.
2437 * config/rs6000/rs6000.c (make_resolver_func): Add comdat
2438 group for resolver and drop public flag if possible.
2439 * multiple_target.c (create_dispatcher_calls): Drop unique_name
2440 and resolution as we want to enable LTO privatization of the default
2443 2020-03-25 Martin Liska <mliska@suse.cz>
2446 * configure.ac: Respect --without-zstd and report
2447 error when we can't find header file with --with-zstd.
2448 * configure: Regenerate.
2450 2020-03-25 Jakub Jelinek <jakub@redhat.com>
2453 * varasm.c (output_constructor_array_range): If local->index
2454 RANGE_EXPR doesn't start at the current location in the constructor,
2455 skip needed number of bytes using assemble_zeros or assert we don't
2459 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong
2460 counter instead of DECL_UID.
2462 PR tree-optimization/94300
2463 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset
2464 is positive, make sure that off + size isn't larger than needed_len.
2466 2020-03-25 Richard Biener <rguenther@suse.de>
2467 Jakub Jelinek <jakub@redhat.com>
2470 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards.
2472 2020-03-24 Christophe Lyon <christophe.lyon@linaro.org>
2474 * doc/sourcebuild.texi (ARM-specific attributes): Add
2476 (Features for dg-add-options): Add arm_fp_dp.
2478 2020-03-24 John David Anglin <danglin@gcc.gnu.org>
2481 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__.
2483 2020-03-24 Tobias Burnus <tobias@codesourcery.com>
2486 * omp-offload.c (omp_finish_file): Fix target-link handling if
2487 targetm_common.have_named_sections is false.
2489 2020-03-24 Jakub Jelinek <jakub@redhat.com>
2492 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode
2496 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to
2497 e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts.
2498 If not after and at *incr_pos is a debug stmt, set stmt location to
2499 location of next non-debug stmt after it if any.
2502 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set
2503 GF_PLF_2, but don't add them to worklist. Don't add an assigment to
2504 worklist or set GF_PLF_2 just because it is used in a debug stmt in
2505 another bb. Formatting improvements.
2508 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and
2509 non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC
2510 regardless of whether TREE_NO_WARNING is set on it or whether
2511 warn_unused_function is true or not.
2513 2020-03-23 Jeff Law <law@redhat.com>
2515 PR rtl-optimization/90275
2518 * simplify-rtx.c (comparison_code_valid_for_mode): New function.
2519 (simplify_logical_relational_operation): Use it.
2521 2020-03-23 Jakub Jelinek <jakub@redhat.com>
2524 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on
2525 ultimate rhs and if returned something different, reconstructing
2528 2020-03-23 Lewis Hyatt <lhyatt@gmail.com>
2530 * opts.c (print_filtered_help): Improve the help text for alias options.
2532 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2533 Andre Vieira <andre.simoesdiasvieira@arm.com>
2534 Mihail Ionescu <mihail.ionescu@arm.com>
2536 * config/arm/arm_mve.h (vshlcq_m_s8): Define macro.
2537 (vshlcq_m_u8): Likewise.
2538 (vshlcq_m_s16): Likewise.
2539 (vshlcq_m_u16): Likewise.
2540 (vshlcq_m_s32): Likewise.
2541 (vshlcq_m_u32): Likewise.
2542 (__arm_vshlcq_m_s8): Define intrinsic.
2543 (__arm_vshlcq_m_u8): Likewise.
2544 (__arm_vshlcq_m_s16): Likewise.
2545 (__arm_vshlcq_m_u16): Likewise.
2546 (__arm_vshlcq_m_s32): Likewise.
2547 (__arm_vshlcq_m_u32): Likewise.
2548 (vshlcq_m): Define polymorphic variant.
2549 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE):
2550 Use builtin qualifier.
2551 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
2552 * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define RTL pattern.
2553 (mve_vshlcq_m_carry_<supf><mode>): Likewise.
2554 (mve_vshlcq_m_<supf><mode>): Likewise.
2556 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2558 * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier.
2559 (UQSHL_QUALIFIERS): Likewise.
2560 (ASRL_QUALIFIERS): Likewise.
2561 (SQSHL_QUALIFIERS): Likewise.
2562 * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in
2564 (sqrshr): Define macro.
2565 (sqrshrl): Likewise.
2566 (sqrshrl_sat48): Likewise.
2572 (uqrshll): Likewise.
2573 (uqrshll_sat48): Likewise.
2580 (__arm_lsll): Define intrinsic.
2581 (__arm_asrl): Likewise.
2582 (__arm_uqrshll): Likewise.
2583 (__arm_uqrshll_sat48): Likewise.
2584 (__arm_sqrshrl): Likewise.
2585 (__arm_sqrshrl_sat48): Likewise.
2586 (__arm_uqshll): Likewise.
2587 (__arm_urshrl): Likewise.
2588 (__arm_srshrl): Likewise.
2589 (__arm_sqshll): Likewise.
2590 (__arm_uqrshl): Likewise.
2591 (__arm_sqrshr): Likewise.
2592 (__arm_uqshl): Likewise.
2593 (__arm_urshr): Likewise.
2594 (__arm_sqshl): Likewise.
2595 (__arm_srshr): Likewise.
2596 * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin
2598 (UQSHL_QUALIFIERS): Likewise.
2599 (ASRL_QUALIFIERS): Likewise.
2600 (SQSHL_QUALIFIERS): Likewise.
2601 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern.
2602 (mve_sqrshrl_sat<supf>_di): Likewise.
2603 (mve_uqrshl_si): Likewise.
2604 (mve_sqrshr_si): Likewise.
2605 (mve_uqshll_di): Likewise.
2606 (mve_urshrl_di): Likewise.
2607 (mve_uqshl_si): Likewise.
2608 (mve_urshr_si): Likewise.
2609 (mve_sqshl_si): Likewise.
2610 (mve_srshr_si): Likewise.
2611 (mve_srshrl_di): Likewise.
2612 (mve_sqshll_di): Likewise.
2614 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2615 Andre Vieira <andre.simoesdiasvieira@arm.com>
2616 Mihail Ionescu <mihail.ionescu@arm.com>
2618 * config/arm/arm_mve.h (vsetq_lane_f16): Define macro.
2619 (vsetq_lane_f32): Likewise.
2620 (vsetq_lane_s16): Likewise.
2621 (vsetq_lane_s32): Likewise.
2622 (vsetq_lane_s8): Likewise.
2623 (vsetq_lane_s64): Likewise.
2624 (vsetq_lane_u8): Likewise.
2625 (vsetq_lane_u16): Likewise.
2626 (vsetq_lane_u32): Likewise.
2627 (vsetq_lane_u64): Likewise.
2628 (vgetq_lane_f16): Likewise.
2629 (vgetq_lane_f32): Likewise.
2630 (vgetq_lane_s16): Likewise.
2631 (vgetq_lane_s32): Likewise.
2632 (vgetq_lane_s8): Likewise.
2633 (vgetq_lane_s64): Likewise.
2634 (vgetq_lane_u8): Likewise.
2635 (vgetq_lane_u16): Likewise.
2636 (vgetq_lane_u32): Likewise.
2637 (vgetq_lane_u64): Likewise.
2638 (__ARM_NUM_LANES): Likewise.
2639 (__ARM_LANEQ): Likewise.
2640 (__ARM_CHECK_LANEQ): Likewise.
2641 (__arm_vsetq_lane_s16): Define intrinsic.
2642 (__arm_vsetq_lane_s32): Likewise.
2643 (__arm_vsetq_lane_s8): Likewise.
2644 (__arm_vsetq_lane_s64): Likewise.
2645 (__arm_vsetq_lane_u8): Likewise.
2646 (__arm_vsetq_lane_u16): Likewise.
2647 (__arm_vsetq_lane_u32): Likewise.
2648 (__arm_vsetq_lane_u64): Likewise.
2649 (__arm_vgetq_lane_s16): Likewise.
2650 (__arm_vgetq_lane_s32): Likewise.
2651 (__arm_vgetq_lane_s8): Likewise.
2652 (__arm_vgetq_lane_s64): Likewise.
2653 (__arm_vgetq_lane_u8): Likewise.
2654 (__arm_vgetq_lane_u16): Likewise.
2655 (__arm_vgetq_lane_u32): Likewise.
2656 (__arm_vgetq_lane_u64): Likewise.
2657 (__arm_vsetq_lane_f16): Likewise.
2658 (__arm_vsetq_lane_f32): Likewise.
2659 (__arm_vgetq_lane_f16): Likewise.
2660 (__arm_vgetq_lane_f32): Likewise.
2661 (vgetq_lane): Define polymorphic variant.
2662 (vsetq_lane): Likewise.
2663 * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Define RTL
2665 (mve_vec_extractv2didi): Likewise.
2666 (mve_vec_extract_sext_internal<mode>): Likewise.
2667 (mve_vec_extract_zext_internal<mode>): Likewise.
2668 (mve_vec_set<mode>_internal): Likewise.
2669 (mve_vec_setv2di_internal): Likewise.
2670 * config/arm/neon.md (vec_set<mode>): Move RTL pattern to vec-common.md
2672 (vec_extract<mode><V_elem_l>): Rename to
2673 "neon_vec_extract<mode><V_elem_l>".
2674 (vec_extractv2didi): Rename to "neon_vec_extractv2didi".
2675 * config/arm/vec-common.md (vec_extract<mode><V_elem_l>): Define RTL
2676 pattern common for MVE and NEON.
2677 (vec_set<mode>): Move RTL pattern from neon.md and modify to accept both
2680 2020-03-23 Andre Vieira <andre.simoesdiasvieira@arm.com>
2682 * config/arm/mve.md (earlyclobber_32): New mode attribute.
2683 (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
2684 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers.
2686 2020-03-23 Richard Biener <rguenther@suse.de>
2688 PR tree-optimization/94261
2689 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove
2690 IL operand swapping code.
2691 (vect_slp_rearrange_stmts): Do not arrange isomorphic
2692 nodes that would need operation code adjustments.
2694 2020-03-23 Tobias Burnus <tobias@codesourcery.com>
2696 * doc/install.texi (amdgcn-*-amdhsa): Renamed
2697 from amdgcn-unknown-amdhsa; change
2698 amdgcn-unknown-amdhsa to amdgcn-amdhsa.
2700 2020-03-23 Richard Biener <rguenther@suse.de>
2703 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP
2704 directly rather than also folding it via build_fold_addr_expr.
2706 2020-03-23 Richard Biener <rguenther@suse.de>
2708 PR tree-optimization/94266
2709 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate
2710 addresses of TARGET_MEM_REFs.
2712 2020-03-23 Martin Liska <mliska@suse.cz>
2715 * symtab.c (symtab_node::clone_references): Save speculative_id
2716 as ref may be overwritten by create_reference.
2717 (symtab_node::clone_referring): Likewise.
2718 (symtab_node::clone_reference): Likewise.
2720 2020-03-22 Iain Sandoe <iain@sandoe.co.uk>
2722 * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove
2723 references to Darwin.
2724 * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this
2725 unconditionally and comment on why.
2727 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
2729 * config/darwin.c (darwin_mergeable_constant_section): Collect
2730 section anchor checks into the caller.
2731 (machopic_select_section): Collect section anchor checks into
2732 the determination of 'effective zero-size' objects. When the
2733 size is unknown, assume it is non-zero, and thus return the
2734 'generic' section for the DECL.
2736 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
2739 * gcc/config/darwin.opt: Amend options descriptions.
2741 2020-03-21 Richard Sandiford <richard.sandiford@arm.com>
2743 PR rtl-optimization/94052
2744 * lra-constraints.c (simplify_operand_subreg): Reload the inner
2745 register of a paradoxical subreg if simplify_subreg_regno fails
2746 to give a valid hard register for the outer mode.
2748 2020-03-20 Martin Jambor <mjambor@suse.cz>
2750 PR tree-optimization/93435
2751 * params.opt (sra-max-propagations): New parameter.
2752 * tree-sra.c (propagation_budget): New variable.
2753 (budget_for_propagation_access): New function.
2754 (propagate_subaccesses_from_rhs): Use it.
2755 (propagate_subaccesses_from_lhs): Likewise.
2756 (propagate_all_subaccesses): Set up and destroy propagation_budget.
2758 2020-03-20 Carl Love <cel@us.ibm.com>
2761 * gcc/config/rs6000/rs6000.c (rs6000_option_override_internal):
2762 Add check for TARGET_FPRND for Power 7 or newer.
2764 2020-03-20 Jan Hubicka <hubicka@ucw.cz>
2767 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag.
2768 (cgraph_edge::redirect_callee): Move here; likewise.
2769 (cgraph_node::remove_callees): Update calls_comdat_local flag.
2770 (cgraph_node::verify_node): Verify that calls_comdat_local flag match
2772 (cgraph_node::check_calls_comdat_local_p): New member function.
2773 * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare.
2774 (cgraph_edge::redirect_callee): Move offline.
2775 * ipa-fnsummary.c (compute_fn_summary): Do not compute
2776 calls_comdat_local flag here.
2777 * ipa-inline-transform.c (inline_call): Fix updating of
2778 calls_comdat_local flag.
2779 * ipa-split.c (split_function): Use true instead of 1 to set the flag.
2780 * symtab.c (symtab_node::add_to_same_comdat_group): Update
2781 calls_comdat_local flag.
2783 2020-03-20 Richard Biener <rguenther@suse.de>
2785 * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree
2786 from the possibly modified root.
2788 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2789 Andre Vieira <andre.simoesdiasvieira@arm.com>
2790 Mihail Ionescu <mihail.ionescu@arm.com>
2792 * config/arm/arm_mve.h (vst1q_p_u8): Define macro.
2793 (vst1q_p_s8): Likewise.
2794 (vst2q_s8): Likewise.
2795 (vst2q_u8): Likewise.
2796 (vld1q_z_u8): Likewise.
2797 (vld1q_z_s8): Likewise.
2798 (vld2q_s8): Likewise.
2799 (vld2q_u8): Likewise.
2800 (vld4q_s8): Likewise.
2801 (vld4q_u8): Likewise.
2802 (vst1q_p_u16): Likewise.
2803 (vst1q_p_s16): Likewise.
2804 (vst2q_s16): Likewise.
2805 (vst2q_u16): Likewise.
2806 (vld1q_z_u16): Likewise.
2807 (vld1q_z_s16): Likewise.
2808 (vld2q_s16): Likewise.
2809 (vld2q_u16): Likewise.
2810 (vld4q_s16): Likewise.
2811 (vld4q_u16): Likewise.
2812 (vst1q_p_u32): Likewise.
2813 (vst1q_p_s32): Likewise.
2814 (vst2q_s32): Likewise.
2815 (vst2q_u32): Likewise.
2816 (vld1q_z_u32): Likewise.
2817 (vld1q_z_s32): Likewise.
2818 (vld2q_s32): Likewise.
2819 (vld2q_u32): Likewise.
2820 (vld4q_s32): Likewise.
2821 (vld4q_u32): Likewise.
2822 (vld4q_f16): Likewise.
2823 (vld2q_f16): Likewise.
2824 (vld1q_z_f16): Likewise.
2825 (vst2q_f16): Likewise.
2826 (vst1q_p_f16): Likewise.
2827 (vld4q_f32): Likewise.
2828 (vld2q_f32): Likewise.
2829 (vld1q_z_f32): Likewise.
2830 (vst2q_f32): Likewise.
2831 (vst1q_p_f32): Likewise.
2832 (__arm_vst1q_p_u8): Define intrinsic.
2833 (__arm_vst1q_p_s8): Likewise.
2834 (__arm_vst2q_s8): Likewise.
2835 (__arm_vst2q_u8): Likewise.
2836 (__arm_vld1q_z_u8): Likewise.
2837 (__arm_vld1q_z_s8): Likewise.
2838 (__arm_vld2q_s8): Likewise.
2839 (__arm_vld2q_u8): Likewise.
2840 (__arm_vld4q_s8): Likewise.
2841 (__arm_vld4q_u8): Likewise.
2842 (__arm_vst1q_p_u16): Likewise.
2843 (__arm_vst1q_p_s16): Likewise.
2844 (__arm_vst2q_s16): Likewise.
2845 (__arm_vst2q_u16): Likewise.
2846 (__arm_vld1q_z_u16): Likewise.
2847 (__arm_vld1q_z_s16): Likewise.
2848 (__arm_vld2q_s16): Likewise.
2849 (__arm_vld2q_u16): Likewise.
2850 (__arm_vld4q_s16): Likewise.
2851 (__arm_vld4q_u16): Likewise.
2852 (__arm_vst1q_p_u32): Likewise.
2853 (__arm_vst1q_p_s32): Likewise.
2854 (__arm_vst2q_s32): Likewise.
2855 (__arm_vst2q_u32): Likewise.
2856 (__arm_vld1q_z_u32): Likewise.
2857 (__arm_vld1q_z_s32): Likewise.
2858 (__arm_vld2q_s32): Likewise.
2859 (__arm_vld2q_u32): Likewise.
2860 (__arm_vld4q_s32): Likewise.
2861 (__arm_vld4q_u32): Likewise.
2862 (__arm_vld4q_f16): Likewise.
2863 (__arm_vld2q_f16): Likewise.
2864 (__arm_vld1q_z_f16): Likewise.
2865 (__arm_vst2q_f16): Likewise.
2866 (__arm_vst1q_p_f16): Likewise.
2867 (__arm_vld4q_f32): Likewise.
2868 (__arm_vld2q_f32): Likewise.
2869 (__arm_vld1q_z_f32): Likewise.
2870 (__arm_vst2q_f32): Likewise.
2871 (__arm_vst1q_p_f32): Likewise.
2872 (vld1q_z): Define polymorphic variant.
2875 (vst1q_p): Likewise.
2877 * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier.
2879 * config/arm/mve.md (mve_vst2q<mode>): Define RTL pattern.
2880 (mve_vld2q<mode>): Likewise.
2881 (mve_vld4q<mode>): Likewise.
2883 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2884 Andre Vieira <andre.simoesdiasvieira@arm.com>
2885 Mihail Ionescu <mihail.ionescu@arm.com>
2887 * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define.
2888 (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise.
2889 (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and
2890 "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array.
2891 (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC
2892 and ARM_BUILTIN_SET_FPSCR_NZCVQC.
2893 * config/arm/arm_mve.h (vadciq_s32): Define macro.
2894 (vadciq_u32): Likewise.
2895 (vadciq_m_s32): Likewise.
2896 (vadciq_m_u32): Likewise.
2897 (vadcq_s32): Likewise.
2898 (vadcq_u32): Likewise.
2899 (vadcq_m_s32): Likewise.
2900 (vadcq_m_u32): Likewise.
2901 (vsbciq_s32): Likewise.
2902 (vsbciq_u32): Likewise.
2903 (vsbciq_m_s32): Likewise.
2904 (vsbciq_m_u32): Likewise.
2905 (vsbcq_s32): Likewise.
2906 (vsbcq_u32): Likewise.
2907 (vsbcq_m_s32): Likewise.
2908 (vsbcq_m_u32): Likewise.
2909 (__arm_vadciq_s32): Define intrinsic.
2910 (__arm_vadciq_u32): Likewise.
2911 (__arm_vadciq_m_s32): Likewise.
2912 (__arm_vadciq_m_u32): Likewise.
2913 (__arm_vadcq_s32): Likewise.
2914 (__arm_vadcq_u32): Likewise.
2915 (__arm_vadcq_m_s32): Likewise.
2916 (__arm_vadcq_m_u32): Likewise.
2917 (__arm_vsbciq_s32): Likewise.
2918 (__arm_vsbciq_u32): Likewise.
2919 (__arm_vsbciq_m_s32): Likewise.
2920 (__arm_vsbciq_m_u32): Likewise.
2921 (__arm_vsbcq_s32): Likewise.
2922 (__arm_vsbcq_u32): Likewise.
2923 (__arm_vsbcq_m_s32): Likewise.
2924 (__arm_vsbcq_m_u32): Likewise.
2925 (vadciq_m): Define polymorphic variant.
2927 (vadcq_m): Likewise.
2929 (vsbciq_m): Likewise.
2931 (vsbcq_m): Likewise.
2933 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin
2935 (BINOP_UNONE_UNONE_UNONE): Likewise.
2936 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
2937 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
2938 * config/arm/mve.md (VADCIQ): Define iterator.
2939 (VADCIQ_M): Likewise.
2941 (VSBCQ_M): Likewise.
2943 (VSBCIQ_M): Likewise.
2945 (VADCQ_M): Likewise.
2946 (mve_vadciq_m_<supf>v4si): Define RTL pattern.
2947 (mve_vadciq_<supf>v4si): Likewise.
2948 (mve_vadcq_m_<supf>v4si): Likewise.
2949 (mve_vadcq_<supf>v4si): Likewise.
2950 (mve_vsbciq_m_<supf>v4si): Likewise.
2951 (mve_vsbciq_<supf>v4si): Likewise.
2952 (mve_vsbcq_m_<supf>v4si): Likewise.
2953 (mve_vsbcq_<supf>v4si): Likewise.
2954 (get_fpscr_nzcvqc): Define isns.
2955 (set_fpscr_nzcvqc): Define isns.
2956 * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define.
2957 (UNSPEC_SET_FPSCR_NZCVQC): Define.
2959 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2961 * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro.
2962 (vddupq_x_n_u16): Likewise.
2963 (vddupq_x_n_u32): Likewise.
2964 (vddupq_x_wb_u8): Likewise.
2965 (vddupq_x_wb_u16): Likewise.
2966 (vddupq_x_wb_u32): Likewise.
2967 (vdwdupq_x_n_u8): Likewise.
2968 (vdwdupq_x_n_u16): Likewise.
2969 (vdwdupq_x_n_u32): Likewise.
2970 (vdwdupq_x_wb_u8): Likewise.
2971 (vdwdupq_x_wb_u16): Likewise.
2972 (vdwdupq_x_wb_u32): Likewise.
2973 (vidupq_x_n_u8): Likewise.
2974 (vidupq_x_n_u16): Likewise.
2975 (vidupq_x_n_u32): Likewise.
2976 (vidupq_x_wb_u8): Likewise.
2977 (vidupq_x_wb_u16): Likewise.
2978 (vidupq_x_wb_u32): Likewise.
2979 (viwdupq_x_n_u8): Likewise.
2980 (viwdupq_x_n_u16): Likewise.
2981 (viwdupq_x_n_u32): Likewise.
2982 (viwdupq_x_wb_u8): Likewise.
2983 (viwdupq_x_wb_u16): Likewise.
2984 (viwdupq_x_wb_u32): Likewise.
2985 (vdupq_x_n_s8): Likewise.
2986 (vdupq_x_n_s16): Likewise.
2987 (vdupq_x_n_s32): Likewise.
2988 (vdupq_x_n_u8): Likewise.
2989 (vdupq_x_n_u16): Likewise.
2990 (vdupq_x_n_u32): Likewise.
2991 (vminq_x_s8): Likewise.
2992 (vminq_x_s16): Likewise.
2993 (vminq_x_s32): Likewise.
2994 (vminq_x_u8): Likewise.
2995 (vminq_x_u16): Likewise.
2996 (vminq_x_u32): Likewise.
2997 (vmaxq_x_s8): Likewise.
2998 (vmaxq_x_s16): Likewise.
2999 (vmaxq_x_s32): Likewise.
3000 (vmaxq_x_u8): Likewise.
3001 (vmaxq_x_u16): Likewise.
3002 (vmaxq_x_u32): Likewise.
3003 (vabdq_x_s8): Likewise.
3004 (vabdq_x_s16): Likewise.
3005 (vabdq_x_s32): Likewise.
3006 (vabdq_x_u8): Likewise.
3007 (vabdq_x_u16): Likewise.
3008 (vabdq_x_u32): Likewise.
3009 (vabsq_x_s8): Likewise.
3010 (vabsq_x_s16): Likewise.
3011 (vabsq_x_s32): Likewise.
3012 (vaddq_x_s8): Likewise.
3013 (vaddq_x_s16): Likewise.
3014 (vaddq_x_s32): Likewise.
3015 (vaddq_x_n_s8): Likewise.
3016 (vaddq_x_n_s16): Likewise.
3017 (vaddq_x_n_s32): Likewise.
3018 (vaddq_x_u8): Likewise.
3019 (vaddq_x_u16): Likewise.
3020 (vaddq_x_u32): Likewise.
3021 (vaddq_x_n_u8): Likewise.
3022 (vaddq_x_n_u16): Likewise.
3023 (vaddq_x_n_u32): Likewise.
3024 (vclsq_x_s8): Likewise.
3025 (vclsq_x_s16): Likewise.
3026 (vclsq_x_s32): Likewise.
3027 (vclzq_x_s8): Likewise.
3028 (vclzq_x_s16): Likewise.
3029 (vclzq_x_s32): Likewise.
3030 (vclzq_x_u8): Likewise.
3031 (vclzq_x_u16): Likewise.
3032 (vclzq_x_u32): Likewise.
3033 (vnegq_x_s8): Likewise.
3034 (vnegq_x_s16): Likewise.
3035 (vnegq_x_s32): Likewise.
3036 (vmulhq_x_s8): Likewise.
3037 (vmulhq_x_s16): Likewise.
3038 (vmulhq_x_s32): Likewise.
3039 (vmulhq_x_u8): Likewise.
3040 (vmulhq_x_u16): Likewise.
3041 (vmulhq_x_u32): Likewise.
3042 (vmullbq_poly_x_p8): Likewise.
3043 (vmullbq_poly_x_p16): Likewise.
3044 (vmullbq_int_x_s8): Likewise.
3045 (vmullbq_int_x_s16): Likewise.
3046 (vmullbq_int_x_s32): Likewise.
3047 (vmullbq_int_x_u8): Likewise.
3048 (vmullbq_int_x_u16): Likewise.
3049 (vmullbq_int_x_u32): Likewise.
3050 (vmulltq_poly_x_p8): Likewise.
3051 (vmulltq_poly_x_p16): Likewise.
3052 (vmulltq_int_x_s8): Likewise.
3053 (vmulltq_int_x_s16): Likewise.
3054 (vmulltq_int_x_s32): Likewise.
3055 (vmulltq_int_x_u8): Likewise.
3056 (vmulltq_int_x_u16): Likewise.
3057 (vmulltq_int_x_u32): Likewise.
3058 (vmulq_x_s8): Likewise.
3059 (vmulq_x_s16): Likewise.
3060 (vmulq_x_s32): Likewise.
3061 (vmulq_x_n_s8): Likewise.
3062 (vmulq_x_n_s16): Likewise.
3063 (vmulq_x_n_s32): Likewise.
3064 (vmulq_x_u8): Likewise.
3065 (vmulq_x_u16): Likewise.
3066 (vmulq_x_u32): Likewise.
3067 (vmulq_x_n_u8): Likewise.
3068 (vmulq_x_n_u16): Likewise.
3069 (vmulq_x_n_u32): Likewise.
3070 (vsubq_x_s8): Likewise.
3071 (vsubq_x_s16): Likewise.
3072 (vsubq_x_s32): Likewise.
3073 (vsubq_x_n_s8): Likewise.
3074 (vsubq_x_n_s16): Likewise.
3075 (vsubq_x_n_s32): Likewise.
3076 (vsubq_x_u8): Likewise.
3077 (vsubq_x_u16): Likewise.
3078 (vsubq_x_u32): Likewise.
3079 (vsubq_x_n_u8): Likewise.
3080 (vsubq_x_n_u16): Likewise.
3081 (vsubq_x_n_u32): Likewise.
3082 (vcaddq_rot90_x_s8): Likewise.
3083 (vcaddq_rot90_x_s16): Likewise.
3084 (vcaddq_rot90_x_s32): Likewise.
3085 (vcaddq_rot90_x_u8): Likewise.
3086 (vcaddq_rot90_x_u16): Likewise.
3087 (vcaddq_rot90_x_u32): Likewise.
3088 (vcaddq_rot270_x_s8): Likewise.
3089 (vcaddq_rot270_x_s16): Likewise.
3090 (vcaddq_rot270_x_s32): Likewise.
3091 (vcaddq_rot270_x_u8): Likewise.
3092 (vcaddq_rot270_x_u16): Likewise.
3093 (vcaddq_rot270_x_u32): Likewise.
3094 (vhaddq_x_n_s8): Likewise.
3095 (vhaddq_x_n_s16): Likewise.
3096 (vhaddq_x_n_s32): Likewise.
3097 (vhaddq_x_n_u8): Likewise.
3098 (vhaddq_x_n_u16): Likewise.
3099 (vhaddq_x_n_u32): Likewise.
3100 (vhaddq_x_s8): Likewise.
3101 (vhaddq_x_s16): Likewise.
3102 (vhaddq_x_s32): Likewise.
3103 (vhaddq_x_u8): Likewise.
3104 (vhaddq_x_u16): Likewise.
3105 (vhaddq_x_u32): Likewise.
3106 (vhcaddq_rot90_x_s8): Likewise.
3107 (vhcaddq_rot90_x_s16): Likewise.
3108 (vhcaddq_rot90_x_s32): Likewise.
3109 (vhcaddq_rot270_x_s8): Likewise.
3110 (vhcaddq_rot270_x_s16): Likewise.
3111 (vhcaddq_rot270_x_s32): Likewise.
3112 (vhsubq_x_n_s8): Likewise.
3113 (vhsubq_x_n_s16): Likewise.
3114 (vhsubq_x_n_s32): Likewise.
3115 (vhsubq_x_n_u8): Likewise.
3116 (vhsubq_x_n_u16): Likewise.
3117 (vhsubq_x_n_u32): Likewise.
3118 (vhsubq_x_s8): Likewise.
3119 (vhsubq_x_s16): Likewise.
3120 (vhsubq_x_s32): Likewise.
3121 (vhsubq_x_u8): Likewise.
3122 (vhsubq_x_u16): Likewise.
3123 (vhsubq_x_u32): Likewise.
3124 (vrhaddq_x_s8): Likewise.
3125 (vrhaddq_x_s16): Likewise.
3126 (vrhaddq_x_s32): Likewise.
3127 (vrhaddq_x_u8): Likewise.
3128 (vrhaddq_x_u16): Likewise.
3129 (vrhaddq_x_u32): Likewise.
3130 (vrmulhq_x_s8): Likewise.
3131 (vrmulhq_x_s16): Likewise.
3132 (vrmulhq_x_s32): Likewise.
3133 (vrmulhq_x_u8): Likewise.
3134 (vrmulhq_x_u16): Likewise.
3135 (vrmulhq_x_u32): Likewise.
3136 (vandq_x_s8): Likewise.
3137 (vandq_x_s16): Likewise.
3138 (vandq_x_s32): Likewise.
3139 (vandq_x_u8): Likewise.
3140 (vandq_x_u16): Likewise.
3141 (vandq_x_u32): Likewise.
3142 (vbicq_x_s8): Likewise.
3143 (vbicq_x_s16): Likewise.
3144 (vbicq_x_s32): Likewise.
3145 (vbicq_x_u8): Likewise.
3146 (vbicq_x_u16): Likewise.
3147 (vbicq_x_u32): Likewise.
3148 (vbrsrq_x_n_s8): Likewise.
3149 (vbrsrq_x_n_s16): Likewise.
3150 (vbrsrq_x_n_s32): Likewise.
3151 (vbrsrq_x_n_u8): Likewise.
3152 (vbrsrq_x_n_u16): Likewise.
3153 (vbrsrq_x_n_u32): Likewise.
3154 (veorq_x_s8): Likewise.
3155 (veorq_x_s16): Likewise.
3156 (veorq_x_s32): Likewise.
3157 (veorq_x_u8): Likewise.
3158 (veorq_x_u16): Likewise.
3159 (veorq_x_u32): Likewise.
3160 (vmovlbq_x_s8): Likewise.
3161 (vmovlbq_x_s16): Likewise.
3162 (vmovlbq_x_u8): Likewise.
3163 (vmovlbq_x_u16): Likewise.
3164 (vmovltq_x_s8): Likewise.
3165 (vmovltq_x_s16): Likewise.
3166 (vmovltq_x_u8): Likewise.
3167 (vmovltq_x_u16): Likewise.
3168 (vmvnq_x_s8): Likewise.
3169 (vmvnq_x_s16): Likewise.
3170 (vmvnq_x_s32): Likewise.
3171 (vmvnq_x_u8): Likewise.
3172 (vmvnq_x_u16): Likewise.
3173 (vmvnq_x_u32): Likewise.
3174 (vmvnq_x_n_s16): Likewise.
3175 (vmvnq_x_n_s32): Likewise.
3176 (vmvnq_x_n_u16): Likewise.
3177 (vmvnq_x_n_u32): Likewise.
3178 (vornq_x_s8): Likewise.
3179 (vornq_x_s16): Likewise.
3180 (vornq_x_s32): Likewise.
3181 (vornq_x_u8): Likewise.
3182 (vornq_x_u16): Likewise.
3183 (vornq_x_u32): Likewise.
3184 (vorrq_x_s8): Likewise.
3185 (vorrq_x_s16): Likewise.
3186 (vorrq_x_s32): Likewise.
3187 (vorrq_x_u8): Likewise.
3188 (vorrq_x_u16): Likewise.
3189 (vorrq_x_u32): Likewise.
3190 (vrev16q_x_s8): Likewise.
3191 (vrev16q_x_u8): Likewise.
3192 (vrev32q_x_s8): Likewise.
3193 (vrev32q_x_s16): Likewise.
3194 (vrev32q_x_u8): Likewise.
3195 (vrev32q_x_u16): Likewise.
3196 (vrev64q_x_s8): Likewise.
3197 (vrev64q_x_s16): Likewise.
3198 (vrev64q_x_s32): Likewise.
3199 (vrev64q_x_u8): Likewise.
3200 (vrev64q_x_u16): Likewise.
3201 (vrev64q_x_u32): Likewise.
3202 (vrshlq_x_s8): Likewise.
3203 (vrshlq_x_s16): Likewise.
3204 (vrshlq_x_s32): Likewise.
3205 (vrshlq_x_u8): Likewise.
3206 (vrshlq_x_u16): Likewise.
3207 (vrshlq_x_u32): Likewise.
3208 (vshllbq_x_n_s8): Likewise.
3209 (vshllbq_x_n_s16): Likewise.
3210 (vshllbq_x_n_u8): Likewise.
3211 (vshllbq_x_n_u16): Likewise.
3212 (vshlltq_x_n_s8): Likewise.
3213 (vshlltq_x_n_s16): Likewise.
3214 (vshlltq_x_n_u8): Likewise.
3215 (vshlltq_x_n_u16): Likewise.
3216 (vshlq_x_s8): Likewise.
3217 (vshlq_x_s16): Likewise.
3218 (vshlq_x_s32): Likewise.
3219 (vshlq_x_u8): Likewise.
3220 (vshlq_x_u16): Likewise.
3221 (vshlq_x_u32): Likewise.
3222 (vshlq_x_n_s8): Likewise.
3223 (vshlq_x_n_s16): Likewise.
3224 (vshlq_x_n_s32): Likewise.
3225 (vshlq_x_n_u8): Likewise.
3226 (vshlq_x_n_u16): Likewise.
3227 (vshlq_x_n_u32): Likewise.
3228 (vrshrq_x_n_s8): Likewise.
3229 (vrshrq_x_n_s16): Likewise.
3230 (vrshrq_x_n_s32): Likewise.
3231 (vrshrq_x_n_u8): Likewise.
3232 (vrshrq_x_n_u16): Likewise.
3233 (vrshrq_x_n_u32): Likewise.
3234 (vshrq_x_n_s8): Likewise.
3235 (vshrq_x_n_s16): Likewise.
3236 (vshrq_x_n_s32): Likewise.
3237 (vshrq_x_n_u8): Likewise.
3238 (vshrq_x_n_u16): Likewise.
3239 (vshrq_x_n_u32): Likewise.
3240 (vdupq_x_n_f16): Likewise.
3241 (vdupq_x_n_f32): Likewise.
3242 (vminnmq_x_f16): Likewise.
3243 (vminnmq_x_f32): Likewise.
3244 (vmaxnmq_x_f16): Likewise.
3245 (vmaxnmq_x_f32): Likewise.
3246 (vabdq_x_f16): Likewise.
3247 (vabdq_x_f32): Likewise.
3248 (vabsq_x_f16): Likewise.
3249 (vabsq_x_f32): Likewise.
3250 (vaddq_x_f16): Likewise.
3251 (vaddq_x_f32): Likewise.
3252 (vaddq_x_n_f16): Likewise.
3253 (vaddq_x_n_f32): Likewise.
3254 (vnegq_x_f16): Likewise.
3255 (vnegq_x_f32): Likewise.
3256 (vmulq_x_f16): Likewise.
3257 (vmulq_x_f32): Likewise.
3258 (vmulq_x_n_f16): Likewise.
3259 (vmulq_x_n_f32): Likewise.
3260 (vsubq_x_f16): Likewise.
3261 (vsubq_x_f32): Likewise.
3262 (vsubq_x_n_f16): Likewise.
3263 (vsubq_x_n_f32): Likewise.
3264 (vcaddq_rot90_x_f16): Likewise.
3265 (vcaddq_rot90_x_f32): Likewise.
3266 (vcaddq_rot270_x_f16): Likewise.
3267 (vcaddq_rot270_x_f32): Likewise.
3268 (vcmulq_x_f16): Likewise.
3269 (vcmulq_x_f32): Likewise.
3270 (vcmulq_rot90_x_f16): Likewise.
3271 (vcmulq_rot90_x_f32): Likewise.
3272 (vcmulq_rot180_x_f16): Likewise.
3273 (vcmulq_rot180_x_f32): Likewise.
3274 (vcmulq_rot270_x_f16): Likewise.
3275 (vcmulq_rot270_x_f32): Likewise.
3276 (vcvtaq_x_s16_f16): Likewise.
3277 (vcvtaq_x_s32_f32): Likewise.
3278 (vcvtaq_x_u16_f16): Likewise.
3279 (vcvtaq_x_u32_f32): Likewise.
3280 (vcvtnq_x_s16_f16): Likewise.
3281 (vcvtnq_x_s32_f32): Likewise.
3282 (vcvtnq_x_u16_f16): Likewise.
3283 (vcvtnq_x_u32_f32): Likewise.
3284 (vcvtpq_x_s16_f16): Likewise.
3285 (vcvtpq_x_s32_f32): Likewise.
3286 (vcvtpq_x_u16_f16): Likewise.
3287 (vcvtpq_x_u32_f32): Likewise.
3288 (vcvtmq_x_s16_f16): Likewise.
3289 (vcvtmq_x_s32_f32): Likewise.
3290 (vcvtmq_x_u16_f16): Likewise.
3291 (vcvtmq_x_u32_f32): Likewise.
3292 (vcvtbq_x_f32_f16): Likewise.
3293 (vcvttq_x_f32_f16): Likewise.
3294 (vcvtq_x_f16_u16): Likewise.
3295 (vcvtq_x_f16_s16): Likewise.
3296 (vcvtq_x_f32_s32): Likewise.
3297 (vcvtq_x_f32_u32): Likewise.
3298 (vcvtq_x_n_f16_s16): Likewise.
3299 (vcvtq_x_n_f16_u16): Likewise.
3300 (vcvtq_x_n_f32_s32): Likewise.
3301 (vcvtq_x_n_f32_u32): Likewise.
3302 (vcvtq_x_s16_f16): Likewise.
3303 (vcvtq_x_s32_f32): Likewise.
3304 (vcvtq_x_u16_f16): Likewise.
3305 (vcvtq_x_u32_f32): Likewise.
3306 (vcvtq_x_n_s16_f16): Likewise.
3307 (vcvtq_x_n_s32_f32): Likewise.
3308 (vcvtq_x_n_u16_f16): Likewise.
3309 (vcvtq_x_n_u32_f32): Likewise.
3310 (vrndq_x_f16): Likewise.
3311 (vrndq_x_f32): Likewise.
3312 (vrndnq_x_f16): Likewise.
3313 (vrndnq_x_f32): Likewise.
3314 (vrndmq_x_f16): Likewise.
3315 (vrndmq_x_f32): Likewise.
3316 (vrndpq_x_f16): Likewise.
3317 (vrndpq_x_f32): Likewise.
3318 (vrndaq_x_f16): Likewise.
3319 (vrndaq_x_f32): Likewise.
3320 (vrndxq_x_f16): Likewise.
3321 (vrndxq_x_f32): Likewise.
3322 (vandq_x_f16): Likewise.
3323 (vandq_x_f32): Likewise.
3324 (vbicq_x_f16): Likewise.
3325 (vbicq_x_f32): Likewise.
3326 (vbrsrq_x_n_f16): Likewise.
3327 (vbrsrq_x_n_f32): Likewise.
3328 (veorq_x_f16): Likewise.
3329 (veorq_x_f32): Likewise.
3330 (vornq_x_f16): Likewise.
3331 (vornq_x_f32): Likewise.
3332 (vorrq_x_f16): Likewise.
3333 (vorrq_x_f32): Likewise.
3334 (vrev32q_x_f16): Likewise.
3335 (vrev64q_x_f16): Likewise.
3336 (vrev64q_x_f32): Likewise.
3337 (__arm_vddupq_x_n_u8): Define intrinsic.
3338 (__arm_vddupq_x_n_u16): Likewise.
3339 (__arm_vddupq_x_n_u32): Likewise.
3340 (__arm_vddupq_x_wb_u8): Likewise.
3341 (__arm_vddupq_x_wb_u16): Likewise.
3342 (__arm_vddupq_x_wb_u32): Likewise.
3343 (__arm_vdwdupq_x_n_u8): Likewise.
3344 (__arm_vdwdupq_x_n_u16): Likewise.
3345 (__arm_vdwdupq_x_n_u32): Likewise.
3346 (__arm_vdwdupq_x_wb_u8): Likewise.
3347 (__arm_vdwdupq_x_wb_u16): Likewise.
3348 (__arm_vdwdupq_x_wb_u32): Likewise.
3349 (__arm_vidupq_x_n_u8): Likewise.
3350 (__arm_vidupq_x_n_u16): Likewise.
3351 (__arm_vidupq_x_n_u32): Likewise.
3352 (__arm_vidupq_x_wb_u8): Likewise.
3353 (__arm_vidupq_x_wb_u16): Likewise.
3354 (__arm_vidupq_x_wb_u32): Likewise.
3355 (__arm_viwdupq_x_n_u8): Likewise.
3356 (__arm_viwdupq_x_n_u16): Likewise.
3357 (__arm_viwdupq_x_n_u32): Likewise.
3358 (__arm_viwdupq_x_wb_u8): Likewise.
3359 (__arm_viwdupq_x_wb_u16): Likewise.
3360 (__arm_viwdupq_x_wb_u32): Likewise.
3361 (__arm_vdupq_x_n_s8): Likewise.
3362 (__arm_vdupq_x_n_s16): Likewise.
3363 (__arm_vdupq_x_n_s32): Likewise.
3364 (__arm_vdupq_x_n_u8): Likewise.
3365 (__arm_vdupq_x_n_u16): Likewise.
3366 (__arm_vdupq_x_n_u32): Likewise.
3367 (__arm_vminq_x_s8): Likewise.
3368 (__arm_vminq_x_s16): Likewise.
3369 (__arm_vminq_x_s32): Likewise.
3370 (__arm_vminq_x_u8): Likewise.
3371 (__arm_vminq_x_u16): Likewise.
3372 (__arm_vminq_x_u32): Likewise.
3373 (__arm_vmaxq_x_s8): Likewise.
3374 (__arm_vmaxq_x_s16): Likewise.
3375 (__arm_vmaxq_x_s32): Likewise.
3376 (__arm_vmaxq_x_u8): Likewise.
3377 (__arm_vmaxq_x_u16): Likewise.
3378 (__arm_vmaxq_x_u32): Likewise.
3379 (__arm_vabdq_x_s8): Likewise.
3380 (__arm_vabdq_x_s16): Likewise.
3381 (__arm_vabdq_x_s32): Likewise.
3382 (__arm_vabdq_x_u8): Likewise.
3383 (__arm_vabdq_x_u16): Likewise.
3384 (__arm_vabdq_x_u32): Likewise.
3385 (__arm_vabsq_x_s8): Likewise.
3386 (__arm_vabsq_x_s16): Likewise.
3387 (__arm_vabsq_x_s32): Likewise.
3388 (__arm_vaddq_x_s8): Likewise.
3389 (__arm_vaddq_x_s16): Likewise.
3390 (__arm_vaddq_x_s32): Likewise.
3391 (__arm_vaddq_x_n_s8): Likewise.
3392 (__arm_vaddq_x_n_s16): Likewise.
3393 (__arm_vaddq_x_n_s32): Likewise.
3394 (__arm_vaddq_x_u8): Likewise.
3395 (__arm_vaddq_x_u16): Likewise.
3396 (__arm_vaddq_x_u32): Likewise.
3397 (__arm_vaddq_x_n_u8): Likewise.
3398 (__arm_vaddq_x_n_u16): Likewise.
3399 (__arm_vaddq_x_n_u32): Likewise.
3400 (__arm_vclsq_x_s8): Likewise.
3401 (__arm_vclsq_x_s16): Likewise.
3402 (__arm_vclsq_x_s32): Likewise.
3403 (__arm_vclzq_x_s8): Likewise.
3404 (__arm_vclzq_x_s16): Likewise.
3405 (__arm_vclzq_x_s32): Likewise.
3406 (__arm_vclzq_x_u8): Likewise.
3407 (__arm_vclzq_x_u16): Likewise.
3408 (__arm_vclzq_x_u32): Likewise.
3409 (__arm_vnegq_x_s8): Likewise.
3410 (__arm_vnegq_x_s16): Likewise.
3411 (__arm_vnegq_x_s32): Likewise.
3412 (__arm_vmulhq_x_s8): Likewise.
3413 (__arm_vmulhq_x_s16): Likewise.
3414 (__arm_vmulhq_x_s32): Likewise.
3415 (__arm_vmulhq_x_u8): Likewise.
3416 (__arm_vmulhq_x_u16): Likewise.
3417 (__arm_vmulhq_x_u32): Likewise.
3418 (__arm_vmullbq_poly_x_p8): Likewise.
3419 (__arm_vmullbq_poly_x_p16): Likewise.
3420 (__arm_vmullbq_int_x_s8): Likewise.
3421 (__arm_vmullbq_int_x_s16): Likewise.
3422 (__arm_vmullbq_int_x_s32): Likewise.
3423 (__arm_vmullbq_int_x_u8): Likewise.
3424 (__arm_vmullbq_int_x_u16): Likewise.
3425 (__arm_vmullbq_int_x_u32): Likewise.
3426 (__arm_vmulltq_poly_x_p8): Likewise.
3427 (__arm_vmulltq_poly_x_p16): Likewise.
3428 (__arm_vmulltq_int_x_s8): Likewise.
3429 (__arm_vmulltq_int_x_s16): Likewise.
3430 (__arm_vmulltq_int_x_s32): Likewise.
3431 (__arm_vmulltq_int_x_u8): Likewise.
3432 (__arm_vmulltq_int_x_u16): Likewise.
3433 (__arm_vmulltq_int_x_u32): Likewise.
3434 (__arm_vmulq_x_s8): Likewise.
3435 (__arm_vmulq_x_s16): Likewise.
3436 (__arm_vmulq_x_s32): Likewise.
3437 (__arm_vmulq_x_n_s8): Likewise.
3438 (__arm_vmulq_x_n_s16): Likewise.
3439 (__arm_vmulq_x_n_s32): Likewise.
3440 (__arm_vmulq_x_u8): Likewise.
3441 (__arm_vmulq_x_u16): Likewise.
3442 (__arm_vmulq_x_u32): Likewise.
3443 (__arm_vmulq_x_n_u8): Likewise.
3444 (__arm_vmulq_x_n_u16): Likewise.
3445 (__arm_vmulq_x_n_u32): Likewise.
3446 (__arm_vsubq_x_s8): Likewise.
3447 (__arm_vsubq_x_s16): Likewise.
3448 (__arm_vsubq_x_s32): Likewise.
3449 (__arm_vsubq_x_n_s8): Likewise.
3450 (__arm_vsubq_x_n_s16): Likewise.
3451 (__arm_vsubq_x_n_s32): Likewise.
3452 (__arm_vsubq_x_u8): Likewise.
3453 (__arm_vsubq_x_u16): Likewise.
3454 (__arm_vsubq_x_u32): Likewise.
3455 (__arm_vsubq_x_n_u8): Likewise.
3456 (__arm_vsubq_x_n_u16): Likewise.
3457 (__arm_vsubq_x_n_u32): Likewise.
3458 (__arm_vcaddq_rot90_x_s8): Likewise.
3459 (__arm_vcaddq_rot90_x_s16): Likewise.
3460 (__arm_vcaddq_rot90_x_s32): Likewise.
3461 (__arm_vcaddq_rot90_x_u8): Likewise.
3462 (__arm_vcaddq_rot90_x_u16): Likewise.
3463 (__arm_vcaddq_rot90_x_u32): Likewise.
3464 (__arm_vcaddq_rot270_x_s8): Likewise.
3465 (__arm_vcaddq_rot270_x_s16): Likewise.
3466 (__arm_vcaddq_rot270_x_s32): Likewise.
3467 (__arm_vcaddq_rot270_x_u8): Likewise.
3468 (__arm_vcaddq_rot270_x_u16): Likewise.
3469 (__arm_vcaddq_rot270_x_u32): Likewise.
3470 (__arm_vhaddq_x_n_s8): Likewise.
3471 (__arm_vhaddq_x_n_s16): Likewise.
3472 (__arm_vhaddq_x_n_s32): Likewise.
3473 (__arm_vhaddq_x_n_u8): Likewise.
3474 (__arm_vhaddq_x_n_u16): Likewise.
3475 (__arm_vhaddq_x_n_u32): Likewise.
3476 (__arm_vhaddq_x_s8): Likewise.
3477 (__arm_vhaddq_x_s16): Likewise.
3478 (__arm_vhaddq_x_s32): Likewise.
3479 (__arm_vhaddq_x_u8): Likewise.
3480 (__arm_vhaddq_x_u16): Likewise.
3481 (__arm_vhaddq_x_u32): Likewise.
3482 (__arm_vhcaddq_rot90_x_s8): Likewise.
3483 (__arm_vhcaddq_rot90_x_s16): Likewise.
3484 (__arm_vhcaddq_rot90_x_s32): Likewise.
3485 (__arm_vhcaddq_rot270_x_s8): Likewise.
3486 (__arm_vhcaddq_rot270_x_s16): Likewise.
3487 (__arm_vhcaddq_rot270_x_s32): Likewise.
3488 (__arm_vhsubq_x_n_s8): Likewise.
3489 (__arm_vhsubq_x_n_s16): Likewise.
3490 (__arm_vhsubq_x_n_s32): Likewise.
3491 (__arm_vhsubq_x_n_u8): Likewise.
3492 (__arm_vhsubq_x_n_u16): Likewise.
3493 (__arm_vhsubq_x_n_u32): Likewise.
3494 (__arm_vhsubq_x_s8): Likewise.
3495 (__arm_vhsubq_x_s16): Likewise.
3496 (__arm_vhsubq_x_s32): Likewise.
3497 (__arm_vhsubq_x_u8): Likewise.
3498 (__arm_vhsubq_x_u16): Likewise.
3499 (__arm_vhsubq_x_u32): Likewise.
3500 (__arm_vrhaddq_x_s8): Likewise.
3501 (__arm_vrhaddq_x_s16): Likewise.
3502 (__arm_vrhaddq_x_s32): Likewise.
3503 (__arm_vrhaddq_x_u8): Likewise.
3504 (__arm_vrhaddq_x_u16): Likewise.
3505 (__arm_vrhaddq_x_u32): Likewise.
3506 (__arm_vrmulhq_x_s8): Likewise.
3507 (__arm_vrmulhq_x_s16): Likewise.
3508 (__arm_vrmulhq_x_s32): Likewise.
3509 (__arm_vrmulhq_x_u8): Likewise.
3510 (__arm_vrmulhq_x_u16): Likewise.
3511 (__arm_vrmulhq_x_u32): Likewise.
3512 (__arm_vandq_x_s8): Likewise.
3513 (__arm_vandq_x_s16): Likewise.
3514 (__arm_vandq_x_s32): Likewise.
3515 (__arm_vandq_x_u8): Likewise.
3516 (__arm_vandq_x_u16): Likewise.
3517 (__arm_vandq_x_u32): Likewise.
3518 (__arm_vbicq_x_s8): Likewise.
3519 (__arm_vbicq_x_s16): Likewise.
3520 (__arm_vbicq_x_s32): Likewise.
3521 (__arm_vbicq_x_u8): Likewise.
3522 (__arm_vbicq_x_u16): Likewise.
3523 (__arm_vbicq_x_u32): Likewise.
3524 (__arm_vbrsrq_x_n_s8): Likewise.
3525 (__arm_vbrsrq_x_n_s16): Likewise.
3526 (__arm_vbrsrq_x_n_s32): Likewise.
3527 (__arm_vbrsrq_x_n_u8): Likewise.
3528 (__arm_vbrsrq_x_n_u16): Likewise.
3529 (__arm_vbrsrq_x_n_u32): Likewise.
3530 (__arm_veorq_x_s8): Likewise.
3531 (__arm_veorq_x_s16): Likewise.
3532 (__arm_veorq_x_s32): Likewise.
3533 (__arm_veorq_x_u8): Likewise.
3534 (__arm_veorq_x_u16): Likewise.
3535 (__arm_veorq_x_u32): Likewise.
3536 (__arm_vmovlbq_x_s8): Likewise.
3537 (__arm_vmovlbq_x_s16): Likewise.
3538 (__arm_vmovlbq_x_u8): Likewise.
3539 (__arm_vmovlbq_x_u16): Likewise.
3540 (__arm_vmovltq_x_s8): Likewise.
3541 (__arm_vmovltq_x_s16): Likewise.
3542 (__arm_vmovltq_x_u8): Likewise.
3543 (__arm_vmovltq_x_u16): Likewise.
3544 (__arm_vmvnq_x_s8): Likewise.
3545 (__arm_vmvnq_x_s16): Likewise.
3546 (__arm_vmvnq_x_s32): Likewise.
3547 (__arm_vmvnq_x_u8): Likewise.
3548 (__arm_vmvnq_x_u16): Likewise.
3549 (__arm_vmvnq_x_u32): Likewise.
3550 (__arm_vmvnq_x_n_s16): Likewise.
3551 (__arm_vmvnq_x_n_s32): Likewise.
3552 (__arm_vmvnq_x_n_u16): Likewise.
3553 (__arm_vmvnq_x_n_u32): Likewise.
3554 (__arm_vornq_x_s8): Likewise.
3555 (__arm_vornq_x_s16): Likewise.
3556 (__arm_vornq_x_s32): Likewise.
3557 (__arm_vornq_x_u8): Likewise.
3558 (__arm_vornq_x_u16): Likewise.
3559 (__arm_vornq_x_u32): Likewise.
3560 (__arm_vorrq_x_s8): Likewise.
3561 (__arm_vorrq_x_s16): Likewise.
3562 (__arm_vorrq_x_s32): Likewise.
3563 (__arm_vorrq_x_u8): Likewise.
3564 (__arm_vorrq_x_u16): Likewise.
3565 (__arm_vorrq_x_u32): Likewise.
3566 (__arm_vrev16q_x_s8): Likewise.
3567 (__arm_vrev16q_x_u8): Likewise.
3568 (__arm_vrev32q_x_s8): Likewise.
3569 (__arm_vrev32q_x_s16): Likewise.
3570 (__arm_vrev32q_x_u8): Likewise.
3571 (__arm_vrev32q_x_u16): Likewise.
3572 (__arm_vrev64q_x_s8): Likewise.
3573 (__arm_vrev64q_x_s16): Likewise.
3574 (__arm_vrev64q_x_s32): Likewise.
3575 (__arm_vrev64q_x_u8): Likewise.
3576 (__arm_vrev64q_x_u16): Likewise.
3577 (__arm_vrev64q_x_u32): Likewise.
3578 (__arm_vrshlq_x_s8): Likewise.
3579 (__arm_vrshlq_x_s16): Likewise.
3580 (__arm_vrshlq_x_s32): Likewise.
3581 (__arm_vrshlq_x_u8): Likewise.
3582 (__arm_vrshlq_x_u16): Likewise.
3583 (__arm_vrshlq_x_u32): Likewise.
3584 (__arm_vshllbq_x_n_s8): Likewise.
3585 (__arm_vshllbq_x_n_s16): Likewise.
3586 (__arm_vshllbq_x_n_u8): Likewise.
3587 (__arm_vshllbq_x_n_u16): Likewise.
3588 (__arm_vshlltq_x_n_s8): Likewise.
3589 (__arm_vshlltq_x_n_s16): Likewise.
3590 (__arm_vshlltq_x_n_u8): Likewise.
3591 (__arm_vshlltq_x_n_u16): Likewise.
3592 (__arm_vshlq_x_s8): Likewise.
3593 (__arm_vshlq_x_s16): Likewise.
3594 (__arm_vshlq_x_s32): Likewise.
3595 (__arm_vshlq_x_u8): Likewise.
3596 (__arm_vshlq_x_u16): Likewise.
3597 (__arm_vshlq_x_u32): Likewise.
3598 (__arm_vshlq_x_n_s8): Likewise.
3599 (__arm_vshlq_x_n_s16): Likewise.
3600 (__arm_vshlq_x_n_s32): Likewise.
3601 (__arm_vshlq_x_n_u8): Likewise.
3602 (__arm_vshlq_x_n_u16): Likewise.
3603 (__arm_vshlq_x_n_u32): Likewise.
3604 (__arm_vrshrq_x_n_s8): Likewise.
3605 (__arm_vrshrq_x_n_s16): Likewise.
3606 (__arm_vrshrq_x_n_s32): Likewise.
3607 (__arm_vrshrq_x_n_u8): Likewise.
3608 (__arm_vrshrq_x_n_u16): Likewise.
3609 (__arm_vrshrq_x_n_u32): Likewise.
3610 (__arm_vshrq_x_n_s8): Likewise.
3611 (__arm_vshrq_x_n_s16): Likewise.
3612 (__arm_vshrq_x_n_s32): Likewise.
3613 (__arm_vshrq_x_n_u8): Likewise.
3614 (__arm_vshrq_x_n_u16): Likewise.
3615 (__arm_vshrq_x_n_u32): Likewise.
3616 (__arm_vdupq_x_n_f16): Likewise.
3617 (__arm_vdupq_x_n_f32): Likewise.
3618 (__arm_vminnmq_x_f16): Likewise.
3619 (__arm_vminnmq_x_f32): Likewise.
3620 (__arm_vmaxnmq_x_f16): Likewise.
3621 (__arm_vmaxnmq_x_f32): Likewise.
3622 (__arm_vabdq_x_f16): Likewise.
3623 (__arm_vabdq_x_f32): Likewise.
3624 (__arm_vabsq_x_f16): Likewise.
3625 (__arm_vabsq_x_f32): Likewise.
3626 (__arm_vaddq_x_f16): Likewise.
3627 (__arm_vaddq_x_f32): Likewise.
3628 (__arm_vaddq_x_n_f16): Likewise.
3629 (__arm_vaddq_x_n_f32): Likewise.
3630 (__arm_vnegq_x_f16): Likewise.
3631 (__arm_vnegq_x_f32): Likewise.
3632 (__arm_vmulq_x_f16): Likewise.
3633 (__arm_vmulq_x_f32): Likewise.
3634 (__arm_vmulq_x_n_f16): Likewise.
3635 (__arm_vmulq_x_n_f32): Likewise.
3636 (__arm_vsubq_x_f16): Likewise.
3637 (__arm_vsubq_x_f32): Likewise.
3638 (__arm_vsubq_x_n_f16): Likewise.
3639 (__arm_vsubq_x_n_f32): Likewise.
3640 (__arm_vcaddq_rot90_x_f16): Likewise.
3641 (__arm_vcaddq_rot90_x_f32): Likewise.
3642 (__arm_vcaddq_rot270_x_f16): Likewise.
3643 (__arm_vcaddq_rot270_x_f32): Likewise.
3644 (__arm_vcmulq_x_f16): Likewise.
3645 (__arm_vcmulq_x_f32): Likewise.
3646 (__arm_vcmulq_rot90_x_f16): Likewise.
3647 (__arm_vcmulq_rot90_x_f32): Likewise.
3648 (__arm_vcmulq_rot180_x_f16): Likewise.
3649 (__arm_vcmulq_rot180_x_f32): Likewise.
3650 (__arm_vcmulq_rot270_x_f16): Likewise.
3651 (__arm_vcmulq_rot270_x_f32): Likewise.
3652 (__arm_vcvtaq_x_s16_f16): Likewise.
3653 (__arm_vcvtaq_x_s32_f32): Likewise.
3654 (__arm_vcvtaq_x_u16_f16): Likewise.
3655 (__arm_vcvtaq_x_u32_f32): Likewise.
3656 (__arm_vcvtnq_x_s16_f16): Likewise.
3657 (__arm_vcvtnq_x_s32_f32): Likewise.
3658 (__arm_vcvtnq_x_u16_f16): Likewise.
3659 (__arm_vcvtnq_x_u32_f32): Likewise.
3660 (__arm_vcvtpq_x_s16_f16): Likewise.
3661 (__arm_vcvtpq_x_s32_f32): Likewise.
3662 (__arm_vcvtpq_x_u16_f16): Likewise.
3663 (__arm_vcvtpq_x_u32_f32): Likewise.
3664 (__arm_vcvtmq_x_s16_f16): Likewise.
3665 (__arm_vcvtmq_x_s32_f32): Likewise.
3666 (__arm_vcvtmq_x_u16_f16): Likewise.
3667 (__arm_vcvtmq_x_u32_f32): Likewise.
3668 (__arm_vcvtbq_x_f32_f16): Likewise.
3669 (__arm_vcvttq_x_f32_f16): Likewise.
3670 (__arm_vcvtq_x_f16_u16): Likewise.
3671 (__arm_vcvtq_x_f16_s16): Likewise.
3672 (__arm_vcvtq_x_f32_s32): Likewise.
3673 (__arm_vcvtq_x_f32_u32): Likewise.
3674 (__arm_vcvtq_x_n_f16_s16): Likewise.
3675 (__arm_vcvtq_x_n_f16_u16): Likewise.
3676 (__arm_vcvtq_x_n_f32_s32): Likewise.
3677 (__arm_vcvtq_x_n_f32_u32): Likewise.
3678 (__arm_vcvtq_x_s16_f16): Likewise.
3679 (__arm_vcvtq_x_s32_f32): Likewise.
3680 (__arm_vcvtq_x_u16_f16): Likewise.
3681 (__arm_vcvtq_x_u32_f32): Likewise.
3682 (__arm_vcvtq_x_n_s16_f16): Likewise.
3683 (__arm_vcvtq_x_n_s32_f32): Likewise.
3684 (__arm_vcvtq_x_n_u16_f16): Likewise.
3685 (__arm_vcvtq_x_n_u32_f32): Likewise.
3686 (__arm_vrndq_x_f16): Likewise.
3687 (__arm_vrndq_x_f32): Likewise.
3688 (__arm_vrndnq_x_f16): Likewise.
3689 (__arm_vrndnq_x_f32): Likewise.
3690 (__arm_vrndmq_x_f16): Likewise.
3691 (__arm_vrndmq_x_f32): Likewise.
3692 (__arm_vrndpq_x_f16): Likewise.
3693 (__arm_vrndpq_x_f32): Likewise.
3694 (__arm_vrndaq_x_f16): Likewise.
3695 (__arm_vrndaq_x_f32): Likewise.
3696 (__arm_vrndxq_x_f16): Likewise.
3697 (__arm_vrndxq_x_f32): Likewise.
3698 (__arm_vandq_x_f16): Likewise.
3699 (__arm_vandq_x_f32): Likewise.
3700 (__arm_vbicq_x_f16): Likewise.
3701 (__arm_vbicq_x_f32): Likewise.
3702 (__arm_vbrsrq_x_n_f16): Likewise.
3703 (__arm_vbrsrq_x_n_f32): Likewise.
3704 (__arm_veorq_x_f16): Likewise.
3705 (__arm_veorq_x_f32): Likewise.
3706 (__arm_vornq_x_f16): Likewise.
3707 (__arm_vornq_x_f32): Likewise.
3708 (__arm_vorrq_x_f16): Likewise.
3709 (__arm_vorrq_x_f32): Likewise.
3710 (__arm_vrev32q_x_f16): Likewise.
3711 (__arm_vrev64q_x_f16): Likewise.
3712 (__arm_vrev64q_x_f32): Likewise.
3713 (vabdq_x): Define polymorphic variant.
3714 (vabsq_x): Likewise.
3715 (vaddq_x): Likewise.
3716 (vandq_x): Likewise.
3717 (vbicq_x): Likewise.
3718 (vbrsrq_x): Likewise.
3719 (vcaddq_rot270_x): Likewise.
3720 (vcaddq_rot90_x): Likewise.
3721 (vcmulq_rot180_x): Likewise.
3722 (vcmulq_rot270_x): Likewise.
3723 (vcmulq_x): Likewise.
3724 (vcvtq_x): Likewise.
3725 (vcvtq_x_n): Likewise.
3726 (vcvtnq_m): Likewise.
3727 (veorq_x): Likewise.
3728 (vmaxnmq_x): Likewise.
3729 (vminnmq_x): Likewise.
3730 (vmulq_x): Likewise.
3731 (vnegq_x): Likewise.
3732 (vornq_x): Likewise.
3733 (vorrq_x): Likewise.
3734 (vrev32q_x): Likewise.
3735 (vrev64q_x): Likewise.
3736 (vrndaq_x): Likewise.
3737 (vrndmq_x): Likewise.
3738 (vrndnq_x): Likewise.
3739 (vrndpq_x): Likewise.
3740 (vrndq_x): Likewise.
3741 (vrndxq_x): Likewise.
3742 (vsubq_x): Likewise.
3743 (vcmulq_rot90_x): Likewise.
3745 (vclsq_x): Likewise.
3746 (vclzq_x): Likewise.
3747 (vhaddq_x): Likewise.
3748 (vhcaddq_rot270_x): Likewise.
3749 (vhcaddq_rot90_x): Likewise.
3750 (vhsubq_x): Likewise.
3751 (vmaxq_x): Likewise.
3752 (vminq_x): Likewise.
3753 (vmovlbq_x): Likewise.
3754 (vmovltq_x): Likewise.
3755 (vmulhq_x): Likewise.
3756 (vmullbq_int_x): Likewise.
3757 (vmullbq_poly_x): Likewise.
3758 (vmulltq_int_x): Likewise.
3759 (vmulltq_poly_x): Likewise.
3760 (vmvnq_x): Likewise.
3761 (vrev16q_x): Likewise.
3762 (vrhaddq_x): Likewise.
3763 (vrmulhq_x): Likewise.
3764 (vrshlq_x): Likewise.
3765 (vrshrq_x): Likewise.
3766 (vshllbq_x): Likewise.
3767 (vshlltq_x): Likewise.
3768 (vshlq_x_n): Likewise.
3769 (vshlq_x): Likewise.
3770 (vdwdupq_x_u8): Likewise.
3771 (vdwdupq_x_u16): Likewise.
3772 (vdwdupq_x_u32): Likewise.
3773 (viwdupq_x_u8): Likewise.
3774 (viwdupq_x_u16): Likewise.
3775 (viwdupq_x_u32): Likewise.
3776 (vidupq_x_u8): Likewise.
3777 (vddupq_x_u8): Likewise.
3778 (vidupq_x_u16): Likewise.
3779 (vddupq_x_u16): Likewise.
3780 (vidupq_x_u32): Likewise.
3781 (vddupq_x_u32): Likewise.
3782 (vshrq_x): Likewise.
3784 2020-03-20 Richard Biener <rguenther@suse.de>
3786 * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts
3787 to vectorize for CTOR defs.
3789 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3790 Andre Vieira <andre.simoesdiasvieira@arm.com>
3791 Mihail Ionescu <mihail.ionescu@arm.com>
3793 * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin
3795 (LDRGBWBU_QUALIFIERS): Likewise.
3796 (LDRGBWBS_Z_QUALIFIERS): Likewise.
3797 (LDRGBWBU_Z_QUALIFIERS): Likewise.
3798 (STRSBWBS_QUALIFIERS): Likewise.
3799 (STRSBWBU_QUALIFIERS): Likewise.
3800 (STRSBWBS_P_QUALIFIERS): Likewise.
3801 (STRSBWBU_P_QUALIFIERS): Likewise.
3802 * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro.
3803 (vldrdq_gather_base_wb_u64): Likewise.
3804 (vldrdq_gather_base_wb_z_s64): Likewise.
3805 (vldrdq_gather_base_wb_z_u64): Likewise.
3806 (vldrwq_gather_base_wb_f32): Likewise.
3807 (vldrwq_gather_base_wb_s32): Likewise.
3808 (vldrwq_gather_base_wb_u32): Likewise.
3809 (vldrwq_gather_base_wb_z_f32): Likewise.
3810 (vldrwq_gather_base_wb_z_s32): Likewise.
3811 (vldrwq_gather_base_wb_z_u32): Likewise.
3812 (vstrdq_scatter_base_wb_p_s64): Likewise.
3813 (vstrdq_scatter_base_wb_p_u64): Likewise.
3814 (vstrdq_scatter_base_wb_s64): Likewise.
3815 (vstrdq_scatter_base_wb_u64): Likewise.
3816 (vstrwq_scatter_base_wb_p_s32): Likewise.
3817 (vstrwq_scatter_base_wb_p_f32): Likewise.
3818 (vstrwq_scatter_base_wb_p_u32): Likewise.
3819 (vstrwq_scatter_base_wb_s32): Likewise.
3820 (vstrwq_scatter_base_wb_u32): Likewise.
3821 (vstrwq_scatter_base_wb_f32): Likewise.
3822 (__arm_vldrdq_gather_base_wb_s64): Define intrinsic.
3823 (__arm_vldrdq_gather_base_wb_u64): Likewise.
3824 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
3825 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
3826 (__arm_vldrwq_gather_base_wb_s32): Likewise.
3827 (__arm_vldrwq_gather_base_wb_u32): Likewise.
3828 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
3829 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
3830 (__arm_vstrdq_scatter_base_wb_s64): Likewise.
3831 (__arm_vstrdq_scatter_base_wb_u64): Likewise.
3832 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
3833 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
3834 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
3835 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
3836 (__arm_vstrwq_scatter_base_wb_s32): Likewise.
3837 (__arm_vstrwq_scatter_base_wb_u32): Likewise.
3838 (__arm_vldrwq_gather_base_wb_f32): Likewise.
3839 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
3840 (__arm_vstrwq_scatter_base_wb_f32): Likewise.
3841 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
3842 (vstrwq_scatter_base_wb): Define polymorphic variant.
3843 (vstrwq_scatter_base_wb_p): Likewise.
3844 (vstrdq_scatter_base_wb_p): Likewise.
3845 (vstrdq_scatter_base_wb): Likewise.
3846 * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin
3848 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Define RTL
3850 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise.
3851 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Likewise.
3852 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
3853 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise.
3854 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Likewise.
3855 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
3856 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
3857 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise.
3858 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
3859 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
3860 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise.
3861 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
3862 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise.
3863 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Likewise.
3864 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
3865 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise.
3866 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Likewise.
3867 (mve_vldrwq_gather_base_wb_<supf>v4si): Likewise.
3868 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
3869 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Likewise.
3870 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
3871 (mve_vldrwq_gather_base_wb_fv4sf): Likewise.
3872 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
3873 (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise.
3874 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
3875 (mve_vldrdq_gather_base_wb_<supf>v2di): Likewise.
3876 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
3877 (mve_vldrdq_gather_base_wb_z_<supf>v2di): Likewise.
3878 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
3880 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3881 Andre Vieira <andre.simoesdiasvieira@arm.com>
3882 Mihail Ionescu <mihail.ionescu@arm.com>
3884 * config/arm/arm-builtins.c
3885 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary
3887 * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro.
3888 (vddupq_m_n_u32): Likewise.
3889 (vddupq_m_n_u16): Likewise.
3890 (vddupq_m_wb_u8): Likewise.
3891 (vddupq_m_wb_u16): Likewise.
3892 (vddupq_m_wb_u32): Likewise.
3893 (vddupq_n_u8): Likewise.
3894 (vddupq_n_u32): Likewise.
3895 (vddupq_n_u16): Likewise.
3896 (vddupq_wb_u8): Likewise.
3897 (vddupq_wb_u16): Likewise.
3898 (vddupq_wb_u32): Likewise.
3899 (vdwdupq_m_n_u8): Likewise.
3900 (vdwdupq_m_n_u32): Likewise.
3901 (vdwdupq_m_n_u16): Likewise.
3902 (vdwdupq_m_wb_u8): Likewise.
3903 (vdwdupq_m_wb_u32): Likewise.
3904 (vdwdupq_m_wb_u16): Likewise.
3905 (vdwdupq_n_u8): Likewise.
3906 (vdwdupq_n_u32): Likewise.
3907 (vdwdupq_n_u16): Likewise.
3908 (vdwdupq_wb_u8): Likewise.
3909 (vdwdupq_wb_u32): Likewise.
3910 (vdwdupq_wb_u16): Likewise.
3911 (vidupq_m_n_u8): Likewise.
3912 (vidupq_m_n_u32): Likewise.
3913 (vidupq_m_n_u16): Likewise.
3914 (vidupq_m_wb_u8): Likewise.
3915 (vidupq_m_wb_u16): Likewise.
3916 (vidupq_m_wb_u32): Likewise.
3917 (vidupq_n_u8): Likewise.
3918 (vidupq_n_u32): Likewise.
3919 (vidupq_n_u16): Likewise.
3920 (vidupq_wb_u8): Likewise.
3921 (vidupq_wb_u16): Likewise.
3922 (vidupq_wb_u32): Likewise.
3923 (viwdupq_m_n_u8): Likewise.
3924 (viwdupq_m_n_u32): Likewise.
3925 (viwdupq_m_n_u16): Likewise.
3926 (viwdupq_m_wb_u8): Likewise.
3927 (viwdupq_m_wb_u32): Likewise.
3928 (viwdupq_m_wb_u16): Likewise.
3929 (viwdupq_n_u8): Likewise.
3930 (viwdupq_n_u32): Likewise.
3931 (viwdupq_n_u16): Likewise.
3932 (viwdupq_wb_u8): Likewise.
3933 (viwdupq_wb_u32): Likewise.
3934 (viwdupq_wb_u16): Likewise.
3935 (__arm_vddupq_m_n_u8): Define intrinsic.
3936 (__arm_vddupq_m_n_u32): Likewise.
3937 (__arm_vddupq_m_n_u16): Likewise.
3938 (__arm_vddupq_m_wb_u8): Likewise.
3939 (__arm_vddupq_m_wb_u16): Likewise.
3940 (__arm_vddupq_m_wb_u32): Likewise.
3941 (__arm_vddupq_n_u8): Likewise.
3942 (__arm_vddupq_n_u32): Likewise.
3943 (__arm_vddupq_n_u16): Likewise.
3944 (__arm_vdwdupq_m_n_u8): Likewise.
3945 (__arm_vdwdupq_m_n_u32): Likewise.
3946 (__arm_vdwdupq_m_n_u16): Likewise.
3947 (__arm_vdwdupq_m_wb_u8): Likewise.
3948 (__arm_vdwdupq_m_wb_u32): Likewise.
3949 (__arm_vdwdupq_m_wb_u16): Likewise.
3950 (__arm_vdwdupq_n_u8): Likewise.
3951 (__arm_vdwdupq_n_u32): Likewise.
3952 (__arm_vdwdupq_n_u16): Likewise.
3953 (__arm_vdwdupq_wb_u8): Likewise.
3954 (__arm_vdwdupq_wb_u32): Likewise.
3955 (__arm_vdwdupq_wb_u16): Likewise.
3956 (__arm_vidupq_m_n_u8): Likewise.
3957 (__arm_vidupq_m_n_u32): Likewise.
3958 (__arm_vidupq_m_n_u16): Likewise.
3959 (__arm_vidupq_n_u8): Likewise.
3960 (__arm_vidupq_m_wb_u8): Likewise.
3961 (__arm_vidupq_m_wb_u16): Likewise.
3962 (__arm_vidupq_m_wb_u32): Likewise.
3963 (__arm_vidupq_n_u32): Likewise.
3964 (__arm_vidupq_n_u16): Likewise.
3965 (__arm_vidupq_wb_u8): Likewise.
3966 (__arm_vidupq_wb_u16): Likewise.
3967 (__arm_vidupq_wb_u32): Likewise.
3968 (__arm_vddupq_wb_u8): Likewise.
3969 (__arm_vddupq_wb_u16): Likewise.
3970 (__arm_vddupq_wb_u32): Likewise.
3971 (__arm_viwdupq_m_n_u8): Likewise.
3972 (__arm_viwdupq_m_n_u32): Likewise.
3973 (__arm_viwdupq_m_n_u16): Likewise.
3974 (__arm_viwdupq_m_wb_u8): Likewise.
3975 (__arm_viwdupq_m_wb_u32): Likewise.
3976 (__arm_viwdupq_m_wb_u16): Likewise.
3977 (__arm_viwdupq_n_u8): Likewise.
3978 (__arm_viwdupq_n_u32): Likewise.
3979 (__arm_viwdupq_n_u16): Likewise.
3980 (__arm_viwdupq_wb_u8): Likewise.
3981 (__arm_viwdupq_wb_u32): Likewise.
3982 (__arm_viwdupq_wb_u16): Likewise.
3983 (vidupq_m): Define polymorphic variant.
3984 (vddupq_m): Likewise.
3985 (vidupq_u16): Likewise.
3986 (vidupq_u32): Likewise.
3987 (vidupq_u8): Likewise.
3988 (vddupq_u16): Likewise.
3989 (vddupq_u32): Likewise.
3990 (vddupq_u8): Likewise.
3991 (viwdupq_m): Likewise.
3992 (viwdupq_u16): Likewise.
3993 (viwdupq_u32): Likewise.
3994 (viwdupq_u8): Likewise.
3995 (vdwdupq_m): Likewise.
3996 (vdwdupq_u16): Likewise.
3997 (vdwdupq_u32): Likewise.
3998 (vdwdupq_u8): Likewise.
3999 * config/arm/arm_mve_builtins.def
4000 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin
4002 * config/arm/mve.md (mve_vidupq_n_u<mode>): Define RTL pattern.
4003 (mve_vidupq_u<mode>_insn): Likewise.
4004 (mve_vidupq_m_n_u<mode>): Likewise.
4005 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
4006 (mve_vddupq_n_u<mode>): Likewise.
4007 (mve_vddupq_u<mode>_insn): Likewise.
4008 (mve_vddupq_m_n_u<mode>): Likewise.
4009 (mve_vddupq_m_wb_u<mode>_insn): Likewise.
4010 (mve_vdwdupq_n_u<mode>): Likewise.
4011 (mve_vdwdupq_wb_u<mode>): Likewise.
4012 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
4013 (mve_vdwdupq_m_n_u<mode>): Likewise.
4014 (mve_vdwdupq_m_wb_u<mode>): Likewise.
4015 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
4016 (mve_viwdupq_n_u<mode>): Likewise.
4017 (mve_viwdupq_wb_u<mode>): Likewise.
4018 (mve_viwdupq_wb_u<mode>_insn): Likewise.
4019 (mve_viwdupq_m_n_u<mode>): Likewise.
4020 (mve_viwdupq_m_wb_u<mode>): Likewise.
4021 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
4023 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4025 * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro.
4026 (vreinterpretq_s16_s64): Likewise.
4027 (vreinterpretq_s16_s8): Likewise.
4028 (vreinterpretq_s16_u16): Likewise.
4029 (vreinterpretq_s16_u32): Likewise.
4030 (vreinterpretq_s16_u64): Likewise.
4031 (vreinterpretq_s16_u8): Likewise.
4032 (vreinterpretq_s32_s16): Likewise.
4033 (vreinterpretq_s32_s64): Likewise.
4034 (vreinterpretq_s32_s8): Likewise.
4035 (vreinterpretq_s32_u16): Likewise.
4036 (vreinterpretq_s32_u32): Likewise.
4037 (vreinterpretq_s32_u64): Likewise.
4038 (vreinterpretq_s32_u8): Likewise.
4039 (vreinterpretq_s64_s16): Likewise.
4040 (vreinterpretq_s64_s32): Likewise.
4041 (vreinterpretq_s64_s8): Likewise.
4042 (vreinterpretq_s64_u16): Likewise.
4043 (vreinterpretq_s64_u32): Likewise.
4044 (vreinterpretq_s64_u64): Likewise.
4045 (vreinterpretq_s64_u8): Likewise.
4046 (vreinterpretq_s8_s16): Likewise.
4047 (vreinterpretq_s8_s32): Likewise.
4048 (vreinterpretq_s8_s64): Likewise.
4049 (vreinterpretq_s8_u16): Likewise.
4050 (vreinterpretq_s8_u32): Likewise.
4051 (vreinterpretq_s8_u64): Likewise.
4052 (vreinterpretq_s8_u8): Likewise.
4053 (vreinterpretq_u16_s16): Likewise.
4054 (vreinterpretq_u16_s32): Likewise.
4055 (vreinterpretq_u16_s64): Likewise.
4056 (vreinterpretq_u16_s8): Likewise.
4057 (vreinterpretq_u16_u32): Likewise.
4058 (vreinterpretq_u16_u64): Likewise.
4059 (vreinterpretq_u16_u8): Likewise.
4060 (vreinterpretq_u32_s16): Likewise.
4061 (vreinterpretq_u32_s32): Likewise.
4062 (vreinterpretq_u32_s64): Likewise.
4063 (vreinterpretq_u32_s8): Likewise.
4064 (vreinterpretq_u32_u16): Likewise.
4065 (vreinterpretq_u32_u64): Likewise.
4066 (vreinterpretq_u32_u8): Likewise.
4067 (vreinterpretq_u64_s16): Likewise.
4068 (vreinterpretq_u64_s32): Likewise.
4069 (vreinterpretq_u64_s64): Likewise.
4070 (vreinterpretq_u64_s8): Likewise.
4071 (vreinterpretq_u64_u16): Likewise.
4072 (vreinterpretq_u64_u32): Likewise.
4073 (vreinterpretq_u64_u8): Likewise.
4074 (vreinterpretq_u8_s16): Likewise.
4075 (vreinterpretq_u8_s32): Likewise.
4076 (vreinterpretq_u8_s64): Likewise.
4077 (vreinterpretq_u8_s8): Likewise.
4078 (vreinterpretq_u8_u16): Likewise.
4079 (vreinterpretq_u8_u32): Likewise.
4080 (vreinterpretq_u8_u64): Likewise.
4081 (vreinterpretq_s32_f16): Likewise.
4082 (vreinterpretq_s32_f32): Likewise.
4083 (vreinterpretq_u16_f16): Likewise.
4084 (vreinterpretq_u16_f32): Likewise.
4085 (vreinterpretq_u32_f16): Likewise.
4086 (vreinterpretq_u32_f32): Likewise.
4087 (vreinterpretq_u64_f16): Likewise.
4088 (vreinterpretq_u64_f32): Likewise.
4089 (vreinterpretq_u8_f16): Likewise.
4090 (vreinterpretq_u8_f32): Likewise.
4091 (vreinterpretq_f16_f32): Likewise.
4092 (vreinterpretq_f16_s16): Likewise.
4093 (vreinterpretq_f16_s32): Likewise.
4094 (vreinterpretq_f16_s64): Likewise.
4095 (vreinterpretq_f16_s8): Likewise.
4096 (vreinterpretq_f16_u16): Likewise.
4097 (vreinterpretq_f16_u32): Likewise.
4098 (vreinterpretq_f16_u64): Likewise.
4099 (vreinterpretq_f16_u8): Likewise.
4100 (vreinterpretq_f32_f16): Likewise.
4101 (vreinterpretq_f32_s16): Likewise.
4102 (vreinterpretq_f32_s32): Likewise.
4103 (vreinterpretq_f32_s64): Likewise.
4104 (vreinterpretq_f32_s8): Likewise.
4105 (vreinterpretq_f32_u16): Likewise.
4106 (vreinterpretq_f32_u32): Likewise.
4107 (vreinterpretq_f32_u64): Likewise.
4108 (vreinterpretq_f32_u8): Likewise.
4109 (vreinterpretq_s16_f16): Likewise.
4110 (vreinterpretq_s16_f32): Likewise.
4111 (vreinterpretq_s64_f16): Likewise.
4112 (vreinterpretq_s64_f32): Likewise.
4113 (vreinterpretq_s8_f16): Likewise.
4114 (vreinterpretq_s8_f32): Likewise.
4115 (vuninitializedq_u8): Likewise.
4116 (vuninitializedq_u16): Likewise.
4117 (vuninitializedq_u32): Likewise.
4118 (vuninitializedq_u64): Likewise.
4119 (vuninitializedq_s8): Likewise.
4120 (vuninitializedq_s16): Likewise.
4121 (vuninitializedq_s32): Likewise.
4122 (vuninitializedq_s64): Likewise.
4123 (vuninitializedq_f16): Likewise.
4124 (vuninitializedq_f32): Likewise.
4125 (__arm_vuninitializedq_u8): Define intrinsic.
4126 (__arm_vuninitializedq_u16): Likewise.
4127 (__arm_vuninitializedq_u32): Likewise.
4128 (__arm_vuninitializedq_u64): Likewise.
4129 (__arm_vuninitializedq_s8): Likewise.
4130 (__arm_vuninitializedq_s16): Likewise.
4131 (__arm_vuninitializedq_s32): Likewise.
4132 (__arm_vuninitializedq_s64): Likewise.
4133 (__arm_vreinterpretq_s16_s32): Likewise.
4134 (__arm_vreinterpretq_s16_s64): Likewise.
4135 (__arm_vreinterpretq_s16_s8): Likewise.
4136 (__arm_vreinterpretq_s16_u16): Likewise.
4137 (__arm_vreinterpretq_s16_u32): Likewise.
4138 (__arm_vreinterpretq_s16_u64): Likewise.
4139 (__arm_vreinterpretq_s16_u8): Likewise.
4140 (__arm_vreinterpretq_s32_s16): Likewise.
4141 (__arm_vreinterpretq_s32_s64): Likewise.
4142 (__arm_vreinterpretq_s32_s8): Likewise.
4143 (__arm_vreinterpretq_s32_u16): Likewise.
4144 (__arm_vreinterpretq_s32_u32): Likewise.
4145 (__arm_vreinterpretq_s32_u64): Likewise.
4146 (__arm_vreinterpretq_s32_u8): Likewise.
4147 (__arm_vreinterpretq_s64_s16): Likewise.
4148 (__arm_vreinterpretq_s64_s32): Likewise.
4149 (__arm_vreinterpretq_s64_s8): Likewise.
4150 (__arm_vreinterpretq_s64_u16): Likewise.
4151 (__arm_vreinterpretq_s64_u32): Likewise.
4152 (__arm_vreinterpretq_s64_u64): Likewise.
4153 (__arm_vreinterpretq_s64_u8): Likewise.
4154 (__arm_vreinterpretq_s8_s16): Likewise.
4155 (__arm_vreinterpretq_s8_s32): Likewise.
4156 (__arm_vreinterpretq_s8_s64): Likewise.
4157 (__arm_vreinterpretq_s8_u16): Likewise.
4158 (__arm_vreinterpretq_s8_u32): Likewise.
4159 (__arm_vreinterpretq_s8_u64): Likewise.
4160 (__arm_vreinterpretq_s8_u8): Likewise.
4161 (__arm_vreinterpretq_u16_s16): Likewise.
4162 (__arm_vreinterpretq_u16_s32): Likewise.
4163 (__arm_vreinterpretq_u16_s64): Likewise.
4164 (__arm_vreinterpretq_u16_s8): Likewise.
4165 (__arm_vreinterpretq_u16_u32): Likewise.
4166 (__arm_vreinterpretq_u16_u64): Likewise.
4167 (__arm_vreinterpretq_u16_u8): Likewise.
4168 (__arm_vreinterpretq_u32_s16): Likewise.
4169 (__arm_vreinterpretq_u32_s32): Likewise.
4170 (__arm_vreinterpretq_u32_s64): Likewise.
4171 (__arm_vreinterpretq_u32_s8): Likewise.
4172 (__arm_vreinterpretq_u32_u16): Likewise.
4173 (__arm_vreinterpretq_u32_u64): Likewise.
4174 (__arm_vreinterpretq_u32_u8): Likewise.
4175 (__arm_vreinterpretq_u64_s16): Likewise.
4176 (__arm_vreinterpretq_u64_s32): Likewise.
4177 (__arm_vreinterpretq_u64_s64): Likewise.
4178 (__arm_vreinterpretq_u64_s8): Likewise.
4179 (__arm_vreinterpretq_u64_u16): Likewise.
4180 (__arm_vreinterpretq_u64_u32): Likewise.
4181 (__arm_vreinterpretq_u64_u8): Likewise.
4182 (__arm_vreinterpretq_u8_s16): Likewise.
4183 (__arm_vreinterpretq_u8_s32): Likewise.
4184 (__arm_vreinterpretq_u8_s64): Likewise.
4185 (__arm_vreinterpretq_u8_s8): Likewise.
4186 (__arm_vreinterpretq_u8_u16): Likewise.
4187 (__arm_vreinterpretq_u8_u32): Likewise.
4188 (__arm_vreinterpretq_u8_u64): Likewise.
4189 (__arm_vuninitializedq_f16): Likewise.
4190 (__arm_vuninitializedq_f32): Likewise.
4191 (__arm_vreinterpretq_s32_f16): Likewise.
4192 (__arm_vreinterpretq_s32_f32): Likewise.
4193 (__arm_vreinterpretq_s16_f16): Likewise.
4194 (__arm_vreinterpretq_s16_f32): Likewise.
4195 (__arm_vreinterpretq_s64_f16): Likewise.
4196 (__arm_vreinterpretq_s64_f32): Likewise.
4197 (__arm_vreinterpretq_s8_f16): Likewise.
4198 (__arm_vreinterpretq_s8_f32): Likewise.
4199 (__arm_vreinterpretq_u16_f16): Likewise.
4200 (__arm_vreinterpretq_u16_f32): Likewise.
4201 (__arm_vreinterpretq_u32_f16): Likewise.
4202 (__arm_vreinterpretq_u32_f32): Likewise.
4203 (__arm_vreinterpretq_u64_f16): Likewise.
4204 (__arm_vreinterpretq_u64_f32): Likewise.
4205 (__arm_vreinterpretq_u8_f16): Likewise.
4206 (__arm_vreinterpretq_u8_f32): Likewise.
4207 (__arm_vreinterpretq_f16_f32): Likewise.
4208 (__arm_vreinterpretq_f16_s16): Likewise.
4209 (__arm_vreinterpretq_f16_s32): Likewise.
4210 (__arm_vreinterpretq_f16_s64): Likewise.
4211 (__arm_vreinterpretq_f16_s8): Likewise.
4212 (__arm_vreinterpretq_f16_u16): Likewise.
4213 (__arm_vreinterpretq_f16_u32): Likewise.
4214 (__arm_vreinterpretq_f16_u64): Likewise.
4215 (__arm_vreinterpretq_f16_u8): Likewise.
4216 (__arm_vreinterpretq_f32_f16): Likewise.
4217 (__arm_vreinterpretq_f32_s16): Likewise.
4218 (__arm_vreinterpretq_f32_s32): Likewise.
4219 (__arm_vreinterpretq_f32_s64): Likewise.
4220 (__arm_vreinterpretq_f32_s8): Likewise.
4221 (__arm_vreinterpretq_f32_u16): Likewise.
4222 (__arm_vreinterpretq_f32_u32): Likewise.
4223 (__arm_vreinterpretq_f32_u64): Likewise.
4224 (__arm_vreinterpretq_f32_u8): Likewise.
4225 (vuninitializedq): Define polymorphic variant.
4226 (vreinterpretq_f16): Likewise.
4227 (vreinterpretq_f32): Likewise.
4228 (vreinterpretq_s16): Likewise.
4229 (vreinterpretq_s32): Likewise.
4230 (vreinterpretq_s64): Likewise.
4231 (vreinterpretq_s8): Likewise.
4232 (vreinterpretq_u16): Likewise.
4233 (vreinterpretq_u32): Likewise.
4234 (vreinterpretq_u64): Likewise.
4235 (vreinterpretq_u8): Likewise.
4237 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4238 Andre Vieira <andre.simoesdiasvieira@arm.com>
4239 Mihail Ionescu <mihail.ionescu@arm.com>
4241 * config/arm/arm_mve.h (vaddq_s8): Define macro.
4242 (vaddq_s16): Likewise.
4243 (vaddq_s32): Likewise.
4244 (vaddq_u8): Likewise.
4245 (vaddq_u16): Likewise.
4246 (vaddq_u32): Likewise.
4247 (vaddq_f16): Likewise.
4248 (vaddq_f32): Likewise.
4249 (__arm_vaddq_s8): Define intrinsic.
4250 (__arm_vaddq_s16): Likewise.
4251 (__arm_vaddq_s32): Likewise.
4252 (__arm_vaddq_u8): Likewise.
4253 (__arm_vaddq_u16): Likewise.
4254 (__arm_vaddq_u32): Likewise.
4255 (__arm_vaddq_f16): Likewise.
4256 (__arm_vaddq_f32): Likewise.
4257 (vaddq): Define polymorphic variant.
4258 * config/arm/iterators.md (VNIM): Define mode iterator for common types
4259 Neon, IWMMXT and MVE.
4260 (VNINOTM): Likewise.
4261 * config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern.
4262 (mve_vaddq_f<mode>): Define RTL pattern.
4263 * config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern.
4264 (addv8hf3_neon): Define RTL pattern.
4265 * config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern
4267 (addv8hf3): Define standard RTL pattern for MVE and Neon.
4268 (add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT.
4270 2020-03-20 Martin Liska <mliska@suse.cz>
4273 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously
4274 build_ref_for_offset function was used and it transforms off to bytes
4277 2020-03-20 Richard Biener <rguenther@suse.de>
4279 PR tree-optimization/94266
4280 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the
4281 type of the underlying object to adjust for the containing
4284 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
4286 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
4287 (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
4288 * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
4290 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
4292 * config/arm/mve.md (mve_mov<mode>): Fix R->R case.
4294 2020-03-20 Jakub Jelinek <jakub@redhat.com>
4296 PR tree-optimization/94224
4297 * gimple-ssa-store-merging.c
4298 (imm_store_chain_info::coalesce_immediate): Don't consider overlapping
4299 or adjacent INTEGER_CST rhs_code stores as mergeable if they have
4302 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
4304 * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve.
4306 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
4309 * cgraph.c (cgraph_node::function_symbol): Fix availability computation.
4310 (cgraph_node::function_or_virtual_thunk_symbol): Likewise.
4312 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
4315 * cgraphunit.c (process_function_and_variable_attributes): warn
4316 for flatten attribute on alias.
4317 * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias.
4319 2020-03-19 Martin Liska <mliska@suse.cz>
4321 * lto-section-in.c: Add ext_symtab.
4322 * lto-streamer-out.c (write_symbol_extension_info): New.
4323 (produce_symtab_extension): New.
4324 (produce_asm_for_decls): Stream also produce_symtab_extension.
4325 * lto-streamer.h (enum lto_section_type): New section.
4327 2020-03-19 Jakub Jelinek <jakub@redhat.com>
4329 PR tree-optimization/94211
4330 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq
4331 instead of estimate_num_insns for bb_seq (middle_bb). Rename
4332 emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust
4335 2020-03-19 Richard Biener <rguenther@suse.de>
4338 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr
4339 and build_ref_for_offset.
4341 2020-03-19 Richard Biener <rguenther@suse.de>
4344 * fold-const.c (fold_binary_loc): Avoid using
4345 build_fold_addr_expr when we really want an ADDR_EXPR.
4347 2020-03-18 Segher Boessenkool <segher@kernel.crashing.org>
4349 * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented
4352 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
4354 PR rtl-optimization/90275
4355 * cse.c (cse_insn): Delete no-op register moves too.
4357 2020-03-18 Martin Sebor <msebor@redhat.com>
4360 * cgraphunit.c (process_function_and_variable_attributes): Also
4361 complain about weakref function definitions and drop all effects
4364 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4365 Mihail Ionescu <mihail.ionescu@arm.com>
4366 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4368 * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro.
4369 (vstrdq_scatter_base_p_u64): Likewise.
4370 (vstrdq_scatter_base_s64): Likewise.
4371 (vstrdq_scatter_base_u64): Likewise.
4372 (vstrdq_scatter_offset_p_s64): Likewise.
4373 (vstrdq_scatter_offset_p_u64): Likewise.
4374 (vstrdq_scatter_offset_s64): Likewise.
4375 (vstrdq_scatter_offset_u64): Likewise.
4376 (vstrdq_scatter_shifted_offset_p_s64): Likewise.
4377 (vstrdq_scatter_shifted_offset_p_u64): Likewise.
4378 (vstrdq_scatter_shifted_offset_s64): Likewise.
4379 (vstrdq_scatter_shifted_offset_u64): Likewise.
4380 (vstrhq_scatter_offset_f16): Likewise.
4381 (vstrhq_scatter_offset_p_f16): Likewise.
4382 (vstrhq_scatter_shifted_offset_f16): Likewise.
4383 (vstrhq_scatter_shifted_offset_p_f16): Likewise.
4384 (vstrwq_scatter_base_f32): Likewise.
4385 (vstrwq_scatter_base_p_f32): Likewise.
4386 (vstrwq_scatter_offset_f32): Likewise.
4387 (vstrwq_scatter_offset_p_f32): Likewise.
4388 (vstrwq_scatter_offset_p_s32): Likewise.
4389 (vstrwq_scatter_offset_p_u32): Likewise.
4390 (vstrwq_scatter_offset_s32): Likewise.
4391 (vstrwq_scatter_offset_u32): Likewise.
4392 (vstrwq_scatter_shifted_offset_f32): Likewise.
4393 (vstrwq_scatter_shifted_offset_p_f32): Likewise.
4394 (vstrwq_scatter_shifted_offset_p_s32): Likewise.
4395 (vstrwq_scatter_shifted_offset_p_u32): Likewise.
4396 (vstrwq_scatter_shifted_offset_s32): Likewise.
4397 (vstrwq_scatter_shifted_offset_u32): Likewise.
4398 (__arm_vstrdq_scatter_base_p_s64): Define intrinsic.
4399 (__arm_vstrdq_scatter_base_p_u64): Likewise.
4400 (__arm_vstrdq_scatter_base_s64): Likewise.
4401 (__arm_vstrdq_scatter_base_u64): Likewise.
4402 (__arm_vstrdq_scatter_offset_p_s64): Likewise.
4403 (__arm_vstrdq_scatter_offset_p_u64): Likewise.
4404 (__arm_vstrdq_scatter_offset_s64): Likewise.
4405 (__arm_vstrdq_scatter_offset_u64): Likewise.
4406 (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise.
4407 (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise.
4408 (__arm_vstrdq_scatter_shifted_offset_s64): Likewise.
4409 (__arm_vstrdq_scatter_shifted_offset_u64): Likewise.
4410 (__arm_vstrwq_scatter_offset_p_s32): Likewise.
4411 (__arm_vstrwq_scatter_offset_p_u32): Likewise.
4412 (__arm_vstrwq_scatter_offset_s32): Likewise.
4413 (__arm_vstrwq_scatter_offset_u32): Likewise.
4414 (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise.
4415 (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise.
4416 (__arm_vstrwq_scatter_shifted_offset_s32): Likewise.
4417 (__arm_vstrwq_scatter_shifted_offset_u32): Likewise.
4418 (__arm_vstrhq_scatter_offset_f16): Likewise.
4419 (__arm_vstrhq_scatter_offset_p_f16): Likewise.
4420 (__arm_vstrhq_scatter_shifted_offset_f16): Likewise.
4421 (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise.
4422 (__arm_vstrwq_scatter_base_f32): Likewise.
4423 (__arm_vstrwq_scatter_base_p_f32): Likewise.
4424 (__arm_vstrwq_scatter_offset_f32): Likewise.
4425 (__arm_vstrwq_scatter_offset_p_f32): Likewise.
4426 (__arm_vstrwq_scatter_shifted_offset_f32): Likewise.
4427 (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise.
4428 (vstrhq_scatter_offset): Define polymorphic variant.
4429 (vstrhq_scatter_offset_p): Likewise.
4430 (vstrhq_scatter_shifted_offset): Likewise.
4431 (vstrhq_scatter_shifted_offset_p): Likewise.
4432 (vstrwq_scatter_base): Likewise.
4433 (vstrwq_scatter_base_p): Likewise.
4434 (vstrwq_scatter_offset): Likewise.
4435 (vstrwq_scatter_offset_p): Likewise.
4436 (vstrwq_scatter_shifted_offset): Likewise.
4437 (vstrwq_scatter_shifted_offset_p): Likewise.
4438 (vstrdq_scatter_base_p): Likewise.
4439 (vstrdq_scatter_base): Likewise.
4440 (vstrdq_scatter_offset_p): Likewise.
4441 (vstrdq_scatter_offset): Likewise.
4442 (vstrdq_scatter_shifted_offset_p): Likewise.
4443 (vstrdq_scatter_shifted_offset): Likewise.
4444 * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier.
4445 (STRSBS_P): Likewise.
4447 (STRSBU_P): Likewise.
4449 (STRSS_P): Likewise.
4451 (STRSU_P): Likewise.
4452 * config/arm/constraints.md (Ri): Define.
4453 * config/arm/mve.md (VSTRDSBQ): Define iterator.
4454 (VSTRDSOQ): Likewise.
4455 (VSTRDSSOQ): Likewise.
4456 (VSTRWSOQ): Likewise.
4457 (VSTRWSSOQ): Likewise.
4458 (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern.
4459 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
4460 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
4461 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
4462 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
4463 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
4464 (mve_vstrhq_scatter_offset_fv8hf): Likewise.
4465 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
4466 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
4467 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
4468 (mve_vstrwq_scatter_base_fv4sf): Likewise.
4469 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
4470 (mve_vstrwq_scatter_offset_fv4sf): Likewise.
4471 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
4472 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
4473 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
4474 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
4475 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
4476 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
4477 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
4478 * config/arm/predicates.md (Ri): Define predicate to check immediate
4479 is the range +/-1016 and multiple of 8.
4481 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4482 Mihail Ionescu <mihail.ionescu@arm.com>
4483 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4485 * config/arm/arm_mve.h (vst1q_f32): Define macro.
4486 (vst1q_f16): Likewise.
4487 (vst1q_s8): Likewise.
4488 (vst1q_s32): Likewise.
4489 (vst1q_s16): Likewise.
4490 (vst1q_u8): Likewise.
4491 (vst1q_u32): Likewise.
4492 (vst1q_u16): Likewise.
4493 (vstrhq_f16): Likewise.
4494 (vstrhq_scatter_offset_s32): Likewise.
4495 (vstrhq_scatter_offset_s16): Likewise.
4496 (vstrhq_scatter_offset_u32): Likewise.
4497 (vstrhq_scatter_offset_u16): Likewise.
4498 (vstrhq_scatter_offset_p_s32): Likewise.
4499 (vstrhq_scatter_offset_p_s16): Likewise.
4500 (vstrhq_scatter_offset_p_u32): Likewise.
4501 (vstrhq_scatter_offset_p_u16): Likewise.
4502 (vstrhq_scatter_shifted_offset_s32): Likewise.
4503 (vstrhq_scatter_shifted_offset_s16): Likewise.
4504 (vstrhq_scatter_shifted_offset_u32): Likewise.
4505 (vstrhq_scatter_shifted_offset_u16): Likewise.
4506 (vstrhq_scatter_shifted_offset_p_s32): Likewise.
4507 (vstrhq_scatter_shifted_offset_p_s16): Likewise.
4508 (vstrhq_scatter_shifted_offset_p_u32): Likewise.
4509 (vstrhq_scatter_shifted_offset_p_u16): Likewise.
4510 (vstrhq_s32): Likewise.
4511 (vstrhq_s16): Likewise.
4512 (vstrhq_u32): Likewise.
4513 (vstrhq_u16): Likewise.
4514 (vstrhq_p_f16): Likewise.
4515 (vstrhq_p_s32): Likewise.
4516 (vstrhq_p_s16): Likewise.
4517 (vstrhq_p_u32): Likewise.
4518 (vstrhq_p_u16): Likewise.
4519 (vstrwq_f32): Likewise.
4520 (vstrwq_s32): Likewise.
4521 (vstrwq_u32): Likewise.
4522 (vstrwq_p_f32): Likewise.
4523 (vstrwq_p_s32): Likewise.
4524 (vstrwq_p_u32): Likewise.
4525 (__arm_vst1q_s8): Define intrinsic.
4526 (__arm_vst1q_s32): Likewise.
4527 (__arm_vst1q_s16): Likewise.
4528 (__arm_vst1q_u8): Likewise.
4529 (__arm_vst1q_u32): Likewise.
4530 (__arm_vst1q_u16): Likewise.
4531 (__arm_vstrhq_scatter_offset_s32): Likewise.
4532 (__arm_vstrhq_scatter_offset_s16): Likewise.
4533 (__arm_vstrhq_scatter_offset_u32): Likewise.
4534 (__arm_vstrhq_scatter_offset_u16): Likewise.
4535 (__arm_vstrhq_scatter_offset_p_s32): Likewise.
4536 (__arm_vstrhq_scatter_offset_p_s16): Likewise.
4537 (__arm_vstrhq_scatter_offset_p_u32): Likewise.
4538 (__arm_vstrhq_scatter_offset_p_u16): Likewise.
4539 (__arm_vstrhq_scatter_shifted_offset_s32): Likewise.
4540 (__arm_vstrhq_scatter_shifted_offset_s16): Likewise.
4541 (__arm_vstrhq_scatter_shifted_offset_u32): Likewise.
4542 (__arm_vstrhq_scatter_shifted_offset_u16): Likewise.
4543 (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise.
4544 (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise.
4545 (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise.
4546 (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise.
4547 (__arm_vstrhq_s32): Likewise.
4548 (__arm_vstrhq_s16): Likewise.
4549 (__arm_vstrhq_u32): Likewise.
4550 (__arm_vstrhq_u16): Likewise.
4551 (__arm_vstrhq_p_s32): Likewise.
4552 (__arm_vstrhq_p_s16): Likewise.
4553 (__arm_vstrhq_p_u32): Likewise.
4554 (__arm_vstrhq_p_u16): Likewise.
4555 (__arm_vstrwq_s32): Likewise.
4556 (__arm_vstrwq_u32): Likewise.
4557 (__arm_vstrwq_p_s32): Likewise.
4558 (__arm_vstrwq_p_u32): Likewise.
4559 (__arm_vstrwq_p_f32): Likewise.
4560 (__arm_vstrwq_f32): Likewise.
4561 (__arm_vst1q_f32): Likewise.
4562 (__arm_vst1q_f16): Likewise.
4563 (__arm_vstrhq_f16): Likewise.
4564 (__arm_vstrhq_p_f16): Likewise.
4565 (vst1q): Define polymorphic variant.
4567 (vstrhq_p): Likewise.
4568 (vstrhq_scatter_offset_p): Likewise.
4569 (vstrhq_scatter_offset): Likewise.
4570 (vstrhq_scatter_shifted_offset_p): Likewise.
4571 (vstrhq_scatter_shifted_offset): Likewise.
4572 (vstrwq_p): Likewise.
4574 * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier.
4577 (STRSS_P): Likewise.
4579 (STRSU_P): Likewise.
4582 * config/arm/mve.md (VST1Q): Define iterator.
4583 (VSTRHSOQ): Likewise.
4584 (VSTRHSSOQ): Likewise.
4587 (mve_vstrhq_fv8hf): Define RTL pattern.
4588 (mve_vstrhq_p_fv8hf): Likewise.
4589 (mve_vstrhq_p_<supf><mode>): Likewise.
4590 (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise.
4591 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
4592 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
4593 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
4594 (mve_vstrhq_<supf><mode>): Likewise.
4595 (mve_vstrwq_fv4sf): Likewise.
4596 (mve_vstrwq_p_fv4sf): Likewise.
4597 (mve_vstrwq_p_<supf>v4si): Likewise.
4598 (mve_vstrwq_<supf>v4si): Likewise.
4599 (mve_vst1q_f<mode>): Define expand.
4600 (mve_vst1q_<supf><mode>): Likewise.
4602 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4603 Mihail Ionescu <mihail.ionescu@arm.com>
4604 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4606 * config/arm/arm_mve.h (vld1q_s8): Define macro.
4607 (vld1q_s32): Likewise.
4608 (vld1q_s16): Likewise.
4609 (vld1q_u8): Likewise.
4610 (vld1q_u32): Likewise.
4611 (vld1q_u16): Likewise.
4612 (vldrhq_gather_offset_s32): Likewise.
4613 (vldrhq_gather_offset_s16): Likewise.
4614 (vldrhq_gather_offset_u32): Likewise.
4615 (vldrhq_gather_offset_u16): Likewise.
4616 (vldrhq_gather_offset_z_s32): Likewise.
4617 (vldrhq_gather_offset_z_s16): Likewise.
4618 (vldrhq_gather_offset_z_u32): Likewise.
4619 (vldrhq_gather_offset_z_u16): Likewise.
4620 (vldrhq_gather_shifted_offset_s32): Likewise.
4621 (vldrhq_gather_shifted_offset_s16): Likewise.
4622 (vldrhq_gather_shifted_offset_u32): Likewise.
4623 (vldrhq_gather_shifted_offset_u16): Likewise.
4624 (vldrhq_gather_shifted_offset_z_s32): Likewise.
4625 (vldrhq_gather_shifted_offset_z_s16): Likewise.
4626 (vldrhq_gather_shifted_offset_z_u32): Likewise.
4627 (vldrhq_gather_shifted_offset_z_u16): Likewise.
4628 (vldrhq_s32): Likewise.
4629 (vldrhq_s16): Likewise.
4630 (vldrhq_u32): Likewise.
4631 (vldrhq_u16): Likewise.
4632 (vldrhq_z_s32): Likewise.
4633 (vldrhq_z_s16): Likewise.
4634 (vldrhq_z_u32): Likewise.
4635 (vldrhq_z_u16): Likewise.
4636 (vldrwq_s32): Likewise.
4637 (vldrwq_u32): Likewise.
4638 (vldrwq_z_s32): Likewise.
4639 (vldrwq_z_u32): Likewise.
4640 (vld1q_f32): Likewise.
4641 (vld1q_f16): Likewise.
4642 (vldrhq_f16): Likewise.
4643 (vldrhq_z_f16): Likewise.
4644 (vldrwq_f32): Likewise.
4645 (vldrwq_z_f32): Likewise.
4646 (__arm_vld1q_s8): Define intrinsic.
4647 (__arm_vld1q_s32): Likewise.
4648 (__arm_vld1q_s16): Likewise.
4649 (__arm_vld1q_u8): Likewise.
4650 (__arm_vld1q_u32): Likewise.
4651 (__arm_vld1q_u16): Likewise.
4652 (__arm_vldrhq_gather_offset_s32): Likewise.
4653 (__arm_vldrhq_gather_offset_s16): Likewise.
4654 (__arm_vldrhq_gather_offset_u32): Likewise.
4655 (__arm_vldrhq_gather_offset_u16): Likewise.
4656 (__arm_vldrhq_gather_offset_z_s32): Likewise.
4657 (__arm_vldrhq_gather_offset_z_s16): Likewise.
4658 (__arm_vldrhq_gather_offset_z_u32): Likewise.
4659 (__arm_vldrhq_gather_offset_z_u16): Likewise.
4660 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
4661 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
4662 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
4663 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
4664 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
4665 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
4666 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
4667 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
4668 (__arm_vldrhq_s32): Likewise.
4669 (__arm_vldrhq_s16): Likewise.
4670 (__arm_vldrhq_u32): Likewise.
4671 (__arm_vldrhq_u16): Likewise.
4672 (__arm_vldrhq_z_s32): Likewise.
4673 (__arm_vldrhq_z_s16): Likewise.
4674 (__arm_vldrhq_z_u32): Likewise.
4675 (__arm_vldrhq_z_u16): Likewise.
4676 (__arm_vldrwq_s32): Likewise.
4677 (__arm_vldrwq_u32): Likewise.
4678 (__arm_vldrwq_z_s32): Likewise.
4679 (__arm_vldrwq_z_u32): Likewise.
4680 (__arm_vld1q_f32): Likewise.
4681 (__arm_vld1q_f16): Likewise.
4682 (__arm_vldrwq_f32): Likewise.
4683 (__arm_vldrwq_z_f32): Likewise.
4684 (__arm_vldrhq_z_f16): Likewise.
4685 (__arm_vldrhq_f16): Likewise.
4686 (vld1q): Define polymorphic variant.
4687 (vldrhq_gather_offset): Likewise.
4688 (vldrhq_gather_offset_z): Likewise.
4689 (vldrhq_gather_shifted_offset): Likewise.
4690 (vldrhq_gather_shifted_offset_z): Likewise.
4691 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
4695 (LDRGU_Z): Likewise.
4697 (LDRGS_Z): Likewise.
4699 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
4700 (V_sz_elem1): Likewise.
4701 (VLD1Q): Define iterator.
4702 (VLDRHGOQ): Likewise.
4703 (VLDRHGSOQ): Likewise.
4706 (mve_vldrhq_fv8hf): Define RTL pattern.
4707 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
4708 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
4709 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
4710 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
4711 (mve_vldrhq_<supf><mode>): Likewise.
4712 (mve_vldrhq_z_fv8hf): Likewise.
4713 (mve_vldrhq_z_<supf><mode>): Likewise.
4714 (mve_vldrwq_fv4sf): Likewise.
4715 (mve_vldrwq_<supf>v4si): Likewise.
4716 (mve_vldrwq_z_fv4sf): Likewise.
4717 (mve_vldrwq_z_<supf>v4si): Likewise.
4718 (mve_vld1q_f<mode>): Define RTL expand pattern.
4719 (mve_vld1q_<supf><mode>): Likewise.
4721 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4722 Mihail Ionescu <mihail.ionescu@arm.com>
4723 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4725 * config/arm/arm_mve.h (vld1q_s8): Define macro.
4726 (vld1q_s32): Likewise.
4727 (vld1q_s16): Likewise.
4728 (vld1q_u8): Likewise.
4729 (vld1q_u32): Likewise.
4730 (vld1q_u16): Likewise.
4731 (vldrhq_gather_offset_s32): Likewise.
4732 (vldrhq_gather_offset_s16): Likewise.
4733 (vldrhq_gather_offset_u32): Likewise.
4734 (vldrhq_gather_offset_u16): Likewise.
4735 (vldrhq_gather_offset_z_s32): Likewise.
4736 (vldrhq_gather_offset_z_s16): Likewise.
4737 (vldrhq_gather_offset_z_u32): Likewise.
4738 (vldrhq_gather_offset_z_u16): Likewise.
4739 (vldrhq_gather_shifted_offset_s32): Likewise.
4740 (vldrhq_gather_shifted_offset_s16): Likewise.
4741 (vldrhq_gather_shifted_offset_u32): Likewise.
4742 (vldrhq_gather_shifted_offset_u16): Likewise.
4743 (vldrhq_gather_shifted_offset_z_s32): Likewise.
4744 (vldrhq_gather_shifted_offset_z_s16): Likewise.
4745 (vldrhq_gather_shifted_offset_z_u32): Likewise.
4746 (vldrhq_gather_shifted_offset_z_u16): Likewise.
4747 (vldrhq_s32): Likewise.
4748 (vldrhq_s16): Likewise.
4749 (vldrhq_u32): Likewise.
4750 (vldrhq_u16): Likewise.
4751 (vldrhq_z_s32): Likewise.
4752 (vldrhq_z_s16): Likewise.
4753 (vldrhq_z_u32): Likewise.
4754 (vldrhq_z_u16): Likewise.
4755 (vldrwq_s32): Likewise.
4756 (vldrwq_u32): Likewise.
4757 (vldrwq_z_s32): Likewise.
4758 (vldrwq_z_u32): Likewise.
4759 (vld1q_f32): Likewise.
4760 (vld1q_f16): Likewise.
4761 (vldrhq_f16): Likewise.
4762 (vldrhq_z_f16): Likewise.
4763 (vldrwq_f32): Likewise.
4764 (vldrwq_z_f32): Likewise.
4765 (__arm_vld1q_s8): Define intrinsic.
4766 (__arm_vld1q_s32): Likewise.
4767 (__arm_vld1q_s16): Likewise.
4768 (__arm_vld1q_u8): Likewise.
4769 (__arm_vld1q_u32): Likewise.
4770 (__arm_vld1q_u16): Likewise.
4771 (__arm_vldrhq_gather_offset_s32): Likewise.
4772 (__arm_vldrhq_gather_offset_s16): Likewise.
4773 (__arm_vldrhq_gather_offset_u32): Likewise.
4774 (__arm_vldrhq_gather_offset_u16): Likewise.
4775 (__arm_vldrhq_gather_offset_z_s32): Likewise.
4776 (__arm_vldrhq_gather_offset_z_s16): Likewise.
4777 (__arm_vldrhq_gather_offset_z_u32): Likewise.
4778 (__arm_vldrhq_gather_offset_z_u16): Likewise.
4779 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
4780 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
4781 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
4782 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
4783 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
4784 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
4785 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
4786 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
4787 (__arm_vldrhq_s32): Likewise.
4788 (__arm_vldrhq_s16): Likewise.
4789 (__arm_vldrhq_u32): Likewise.
4790 (__arm_vldrhq_u16): Likewise.
4791 (__arm_vldrhq_z_s32): Likewise.
4792 (__arm_vldrhq_z_s16): Likewise.
4793 (__arm_vldrhq_z_u32): Likewise.
4794 (__arm_vldrhq_z_u16): Likewise.
4795 (__arm_vldrwq_s32): Likewise.
4796 (__arm_vldrwq_u32): Likewise.
4797 (__arm_vldrwq_z_s32): Likewise.
4798 (__arm_vldrwq_z_u32): Likewise.
4799 (__arm_vld1q_f32): Likewise.
4800 (__arm_vld1q_f16): Likewise.
4801 (__arm_vldrwq_f32): Likewise.
4802 (__arm_vldrwq_z_f32): Likewise.
4803 (__arm_vldrhq_z_f16): Likewise.
4804 (__arm_vldrhq_f16): Likewise.
4805 (vld1q): Define polymorphic variant.
4806 (vldrhq_gather_offset): Likewise.
4807 (vldrhq_gather_offset_z): Likewise.
4808 (vldrhq_gather_shifted_offset): Likewise.
4809 (vldrhq_gather_shifted_offset_z): Likewise.
4810 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
4814 (LDRGU_Z): Likewise.
4816 (LDRGS_Z): Likewise.
4818 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
4819 (V_sz_elem1): Likewise.
4820 (VLD1Q): Define iterator.
4821 (VLDRHGOQ): Likewise.
4822 (VLDRHGSOQ): Likewise.
4825 (mve_vldrhq_fv8hf): Define RTL pattern.
4826 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
4827 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
4828 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
4829 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
4830 (mve_vldrhq_<supf><mode>): Likewise.
4831 (mve_vldrhq_z_fv8hf): Likewise.
4832 (mve_vldrhq_z_<supf><mode>): Likewise.
4833 (mve_vldrwq_fv4sf): Likewise.
4834 (mve_vldrwq_<supf>v4si): Likewise.
4835 (mve_vldrwq_z_fv4sf): Likewise.
4836 (mve_vldrwq_z_<supf>v4si): Likewise.
4837 (mve_vld1q_f<mode>): Define RTL expand pattern.
4838 (mve_vld1q_<supf><mode>): Likewise.
4840 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4841 Mihail Ionescu <mihail.ionescu@arm.com>
4842 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4844 * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin
4846 (LDRGBU_Z_QUALIFIERS): Likewise.
4847 (LDRGS_Z_QUALIFIERS): Likewise.
4848 (LDRGU_Z_QUALIFIERS): Likewise.
4849 (LDRS_Z_QUALIFIERS): Likewise.
4850 (LDRU_Z_QUALIFIERS): Likewise.
4851 * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro.
4852 (vldrbq_gather_offset_z_u8): Likewise.
4853 (vldrbq_gather_offset_z_s32): Likewise.
4854 (vldrbq_gather_offset_z_u16): Likewise.
4855 (vldrbq_gather_offset_z_u32): Likewise.
4856 (vldrbq_gather_offset_z_s8): Likewise.
4857 (vldrbq_z_s16): Likewise.
4858 (vldrbq_z_u8): Likewise.
4859 (vldrbq_z_s8): Likewise.
4860 (vldrbq_z_s32): Likewise.
4861 (vldrbq_z_u16): Likewise.
4862 (vldrbq_z_u32): Likewise.
4863 (vldrwq_gather_base_z_u32): Likewise.
4864 (vldrwq_gather_base_z_s32): Likewise.
4865 (__arm_vldrbq_gather_offset_z_s8): Define intrinsic.
4866 (__arm_vldrbq_gather_offset_z_s32): Likewise.
4867 (__arm_vldrbq_gather_offset_z_s16): Likewise.
4868 (__arm_vldrbq_gather_offset_z_u8): Likewise.
4869 (__arm_vldrbq_gather_offset_z_u32): Likewise.
4870 (__arm_vldrbq_gather_offset_z_u16): Likewise.
4871 (__arm_vldrbq_z_s8): Likewise.
4872 (__arm_vldrbq_z_s32): Likewise.
4873 (__arm_vldrbq_z_s16): Likewise.
4874 (__arm_vldrbq_z_u8): Likewise.
4875 (__arm_vldrbq_z_u32): Likewise.
4876 (__arm_vldrbq_z_u16): Likewise.
4877 (__arm_vldrwq_gather_base_z_s32): Likewise.
4878 (__arm_vldrwq_gather_base_z_u32): Likewise.
4879 (vldrbq_gather_offset_z): Define polymorphic variant.
4880 * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin
4882 (LDRGBU_Z_QUALIFIERS): Likewise.
4883 (LDRGS_Z_QUALIFIERS): Likewise.
4884 (LDRGU_Z_QUALIFIERS): Likewise.
4885 (LDRS_Z_QUALIFIERS): Likewise.
4886 (LDRU_Z_QUALIFIERS): Likewise.
4887 * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define
4889 (mve_vldrbq_z_<supf><mode>): Likewise.
4890 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
4892 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4893 Mihail Ionescu <mihail.ionescu@arm.com>
4894 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4896 * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin
4898 (STRU_P_QUALIFIERS): Likewise.
4899 (STRSU_P_QUALIFIERS): Likewise.
4900 (STRSS_P_QUALIFIERS): Likewise.
4901 (STRSBS_P_QUALIFIERS): Likewise.
4902 (STRSBU_P_QUALIFIERS): Likewise.
4903 * config/arm/arm_mve.h (vstrbq_p_s8): Define macro.
4904 (vstrbq_p_s32): Likewise.
4905 (vstrbq_p_s16): Likewise.
4906 (vstrbq_p_u8): Likewise.
4907 (vstrbq_p_u32): Likewise.
4908 (vstrbq_p_u16): Likewise.
4909 (vstrbq_scatter_offset_p_s8): Likewise.
4910 (vstrbq_scatter_offset_p_s32): Likewise.
4911 (vstrbq_scatter_offset_p_s16): Likewise.
4912 (vstrbq_scatter_offset_p_u8): Likewise.
4913 (vstrbq_scatter_offset_p_u32): Likewise.
4914 (vstrbq_scatter_offset_p_u16): Likewise.
4915 (vstrwq_scatter_base_p_s32): Likewise.
4916 (vstrwq_scatter_base_p_u32): Likewise.
4917 (__arm_vstrbq_p_s8): Define intrinsic.
4918 (__arm_vstrbq_p_s32): Likewise.
4919 (__arm_vstrbq_p_s16): Likewise.
4920 (__arm_vstrbq_p_u8): Likewise.
4921 (__arm_vstrbq_p_u32): Likewise.
4922 (__arm_vstrbq_p_u16): Likewise.
4923 (__arm_vstrbq_scatter_offset_p_s8): Likewise.
4924 (__arm_vstrbq_scatter_offset_p_s32): Likewise.
4925 (__arm_vstrbq_scatter_offset_p_s16): Likewise.
4926 (__arm_vstrbq_scatter_offset_p_u8): Likewise.
4927 (__arm_vstrbq_scatter_offset_p_u32): Likewise.
4928 (__arm_vstrbq_scatter_offset_p_u16): Likewise.
4929 (__arm_vstrwq_scatter_base_p_s32): Likewise.
4930 (__arm_vstrwq_scatter_base_p_u32): Likewise.
4931 (vstrbq_p): Define polymorphic variant.
4932 (vstrbq_scatter_offset_p): Likewise.
4933 (vstrwq_scatter_base_p): Likewise.
4934 * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin
4936 (STRU_P_QUALIFIERS): Likewise.
4937 (STRSU_P_QUALIFIERS): Likewise.
4938 (STRSS_P_QUALIFIERS): Likewise.
4939 (STRSBS_P_QUALIFIERS): Likewise.
4940 (STRSBU_P_QUALIFIERS): Likewise.
4941 * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define
4943 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
4944 (mve_vstrbq_p_<supf><mode>): Likewise.
4946 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4947 Mihail Ionescu <mihail.ionescu@arm.com>
4948 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4950 * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin
4952 (LDRGS_QUALIFIERS): Likewise.
4953 (LDRS_QUALIFIERS): Likewise.
4954 (LDRU_QUALIFIERS): Likewise.
4955 (LDRGBS_QUALIFIERS): Likewise.
4956 (LDRGBU_QUALIFIERS): Likewise.
4957 * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro.
4958 (vldrbq_gather_offset_s8): Likewise.
4959 (vldrbq_s8): Likewise.
4960 (vldrbq_u8): Likewise.
4961 (vldrbq_gather_offset_u16): Likewise.
4962 (vldrbq_gather_offset_s16): Likewise.
4963 (vldrbq_s16): Likewise.
4964 (vldrbq_u16): Likewise.
4965 (vldrbq_gather_offset_u32): Likewise.
4966 (vldrbq_gather_offset_s32): Likewise.
4967 (vldrbq_s32): Likewise.
4968 (vldrbq_u32): Likewise.
4969 (vldrwq_gather_base_s32): Likewise.
4970 (vldrwq_gather_base_u32): Likewise.
4971 (__arm_vldrbq_gather_offset_u8): Define intrinsic.
4972 (__arm_vldrbq_gather_offset_s8): Likewise.
4973 (__arm_vldrbq_s8): Likewise.
4974 (__arm_vldrbq_u8): Likewise.
4975 (__arm_vldrbq_gather_offset_u16): Likewise.
4976 (__arm_vldrbq_gather_offset_s16): Likewise.
4977 (__arm_vldrbq_s16): Likewise.
4978 (__arm_vldrbq_u16): Likewise.
4979 (__arm_vldrbq_gather_offset_u32): Likewise.
4980 (__arm_vldrbq_gather_offset_s32): Likewise.
4981 (__arm_vldrbq_s32): Likewise.
4982 (__arm_vldrbq_u32): Likewise.
4983 (__arm_vldrwq_gather_base_s32): Likewise.
4984 (__arm_vldrwq_gather_base_u32): Likewise.
4985 (vldrbq_gather_offset): Define polymorphic variant.
4986 * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin
4988 (LDRGS_QUALIFIERS): Likewise.
4989 (LDRS_QUALIFIERS): Likewise.
4990 (LDRU_QUALIFIERS): Likewise.
4991 (LDRGBS_QUALIFIERS): Likewise.
4992 (LDRGBU_QUALIFIERS): Likewise.
4993 * config/arm/mve.md (VLDRBGOQ): Define iterator.
4995 (VLDRWGBQ): Likewise.
4996 (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern.
4997 (mve_vldrbq_<supf><mode>): Likewise.
4998 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
5000 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
5001 Mihail Ionescu <mihail.ionescu@arm.com>
5002 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5004 * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier.
5005 (STRU_QUALIFIERS): Likewise.
5006 (STRSS_QUALIFIERS): Likewise.
5007 (STRSU_QUALIFIERS): Likewise.
5008 (STRSBS_QUALIFIERS): Likewise.
5009 (STRSBU_QUALIFIERS): Likewise.
5010 * config/arm/arm_mve.h (vstrbq_s8): Define macro.
5011 (vstrbq_u8): Likewise.
5012 (vstrbq_u16): Likewise.
5013 (vstrbq_scatter_offset_s8): Likewise.
5014 (vstrbq_scatter_offset_u8): Likewise.
5015 (vstrbq_scatter_offset_u16): Likewise.
5016 (vstrbq_s16): Likewise.
5017 (vstrbq_u32): Likewise.
5018 (vstrbq_scatter_offset_s16): Likewise.
5019 (vstrbq_scatter_offset_u32): Likewise.
5020 (vstrbq_s32): Likewise.
5021 (vstrbq_scatter_offset_s32): Likewise.
5022 (vstrwq_scatter_base_s32): Likewise.
5023 (vstrwq_scatter_base_u32): Likewise.
5024 (__arm_vstrbq_scatter_offset_s8): Define intrinsic.
5025 (__arm_vstrbq_scatter_offset_s32): Likewise.
5026 (__arm_vstrbq_scatter_offset_s16): Likewise.
5027 (__arm_vstrbq_scatter_offset_u8): Likewise.
5028 (__arm_vstrbq_scatter_offset_u32): Likewise.
5029 (__arm_vstrbq_scatter_offset_u16): Likewise.
5030 (__arm_vstrbq_s8): Likewise.
5031 (__arm_vstrbq_s32): Likewise.
5032 (__arm_vstrbq_s16): Likewise.
5033 (__arm_vstrbq_u8): Likewise.
5034 (__arm_vstrbq_u32): Likewise.
5035 (__arm_vstrbq_u16): Likewise.
5036 (__arm_vstrwq_scatter_base_s32): Likewise.
5037 (__arm_vstrwq_scatter_base_u32): Likewise.
5038 (vstrbq): Define polymorphic variant.
5039 (vstrbq_scatter_offset): Likewise.
5040 (vstrwq_scatter_base): Likewise.
5041 * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin
5043 (STRU_QUALIFIERS): Likewise.
5044 (STRSS_QUALIFIERS): Likewise.
5045 (STRSU_QUALIFIERS): Likewise.
5046 (STRSBS_QUALIFIERS): Likewise.
5047 (STRSBU_QUALIFIERS): Likewise.
5048 * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator.
5049 (VSTRWSBQ): Define iterators.
5050 (VSTRBSOQ): Likewise.
5052 (mve_vstrbq_<supf><mode>): Define RTL pattern.
5053 (mve_vstrbq_scatter_offset_<supf><mode>): Likewise.
5054 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
5056 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
5057 Mihail Ionescu <mihail.ionescu@arm.com>
5058 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5060 * config/arm/arm_mve.h (vabdq_m_f32): Define macro.
5061 (vabdq_m_f16): Likewise.
5062 (vaddq_m_f32): Likewise.
5063 (vaddq_m_f16): Likewise.
5064 (vaddq_m_n_f32): Likewise.
5065 (vaddq_m_n_f16): Likewise.
5066 (vandq_m_f32): Likewise.
5067 (vandq_m_f16): Likewise.
5068 (vbicq_m_f32): Likewise.
5069 (vbicq_m_f16): Likewise.
5070 (vbrsrq_m_n_f32): Likewise.
5071 (vbrsrq_m_n_f16): Likewise.
5072 (vcaddq_rot270_m_f32): Likewise.
5073 (vcaddq_rot270_m_f16): Likewise.
5074 (vcaddq_rot90_m_f32): Likewise.
5075 (vcaddq_rot90_m_f16): Likewise.
5076 (vcmlaq_m_f32): Likewise.
5077 (vcmlaq_m_f16): Likewise.
5078 (vcmlaq_rot180_m_f32): Likewise.
5079 (vcmlaq_rot180_m_f16): Likewise.
5080 (vcmlaq_rot270_m_f32): Likewise.
5081 (vcmlaq_rot270_m_f16): Likewise.
5082 (vcmlaq_rot90_m_f32): Likewise.
5083 (vcmlaq_rot90_m_f16): Likewise.
5084 (vcmulq_m_f32): Likewise.
5085 (vcmulq_m_f16): Likewise.
5086 (vcmulq_rot180_m_f32): Likewise.
5087 (vcmulq_rot180_m_f16): Likewise.
5088 (vcmulq_rot270_m_f32): Likewise.
5089 (vcmulq_rot270_m_f16): Likewise.
5090 (vcmulq_rot90_m_f32): Likewise.
5091 (vcmulq_rot90_m_f16): Likewise.
5092 (vcvtq_m_n_s32_f32): Likewise.
5093 (vcvtq_m_n_s16_f16): Likewise.
5094 (vcvtq_m_n_u32_f32): Likewise.
5095 (vcvtq_m_n_u16_f16): Likewise.
5096 (veorq_m_f32): Likewise.
5097 (veorq_m_f16): Likewise.
5098 (vfmaq_m_f32): Likewise.
5099 (vfmaq_m_f16): Likewise.
5100 (vfmaq_m_n_f32): Likewise.
5101 (vfmaq_m_n_f16): Likewise.
5102 (vfmasq_m_n_f32): Likewise.
5103 (vfmasq_m_n_f16): Likewise.
5104 (vfmsq_m_f32): Likewise.
5105 (vfmsq_m_f16): Likewise.
5106 (vmaxnmq_m_f32): Likewise.
5107 (vmaxnmq_m_f16): Likewise.
5108 (vminnmq_m_f32): Likewise.
5109 (vminnmq_m_f16): Likewise.
5110 (vmulq_m_f32): Likewise.
5111 (vmulq_m_f16): Likewise.
5112 (vmulq_m_n_f32): Likewise.
5113 (vmulq_m_n_f16): Likewise.
5114 (vornq_m_f32): Likewise.
5115 (vornq_m_f16): Likewise.
5116 (vorrq_m_f32): Likewise.
5117 (vorrq_m_f16): Likewise.
5118 (vsubq_m_f32): Likewise.
5119 (vsubq_m_f16): Likewise.
5120 (vsubq_m_n_f32): Likewise.
5121 (vsubq_m_n_f16): Likewise.
5122 (__attribute__): Likewise.
5123 (__arm_vabdq_m_f32): Likewise.
5124 (__arm_vabdq_m_f16): Likewise.
5125 (__arm_vaddq_m_f32): Likewise.
5126 (__arm_vaddq_m_f16): Likewise.
5127 (__arm_vaddq_m_n_f32): Likewise.
5128 (__arm_vaddq_m_n_f16): Likewise.
5129 (__arm_vandq_m_f32): Likewise.
5130 (__arm_vandq_m_f16): Likewise.
5131 (__arm_vbicq_m_f32): Likewise.
5132 (__arm_vbicq_m_f16): Likewise.
5133 (__arm_vbrsrq_m_n_f32): Likewise.
5134 (__arm_vbrsrq_m_n_f16): Likewise.
5135 (__arm_vcaddq_rot270_m_f32): Likewise.
5136 (__arm_vcaddq_rot270_m_f16): Likewise.
5137 (__arm_vcaddq_rot90_m_f32): Likewise.
5138 (__arm_vcaddq_rot90_m_f16): Likewise.
5139 (__arm_vcmlaq_m_f32): Likewise.
5140 (__arm_vcmlaq_m_f16): Likewise.
5141 (__arm_vcmlaq_rot180_m_f32): Likewise.
5142 (__arm_vcmlaq_rot180_m_f16): Likewise.
5143 (__arm_vcmlaq_rot270_m_f32): Likewise.
5144 (__arm_vcmlaq_rot270_m_f16): Likewise.
5145 (__arm_vcmlaq_rot90_m_f32): Likewise.
5146 (__arm_vcmlaq_rot90_m_f16): Likewise.
5147 (__arm_vcmulq_m_f32): Likewise.
5148 (__arm_vcmulq_m_f16): Likewise.
5149 (__arm_vcmulq_rot180_m_f32): Define intrinsic.
5150 (__arm_vcmulq_rot180_m_f16): Likewise.
5151 (__arm_vcmulq_rot270_m_f32): Likewise.
5152 (__arm_vcmulq_rot270_m_f16): Likewise.
5153 (__arm_vcmulq_rot90_m_f32): Likewise.
5154 (__arm_vcmulq_rot90_m_f16): Likewise.
5155 (__arm_vcvtq_m_n_s32_f32): Likewise.
5156 (__arm_vcvtq_m_n_s16_f16): Likewise.
5157 (__arm_vcvtq_m_n_u32_f32): Likewise.
5158 (__arm_vcvtq_m_n_u16_f16): Likewise.
5159 (__arm_veorq_m_f32): Likewise.
5160 (__arm_veorq_m_f16): Likewise.
5161 (__arm_vfmaq_m_f32): Likewise.
5162 (__arm_vfmaq_m_f16): Likewise.
5163 (__arm_vfmaq_m_n_f32): Likewise.
5164 (__arm_vfmaq_m_n_f16): Likewise.
5165 (__arm_vfmasq_m_n_f32): Likewise.
5166 (__arm_vfmasq_m_n_f16): Likewise.
5167 (__arm_vfmsq_m_f32): Likewise.
5168 (__arm_vfmsq_m_f16): Likewise.
5169 (__arm_vmaxnmq_m_f32): Likewise.
5170 (__arm_vmaxnmq_m_f16): Likewise.
5171 (__arm_vminnmq_m_f32): Likewise.
5172 (__arm_vminnmq_m_f16): Likewise.
5173 (__arm_vmulq_m_f32): Likewise.
5174 (__arm_vmulq_m_f16): Likewise.
5175 (__arm_vmulq_m_n_f32): Likewise.
5176 (__arm_vmulq_m_n_f16): Likewise.
5177 (__arm_vornq_m_f32): Likewise.
5178 (__arm_vornq_m_f16): Likewise.
5179 (__arm_vorrq_m_f32): Likewise.
5180 (__arm_vorrq_m_f16): Likewise.
5181 (__arm_vsubq_m_f32): Likewise.
5182 (__arm_vsubq_m_f16): Likewise.
5183 (__arm_vsubq_m_n_f32): Likewise.
5184 (__arm_vsubq_m_n_f16): Likewise.
5185 (vabdq_m): Define polymorphic variant.
5186 (vaddq_m): Likewise.
5187 (vaddq_m_n): Likewise.
5188 (vandq_m): Likewise.
5189 (vbicq_m): Likewise.
5190 (vbrsrq_m_n): Likewise.
5191 (vcaddq_rot270_m): Likewise.
5192 (vcaddq_rot90_m): Likewise.
5193 (vcmlaq_m): Likewise.
5194 (vcmlaq_rot180_m): Likewise.
5195 (vcmlaq_rot270_m): Likewise.
5196 (vcmlaq_rot90_m): Likewise.
5197 (vcmulq_m): Likewise.
5198 (vcmulq_rot180_m): Likewise.
5199 (vcmulq_rot270_m): Likewise.
5200 (vcmulq_rot90_m): Likewise.
5201 (veorq_m): Likewise.
5202 (vfmaq_m): Likewise.
5203 (vfmaq_m_n): Likewise.
5204 (vfmasq_m_n): Likewise.
5205 (vfmsq_m): Likewise.
5206 (vmaxnmq_m): Likewise.
5207 (vminnmq_m): Likewise.
5208 (vmulq_m): Likewise.
5209 (vmulq_m_n): Likewise.
5210 (vornq_m): Likewise.
5211 (vsubq_m): Likewise.
5212 (vsubq_m_n): Likewise.
5213 (vorrq_m): Likewise.
5214 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
5216 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
5217 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
5218 * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern.
5219 (mve_vaddq_m_f<mode>): Likewise.
5220 (mve_vaddq_m_n_f<mode>): Likewise.
5221 (mve_vandq_m_f<mode>): Likewise.
5222 (mve_vbicq_m_f<mode>): Likewise.
5223 (mve_vbrsrq_m_n_f<mode>): Likewise.
5224 (mve_vcaddq_rot270_m_f<mode>): Likewise.
5225 (mve_vcaddq_rot90_m_f<mode>): Likewise.
5226 (mve_vcmlaq_m_f<mode>): Likewise.
5227 (mve_vcmlaq_rot180_m_f<mode>): Likewise.
5228 (mve_vcmlaq_rot270_m_f<mode>): Likewise.
5229 (mve_vcmlaq_rot90_m_f<mode>): Likewise.
5230 (mve_vcmulq_m_f<mode>): Likewise.
5231 (mve_vcmulq_rot180_m_f<mode>): Likewise.
5232 (mve_vcmulq_rot270_m_f<mode>): Likewise.
5233 (mve_vcmulq_rot90_m_f<mode>): Likewise.
5234 (mve_veorq_m_f<mode>): Likewise.
5235 (mve_vfmaq_m_f<mode>): Likewise.
5236 (mve_vfmaq_m_n_f<mode>): Likewise.
5237 (mve_vfmasq_m_n_f<mode>): Likewise.
5238 (mve_vfmsq_m_f<mode>): Likewise.
5239 (mve_vmaxnmq_m_f<mode>): Likewise.
5240 (mve_vminnmq_m_f<mode>): Likewise.
5241 (mve_vmulq_m_f<mode>): Likewise.
5242 (mve_vmulq_m_n_f<mode>): Likewise.
5243 (mve_vornq_m_f<mode>): Likewise.
5244 (mve_vorrq_m_f<mode>): Likewise.
5245 (mve_vsubq_m_f<mode>): Likewise.
5246 (mve_vsubq_m_n_f<mode>): Likewise.
5248 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
5249 Mihail Ionescu <mihail.ionescu@arm.com>
5250 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5252 * config/arm/arm-protos.h (arm_mve_immediate_check):
5253 * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check
5254 mode and interger value.
5255 * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro.
5256 (vmlaldavaq_p_s16): Likewise.
5257 (vmlaldavaq_p_u32): Likewise.
5258 (vmlaldavaq_p_u16): Likewise.
5259 (vmlaldavaxq_p_s32): Likewise.
5260 (vmlaldavaxq_p_s16): Likewise.
5261 (vmlaldavaxq_p_u32): Likewise.
5262 (vmlaldavaxq_p_u16): Likewise.
5263 (vmlsldavaq_p_s32): Likewise.
5264 (vmlsldavaq_p_s16): Likewise.
5265 (vmlsldavaxq_p_s32): Likewise.
5266 (vmlsldavaxq_p_s16): Likewise.
5267 (vmullbq_poly_m_p8): Likewise.
5268 (vmullbq_poly_m_p16): Likewise.
5269 (vmulltq_poly_m_p8): Likewise.
5270 (vmulltq_poly_m_p16): Likewise.
5271 (vqdmullbq_m_n_s32): Likewise.
5272 (vqdmullbq_m_n_s16): Likewise.
5273 (vqdmullbq_m_s32): Likewise.
5274 (vqdmullbq_m_s16): Likewise.
5275 (vqdmulltq_m_n_s32): Likewise.
5276 (vqdmulltq_m_n_s16): Likewise.
5277 (vqdmulltq_m_s32): Likewise.
5278 (vqdmulltq_m_s16): Likewise.
5279 (vqrshrnbq_m_n_s32): Likewise.
5280 (vqrshrnbq_m_n_s16): Likewise.
5281 (vqrshrnbq_m_n_u32): Likewise.
5282 (vqrshrnbq_m_n_u16): Likewise.
5283 (vqrshrntq_m_n_s32): Likewise.
5284 (vqrshrntq_m_n_s16): Likewise.
5285 (vqrshrntq_m_n_u32): Likewise.
5286 (vqrshrntq_m_n_u16): Likewise.
5287 (vqrshrunbq_m_n_s32): Likewise.
5288 (vqrshrunbq_m_n_s16): Likewise.
5289 (vqrshruntq_m_n_s32): Likewise.
5290 (vqrshruntq_m_n_s16): Likewise.
5291 (vqshrnbq_m_n_s32): Likewise.
5292 (vqshrnbq_m_n_s16): Likewise.
5293 (vqshrnbq_m_n_u32): Likewise.
5294 (vqshrnbq_m_n_u16): Likewise.
5295 (vqshrntq_m_n_s32): Likewise.
5296 (vqshrntq_m_n_s16): Likewise.
5297 (vqshrntq_m_n_u32): Likewise.
5298 (vqshrntq_m_n_u16): Likewise.
5299 (vqshrunbq_m_n_s32): Likewise.
5300 (vqshrunbq_m_n_s16): Likewise.
5301 (vqshruntq_m_n_s32): Likewise.
5302 (vqshruntq_m_n_s16): Likewise.
5303 (vrmlaldavhaq_p_s32): Likewise.
5304 (vrmlaldavhaq_p_u32): Likewise.
5305 (vrmlaldavhaxq_p_s32): Likewise.
5306 (vrmlsldavhaq_p_s32): Likewise.
5307 (vrmlsldavhaxq_p_s32): Likewise.
5308 (vrshrnbq_m_n_s32): Likewise.
5309 (vrshrnbq_m_n_s16): Likewise.
5310 (vrshrnbq_m_n_u32): Likewise.
5311 (vrshrnbq_m_n_u16): Likewise.
5312 (vrshrntq_m_n_s32): Likewise.
5313 (vrshrntq_m_n_s16): Likewise.
5314 (vrshrntq_m_n_u32): Likewise.
5315 (vrshrntq_m_n_u16): Likewise.
5316 (vshllbq_m_n_s8): Likewise.
5317 (vshllbq_m_n_s16): Likewise.
5318 (vshllbq_m_n_u8): Likewise.
5319 (vshllbq_m_n_u16): Likewise.
5320 (vshlltq_m_n_s8): Likewise.
5321 (vshlltq_m_n_s16): Likewise.
5322 (vshlltq_m_n_u8): Likewise.
5323 (vshlltq_m_n_u16): Likewise.
5324 (vshrnbq_m_n_s32): Likewise.
5325 (vshrnbq_m_n_s16): Likewise.
5326 (vshrnbq_m_n_u32): Likewise.
5327 (vshrnbq_m_n_u16): Likewise.
5328 (vshrntq_m_n_s32): Likewise.
5329 (vshrntq_m_n_s16): Likewise.
5330 (vshrntq_m_n_u32): Likewise.
5331 (vshrntq_m_n_u16): Likewise.
5332 (__arm_vmlaldavaq_p_s32): Define intrinsic.
5333 (__arm_vmlaldavaq_p_s16): Likewise.
5334 (__arm_vmlaldavaq_p_u32): Likewise.
5335 (__arm_vmlaldavaq_p_u16): Likewise.
5336 (__arm_vmlaldavaxq_p_s32): Likewise.
5337 (__arm_vmlaldavaxq_p_s16): Likewise.
5338 (__arm_vmlaldavaxq_p_u32): Likewise.
5339 (__arm_vmlaldavaxq_p_u16): Likewise.
5340 (__arm_vmlsldavaq_p_s32): Likewise.
5341 (__arm_vmlsldavaq_p_s16): Likewise.
5342 (__arm_vmlsldavaxq_p_s32): Likewise.
5343 (__arm_vmlsldavaxq_p_s16): Likewise.
5344 (__arm_vmullbq_poly_m_p8): Likewise.
5345 (__arm_vmullbq_poly_m_p16): Likewise.
5346 (__arm_vmulltq_poly_m_p8): Likewise.
5347 (__arm_vmulltq_poly_m_p16): Likewise.
5348 (__arm_vqdmullbq_m_n_s32): Likewise.
5349 (__arm_vqdmullbq_m_n_s16): Likewise.
5350 (__arm_vqdmullbq_m_s32): Likewise.
5351 (__arm_vqdmullbq_m_s16): Likewise.
5352 (__arm_vqdmulltq_m_n_s32): Likewise.
5353 (__arm_vqdmulltq_m_n_s16): Likewise.
5354 (__arm_vqdmulltq_m_s32): Likewise.
5355 (__arm_vqdmulltq_m_s16): Likewise.
5356 (__arm_vqrshrnbq_m_n_s32): Likewise.
5357 (__arm_vqrshrnbq_m_n_s16): Likewise.
5358 (__arm_vqrshrnbq_m_n_u32): Likewise.
5359 (__arm_vqrshrnbq_m_n_u16): Likewise.
5360 (__arm_vqrshrntq_m_n_s32): Likewise.
5361 (__arm_vqrshrntq_m_n_s16): Likewise.
5362 (__arm_vqrshrntq_m_n_u32): Likewise.
5363 (__arm_vqrshrntq_m_n_u16): Likewise.
5364 (__arm_vqrshrunbq_m_n_s32): Likewise.
5365 (__arm_vqrshrunbq_m_n_s16): Likewise.
5366 (__arm_vqrshruntq_m_n_s32): Likewise.
5367 (__arm_vqrshruntq_m_n_s16): Likewise.
5368 (__arm_vqshrnbq_m_n_s32): Likewise.
5369 (__arm_vqshrnbq_m_n_s16): Likewise.
5370 (__arm_vqshrnbq_m_n_u32): Likewise.
5371 (__arm_vqshrnbq_m_n_u16): Likewise.
5372 (__arm_vqshrntq_m_n_s32): Likewise.
5373 (__arm_vqshrntq_m_n_s16): Likewise.
5374 (__arm_vqshrntq_m_n_u32): Likewise.
5375 (__arm_vqshrntq_m_n_u16): Likewise.
5376 (__arm_vqshrunbq_m_n_s32): Likewise.
5377 (__arm_vqshrunbq_m_n_s16): Likewise.
5378 (__arm_vqshruntq_m_n_s32): Likewise.
5379 (__arm_vqshruntq_m_n_s16): Likewise.
5380 (__arm_vrmlaldavhaq_p_s32): Likewise.
5381 (__arm_vrmlaldavhaq_p_u32): Likewise.
5382 (__arm_vrmlaldavhaxq_p_s32): Likewise.
5383 (__arm_vrmlsldavhaq_p_s32): Likewise.
5384 (__arm_vrmlsldavhaxq_p_s32): Likewise.
5385 (__arm_vrshrnbq_m_n_s32): Likewise.
5386 (__arm_vrshrnbq_m_n_s16): Likewise.
5387 (__arm_vrshrnbq_m_n_u32): Likewise.
5388 (__arm_vrshrnbq_m_n_u16): Likewise.
5389 (__arm_vrshrntq_m_n_s32): Likewise.
5390 (__arm_vrshrntq_m_n_s16): Likewise.
5391 (__arm_vrshrntq_m_n_u32): Likewise.
5392 (__arm_vrshrntq_m_n_u16): Likewise.
5393 (__arm_vshllbq_m_n_s8): Likewise.
5394 (__arm_vshllbq_m_n_s16): Likewise.
5395 (__arm_vshllbq_m_n_u8): Likewise.
5396 (__arm_vshllbq_m_n_u16): Likewise.
5397 (__arm_vshlltq_m_n_s8): Likewise.
5398 (__arm_vshlltq_m_n_s16): Likewise.
5399 (__arm_vshlltq_m_n_u8): Likewise.
5400 (__arm_vshlltq_m_n_u16): Likewise.
5401 (__arm_vshrnbq_m_n_s32): Likewise.
5402 (__arm_vshrnbq_m_n_s16): Likewise.
5403 (__arm_vshrnbq_m_n_u32): Likewise.
5404 (__arm_vshrnbq_m_n_u16): Likewise.
5405 (__arm_vshrntq_m_n_s32): Likewise.
5406 (__arm_vshrntq_m_n_s16): Likewise.
5407 (__arm_vshrntq_m_n_u32): Likewise.
5408 (__arm_vshrntq_m_n_u16): Likewise.
5409 (vmullbq_poly_m): Define polymorphic variant.
5410 (vmulltq_poly_m): Likewise.
5411 (vshllbq_m): Likewise.
5412 (vshrntq_m_n): Likewise.
5413 (vshrnbq_m_n): Likewise.
5414 (vshlltq_m_n): Likewise.
5415 (vshllbq_m_n): Likewise.
5416 (vrshrntq_m_n): Likewise.
5417 (vrshrnbq_m_n): Likewise.
5418 (vqshruntq_m_n): Likewise.
5419 (vqshrunbq_m_n): Likewise.
5420 (vqdmullbq_m_n): Likewise.
5421 (vqdmullbq_m): Likewise.
5422 (vqdmulltq_m_n): Likewise.
5423 (vqdmulltq_m): Likewise.
5424 (vqrshrnbq_m_n): Likewise.
5425 (vqrshrntq_m_n): Likewise.
5426 (vqrshrunbq_m_n): Likewise.
5427 (vqrshruntq_m_n): Likewise.
5428 (vqshrnbq_m_n): Likewise.
5429 (vqshrntq_m_n): Likewise.
5430 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
5432 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
5433 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
5434 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
5435 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
5436 * config/arm/mve.md (VMLALDAVAQ_P): Define iterator.
5437 (VMLALDAVAXQ_P): Likewise.
5438 (VQRSHRNBQ_M_N): Likewise.
5439 (VQRSHRNTQ_M_N): Likewise.
5440 (VQSHRNBQ_M_N): Likewise.
5441 (VQSHRNTQ_M_N): Likewise.
5442 (VRSHRNBQ_M_N): Likewise.
5443 (VRSHRNTQ_M_N): Likewise.
5444 (VSHLLBQ_M_N): Likewise.
5445 (VSHLLTQ_M_N): Likewise.
5446 (VSHRNBQ_M_N): Likewise.
5447 (VSHRNTQ_M_N): Likewise.
5448 (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern.
5449 (mve_vmlaldavaxq_p_<supf><mode>): Likewise.
5450 (mve_vqrshrnbq_m_n_<supf><mode>): Likewise.
5451 (mve_vqrshrntq_m_n_<supf><mode>): Likewise.
5452 (mve_vqshrnbq_m_n_<supf><mode>): Likewise.
5453 (mve_vqshrntq_m_n_<supf><mode>): Likewise.
5454 (mve_vrmlaldavhaq_p_sv4si): Likewise.
5455 (mve_vrshrnbq_m_n_<supf><mode>): Likewise.
5456 (mve_vrshrntq_m_n_<supf><mode>): Likewise.
5457 (mve_vshllbq_m_n_<supf><mode>): Likewise.
5458 (mve_vshlltq_m_n_<supf><mode>): Likewise.
5459 (mve_vshrnbq_m_n_<supf><mode>): Likewise.
5460 (mve_vshrntq_m_n_<supf><mode>): Likewise.
5461 (mve_vmlsldavaq_p_s<mode>): Likewise.
5462 (mve_vmlsldavaxq_p_s<mode>): Likewise.
5463 (mve_vmullbq_poly_m_p<mode>): Likewise.
5464 (mve_vmulltq_poly_m_p<mode>): Likewise.
5465 (mve_vqdmullbq_m_n_s<mode>): Likewise.
5466 (mve_vqdmullbq_m_s<mode>): Likewise.
5467 (mve_vqdmulltq_m_n_s<mode>): Likewise.
5468 (mve_vqdmulltq_m_s<mode>): Likewise.
5469 (mve_vqrshrunbq_m_n_s<mode>): Likewise.
5470 (mve_vqrshruntq_m_n_s<mode>): Likewise.
5471 (mve_vqshrunbq_m_n_s<mode>): Likewise.
5472 (mve_vqshruntq_m_n_s<mode>): Likewise.
5473 (mve_vrmlaldavhaq_p_uv4si): Likewise.
5474 (mve_vrmlaldavhaxq_p_sv4si): Likewise.
5475 (mve_vrmlsldavhaq_p_sv4si): Likewise.
5476 (mve_vrmlsldavhaxq_p_sv4si): Likewise.
5478 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
5479 Mihail Ionescu <mihail.ionescu@arm.com>
5480 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5482 * config/arm/arm_mve.h (vabdq_m_s8): Define macro.
5483 (vabdq_m_s32): Likewise.
5484 (vabdq_m_s16): Likewise.
5485 (vabdq_m_u8): Likewise.
5486 (vabdq_m_u32): Likewise.
5487 (vabdq_m_u16): Likewise.
5488 (vaddq_m_n_s8): Likewise.
5489 (vaddq_m_n_s32): Likewise.
5490 (vaddq_m_n_s16): Likewise.
5491 (vaddq_m_n_u8): Likewise.
5492 (vaddq_m_n_u32): Likewise.
5493 (vaddq_m_n_u16): Likewise.
5494 (vaddq_m_s8): Likewise.
5495 (vaddq_m_s32): Likewise.
5496 (vaddq_m_s16): Likewise.
5497 (vaddq_m_u8): Likewise.
5498 (vaddq_m_u32): Likewise.
5499 (vaddq_m_u16): Likewise.
5500 (vandq_m_s8): Likewise.
5501 (vandq_m_s32): Likewise.
5502 (vandq_m_s16): Likewise.
5503 (vandq_m_u8): Likewise.
5504 (vandq_m_u32): Likewise.
5505 (vandq_m_u16): Likewise.
5506 (vbicq_m_s8): Likewise.
5507 (vbicq_m_s32): Likewise.
5508 (vbicq_m_s16): Likewise.
5509 (vbicq_m_u8): Likewise.
5510 (vbicq_m_u32): Likewise.
5511 (vbicq_m_u16): Likewise.
5512 (vbrsrq_m_n_s8): Likewise.
5513 (vbrsrq_m_n_s32): Likewise.
5514 (vbrsrq_m_n_s16): Likewise.
5515 (vbrsrq_m_n_u8): Likewise.
5516 (vbrsrq_m_n_u32): Likewise.
5517 (vbrsrq_m_n_u16): Likewise.
5518 (vcaddq_rot270_m_s8): Likewise.
5519 (vcaddq_rot270_m_s32): Likewise.
5520 (vcaddq_rot270_m_s16): Likewise.
5521 (vcaddq_rot270_m_u8): Likewise.
5522 (vcaddq_rot270_m_u32): Likewise.
5523 (vcaddq_rot270_m_u16): Likewise.
5524 (vcaddq_rot90_m_s8): Likewise.
5525 (vcaddq_rot90_m_s32): Likewise.
5526 (vcaddq_rot90_m_s16): Likewise.
5527 (vcaddq_rot90_m_u8): Likewise.
5528 (vcaddq_rot90_m_u32): Likewise.
5529 (vcaddq_rot90_m_u16): Likewise.
5530 (veorq_m_s8): Likewise.
5531 (veorq_m_s32): Likewise.
5532 (veorq_m_s16): Likewise.
5533 (veorq_m_u8): Likewise.
5534 (veorq_m_u32): Likewise.
5535 (veorq_m_u16): Likewise.
5536 (vhaddq_m_n_s8): Likewise.
5537 (vhaddq_m_n_s32): Likewise.
5538 (vhaddq_m_n_s16): Likewise.
5539 (vhaddq_m_n_u8): Likewise.
5540 (vhaddq_m_n_u32): Likewise.
5541 (vhaddq_m_n_u16): Likewise.
5542 (vhaddq_m_s8): Likewise.
5543 (vhaddq_m_s32): Likewise.
5544 (vhaddq_m_s16): Likewise.
5545 (vhaddq_m_u8): Likewise.
5546 (vhaddq_m_u32): Likewise.
5547 (vhaddq_m_u16): Likewise.
5548 (vhcaddq_rot270_m_s8): Likewise.
5549 (vhcaddq_rot270_m_s32): Likewise.
5550 (vhcaddq_rot270_m_s16): Likewise.
5551 (vhcaddq_rot90_m_s8): Likewise.
5552 (vhcaddq_rot90_m_s32): Likewise.
5553 (vhcaddq_rot90_m_s16): Likewise.
5554 (vhsubq_m_n_s8): Likewise.
5555 (vhsubq_m_n_s32): Likewise.
5556 (vhsubq_m_n_s16): Likewise.
5557 (vhsubq_m_n_u8): Likewise.
5558 (vhsubq_m_n_u32): Likewise.
5559 (vhsubq_m_n_u16): Likewise.
5560 (vhsubq_m_s8): Likewise.
5561 (vhsubq_m_s32): Likewise.
5562 (vhsubq_m_s16): Likewise.
5563 (vhsubq_m_u8): Likewise.
5564 (vhsubq_m_u32): Likewise.
5565 (vhsubq_m_u16): Likewise.
5566 (vmaxq_m_s8): Likewise.
5567 (vmaxq_m_s32): Likewise.
5568 (vmaxq_m_s16): Likewise.
5569 (vmaxq_m_u8): Likewise.
5570 (vmaxq_m_u32): Likewise.
5571 (vmaxq_m_u16): Likewise.
5572 (vminq_m_s8): Likewise.
5573 (vminq_m_s32): Likewise.
5574 (vminq_m_s16): Likewise.
5575 (vminq_m_u8): Likewise.
5576 (vminq_m_u32): Likewise.
5577 (vminq_m_u16): Likewise.
5578 (vmladavaq_p_s8): Likewise.
5579 (vmladavaq_p_s32): Likewise.
5580 (vmladavaq_p_s16): Likewise.
5581 (vmladavaq_p_u8): Likewise.
5582 (vmladavaq_p_u32): Likewise.
5583 (vmladavaq_p_u16): Likewise.
5584 (vmladavaxq_p_s8): Likewise.
5585 (vmladavaxq_p_s32): Likewise.
5586 (vmladavaxq_p_s16): Likewise.
5587 (vmlaq_m_n_s8): Likewise.
5588 (vmlaq_m_n_s32): Likewise.
5589 (vmlaq_m_n_s16): Likewise.
5590 (vmlaq_m_n_u8): Likewise.
5591 (vmlaq_m_n_u32): Likewise.
5592 (vmlaq_m_n_u16): Likewise.
5593 (vmlasq_m_n_s8): Likewise.
5594 (vmlasq_m_n_s32): Likewise.
5595 (vmlasq_m_n_s16): Likewise.
5596 (vmlasq_m_n_u8): Likewise.
5597 (vmlasq_m_n_u32): Likewise.
5598 (vmlasq_m_n_u16): Likewise.
5599 (vmlsdavaq_p_s8): Likewise.
5600 (vmlsdavaq_p_s32): Likewise.
5601 (vmlsdavaq_p_s16): Likewise.
5602 (vmlsdavaxq_p_s8): Likewise.
5603 (vmlsdavaxq_p_s32): Likewise.
5604 (vmlsdavaxq_p_s16): Likewise.
5605 (vmulhq_m_s8): Likewise.
5606 (vmulhq_m_s32): Likewise.
5607 (vmulhq_m_s16): Likewise.
5608 (vmulhq_m_u8): Likewise.
5609 (vmulhq_m_u32): Likewise.
5610 (vmulhq_m_u16): Likewise.
5611 (vmullbq_int_m_s8): Likewise.
5612 (vmullbq_int_m_s32): Likewise.
5613 (vmullbq_int_m_s16): Likewise.
5614 (vmullbq_int_m_u8): Likewise.
5615 (vmullbq_int_m_u32): Likewise.
5616 (vmullbq_int_m_u16): Likewise.
5617 (vmulltq_int_m_s8): Likewise.
5618 (vmulltq_int_m_s32): Likewise.
5619 (vmulltq_int_m_s16): Likewise.
5620 (vmulltq_int_m_u8): Likewise.
5621 (vmulltq_int_m_u32): Likewise.
5622 (vmulltq_int_m_u16): Likewise.
5623 (vmulq_m_n_s8): Likewise.
5624 (vmulq_m_n_s32): Likewise.
5625 (vmulq_m_n_s16): Likewise.
5626 (vmulq_m_n_u8): Likewise.
5627 (vmulq_m_n_u32): Likewise.
5628 (vmulq_m_n_u16): Likewise.
5629 (vmulq_m_s8): Likewise.
5630 (vmulq_m_s32): Likewise.
5631 (vmulq_m_s16): Likewise.
5632 (vmulq_m_u8): Likewise.
5633 (vmulq_m_u32): Likewise.
5634 (vmulq_m_u16): Likewise.
5635 (vornq_m_s8): Likewise.
5636 (vornq_m_s32): Likewise.
5637 (vornq_m_s16): Likewise.
5638 (vornq_m_u8): Likewise.
5639 (vornq_m_u32): Likewise.
5640 (vornq_m_u16): Likewise.
5641 (vorrq_m_s8): Likewise.
5642 (vorrq_m_s32): Likewise.
5643 (vorrq_m_s16): Likewise.
5644 (vorrq_m_u8): Likewise.
5645 (vorrq_m_u32): Likewise.
5646 (vorrq_m_u16): Likewise.
5647 (vqaddq_m_n_s8): Likewise.
5648 (vqaddq_m_n_s32): Likewise.
5649 (vqaddq_m_n_s16): Likewise.
5650 (vqaddq_m_n_u8): Likewise.
5651 (vqaddq_m_n_u32): Likewise.
5652 (vqaddq_m_n_u16): Likewise.
5653 (vqaddq_m_s8): Likewise.
5654 (vqaddq_m_s32): Likewise.
5655 (vqaddq_m_s16): Likewise.
5656 (vqaddq_m_u8): Likewise.
5657 (vqaddq_m_u32): Likewise.
5658 (vqaddq_m_u16): Likewise.
5659 (vqdmladhq_m_s8): Likewise.
5660 (vqdmladhq_m_s32): Likewise.
5661 (vqdmladhq_m_s16): Likewise.
5662 (vqdmladhxq_m_s8): Likewise.
5663 (vqdmladhxq_m_s32): Likewise.
5664 (vqdmladhxq_m_s16): Likewise.
5665 (vqdmlahq_m_n_s8): Likewise.
5666 (vqdmlahq_m_n_s32): Likewise.
5667 (vqdmlahq_m_n_s16): Likewise.
5668 (vqdmlahq_m_n_u8): Likewise.
5669 (vqdmlahq_m_n_u32): Likewise.
5670 (vqdmlahq_m_n_u16): Likewise.
5671 (vqdmlsdhq_m_s8): Likewise.
5672 (vqdmlsdhq_m_s32): Likewise.
5673 (vqdmlsdhq_m_s16): Likewise.
5674 (vqdmlsdhxq_m_s8): Likewise.
5675 (vqdmlsdhxq_m_s32): Likewise.
5676 (vqdmlsdhxq_m_s16): Likewise.
5677 (vqdmulhq_m_n_s8): Likewise.
5678 (vqdmulhq_m_n_s32): Likewise.
5679 (vqdmulhq_m_n_s16): Likewise.
5680 (vqdmulhq_m_s8): Likewise.
5681 (vqdmulhq_m_s32): Likewise.
5682 (vqdmulhq_m_s16): Likewise.
5683 (vqrdmladhq_m_s8): Likewise.
5684 (vqrdmladhq_m_s32): Likewise.
5685 (vqrdmladhq_m_s16): Likewise.
5686 (vqrdmladhxq_m_s8): Likewise.
5687 (vqrdmladhxq_m_s32): Likewise.
5688 (vqrdmladhxq_m_s16): Likewise.
5689 (vqrdmlahq_m_n_s8): Likewise.
5690 (vqrdmlahq_m_n_s32): Likewise.
5691 (vqrdmlahq_m_n_s16): Likewise.
5692 (vqrdmlahq_m_n_u8): Likewise.
5693 (vqrdmlahq_m_n_u32): Likewise.
5694 (vqrdmlahq_m_n_u16): Likewise.
5695 (vqrdmlashq_m_n_s8): Likewise.
5696 (vqrdmlashq_m_n_s32): Likewise.
5697 (vqrdmlashq_m_n_s16): Likewise.
5698 (vqrdmlashq_m_n_u8): Likewise.
5699 (vqrdmlashq_m_n_u32): Likewise.
5700 (vqrdmlashq_m_n_u16): Likewise.
5701 (vqrdmlsdhq_m_s8): Likewise.
5702 (vqrdmlsdhq_m_s32): Likewise.
5703 (vqrdmlsdhq_m_s16): Likewise.
5704 (vqrdmlsdhxq_m_s8): Likewise.
5705 (vqrdmlsdhxq_m_s32): Likewise.
5706 (vqrdmlsdhxq_m_s16): Likewise.
5707 (vqrdmulhq_m_n_s8): Likewise.
5708 (vqrdmulhq_m_n_s32): Likewise.
5709 (vqrdmulhq_m_n_s16): Likewise.
5710 (vqrdmulhq_m_s8): Likewise.
5711 (vqrdmulhq_m_s32): Likewise.
5712 (vqrdmulhq_m_s16): Likewise.
5713 (vqrshlq_m_s8): Likewise.
5714 (vqrshlq_m_s32): Likewise.
5715 (vqrshlq_m_s16): Likewise.
5716 (vqrshlq_m_u8): Likewise.
5717 (vqrshlq_m_u32): Likewise.
5718 (vqrshlq_m_u16): Likewise.
5719 (vqshlq_m_n_s8): Likewise.
5720 (vqshlq_m_n_s32): Likewise.
5721 (vqshlq_m_n_s16): Likewise.
5722 (vqshlq_m_n_u8): Likewise.
5723 (vqshlq_m_n_u32): Likewise.
5724 (vqshlq_m_n_u16): Likewise.
5725 (vqshlq_m_s8): Likewise.
5726 (vqshlq_m_s32): Likewise.
5727 (vqshlq_m_s16): Likewise.
5728 (vqshlq_m_u8): Likewise.
5729 (vqshlq_m_u32): Likewise.
5730 (vqshlq_m_u16): Likewise.
5731 (vqsubq_m_n_s8): Likewise.
5732 (vqsubq_m_n_s32): Likewise.
5733 (vqsubq_m_n_s16): Likewise.
5734 (vqsubq_m_n_u8): Likewise.
5735 (vqsubq_m_n_u32): Likewise.
5736 (vqsubq_m_n_u16): Likewise.
5737 (vqsubq_m_s8): Likewise.
5738 (vqsubq_m_s32): Likewise.
5739 (vqsubq_m_s16): Likewise.
5740 (vqsubq_m_u8): Likewise.
5741 (vqsubq_m_u32): Likewise.
5742 (vqsubq_m_u16): Likewise.
5743 (vrhaddq_m_s8): Likewise.
5744 (vrhaddq_m_s32): Likewise.
5745 (vrhaddq_m_s16): Likewise.
5746 (vrhaddq_m_u8): Likewise.
5747 (vrhaddq_m_u32): Likewise.
5748 (vrhaddq_m_u16): Likewise.
5749 (vrmulhq_m_s8): Likewise.
5750 (vrmulhq_m_s32): Likewise.
5751 (vrmulhq_m_s16): Likewise.
5752 (vrmulhq_m_u8): Likewise.
5753 (vrmulhq_m_u32): Likewise.
5754 (vrmulhq_m_u16): Likewise.
5755 (vrshlq_m_s8): Likewise.
5756 (vrshlq_m_s32): Likewise.
5757 (vrshlq_m_s16): Likewise.
5758 (vrshlq_m_u8): Likewise.
5759 (vrshlq_m_u32): Likewise.
5760 (vrshlq_m_u16): Likewise.
5761 (vrshrq_m_n_s8): Likewise.
5762 (vrshrq_m_n_s32): Likewise.
5763 (vrshrq_m_n_s16): Likewise.
5764 (vrshrq_m_n_u8): Likewise.
5765 (vrshrq_m_n_u32): Likewise.
5766 (vrshrq_m_n_u16): Likewise.
5767 (vshlq_m_n_s8): Likewise.
5768 (vshlq_m_n_s32): Likewise.
5769 (vshlq_m_n_s16): Likewise.
5770 (vshlq_m_n_u8): Likewise.
5771 (vshlq_m_n_u32): Likewise.
5772 (vshlq_m_n_u16): Likewise.
5773 (vshrq_m_n_s8): Likewise.
5774 (vshrq_m_n_s32): Likewise.
5775 (vshrq_m_n_s16): Likewise.
5776 (vshrq_m_n_u8): Likewise.
5777 (vshrq_m_n_u32): Likewise.
5778 (vshrq_m_n_u16): Likewise.
5779 (vsliq_m_n_s8): Likewise.
5780 (vsliq_m_n_s32): Likewise.
5781 (vsliq_m_n_s16): Likewise.
5782 (vsliq_m_n_u8): Likewise.
5783 (vsliq_m_n_u32): Likewise.
5784 (vsliq_m_n_u16): Likewise.
5785 (vsubq_m_n_s8): Likewise.
5786 (vsubq_m_n_s32): Likewise.
5787 (vsubq_m_n_s16): Likewise.
5788 (vsubq_m_n_u8): Likewise.
5789 (vsubq_m_n_u32): Likewise.
5790 (vsubq_m_n_u16): Likewise.
5791 (__arm_vabdq_m_s8): Define intrinsic.
5792 (__arm_vabdq_m_s32): Likewise.
5793 (__arm_vabdq_m_s16): Likewise.
5794 (__arm_vabdq_m_u8): Likewise.
5795 (__arm_vabdq_m_u32): Likewise.
5796 (__arm_vabdq_m_u16): Likewise.
5797 (__arm_vaddq_m_n_s8): Likewise.
5798 (__arm_vaddq_m_n_s32): Likewise.
5799 (__arm_vaddq_m_n_s16): Likewise.
5800 (__arm_vaddq_m_n_u8): Likewise.
5801 (__arm_vaddq_m_n_u32): Likewise.
5802 (__arm_vaddq_m_n_u16): Likewise.
5803 (__arm_vaddq_m_s8): Likewise.
5804 (__arm_vaddq_m_s32): Likewise.
5805 (__arm_vaddq_m_s16): Likewise.
5806 (__arm_vaddq_m_u8): Likewise.
5807 (__arm_vaddq_m_u32): Likewise.
5808 (__arm_vaddq_m_u16): Likewise.
5809 (__arm_vandq_m_s8): Likewise.
5810 (__arm_vandq_m_s32): Likewise.
5811 (__arm_vandq_m_s16): Likewise.
5812 (__arm_vandq_m_u8): Likewise.
5813 (__arm_vandq_m_u32): Likewise.
5814 (__arm_vandq_m_u16): Likewise.
5815 (__arm_vbicq_m_s8): Likewise.
5816 (__arm_vbicq_m_s32): Likewise.
5817 (__arm_vbicq_m_s16): Likewise.
5818 (__arm_vbicq_m_u8): Likewise.
5819 (__arm_vbicq_m_u32): Likewise.
5820 (__arm_vbicq_m_u16): Likewise.
5821 (__arm_vbrsrq_m_n_s8): Likewise.
5822 (__arm_vbrsrq_m_n_s32): Likewise.
5823 (__arm_vbrsrq_m_n_s16): Likewise.
5824 (__arm_vbrsrq_m_n_u8): Likewise.
5825 (__arm_vbrsrq_m_n_u32): Likewise.
5826 (__arm_vbrsrq_m_n_u16): Likewise.
5827 (__arm_vcaddq_rot270_m_s8): Likewise.
5828 (__arm_vcaddq_rot270_m_s32): Likewise.
5829 (__arm_vcaddq_rot270_m_s16): Likewise.
5830 (__arm_vcaddq_rot270_m_u8): Likewise.
5831 (__arm_vcaddq_rot270_m_u32): Likewise.
5832 (__arm_vcaddq_rot270_m_u16): Likewise.
5833 (__arm_vcaddq_rot90_m_s8): Likewise.
5834 (__arm_vcaddq_rot90_m_s32): Likewise.
5835 (__arm_vcaddq_rot90_m_s16): Likewise.
5836 (__arm_vcaddq_rot90_m_u8): Likewise.
5837 (__arm_vcaddq_rot90_m_u32): Likewise.
5838 (__arm_vcaddq_rot90_m_u16): Likewise.
5839 (__arm_veorq_m_s8): Likewise.
5840 (__arm_veorq_m_s32): Likewise.
5841 (__arm_veorq_m_s16): Likewise.
5842 (__arm_veorq_m_u8): Likewise.
5843 (__arm_veorq_m_u32): Likewise.
5844 (__arm_veorq_m_u16): Likewise.
5845 (__arm_vhaddq_m_n_s8): Likewise.
5846 (__arm_vhaddq_m_n_s32): Likewise.
5847 (__arm_vhaddq_m_n_s16): Likewise.
5848 (__arm_vhaddq_m_n_u8): Likewise.
5849 (__arm_vhaddq_m_n_u32): Likewise.
5850 (__arm_vhaddq_m_n_u16): Likewise.
5851 (__arm_vhaddq_m_s8): Likewise.
5852 (__arm_vhaddq_m_s32): Likewise.
5853 (__arm_vhaddq_m_s16): Likewise.
5854 (__arm_vhaddq_m_u8): Likewise.
5855 (__arm_vhaddq_m_u32): Likewise.
5856 (__arm_vhaddq_m_u16): Likewise.
5857 (__arm_vhcaddq_rot270_m_s8): Likewise.
5858 (__arm_vhcaddq_rot270_m_s32): Likewise.
5859 (__arm_vhcaddq_rot270_m_s16): Likewise.
5860 (__arm_vhcaddq_rot90_m_s8): Likewise.
5861 (__arm_vhcaddq_rot90_m_s32): Likewise.
5862 (__arm_vhcaddq_rot90_m_s16): Likewise.
5863 (__arm_vhsubq_m_n_s8): Likewise.
5864 (__arm_vhsubq_m_n_s32): Likewise.
5865 (__arm_vhsubq_m_n_s16): Likewise.
5866 (__arm_vhsubq_m_n_u8): Likewise.
5867 (__arm_vhsubq_m_n_u32): Likewise.
5868 (__arm_vhsubq_m_n_u16): Likewise.
5869 (__arm_vhsubq_m_s8): Likewise.
5870 (__arm_vhsubq_m_s32): Likewise.
5871 (__arm_vhsubq_m_s16): Likewise.
5872 (__arm_vhsubq_m_u8): Likewise.
5873 (__arm_vhsubq_m_u32): Likewise.
5874 (__arm_vhsubq_m_u16): Likewise.
5875 (__arm_vmaxq_m_s8): Likewise.
5876 (__arm_vmaxq_m_s32): Likewise.
5877 (__arm_vmaxq_m_s16): Likewise.
5878 (__arm_vmaxq_m_u8): Likewise.
5879 (__arm_vmaxq_m_u32): Likewise.
5880 (__arm_vmaxq_m_u16): Likewise.
5881 (__arm_vminq_m_s8): Likewise.
5882 (__arm_vminq_m_s32): Likewise.
5883 (__arm_vminq_m_s16): Likewise.
5884 (__arm_vminq_m_u8): Likewise.
5885 (__arm_vminq_m_u32): Likewise.
5886 (__arm_vminq_m_u16): Likewise.
5887 (__arm_vmladavaq_p_s8): Likewise.
5888 (__arm_vmladavaq_p_s32): Likewise.
5889 (__arm_vmladavaq_p_s16): Likewise.
5890 (__arm_vmladavaq_p_u8): Likewise.
5891 (__arm_vmladavaq_p_u32): Likewise.
5892 (__arm_vmladavaq_p_u16): Likewise.
5893 (__arm_vmladavaxq_p_s8): Likewise.
5894 (__arm_vmladavaxq_p_s32): Likewise.
5895 (__arm_vmladavaxq_p_s16): Likewise.
5896 (__arm_vmlaq_m_n_s8): Likewise.
5897 (__arm_vmlaq_m_n_s32): Likewise.
5898 (__arm_vmlaq_m_n_s16): Likewise.
5899 (__arm_vmlaq_m_n_u8): Likewise.
5900 (__arm_vmlaq_m_n_u32): Likewise.
5901 (__arm_vmlaq_m_n_u16): Likewise.
5902 (__arm_vmlasq_m_n_s8): Likewise.
5903 (__arm_vmlasq_m_n_s32): Likewise.
5904 (__arm_vmlasq_m_n_s16): Likewise.
5905 (__arm_vmlasq_m_n_u8): Likewise.
5906 (__arm_vmlasq_m_n_u32): Likewise.
5907 (__arm_vmlasq_m_n_u16): Likewise.
5908 (__arm_vmlsdavaq_p_s8): Likewise.
5909 (__arm_vmlsdavaq_p_s32): Likewise.
5910 (__arm_vmlsdavaq_p_s16): Likewise.
5911 (__arm_vmlsdavaxq_p_s8): Likewise.
5912 (__arm_vmlsdavaxq_p_s32): Likewise.
5913 (__arm_vmlsdavaxq_p_s16): Likewise.
5914 (__arm_vmulhq_m_s8): Likewise.
5915 (__arm_vmulhq_m_s32): Likewise.
5916 (__arm_vmulhq_m_s16): Likewise.
5917 (__arm_vmulhq_m_u8): Likewise.
5918 (__arm_vmulhq_m_u32): Likewise.
5919 (__arm_vmulhq_m_u16): Likewise.
5920 (__arm_vmullbq_int_m_s8): Likewise.
5921 (__arm_vmullbq_int_m_s32): Likewise.
5922 (__arm_vmullbq_int_m_s16): Likewise.
5923 (__arm_vmullbq_int_m_u8): Likewise.
5924 (__arm_vmullbq_int_m_u32): Likewise.
5925 (__arm_vmullbq_int_m_u16): Likewise.
5926 (__arm_vmulltq_int_m_s8): Likewise.
5927 (__arm_vmulltq_int_m_s32): Likewise.
5928 (__arm_vmulltq_int_m_s16): Likewise.
5929 (__arm_vmulltq_int_m_u8): Likewise.
5930 (__arm_vmulltq_int_m_u32): Likewise.
5931 (__arm_vmulltq_int_m_u16): Likewise.
5932 (__arm_vmulq_m_n_s8): Likewise.
5933 (__arm_vmulq_m_n_s32): Likewise.
5934 (__arm_vmulq_m_n_s16): Likewise.
5935 (__arm_vmulq_m_n_u8): Likewise.
5936 (__arm_vmulq_m_n_u32): Likewise.
5937 (__arm_vmulq_m_n_u16): Likewise.
5938 (__arm_vmulq_m_s8): Likewise.
5939 (__arm_vmulq_m_s32): Likewise.
5940 (__arm_vmulq_m_s16): Likewise.
5941 (__arm_vmulq_m_u8): Likewise.
5942 (__arm_vmulq_m_u32): Likewise.
5943 (__arm_vmulq_m_u16): Likewise.
5944 (__arm_vornq_m_s8): Likewise.
5945 (__arm_vornq_m_s32): Likewise.
5946 (__arm_vornq_m_s16): Likewise.
5947 (__arm_vornq_m_u8): Likewise.
5948 (__arm_vornq_m_u32): Likewise.
5949 (__arm_vornq_m_u16): Likewise.
5950 (__arm_vorrq_m_s8): Likewise.
5951 (__arm_vorrq_m_s32): Likewise.
5952 (__arm_vorrq_m_s16): Likewise.
5953 (__arm_vorrq_m_u8): Likewise.
5954 (__arm_vorrq_m_u32): Likewise.
5955 (__arm_vorrq_m_u16): Likewise.
5956 (__arm_vqaddq_m_n_s8): Likewise.
5957 (__arm_vqaddq_m_n_s32): Likewise.
5958 (__arm_vqaddq_m_n_s16): Likewise.
5959 (__arm_vqaddq_m_n_u8): Likewise.
5960 (__arm_vqaddq_m_n_u32): Likewise.
5961 (__arm_vqaddq_m_n_u16): Likewise.
5962 (__arm_vqaddq_m_s8): Likewise.
5963 (__arm_vqaddq_m_s32): Likewise.
5964 (__arm_vqaddq_m_s16): Likewise.
5965 (__arm_vqaddq_m_u8): Likewise.
5966 (__arm_vqaddq_m_u32): Likewise.
5967 (__arm_vqaddq_m_u16): Likewise.
5968 (__arm_vqdmladhq_m_s8): Likewise.
5969 (__arm_vqdmladhq_m_s32): Likewise.
5970 (__arm_vqdmladhq_m_s16): Likewise.
5971 (__arm_vqdmladhxq_m_s8): Likewise.
5972 (__arm_vqdmladhxq_m_s32): Likewise.
5973 (__arm_vqdmladhxq_m_s16): Likewise.
5974 (__arm_vqdmlahq_m_n_s8): Likewise.
5975 (__arm_vqdmlahq_m_n_s32): Likewise.
5976 (__arm_vqdmlahq_m_n_s16): Likewise.
5977 (__arm_vqdmlahq_m_n_u8): Likewise.
5978 (__arm_vqdmlahq_m_n_u32): Likewise.
5979 (__arm_vqdmlahq_m_n_u16): Likewise.
5980 (__arm_vqdmlsdhq_m_s8): Likewise.
5981 (__arm_vqdmlsdhq_m_s32): Likewise.
5982 (__arm_vqdmlsdhq_m_s16): Likewise.
5983 (__arm_vqdmlsdhxq_m_s8): Likewise.
5984 (__arm_vqdmlsdhxq_m_s32): Likewise.
5985 (__arm_vqdmlsdhxq_m_s16): Likewise.
5986 (__arm_vqdmulhq_m_n_s8): Likewise.
5987 (__arm_vqdmulhq_m_n_s32): Likewise.
5988 (__arm_vqdmulhq_m_n_s16): Likewise.
5989 (__arm_vqdmulhq_m_s8): Likewise.
5990 (__arm_vqdmulhq_m_s32): Likewise.
5991 (__arm_vqdmulhq_m_s16): Likewise.
5992 (__arm_vqrdmladhq_m_s8): Likewise.
5993 (__arm_vqrdmladhq_m_s32): Likewise.
5994 (__arm_vqrdmladhq_m_s16): Likewise.
5995 (__arm_vqrdmladhxq_m_s8): Likewise.
5996 (__arm_vqrdmladhxq_m_s32): Likewise.
5997 (__arm_vqrdmladhxq_m_s16): Likewise.
5998 (__arm_vqrdmlahq_m_n_s8): Likewise.
5999 (__arm_vqrdmlahq_m_n_s32): Likewise.
6000 (__arm_vqrdmlahq_m_n_s16): Likewise.
6001 (__arm_vqrdmlahq_m_n_u8): Likewise.
6002 (__arm_vqrdmlahq_m_n_u32): Likewise.
6003 (__arm_vqrdmlahq_m_n_u16): Likewise.
6004 (__arm_vqrdmlashq_m_n_s8): Likewise.
6005 (__arm_vqrdmlashq_m_n_s32): Likewise.
6006 (__arm_vqrdmlashq_m_n_s16): Likewise.
6007 (__arm_vqrdmlashq_m_n_u8): Likewise.
6008 (__arm_vqrdmlashq_m_n_u32): Likewise.
6009 (__arm_vqrdmlashq_m_n_u16): Likewise.
6010 (__arm_vqrdmlsdhq_m_s8): Likewise.
6011 (__arm_vqrdmlsdhq_m_s32): Likewise.
6012 (__arm_vqrdmlsdhq_m_s16): Likewise.
6013 (__arm_vqrdmlsdhxq_m_s8): Likewise.
6014 (__arm_vqrdmlsdhxq_m_s32): Likewise.
6015 (__arm_vqrdmlsdhxq_m_s16): Likewise.
6016 (__arm_vqrdmulhq_m_n_s8): Likewise.
6017 (__arm_vqrdmulhq_m_n_s32): Likewise.
6018 (__arm_vqrdmulhq_m_n_s16): Likewise.
6019 (__arm_vqrdmulhq_m_s8): Likewise.
6020 (__arm_vqrdmulhq_m_s32): Likewise.
6021 (__arm_vqrdmulhq_m_s16): Likewise.
6022 (__arm_vqrshlq_m_s8): Likewise.
6023 (__arm_vqrshlq_m_s32): Likewise.
6024 (__arm_vqrshlq_m_s16): Likewise.
6025 (__arm_vqrshlq_m_u8): Likewise.
6026 (__arm_vqrshlq_m_u32): Likewise.
6027 (__arm_vqrshlq_m_u16): Likewise.
6028 (__arm_vqshlq_m_n_s8): Likewise.
6029 (__arm_vqshlq_m_n_s32): Likewise.
6030 (__arm_vqshlq_m_n_s16): Likewise.
6031 (__arm_vqshlq_m_n_u8): Likewise.
6032 (__arm_vqshlq_m_n_u32): Likewise.
6033 (__arm_vqshlq_m_n_u16): Likewise.
6034 (__arm_vqshlq_m_s8): Likewise.
6035 (__arm_vqshlq_m_s32): Likewise.
6036 (__arm_vqshlq_m_s16): Likewise.
6037 (__arm_vqshlq_m_u8): Likewise.
6038 (__arm_vqshlq_m_u32): Likewise.
6039 (__arm_vqshlq_m_u16): Likewise.
6040 (__arm_vqsubq_m_n_s8): Likewise.
6041 (__arm_vqsubq_m_n_s32): Likewise.
6042 (__arm_vqsubq_m_n_s16): Likewise.
6043 (__arm_vqsubq_m_n_u8): Likewise.
6044 (__arm_vqsubq_m_n_u32): Likewise.
6045 (__arm_vqsubq_m_n_u16): Likewise.
6046 (__arm_vqsubq_m_s8): Likewise.
6047 (__arm_vqsubq_m_s32): Likewise.
6048 (__arm_vqsubq_m_s16): Likewise.
6049 (__arm_vqsubq_m_u8): Likewise.
6050 (__arm_vqsubq_m_u32): Likewise.
6051 (__arm_vqsubq_m_u16): Likewise.
6052 (__arm_vrhaddq_m_s8): Likewise.
6053 (__arm_vrhaddq_m_s32): Likewise.
6054 (__arm_vrhaddq_m_s16): Likewise.
6055 (__arm_vrhaddq_m_u8): Likewise.
6056 (__arm_vrhaddq_m_u32): Likewise.
6057 (__arm_vrhaddq_m_u16): Likewise.
6058 (__arm_vrmulhq_m_s8): Likewise.
6059 (__arm_vrmulhq_m_s32): Likewise.
6060 (__arm_vrmulhq_m_s16): Likewise.
6061 (__arm_vrmulhq_m_u8): Likewise.
6062 (__arm_vrmulhq_m_u32): Likewise.
6063 (__arm_vrmulhq_m_u16): Likewise.
6064 (__arm_vrshlq_m_s8): Likewise.
6065 (__arm_vrshlq_m_s32): Likewise.
6066 (__arm_vrshlq_m_s16): Likewise.
6067 (__arm_vrshlq_m_u8): Likewise.
6068 (__arm_vrshlq_m_u32): Likewise.
6069 (__arm_vrshlq_m_u16): Likewise.
6070 (__arm_vrshrq_m_n_s8): Likewise.
6071 (__arm_vrshrq_m_n_s32): Likewise.
6072 (__arm_vrshrq_m_n_s16): Likewise.
6073 (__arm_vrshrq_m_n_u8): Likewise.
6074 (__arm_vrshrq_m_n_u32): Likewise.
6075 (__arm_vrshrq_m_n_u16): Likewise.
6076 (__arm_vshlq_m_n_s8): Likewise.
6077 (__arm_vshlq_m_n_s32): Likewise.
6078 (__arm_vshlq_m_n_s16): Likewise.
6079 (__arm_vshlq_m_n_u8): Likewise.
6080 (__arm_vshlq_m_n_u32): Likewise.
6081 (__arm_vshlq_m_n_u16): Likewise.
6082 (__arm_vshrq_m_n_s8): Likewise.
6083 (__arm_vshrq_m_n_s32): Likewise.
6084 (__arm_vshrq_m_n_s16): Likewise.
6085 (__arm_vshrq_m_n_u8): Likewise.
6086 (__arm_vshrq_m_n_u32): Likewise.
6087 (__arm_vshrq_m_n_u16): Likewise.
6088 (__arm_vsliq_m_n_s8): Likewise.
6089 (__arm_vsliq_m_n_s32): Likewise.
6090 (__arm_vsliq_m_n_s16): Likewise.
6091 (__arm_vsliq_m_n_u8): Likewise.
6092 (__arm_vsliq_m_n_u32): Likewise.
6093 (__arm_vsliq_m_n_u16): Likewise.
6094 (__arm_vsubq_m_n_s8): Likewise.
6095 (__arm_vsubq_m_n_s32): Likewise.
6096 (__arm_vsubq_m_n_s16): Likewise.
6097 (__arm_vsubq_m_n_u8): Likewise.
6098 (__arm_vsubq_m_n_u32): Likewise.
6099 (__arm_vsubq_m_n_u16): Likewise.
6100 (vqdmladhq_m): Define polymorphic variant.
6101 (vqdmladhxq_m): Likewise.
6102 (vqdmlsdhq_m): Likewise.
6103 (vqdmlsdhxq_m): Likewise.
6104 (vabdq_m): Likewise.
6105 (vandq_m): Likewise.
6106 (vbicq_m): Likewise.
6107 (vbrsrq_m_n): Likewise.
6108 (vcaddq_rot270_m): Likewise.
6109 (vcaddq_rot90_m): Likewise.
6110 (veorq_m): Likewise.
6111 (vmaxq_m): Likewise.
6112 (vminq_m): Likewise.
6113 (vmladavaq_p): Likewise.
6114 (vmlaq_m_n): Likewise.
6115 (vmlasq_m_n): Likewise.
6116 (vmulhq_m): Likewise.
6117 (vmullbq_int_m): Likewise.
6118 (vmulltq_int_m): Likewise.
6119 (vornq_m): Likewise.
6120 (vorrq_m): Likewise.
6121 (vqdmlahq_m_n): Likewise.
6122 (vqrdmlahq_m_n): Likewise.
6123 (vqrdmlashq_m_n): Likewise.
6124 (vqrshlq_m): Likewise.
6125 (vqshlq_m_n): Likewise.
6126 (vqshlq_m): Likewise.
6127 (vrhaddq_m): Likewise.
6128 (vrmulhq_m): Likewise.
6129 (vrshlq_m): Likewise.
6130 (vrshrq_m_n): Likewise.
6131 (vshlq_m_n): Likewise.
6132 (vshrq_m_n): Likewise.
6133 (vsliq_m): Likewise.
6134 (vaddq_m_n): Likewise.
6135 (vaddq_m): Likewise.
6136 (vhaddq_m_n): Likewise.
6137 (vhaddq_m): Likewise.
6138 (vhcaddq_rot270_m): Likewise.
6139 (vhcaddq_rot90_m): Likewise.
6140 (vhsubq_m): Likewise.
6141 (vhsubq_m_n): Likewise.
6142 (vmulq_m_n): Likewise.
6143 (vmulq_m): Likewise.
6144 (vqaddq_m_n): Likewise.
6145 (vqaddq_m): Likewise.
6146 (vqdmulhq_m_n): Likewise.
6147 (vqdmulhq_m): Likewise.
6148 (vsubq_m_n): Likewise.
6149 (vsliq_m_n): Likewise.
6150 (vqsubq_m_n): Likewise.
6151 (vqsubq_m): Likewise.
6152 (vqrdmulhq_m): Likewise.
6153 (vqrdmulhq_m_n): Likewise.
6154 (vqrdmlsdhxq_m): Likewise.
6155 (vqrdmlsdhq_m): Likewise.
6156 (vqrdmladhq_m): Likewise.
6157 (vqrdmladhxq_m): Likewise.
6158 (vmlsdavaxq_p): Likewise.
6159 (vmlsdavaq_p): Likewise.
6160 (vmladavaxq_p): Likewise.
6161 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
6163 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
6164 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
6165 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
6166 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
6167 * config/arm/mve.md (VHSUBQ_M): Define iterators.
6168 (VSLIQ_M_N): Likewise.
6169 (VQRDMLAHQ_M_N): Likewise.
6170 (VRSHLQ_M): Likewise.
6171 (VMINQ_M): Likewise.
6172 (VMULLBQ_INT_M): Likewise.
6173 (VMULHQ_M): Likewise.
6174 (VMULQ_M): Likewise.
6175 (VHSUBQ_M_N): Likewise.
6176 (VHADDQ_M_N): Likewise.
6177 (VORRQ_M): Likewise.
6178 (VRMULHQ_M): Likewise.
6179 (VQADDQ_M): Likewise.
6180 (VRSHRQ_M_N): Likewise.
6181 (VQSUBQ_M_N): Likewise.
6182 (VADDQ_M): Likewise.
6183 (VORNQ_M): Likewise.
6184 (VQDMLAHQ_M_N): Likewise.
6185 (VRHADDQ_M): Likewise.
6186 (VQSHLQ_M): Likewise.
6187 (VANDQ_M): Likewise.
6188 (VBICQ_M): Likewise.
6189 (VSHLQ_M_N): Likewise.
6190 (VCADDQ_ROT270_M): Likewise.
6191 (VQRSHLQ_M): Likewise.
6192 (VQADDQ_M_N): Likewise.
6193 (VADDQ_M_N): Likewise.
6194 (VMAXQ_M): Likewise.
6195 (VQSUBQ_M): Likewise.
6196 (VMLASQ_M_N): Likewise.
6197 (VMLADAVAQ_P): Likewise.
6198 (VBRSRQ_M_N): Likewise.
6199 (VMULQ_M_N): Likewise.
6200 (VCADDQ_ROT90_M): Likewise.
6201 (VMULLTQ_INT_M): Likewise.
6202 (VEORQ_M): Likewise.
6203 (VSHRQ_M_N): Likewise.
6204 (VSUBQ_M_N): Likewise.
6205 (VHADDQ_M): Likewise.
6206 (VABDQ_M): Likewise.
6207 (VQRDMLASHQ_M_N): Likewise.
6208 (VMLAQ_M_N): Likewise.
6209 (VQSHLQ_M_N): Likewise.
6210 (mve_vabdq_m_<supf><mode>): Define RTL pattern.
6211 (mve_vaddq_m_n_<supf><mode>): Likewise.
6212 (mve_vaddq_m_<supf><mode>): Likewise.
6213 (mve_vandq_m_<supf><mode>): Likewise.
6214 (mve_vbicq_m_<supf><mode>): Likewise.
6215 (mve_vbrsrq_m_n_<supf><mode>): Likewise.
6216 (mve_vcaddq_rot270_m_<supf><mode>): Likewise.
6217 (mve_vcaddq_rot90_m_<supf><mode>): Likewise.
6218 (mve_veorq_m_<supf><mode>): Likewise.
6219 (mve_vhaddq_m_n_<supf><mode>): Likewise.
6220 (mve_vhaddq_m_<supf><mode>): Likewise.
6221 (mve_vhsubq_m_n_<supf><mode>): Likewise.
6222 (mve_vhsubq_m_<supf><mode>): Likewise.
6223 (mve_vmaxq_m_<supf><mode>): Likewise.
6224 (mve_vminq_m_<supf><mode>): Likewise.
6225 (mve_vmladavaq_p_<supf><mode>): Likewise.
6226 (mve_vmlaq_m_n_<supf><mode>): Likewise.
6227 (mve_vmlasq_m_n_<supf><mode>): Likewise.
6228 (mve_vmulhq_m_<supf><mode>): Likewise.
6229 (mve_vmullbq_int_m_<supf><mode>): Likewise.
6230 (mve_vmulltq_int_m_<supf><mode>): Likewise.
6231 (mve_vmulq_m_n_<supf><mode>): Likewise.
6232 (mve_vmulq_m_<supf><mode>): Likewise.
6233 (mve_vornq_m_<supf><mode>): Likewise.
6234 (mve_vorrq_m_<supf><mode>): Likewise.
6235 (mve_vqaddq_m_n_<supf><mode>): Likewise.
6236 (mve_vqaddq_m_<supf><mode>): Likewise.
6237 (mve_vqdmlahq_m_n_<supf><mode>): Likewise.
6238 (mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
6239 (mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
6240 (mve_vqrshlq_m_<supf><mode>): Likewise.
6241 (mve_vqshlq_m_n_<supf><mode>): Likewise.
6242 (mve_vqshlq_m_<supf><mode>): Likewise.
6243 (mve_vqsubq_m_n_<supf><mode>): Likewise.
6244 (mve_vqsubq_m_<supf><mode>): Likewise.
6245 (mve_vrhaddq_m_<supf><mode>): Likewise.
6246 (mve_vrmulhq_m_<supf><mode>): Likewise.
6247 (mve_vrshlq_m_<supf><mode>): Likewise.
6248 (mve_vrshrq_m_n_<supf><mode>): Likewise.
6249 (mve_vshlq_m_n_<supf><mode>): Likewise.
6250 (mve_vshrq_m_n_<supf><mode>): Likewise.
6251 (mve_vsliq_m_n_<supf><mode>): Likewise.
6252 (mve_vsubq_m_n_<supf><mode>): Likewise.
6253 (mve_vhcaddq_rot270_m_s<mode>): Likewise.
6254 (mve_vhcaddq_rot90_m_s<mode>): Likewise.
6255 (mve_vmladavaxq_p_s<mode>): Likewise.
6256 (mve_vmlsdavaq_p_s<mode>): Likewise.
6257 (mve_vmlsdavaxq_p_s<mode>): Likewise.
6258 (mve_vqdmladhq_m_s<mode>): Likewise.
6259 (mve_vqdmladhxq_m_s<mode>): Likewise.
6260 (mve_vqdmlsdhq_m_s<mode>): Likewise.
6261 (mve_vqdmlsdhxq_m_s<mode>): Likewise.
6262 (mve_vqdmulhq_m_n_s<mode>): Likewise.
6263 (mve_vqdmulhq_m_s<mode>): Likewise.
6264 (mve_vqrdmladhq_m_s<mode>): Likewise.
6265 (mve_vqrdmladhxq_m_s<mode>): Likewise.
6266 (mve_vqrdmlsdhq_m_s<mode>): Likewise.
6267 (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
6268 (mve_vqrdmulhq_m_n_s<mode>): Likewise.
6269 (mve_vqrdmulhq_m_s<mode>): Likewise.
6271 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6272 Mihail Ionescu <mihail.ionescu@arm.com>
6273 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6275 * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS):
6276 Define builtin qualifier.
6277 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
6278 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
6279 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
6280 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
6281 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
6282 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
6283 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
6284 * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro.
6285 (vsubq_m_s8): Likewise.
6286 (vcvtq_m_n_f16_u16): Likewise.
6287 (vqshluq_m_n_s8): Likewise.
6288 (vabavq_p_s8): Likewise.
6289 (vsriq_m_n_u8): Likewise.
6290 (vshlq_m_u8): Likewise.
6291 (vsubq_m_u8): Likewise.
6292 (vabavq_p_u8): Likewise.
6293 (vshlq_m_s8): Likewise.
6294 (vcvtq_m_n_f16_s16): Likewise.
6295 (vsriq_m_n_s16): Likewise.
6296 (vsubq_m_s16): Likewise.
6297 (vcvtq_m_n_f32_u32): Likewise.
6298 (vqshluq_m_n_s16): Likewise.
6299 (vabavq_p_s16): Likewise.
6300 (vsriq_m_n_u16): Likewise.
6301 (vshlq_m_u16): Likewise.
6302 (vsubq_m_u16): Likewise.
6303 (vabavq_p_u16): Likewise.
6304 (vshlq_m_s16): Likewise.
6305 (vcvtq_m_n_f32_s32): Likewise.
6306 (vsriq_m_n_s32): Likewise.
6307 (vsubq_m_s32): Likewise.
6308 (vqshluq_m_n_s32): Likewise.
6309 (vabavq_p_s32): Likewise.
6310 (vsriq_m_n_u32): Likewise.
6311 (vshlq_m_u32): Likewise.
6312 (vsubq_m_u32): Likewise.
6313 (vabavq_p_u32): Likewise.
6314 (vshlq_m_s32): Likewise.
6315 (__arm_vsriq_m_n_s8): Define intrinsic.
6316 (__arm_vsubq_m_s8): Likewise.
6317 (__arm_vqshluq_m_n_s8): Likewise.
6318 (__arm_vabavq_p_s8): Likewise.
6319 (__arm_vsriq_m_n_u8): Likewise.
6320 (__arm_vshlq_m_u8): Likewise.
6321 (__arm_vsubq_m_u8): Likewise.
6322 (__arm_vabavq_p_u8): Likewise.
6323 (__arm_vshlq_m_s8): Likewise.
6324 (__arm_vsriq_m_n_s16): Likewise.
6325 (__arm_vsubq_m_s16): Likewise.
6326 (__arm_vqshluq_m_n_s16): Likewise.
6327 (__arm_vabavq_p_s16): Likewise.
6328 (__arm_vsriq_m_n_u16): Likewise.
6329 (__arm_vshlq_m_u16): Likewise.
6330 (__arm_vsubq_m_u16): Likewise.
6331 (__arm_vabavq_p_u16): Likewise.
6332 (__arm_vshlq_m_s16): Likewise.
6333 (__arm_vsriq_m_n_s32): Likewise.
6334 (__arm_vsubq_m_s32): Likewise.
6335 (__arm_vqshluq_m_n_s32): Likewise.
6336 (__arm_vabavq_p_s32): Likewise.
6337 (__arm_vsriq_m_n_u32): Likewise.
6338 (__arm_vshlq_m_u32): Likewise.
6339 (__arm_vsubq_m_u32): Likewise.
6340 (__arm_vabavq_p_u32): Likewise.
6341 (__arm_vshlq_m_s32): Likewise.
6342 (__arm_vcvtq_m_n_f16_u16): Likewise.
6343 (__arm_vcvtq_m_n_f16_s16): Likewise.
6344 (__arm_vcvtq_m_n_f32_u32): Likewise.
6345 (__arm_vcvtq_m_n_f32_s32): Likewise.
6346 (vcvtq_m_n): Define polymorphic variant.
6347 (vqshluq_m_n): Likewise.
6348 (vshlq_m): Likewise.
6349 (vsriq_m_n): Likewise.
6350 (vsubq_m): Likewise.
6351 (vabavq_p): Likewise.
6352 * config/arm/arm_mve_builtins.def
6353 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier.
6354 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
6355 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
6356 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
6357 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
6358 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
6359 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
6360 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
6361 * config/arm/mve.md (VABAVQ_P): Define iterator.
6362 (VSHLQ_M): Likewise.
6363 (VSRIQ_M_N): Likewise.
6364 (VSUBQ_M): Likewise.
6365 (VCVTQ_M_N_TO_F): Likewise.
6366 (mve_vabavq_p_<supf><mode>): Define RTL pattern.
6367 (mve_vqshluq_m_n_s<mode>): Likewise.
6368 (mve_vshlq_m_<supf><mode>): Likewise.
6369 (mve_vsriq_m_n_<supf><mode>): Likewise.
6370 (mve_vsubq_m_<supf><mode>): Likewise.
6371 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
6373 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6374 Mihail Ionescu <mihail.ionescu@arm.com>
6375 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6377 * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro.
6378 (vrmlsldavhaq_s32): Likewise.
6379 (vrmlsldavhaxq_s32): Likewise.
6380 (vaddlvaq_p_s32): Likewise.
6381 (vcvtbq_m_f16_f32): Likewise.
6382 (vcvtbq_m_f32_f16): Likewise.
6383 (vcvttq_m_f16_f32): Likewise.
6384 (vcvttq_m_f32_f16): Likewise.
6385 (vrev16q_m_s8): Likewise.
6386 (vrev32q_m_f16): Likewise.
6387 (vrmlaldavhq_p_s32): Likewise.
6388 (vrmlaldavhxq_p_s32): Likewise.
6389 (vrmlsldavhq_p_s32): Likewise.
6390 (vrmlsldavhxq_p_s32): Likewise.
6391 (vaddlvaq_p_u32): Likewise.
6392 (vrev16q_m_u8): Likewise.
6393 (vrmlaldavhq_p_u32): Likewise.
6394 (vmvnq_m_n_s16): Likewise.
6395 (vorrq_m_n_s16): Likewise.
6396 (vqrshrntq_n_s16): Likewise.
6397 (vqshrnbq_n_s16): Likewise.
6398 (vqshrntq_n_s16): Likewise.
6399 (vrshrnbq_n_s16): Likewise.
6400 (vrshrntq_n_s16): Likewise.
6401 (vshrnbq_n_s16): Likewise.
6402 (vshrntq_n_s16): Likewise.
6403 (vcmlaq_f16): Likewise.
6404 (vcmlaq_rot180_f16): Likewise.
6405 (vcmlaq_rot270_f16): Likewise.
6406 (vcmlaq_rot90_f16): Likewise.
6407 (vfmaq_f16): Likewise.
6408 (vfmaq_n_f16): Likewise.
6409 (vfmasq_n_f16): Likewise.
6410 (vfmsq_f16): Likewise.
6411 (vmlaldavaq_s16): Likewise.
6412 (vmlaldavaxq_s16): Likewise.
6413 (vmlsldavaq_s16): Likewise.
6414 (vmlsldavaxq_s16): Likewise.
6415 (vabsq_m_f16): Likewise.
6416 (vcvtmq_m_s16_f16): Likewise.
6417 (vcvtnq_m_s16_f16): Likewise.
6418 (vcvtpq_m_s16_f16): Likewise.
6419 (vcvtq_m_s16_f16): Likewise.
6420 (vdupq_m_n_f16): Likewise.
6421 (vmaxnmaq_m_f16): Likewise.
6422 (vmaxnmavq_p_f16): Likewise.
6423 (vmaxnmvq_p_f16): Likewise.
6424 (vminnmaq_m_f16): Likewise.
6425 (vminnmavq_p_f16): Likewise.
6426 (vminnmvq_p_f16): Likewise.
6427 (vmlaldavq_p_s16): Likewise.
6428 (vmlaldavxq_p_s16): Likewise.
6429 (vmlsldavq_p_s16): Likewise.
6430 (vmlsldavxq_p_s16): Likewise.
6431 (vmovlbq_m_s8): Likewise.
6432 (vmovltq_m_s8): Likewise.
6433 (vmovnbq_m_s16): Likewise.
6434 (vmovntq_m_s16): Likewise.
6435 (vnegq_m_f16): Likewise.
6436 (vpselq_f16): Likewise.
6437 (vqmovnbq_m_s16): Likewise.
6438 (vqmovntq_m_s16): Likewise.
6439 (vrev32q_m_s8): Likewise.
6440 (vrev64q_m_f16): Likewise.
6441 (vrndaq_m_f16): Likewise.
6442 (vrndmq_m_f16): Likewise.
6443 (vrndnq_m_f16): Likewise.
6444 (vrndpq_m_f16): Likewise.
6445 (vrndq_m_f16): Likewise.
6446 (vrndxq_m_f16): Likewise.
6447 (vcmpeqq_m_n_f16): Likewise.
6448 (vcmpgeq_m_f16): Likewise.
6449 (vcmpgeq_m_n_f16): Likewise.
6450 (vcmpgtq_m_f16): Likewise.
6451 (vcmpgtq_m_n_f16): Likewise.
6452 (vcmpleq_m_f16): Likewise.
6453 (vcmpleq_m_n_f16): Likewise.
6454 (vcmpltq_m_f16): Likewise.
6455 (vcmpltq_m_n_f16): Likewise.
6456 (vcmpneq_m_f16): Likewise.
6457 (vcmpneq_m_n_f16): Likewise.
6458 (vmvnq_m_n_u16): Likewise.
6459 (vorrq_m_n_u16): Likewise.
6460 (vqrshruntq_n_s16): Likewise.
6461 (vqshrunbq_n_s16): Likewise.
6462 (vqshruntq_n_s16): Likewise.
6463 (vcvtmq_m_u16_f16): Likewise.
6464 (vcvtnq_m_u16_f16): Likewise.
6465 (vcvtpq_m_u16_f16): Likewise.
6466 (vcvtq_m_u16_f16): Likewise.
6467 (vqmovunbq_m_s16): Likewise.
6468 (vqmovuntq_m_s16): Likewise.
6469 (vqrshrntq_n_u16): Likewise.
6470 (vqshrnbq_n_u16): Likewise.
6471 (vqshrntq_n_u16): Likewise.
6472 (vrshrnbq_n_u16): Likewise.
6473 (vrshrntq_n_u16): Likewise.
6474 (vshrnbq_n_u16): Likewise.
6475 (vshrntq_n_u16): Likewise.
6476 (vmlaldavaq_u16): Likewise.
6477 (vmlaldavaxq_u16): Likewise.
6478 (vmlaldavq_p_u16): Likewise.
6479 (vmlaldavxq_p_u16): Likewise.
6480 (vmovlbq_m_u8): Likewise.
6481 (vmovltq_m_u8): Likewise.
6482 (vmovnbq_m_u16): Likewise.
6483 (vmovntq_m_u16): Likewise.
6484 (vqmovnbq_m_u16): Likewise.
6485 (vqmovntq_m_u16): Likewise.
6486 (vrev32q_m_u8): Likewise.
6487 (vmvnq_m_n_s32): Likewise.
6488 (vorrq_m_n_s32): Likewise.
6489 (vqrshrntq_n_s32): Likewise.
6490 (vqshrnbq_n_s32): Likewise.
6491 (vqshrntq_n_s32): Likewise.
6492 (vrshrnbq_n_s32): Likewise.
6493 (vrshrntq_n_s32): Likewise.
6494 (vshrnbq_n_s32): Likewise.
6495 (vshrntq_n_s32): Likewise.
6496 (vcmlaq_f32): Likewise.
6497 (vcmlaq_rot180_f32): Likewise.
6498 (vcmlaq_rot270_f32): Likewise.
6499 (vcmlaq_rot90_f32): Likewise.
6500 (vfmaq_f32): Likewise.
6501 (vfmaq_n_f32): Likewise.
6502 (vfmasq_n_f32): Likewise.
6503 (vfmsq_f32): Likewise.
6504 (vmlaldavaq_s32): Likewise.
6505 (vmlaldavaxq_s32): Likewise.
6506 (vmlsldavaq_s32): Likewise.
6507 (vmlsldavaxq_s32): Likewise.
6508 (vabsq_m_f32): Likewise.
6509 (vcvtmq_m_s32_f32): Likewise.
6510 (vcvtnq_m_s32_f32): Likewise.
6511 (vcvtpq_m_s32_f32): Likewise.
6512 (vcvtq_m_s32_f32): Likewise.
6513 (vdupq_m_n_f32): Likewise.
6514 (vmaxnmaq_m_f32): Likewise.
6515 (vmaxnmavq_p_f32): Likewise.
6516 (vmaxnmvq_p_f32): Likewise.
6517 (vminnmaq_m_f32): Likewise.
6518 (vminnmavq_p_f32): Likewise.
6519 (vminnmvq_p_f32): Likewise.
6520 (vmlaldavq_p_s32): Likewise.
6521 (vmlaldavxq_p_s32): Likewise.
6522 (vmlsldavq_p_s32): Likewise.
6523 (vmlsldavxq_p_s32): Likewise.
6524 (vmovlbq_m_s16): Likewise.
6525 (vmovltq_m_s16): Likewise.
6526 (vmovnbq_m_s32): Likewise.
6527 (vmovntq_m_s32): Likewise.
6528 (vnegq_m_f32): Likewise.
6529 (vpselq_f32): Likewise.
6530 (vqmovnbq_m_s32): Likewise.
6531 (vqmovntq_m_s32): Likewise.
6532 (vrev32q_m_s16): Likewise.
6533 (vrev64q_m_f32): Likewise.
6534 (vrndaq_m_f32): Likewise.
6535 (vrndmq_m_f32): Likewise.
6536 (vrndnq_m_f32): Likewise.
6537 (vrndpq_m_f32): Likewise.
6538 (vrndq_m_f32): Likewise.
6539 (vrndxq_m_f32): Likewise.
6540 (vcmpeqq_m_n_f32): Likewise.
6541 (vcmpgeq_m_f32): Likewise.
6542 (vcmpgeq_m_n_f32): Likewise.
6543 (vcmpgtq_m_f32): Likewise.
6544 (vcmpgtq_m_n_f32): Likewise.
6545 (vcmpleq_m_f32): Likewise.
6546 (vcmpleq_m_n_f32): Likewise.
6547 (vcmpltq_m_f32): Likewise.
6548 (vcmpltq_m_n_f32): Likewise.
6549 (vcmpneq_m_f32): Likewise.
6550 (vcmpneq_m_n_f32): Likewise.
6551 (vmvnq_m_n_u32): Likewise.
6552 (vorrq_m_n_u32): Likewise.
6553 (vqrshruntq_n_s32): Likewise.
6554 (vqshrunbq_n_s32): Likewise.
6555 (vqshruntq_n_s32): Likewise.
6556 (vcvtmq_m_u32_f32): Likewise.
6557 (vcvtnq_m_u32_f32): Likewise.
6558 (vcvtpq_m_u32_f32): Likewise.
6559 (vcvtq_m_u32_f32): Likewise.
6560 (vqmovunbq_m_s32): Likewise.
6561 (vqmovuntq_m_s32): Likewise.
6562 (vqrshrntq_n_u32): Likewise.
6563 (vqshrnbq_n_u32): Likewise.
6564 (vqshrntq_n_u32): Likewise.
6565 (vrshrnbq_n_u32): Likewise.
6566 (vrshrntq_n_u32): Likewise.
6567 (vshrnbq_n_u32): Likewise.
6568 (vshrntq_n_u32): Likewise.
6569 (vmlaldavaq_u32): Likewise.
6570 (vmlaldavaxq_u32): Likewise.
6571 (vmlaldavq_p_u32): Likewise.
6572 (vmlaldavxq_p_u32): Likewise.
6573 (vmovlbq_m_u16): Likewise.
6574 (vmovltq_m_u16): Likewise.
6575 (vmovnbq_m_u32): Likewise.
6576 (vmovntq_m_u32): Likewise.
6577 (vqmovnbq_m_u32): Likewise.
6578 (vqmovntq_m_u32): Likewise.
6579 (vrev32q_m_u16): Likewise.
6580 (__arm_vrmlaldavhaxq_s32): Define intrinsic.
6581 (__arm_vrmlsldavhaq_s32): Likewise.
6582 (__arm_vrmlsldavhaxq_s32): Likewise.
6583 (__arm_vaddlvaq_p_s32): Likewise.
6584 (__arm_vrev16q_m_s8): Likewise.
6585 (__arm_vrmlaldavhq_p_s32): Likewise.
6586 (__arm_vrmlaldavhxq_p_s32): Likewise.
6587 (__arm_vrmlsldavhq_p_s32): Likewise.
6588 (__arm_vrmlsldavhxq_p_s32): Likewise.
6589 (__arm_vaddlvaq_p_u32): Likewise.
6590 (__arm_vrev16q_m_u8): Likewise.
6591 (__arm_vrmlaldavhq_p_u32): Likewise.
6592 (__arm_vmvnq_m_n_s16): Likewise.
6593 (__arm_vorrq_m_n_s16): Likewise.
6594 (__arm_vqrshrntq_n_s16): Likewise.
6595 (__arm_vqshrnbq_n_s16): Likewise.
6596 (__arm_vqshrntq_n_s16): Likewise.
6597 (__arm_vrshrnbq_n_s16): Likewise.
6598 (__arm_vrshrntq_n_s16): Likewise.
6599 (__arm_vshrnbq_n_s16): Likewise.
6600 (__arm_vshrntq_n_s16): Likewise.
6601 (__arm_vmlaldavaq_s16): Likewise.
6602 (__arm_vmlaldavaxq_s16): Likewise.
6603 (__arm_vmlsldavaq_s16): Likewise.
6604 (__arm_vmlsldavaxq_s16): Likewise.
6605 (__arm_vmlaldavq_p_s16): Likewise.
6606 (__arm_vmlaldavxq_p_s16): Likewise.
6607 (__arm_vmlsldavq_p_s16): Likewise.
6608 (__arm_vmlsldavxq_p_s16): Likewise.
6609 (__arm_vmovlbq_m_s8): Likewise.
6610 (__arm_vmovltq_m_s8): Likewise.
6611 (__arm_vmovnbq_m_s16): Likewise.
6612 (__arm_vmovntq_m_s16): Likewise.
6613 (__arm_vqmovnbq_m_s16): Likewise.
6614 (__arm_vqmovntq_m_s16): Likewise.
6615 (__arm_vrev32q_m_s8): Likewise.
6616 (__arm_vmvnq_m_n_u16): Likewise.
6617 (__arm_vorrq_m_n_u16): Likewise.
6618 (__arm_vqrshruntq_n_s16): Likewise.
6619 (__arm_vqshrunbq_n_s16): Likewise.
6620 (__arm_vqshruntq_n_s16): Likewise.
6621 (__arm_vqmovunbq_m_s16): Likewise.
6622 (__arm_vqmovuntq_m_s16): Likewise.
6623 (__arm_vqrshrntq_n_u16): Likewise.
6624 (__arm_vqshrnbq_n_u16): Likewise.
6625 (__arm_vqshrntq_n_u16): Likewise.
6626 (__arm_vrshrnbq_n_u16): Likewise.
6627 (__arm_vrshrntq_n_u16): Likewise.
6628 (__arm_vshrnbq_n_u16): Likewise.
6629 (__arm_vshrntq_n_u16): Likewise.
6630 (__arm_vmlaldavaq_u16): Likewise.
6631 (__arm_vmlaldavaxq_u16): Likewise.
6632 (__arm_vmlaldavq_p_u16): Likewise.
6633 (__arm_vmlaldavxq_p_u16): Likewise.
6634 (__arm_vmovlbq_m_u8): Likewise.
6635 (__arm_vmovltq_m_u8): Likewise.
6636 (__arm_vmovnbq_m_u16): Likewise.
6637 (__arm_vmovntq_m_u16): Likewise.
6638 (__arm_vqmovnbq_m_u16): Likewise.
6639 (__arm_vqmovntq_m_u16): Likewise.
6640 (__arm_vrev32q_m_u8): Likewise.
6641 (__arm_vmvnq_m_n_s32): Likewise.
6642 (__arm_vorrq_m_n_s32): Likewise.
6643 (__arm_vqrshrntq_n_s32): Likewise.
6644 (__arm_vqshrnbq_n_s32): Likewise.
6645 (__arm_vqshrntq_n_s32): Likewise.
6646 (__arm_vrshrnbq_n_s32): Likewise.
6647 (__arm_vrshrntq_n_s32): Likewise.
6648 (__arm_vshrnbq_n_s32): Likewise.
6649 (__arm_vshrntq_n_s32): Likewise.
6650 (__arm_vmlaldavaq_s32): Likewise.
6651 (__arm_vmlaldavaxq_s32): Likewise.
6652 (__arm_vmlsldavaq_s32): Likewise.
6653 (__arm_vmlsldavaxq_s32): Likewise.
6654 (__arm_vmlaldavq_p_s32): Likewise.
6655 (__arm_vmlaldavxq_p_s32): Likewise.
6656 (__arm_vmlsldavq_p_s32): Likewise.
6657 (__arm_vmlsldavxq_p_s32): Likewise.
6658 (__arm_vmovlbq_m_s16): Likewise.
6659 (__arm_vmovltq_m_s16): Likewise.
6660 (__arm_vmovnbq_m_s32): Likewise.
6661 (__arm_vmovntq_m_s32): Likewise.
6662 (__arm_vqmovnbq_m_s32): Likewise.
6663 (__arm_vqmovntq_m_s32): Likewise.
6664 (__arm_vrev32q_m_s16): Likewise.
6665 (__arm_vmvnq_m_n_u32): Likewise.
6666 (__arm_vorrq_m_n_u32): Likewise.
6667 (__arm_vqrshruntq_n_s32): Likewise.
6668 (__arm_vqshrunbq_n_s32): Likewise.
6669 (__arm_vqshruntq_n_s32): Likewise.
6670 (__arm_vqmovunbq_m_s32): Likewise.
6671 (__arm_vqmovuntq_m_s32): Likewise.
6672 (__arm_vqrshrntq_n_u32): Likewise.
6673 (__arm_vqshrnbq_n_u32): Likewise.
6674 (__arm_vqshrntq_n_u32): Likewise.
6675 (__arm_vrshrnbq_n_u32): Likewise.
6676 (__arm_vrshrntq_n_u32): Likewise.
6677 (__arm_vshrnbq_n_u32): Likewise.
6678 (__arm_vshrntq_n_u32): Likewise.
6679 (__arm_vmlaldavaq_u32): Likewise.
6680 (__arm_vmlaldavaxq_u32): Likewise.
6681 (__arm_vmlaldavq_p_u32): Likewise.
6682 (__arm_vmlaldavxq_p_u32): Likewise.
6683 (__arm_vmovlbq_m_u16): Likewise.
6684 (__arm_vmovltq_m_u16): Likewise.
6685 (__arm_vmovnbq_m_u32): Likewise.
6686 (__arm_vmovntq_m_u32): Likewise.
6687 (__arm_vqmovnbq_m_u32): Likewise.
6688 (__arm_vqmovntq_m_u32): Likewise.
6689 (__arm_vrev32q_m_u16): Likewise.
6690 (__arm_vcvtbq_m_f16_f32): Likewise.
6691 (__arm_vcvtbq_m_f32_f16): Likewise.
6692 (__arm_vcvttq_m_f16_f32): Likewise.
6693 (__arm_vcvttq_m_f32_f16): Likewise.
6694 (__arm_vrev32q_m_f16): Likewise.
6695 (__arm_vcmlaq_f16): Likewise.
6696 (__arm_vcmlaq_rot180_f16): Likewise.
6697 (__arm_vcmlaq_rot270_f16): Likewise.
6698 (__arm_vcmlaq_rot90_f16): Likewise.
6699 (__arm_vfmaq_f16): Likewise.
6700 (__arm_vfmaq_n_f16): Likewise.
6701 (__arm_vfmasq_n_f16): Likewise.
6702 (__arm_vfmsq_f16): Likewise.
6703 (__arm_vabsq_m_f16): Likewise.
6704 (__arm_vcvtmq_m_s16_f16): Likewise.
6705 (__arm_vcvtnq_m_s16_f16): Likewise.
6706 (__arm_vcvtpq_m_s16_f16): Likewise.
6707 (__arm_vcvtq_m_s16_f16): Likewise.
6708 (__arm_vdupq_m_n_f16): Likewise.
6709 (__arm_vmaxnmaq_m_f16): Likewise.
6710 (__arm_vmaxnmavq_p_f16): Likewise.
6711 (__arm_vmaxnmvq_p_f16): Likewise.
6712 (__arm_vminnmaq_m_f16): Likewise.
6713 (__arm_vminnmavq_p_f16): Likewise.
6714 (__arm_vminnmvq_p_f16): Likewise.
6715 (__arm_vnegq_m_f16): Likewise.
6716 (__arm_vpselq_f16): Likewise.
6717 (__arm_vrev64q_m_f16): Likewise.
6718 (__arm_vrndaq_m_f16): Likewise.
6719 (__arm_vrndmq_m_f16): Likewise.
6720 (__arm_vrndnq_m_f16): Likewise.
6721 (__arm_vrndpq_m_f16): Likewise.
6722 (__arm_vrndq_m_f16): Likewise.
6723 (__arm_vrndxq_m_f16): Likewise.
6724 (__arm_vcmpeqq_m_n_f16): Likewise.
6725 (__arm_vcmpgeq_m_f16): Likewise.
6726 (__arm_vcmpgeq_m_n_f16): Likewise.
6727 (__arm_vcmpgtq_m_f16): Likewise.
6728 (__arm_vcmpgtq_m_n_f16): Likewise.
6729 (__arm_vcmpleq_m_f16): Likewise.
6730 (__arm_vcmpleq_m_n_f16): Likewise.
6731 (__arm_vcmpltq_m_f16): Likewise.
6732 (__arm_vcmpltq_m_n_f16): Likewise.
6733 (__arm_vcmpneq_m_f16): Likewise.
6734 (__arm_vcmpneq_m_n_f16): Likewise.
6735 (__arm_vcvtmq_m_u16_f16): Likewise.
6736 (__arm_vcvtnq_m_u16_f16): Likewise.
6737 (__arm_vcvtpq_m_u16_f16): Likewise.
6738 (__arm_vcvtq_m_u16_f16): Likewise.
6739 (__arm_vcmlaq_f32): Likewise.
6740 (__arm_vcmlaq_rot180_f32): Likewise.
6741 (__arm_vcmlaq_rot270_f32): Likewise.
6742 (__arm_vcmlaq_rot90_f32): Likewise.
6743 (__arm_vfmaq_f32): Likewise.
6744 (__arm_vfmaq_n_f32): Likewise.
6745 (__arm_vfmasq_n_f32): Likewise.
6746 (__arm_vfmsq_f32): Likewise.
6747 (__arm_vabsq_m_f32): Likewise.
6748 (__arm_vcvtmq_m_s32_f32): Likewise.
6749 (__arm_vcvtnq_m_s32_f32): Likewise.
6750 (__arm_vcvtpq_m_s32_f32): Likewise.
6751 (__arm_vcvtq_m_s32_f32): Likewise.
6752 (__arm_vdupq_m_n_f32): Likewise.
6753 (__arm_vmaxnmaq_m_f32): Likewise.
6754 (__arm_vmaxnmavq_p_f32): Likewise.
6755 (__arm_vmaxnmvq_p_f32): Likewise.
6756 (__arm_vminnmaq_m_f32): Likewise.
6757 (__arm_vminnmavq_p_f32): Likewise.
6758 (__arm_vminnmvq_p_f32): Likewise.
6759 (__arm_vnegq_m_f32): Likewise.
6760 (__arm_vpselq_f32): Likewise.
6761 (__arm_vrev64q_m_f32): Likewise.
6762 (__arm_vrndaq_m_f32): Likewise.
6763 (__arm_vrndmq_m_f32): Likewise.
6764 (__arm_vrndnq_m_f32): Likewise.
6765 (__arm_vrndpq_m_f32): Likewise.
6766 (__arm_vrndq_m_f32): Likewise.
6767 (__arm_vrndxq_m_f32): Likewise.
6768 (__arm_vcmpeqq_m_n_f32): Likewise.
6769 (__arm_vcmpgeq_m_f32): Likewise.
6770 (__arm_vcmpgeq_m_n_f32): Likewise.
6771 (__arm_vcmpgtq_m_f32): Likewise.
6772 (__arm_vcmpgtq_m_n_f32): Likewise.
6773 (__arm_vcmpleq_m_f32): Likewise.
6774 (__arm_vcmpleq_m_n_f32): Likewise.
6775 (__arm_vcmpltq_m_f32): Likewise.
6776 (__arm_vcmpltq_m_n_f32): Likewise.
6777 (__arm_vcmpneq_m_f32): Likewise.
6778 (__arm_vcmpneq_m_n_f32): Likewise.
6779 (__arm_vcvtmq_m_u32_f32): Likewise.
6780 (__arm_vcvtnq_m_u32_f32): Likewise.
6781 (__arm_vcvtpq_m_u32_f32): Likewise.
6782 (__arm_vcvtq_m_u32_f32): Likewise.
6783 (vcvtq_m): Define polymorphic variant.
6784 (vabsq_m): Likewise.
6786 (vcmlaq_rot180): Likewise.
6787 (vcmlaq_rot270): Likewise.
6788 (vcmlaq_rot90): Likewise.
6789 (vcmpeqq_m_n): Likewise.
6790 (vcmpgeq_m_n): Likewise.
6791 (vrndxq_m): Likewise.
6792 (vrndq_m): Likewise.
6793 (vrndpq_m): Likewise.
6794 (vcmpgtq_m_n): Likewise.
6795 (vcmpgtq_m): Likewise.
6796 (vcmpleq_m): Likewise.
6797 (vcmpleq_m_n): Likewise.
6798 (vcmpltq_m_n): Likewise.
6799 (vcmpltq_m): Likewise.
6800 (vcmpneq_m): Likewise.
6801 (vcmpneq_m_n): Likewise.
6802 (vcvtbq_m): Likewise.
6803 (vcvttq_m): Likewise.
6804 (vcvtmq_m): Likewise.
6805 (vcvtnq_m): Likewise.
6806 (vcvtpq_m): Likewise.
6807 (vdupq_m_n): Likewise.
6808 (vfmaq_n): Likewise.
6810 (vfmasq_n): Likewise.
6812 (vmaxnmaq_m): Likewise.
6813 (vmaxnmavq_m): Likewise.
6814 (vmaxnmvq_m): Likewise.
6815 (vmaxnmavq_p): Likewise.
6816 (vmaxnmvq_p): Likewise.
6817 (vminnmaq_m): Likewise.
6818 (vminnmavq_p): Likewise.
6819 (vminnmvq_p): Likewise.
6820 (vrndnq_m): Likewise.
6821 (vrndaq_m): Likewise.
6822 (vrndmq_m): Likewise.
6823 (vrev64q_m): Likewise.
6824 (vrev32q_m): Likewise.
6826 (vnegq_m): Likewise.
6827 (vcmpgeq_m): Likewise.
6828 (vshrntq_n): Likewise.
6829 (vrshrntq_n): Likewise.
6830 (vmovlbq_m): Likewise.
6831 (vmovnbq_m): Likewise.
6832 (vmovntq_m): Likewise.
6833 (vmvnq_m_n): Likewise.
6834 (vmvnq_m): Likewise.
6835 (vshrnbq_n): Likewise.
6836 (vrshrnbq_n): Likewise.
6837 (vqshruntq_n): Likewise.
6838 (vrev16q_m): Likewise.
6839 (vqshrunbq_n): Likewise.
6840 (vqshrntq_n): Likewise.
6841 (vqrshruntq_n): Likewise.
6842 (vqrshrntq_n): Likewise.
6843 (vqshrnbq_n): Likewise.
6844 (vqmovuntq_m): Likewise.
6845 (vqmovntq_m): Likewise.
6846 (vqmovnbq_m): Likewise.
6847 (vorrq_m_n): Likewise.
6848 (vmovltq_m): Likewise.
6849 (vqmovunbq_m): Likewise.
6850 (vaddlvaq_p): Likewise.
6851 (vmlaldavaq): Likewise.
6852 (vmlaldavaxq): Likewise.
6853 (vmlaldavq_p): Likewise.
6854 (vmlaldavxq_p): Likewise.
6855 (vmlsldavaq): Likewise.
6856 (vmlsldavaxq): Likewise.
6857 (vmlsldavq_p): Likewise.
6858 (vmlsldavxq_p): Likewise.
6859 (vrmlaldavhaxq): Likewise.
6860 (vrmlaldavhq_p): Likewise.
6861 (vrmlaldavhxq_p): Likewise.
6862 (vrmlsldavhaq): Likewise.
6863 (vrmlsldavhaxq): Likewise.
6864 (vrmlsldavhq_p): Likewise.
6865 (vrmlsldavhxq_p): Likewise.
6866 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use
6868 (TERNOP_NONE_NONE_NONE_IMM): Likewise.
6869 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
6870 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
6871 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
6872 (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise.
6873 (TERNOP_UNONE_UNONE_NONE_IMM): Likewise.
6874 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
6875 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
6876 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
6877 * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator.
6878 (MVE_pred3): Likewise.
6879 (MVE_constraint1): Likewise.
6880 (MVE_pred1): Likewise.
6881 (VMLALDAVQ_P): Define iterator.
6882 (VQMOVNBQ_M): Likewise.
6883 (VMOVLTQ_M): Likewise.
6884 (VMOVNBQ_M): Likewise.
6885 (VRSHRNTQ_N): Likewise.
6886 (VORRQ_M_N): Likewise.
6887 (VREV32Q_M): Likewise.
6888 (VREV16Q_M): Likewise.
6889 (VQRSHRNTQ_N): Likewise.
6890 (VMOVNTQ_M): Likewise.
6891 (VMOVLBQ_M): Likewise.
6892 (VMLALDAVAQ): Likewise.
6893 (VQSHRNBQ_N): Likewise.
6894 (VSHRNBQ_N): Likewise.
6895 (VRSHRNBQ_N): Likewise.
6896 (VMLALDAVXQ_P): Likewise.
6897 (VQMOVNTQ_M): Likewise.
6898 (VMVNQ_M_N): Likewise.
6899 (VQSHRNTQ_N): Likewise.
6900 (VMLALDAVAXQ): Likewise.
6901 (VSHRNTQ_N): Likewise.
6902 (VCVTMQ_M): Likewise.
6903 (VCVTNQ_M): Likewise.
6904 (VCVTPQ_M): Likewise.
6905 (VCVTQ_M_N_FROM_F): Likewise.
6906 (VCVTQ_M_FROM_F): Likewise.
6907 (VRMLALDAVHQ_P): Likewise.
6908 (VADDLVAQ_P): Likewise.
6909 (mve_vrndq_m_f<mode>): Define RTL pattern.
6910 (mve_vabsq_m_f<mode>): Likewise.
6911 (mve_vaddlvaq_p_<supf>v4si): Likewise.
6912 (mve_vcmlaq_f<mode>): Likewise.
6913 (mve_vcmlaq_rot180_f<mode>): Likewise.
6914 (mve_vcmlaq_rot270_f<mode>): Likewise.
6915 (mve_vcmlaq_rot90_f<mode>): Likewise.
6916 (mve_vcmpeqq_m_n_f<mode>): Likewise.
6917 (mve_vcmpgeq_m_f<mode>): Likewise.
6918 (mve_vcmpgeq_m_n_f<mode>): Likewise.
6919 (mve_vcmpgtq_m_f<mode>): Likewise.
6920 (mve_vcmpgtq_m_n_f<mode>): Likewise.
6921 (mve_vcmpleq_m_f<mode>): Likewise.
6922 (mve_vcmpleq_m_n_f<mode>): Likewise.
6923 (mve_vcmpltq_m_f<mode>): Likewise.
6924 (mve_vcmpltq_m_n_f<mode>): Likewise.
6925 (mve_vcmpneq_m_f<mode>): Likewise.
6926 (mve_vcmpneq_m_n_f<mode>): Likewise.
6927 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
6928 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
6929 (mve_vcvttq_m_f16_f32v8hf): Likewise.
6930 (mve_vcvttq_m_f32_f16v4sf): Likewise.
6931 (mve_vdupq_m_n_f<mode>): Likewise.
6932 (mve_vfmaq_f<mode>): Likewise.
6933 (mve_vfmaq_n_f<mode>): Likewise.
6934 (mve_vfmasq_n_f<mode>): Likewise.
6935 (mve_vfmsq_f<mode>): Likewise.
6936 (mve_vmaxnmaq_m_f<mode>): Likewise.
6937 (mve_vmaxnmavq_p_f<mode>): Likewise.
6938 (mve_vmaxnmvq_p_f<mode>): Likewise.
6939 (mve_vminnmaq_m_f<mode>): Likewise.
6940 (mve_vminnmavq_p_f<mode>): Likewise.
6941 (mve_vminnmvq_p_f<mode>): Likewise.
6942 (mve_vmlaldavaq_<supf><mode>): Likewise.
6943 (mve_vmlaldavaxq_<supf><mode>): Likewise.
6944 (mve_vmlaldavq_p_<supf><mode>): Likewise.
6945 (mve_vmlaldavxq_p_<supf><mode>): Likewise.
6946 (mve_vmlsldavaq_s<mode>): Likewise.
6947 (mve_vmlsldavaxq_s<mode>): Likewise.
6948 (mve_vmlsldavq_p_s<mode>): Likewise.
6949 (mve_vmlsldavxq_p_s<mode>): Likewise.
6950 (mve_vmovlbq_m_<supf><mode>): Likewise.
6951 (mve_vmovltq_m_<supf><mode>): Likewise.
6952 (mve_vmovnbq_m_<supf><mode>): Likewise.
6953 (mve_vmovntq_m_<supf><mode>): Likewise.
6954 (mve_vmvnq_m_n_<supf><mode>): Likewise.
6955 (mve_vnegq_m_f<mode>): Likewise.
6956 (mve_vorrq_m_n_<supf><mode>): Likewise.
6957 (mve_vpselq_f<mode>): Likewise.
6958 (mve_vqmovnbq_m_<supf><mode>): Likewise.
6959 (mve_vqmovntq_m_<supf><mode>): Likewise.
6960 (mve_vqmovunbq_m_s<mode>): Likewise.
6961 (mve_vqmovuntq_m_s<mode>): Likewise.
6962 (mve_vqrshrntq_n_<supf><mode>): Likewise.
6963 (mve_vqrshruntq_n_s<mode>): Likewise.
6964 (mve_vqshrnbq_n_<supf><mode>): Likewise.
6965 (mve_vqshrntq_n_<supf><mode>): Likewise.
6966 (mve_vqshrunbq_n_s<mode>): Likewise.
6967 (mve_vqshruntq_n_s<mode>): Likewise.
6968 (mve_vrev32q_m_fv8hf): Likewise.
6969 (mve_vrev32q_m_<supf><mode>): Likewise.
6970 (mve_vrev64q_m_f<mode>): Likewise.
6971 (mve_vrmlaldavhaxq_sv4si): Likewise.
6972 (mve_vrmlaldavhxq_p_sv4si): Likewise.
6973 (mve_vrmlsldavhaxq_sv4si): Likewise.
6974 (mve_vrmlsldavhq_p_sv4si): Likewise.
6975 (mve_vrmlsldavhxq_p_sv4si): Likewise.
6976 (mve_vrndaq_m_f<mode>): Likewise.
6977 (mve_vrndmq_m_f<mode>): Likewise.
6978 (mve_vrndnq_m_f<mode>): Likewise.
6979 (mve_vrndpq_m_f<mode>): Likewise.
6980 (mve_vrndxq_m_f<mode>): Likewise.
6981 (mve_vrshrnbq_n_<supf><mode>): Likewise.
6982 (mve_vrshrntq_n_<supf><mode>): Likewise.
6983 (mve_vshrnbq_n_<supf><mode>): Likewise.
6984 (mve_vshrntq_n_<supf><mode>): Likewise.
6985 (mve_vcvtmq_m_<supf><mode>): Likewise.
6986 (mve_vcvtpq_m_<supf><mode>): Likewise.
6987 (mve_vcvtnq_m_<supf><mode>): Likewise.
6988 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
6989 (mve_vrev16q_m_<supf>v16qi): Likewise.
6990 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
6991 (mve_vrmlaldavhq_p_<supf>v4si): Likewise.
6992 (mve_vrmlsldavhaq_sv4si): Likewise.
6994 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6995 Mihail Ionescu <mihail.ionescu@arm.com>
6996 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6998 * config/arm/arm_mve.h (vpselq_u8): Define macro.
6999 (vpselq_s8): Likewise.
7000 (vrev64q_m_u8): Likewise.
7001 (vqrdmlashq_n_u8): Likewise.
7002 (vqrdmlahq_n_u8): Likewise.
7003 (vqdmlahq_n_u8): Likewise.
7004 (vmvnq_m_u8): Likewise.
7005 (vmlasq_n_u8): Likewise.
7006 (vmlaq_n_u8): Likewise.
7007 (vmladavq_p_u8): Likewise.
7008 (vmladavaq_u8): Likewise.
7009 (vminvq_p_u8): Likewise.
7010 (vmaxvq_p_u8): Likewise.
7011 (vdupq_m_n_u8): Likewise.
7012 (vcmpneq_m_u8): Likewise.
7013 (vcmpneq_m_n_u8): Likewise.
7014 (vcmphiq_m_u8): Likewise.
7015 (vcmphiq_m_n_u8): Likewise.
7016 (vcmpeqq_m_u8): Likewise.
7017 (vcmpeqq_m_n_u8): Likewise.
7018 (vcmpcsq_m_u8): Likewise.
7019 (vcmpcsq_m_n_u8): Likewise.
7020 (vclzq_m_u8): Likewise.
7021 (vaddvaq_p_u8): Likewise.
7022 (vsriq_n_u8): Likewise.
7023 (vsliq_n_u8): Likewise.
7024 (vshlq_m_r_u8): Likewise.
7025 (vrshlq_m_n_u8): Likewise.
7026 (vqshlq_m_r_u8): Likewise.
7027 (vqrshlq_m_n_u8): Likewise.
7028 (vminavq_p_s8): Likewise.
7029 (vminaq_m_s8): Likewise.
7030 (vmaxavq_p_s8): Likewise.
7031 (vmaxaq_m_s8): Likewise.
7032 (vcmpneq_m_s8): Likewise.
7033 (vcmpneq_m_n_s8): Likewise.
7034 (vcmpltq_m_s8): Likewise.
7035 (vcmpltq_m_n_s8): Likewise.
7036 (vcmpleq_m_s8): Likewise.
7037 (vcmpleq_m_n_s8): Likewise.
7038 (vcmpgtq_m_s8): Likewise.
7039 (vcmpgtq_m_n_s8): Likewise.
7040 (vcmpgeq_m_s8): Likewise.
7041 (vcmpgeq_m_n_s8): Likewise.
7042 (vcmpeqq_m_s8): Likewise.
7043 (vcmpeqq_m_n_s8): Likewise.
7044 (vshlq_m_r_s8): Likewise.
7045 (vrshlq_m_n_s8): Likewise.
7046 (vrev64q_m_s8): Likewise.
7047 (vqshlq_m_r_s8): Likewise.
7048 (vqrshlq_m_n_s8): Likewise.
7049 (vqnegq_m_s8): Likewise.
7050 (vqabsq_m_s8): Likewise.
7051 (vnegq_m_s8): Likewise.
7052 (vmvnq_m_s8): Likewise.
7053 (vmlsdavxq_p_s8): Likewise.
7054 (vmlsdavq_p_s8): Likewise.
7055 (vmladavxq_p_s8): Likewise.
7056 (vmladavq_p_s8): Likewise.
7057 (vminvq_p_s8): Likewise.
7058 (vmaxvq_p_s8): Likewise.
7059 (vdupq_m_n_s8): Likewise.
7060 (vclzq_m_s8): Likewise.
7061 (vclsq_m_s8): Likewise.
7062 (vaddvaq_p_s8): Likewise.
7063 (vabsq_m_s8): Likewise.
7064 (vqrdmlsdhxq_s8): Likewise.
7065 (vqrdmlsdhq_s8): Likewise.
7066 (vqrdmlashq_n_s8): Likewise.
7067 (vqrdmlahq_n_s8): Likewise.
7068 (vqrdmladhxq_s8): Likewise.
7069 (vqrdmladhq_s8): Likewise.
7070 (vqdmlsdhxq_s8): Likewise.
7071 (vqdmlsdhq_s8): Likewise.
7072 (vqdmlahq_n_s8): Likewise.
7073 (vqdmladhxq_s8): Likewise.
7074 (vqdmladhq_s8): Likewise.
7075 (vmlsdavaxq_s8): Likewise.
7076 (vmlsdavaq_s8): Likewise.
7077 (vmlasq_n_s8): Likewise.
7078 (vmlaq_n_s8): Likewise.
7079 (vmladavaxq_s8): Likewise.
7080 (vmladavaq_s8): Likewise.
7081 (vsriq_n_s8): Likewise.
7082 (vsliq_n_s8): Likewise.
7083 (vpselq_u16): Likewise.
7084 (vpselq_s16): Likewise.
7085 (vrev64q_m_u16): Likewise.
7086 (vqrdmlashq_n_u16): Likewise.
7087 (vqrdmlahq_n_u16): Likewise.
7088 (vqdmlahq_n_u16): Likewise.
7089 (vmvnq_m_u16): Likewise.
7090 (vmlasq_n_u16): Likewise.
7091 (vmlaq_n_u16): Likewise.
7092 (vmladavq_p_u16): Likewise.
7093 (vmladavaq_u16): Likewise.
7094 (vminvq_p_u16): Likewise.
7095 (vmaxvq_p_u16): Likewise.
7096 (vdupq_m_n_u16): Likewise.
7097 (vcmpneq_m_u16): Likewise.
7098 (vcmpneq_m_n_u16): Likewise.
7099 (vcmphiq_m_u16): Likewise.
7100 (vcmphiq_m_n_u16): Likewise.
7101 (vcmpeqq_m_u16): Likewise.
7102 (vcmpeqq_m_n_u16): Likewise.
7103 (vcmpcsq_m_u16): Likewise.
7104 (vcmpcsq_m_n_u16): Likewise.
7105 (vclzq_m_u16): Likewise.
7106 (vaddvaq_p_u16): Likewise.
7107 (vsriq_n_u16): Likewise.
7108 (vsliq_n_u16): Likewise.
7109 (vshlq_m_r_u16): Likewise.
7110 (vrshlq_m_n_u16): Likewise.
7111 (vqshlq_m_r_u16): Likewise.
7112 (vqrshlq_m_n_u16): Likewise.
7113 (vminavq_p_s16): Likewise.
7114 (vminaq_m_s16): Likewise.
7115 (vmaxavq_p_s16): Likewise.
7116 (vmaxaq_m_s16): Likewise.
7117 (vcmpneq_m_s16): Likewise.
7118 (vcmpneq_m_n_s16): Likewise.
7119 (vcmpltq_m_s16): Likewise.
7120 (vcmpltq_m_n_s16): Likewise.
7121 (vcmpleq_m_s16): Likewise.
7122 (vcmpleq_m_n_s16): Likewise.
7123 (vcmpgtq_m_s16): Likewise.
7124 (vcmpgtq_m_n_s16): Likewise.
7125 (vcmpgeq_m_s16): Likewise.
7126 (vcmpgeq_m_n_s16): Likewise.
7127 (vcmpeqq_m_s16): Likewise.
7128 (vcmpeqq_m_n_s16): Likewise.
7129 (vshlq_m_r_s16): Likewise.
7130 (vrshlq_m_n_s16): Likewise.
7131 (vrev64q_m_s16): Likewise.
7132 (vqshlq_m_r_s16): Likewise.
7133 (vqrshlq_m_n_s16): Likewise.
7134 (vqnegq_m_s16): Likewise.
7135 (vqabsq_m_s16): Likewise.
7136 (vnegq_m_s16): Likewise.
7137 (vmvnq_m_s16): Likewise.
7138 (vmlsdavxq_p_s16): Likewise.
7139 (vmlsdavq_p_s16): Likewise.
7140 (vmladavxq_p_s16): Likewise.
7141 (vmladavq_p_s16): Likewise.
7142 (vminvq_p_s16): Likewise.
7143 (vmaxvq_p_s16): Likewise.
7144 (vdupq_m_n_s16): Likewise.
7145 (vclzq_m_s16): Likewise.
7146 (vclsq_m_s16): Likewise.
7147 (vaddvaq_p_s16): Likewise.
7148 (vabsq_m_s16): Likewise.
7149 (vqrdmlsdhxq_s16): Likewise.
7150 (vqrdmlsdhq_s16): Likewise.
7151 (vqrdmlashq_n_s16): Likewise.
7152 (vqrdmlahq_n_s16): Likewise.
7153 (vqrdmladhxq_s16): Likewise.
7154 (vqrdmladhq_s16): Likewise.
7155 (vqdmlsdhxq_s16): Likewise.
7156 (vqdmlsdhq_s16): Likewise.
7157 (vqdmlahq_n_s16): Likewise.
7158 (vqdmladhxq_s16): Likewise.
7159 (vqdmladhq_s16): Likewise.
7160 (vmlsdavaxq_s16): Likewise.
7161 (vmlsdavaq_s16): Likewise.
7162 (vmlasq_n_s16): Likewise.
7163 (vmlaq_n_s16): Likewise.
7164 (vmladavaxq_s16): Likewise.
7165 (vmladavaq_s16): Likewise.
7166 (vsriq_n_s16): Likewise.
7167 (vsliq_n_s16): Likewise.
7168 (vpselq_u32): Likewise.
7169 (vpselq_s32): Likewise.
7170 (vrev64q_m_u32): Likewise.
7171 (vqrdmlashq_n_u32): Likewise.
7172 (vqrdmlahq_n_u32): Likewise.
7173 (vqdmlahq_n_u32): Likewise.
7174 (vmvnq_m_u32): Likewise.
7175 (vmlasq_n_u32): Likewise.
7176 (vmlaq_n_u32): Likewise.
7177 (vmladavq_p_u32): Likewise.
7178 (vmladavaq_u32): Likewise.
7179 (vminvq_p_u32): Likewise.
7180 (vmaxvq_p_u32): Likewise.
7181 (vdupq_m_n_u32): Likewise.
7182 (vcmpneq_m_u32): Likewise.
7183 (vcmpneq_m_n_u32): Likewise.
7184 (vcmphiq_m_u32): Likewise.
7185 (vcmphiq_m_n_u32): Likewise.
7186 (vcmpeqq_m_u32): Likewise.
7187 (vcmpeqq_m_n_u32): Likewise.
7188 (vcmpcsq_m_u32): Likewise.
7189 (vcmpcsq_m_n_u32): Likewise.
7190 (vclzq_m_u32): Likewise.
7191 (vaddvaq_p_u32): Likewise.
7192 (vsriq_n_u32): Likewise.
7193 (vsliq_n_u32): Likewise.
7194 (vshlq_m_r_u32): Likewise.
7195 (vrshlq_m_n_u32): Likewise.
7196 (vqshlq_m_r_u32): Likewise.
7197 (vqrshlq_m_n_u32): Likewise.
7198 (vminavq_p_s32): Likewise.
7199 (vminaq_m_s32): Likewise.
7200 (vmaxavq_p_s32): Likewise.
7201 (vmaxaq_m_s32): Likewise.
7202 (vcmpneq_m_s32): Likewise.
7203 (vcmpneq_m_n_s32): Likewise.
7204 (vcmpltq_m_s32): Likewise.
7205 (vcmpltq_m_n_s32): Likewise.
7206 (vcmpleq_m_s32): Likewise.
7207 (vcmpleq_m_n_s32): Likewise.
7208 (vcmpgtq_m_s32): Likewise.
7209 (vcmpgtq_m_n_s32): Likewise.
7210 (vcmpgeq_m_s32): Likewise.
7211 (vcmpgeq_m_n_s32): Likewise.
7212 (vcmpeqq_m_s32): Likewise.
7213 (vcmpeqq_m_n_s32): Likewise.
7214 (vshlq_m_r_s32): Likewise.
7215 (vrshlq_m_n_s32): Likewise.
7216 (vrev64q_m_s32): Likewise.
7217 (vqshlq_m_r_s32): Likewise.
7218 (vqrshlq_m_n_s32): Likewise.
7219 (vqnegq_m_s32): Likewise.
7220 (vqabsq_m_s32): Likewise.
7221 (vnegq_m_s32): Likewise.
7222 (vmvnq_m_s32): Likewise.
7223 (vmlsdavxq_p_s32): Likewise.
7224 (vmlsdavq_p_s32): Likewise.
7225 (vmladavxq_p_s32): Likewise.
7226 (vmladavq_p_s32): Likewise.
7227 (vminvq_p_s32): Likewise.
7228 (vmaxvq_p_s32): Likewise.
7229 (vdupq_m_n_s32): Likewise.
7230 (vclzq_m_s32): Likewise.
7231 (vclsq_m_s32): Likewise.
7232 (vaddvaq_p_s32): Likewise.
7233 (vabsq_m_s32): Likewise.
7234 (vqrdmlsdhxq_s32): Likewise.
7235 (vqrdmlsdhq_s32): Likewise.
7236 (vqrdmlashq_n_s32): Likewise.
7237 (vqrdmlahq_n_s32): Likewise.
7238 (vqrdmladhxq_s32): Likewise.
7239 (vqrdmladhq_s32): Likewise.
7240 (vqdmlsdhxq_s32): Likewise.
7241 (vqdmlsdhq_s32): Likewise.
7242 (vqdmlahq_n_s32): Likewise.
7243 (vqdmladhxq_s32): Likewise.
7244 (vqdmladhq_s32): Likewise.
7245 (vmlsdavaxq_s32): Likewise.
7246 (vmlsdavaq_s32): Likewise.
7247 (vmlasq_n_s32): Likewise.
7248 (vmlaq_n_s32): Likewise.
7249 (vmladavaxq_s32): Likewise.
7250 (vmladavaq_s32): Likewise.
7251 (vsriq_n_s32): Likewise.
7252 (vsliq_n_s32): Likewise.
7253 (vpselq_u64): Likewise.
7254 (vpselq_s64): Likewise.
7255 (__arm_vpselq_u8): Define intrinsic.
7256 (__arm_vpselq_s8): Likewise.
7257 (__arm_vrev64q_m_u8): Likewise.
7258 (__arm_vqrdmlashq_n_u8): Likewise.
7259 (__arm_vqrdmlahq_n_u8): Likewise.
7260 (__arm_vqdmlahq_n_u8): Likewise.
7261 (__arm_vmvnq_m_u8): Likewise.
7262 (__arm_vmlasq_n_u8): Likewise.
7263 (__arm_vmlaq_n_u8): Likewise.
7264 (__arm_vmladavq_p_u8): Likewise.
7265 (__arm_vmladavaq_u8): Likewise.
7266 (__arm_vminvq_p_u8): Likewise.
7267 (__arm_vmaxvq_p_u8): Likewise.
7268 (__arm_vdupq_m_n_u8): Likewise.
7269 (__arm_vcmpneq_m_u8): Likewise.
7270 (__arm_vcmpneq_m_n_u8): Likewise.
7271 (__arm_vcmphiq_m_u8): Likewise.
7272 (__arm_vcmphiq_m_n_u8): Likewise.
7273 (__arm_vcmpeqq_m_u8): Likewise.
7274 (__arm_vcmpeqq_m_n_u8): Likewise.
7275 (__arm_vcmpcsq_m_u8): Likewise.
7276 (__arm_vcmpcsq_m_n_u8): Likewise.
7277 (__arm_vclzq_m_u8): Likewise.
7278 (__arm_vaddvaq_p_u8): Likewise.
7279 (__arm_vsriq_n_u8): Likewise.
7280 (__arm_vsliq_n_u8): Likewise.
7281 (__arm_vshlq_m_r_u8): Likewise.
7282 (__arm_vrshlq_m_n_u8): Likewise.
7283 (__arm_vqshlq_m_r_u8): Likewise.
7284 (__arm_vqrshlq_m_n_u8): Likewise.
7285 (__arm_vminavq_p_s8): Likewise.
7286 (__arm_vminaq_m_s8): Likewise.
7287 (__arm_vmaxavq_p_s8): Likewise.
7288 (__arm_vmaxaq_m_s8): Likewise.
7289 (__arm_vcmpneq_m_s8): Likewise.
7290 (__arm_vcmpneq_m_n_s8): Likewise.
7291 (__arm_vcmpltq_m_s8): Likewise.
7292 (__arm_vcmpltq_m_n_s8): Likewise.
7293 (__arm_vcmpleq_m_s8): Likewise.
7294 (__arm_vcmpleq_m_n_s8): Likewise.
7295 (__arm_vcmpgtq_m_s8): Likewise.
7296 (__arm_vcmpgtq_m_n_s8): Likewise.
7297 (__arm_vcmpgeq_m_s8): Likewise.
7298 (__arm_vcmpgeq_m_n_s8): Likewise.
7299 (__arm_vcmpeqq_m_s8): Likewise.
7300 (__arm_vcmpeqq_m_n_s8): Likewise.
7301 (__arm_vshlq_m_r_s8): Likewise.
7302 (__arm_vrshlq_m_n_s8): Likewise.
7303 (__arm_vrev64q_m_s8): Likewise.
7304 (__arm_vqshlq_m_r_s8): Likewise.
7305 (__arm_vqrshlq_m_n_s8): Likewise.
7306 (__arm_vqnegq_m_s8): Likewise.
7307 (__arm_vqabsq_m_s8): Likewise.
7308 (__arm_vnegq_m_s8): Likewise.
7309 (__arm_vmvnq_m_s8): Likewise.
7310 (__arm_vmlsdavxq_p_s8): Likewise.
7311 (__arm_vmlsdavq_p_s8): Likewise.
7312 (__arm_vmladavxq_p_s8): Likewise.
7313 (__arm_vmladavq_p_s8): Likewise.
7314 (__arm_vminvq_p_s8): Likewise.
7315 (__arm_vmaxvq_p_s8): Likewise.
7316 (__arm_vdupq_m_n_s8): Likewise.
7317 (__arm_vclzq_m_s8): Likewise.
7318 (__arm_vclsq_m_s8): Likewise.
7319 (__arm_vaddvaq_p_s8): Likewise.
7320 (__arm_vabsq_m_s8): Likewise.
7321 (__arm_vqrdmlsdhxq_s8): Likewise.
7322 (__arm_vqrdmlsdhq_s8): Likewise.
7323 (__arm_vqrdmlashq_n_s8): Likewise.
7324 (__arm_vqrdmlahq_n_s8): Likewise.
7325 (__arm_vqrdmladhxq_s8): Likewise.
7326 (__arm_vqrdmladhq_s8): Likewise.
7327 (__arm_vqdmlsdhxq_s8): Likewise.
7328 (__arm_vqdmlsdhq_s8): Likewise.
7329 (__arm_vqdmlahq_n_s8): Likewise.
7330 (__arm_vqdmladhxq_s8): Likewise.
7331 (__arm_vqdmladhq_s8): Likewise.
7332 (__arm_vmlsdavaxq_s8): Likewise.
7333 (__arm_vmlsdavaq_s8): Likewise.
7334 (__arm_vmlasq_n_s8): Likewise.
7335 (__arm_vmlaq_n_s8): Likewise.
7336 (__arm_vmladavaxq_s8): Likewise.
7337 (__arm_vmladavaq_s8): Likewise.
7338 (__arm_vsriq_n_s8): Likewise.
7339 (__arm_vsliq_n_s8): Likewise.
7340 (__arm_vpselq_u16): Likewise.
7341 (__arm_vpselq_s16): Likewise.
7342 (__arm_vrev64q_m_u16): Likewise.
7343 (__arm_vqrdmlashq_n_u16): Likewise.
7344 (__arm_vqrdmlahq_n_u16): Likewise.
7345 (__arm_vqdmlahq_n_u16): Likewise.
7346 (__arm_vmvnq_m_u16): Likewise.
7347 (__arm_vmlasq_n_u16): Likewise.
7348 (__arm_vmlaq_n_u16): Likewise.
7349 (__arm_vmladavq_p_u16): Likewise.
7350 (__arm_vmladavaq_u16): Likewise.
7351 (__arm_vminvq_p_u16): Likewise.
7352 (__arm_vmaxvq_p_u16): Likewise.
7353 (__arm_vdupq_m_n_u16): Likewise.
7354 (__arm_vcmpneq_m_u16): Likewise.
7355 (__arm_vcmpneq_m_n_u16): Likewise.
7356 (__arm_vcmphiq_m_u16): Likewise.
7357 (__arm_vcmphiq_m_n_u16): Likewise.
7358 (__arm_vcmpeqq_m_u16): Likewise.
7359 (__arm_vcmpeqq_m_n_u16): Likewise.
7360 (__arm_vcmpcsq_m_u16): Likewise.
7361 (__arm_vcmpcsq_m_n_u16): Likewise.
7362 (__arm_vclzq_m_u16): Likewise.
7363 (__arm_vaddvaq_p_u16): Likewise.
7364 (__arm_vsriq_n_u16): Likewise.
7365 (__arm_vsliq_n_u16): Likewise.
7366 (__arm_vshlq_m_r_u16): Likewise.
7367 (__arm_vrshlq_m_n_u16): Likewise.
7368 (__arm_vqshlq_m_r_u16): Likewise.
7369 (__arm_vqrshlq_m_n_u16): Likewise.
7370 (__arm_vminavq_p_s16): Likewise.
7371 (__arm_vminaq_m_s16): Likewise.
7372 (__arm_vmaxavq_p_s16): Likewise.
7373 (__arm_vmaxaq_m_s16): Likewise.
7374 (__arm_vcmpneq_m_s16): Likewise.
7375 (__arm_vcmpneq_m_n_s16): Likewise.
7376 (__arm_vcmpltq_m_s16): Likewise.
7377 (__arm_vcmpltq_m_n_s16): Likewise.
7378 (__arm_vcmpleq_m_s16): Likewise.
7379 (__arm_vcmpleq_m_n_s16): Likewise.
7380 (__arm_vcmpgtq_m_s16): Likewise.
7381 (__arm_vcmpgtq_m_n_s16): Likewise.
7382 (__arm_vcmpgeq_m_s16): Likewise.
7383 (__arm_vcmpgeq_m_n_s16): Likewise.
7384 (__arm_vcmpeqq_m_s16): Likewise.
7385 (__arm_vcmpeqq_m_n_s16): Likewise.
7386 (__arm_vshlq_m_r_s16): Likewise.
7387 (__arm_vrshlq_m_n_s16): Likewise.
7388 (__arm_vrev64q_m_s16): Likewise.
7389 (__arm_vqshlq_m_r_s16): Likewise.
7390 (__arm_vqrshlq_m_n_s16): Likewise.
7391 (__arm_vqnegq_m_s16): Likewise.
7392 (__arm_vqabsq_m_s16): Likewise.
7393 (__arm_vnegq_m_s16): Likewise.
7394 (__arm_vmvnq_m_s16): Likewise.
7395 (__arm_vmlsdavxq_p_s16): Likewise.
7396 (__arm_vmlsdavq_p_s16): Likewise.
7397 (__arm_vmladavxq_p_s16): Likewise.
7398 (__arm_vmladavq_p_s16): Likewise.
7399 (__arm_vminvq_p_s16): Likewise.
7400 (__arm_vmaxvq_p_s16): Likewise.
7401 (__arm_vdupq_m_n_s16): Likewise.
7402 (__arm_vclzq_m_s16): Likewise.
7403 (__arm_vclsq_m_s16): Likewise.
7404 (__arm_vaddvaq_p_s16): Likewise.
7405 (__arm_vabsq_m_s16): Likewise.
7406 (__arm_vqrdmlsdhxq_s16): Likewise.
7407 (__arm_vqrdmlsdhq_s16): Likewise.
7408 (__arm_vqrdmlashq_n_s16): Likewise.
7409 (__arm_vqrdmlahq_n_s16): Likewise.
7410 (__arm_vqrdmladhxq_s16): Likewise.
7411 (__arm_vqrdmladhq_s16): Likewise.
7412 (__arm_vqdmlsdhxq_s16): Likewise.
7413 (__arm_vqdmlsdhq_s16): Likewise.
7414 (__arm_vqdmlahq_n_s16): Likewise.
7415 (__arm_vqdmladhxq_s16): Likewise.
7416 (__arm_vqdmladhq_s16): Likewise.
7417 (__arm_vmlsdavaxq_s16): Likewise.
7418 (__arm_vmlsdavaq_s16): Likewise.
7419 (__arm_vmlasq_n_s16): Likewise.
7420 (__arm_vmlaq_n_s16): Likewise.
7421 (__arm_vmladavaxq_s16): Likewise.
7422 (__arm_vmladavaq_s16): Likewise.
7423 (__arm_vsriq_n_s16): Likewise.
7424 (__arm_vsliq_n_s16): Likewise.
7425 (__arm_vpselq_u32): Likewise.
7426 (__arm_vpselq_s32): Likewise.
7427 (__arm_vrev64q_m_u32): Likewise.
7428 (__arm_vqrdmlashq_n_u32): Likewise.
7429 (__arm_vqrdmlahq_n_u32): Likewise.
7430 (__arm_vqdmlahq_n_u32): Likewise.
7431 (__arm_vmvnq_m_u32): Likewise.
7432 (__arm_vmlasq_n_u32): Likewise.
7433 (__arm_vmlaq_n_u32): Likewise.
7434 (__arm_vmladavq_p_u32): Likewise.
7435 (__arm_vmladavaq_u32): Likewise.
7436 (__arm_vminvq_p_u32): Likewise.
7437 (__arm_vmaxvq_p_u32): Likewise.
7438 (__arm_vdupq_m_n_u32): Likewise.
7439 (__arm_vcmpneq_m_u32): Likewise.
7440 (__arm_vcmpneq_m_n_u32): Likewise.
7441 (__arm_vcmphiq_m_u32): Likewise.
7442 (__arm_vcmphiq_m_n_u32): Likewise.
7443 (__arm_vcmpeqq_m_u32): Likewise.
7444 (__arm_vcmpeqq_m_n_u32): Likewise.
7445 (__arm_vcmpcsq_m_u32): Likewise.
7446 (__arm_vcmpcsq_m_n_u32): Likewise.
7447 (__arm_vclzq_m_u32): Likewise.
7448 (__arm_vaddvaq_p_u32): Likewise.
7449 (__arm_vsriq_n_u32): Likewise.
7450 (__arm_vsliq_n_u32): Likewise.
7451 (__arm_vshlq_m_r_u32): Likewise.
7452 (__arm_vrshlq_m_n_u32): Likewise.
7453 (__arm_vqshlq_m_r_u32): Likewise.
7454 (__arm_vqrshlq_m_n_u32): Likewise.
7455 (__arm_vminavq_p_s32): Likewise.
7456 (__arm_vminaq_m_s32): Likewise.
7457 (__arm_vmaxavq_p_s32): Likewise.
7458 (__arm_vmaxaq_m_s32): Likewise.
7459 (__arm_vcmpneq_m_s32): Likewise.
7460 (__arm_vcmpneq_m_n_s32): Likewise.
7461 (__arm_vcmpltq_m_s32): Likewise.
7462 (__arm_vcmpltq_m_n_s32): Likewise.
7463 (__arm_vcmpleq_m_s32): Likewise.
7464 (__arm_vcmpleq_m_n_s32): Likewise.
7465 (__arm_vcmpgtq_m_s32): Likewise.
7466 (__arm_vcmpgtq_m_n_s32): Likewise.
7467 (__arm_vcmpgeq_m_s32): Likewise.
7468 (__arm_vcmpgeq_m_n_s32): Likewise.
7469 (__arm_vcmpeqq_m_s32): Likewise.
7470 (__arm_vcmpeqq_m_n_s32): Likewise.
7471 (__arm_vshlq_m_r_s32): Likewise.
7472 (__arm_vrshlq_m_n_s32): Likewise.
7473 (__arm_vrev64q_m_s32): Likewise.
7474 (__arm_vqshlq_m_r_s32): Likewise.
7475 (__arm_vqrshlq_m_n_s32): Likewise.
7476 (__arm_vqnegq_m_s32): Likewise.
7477 (__arm_vqabsq_m_s32): Likewise.
7478 (__arm_vnegq_m_s32): Likewise.
7479 (__arm_vmvnq_m_s32): Likewise.
7480 (__arm_vmlsdavxq_p_s32): Likewise.
7481 (__arm_vmlsdavq_p_s32): Likewise.
7482 (__arm_vmladavxq_p_s32): Likewise.
7483 (__arm_vmladavq_p_s32): Likewise.
7484 (__arm_vminvq_p_s32): Likewise.
7485 (__arm_vmaxvq_p_s32): Likewise.
7486 (__arm_vdupq_m_n_s32): Likewise.
7487 (__arm_vclzq_m_s32): Likewise.
7488 (__arm_vclsq_m_s32): Likewise.
7489 (__arm_vaddvaq_p_s32): Likewise.
7490 (__arm_vabsq_m_s32): Likewise.
7491 (__arm_vqrdmlsdhxq_s32): Likewise.
7492 (__arm_vqrdmlsdhq_s32): Likewise.
7493 (__arm_vqrdmlashq_n_s32): Likewise.
7494 (__arm_vqrdmlahq_n_s32): Likewise.
7495 (__arm_vqrdmladhxq_s32): Likewise.
7496 (__arm_vqrdmladhq_s32): Likewise.
7497 (__arm_vqdmlsdhxq_s32): Likewise.
7498 (__arm_vqdmlsdhq_s32): Likewise.
7499 (__arm_vqdmlahq_n_s32): Likewise.
7500 (__arm_vqdmladhxq_s32): Likewise.
7501 (__arm_vqdmladhq_s32): Likewise.
7502 (__arm_vmlsdavaxq_s32): Likewise.
7503 (__arm_vmlsdavaq_s32): Likewise.
7504 (__arm_vmlasq_n_s32): Likewise.
7505 (__arm_vmlaq_n_s32): Likewise.
7506 (__arm_vmladavaxq_s32): Likewise.
7507 (__arm_vmladavaq_s32): Likewise.
7508 (__arm_vsriq_n_s32): Likewise.
7509 (__arm_vsliq_n_s32): Likewise.
7510 (__arm_vpselq_u64): Likewise.
7511 (__arm_vpselq_s64): Likewise.
7512 (vcmpneq_m_n): Define polymorphic variant.
7513 (vcmpneq_m): Likewise.
7514 (vqrdmlsdhq): Likewise.
7515 (vqrdmlsdhxq): Likewise.
7516 (vqrshlq_m_n): Likewise.
7517 (vqshlq_m_r): Likewise.
7518 (vrev64q_m): Likewise.
7519 (vrshlq_m_n): Likewise.
7520 (vshlq_m_r): Likewise.
7521 (vsliq_n): Likewise.
7522 (vsriq_n): Likewise.
7523 (vqrdmlashq_n): Likewise.
7524 (vqrdmlahq): Likewise.
7525 (vqrdmladhxq): Likewise.
7526 (vqrdmladhq): Likewise.
7527 (vqnegq_m): Likewise.
7528 (vqdmlsdhxq): Likewise.
7529 (vabsq_m): Likewise.
7530 (vclsq_m): Likewise.
7531 (vclzq_m): Likewise.
7532 (vcmpgeq_m): Likewise.
7533 (vcmpgeq_m_n): Likewise.
7534 (vdupq_m_n): Likewise.
7535 (vmaxaq_m): Likewise.
7536 (vmlaq_n): Likewise.
7537 (vmlasq_n): Likewise.
7538 (vmvnq_m): Likewise.
7539 (vnegq_m): Likewise.
7541 (vqdmlahq_n): Likewise.
7542 (vqrdmlahq_n): Likewise.
7543 (vqdmlsdhq): Likewise.
7544 (vqdmladhq): Likewise.
7545 (vqabsq_m): Likewise.
7546 (vminaq_m): Likewise.
7547 (vrmlaldavhaq): Likewise.
7548 (vmlsdavxq_p): Likewise.
7549 (vmlsdavq_p): Likewise.
7550 (vmlsdavaxq): Likewise.
7551 (vmlsdavaq): Likewise.
7552 (vaddvaq_p): Likewise.
7553 (vcmpcsq_m_n): Likewise.
7554 (vcmpcsq_m): Likewise.
7555 (vcmpeqq_m_n): Likewise.
7556 (vcmpeqq_m): Likewise.
7557 (vmladavxq_p): Likewise.
7558 (vmladavq_p): Likewise.
7559 (vmladavaxq): Likewise.
7560 (vmladavaq): Likewise.
7561 (vminvq_p): Likewise.
7562 (vminavq_p): Likewise.
7563 (vmaxvq_p): Likewise.
7564 (vmaxavq_p): Likewise.
7565 (vcmpltq_m_n): Likewise.
7566 (vcmpltq_m): Likewise.
7567 (vcmpleq_m): Likewise.
7568 (vcmpleq_m_n): Likewise.
7569 (vcmphiq_m_n): Likewise.
7570 (vcmphiq_m): Likewise.
7571 (vcmpgtq_m_n): Likewise.
7572 (vcmpgtq_m): Likewise.
7573 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use
7575 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
7576 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
7577 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
7578 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
7579 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
7580 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
7581 * config/arm/constraints.md (Rc): Define constraint to check constant is
7582 in the range of 0 to 15.
7583 (Re): Define constraint to check constant is in the range of 0 to 31.
7584 * config/arm/mve.md (VADDVAQ_P): Define iterator.
7585 (VCLZQ_M): Likewise.
7586 (VCMPEQQ_M_N): Likewise.
7587 (VCMPEQQ_M): Likewise.
7588 (VCMPNEQ_M_N): Likewise.
7589 (VCMPNEQ_M): Likewise.
7590 (VDUPQ_M_N): Likewise.
7591 (VMAXVQ_P): Likewise.
7592 (VMINVQ_P): Likewise.
7593 (VMLADAVAQ): Likewise.
7594 (VMLADAVQ_P): Likewise.
7595 (VMLAQ_N): Likewise.
7596 (VMLASQ_N): Likewise.
7597 (VMVNQ_M): Likewise.
7599 (VQDMLAHQ_N): Likewise.
7600 (VQRDMLAHQ_N): Likewise.
7601 (VQRDMLASHQ_N): Likewise.
7602 (VQRSHLQ_M_N): Likewise.
7603 (VQSHLQ_M_R): Likewise.
7604 (VREV64Q_M): Likewise.
7605 (VRSHLQ_M_N): Likewise.
7606 (VSHLQ_M_R): Likewise.
7607 (VSLIQ_N): Likewise.
7608 (VSRIQ_N): Likewise.
7609 (mve_vabsq_m_s<mode>): Define RTL pattern.
7610 (mve_vaddvaq_p_<supf><mode>): Likewise.
7611 (mve_vclsq_m_s<mode>): Likewise.
7612 (mve_vclzq_m_<supf><mode>): Likewise.
7613 (mve_vcmpcsq_m_n_u<mode>): Likewise.
7614 (mve_vcmpcsq_m_u<mode>): Likewise.
7615 (mve_vcmpeqq_m_n_<supf><mode>): Likewise.
7616 (mve_vcmpeqq_m_<supf><mode>): Likewise.
7617 (mve_vcmpgeq_m_n_s<mode>): Likewise.
7618 (mve_vcmpgeq_m_s<mode>): Likewise.
7619 (mve_vcmpgtq_m_n_s<mode>): Likewise.
7620 (mve_vcmpgtq_m_s<mode>): Likewise.
7621 (mve_vcmphiq_m_n_u<mode>): Likewise.
7622 (mve_vcmphiq_m_u<mode>): Likewise.
7623 (mve_vcmpleq_m_n_s<mode>): Likewise.
7624 (mve_vcmpleq_m_s<mode>): Likewise.
7625 (mve_vcmpltq_m_n_s<mode>): Likewise.
7626 (mve_vcmpltq_m_s<mode>): Likewise.
7627 (mve_vcmpneq_m_n_<supf><mode>): Likewise.
7628 (mve_vcmpneq_m_<supf><mode>): Likewise.
7629 (mve_vdupq_m_n_<supf><mode>): Likewise.
7630 (mve_vmaxaq_m_s<mode>): Likewise.
7631 (mve_vmaxavq_p_s<mode>): Likewise.
7632 (mve_vmaxvq_p_<supf><mode>): Likewise.
7633 (mve_vminaq_m_s<mode>): Likewise.
7634 (mve_vminavq_p_s<mode>): Likewise.
7635 (mve_vminvq_p_<supf><mode>): Likewise.
7636 (mve_vmladavaq_<supf><mode>): Likewise.
7637 (mve_vmladavq_p_<supf><mode>): Likewise.
7638 (mve_vmladavxq_p_s<mode>): Likewise.
7639 (mve_vmlaq_n_<supf><mode>): Likewise.
7640 (mve_vmlasq_n_<supf><mode>): Likewise.
7641 (mve_vmlsdavq_p_s<mode>): Likewise.
7642 (mve_vmlsdavxq_p_s<mode>): Likewise.
7643 (mve_vmvnq_m_<supf><mode>): Likewise.
7644 (mve_vnegq_m_s<mode>): Likewise.
7645 (mve_vpselq_<supf><mode>): Likewise.
7646 (mve_vqabsq_m_s<mode>): Likewise.
7647 (mve_vqdmlahq_n_<supf><mode>): Likewise.
7648 (mve_vqnegq_m_s<mode>): Likewise.
7649 (mve_vqrdmladhq_s<mode>): Likewise.
7650 (mve_vqrdmladhxq_s<mode>): Likewise.
7651 (mve_vqrdmlahq_n_<supf><mode>): Likewise.
7652 (mve_vqrdmlashq_n_<supf><mode>): Likewise.
7653 (mve_vqrdmlsdhq_s<mode>): Likewise.
7654 (mve_vqrdmlsdhxq_s<mode>): Likewise.
7655 (mve_vqrshlq_m_n_<supf><mode>): Likewise.
7656 (mve_vqshlq_m_r_<supf><mode>): Likewise.
7657 (mve_vrev64q_m_<supf><mode>): Likewise.
7658 (mve_vrshlq_m_n_<supf><mode>): Likewise.
7659 (mve_vshlq_m_r_<supf><mode>): Likewise.
7660 (mve_vsliq_n_<supf><mode>): Likewise.
7661 (mve_vsriq_n_<supf><mode>): Likewise.
7662 (mve_vqdmlsdhxq_s<mode>): Likewise.
7663 (mve_vqdmlsdhq_s<mode>): Likewise.
7664 (mve_vqdmladhxq_s<mode>): Likewise.
7665 (mve_vqdmladhq_s<mode>): Likewise.
7666 (mve_vmlsdavaxq_s<mode>): Likewise.
7667 (mve_vmlsdavaq_s<mode>): Likewise.
7668 (mve_vmladavaxq_s<mode>): Likewise.
7669 * config/arm/predicates.md (mve_imm_15):Define predicate to check the
7670 matching constraint Rc.
7671 (mve_imm_31): Define predicate to check the matching constraint Re.
7673 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
7675 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
7676 (vec_cmp<mode>di_dup): Likewise.
7677 * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.
7679 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
7681 * config/gcn/gcn-valu.md (COND_MODE): Delete.
7682 (COND_INT_MODE): Delete.
7683 (cond_op): Add "mult".
7684 (cond_<expander><mode>): Use VEC_ALLREG_MODE.
7685 (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
7687 2020-03-18 Richard Biener <rguenther@suse.de>
7690 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using
7691 partial int modes or not mode-precision integer types for
7694 2020-03-18 Jakub Jelinek <jakub@redhat.com>
7696 * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue
7698 * config/arc/arc.c (frame_stack_add): Likewise.
7699 * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term):
7701 * ipa-predicate.c (predicate::remap_after_inlining): Likewise.
7702 * tree-ssa-strlen.h (handle_printf_call): Likewise.
7703 * tree-ssa-strlen.c (is_strlen_related_p): Likewise.
7704 * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise.
7706 2020-03-18 Duan bo <duanbo3@huawei.com>
7709 * config/aarch64/aarch64.md (ldr_got_tiny): Delete.
7710 (@ldr_got_tiny_<mode>): New pattern.
7711 (ldr_got_tiny_sidi): Likewise.
7712 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use
7713 them to handle SYMBOL_TINY_GOT for ILP32.
7715 2020-03-18 Richard Sandiford <richard.sandiford@arm.com>
7717 * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
7718 call-preserved for SVE PCS functions.
7719 (aarch64_layout_frame): Cope with up to 12 predicate save slots.
7720 Optimize the case in which there are no following vector save slots.
7722 2020-03-18 Richard Biener <rguenther@suse.de>
7725 * fold-const.c (build_fold_addr_expr): Convert address to
7727 * asan.c (maybe_create_ssa_name): Strip useless type conversions.
7728 * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1
7729 to build the ADDR_EXPR which we don't really want to simplify.
7730 * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise.
7731 * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise.
7732 * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
7733 (simplify_builtin_call): Strip useless type conversions.
7734 * tree-ssa-strlen.c (new_strinfo): Likewise.
7736 2020-03-17 Alexey Neyman <stilor@att.net>
7739 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if
7740 the debug level is terse and the declaration is public. Do not
7742 (dwarf2out_decl): Same.
7743 (add_type_attribute): Return immediately if debug level is
7746 2020-03-17 Richard Sandiford <richard.sandiford@arm.com>
7748 * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF.
7750 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
7751 Mihail Ionescu <mihail.ionescu@arm.com>
7752 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7754 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
7755 Define qualifier for ternary operands.
7756 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
7757 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
7758 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
7759 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
7760 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
7761 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
7762 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
7763 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
7764 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
7765 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
7766 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
7767 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
7768 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
7769 * config/arm/arm_mve.h (vabavq_s8): Define macro.
7770 (vabavq_s16): Likewise.
7771 (vabavq_s32): Likewise.
7772 (vbicq_m_n_s16): Likewise.
7773 (vbicq_m_n_s32): Likewise.
7774 (vbicq_m_n_u16): Likewise.
7775 (vbicq_m_n_u32): Likewise.
7776 (vcmpeqq_m_f16): Likewise.
7777 (vcmpeqq_m_f32): Likewise.
7778 (vcvtaq_m_s16_f16): Likewise.
7779 (vcvtaq_m_u16_f16): Likewise.
7780 (vcvtaq_m_s32_f32): Likewise.
7781 (vcvtaq_m_u32_f32): Likewise.
7782 (vcvtq_m_f16_s16): Likewise.
7783 (vcvtq_m_f16_u16): Likewise.
7784 (vcvtq_m_f32_s32): Likewise.
7785 (vcvtq_m_f32_u32): Likewise.
7786 (vqrshrnbq_n_s16): Likewise.
7787 (vqrshrnbq_n_u16): Likewise.
7788 (vqrshrnbq_n_s32): Likewise.
7789 (vqrshrnbq_n_u32): Likewise.
7790 (vqrshrunbq_n_s16): Likewise.
7791 (vqrshrunbq_n_s32): Likewise.
7792 (vrmlaldavhaq_s32): Likewise.
7793 (vrmlaldavhaq_u32): Likewise.
7794 (vshlcq_s8): Likewise.
7795 (vshlcq_u8): Likewise.
7796 (vshlcq_s16): Likewise.
7797 (vshlcq_u16): Likewise.
7798 (vshlcq_s32): Likewise.
7799 (vshlcq_u32): Likewise.
7800 (vabavq_u8): Likewise.
7801 (vabavq_u16): Likewise.
7802 (vabavq_u32): Likewise.
7803 (__arm_vabavq_s8): Define intrinsic.
7804 (__arm_vabavq_s16): Likewise.
7805 (__arm_vabavq_s32): Likewise.
7806 (__arm_vabavq_u8): Likewise.
7807 (__arm_vabavq_u16): Likewise.
7808 (__arm_vabavq_u32): Likewise.
7809 (__arm_vbicq_m_n_s16): Likewise.
7810 (__arm_vbicq_m_n_s32): Likewise.
7811 (__arm_vbicq_m_n_u16): Likewise.
7812 (__arm_vbicq_m_n_u32): Likewise.
7813 (__arm_vqrshrnbq_n_s16): Likewise.
7814 (__arm_vqrshrnbq_n_u16): Likewise.
7815 (__arm_vqrshrnbq_n_s32): Likewise.
7816 (__arm_vqrshrnbq_n_u32): Likewise.
7817 (__arm_vqrshrunbq_n_s16): Likewise.
7818 (__arm_vqrshrunbq_n_s32): Likewise.
7819 (__arm_vrmlaldavhaq_s32): Likewise.
7820 (__arm_vrmlaldavhaq_u32): Likewise.
7821 (__arm_vshlcq_s8): Likewise.
7822 (__arm_vshlcq_u8): Likewise.
7823 (__arm_vshlcq_s16): Likewise.
7824 (__arm_vshlcq_u16): Likewise.
7825 (__arm_vshlcq_s32): Likewise.
7826 (__arm_vshlcq_u32): Likewise.
7827 (__arm_vcmpeqq_m_f16): Likewise.
7828 (__arm_vcmpeqq_m_f32): Likewise.
7829 (__arm_vcvtaq_m_s16_f16): Likewise.
7830 (__arm_vcvtaq_m_u16_f16): Likewise.
7831 (__arm_vcvtaq_m_s32_f32): Likewise.
7832 (__arm_vcvtaq_m_u32_f32): Likewise.
7833 (__arm_vcvtq_m_f16_s16): Likewise.
7834 (__arm_vcvtq_m_f16_u16): Likewise.
7835 (__arm_vcvtq_m_f32_s32): Likewise.
7836 (__arm_vcvtq_m_f32_u32): Likewise.
7837 (vcvtaq_m): Define polymorphic variant.
7838 (vcvtq_m): Likewise.
7841 (vbicq_m_n): Likewise.
7842 (vqrshrnbq_n): Likewise.
7843 (vqrshrunbq_n): Likewise.
7844 * config/arm/arm_mve_builtins.def
7845 (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
7846 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
7847 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
7848 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
7849 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
7850 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
7851 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
7852 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
7853 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
7854 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
7855 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
7856 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
7857 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
7858 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
7859 * config/arm/mve.md (VBICQ_M_N): Define iterator.
7860 (VCVTAQ_M): Likewise.
7861 (VCVTQ_M_TO_F): Likewise.
7862 (VQRSHRNBQ_N): Likewise.
7865 (VRMLALDAVHAQ): Likewise.
7866 (mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
7867 (mve_vcmpeqq_m_f<mode>): Likewise.
7868 (mve_vcvtaq_m_<supf><mode>): Likewise.
7869 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
7870 (mve_vqrshrnbq_n_<supf><mode>): Likewise.
7871 (mve_vqrshrunbq_n_s<mode>): Likewise.
7872 (mve_vrmlaldavhaq_<supf>v4si): Likewise.
7873 (mve_vabavq_<supf><mode>): Likewise.
7874 (mve_vshlcq_<supf><mode>): Likewise.
7875 (mve_vshlcq_<supf><mode>): Likewise.
7876 (mve_vshlcq_vec_<supf><mode>): Define RTL expand.
7877 (mve_vshlcq_carry_<supf><mode>): Likewise.
7879 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
7880 Mihail Ionescu <mihail.ionescu@arm.com>
7881 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7883 * config/arm/arm_mve.h (vqmovntq_u16): Define macro.
7884 (vqmovnbq_u16): Likewise.
7885 (vmulltq_poly_p8): Likewise.
7886 (vmullbq_poly_p8): Likewise.
7887 (vmovntq_u16): Likewise.
7888 (vmovnbq_u16): Likewise.
7889 (vmlaldavxq_u16): Likewise.
7890 (vmlaldavq_u16): Likewise.
7891 (vqmovuntq_s16): Likewise.
7892 (vqmovunbq_s16): Likewise.
7893 (vshlltq_n_u8): Likewise.
7894 (vshllbq_n_u8): Likewise.
7895 (vorrq_n_u16): Likewise.
7896 (vbicq_n_u16): Likewise.
7897 (vcmpneq_n_f16): Likewise.
7898 (vcmpneq_f16): Likewise.
7899 (vcmpltq_n_f16): Likewise.
7900 (vcmpltq_f16): Likewise.
7901 (vcmpleq_n_f16): Likewise.
7902 (vcmpleq_f16): Likewise.
7903 (vcmpgtq_n_f16): Likewise.
7904 (vcmpgtq_f16): Likewise.
7905 (vcmpgeq_n_f16): Likewise.
7906 (vcmpgeq_f16): Likewise.
7907 (vcmpeqq_n_f16): Likewise.
7908 (vcmpeqq_f16): Likewise.
7909 (vsubq_f16): Likewise.
7910 (vqmovntq_s16): Likewise.
7911 (vqmovnbq_s16): Likewise.
7912 (vqdmulltq_s16): Likewise.
7913 (vqdmulltq_n_s16): Likewise.
7914 (vqdmullbq_s16): Likewise.
7915 (vqdmullbq_n_s16): Likewise.
7916 (vorrq_f16): Likewise.
7917 (vornq_f16): Likewise.
7918 (vmulq_n_f16): Likewise.
7919 (vmulq_f16): Likewise.
7920 (vmovntq_s16): Likewise.
7921 (vmovnbq_s16): Likewise.
7922 (vmlsldavxq_s16): Likewise.
7923 (vmlsldavq_s16): Likewise.
7924 (vmlaldavxq_s16): Likewise.
7925 (vmlaldavq_s16): Likewise.
7926 (vminnmvq_f16): Likewise.
7927 (vminnmq_f16): Likewise.
7928 (vminnmavq_f16): Likewise.
7929 (vminnmaq_f16): Likewise.
7930 (vmaxnmvq_f16): Likewise.
7931 (vmaxnmq_f16): Likewise.
7932 (vmaxnmavq_f16): Likewise.
7933 (vmaxnmaq_f16): Likewise.
7934 (veorq_f16): Likewise.
7935 (vcmulq_rot90_f16): Likewise.
7936 (vcmulq_rot270_f16): Likewise.
7937 (vcmulq_rot180_f16): Likewise.
7938 (vcmulq_f16): Likewise.
7939 (vcaddq_rot90_f16): Likewise.
7940 (vcaddq_rot270_f16): Likewise.
7941 (vbicq_f16): Likewise.
7942 (vandq_f16): Likewise.
7943 (vaddq_n_f16): Likewise.
7944 (vabdq_f16): Likewise.
7945 (vshlltq_n_s8): Likewise.
7946 (vshllbq_n_s8): Likewise.
7947 (vorrq_n_s16): Likewise.
7948 (vbicq_n_s16): Likewise.
7949 (vqmovntq_u32): Likewise.
7950 (vqmovnbq_u32): Likewise.
7951 (vmulltq_poly_p16): Likewise.
7952 (vmullbq_poly_p16): Likewise.
7953 (vmovntq_u32): Likewise.
7954 (vmovnbq_u32): Likewise.
7955 (vmlaldavxq_u32): Likewise.
7956 (vmlaldavq_u32): Likewise.
7957 (vqmovuntq_s32): Likewise.
7958 (vqmovunbq_s32): Likewise.
7959 (vshlltq_n_u16): Likewise.
7960 (vshllbq_n_u16): Likewise.
7961 (vorrq_n_u32): Likewise.
7962 (vbicq_n_u32): Likewise.
7963 (vcmpneq_n_f32): Likewise.
7964 (vcmpneq_f32): Likewise.
7965 (vcmpltq_n_f32): Likewise.
7966 (vcmpltq_f32): Likewise.
7967 (vcmpleq_n_f32): Likewise.
7968 (vcmpleq_f32): Likewise.
7969 (vcmpgtq_n_f32): Likewise.
7970 (vcmpgtq_f32): Likewise.
7971 (vcmpgeq_n_f32): Likewise.
7972 (vcmpgeq_f32): Likewise.
7973 (vcmpeqq_n_f32): Likewise.
7974 (vcmpeqq_f32): Likewise.
7975 (vsubq_f32): Likewise.
7976 (vqmovntq_s32): Likewise.
7977 (vqmovnbq_s32): Likewise.
7978 (vqdmulltq_s32): Likewise.
7979 (vqdmulltq_n_s32): Likewise.
7980 (vqdmullbq_s32): Likewise.
7981 (vqdmullbq_n_s32): Likewise.
7982 (vorrq_f32): Likewise.
7983 (vornq_f32): Likewise.
7984 (vmulq_n_f32): Likewise.
7985 (vmulq_f32): Likewise.
7986 (vmovntq_s32): Likewise.
7987 (vmovnbq_s32): Likewise.
7988 (vmlsldavxq_s32): Likewise.
7989 (vmlsldavq_s32): Likewise.
7990 (vmlaldavxq_s32): Likewise.
7991 (vmlaldavq_s32): Likewise.
7992 (vminnmvq_f32): Likewise.
7993 (vminnmq_f32): Likewise.
7994 (vminnmavq_f32): Likewise.
7995 (vminnmaq_f32): Likewise.
7996 (vmaxnmvq_f32): Likewise.
7997 (vmaxnmq_f32): Likewise.
7998 (vmaxnmavq_f32): Likewise.
7999 (vmaxnmaq_f32): Likewise.
8000 (veorq_f32): Likewise.
8001 (vcmulq_rot90_f32): Likewise.
8002 (vcmulq_rot270_f32): Likewise.
8003 (vcmulq_rot180_f32): Likewise.
8004 (vcmulq_f32): Likewise.
8005 (vcaddq_rot90_f32): Likewise.
8006 (vcaddq_rot270_f32): Likewise.
8007 (vbicq_f32): Likewise.
8008 (vandq_f32): Likewise.
8009 (vaddq_n_f32): Likewise.
8010 (vabdq_f32): Likewise.
8011 (vshlltq_n_s16): Likewise.
8012 (vshllbq_n_s16): Likewise.
8013 (vorrq_n_s32): Likewise.
8014 (vbicq_n_s32): Likewise.
8015 (vrmlaldavhq_u32): Likewise.
8016 (vctp8q_m): Likewise.
8017 (vctp64q_m): Likewise.
8018 (vctp32q_m): Likewise.
8019 (vctp16q_m): Likewise.
8020 (vaddlvaq_u32): Likewise.
8021 (vrmlsldavhxq_s32): Likewise.
8022 (vrmlsldavhq_s32): Likewise.
8023 (vrmlaldavhxq_s32): Likewise.
8024 (vrmlaldavhq_s32): Likewise.
8025 (vcvttq_f16_f32): Likewise.
8026 (vcvtbq_f16_f32): Likewise.
8027 (vaddlvaq_s32): Likewise.
8028 (__arm_vqmovntq_u16): Define intrinsic.
8029 (__arm_vqmovnbq_u16): Likewise.
8030 (__arm_vmulltq_poly_p8): Likewise.
8031 (__arm_vmullbq_poly_p8): Likewise.
8032 (__arm_vmovntq_u16): Likewise.
8033 (__arm_vmovnbq_u16): Likewise.
8034 (__arm_vmlaldavxq_u16): Likewise.
8035 (__arm_vmlaldavq_u16): Likewise.
8036 (__arm_vqmovuntq_s16): Likewise.
8037 (__arm_vqmovunbq_s16): Likewise.
8038 (__arm_vshlltq_n_u8): Likewise.
8039 (__arm_vshllbq_n_u8): Likewise.
8040 (__arm_vorrq_n_u16): Likewise.
8041 (__arm_vbicq_n_u16): Likewise.
8042 (__arm_vcmpneq_n_f16): Likewise.
8043 (__arm_vcmpneq_f16): Likewise.
8044 (__arm_vcmpltq_n_f16): Likewise.
8045 (__arm_vcmpltq_f16): Likewise.
8046 (__arm_vcmpleq_n_f16): Likewise.
8047 (__arm_vcmpleq_f16): Likewise.
8048 (__arm_vcmpgtq_n_f16): Likewise.
8049 (__arm_vcmpgtq_f16): Likewise.
8050 (__arm_vcmpgeq_n_f16): Likewise.
8051 (__arm_vcmpgeq_f16): Likewise.
8052 (__arm_vcmpeqq_n_f16): Likewise.
8053 (__arm_vcmpeqq_f16): Likewise.
8054 (__arm_vsubq_f16): Likewise.
8055 (__arm_vqmovntq_s16): Likewise.
8056 (__arm_vqmovnbq_s16): Likewise.
8057 (__arm_vqdmulltq_s16): Likewise.
8058 (__arm_vqdmulltq_n_s16): Likewise.
8059 (__arm_vqdmullbq_s16): Likewise.
8060 (__arm_vqdmullbq_n_s16): Likewise.
8061 (__arm_vorrq_f16): Likewise.
8062 (__arm_vornq_f16): Likewise.
8063 (__arm_vmulq_n_f16): Likewise.
8064 (__arm_vmulq_f16): Likewise.
8065 (__arm_vmovntq_s16): Likewise.
8066 (__arm_vmovnbq_s16): Likewise.
8067 (__arm_vmlsldavxq_s16): Likewise.
8068 (__arm_vmlsldavq_s16): Likewise.
8069 (__arm_vmlaldavxq_s16): Likewise.
8070 (__arm_vmlaldavq_s16): Likewise.
8071 (__arm_vminnmvq_f16): Likewise.
8072 (__arm_vminnmq_f16): Likewise.
8073 (__arm_vminnmavq_f16): Likewise.
8074 (__arm_vminnmaq_f16): Likewise.
8075 (__arm_vmaxnmvq_f16): Likewise.
8076 (__arm_vmaxnmq_f16): Likewise.
8077 (__arm_vmaxnmavq_f16): Likewise.
8078 (__arm_vmaxnmaq_f16): Likewise.
8079 (__arm_veorq_f16): Likewise.
8080 (__arm_vcmulq_rot90_f16): Likewise.
8081 (__arm_vcmulq_rot270_f16): Likewise.
8082 (__arm_vcmulq_rot180_f16): Likewise.
8083 (__arm_vcmulq_f16): Likewise.
8084 (__arm_vcaddq_rot90_f16): Likewise.
8085 (__arm_vcaddq_rot270_f16): Likewise.
8086 (__arm_vbicq_f16): Likewise.
8087 (__arm_vandq_f16): Likewise.
8088 (__arm_vaddq_n_f16): Likewise.
8089 (__arm_vabdq_f16): Likewise.
8090 (__arm_vshlltq_n_s8): Likewise.
8091 (__arm_vshllbq_n_s8): Likewise.
8092 (__arm_vorrq_n_s16): Likewise.
8093 (__arm_vbicq_n_s16): Likewise.
8094 (__arm_vqmovntq_u32): Likewise.
8095 (__arm_vqmovnbq_u32): Likewise.
8096 (__arm_vmulltq_poly_p16): Likewise.
8097 (__arm_vmullbq_poly_p16): Likewise.
8098 (__arm_vmovntq_u32): Likewise.
8099 (__arm_vmovnbq_u32): Likewise.
8100 (__arm_vmlaldavxq_u32): Likewise.
8101 (__arm_vmlaldavq_u32): Likewise.
8102 (__arm_vqmovuntq_s32): Likewise.
8103 (__arm_vqmovunbq_s32): Likewise.
8104 (__arm_vshlltq_n_u16): Likewise.
8105 (__arm_vshllbq_n_u16): Likewise.
8106 (__arm_vorrq_n_u32): Likewise.
8107 (__arm_vbicq_n_u32): Likewise.
8108 (__arm_vcmpneq_n_f32): Likewise.
8109 (__arm_vcmpneq_f32): Likewise.
8110 (__arm_vcmpltq_n_f32): Likewise.
8111 (__arm_vcmpltq_f32): Likewise.
8112 (__arm_vcmpleq_n_f32): Likewise.
8113 (__arm_vcmpleq_f32): Likewise.
8114 (__arm_vcmpgtq_n_f32): Likewise.
8115 (__arm_vcmpgtq_f32): Likewise.
8116 (__arm_vcmpgeq_n_f32): Likewise.
8117 (__arm_vcmpgeq_f32): Likewise.
8118 (__arm_vcmpeqq_n_f32): Likewise.
8119 (__arm_vcmpeqq_f32): Likewise.
8120 (__arm_vsubq_f32): Likewise.
8121 (__arm_vqmovntq_s32): Likewise.
8122 (__arm_vqmovnbq_s32): Likewise.
8123 (__arm_vqdmulltq_s32): Likewise.
8124 (__arm_vqdmulltq_n_s32): Likewise.
8125 (__arm_vqdmullbq_s32): Likewise.
8126 (__arm_vqdmullbq_n_s32): Likewise.
8127 (__arm_vorrq_f32): Likewise.
8128 (__arm_vornq_f32): Likewise.
8129 (__arm_vmulq_n_f32): Likewise.
8130 (__arm_vmulq_f32): Likewise.
8131 (__arm_vmovntq_s32): Likewise.
8132 (__arm_vmovnbq_s32): Likewise.
8133 (__arm_vmlsldavxq_s32): Likewise.
8134 (__arm_vmlsldavq_s32): Likewise.
8135 (__arm_vmlaldavxq_s32): Likewise.
8136 (__arm_vmlaldavq_s32): Likewise.
8137 (__arm_vminnmvq_f32): Likewise.
8138 (__arm_vminnmq_f32): Likewise.
8139 (__arm_vminnmavq_f32): Likewise.
8140 (__arm_vminnmaq_f32): Likewise.
8141 (__arm_vmaxnmvq_f32): Likewise.
8142 (__arm_vmaxnmq_f32): Likewise.
8143 (__arm_vmaxnmavq_f32): Likewise.
8144 (__arm_vmaxnmaq_f32): Likewise.
8145 (__arm_veorq_f32): Likewise.
8146 (__arm_vcmulq_rot90_f32): Likewise.
8147 (__arm_vcmulq_rot270_f32): Likewise.
8148 (__arm_vcmulq_rot180_f32): Likewise.
8149 (__arm_vcmulq_f32): Likewise.
8150 (__arm_vcaddq_rot90_f32): Likewise.
8151 (__arm_vcaddq_rot270_f32): Likewise.
8152 (__arm_vbicq_f32): Likewise.
8153 (__arm_vandq_f32): Likewise.
8154 (__arm_vaddq_n_f32): Likewise.
8155 (__arm_vabdq_f32): Likewise.
8156 (__arm_vshlltq_n_s16): Likewise.
8157 (__arm_vshllbq_n_s16): Likewise.
8158 (__arm_vorrq_n_s32): Likewise.
8159 (__arm_vbicq_n_s32): Likewise.
8160 (__arm_vrmlaldavhq_u32): Likewise.
8161 (__arm_vctp8q_m): Likewise.
8162 (__arm_vctp64q_m): Likewise.
8163 (__arm_vctp32q_m): Likewise.
8164 (__arm_vctp16q_m): Likewise.
8165 (__arm_vaddlvaq_u32): Likewise.
8166 (__arm_vrmlsldavhxq_s32): Likewise.
8167 (__arm_vrmlsldavhq_s32): Likewise.
8168 (__arm_vrmlaldavhxq_s32): Likewise.
8169 (__arm_vrmlaldavhq_s32): Likewise.
8170 (__arm_vcvttq_f16_f32): Likewise.
8171 (__arm_vcvtbq_f16_f32): Likewise.
8172 (__arm_vaddlvaq_s32): Likewise.
8173 (vst4q): Define polymorphic variant.
8180 (vrev64q): Likewise.
8182 (vdupq_n): Likewise.
8184 (vrev32q): Likewise.
8185 (vcvtbq_f32): Likewise.
8186 (vcvttq_f32): Likewise.
8188 (vsubq_n): Likewise.
8189 (vbrsrq_n): Likewise.
8190 (vcvtq_n): Likewise.
8194 (vaddq_n): Likewise.
8198 (vmulq_n): Likewise.
8200 (vcaddq_rot270): Likewise.
8201 (vcmpeqq_n): Likewise.
8202 (vcmpeqq): Likewise.
8203 (vcaddq_rot90): Likewise.
8204 (vcmpgeq_n): Likewise.
8205 (vcmpgeq): Likewise.
8206 (vcmpgtq_n): Likewise.
8207 (vcmpgtq): Likewise.
8208 (vcmpgtq): Likewise.
8209 (vcmpleq_n): Likewise.
8210 (vcmpleq_n): Likewise.
8211 (vcmpleq): Likewise.
8212 (vcmpleq): Likewise.
8213 (vcmpltq_n): Likewise.
8214 (vcmpltq_n): Likewise.
8215 (vcmpltq): Likewise.
8216 (vcmpltq): Likewise.
8217 (vcmpneq_n): Likewise.
8218 (vcmpneq_n): Likewise.
8219 (vcmpneq): Likewise.
8220 (vcmpneq): Likewise.
8223 (vcmulq_rot180): Likewise.
8224 (vcmulq_rot180): Likewise.
8225 (vcmulq_rot270): Likewise.
8226 (vcmulq_rot270): Likewise.
8227 (vcmulq_rot90): Likewise.
8228 (vcmulq_rot90): Likewise.
8231 (vmaxnmaq): Likewise.
8232 (vmaxnmaq): Likewise.
8233 (vmaxnmavq): Likewise.
8234 (vmaxnmavq): Likewise.
8235 (vmaxnmq): Likewise.
8236 (vmaxnmq): Likewise.
8237 (vmaxnmvq): Likewise.
8238 (vmaxnmvq): Likewise.
8239 (vminnmaq): Likewise.
8240 (vminnmaq): Likewise.
8241 (vminnmavq): Likewise.
8242 (vminnmavq): Likewise.
8243 (vminnmq): Likewise.
8244 (vminnmq): Likewise.
8245 (vminnmvq): Likewise.
8246 (vminnmvq): Likewise.
8247 (vbicq_n): Likewise.
8248 (vqmovntq): Likewise.
8249 (vqmovntq): Likewise.
8250 (vqmovnbq): Likewise.
8251 (vqmovnbq): Likewise.
8252 (vmulltq_poly): Likewise.
8253 (vmulltq_poly): Likewise.
8254 (vmullbq_poly): Likewise.
8255 (vmullbq_poly): Likewise.
8256 (vmovntq): Likewise.
8257 (vmovntq): Likewise.
8258 (vmovnbq): Likewise.
8259 (vmovnbq): Likewise.
8260 (vmlaldavxq): Likewise.
8261 (vmlaldavxq): Likewise.
8262 (vqmovuntq): Likewise.
8263 (vqmovuntq): Likewise.
8264 (vshlltq_n): Likewise.
8265 (vshlltq_n): Likewise.
8266 (vshllbq_n): Likewise.
8267 (vshllbq_n): Likewise.
8268 (vorrq_n): Likewise.
8269 (vorrq_n): Likewise.
8270 (vmlaldavq): Likewise.
8271 (vmlaldavq): Likewise.
8272 (vqmovunbq): Likewise.
8273 (vqmovunbq): Likewise.
8274 (vqdmulltq_n): Likewise.
8275 (vqdmulltq_n): Likewise.
8276 (vqdmulltq): Likewise.
8277 (vqdmulltq): Likewise.
8278 (vqdmullbq_n): Likewise.
8279 (vqdmullbq_n): Likewise.
8280 (vqdmullbq): Likewise.
8281 (vqdmullbq): Likewise.
8282 (vaddlvaq): Likewise.
8283 (vaddlvaq): Likewise.
8284 (vrmlaldavhq): Likewise.
8285 (vrmlaldavhq): Likewise.
8286 (vrmlaldavhxq): Likewise.
8287 (vrmlaldavhxq): Likewise.
8288 (vrmlsldavhq): Likewise.
8289 (vrmlsldavhq): Likewise.
8290 (vrmlsldavhxq): Likewise.
8291 (vrmlsldavhxq): Likewise.
8292 (vmlsldavxq): Likewise.
8293 (vmlsldavxq): Likewise.
8294 (vmlsldavq): Likewise.
8295 (vmlsldavq): Likewise.
8296 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
8297 (BINOP_NONE_NONE_NONE): Likewise.
8298 (BINOP_UNONE_NONE_NONE): Likewise.
8299 (BINOP_UNONE_UNONE_IMM): Likewise.
8300 (BINOP_UNONE_UNONE_NONE): Likewise.
8301 (BINOP_UNONE_UNONE_UNONE): Likewise.
8302 * config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
8303 (mve_vaddlvaq_<supf>v4si): Likewise.
8304 (mve_vaddq_n_f<mode>): Likewise.
8305 (mve_vandq_f<mode>): Likewise.
8306 (mve_vbicq_f<mode>): Likewise.
8307 (mve_vbicq_n_<supf><mode>): Likewise.
8308 (mve_vcaddq_rot270_f<mode>): Likewise.
8309 (mve_vcaddq_rot90_f<mode>): Likewise.
8310 (mve_vcmpeqq_f<mode>): Likewise.
8311 (mve_vcmpeqq_n_f<mode>): Likewise.
8312 (mve_vcmpgeq_f<mode>): Likewise.
8313 (mve_vcmpgeq_n_f<mode>): Likewise.
8314 (mve_vcmpgtq_f<mode>): Likewise.
8315 (mve_vcmpgtq_n_f<mode>): Likewise.
8316 (mve_vcmpleq_f<mode>): Likewise.
8317 (mve_vcmpleq_n_f<mode>): Likewise.
8318 (mve_vcmpltq_f<mode>): Likewise.
8319 (mve_vcmpltq_n_f<mode>): Likewise.
8320 (mve_vcmpneq_f<mode>): Likewise.
8321 (mve_vcmpneq_n_f<mode>): Likewise.
8322 (mve_vcmulq_f<mode>): Likewise.
8323 (mve_vcmulq_rot180_f<mode>): Likewise.
8324 (mve_vcmulq_rot270_f<mode>): Likewise.
8325 (mve_vcmulq_rot90_f<mode>): Likewise.
8326 (mve_vctp<mode1>q_mhi): Likewise.
8327 (mve_vcvtbq_f16_f32v8hf): Likewise.
8328 (mve_vcvttq_f16_f32v8hf): Likewise.
8329 (mve_veorq_f<mode>): Likewise.
8330 (mve_vmaxnmaq_f<mode>): Likewise.
8331 (mve_vmaxnmavq_f<mode>): Likewise.
8332 (mve_vmaxnmq_f<mode>): Likewise.
8333 (mve_vmaxnmvq_f<mode>): Likewise.
8334 (mve_vminnmaq_f<mode>): Likewise.
8335 (mve_vminnmavq_f<mode>): Likewise.
8336 (mve_vminnmq_f<mode>): Likewise.
8337 (mve_vminnmvq_f<mode>): Likewise.
8338 (mve_vmlaldavq_<supf><mode>): Likewise.
8339 (mve_vmlaldavxq_<supf><mode>): Likewise.
8340 (mve_vmlsldavq_s<mode>): Likewise.
8341 (mve_vmlsldavxq_s<mode>): Likewise.
8342 (mve_vmovnbq_<supf><mode>): Likewise.
8343 (mve_vmovntq_<supf><mode>): Likewise.
8344 (mve_vmulq_f<mode>): Likewise.
8345 (mve_vmulq_n_f<mode>): Likewise.
8346 (mve_vornq_f<mode>): Likewise.
8347 (mve_vorrq_f<mode>): Likewise.
8348 (mve_vorrq_n_<supf><mode>): Likewise.
8349 (mve_vqdmullbq_n_s<mode>): Likewise.
8350 (mve_vqdmullbq_s<mode>): Likewise.
8351 (mve_vqdmulltq_n_s<mode>): Likewise.
8352 (mve_vqdmulltq_s<mode>): Likewise.
8353 (mve_vqmovnbq_<supf><mode>): Likewise.
8354 (mve_vqmovntq_<supf><mode>): Likewise.
8355 (mve_vqmovunbq_s<mode>): Likewise.
8356 (mve_vqmovuntq_s<mode>): Likewise.
8357 (mve_vrmlaldavhxq_sv4si): Likewise.
8358 (mve_vrmlsldavhq_sv4si): Likewise.
8359 (mve_vrmlsldavhxq_sv4si): Likewise.
8360 (mve_vshllbq_n_<supf><mode>): Likewise.
8361 (mve_vshlltq_n_<supf><mode>): Likewise.
8362 (mve_vsubq_f<mode>): Likewise.
8363 (mve_vmulltq_poly_p<mode>): Likewise.
8364 (mve_vmullbq_poly_p<mode>): Likewise.
8365 (mve_vrmlaldavhq_<supf>v4si): Likewise.
8367 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8368 Mihail Ionescu <mihail.ionescu@arm.com>
8369 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8371 * config/arm/arm_mve.h (vsubq_u8): Define macro.
8372 (vsubq_n_u8): Likewise.
8373 (vrmulhq_u8): Likewise.
8374 (vrhaddq_u8): Likewise.
8375 (vqsubq_u8): Likewise.
8376 (vqsubq_n_u8): Likewise.
8377 (vqaddq_u8): Likewise.
8378 (vqaddq_n_u8): Likewise.
8379 (vorrq_u8): Likewise.
8380 (vornq_u8): Likewise.
8381 (vmulq_u8): Likewise.
8382 (vmulq_n_u8): Likewise.
8383 (vmulltq_int_u8): Likewise.
8384 (vmullbq_int_u8): Likewise.
8385 (vmulhq_u8): Likewise.
8386 (vmladavq_u8): Likewise.
8387 (vminvq_u8): Likewise.
8388 (vminq_u8): Likewise.
8389 (vmaxvq_u8): Likewise.
8390 (vmaxq_u8): Likewise.
8391 (vhsubq_u8): Likewise.
8392 (vhsubq_n_u8): Likewise.
8393 (vhaddq_u8): Likewise.
8394 (vhaddq_n_u8): Likewise.
8395 (veorq_u8): Likewise.
8396 (vcmpneq_n_u8): Likewise.
8397 (vcmphiq_u8): Likewise.
8398 (vcmphiq_n_u8): Likewise.
8399 (vcmpeqq_u8): Likewise.
8400 (vcmpeqq_n_u8): Likewise.
8401 (vcmpcsq_u8): Likewise.
8402 (vcmpcsq_n_u8): Likewise.
8403 (vcaddq_rot90_u8): Likewise.
8404 (vcaddq_rot270_u8): Likewise.
8405 (vbicq_u8): Likewise.
8406 (vandq_u8): Likewise.
8407 (vaddvq_p_u8): Likewise.
8408 (vaddvaq_u8): Likewise.
8409 (vaddq_n_u8): Likewise.
8410 (vabdq_u8): Likewise.
8411 (vshlq_r_u8): Likewise.
8412 (vrshlq_u8): Likewise.
8413 (vrshlq_n_u8): Likewise.
8414 (vqshlq_u8): Likewise.
8415 (vqshlq_r_u8): Likewise.
8416 (vqrshlq_u8): Likewise.
8417 (vqrshlq_n_u8): Likewise.
8418 (vminavq_s8): Likewise.
8419 (vminaq_s8): Likewise.
8420 (vmaxavq_s8): Likewise.
8421 (vmaxaq_s8): Likewise.
8422 (vbrsrq_n_u8): Likewise.
8423 (vshlq_n_u8): Likewise.
8424 (vrshrq_n_u8): Likewise.
8425 (vqshlq_n_u8): Likewise.
8426 (vcmpneq_n_s8): Likewise.
8427 (vcmpltq_s8): Likewise.
8428 (vcmpltq_n_s8): Likewise.
8429 (vcmpleq_s8): Likewise.
8430 (vcmpleq_n_s8): Likewise.
8431 (vcmpgtq_s8): Likewise.
8432 (vcmpgtq_n_s8): Likewise.
8433 (vcmpgeq_s8): Likewise.
8434 (vcmpgeq_n_s8): Likewise.
8435 (vcmpeqq_s8): Likewise.
8436 (vcmpeqq_n_s8): Likewise.
8437 (vqshluq_n_s8): Likewise.
8438 (vaddvq_p_s8): Likewise.
8439 (vsubq_s8): Likewise.
8440 (vsubq_n_s8): Likewise.
8441 (vshlq_r_s8): Likewise.
8442 (vrshlq_s8): Likewise.
8443 (vrshlq_n_s8): Likewise.
8444 (vrmulhq_s8): Likewise.
8445 (vrhaddq_s8): Likewise.
8446 (vqsubq_s8): Likewise.
8447 (vqsubq_n_s8): Likewise.
8448 (vqshlq_s8): Likewise.
8449 (vqshlq_r_s8): Likewise.
8450 (vqrshlq_s8): Likewise.
8451 (vqrshlq_n_s8): Likewise.
8452 (vqrdmulhq_s8): Likewise.
8453 (vqrdmulhq_n_s8): Likewise.
8454 (vqdmulhq_s8): Likewise.
8455 (vqdmulhq_n_s8): Likewise.
8456 (vqaddq_s8): Likewise.
8457 (vqaddq_n_s8): Likewise.
8458 (vorrq_s8): Likewise.
8459 (vornq_s8): Likewise.
8460 (vmulq_s8): Likewise.
8461 (vmulq_n_s8): Likewise.
8462 (vmulltq_int_s8): Likewise.
8463 (vmullbq_int_s8): Likewise.
8464 (vmulhq_s8): Likewise.
8465 (vmlsdavxq_s8): Likewise.
8466 (vmlsdavq_s8): Likewise.
8467 (vmladavxq_s8): Likewise.
8468 (vmladavq_s8): Likewise.
8469 (vminvq_s8): Likewise.
8470 (vminq_s8): Likewise.
8471 (vmaxvq_s8): Likewise.
8472 (vmaxq_s8): Likewise.
8473 (vhsubq_s8): Likewise.
8474 (vhsubq_n_s8): Likewise.
8475 (vhcaddq_rot90_s8): Likewise.
8476 (vhcaddq_rot270_s8): Likewise.
8477 (vhaddq_s8): Likewise.
8478 (vhaddq_n_s8): Likewise.
8479 (veorq_s8): Likewise.
8480 (vcaddq_rot90_s8): Likewise.
8481 (vcaddq_rot270_s8): Likewise.
8482 (vbrsrq_n_s8): Likewise.
8483 (vbicq_s8): Likewise.
8484 (vandq_s8): Likewise.
8485 (vaddvaq_s8): Likewise.
8486 (vaddq_n_s8): Likewise.
8487 (vabdq_s8): Likewise.
8488 (vshlq_n_s8): Likewise.
8489 (vrshrq_n_s8): Likewise.
8490 (vqshlq_n_s8): Likewise.
8491 (vsubq_u16): Likewise.
8492 (vsubq_n_u16): Likewise.
8493 (vrmulhq_u16): Likewise.
8494 (vrhaddq_u16): Likewise.
8495 (vqsubq_u16): Likewise.
8496 (vqsubq_n_u16): Likewise.
8497 (vqaddq_u16): Likewise.
8498 (vqaddq_n_u16): Likewise.
8499 (vorrq_u16): Likewise.
8500 (vornq_u16): Likewise.
8501 (vmulq_u16): Likewise.
8502 (vmulq_n_u16): Likewise.
8503 (vmulltq_int_u16): Likewise.
8504 (vmullbq_int_u16): Likewise.
8505 (vmulhq_u16): Likewise.
8506 (vmladavq_u16): Likewise.
8507 (vminvq_u16): Likewise.
8508 (vminq_u16): Likewise.
8509 (vmaxvq_u16): Likewise.
8510 (vmaxq_u16): Likewise.
8511 (vhsubq_u16): Likewise.
8512 (vhsubq_n_u16): Likewise.
8513 (vhaddq_u16): Likewise.
8514 (vhaddq_n_u16): Likewise.
8515 (veorq_u16): Likewise.
8516 (vcmpneq_n_u16): Likewise.
8517 (vcmphiq_u16): Likewise.
8518 (vcmphiq_n_u16): Likewise.
8519 (vcmpeqq_u16): Likewise.
8520 (vcmpeqq_n_u16): Likewise.
8521 (vcmpcsq_u16): Likewise.
8522 (vcmpcsq_n_u16): Likewise.
8523 (vcaddq_rot90_u16): Likewise.
8524 (vcaddq_rot270_u16): Likewise.
8525 (vbicq_u16): Likewise.
8526 (vandq_u16): Likewise.
8527 (vaddvq_p_u16): Likewise.
8528 (vaddvaq_u16): Likewise.
8529 (vaddq_n_u16): Likewise.
8530 (vabdq_u16): Likewise.
8531 (vshlq_r_u16): Likewise.
8532 (vrshlq_u16): Likewise.
8533 (vrshlq_n_u16): Likewise.
8534 (vqshlq_u16): Likewise.
8535 (vqshlq_r_u16): Likewise.
8536 (vqrshlq_u16): Likewise.
8537 (vqrshlq_n_u16): Likewise.
8538 (vminavq_s16): Likewise.
8539 (vminaq_s16): Likewise.
8540 (vmaxavq_s16): Likewise.
8541 (vmaxaq_s16): Likewise.
8542 (vbrsrq_n_u16): Likewise.
8543 (vshlq_n_u16): Likewise.
8544 (vrshrq_n_u16): Likewise.
8545 (vqshlq_n_u16): Likewise.
8546 (vcmpneq_n_s16): Likewise.
8547 (vcmpltq_s16): Likewise.
8548 (vcmpltq_n_s16): Likewise.
8549 (vcmpleq_s16): Likewise.
8550 (vcmpleq_n_s16): Likewise.
8551 (vcmpgtq_s16): Likewise.
8552 (vcmpgtq_n_s16): Likewise.
8553 (vcmpgeq_s16): Likewise.
8554 (vcmpgeq_n_s16): Likewise.
8555 (vcmpeqq_s16): Likewise.
8556 (vcmpeqq_n_s16): Likewise.
8557 (vqshluq_n_s16): Likewise.
8558 (vaddvq_p_s16): Likewise.
8559 (vsubq_s16): Likewise.
8560 (vsubq_n_s16): Likewise.
8561 (vshlq_r_s16): Likewise.
8562 (vrshlq_s16): Likewise.
8563 (vrshlq_n_s16): Likewise.
8564 (vrmulhq_s16): Likewise.
8565 (vrhaddq_s16): Likewise.
8566 (vqsubq_s16): Likewise.
8567 (vqsubq_n_s16): Likewise.
8568 (vqshlq_s16): Likewise.
8569 (vqshlq_r_s16): Likewise.
8570 (vqrshlq_s16): Likewise.
8571 (vqrshlq_n_s16): Likewise.
8572 (vqrdmulhq_s16): Likewise.
8573 (vqrdmulhq_n_s16): Likewise.
8574 (vqdmulhq_s16): Likewise.
8575 (vqdmulhq_n_s16): Likewise.
8576 (vqaddq_s16): Likewise.
8577 (vqaddq_n_s16): Likewise.
8578 (vorrq_s16): Likewise.
8579 (vornq_s16): Likewise.
8580 (vmulq_s16): Likewise.
8581 (vmulq_n_s16): Likewise.
8582 (vmulltq_int_s16): Likewise.
8583 (vmullbq_int_s16): Likewise.
8584 (vmulhq_s16): Likewise.
8585 (vmlsdavxq_s16): Likewise.
8586 (vmlsdavq_s16): Likewise.
8587 (vmladavxq_s16): Likewise.
8588 (vmladavq_s16): Likewise.
8589 (vminvq_s16): Likewise.
8590 (vminq_s16): Likewise.
8591 (vmaxvq_s16): Likewise.
8592 (vmaxq_s16): Likewise.
8593 (vhsubq_s16): Likewise.
8594 (vhsubq_n_s16): Likewise.
8595 (vhcaddq_rot90_s16): Likewise.
8596 (vhcaddq_rot270_s16): Likewise.
8597 (vhaddq_s16): Likewise.
8598 (vhaddq_n_s16): Likewise.
8599 (veorq_s16): Likewise.
8600 (vcaddq_rot90_s16): Likewise.
8601 (vcaddq_rot270_s16): Likewise.
8602 (vbrsrq_n_s16): Likewise.
8603 (vbicq_s16): Likewise.
8604 (vandq_s16): Likewise.
8605 (vaddvaq_s16): Likewise.
8606 (vaddq_n_s16): Likewise.
8607 (vabdq_s16): Likewise.
8608 (vshlq_n_s16): Likewise.
8609 (vrshrq_n_s16): Likewise.
8610 (vqshlq_n_s16): Likewise.
8611 (vsubq_u32): Likewise.
8612 (vsubq_n_u32): Likewise.
8613 (vrmulhq_u32): Likewise.
8614 (vrhaddq_u32): Likewise.
8615 (vqsubq_u32): Likewise.
8616 (vqsubq_n_u32): Likewise.
8617 (vqaddq_u32): Likewise.
8618 (vqaddq_n_u32): Likewise.
8619 (vorrq_u32): Likewise.
8620 (vornq_u32): Likewise.
8621 (vmulq_u32): Likewise.
8622 (vmulq_n_u32): Likewise.
8623 (vmulltq_int_u32): Likewise.
8624 (vmullbq_int_u32): Likewise.
8625 (vmulhq_u32): Likewise.
8626 (vmladavq_u32): Likewise.
8627 (vminvq_u32): Likewise.
8628 (vminq_u32): Likewise.
8629 (vmaxvq_u32): Likewise.
8630 (vmaxq_u32): Likewise.
8631 (vhsubq_u32): Likewise.
8632 (vhsubq_n_u32): Likewise.
8633 (vhaddq_u32): Likewise.
8634 (vhaddq_n_u32): Likewise.
8635 (veorq_u32): Likewise.
8636 (vcmpneq_n_u32): Likewise.
8637 (vcmphiq_u32): Likewise.
8638 (vcmphiq_n_u32): Likewise.
8639 (vcmpeqq_u32): Likewise.
8640 (vcmpeqq_n_u32): Likewise.
8641 (vcmpcsq_u32): Likewise.
8642 (vcmpcsq_n_u32): Likewise.
8643 (vcaddq_rot90_u32): Likewise.
8644 (vcaddq_rot270_u32): Likewise.
8645 (vbicq_u32): Likewise.
8646 (vandq_u32): Likewise.
8647 (vaddvq_p_u32): Likewise.
8648 (vaddvaq_u32): Likewise.
8649 (vaddq_n_u32): Likewise.
8650 (vabdq_u32): Likewise.
8651 (vshlq_r_u32): Likewise.
8652 (vrshlq_u32): Likewise.
8653 (vrshlq_n_u32): Likewise.
8654 (vqshlq_u32): Likewise.
8655 (vqshlq_r_u32): Likewise.
8656 (vqrshlq_u32): Likewise.
8657 (vqrshlq_n_u32): Likewise.
8658 (vminavq_s32): Likewise.
8659 (vminaq_s32): Likewise.
8660 (vmaxavq_s32): Likewise.
8661 (vmaxaq_s32): Likewise.
8662 (vbrsrq_n_u32): Likewise.
8663 (vshlq_n_u32): Likewise.
8664 (vrshrq_n_u32): Likewise.
8665 (vqshlq_n_u32): Likewise.
8666 (vcmpneq_n_s32): Likewise.
8667 (vcmpltq_s32): Likewise.
8668 (vcmpltq_n_s32): Likewise.
8669 (vcmpleq_s32): Likewise.
8670 (vcmpleq_n_s32): Likewise.
8671 (vcmpgtq_s32): Likewise.
8672 (vcmpgtq_n_s32): Likewise.
8673 (vcmpgeq_s32): Likewise.
8674 (vcmpgeq_n_s32): Likewise.
8675 (vcmpeqq_s32): Likewise.
8676 (vcmpeqq_n_s32): Likewise.
8677 (vqshluq_n_s32): Likewise.
8678 (vaddvq_p_s32): Likewise.
8679 (vsubq_s32): Likewise.
8680 (vsubq_n_s32): Likewise.
8681 (vshlq_r_s32): Likewise.
8682 (vrshlq_s32): Likewise.
8683 (vrshlq_n_s32): Likewise.
8684 (vrmulhq_s32): Likewise.
8685 (vrhaddq_s32): Likewise.
8686 (vqsubq_s32): Likewise.
8687 (vqsubq_n_s32): Likewise.
8688 (vqshlq_s32): Likewise.
8689 (vqshlq_r_s32): Likewise.
8690 (vqrshlq_s32): Likewise.
8691 (vqrshlq_n_s32): Likewise.
8692 (vqrdmulhq_s32): Likewise.
8693 (vqrdmulhq_n_s32): Likewise.
8694 (vqdmulhq_s32): Likewise.
8695 (vqdmulhq_n_s32): Likewise.
8696 (vqaddq_s32): Likewise.
8697 (vqaddq_n_s32): Likewise.
8698 (vorrq_s32): Likewise.
8699 (vornq_s32): Likewise.
8700 (vmulq_s32): Likewise.
8701 (vmulq_n_s32): Likewise.
8702 (vmulltq_int_s32): Likewise.
8703 (vmullbq_int_s32): Likewise.
8704 (vmulhq_s32): Likewise.
8705 (vmlsdavxq_s32): Likewise.
8706 (vmlsdavq_s32): Likewise.
8707 (vmladavxq_s32): Likewise.
8708 (vmladavq_s32): Likewise.
8709 (vminvq_s32): Likewise.
8710 (vminq_s32): Likewise.
8711 (vmaxvq_s32): Likewise.
8712 (vmaxq_s32): Likewise.
8713 (vhsubq_s32): Likewise.
8714 (vhsubq_n_s32): Likewise.
8715 (vhcaddq_rot90_s32): Likewise.
8716 (vhcaddq_rot270_s32): Likewise.
8717 (vhaddq_s32): Likewise.
8718 (vhaddq_n_s32): Likewise.
8719 (veorq_s32): Likewise.
8720 (vcaddq_rot90_s32): Likewise.
8721 (vcaddq_rot270_s32): Likewise.
8722 (vbrsrq_n_s32): Likewise.
8723 (vbicq_s32): Likewise.
8724 (vandq_s32): Likewise.
8725 (vaddvaq_s32): Likewise.
8726 (vaddq_n_s32): Likewise.
8727 (vabdq_s32): Likewise.
8728 (vshlq_n_s32): Likewise.
8729 (vrshrq_n_s32): Likewise.
8730 (vqshlq_n_s32): Likewise.
8731 (__arm_vsubq_u8): Define intrinsic.
8732 (__arm_vsubq_n_u8): Likewise.
8733 (__arm_vrmulhq_u8): Likewise.
8734 (__arm_vrhaddq_u8): Likewise.
8735 (__arm_vqsubq_u8): Likewise.
8736 (__arm_vqsubq_n_u8): Likewise.
8737 (__arm_vqaddq_u8): Likewise.
8738 (__arm_vqaddq_n_u8): Likewise.
8739 (__arm_vorrq_u8): Likewise.
8740 (__arm_vornq_u8): Likewise.
8741 (__arm_vmulq_u8): Likewise.
8742 (__arm_vmulq_n_u8): Likewise.
8743 (__arm_vmulltq_int_u8): Likewise.
8744 (__arm_vmullbq_int_u8): Likewise.
8745 (__arm_vmulhq_u8): Likewise.
8746 (__arm_vmladavq_u8): Likewise.
8747 (__arm_vminvq_u8): Likewise.
8748 (__arm_vminq_u8): Likewise.
8749 (__arm_vmaxvq_u8): Likewise.
8750 (__arm_vmaxq_u8): Likewise.
8751 (__arm_vhsubq_u8): Likewise.
8752 (__arm_vhsubq_n_u8): Likewise.
8753 (__arm_vhaddq_u8): Likewise.
8754 (__arm_vhaddq_n_u8): Likewise.
8755 (__arm_veorq_u8): Likewise.
8756 (__arm_vcmpneq_n_u8): Likewise.
8757 (__arm_vcmphiq_u8): Likewise.
8758 (__arm_vcmphiq_n_u8): Likewise.
8759 (__arm_vcmpeqq_u8): Likewise.
8760 (__arm_vcmpeqq_n_u8): Likewise.
8761 (__arm_vcmpcsq_u8): Likewise.
8762 (__arm_vcmpcsq_n_u8): Likewise.
8763 (__arm_vcaddq_rot90_u8): Likewise.
8764 (__arm_vcaddq_rot270_u8): Likewise.
8765 (__arm_vbicq_u8): Likewise.
8766 (__arm_vandq_u8): Likewise.
8767 (__arm_vaddvq_p_u8): Likewise.
8768 (__arm_vaddvaq_u8): Likewise.
8769 (__arm_vaddq_n_u8): Likewise.
8770 (__arm_vabdq_u8): Likewise.
8771 (__arm_vshlq_r_u8): Likewise.
8772 (__arm_vrshlq_u8): Likewise.
8773 (__arm_vrshlq_n_u8): Likewise.
8774 (__arm_vqshlq_u8): Likewise.
8775 (__arm_vqshlq_r_u8): Likewise.
8776 (__arm_vqrshlq_u8): Likewise.
8777 (__arm_vqrshlq_n_u8): Likewise.
8778 (__arm_vminavq_s8): Likewise.
8779 (__arm_vminaq_s8): Likewise.
8780 (__arm_vmaxavq_s8): Likewise.
8781 (__arm_vmaxaq_s8): Likewise.
8782 (__arm_vbrsrq_n_u8): Likewise.
8783 (__arm_vshlq_n_u8): Likewise.
8784 (__arm_vrshrq_n_u8): Likewise.
8785 (__arm_vqshlq_n_u8): Likewise.
8786 (__arm_vcmpneq_n_s8): Likewise.
8787 (__arm_vcmpltq_s8): Likewise.
8788 (__arm_vcmpltq_n_s8): Likewise.
8789 (__arm_vcmpleq_s8): Likewise.
8790 (__arm_vcmpleq_n_s8): Likewise.
8791 (__arm_vcmpgtq_s8): Likewise.
8792 (__arm_vcmpgtq_n_s8): Likewise.
8793 (__arm_vcmpgeq_s8): Likewise.
8794 (__arm_vcmpgeq_n_s8): Likewise.
8795 (__arm_vcmpeqq_s8): Likewise.
8796 (__arm_vcmpeqq_n_s8): Likewise.
8797 (__arm_vqshluq_n_s8): Likewise.
8798 (__arm_vaddvq_p_s8): Likewise.
8799 (__arm_vsubq_s8): Likewise.
8800 (__arm_vsubq_n_s8): Likewise.
8801 (__arm_vshlq_r_s8): Likewise.
8802 (__arm_vrshlq_s8): Likewise.
8803 (__arm_vrshlq_n_s8): Likewise.
8804 (__arm_vrmulhq_s8): Likewise.
8805 (__arm_vrhaddq_s8): Likewise.
8806 (__arm_vqsubq_s8): Likewise.
8807 (__arm_vqsubq_n_s8): Likewise.
8808 (__arm_vqshlq_s8): Likewise.
8809 (__arm_vqshlq_r_s8): Likewise.
8810 (__arm_vqrshlq_s8): Likewise.
8811 (__arm_vqrshlq_n_s8): Likewise.
8812 (__arm_vqrdmulhq_s8): Likewise.
8813 (__arm_vqrdmulhq_n_s8): Likewise.
8814 (__arm_vqdmulhq_s8): Likewise.
8815 (__arm_vqdmulhq_n_s8): Likewise.
8816 (__arm_vqaddq_s8): Likewise.
8817 (__arm_vqaddq_n_s8): Likewise.
8818 (__arm_vorrq_s8): Likewise.
8819 (__arm_vornq_s8): Likewise.
8820 (__arm_vmulq_s8): Likewise.
8821 (__arm_vmulq_n_s8): Likewise.
8822 (__arm_vmulltq_int_s8): Likewise.
8823 (__arm_vmullbq_int_s8): Likewise.
8824 (__arm_vmulhq_s8): Likewise.
8825 (__arm_vmlsdavxq_s8): Likewise.
8826 (__arm_vmlsdavq_s8): Likewise.
8827 (__arm_vmladavxq_s8): Likewise.
8828 (__arm_vmladavq_s8): Likewise.
8829 (__arm_vminvq_s8): Likewise.
8830 (__arm_vminq_s8): Likewise.
8831 (__arm_vmaxvq_s8): Likewise.
8832 (__arm_vmaxq_s8): Likewise.
8833 (__arm_vhsubq_s8): Likewise.
8834 (__arm_vhsubq_n_s8): Likewise.
8835 (__arm_vhcaddq_rot90_s8): Likewise.
8836 (__arm_vhcaddq_rot270_s8): Likewise.
8837 (__arm_vhaddq_s8): Likewise.
8838 (__arm_vhaddq_n_s8): Likewise.
8839 (__arm_veorq_s8): Likewise.
8840 (__arm_vcaddq_rot90_s8): Likewise.
8841 (__arm_vcaddq_rot270_s8): Likewise.
8842 (__arm_vbrsrq_n_s8): Likewise.
8843 (__arm_vbicq_s8): Likewise.
8844 (__arm_vandq_s8): Likewise.
8845 (__arm_vaddvaq_s8): Likewise.
8846 (__arm_vaddq_n_s8): Likewise.
8847 (__arm_vabdq_s8): Likewise.
8848 (__arm_vshlq_n_s8): Likewise.
8849 (__arm_vrshrq_n_s8): Likewise.
8850 (__arm_vqshlq_n_s8): Likewise.
8851 (__arm_vsubq_u16): Likewise.
8852 (__arm_vsubq_n_u16): Likewise.
8853 (__arm_vrmulhq_u16): Likewise.
8854 (__arm_vrhaddq_u16): Likewise.
8855 (__arm_vqsubq_u16): Likewise.
8856 (__arm_vqsubq_n_u16): Likewise.
8857 (__arm_vqaddq_u16): Likewise.
8858 (__arm_vqaddq_n_u16): Likewise.
8859 (__arm_vorrq_u16): Likewise.
8860 (__arm_vornq_u16): Likewise.
8861 (__arm_vmulq_u16): Likewise.
8862 (__arm_vmulq_n_u16): Likewise.
8863 (__arm_vmulltq_int_u16): Likewise.
8864 (__arm_vmullbq_int_u16): Likewise.
8865 (__arm_vmulhq_u16): Likewise.
8866 (__arm_vmladavq_u16): Likewise.
8867 (__arm_vminvq_u16): Likewise.
8868 (__arm_vminq_u16): Likewise.
8869 (__arm_vmaxvq_u16): Likewise.
8870 (__arm_vmaxq_u16): Likewise.
8871 (__arm_vhsubq_u16): Likewise.
8872 (__arm_vhsubq_n_u16): Likewise.
8873 (__arm_vhaddq_u16): Likewise.
8874 (__arm_vhaddq_n_u16): Likewise.
8875 (__arm_veorq_u16): Likewise.
8876 (__arm_vcmpneq_n_u16): Likewise.
8877 (__arm_vcmphiq_u16): Likewise.
8878 (__arm_vcmphiq_n_u16): Likewise.
8879 (__arm_vcmpeqq_u16): Likewise.
8880 (__arm_vcmpeqq_n_u16): Likewise.
8881 (__arm_vcmpcsq_u16): Likewise.
8882 (__arm_vcmpcsq_n_u16): Likewise.
8883 (__arm_vcaddq_rot90_u16): Likewise.
8884 (__arm_vcaddq_rot270_u16): Likewise.
8885 (__arm_vbicq_u16): Likewise.
8886 (__arm_vandq_u16): Likewise.
8887 (__arm_vaddvq_p_u16): Likewise.
8888 (__arm_vaddvaq_u16): Likewise.
8889 (__arm_vaddq_n_u16): Likewise.
8890 (__arm_vabdq_u16): Likewise.
8891 (__arm_vshlq_r_u16): Likewise.
8892 (__arm_vrshlq_u16): Likewise.
8893 (__arm_vrshlq_n_u16): Likewise.
8894 (__arm_vqshlq_u16): Likewise.
8895 (__arm_vqshlq_r_u16): Likewise.
8896 (__arm_vqrshlq_u16): Likewise.
8897 (__arm_vqrshlq_n_u16): Likewise.
8898 (__arm_vminavq_s16): Likewise.
8899 (__arm_vminaq_s16): Likewise.
8900 (__arm_vmaxavq_s16): Likewise.
8901 (__arm_vmaxaq_s16): Likewise.
8902 (__arm_vbrsrq_n_u16): Likewise.
8903 (__arm_vshlq_n_u16): Likewise.
8904 (__arm_vrshrq_n_u16): Likewise.
8905 (__arm_vqshlq_n_u16): Likewise.
8906 (__arm_vcmpneq_n_s16): Likewise.
8907 (__arm_vcmpltq_s16): Likewise.
8908 (__arm_vcmpltq_n_s16): Likewise.
8909 (__arm_vcmpleq_s16): Likewise.
8910 (__arm_vcmpleq_n_s16): Likewise.
8911 (__arm_vcmpgtq_s16): Likewise.
8912 (__arm_vcmpgtq_n_s16): Likewise.
8913 (__arm_vcmpgeq_s16): Likewise.
8914 (__arm_vcmpgeq_n_s16): Likewise.
8915 (__arm_vcmpeqq_s16): Likewise.
8916 (__arm_vcmpeqq_n_s16): Likewise.
8917 (__arm_vqshluq_n_s16): Likewise.
8918 (__arm_vaddvq_p_s16): Likewise.
8919 (__arm_vsubq_s16): Likewise.
8920 (__arm_vsubq_n_s16): Likewise.
8921 (__arm_vshlq_r_s16): Likewise.
8922 (__arm_vrshlq_s16): Likewise.
8923 (__arm_vrshlq_n_s16): Likewise.
8924 (__arm_vrmulhq_s16): Likewise.
8925 (__arm_vrhaddq_s16): Likewise.
8926 (__arm_vqsubq_s16): Likewise.
8927 (__arm_vqsubq_n_s16): Likewise.
8928 (__arm_vqshlq_s16): Likewise.
8929 (__arm_vqshlq_r_s16): Likewise.
8930 (__arm_vqrshlq_s16): Likewise.
8931 (__arm_vqrshlq_n_s16): Likewise.
8932 (__arm_vqrdmulhq_s16): Likewise.
8933 (__arm_vqrdmulhq_n_s16): Likewise.
8934 (__arm_vqdmulhq_s16): Likewise.
8935 (__arm_vqdmulhq_n_s16): Likewise.
8936 (__arm_vqaddq_s16): Likewise.
8937 (__arm_vqaddq_n_s16): Likewise.
8938 (__arm_vorrq_s16): Likewise.
8939 (__arm_vornq_s16): Likewise.
8940 (__arm_vmulq_s16): Likewise.
8941 (__arm_vmulq_n_s16): Likewise.
8942 (__arm_vmulltq_int_s16): Likewise.
8943 (__arm_vmullbq_int_s16): Likewise.
8944 (__arm_vmulhq_s16): Likewise.
8945 (__arm_vmlsdavxq_s16): Likewise.
8946 (__arm_vmlsdavq_s16): Likewise.
8947 (__arm_vmladavxq_s16): Likewise.
8948 (__arm_vmladavq_s16): Likewise.
8949 (__arm_vminvq_s16): Likewise.
8950 (__arm_vminq_s16): Likewise.
8951 (__arm_vmaxvq_s16): Likewise.
8952 (__arm_vmaxq_s16): Likewise.
8953 (__arm_vhsubq_s16): Likewise.
8954 (__arm_vhsubq_n_s16): Likewise.
8955 (__arm_vhcaddq_rot90_s16): Likewise.
8956 (__arm_vhcaddq_rot270_s16): Likewise.
8957 (__arm_vhaddq_s16): Likewise.
8958 (__arm_vhaddq_n_s16): Likewise.
8959 (__arm_veorq_s16): Likewise.
8960 (__arm_vcaddq_rot90_s16): Likewise.
8961 (__arm_vcaddq_rot270_s16): Likewise.
8962 (__arm_vbrsrq_n_s16): Likewise.
8963 (__arm_vbicq_s16): Likewise.
8964 (__arm_vandq_s16): Likewise.
8965 (__arm_vaddvaq_s16): Likewise.
8966 (__arm_vaddq_n_s16): Likewise.
8967 (__arm_vabdq_s16): Likewise.
8968 (__arm_vshlq_n_s16): Likewise.
8969 (__arm_vrshrq_n_s16): Likewise.
8970 (__arm_vqshlq_n_s16): Likewise.
8971 (__arm_vsubq_u32): Likewise.
8972 (__arm_vsubq_n_u32): Likewise.
8973 (__arm_vrmulhq_u32): Likewise.
8974 (__arm_vrhaddq_u32): Likewise.
8975 (__arm_vqsubq_u32): Likewise.
8976 (__arm_vqsubq_n_u32): Likewise.
8977 (__arm_vqaddq_u32): Likewise.
8978 (__arm_vqaddq_n_u32): Likewise.
8979 (__arm_vorrq_u32): Likewise.
8980 (__arm_vornq_u32): Likewise.
8981 (__arm_vmulq_u32): Likewise.
8982 (__arm_vmulq_n_u32): Likewise.
8983 (__arm_vmulltq_int_u32): Likewise.
8984 (__arm_vmullbq_int_u32): Likewise.
8985 (__arm_vmulhq_u32): Likewise.
8986 (__arm_vmladavq_u32): Likewise.
8987 (__arm_vminvq_u32): Likewise.
8988 (__arm_vminq_u32): Likewise.
8989 (__arm_vmaxvq_u32): Likewise.
8990 (__arm_vmaxq_u32): Likewise.
8991 (__arm_vhsubq_u32): Likewise.
8992 (__arm_vhsubq_n_u32): Likewise.
8993 (__arm_vhaddq_u32): Likewise.
8994 (__arm_vhaddq_n_u32): Likewise.
8995 (__arm_veorq_u32): Likewise.
8996 (__arm_vcmpneq_n_u32): Likewise.
8997 (__arm_vcmphiq_u32): Likewise.
8998 (__arm_vcmphiq_n_u32): Likewise.
8999 (__arm_vcmpeqq_u32): Likewise.
9000 (__arm_vcmpeqq_n_u32): Likewise.
9001 (__arm_vcmpcsq_u32): Likewise.
9002 (__arm_vcmpcsq_n_u32): Likewise.
9003 (__arm_vcaddq_rot90_u32): Likewise.
9004 (__arm_vcaddq_rot270_u32): Likewise.
9005 (__arm_vbicq_u32): Likewise.
9006 (__arm_vandq_u32): Likewise.
9007 (__arm_vaddvq_p_u32): Likewise.
9008 (__arm_vaddvaq_u32): Likewise.
9009 (__arm_vaddq_n_u32): Likewise.
9010 (__arm_vabdq_u32): Likewise.
9011 (__arm_vshlq_r_u32): Likewise.
9012 (__arm_vrshlq_u32): Likewise.
9013 (__arm_vrshlq_n_u32): Likewise.
9014 (__arm_vqshlq_u32): Likewise.
9015 (__arm_vqshlq_r_u32): Likewise.
9016 (__arm_vqrshlq_u32): Likewise.
9017 (__arm_vqrshlq_n_u32): Likewise.
9018 (__arm_vminavq_s32): Likewise.
9019 (__arm_vminaq_s32): Likewise.
9020 (__arm_vmaxavq_s32): Likewise.
9021 (__arm_vmaxaq_s32): Likewise.
9022 (__arm_vbrsrq_n_u32): Likewise.
9023 (__arm_vshlq_n_u32): Likewise.
9024 (__arm_vrshrq_n_u32): Likewise.
9025 (__arm_vqshlq_n_u32): Likewise.
9026 (__arm_vcmpneq_n_s32): Likewise.
9027 (__arm_vcmpltq_s32): Likewise.
9028 (__arm_vcmpltq_n_s32): Likewise.
9029 (__arm_vcmpleq_s32): Likewise.
9030 (__arm_vcmpleq_n_s32): Likewise.
9031 (__arm_vcmpgtq_s32): Likewise.
9032 (__arm_vcmpgtq_n_s32): Likewise.
9033 (__arm_vcmpgeq_s32): Likewise.
9034 (__arm_vcmpgeq_n_s32): Likewise.
9035 (__arm_vcmpeqq_s32): Likewise.
9036 (__arm_vcmpeqq_n_s32): Likewise.
9037 (__arm_vqshluq_n_s32): Likewise.
9038 (__arm_vaddvq_p_s32): Likewise.
9039 (__arm_vsubq_s32): Likewise.
9040 (__arm_vsubq_n_s32): Likewise.
9041 (__arm_vshlq_r_s32): Likewise.
9042 (__arm_vrshlq_s32): Likewise.
9043 (__arm_vrshlq_n_s32): Likewise.
9044 (__arm_vrmulhq_s32): Likewise.
9045 (__arm_vrhaddq_s32): Likewise.
9046 (__arm_vqsubq_s32): Likewise.
9047 (__arm_vqsubq_n_s32): Likewise.
9048 (__arm_vqshlq_s32): Likewise.
9049 (__arm_vqshlq_r_s32): Likewise.
9050 (__arm_vqrshlq_s32): Likewise.
9051 (__arm_vqrshlq_n_s32): Likewise.
9052 (__arm_vqrdmulhq_s32): Likewise.
9053 (__arm_vqrdmulhq_n_s32): Likewise.
9054 (__arm_vqdmulhq_s32): Likewise.
9055 (__arm_vqdmulhq_n_s32): Likewise.
9056 (__arm_vqaddq_s32): Likewise.
9057 (__arm_vqaddq_n_s32): Likewise.
9058 (__arm_vorrq_s32): Likewise.
9059 (__arm_vornq_s32): Likewise.
9060 (__arm_vmulq_s32): Likewise.
9061 (__arm_vmulq_n_s32): Likewise.
9062 (__arm_vmulltq_int_s32): Likewise.
9063 (__arm_vmullbq_int_s32): Likewise.
9064 (__arm_vmulhq_s32): Likewise.
9065 (__arm_vmlsdavxq_s32): Likewise.
9066 (__arm_vmlsdavq_s32): Likewise.
9067 (__arm_vmladavxq_s32): Likewise.
9068 (__arm_vmladavq_s32): Likewise.
9069 (__arm_vminvq_s32): Likewise.
9070 (__arm_vminq_s32): Likewise.
9071 (__arm_vmaxvq_s32): Likewise.
9072 (__arm_vmaxq_s32): Likewise.
9073 (__arm_vhsubq_s32): Likewise.
9074 (__arm_vhsubq_n_s32): Likewise.
9075 (__arm_vhcaddq_rot90_s32): Likewise.
9076 (__arm_vhcaddq_rot270_s32): Likewise.
9077 (__arm_vhaddq_s32): Likewise.
9078 (__arm_vhaddq_n_s32): Likewise.
9079 (__arm_veorq_s32): Likewise.
9080 (__arm_vcaddq_rot90_s32): Likewise.
9081 (__arm_vcaddq_rot270_s32): Likewise.
9082 (__arm_vbrsrq_n_s32): Likewise.
9083 (__arm_vbicq_s32): Likewise.
9084 (__arm_vandq_s32): Likewise.
9085 (__arm_vaddvaq_s32): Likewise.
9086 (__arm_vaddq_n_s32): Likewise.
9087 (__arm_vabdq_s32): Likewise.
9088 (__arm_vshlq_n_s32): Likewise.
9089 (__arm_vrshrq_n_s32): Likewise.
9090 (__arm_vqshlq_n_s32): Likewise.
9091 (vsubq): Define polymorphic variant.
9092 (vsubq_n): Likewise.
9093 (vshlq_r): Likewise.
9094 (vrshlq_n): Likewise.
9096 (vrmulhq): Likewise.
9097 (vrhaddq): Likewise.
9098 (vqsubq_n): Likewise.
9101 (vqshlq_r): Likewise.
9102 (vqshluq): Likewise.
9103 (vrshrq_n): Likewise.
9104 (vshlq_n): Likewise.
9105 (vqshluq_n): Likewise.
9106 (vqshlq_n): Likewise.
9107 (vqrshlq_n): Likewise.
9108 (vqrshlq): Likewise.
9109 (vqrdmulhq_n): Likewise.
9110 (vqrdmulhq): Likewise.
9111 (vqdmulhq_n): Likewise.
9112 (vqdmulhq): Likewise.
9113 (vqaddq_n): Likewise.
9115 (vorrq_n): Likewise.
9118 (vmulq_n): Likewise.
9120 (vmulltq_int): Likewise.
9121 (vmullbq_int): Likewise.
9127 (vhsubq_n): Likewise.
9129 (vhcaddq_rot90): Likewise.
9130 (vhcaddq_rot270): Likewise.
9131 (vhaddq_n): Likewise.
9134 (vcaddq_rot90): Likewise.
9135 (vcaddq_rot270): Likewise.
9136 (vbrsrq_n): Likewise.
9137 (vbicq_n): Likewise.
9140 (vaddq_n): Likewise.
9143 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
9144 (BINOP_NONE_NONE_NONE): Likewise.
9145 (BINOP_NONE_NONE_UNONE): Likewise.
9146 (BINOP_UNONE_NONE_IMM): Likewise.
9147 (BINOP_UNONE_NONE_NONE): Likewise.
9148 (BINOP_UNONE_UNONE_IMM): Likewise.
9149 (BINOP_UNONE_UNONE_NONE): Likewise.
9150 (BINOP_UNONE_UNONE_UNONE): Likewise.
9151 * config/arm/constraints.md (Ra): Define constraint to check constant is
9152 in the range of 0 to 7.
9153 (Rg): Define constriant to check the constant is one among 1, 2, 4
9155 * config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern.
9156 (mve_vaddq_n_<supf>): Likewise.
9157 (mve_vaddvaq_<supf>): Likewise.
9158 (mve_vaddvq_p_<supf>): Likewise.
9159 (mve_vandq_<supf>): Likewise.
9160 (mve_vbicq_<supf>): Likewise.
9161 (mve_vbrsrq_n_<supf>): Likewise.
9162 (mve_vcaddq_rot270_<supf>): Likewise.
9163 (mve_vcaddq_rot90_<supf>): Likewise.
9164 (mve_vcmpcsq_n_u): Likewise.
9165 (mve_vcmpcsq_u): Likewise.
9166 (mve_vcmpeqq_n_<supf>): Likewise.
9167 (mve_vcmpeqq_<supf>): Likewise.
9168 (mve_vcmpgeq_n_s): Likewise.
9169 (mve_vcmpgeq_s): Likewise.
9170 (mve_vcmpgtq_n_s): Likewise.
9171 (mve_vcmpgtq_s): Likewise.
9172 (mve_vcmphiq_n_u): Likewise.
9173 (mve_vcmphiq_u): Likewise.
9174 (mve_vcmpleq_n_s): Likewise.
9175 (mve_vcmpleq_s): Likewise.
9176 (mve_vcmpltq_n_s): Likewise.
9177 (mve_vcmpltq_s): Likewise.
9178 (mve_vcmpneq_n_<supf>): Likewise.
9179 (mve_vddupq_n_u): Likewise.
9180 (mve_veorq_<supf>): Likewise.
9181 (mve_vhaddq_n_<supf>): Likewise.
9182 (mve_vhaddq_<supf>): Likewise.
9183 (mve_vhcaddq_rot270_s): Likewise.
9184 (mve_vhcaddq_rot90_s): Likewise.
9185 (mve_vhsubq_n_<supf>): Likewise.
9186 (mve_vhsubq_<supf>): Likewise.
9187 (mve_vidupq_n_u): Likewise.
9188 (mve_vmaxaq_s): Likewise.
9189 (mve_vmaxavq_s): Likewise.
9190 (mve_vmaxq_<supf>): Likewise.
9191 (mve_vmaxvq_<supf>): Likewise.
9192 (mve_vminaq_s): Likewise.
9193 (mve_vminavq_s): Likewise.
9194 (mve_vminq_<supf>): Likewise.
9195 (mve_vminvq_<supf>): Likewise.
9196 (mve_vmladavq_<supf>): Likewise.
9197 (mve_vmladavxq_s): Likewise.
9198 (mve_vmlsdavq_s): Likewise.
9199 (mve_vmlsdavxq_s): Likewise.
9200 (mve_vmulhq_<supf>): Likewise.
9201 (mve_vmullbq_int_<supf>): Likewise.
9202 (mve_vmulltq_int_<supf>): Likewise.
9203 (mve_vmulq_n_<supf>): Likewise.
9204 (mve_vmulq_<supf>): Likewise.
9205 (mve_vornq_<supf>): Likewise.
9206 (mve_vorrq_<supf>): Likewise.
9207 (mve_vqaddq_n_<supf>): Likewise.
9208 (mve_vqaddq_<supf>): Likewise.
9209 (mve_vqdmulhq_n_s): Likewise.
9210 (mve_vqdmulhq_s): Likewise.
9211 (mve_vqrdmulhq_n_s): Likewise.
9212 (mve_vqrdmulhq_s): Likewise.
9213 (mve_vqrshlq_n_<supf>): Likewise.
9214 (mve_vqrshlq_<supf>): Likewise.
9215 (mve_vqshlq_n_<supf>): Likewise.
9216 (mve_vqshlq_r_<supf>): Likewise.
9217 (mve_vqshlq_<supf>): Likewise.
9218 (mve_vqshluq_n_s): Likewise.
9219 (mve_vqsubq_n_<supf>): Likewise.
9220 (mve_vqsubq_<supf>): Likewise.
9221 (mve_vrhaddq_<supf>): Likewise.
9222 (mve_vrmulhq_<supf>): Likewise.
9223 (mve_vrshlq_n_<supf>): Likewise.
9224 (mve_vrshlq_<supf>): Likewise.
9225 (mve_vrshrq_n_<supf>): Likewise.
9226 (mve_vshlq_n_<supf>): Likewise.
9227 (mve_vshlq_r_<supf>): Likewise.
9228 (mve_vsubq_n_<supf>): Likewise.
9229 (mve_vsubq_<supf>): Likewise.
9230 * config/arm/predicates.md (mve_imm_7): Define predicate to check
9231 the matching constraint Ra.
9232 (mve_imm_selective_upto_8): Define predicate to check the matching
9235 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9236 Mihail Ionescu <mihail.ionescu@arm.com>
9237 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9239 * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define
9240 qualifier for binary operands.
9241 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
9242 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
9243 * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro.
9244 (vaddlvq_p_u32): Likewise.
9245 (vcmpneq_s8): Likewise.
9246 (vcmpneq_s16): Likewise.
9247 (vcmpneq_s32): Likewise.
9248 (vcmpneq_u8): Likewise.
9249 (vcmpneq_u16): Likewise.
9250 (vcmpneq_u32): Likewise.
9251 (vshlq_s8): Likewise.
9252 (vshlq_s16): Likewise.
9253 (vshlq_s32): Likewise.
9254 (vshlq_u8): Likewise.
9255 (vshlq_u16): Likewise.
9256 (vshlq_u32): Likewise.
9257 (__arm_vaddlvq_p_s32): Define intrinsic.
9258 (__arm_vaddlvq_p_u32): Likewise.
9259 (__arm_vcmpneq_s8): Likewise.
9260 (__arm_vcmpneq_s16): Likewise.
9261 (__arm_vcmpneq_s32): Likewise.
9262 (__arm_vcmpneq_u8): Likewise.
9263 (__arm_vcmpneq_u16): Likewise.
9264 (__arm_vcmpneq_u32): Likewise.
9265 (__arm_vshlq_s8): Likewise.
9266 (__arm_vshlq_s16): Likewise.
9267 (__arm_vshlq_s32): Likewise.
9268 (__arm_vshlq_u8): Likewise.
9269 (__arm_vshlq_u16): Likewise.
9270 (__arm_vshlq_u32): Likewise.
9271 (vaddlvq_p): Define polymorphic variant.
9272 (vcmpneq): Likewise.
9274 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS):
9276 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
9277 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
9278 * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern.
9279 (mve_vcmpneq_<supf><mode>): Likewise.
9280 (mve_vshlq_<supf><mode>): Likewise.
9282 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9283 Mihail Ionescu <mihail.ionescu@arm.com>
9284 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9286 * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
9287 qualifier for binary operands.
9288 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
9289 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
9290 * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
9291 (vcvtq_n_s32_f32): Likewise.
9292 (vcvtq_n_u16_f16): Likewise.
9293 (vcvtq_n_u32_f32): Likewise.
9294 (vcreateq_u8): Likewise.
9295 (vcreateq_u16): Likewise.
9296 (vcreateq_u32): Likewise.
9297 (vcreateq_u64): Likewise.
9298 (vcreateq_s8): Likewise.
9299 (vcreateq_s16): Likewise.
9300 (vcreateq_s32): Likewise.
9301 (vcreateq_s64): Likewise.
9302 (vshrq_n_s8): Likewise.
9303 (vshrq_n_s16): Likewise.
9304 (vshrq_n_s32): Likewise.
9305 (vshrq_n_u8): Likewise.
9306 (vshrq_n_u16): Likewise.
9307 (vshrq_n_u32): Likewise.
9308 (__arm_vcreateq_u8): Define intrinsic.
9309 (__arm_vcreateq_u16): Likewise.
9310 (__arm_vcreateq_u32): Likewise.
9311 (__arm_vcreateq_u64): Likewise.
9312 (__arm_vcreateq_s8): Likewise.
9313 (__arm_vcreateq_s16): Likewise.
9314 (__arm_vcreateq_s32): Likewise.
9315 (__arm_vcreateq_s64): Likewise.
9316 (__arm_vshrq_n_s8): Likewise.
9317 (__arm_vshrq_n_s16): Likewise.
9318 (__arm_vshrq_n_s32): Likewise.
9319 (__arm_vshrq_n_u8): Likewise.
9320 (__arm_vshrq_n_u16): Likewise.
9321 (__arm_vshrq_n_u32): Likewise.
9322 (__arm_vcvtq_n_s16_f16): Likewise.
9323 (__arm_vcvtq_n_s32_f32): Likewise.
9324 (__arm_vcvtq_n_u16_f16): Likewise.
9325 (__arm_vcvtq_n_u32_f32): Likewise.
9326 (vshrq_n): Define polymorphic variant.
9327 * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
9329 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
9330 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
9331 * config/arm/constraints.md (Rb): Define constraint to check constant is
9332 in the range of 1 to 8.
9333 (Rf): Define constraint to check constant is in the range of 1 to 32.
9334 * config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
9335 (mve_vshrq_n_<supf><mode>): Likewise.
9336 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
9337 * config/arm/predicates.md (mve_imm_8): Define predicate to check
9338 the matching constraint Rb.
9339 (mve_imm_32): Define predicate to check the matching constraint Rf.
9341 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9342 Mihail Ionescu <mihail.ionescu@arm.com>
9343 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9345 * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define
9346 qualifier for binary operands.
9347 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
9348 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9349 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
9350 * config/arm/arm_mve.h (vsubq_n_f16): Define macro.
9351 (vsubq_n_f32): Likewise.
9352 (vbrsrq_n_f16): Likewise.
9353 (vbrsrq_n_f32): Likewise.
9354 (vcvtq_n_f16_s16): Likewise.
9355 (vcvtq_n_f32_s32): Likewise.
9356 (vcvtq_n_f16_u16): Likewise.
9357 (vcvtq_n_f32_u32): Likewise.
9358 (vcreateq_f16): Likewise.
9359 (vcreateq_f32): Likewise.
9360 (__arm_vsubq_n_f16): Define intrinsic.
9361 (__arm_vsubq_n_f32): Likewise.
9362 (__arm_vbrsrq_n_f16): Likewise.
9363 (__arm_vbrsrq_n_f32): Likewise.
9364 (__arm_vcvtq_n_f16_s16): Likewise.
9365 (__arm_vcvtq_n_f32_s32): Likewise.
9366 (__arm_vcvtq_n_f16_u16): Likewise.
9367 (__arm_vcvtq_n_f32_u32): Likewise.
9368 (__arm_vcreateq_f16): Likewise.
9369 (__arm_vcreateq_f32): Likewise.
9370 (vsubq): Define polymorphic variant.
9372 (vcvtq_n): Likewise.
9373 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use
9375 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
9376 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9377 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
9378 * config/arm/constraints.md (Rd): Define constraint to check constant is
9379 in the range of 1 to 16.
9380 * config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern.
9381 mve_vbrsrq_n_f<mode>: Likewise.
9382 mve_vcvtq_n_to_f_<supf><mode>: Likewise.
9383 mve_vcreateq_f<mode>: Likewise.
9384 * config/arm/predicates.md (mve_imm_16): Define predicate to check
9385 the matching constraint Rd.
9387 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9388 Mihail Ionescu <mihail.ionescu@arm.com>
9389 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9391 * config/arm/arm-builtins.c (hi_UP): Define mode.
9392 * config/arm/arm.h (IS_VPR_REGNUM): Move.
9393 * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
9394 (APSRQ_REGNUM): Modify.
9395 (APSRGE_REGNUM): Modify.
9396 * config/arm/arm_mve.h (vctp16q): Define macro.
9397 (vctp32q): Likewise.
9398 (vctp64q): Likewise.
9401 (__arm_vctp16q): Define intrinsic.
9402 (__arm_vctp32q): Likewise.
9403 (__arm_vctp64q): Likewise.
9404 (__arm_vctp8q): Likewise.
9405 (__arm_vpnot): Likewise.
9406 * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
9408 * config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
9409 (mve_vpnothi): Likewise.
9411 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9412 Mihail Ionescu <mihail.ionescu@arm.com>
9413 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9415 * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
9416 * config/arm/arm_mve.h (vdupq_n_s8): Define macro.
9417 (vdupq_n_s16): Likewise.
9418 (vdupq_n_s32): Likewise.
9419 (vabsq_s8): Likewise.
9420 (vabsq_s16): Likewise.
9421 (vabsq_s32): Likewise.
9422 (vclsq_s8): Likewise.
9423 (vclsq_s16): Likewise.
9424 (vclsq_s32): Likewise.
9425 (vclzq_s8): Likewise.
9426 (vclzq_s16): Likewise.
9427 (vclzq_s32): Likewise.
9428 (vnegq_s8): Likewise.
9429 (vnegq_s16): Likewise.
9430 (vnegq_s32): Likewise.
9431 (vaddlvq_s32): Likewise.
9432 (vaddvq_s8): Likewise.
9433 (vaddvq_s16): Likewise.
9434 (vaddvq_s32): Likewise.
9435 (vmovlbq_s8): Likewise.
9436 (vmovlbq_s16): Likewise.
9437 (vmovltq_s8): Likewise.
9438 (vmovltq_s16): Likewise.
9439 (vmvnq_s8): Likewise.
9440 (vmvnq_s16): Likewise.
9441 (vmvnq_s32): Likewise.
9442 (vrev16q_s8): Likewise.
9443 (vrev32q_s8): Likewise.
9444 (vrev32q_s16): Likewise.
9445 (vqabsq_s8): Likewise.
9446 (vqabsq_s16): Likewise.
9447 (vqabsq_s32): Likewise.
9448 (vqnegq_s8): Likewise.
9449 (vqnegq_s16): Likewise.
9450 (vqnegq_s32): Likewise.
9451 (vcvtaq_s16_f16): Likewise.
9452 (vcvtaq_s32_f32): Likewise.
9453 (vcvtnq_s16_f16): Likewise.
9454 (vcvtnq_s32_f32): Likewise.
9455 (vcvtpq_s16_f16): Likewise.
9456 (vcvtpq_s32_f32): Likewise.
9457 (vcvtmq_s16_f16): Likewise.
9458 (vcvtmq_s32_f32): Likewise.
9459 (vmvnq_u8): Likewise.
9460 (vmvnq_u16): Likewise.
9461 (vmvnq_u32): Likewise.
9462 (vdupq_n_u8): Likewise.
9463 (vdupq_n_u16): Likewise.
9464 (vdupq_n_u32): Likewise.
9465 (vclzq_u8): Likewise.
9466 (vclzq_u16): Likewise.
9467 (vclzq_u32): Likewise.
9468 (vaddvq_u8): Likewise.
9469 (vaddvq_u16): Likewise.
9470 (vaddvq_u32): Likewise.
9471 (vrev32q_u8): Likewise.
9472 (vrev32q_u16): Likewise.
9473 (vmovltq_u8): Likewise.
9474 (vmovltq_u16): Likewise.
9475 (vmovlbq_u8): Likewise.
9476 (vmovlbq_u16): Likewise.
9477 (vrev16q_u8): Likewise.
9478 (vaddlvq_u32): Likewise.
9479 (vcvtpq_u16_f16): Likewise.
9480 (vcvtpq_u32_f32): Likewise.
9481 (vcvtnq_u16_f16): Likewise.
9482 (vcvtmq_u16_f16): Likewise.
9483 (vcvtmq_u32_f32): Likewise.
9484 (vcvtaq_u16_f16): Likewise.
9485 (vcvtaq_u32_f32): Likewise.
9486 (__arm_vdupq_n_s8): Define intrinsic.
9487 (__arm_vdupq_n_s16): Likewise.
9488 (__arm_vdupq_n_s32): Likewise.
9489 (__arm_vabsq_s8): Likewise.
9490 (__arm_vabsq_s16): Likewise.
9491 (__arm_vabsq_s32): Likewise.
9492 (__arm_vclsq_s8): Likewise.
9493 (__arm_vclsq_s16): Likewise.
9494 (__arm_vclsq_s32): Likewise.
9495 (__arm_vclzq_s8): Likewise.
9496 (__arm_vclzq_s16): Likewise.
9497 (__arm_vclzq_s32): Likewise.
9498 (__arm_vnegq_s8): Likewise.
9499 (__arm_vnegq_s16): Likewise.
9500 (__arm_vnegq_s32): Likewise.
9501 (__arm_vaddlvq_s32): Likewise.
9502 (__arm_vaddvq_s8): Likewise.
9503 (__arm_vaddvq_s16): Likewise.
9504 (__arm_vaddvq_s32): Likewise.
9505 (__arm_vmovlbq_s8): Likewise.
9506 (__arm_vmovlbq_s16): Likewise.
9507 (__arm_vmovltq_s8): Likewise.
9508 (__arm_vmovltq_s16): Likewise.
9509 (__arm_vmvnq_s8): Likewise.
9510 (__arm_vmvnq_s16): Likewise.
9511 (__arm_vmvnq_s32): Likewise.
9512 (__arm_vrev16q_s8): Likewise.
9513 (__arm_vrev32q_s8): Likewise.
9514 (__arm_vrev32q_s16): Likewise.
9515 (__arm_vqabsq_s8): Likewise.
9516 (__arm_vqabsq_s16): Likewise.
9517 (__arm_vqabsq_s32): Likewise.
9518 (__arm_vqnegq_s8): Likewise.
9519 (__arm_vqnegq_s16): Likewise.
9520 (__arm_vqnegq_s32): Likewise.
9521 (__arm_vmvnq_u8): Likewise.
9522 (__arm_vmvnq_u16): Likewise.
9523 (__arm_vmvnq_u32): Likewise.
9524 (__arm_vdupq_n_u8): Likewise.
9525 (__arm_vdupq_n_u16): Likewise.
9526 (__arm_vdupq_n_u32): Likewise.
9527 (__arm_vclzq_u8): Likewise.
9528 (__arm_vclzq_u16): Likewise.
9529 (__arm_vclzq_u32): Likewise.
9530 (__arm_vaddvq_u8): Likewise.
9531 (__arm_vaddvq_u16): Likewise.
9532 (__arm_vaddvq_u32): Likewise.
9533 (__arm_vrev32q_u8): Likewise.
9534 (__arm_vrev32q_u16): Likewise.
9535 (__arm_vmovltq_u8): Likewise.
9536 (__arm_vmovltq_u16): Likewise.
9537 (__arm_vmovlbq_u8): Likewise.
9538 (__arm_vmovlbq_u16): Likewise.
9539 (__arm_vrev16q_u8): Likewise.
9540 (__arm_vaddlvq_u32): Likewise.
9541 (__arm_vcvtpq_u16_f16): Likewise.
9542 (__arm_vcvtpq_u32_f32): Likewise.
9543 (__arm_vcvtnq_u16_f16): Likewise.
9544 (__arm_vcvtmq_u16_f16): Likewise.
9545 (__arm_vcvtmq_u32_f32): Likewise.
9546 (__arm_vcvtaq_u16_f16): Likewise.
9547 (__arm_vcvtaq_u32_f32): Likewise.
9548 (__arm_vcvtaq_s16_f16): Likewise.
9549 (__arm_vcvtaq_s32_f32): Likewise.
9550 (__arm_vcvtnq_s16_f16): Likewise.
9551 (__arm_vcvtnq_s32_f32): Likewise.
9552 (__arm_vcvtpq_s16_f16): Likewise.
9553 (__arm_vcvtpq_s32_f32): Likewise.
9554 (__arm_vcvtmq_s16_f16): Likewise.
9555 (__arm_vcvtmq_s32_f32): Likewise.
9556 (vdupq_n): Define polymorphic variant.
9561 (vaddlvq): Likewise.
9563 (vmovlbq): Likewise.
9564 (vmovltq): Likewise.
9566 (vrev16q): Likewise.
9567 (vrev32q): Likewise.
9570 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
9571 (UNOP_SNONE_NONE): Likewise.
9572 (UNOP_UNONE_UNONE): Likewise.
9573 (UNOP_UNONE_NONE): Likewise.
9574 * config/arm/constraints.md (e): Define new constriant to allow only
9576 * config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
9577 (mve_vnegq_s<mode>): Likewise.
9578 (mve_vmvnq_<supf><mode>): Likewise.
9579 (mve_vdupq_n_<supf><mode>): Likewise.
9580 (mve_vclzq_<supf><mode>): Likewise.
9581 (mve_vclsq_s<mode>): Likewise.
9582 (mve_vaddvq_<supf><mode>): Likewise.
9583 (mve_vabsq_s<mode>): Likewise.
9584 (mve_vrev32q_<supf><mode>): Likewise.
9585 (mve_vmovltq_<supf><mode>): Likewise.
9586 (mve_vmovlbq_<supf><mode>): Likewise.
9587 (mve_vcvtpq_<supf><mode>): Likewise.
9588 (mve_vcvtnq_<supf><mode>): Likewise.
9589 (mve_vcvtmq_<supf><mode>): Likewise.
9590 (mve_vcvtaq_<supf><mode>): Likewise.
9591 (mve_vrev16q_<supf>v16qi): Likewise.
9592 (mve_vaddlvq_<supf>v4si): Likewise.
9594 2020-03-17 Jakub Jelinek <jakub@redhat.com>
9596 * lra-spills.c (remove_pseudos): Fix up duplicated word issue in
9598 * tree-sra.c (create_access_replacement): Fix up duplicated word issue
9600 * read-rtl-function.c (find_param_by_name,
9601 function_reader::parse_enum_value, function_reader::get_insn_by_uid):
9603 * spellcheck.c (get_edit_distance_cutoff): Likewise.
9604 * tree-data-ref.c (create_ifn_alias_checks): Likewise.
9605 * tree.def (SWITCH_EXPR): Likewise.
9606 * selftest.c (assert_str_contains): Likewise.
9607 * ipa-param-manipulation.h (class ipa_param_body_adjustments):
9609 * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise.
9610 * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise.
9611 * langhooks.h (struct lang_hooks_for_decls): Likewise.
9612 * ipa-prop.h (struct ipa_param_descriptor): Likewise.
9613 * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store):
9615 * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise.
9616 * tree-ssa-reassoc.c (reassociate_bb): Likewise.
9617 * tree.c (component_ref_size): Likewise.
9618 * hsa-common.c (hsa_init_compilation_unit_data): Likewise.
9619 * gimple-ssa-sprintf.c (get_string_length, format_string,
9620 format_directive): Likewise.
9621 * omp-grid.c (grid_process_kernel_body_copy): Likewise.
9622 * input.c (string_concat_db::get_string_concatenation,
9623 test_lexer_string_locations_ucn4): Likewise.
9624 * cfgexpand.c (pass_expand::execute): Likewise.
9625 * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds,
9626 maybe_diag_overlap): Likewise.
9627 * rtl.c (RTX_CODE_HWINT_P_1): Likewise.
9628 * shrink-wrap.c (spread_components): Likewise.
9629 * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse):
9631 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
9633 * dwarf2out.c (dwarf2out_early_finish): Likewise.
9634 * gimple-ssa-store-merging.c: Likewise.
9635 * ira-costs.c (record_operand_costs): Likewise.
9636 * tree-vect-loop.c (vectorizable_reduction): Likewise.
9637 * target.def (dispatch): Likewise.
9638 (validate_dims, gen_ccmp_first): Fix up duplicated word issue
9639 in documentation text.
9640 * doc/tm.texi: Regenerated.
9641 * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up
9642 duplicated word issue in a comment.
9643 * config/i386/i386.c (ix86_test_loading_unspec): Likewise.
9644 * config/i386/i386-features.c (remove_partial_avx_dependency):
9646 * config/msp430/msp430.c (msp430_select_section): Likewise.
9647 * config/gcn/gcn-run.c (load_image): Likewise.
9648 * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise.
9649 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise.
9650 * config/aarch64/falkor-tag-collision-avoidance.c
9651 (single_dest_per_chain): Likewise.
9652 * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise.
9653 * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise.
9654 * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise.
9655 * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant):
9657 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise.
9658 * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise.
9659 * config/rs6000/rs6000-logue.c
9660 (rs6000_emit_probe_stack_range_stack_clash): Likewise.
9661 * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise.
9662 Fix various other issues in the comment.
9664 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
9666 * config/arm/t-rmprofile: create new multilib for
9667 armv8.1-m.main+mve hard float and reuse v8-m.main ones for
9670 2020-03-17 Jakub Jelinek <jakub@redhat.com>
9672 PR tree-optimization/94015
9673 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the
9674 function where EXP is address of the bytes being stored rather than
9675 the bytes themselves into count_nonzero_bytes_addr. Punt on zero
9676 sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs.
9677 Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before
9678 calling native_encode_expr if host or target doesn't have 8-bit
9679 chars. Formatting fixes.
9680 (count_nonzero_bytes_addr): New function.
9682 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9683 Mihail Ionescu <mihail.ionescu@arm.com>
9684 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9686 * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define.
9687 (UNOP_SNONE_NONE_QUALIFIERS): Likewise.
9688 (UNOP_SNONE_IMM_QUALIFIERS): Likewise.
9689 (UNOP_UNONE_NONE_QUALIFIERS): Likewise.
9690 (UNOP_UNONE_UNONE_QUALIFIERS): Likewise.
9691 (UNOP_UNONE_IMM_QUALIFIERS): Likewise.
9692 * config/arm/arm_mve.h (vmvnq_n_s16): Define macro.
9693 (vmvnq_n_s32): Likewise.
9694 (vrev64q_s8): Likewise.
9695 (vrev64q_s16): Likewise.
9696 (vrev64q_s32): Likewise.
9697 (vcvtq_s16_f16): Likewise.
9698 (vcvtq_s32_f32): Likewise.
9699 (vrev64q_u8): Likewise.
9700 (vrev64q_u16): Likewise.
9701 (vrev64q_u32): Likewise.
9702 (vmvnq_n_u16): Likewise.
9703 (vmvnq_n_u32): Likewise.
9704 (vcvtq_u16_f16): Likewise.
9705 (vcvtq_u32_f32): Likewise.
9706 (__arm_vmvnq_n_s16): Define intrinsic.
9707 (__arm_vmvnq_n_s32): Likewise.
9708 (__arm_vrev64q_s8): Likewise.
9709 (__arm_vrev64q_s16): Likewise.
9710 (__arm_vrev64q_s32): Likewise.
9711 (__arm_vrev64q_u8): Likewise.
9712 (__arm_vrev64q_u16): Likewise.
9713 (__arm_vrev64q_u32): Likewise.
9714 (__arm_vmvnq_n_u16): Likewise.
9715 (__arm_vmvnq_n_u32): Likewise.
9716 (__arm_vcvtq_s16_f16): Likewise.
9717 (__arm_vcvtq_s32_f32): Likewise.
9718 (__arm_vcvtq_u16_f16): Likewise.
9719 (__arm_vcvtq_u32_f32): Likewise.
9720 (vrev64q): Define polymorphic variant.
9721 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
9722 (UNOP_SNONE_NONE): Likewise.
9723 (UNOP_SNONE_IMM): Likewise.
9724 (UNOP_UNONE_UNONE): Likewise.
9725 (UNOP_UNONE_NONE): Likewise.
9726 (UNOP_UNONE_IMM): Likewise.
9727 * config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern.
9728 (mve_vcvtq_from_f_<supf><mode>): Likewise.
9729 (mve_vmvnq_n_<supf><mode>): Likewise.
9731 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9732 Mihail Ionescu <mihail.ionescu@arm.com>
9733 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9735 * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
9736 (UNOP_NONE_SNONE_QUALIFIERS): Likewise.
9737 (UNOP_NONE_UNONE_QUALIFIERS): Likewise.
9738 * config/arm/arm_mve.h (vrndxq_f16): Define macro.
9739 (vrndxq_f32): Likewise.
9740 (vrndq_f16) Likewise.
9741 (vrndq_f32): Likewise.
9742 (vrndpq_f16): Likewise.
9743 (vrndpq_f32): Likewise.
9744 (vrndnq_f16): Likewise.
9745 (vrndnq_f32): Likewise.
9746 (vrndmq_f16): Likewise.
9747 (vrndmq_f32): Likewise.
9748 (vrndaq_f16): Likewise.
9749 (vrndaq_f32): Likewise.
9750 (vrev64q_f16): Likewise.
9751 (vrev64q_f32): Likewise.
9752 (vnegq_f16): Likewise.
9753 (vnegq_f32): Likewise.
9754 (vdupq_n_f16): Likewise.
9755 (vdupq_n_f32): Likewise.
9756 (vabsq_f16): Likewise.
9757 (vabsq_f32): Likewise.
9758 (vrev32q_f16): Likewise.
9759 (vcvttq_f32_f16): Likewise.
9760 (vcvtbq_f32_f16): Likewise.
9761 (vcvtq_f16_s16): Likewise.
9762 (vcvtq_f32_s32): Likewise.
9763 (vcvtq_f16_u16): Likewise.
9764 (vcvtq_f32_u32): Likewise.
9765 (__arm_vrndxq_f16): Define intrinsic.
9766 (__arm_vrndxq_f32): Likewise.
9767 (__arm_vrndq_f16): Likewise.
9768 (__arm_vrndq_f32): Likewise.
9769 (__arm_vrndpq_f16): Likewise.
9770 (__arm_vrndpq_f32): Likewise.
9771 (__arm_vrndnq_f16): Likewise.
9772 (__arm_vrndnq_f32): Likewise.
9773 (__arm_vrndmq_f16): Likewise.
9774 (__arm_vrndmq_f32): Likewise.
9775 (__arm_vrndaq_f16): Likewise.
9776 (__arm_vrndaq_f32): Likewise.
9777 (__arm_vrev64q_f16): Likewise.
9778 (__arm_vrev64q_f32): Likewise.
9779 (__arm_vnegq_f16): Likewise.
9780 (__arm_vnegq_f32): Likewise.
9781 (__arm_vdupq_n_f16): Likewise.
9782 (__arm_vdupq_n_f32): Likewise.
9783 (__arm_vabsq_f16): Likewise.
9784 (__arm_vabsq_f32): Likewise.
9785 (__arm_vrev32q_f16): Likewise.
9786 (__arm_vcvttq_f32_f16): Likewise.
9787 (__arm_vcvtbq_f32_f16): Likewise.
9788 (__arm_vcvtq_f16_s16): Likewise.
9789 (__arm_vcvtq_f32_s32): Likewise.
9790 (__arm_vcvtq_f16_u16): Likewise.
9791 (__arm_vcvtq_f32_u32): Likewise.
9792 (vrndxq): Define polymorphic variants.
9798 (vrev64q): Likewise.
9801 (vrev32q): Likewise.
9802 (vcvtbq_f32): Likewise.
9803 (vcvttq_f32): Likewise.
9805 * config/arm/arm_mve_builtins.def (VAR2): Define.
9807 * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
9808 (mve_vrndq_f<mode>): Likewise.
9809 (mve_vrndpq_f<mode>): Likewise.
9810 (mve_vrndnq_f<mode>): Likewise.
9811 (mve_vrndmq_f<mode>): Likewise.
9812 (mve_vrndaq_f<mode>): Likewise.
9813 (mve_vrev64q_f<mode>): Likewise.
9814 (mve_vnegq_f<mode>): Likewise.
9815 (mve_vdupq_n_f<mode>): Likewise.
9816 (mve_vabsq_f<mode>): Likewise.
9817 (mve_vrev32q_fv8hf): Likewise.
9818 (mve_vcvttq_f32_f16v4sf): Likewise.
9819 (mve_vcvtbq_f32_f16v4sf): Likewise.
9820 (mve_vcvtq_to_f_<supf><mode>): Likewise.
9822 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
9823 Mihail Ionescu <mihail.ionescu@arm.com>
9824 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9826 * config/arm/arm-builtins.c (CF): Define mve_builtin_data.
9828 (ARM_BUILTIN_MVE_PATTERN_START): Define.
9829 (arm_init_mve_builtins): Define function.
9830 (arm_init_builtins): Add TARGET_HAVE_MVE check.
9831 (arm_expand_builtin_1): Check the range of fcode.
9832 (arm_expand_mve_builtin): Define function to expand MVE builtins.
9833 (arm_expand_builtin): Check the range of fcode.
9834 * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point
9836 (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace.
9837 (vst4q_s8): Define macro.
9838 (vst4q_s16): Likewise.
9839 (vst4q_s32): Likewise.
9840 (vst4q_u8): Likewise.
9841 (vst4q_u16): Likewise.
9842 (vst4q_u32): Likewise.
9843 (vst4q_f16): Likewise.
9844 (vst4q_f32): Likewise.
9845 (__arm_vst4q_s8): Define inline builtin.
9846 (__arm_vst4q_s16): Likewise.
9847 (__arm_vst4q_s32): Likewise.
9848 (__arm_vst4q_u8): Likewise.
9849 (__arm_vst4q_u16): Likewise.
9850 (__arm_vst4q_u32): Likewise.
9851 (__arm_vst4q_f16): Likewise.
9852 (__arm_vst4q_f32): Likewise.
9853 (__ARM_mve_typeid): Define macro with MVE types.
9854 (__ARM_mve_coerce): Define macro with _Generic feature.
9855 (vst4q): Define polymorphic variant for different vst4q builtins.
9856 * config/arm/arm_mve_builtins.def: New file.
9857 * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI
9859 * config/arm/mve.md (MVE_VLD_ST): Define iterator.
9860 (unspec): Define unspec.
9861 (mve_vst4q<mode>): Define RTL pattern.
9862 * config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI
9864 (neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes
9866 (define_split): Allow OI mode split for MVE after reload.
9867 (define_split): Allow XI mode split for MVE after reload.
9868 * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def.
9869 (arm-builtins.o): Likewise.
9871 2020-03-17 Christophe Lyon <christophe.lyon@linaro.org>
9873 * c-typeck.c (process_init_element): Handle constructor_type with
9874 type size represented by POLY_INT_CST.
9876 2020-03-17 Jakub Jelinek <jakub@redhat.com>
9878 PR tree-optimization/94187
9879 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if
9880 nchars - offset < nbytes.
9883 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would
9884 emit a warning if it was enabled and don't depend on TREE_NO_WARNING
9885 for code-generation.
9887 2020-03-16 Vladimir Makarov <vmakarov@redhat.com>
9890 * lra-spills.c (remove_pseudos): Do not reuse insn alternative
9891 after changing memory subreg.
9893 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
9894 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9896 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add
9897 emulator calls for dobule precision arithmetic operations for MVE.
9899 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
9900 Mihail Ionescu <mihail.ionescu@arm.com>
9901 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9903 * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base
9904 feature bit is on and -mfpu=auto is passed as compiler option, do not
9905 generate error on not finding any matching fpu. Because in this case
9906 fpu is not required.
9907 * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is
9908 enabled for MVE and also for all VFP extensions.
9909 (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2
9911 (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em.
9912 (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5
9913 along with feature bits mve_float.
9914 (mve): Modify add options in armv8.1-m.main arch for MVE.
9915 (mve.fp): Modify add options in armv8.1-m.main arch for MVE with
9917 * config/arm/arm.c (use_return_insn): Replace the
9918 check with TARGET_VFP_BASE.
9919 (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with
9921 (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
9922 with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as
9924 (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with
9925 TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE
9927 (arm_compute_frame_layout): Likewise.
9928 (arm_save_coproc_regs): Likewise.
9929 (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM
9931 (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
9932 with equivalent macro TARGET_VFP_BASE.
9933 (arm_expand_epilogue_apcs_frame): Likewise.
9934 (arm_expand_epilogue): Likewise.
9935 (arm_conditional_register_usage): Likewise.
9936 (arm_declare_function_name): Add check to skip printing .fpu directive
9937 in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is
9939 * config/arm/arm.h (TARGET_VFP_BASE): Define.
9940 * config/arm/arm.md (arch): Add "mve" to arch.
9941 (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true.
9942 (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT
9943 || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE.
9944 * config/arm/constraints.md (Uf): Define to allow modification to FPCCR
9946 * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard
9947 to not allow for MVE.
9948 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs
9950 (VUNSPEC_GET_FPSCR): Define.
9951 * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS
9952 instructions which move to general-purpose Register from Floating-point
9953 Special register and vice-versa.
9954 (thumb2_movhi_fp16): Likewise.
9955 (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along
9956 with MCR and MRC instructions which set and get Floating-point Status
9957 and Control Register (FPSCR).
9958 (movdi_vfp): Modify pattern to enable Single-precision scalar float move
9960 (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar
9961 float move patterns in MVE.
9962 (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional
9963 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
9964 (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional
9965 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
9966 (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding
9967 TARGET_VFP_BASE check.
9968 (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern
9969 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
9971 (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern
9972 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
9976 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
9977 Mihail Ionescu <mihail.ionescu@arm.com>
9978 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9980 * config.gcc (arm_mve.h): Include mve intrinsics header file.
9981 * config/arm/aout.h (p0): Add new register name for MVE predicated
9983 * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
9984 common to Neon and MVE.
9985 (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
9986 (arm_init_simd_builtin_types): Disable poly types for MVE.
9987 (arm_init_neon_builtins): Move a check to arm_init_builtins function.
9988 (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
9989 ARM_BUILTIN_NEON_LANE_CHECK.
9990 (mve_dereference_pointer): Add function.
9991 (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
9993 (arm_expand_neon_builtin): Moved to arm_expand_builtin function.
9994 (arm_expand_builtin): Moved from arm_expand_neon_builtin function.
9995 * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
9996 with floating point enabled.
9997 * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
9998 simd_immediate_valid_for_move.
9999 (simd_immediate_valid_for_move): Renamed from
10000 neon_immediate_valid_for_move function.
10001 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
10002 error if vfpv2 feature bit is disabled and mve feature bit is also
10003 disabled for HARD_FLOAT_ABI.
10004 (use_return_insn): Check to not push VFP regs for MVE.
10005 (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
10007 (aapcs_vfp_allocate_return_reg): Likewise.
10008 (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
10009 address operand for MVE.
10010 (arm_rtx_costs_internal): MVE check to determine cost of rtx.
10011 (neon_valid_immediate): Rename to simd_valid_immediate.
10012 (simd_valid_immediate): Rename from neon_valid_immediate.
10013 (simd_valid_immediate): MVE check on size of vector is 128 bits.
10014 (neon_immediate_valid_for_move): Rename to
10015 simd_immediate_valid_for_move.
10016 (simd_immediate_valid_for_move): Rename from
10017 neon_immediate_valid_for_move.
10018 (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
10020 (neon_make_constant): Modify call to neon_valid_immediate function.
10021 (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
10023 (output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
10024 (arm_compute_frame_layout): Calculate space for saved VFP registers for
10026 (arm_save_coproc_regs): Save coproc registers for MVE.
10027 (arm_print_operand): Add case 'E' to print memory operands for MVE.
10028 (arm_print_operand_address): Check to print register number for MVE.
10029 (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
10030 (arm_modes_tieable_p): Check to allow structure mode for MVE.
10031 (arm_regno_class): Add VPR_REGNUM check.
10032 (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
10034 (arm_expand_epilogue): MVE check for enabling pop instructions in
10036 (arm_print_asm_arch_directives): Modify function to disable print of
10037 .arch_extension "mve" and "fp" for cases where MVE is enabled with
10039 (arm_vector_mode_supported_p): Check for modes available in MVE interger
10040 and MVE floating point.
10041 (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
10043 (arm_conditional_register_usage): Enable usage of conditional regsiter
10045 (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
10046 (arm_declare_function_name): Modify function to disable print of
10047 .arch_extension "mve" and "fp" for cases where MVE is enabled with
10049 * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
10050 when target general registers are required.
10051 (TARGET_HAVE_MVE_FLOAT): Likewise.
10052 (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
10054 (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
10055 which indicate this is not available for across function calls.
10056 (FIRST_PSEUDO_REGISTER): Modify.
10057 (VALID_MVE_MODE): Define valid MVE mode.
10058 (VALID_MVE_SI_MODE): Define valid MVE SI mode.
10059 (VALID_MVE_SF_MODE): Define valid MVE SF mode.
10060 (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
10061 (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
10063 (IS_VPR_REGNUM): Macro to check for VPR_REG register.
10064 (REG_ALLOC_ORDER): Add VPR_REGNUM entry.
10065 (enum reg_class): Add VPR_REG entry.
10066 (REG_CLASS_NAMES): Add VPR_REG entry.
10067 * config/arm/arm.md (VPR_REGNUM): Define.
10068 (conds): Check is_mve_type attrbiute to differentiate "conditional" and
10069 "unconditional" instructions.
10070 (arm_movsf_soft_insn): Modify RTL to not allow for MVE.
10071 (movdf_soft_insn): Modify RTL to not allow for MVE.
10072 (vfp_pop_multiple_with_writeback): Enable for MVE.
10073 (include "mve.md"): Include mve.md file.
10074 * config/arm/arm_mve.h: Add MVE intrinsics head file.
10075 * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
10076 for vector predicated operands.
10077 * config/arm/iterators.md (VNIM1): Define.
10078 (VNINOTM1): Define.
10079 (VHFBF_split): Define
10080 * config/arm/mve.md: New file.
10081 (mve_mov<mode>): Define RTL for move, store and load in MVE.
10082 (mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
10084 * config/arm/neon.md (neon_immediate_valid_for_move): Rename with
10085 simd_immediate_valid_for_move.
10086 (neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
10087 is common to MVE and NEON to vec-common.md file.
10088 (vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
10089 * config/arm/predicates.md (vpr_register_operand): Define.
10090 * config/arm/t-arm: Add mve.md file.
10091 * config/arm/types.md (mve_move): Add MVE instructions mve_move to
10093 (mve_store): Add MVE instructions mve_store to attribute "type".
10094 (mve_load): Add MVE instructions mve_load to attribute "type".
10095 (is_mve_type): Define attribute.
10096 * config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
10097 standard move patterns in MVE along with NEON and IWMMXT with mode
10099 (mov<mode>): Modify RTL expand to support standard move patterns in NEON
10100 and IWMMXT with mode iterator V8HF.
10101 (movv8hf): Define RTL expand to support standard "movv8hf" pattern in
10103 * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
10104 simd_immediate_valid_for_move.
10107 2020-03-16 H.J. Lu <hongjiu.lu@intel.com>
10110 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
10111 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
10113 * config/i386/predicates.md (ext_sse_reg_operand): Removed.
10115 2020-03-16 Jakub Jelinek <jakub@redhat.com>
10118 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
10121 PR tree-optimization/94166
10122 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION
10123 as secondary comparison key.
10125 2020-03-16 Bin Cheng <bin.cheng@linux.alibaba.com>
10127 PR tree-optimization/94125
10128 * tree-loop-distribution.c
10129 (loop_distribution::break_alias_scc_partitions): Update post order
10130 number for merged scc.
10132 2020-03-15 H.J. Lu <hongjiu.lu@intel.com>
10135 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and
10137 * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov
10138 for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
10139 and ext_sse_reg_operand check.
10141 2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
10143 * common.opt: Avoid redundancy in the help text.
10144 * config/arc/arc.opt: Likewise.
10145 * config/cr16/cr16.opt: Likewise.
10147 2020-03-14 Jakub Jelinek <jakub@redhat.com>
10149 PR middle-end/93566
10150 * tree-nested.c (convert_nonlocal_omp_clauses,
10151 convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
10152 with C/C++ array sections.
10154 2020-03-14 H.J. Lu <hongjiu.lu@intel.com>
10157 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
10158 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
10161 2020-03-14 Jakub Jelinek <jakub@redhat.com>
10163 * gimple-fold.c (gimple_fold_builtin_strncpy): Change
10164 "a an" to "an" in a comment.
10165 * hsa-common.h (is_a_helper): Likewise.
10166 * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise.
10167 * config/arc/arc.c (arc600_corereg_hazard): Likewise.
10168 * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise.
10170 2020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com>
10173 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a
10174 64-bit value by 64 bits (UB).
10176 2020-03-13 Vladimir Makarov <vmakarov@redhat.com>
10178 PR rtl-optimization/92303
10179 * lra-spills.c (remove_pseudos): Try to simplify memory subreg.
10181 2020-03-13 Segher Boessenkool <segher@kernel.crashing.org>
10183 PR rtl-optimization/94148
10184 PR rtl-optimization/94042
10185 * df-core.c (BB_LAST_CHANGE_AGE): Delete.
10186 (df_worklist_propagate_forward): New parameter last_change_age, use
10187 that instead of bb->aux.
10188 (df_worklist_propagate_backward): Ditto.
10189 (df_worklist_dataflow_doublequeue): Use a local array last_change_age.
10191 2020-03-13 Richard Biener <rguenther@suse.de>
10193 PR tree-optimization/94163
10194 * tree-ssa-pre.c (create_expression_by_pieces): Check
10195 whether alignment would be zero.
10197 2020-03-13 Martin Liska <mliska@suse.cz>
10200 * lto-wrapper.c (run_gcc): Use concat for appending
10201 to collect_gcc_options.
10203 2020-03-13 Jakub Jelinek <jakub@redhat.com>
10206 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
10207 instead of GEN_INT.
10209 2020-03-13 H.J. Lu <hongjiu.lu@intel.com>
10212 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
10213 * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
10214 for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
10215 TARGET_AVX512VL and ext_sse_reg_operand check.
10217 2020-03-13 Bu Le <bule1@huawei.com>
10220 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=)
10221 (-param=aarch64-double-recp-precision=): New options.
10222 * doc/invoke.texi: Document them.
10223 * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them
10224 instead of hard-coding the choice of 1 for float and 2 for double.
10226 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
10228 PR rtl-optimization/94119
10229 * resource.h (clear_hashed_info_until_next_barrier): Declare.
10230 * resource.c (clear_hashed_info_until_next_barrier): New function.
10231 * reorg.c (add_to_delay_list): Fix formatting.
10232 (relax_delay_slots): Call clear_hashed_info_until_next_barrier on
10233 the next instruction after removing a BARRIER.
10235 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
10237 PR middle-end/92071
10238 * expmed.c (store_integral_bit_field): For fields larger than a word,
10239 call extract_bit_field on the value if the mode is BLKmode. Remove
10240 specific path for big-endian targets and tidy things up a little bit.
10242 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
10244 PR rtl-optimization/90275
10245 * cse.c (cse_insn): Delete no-op register moves too.
10247 2020-03-12 Darius Galis <darius.galis@cyberthorstudios.com>
10249 * config/rx/rx.md (CTRLREG_CPEN): Remove.
10250 * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support.
10252 2020-03-12 Richard Biener <rguenther@suse.de>
10254 PR tree-optimization/94103
10255 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type
10256 punning when the mode precision is not sufficient.
10258 2020-03-12 H.J. Lu <hongjiu.lu@intel.com>
10261 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
10262 MODE_V1DF and MODE_V2SF.
10263 * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
10264 ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand
10267 2020-03-12 Jakub Jelinek <jakub@redhat.com>
10269 * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
10270 ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
10271 and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
10272 * doc/tm.texi: Regenerated.
10274 PR tree-optimization/94130
10275 * tree-ssa-dse.c: Include gimplify.h.
10276 (increment_start_addr): If stmt has lhs, drop the lhs from call and
10277 set it after the call to the original value of the first argument.
10279 (decrement_count): Formatting fix.
10281 2020-03-11 Delia Burduv <delia.burduv@arm.com>
10283 * config/arm/arm-builtins.c
10284 (arm_init_simd_builtin_scalar_types): New.
10285 * config/arm/arm_neon.h (vld2_bf16): Used new builtin type.
10286 (vld2q_bf16): Used new builtin type.
10287 (vld3_bf16): Used new builtin type.
10288 (vld3q_bf16): Used new builtin type.
10289 (vld4_bf16): Used new builtin type.
10290 (vld4q_bf16): Used new builtin type.
10291 (vld2_dup_bf16): Used new builtin type.
10292 (vld2q_dup_bf16): Used new builtin type.
10293 (vld3_dup_bf16): Used new builtin type.
10294 (vld3q_dup_bf16): Used new builtin type.
10295 (vld4_dup_bf16): Used new builtin type.
10296 (vld4q_dup_bf16): Used new builtin type.
10298 2020-03-11 Jakub Jelinek <jakub@redhat.com>
10301 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
10302 at the start to switch to data section. Don't print extra newline if
10303 .globl directive has not been emitted.
10305 2020-03-11 Richard Biener <rguenther@suse.de>
10307 * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]):
10310 2020-03-11 Eric Botcazou <ebotcazou@adacore.com>
10312 PR middle-end/93961
10313 * tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into fields
10314 whose type is a qualified union.
10316 2020-03-11 Jakub Jelinek <jakub@redhat.com>
10319 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
10320 instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
10323 * value-prof.c (dump_histogram_value): Use abs_hwi instead of
10325 (get_nth_most_common_value): Use abs_hwi instead of abs.
10327 PR middle-end/94111
10328 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
10329 is rvc_normal, otherwise use real_to_decimal to print the number to
10332 PR tree-optimization/94114
10333 * tree-loop-distribution.c (generate_memset_builtin): Call
10334 rewrite_to_non_trapping_overflow even on mem.
10335 (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
10338 2020-03-10 Jeff Law <law@redhat.com>
10340 * config/bfin/bfin.md (movsi_insv): Add length attribute.
10342 2020-03-10 Jiufu Guo <guojiufu@linux.ibm.com>
10345 * gcc/config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check
10346 NAN and SIGNED_ZEROR for smax/smin.
10348 2020-03-10 Will Schmidt <will_schmidt@vnet.ibm.com>
10351 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
10352 clause to handle P9V_BUILTIN_VEC_LXVL with const arguments.
10354 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
10356 * loop-iv.c (find_simple_exit): Make it static.
10357 * cfgloop.h: Remove the corresponding prototype.
10359 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
10361 * ddg.c (create_ddg): Fix intendation.
10362 (set_recurrence_length): Likewise.
10363 (create_ddg_all_sccs): Likewise.
10365 2020-03-10 Jakub Jelinek <jakub@redhat.com>
10368 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with
10369 CCZmode instead of CCNOmode if operands[2] has DImode and pos + len
10372 2020-03-09 Jason Merrill <jason@redhat.com>
10374 * gdbinit.in (pgs): Fix typo in documentation.
10376 2020-03-09 Vladimir Makarov <vmakarov@redhat.com>
10380 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
10382 PR rtl-optimization/93564
10383 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
10384 do not honor reg alloc order.
10386 2020-03-09 Andrew Pinski <apinski@marvell.com>
10388 PR inline-asm/94095
10389 * doc/extend.texi (x86 Operand Modifiers): Fix column
10392 2020-03-09 Martin Liska <mliska@suse.cz>
10395 * config/rs6000/rs6000.c (rs6000_option_override_internal):
10396 Remove set of str_align_loops and str_align_jumps as these
10397 should be set in previous 2 conditions in the function.
10399 2020-03-09 Jakub Jelinek <jakub@redhat.com>
10401 PR rtl-optimization/94045
10402 * params.opt (-param=max-find-base-term-values=): New option.
10403 * alias.c (find_base_term): Add cut-off for number of visited VALUEs
10404 in a single toplevel find_base_term call.
10406 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
10409 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define.
10410 * config/aarch64/aarch64-simd.md
10411 (aarch64_vec_<su>mult_lane<Qlane>): Add new insn for widening lane mul.
10412 (aarch64_vec_<su>mlal_lane<Qlane>): Likewise.
10413 * config/aarch64/aarch64-simd-builtins.def: Add intrinsics.
10414 * config/aarch64/arm_neon.h:
10415 (vmlal_lane_s16): Expand using intrinsics rather than inline asm.
10416 (vmlal_lane_u16): Likewise.
10417 (vmlal_lane_s32): Likewise.
10418 (vmlal_lane_u32): Likewise.
10419 (vmlal_laneq_s16): Likewise.
10420 (vmlal_laneq_u16): Likewise.
10421 (vmlal_laneq_s32): Likewise.
10422 (vmlal_laneq_u32): Likewise.
10423 (vmull_lane_s16): Likewise.
10424 (vmull_lane_u16): Likewise.
10425 (vmull_lane_s32): Likewise.
10426 (vmull_lane_u32): Likewise.
10427 (vmull_laneq_s16): Likewise.
10428 (vmull_laneq_u16): Likewise.
10429 (vmull_laneq_s32): Likewise.
10430 (vmull_laneq_u32): Likewise.
10431 * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul.
10434 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
10436 * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
10437 (aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
10438 (aarch64_mls_elt<mode>): Likewise.
10439 (aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
10440 (aarch64_fma4_elt<mode>): Likewise.
10441 (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
10442 (aarch64_fma4_elt_to_64v2df): Likewise.
10443 (aarch64_fnma4_elt<mode>): Likewise.
10444 (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
10445 (aarch64_fnma4_elt_to_64v2df): Likewise.
10447 2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
10449 * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
10450 Specify movprfx attribute.
10451 (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
10453 2020-03-06 David Edelsohn <dje.gcc@gmail.com>
10456 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for
10458 (TARGET_NO_FP_IN_TOC): Same.
10459 * config/rs6000/aix71.h: Same.
10460 * config/rs6000/aix72.h: Same.
10462 2020-03-06 Andrew Pinski <apinski@marvell.com>
10463 Jeff Law <law@redhat.com>
10465 PR rtl-optimization/93996
10466 * haifa-sched.c (remove_notes): Be more careful when adding
10469 2020-03-06 Delia Burduv <delia.burduv@arm.com>
10471 * config/arm/arm_neon.h (vld2_bf16): New.
10477 (vld2_dup_bf16): New.
10478 (vld2q_dup_bf16): New.
10479 (vld3_dup_bf16): New.
10480 (vld3q_dup_bf16): New.
10481 (vld4_dup_bf16): New.
10482 (vld4q_dup_bf16): New.
10483 * config/arm/arm_neon_builtins.def
10484 (vld2): Changed to VAR13 and added v4bf, v8bf
10485 (vld2_dup): Changed to VAR8 and added v4bf, v8bf
10486 (vld3): Changed to VAR13 and added v4bf, v8bf
10487 (vld3_dup): Changed to VAR8 and added v4bf, v8bf
10488 (vld4): Changed to VAR13 and added v4bf, v8bf
10489 (vld4_dup): Changed to VAR8 and added v4bf, v8bf
10490 * config/arm/iterators.md (VDXBF2): New iterator.
10491 *config/arm/neon.md (neon_vld2): Use new iterators.
10492 (neon_vld2_dup<mode): Use new iterators.
10493 (neon_vld3<mode>): Likewise.
10494 (neon_vld3qa<mode>): Likewise.
10495 (neon_vld3qb<mode>): Likewise.
10496 (neon_vld3_dup<mode>): Likewise.
10497 (neon_vld4<mode>): Likewise.
10498 (neon_vld4qa<mode>): Likewise.
10499 (neon_vld4qb<mode>): Likewise.
10500 (neon_vld4_dup<mode>): Likewise.
10501 (neon_vld2_dupv8bf): New.
10502 (neon_vld3_dupv8bf): Likewise.
10503 (neon_vld4_dupv8bf): Likewise.
10505 2020-03-06 Delia Burduv <delia.burduv@arm.com>
10507 * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef.
10508 (bfloat16x8x2_t): New typedef.
10509 (bfloat16x4x3_t): New typedef.
10510 (bfloat16x8x3_t): New typedef.
10511 (bfloat16x4x4_t): New typedef.
10512 (bfloat16x8x4_t): New typedef.
10519 * config/arm/arm-builtins.c (v2bf_UP): Define.
10521 (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype.
10522 * config/arm/arm-modes.def (V2BF): New mode.
10523 * config/arm/arm-simd-builtin-types.def
10524 (Bfloat16x2_t): New entry.
10525 * config/arm/arm_neon_builtins.def
10526 (vst2): Changed to VAR13 and added v4bf, v8bf
10527 (vst3): Changed to VAR13 and added v4bf, v8bf
10528 (vst4): Changed to VAR13 and added v4bf, v8bf
10529 * config/arm/iterators.md (VDXBF): New iterator.
10530 (VQ2BF): New iterator.
10531 *config/arm/neon.md (neon_vst2<mode>): Used new iterators.
10532 (neon_vst2<mode>): Used new iterators.
10533 (neon_vst3<mode>): Used new iterators.
10534 (neon_vst3<mode>): Used new iterators.
10535 (neon_vst3qa<mode>): Used new iterators.
10536 (neon_vst3qb<mode>): Used new iterators.
10537 (neon_vst4<mode>): Used new iterators.
10538 (neon_vst4<mode>): Used new iterators.
10539 (neon_vst4qa<mode>): Used new iterators.
10540 (neon_vst4qb<mode>): Used new iterators.
10542 2020-03-06 Delia Burduv <delia.burduv@arm.com>
10544 * config/aarch64/aarch64-simd-builtins.def
10545 (bfcvtn): New built-in function.
10546 (bfcvtn_q): New built-in function.
10547 (bfcvtn2): New built-in function.
10548 (bfcvt): New built-in function.
10549 * config/aarch64/aarch64-simd.md
10550 (aarch64_bfcvtn<q><mode>): New pattern.
10551 (aarch64_bfcvtn2v8bf): New pattern.
10552 (aarch64_bfcvtbf): New pattern.
10553 * config/aarch64/arm_bf16.h (float32_t): New typedef.
10554 (vcvth_bf16_f32): New intrinsic.
10555 * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic.
10556 (vcvtq_low_bf16_f32): New intrinsic.
10557 (vcvtq_high_bf16_f32): New intrinsic.
10558 * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator.
10559 (UNSPEC_BFCVTN): New UNSPEC.
10560 (UNSPEC_BFCVTN2): New UNSPEC.
10561 (UNSPEC_BFCVT): New UNSPEC.
10562 * config/arm/types.md (bf_cvt): New type.
10564 2020-03-06 Andreas Krebbel <krebbel@linux.ibm.com>
10566 * config/s390/s390.md ("tabort"): Get rid of two consecutive
10567 blanks in format string.
10569 2020-03-05 H.J. Lu <hongjiu.lu@intel.com>
10573 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype.
10574 * config/i386/i386.c (ix86_get_ssemov): New function.
10575 (ix86_output_ssemov): Likewise.
10576 * config/i386/sse.md (VMOVE:mov<mode>_internal): Call
10577 ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL
10579 (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV.
10580 (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV.
10581 Remove ext_sse_reg_operand and TARGET_AVX512VL check.
10582 (*movti_internal): Likewise.
10583 (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV.
10585 2020-03-05 Jeff Law <law@redhat.com>
10587 PR tree-optimization/91890
10588 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument.
10589 Use gimple_or_expr_nonartificial_location.
10590 (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds.
10591 Use gimple_or_expr_nonartificial_location.
10592 * gimple.c (gimple_or_expr_nonartificial_location): New function.
10593 * gimple.h (gimple_or_expr_nonartificial_location): Declare it.
10594 * tree-ssa-strlen.c (maybe_warn_overflow): Use
10595 gimple_or_expr_nonartificial_location.
10596 (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise.
10597 (maybe_warn_pointless_strcmp): Likewise.
10599 2020-03-05 Jakub Jelinek <jakub@redhat.com>
10602 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of
10603 SRC and MASK arguments to __m128 from __m128d.
10604 (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256
10606 (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128
10608 * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C
10609 argument to __m128i from __m128d.
10610 (_mm256_permute2_pd): Fix first cast of C argument to __m256i from
10612 (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128.
10613 (_mm256_permute2_ps): Fix first cast of C argument to __m256i from
10616 2020-03-05 Delia Burduv <delia.burduv@arm.com>
10618 * config/arm/arm_neon.h (vbfmmlaq_f32): New.
10619 (vbfmlalbq_f32): New.
10620 (vbfmlaltq_f32): New.
10621 (vbfmlalbq_lane_f32): New.
10622 (vbfmlaltq_lane_f32): New.
10623 (vbfmlalbq_laneq_f32): New.
10624 (vbfmlaltq_laneq_f32): New.
10625 * config/arm/arm_neon_builtins.def (vmmla): New.
10630 (vfmab_laneq): New.
10631 (vfmat_laneq): New.
10632 * config/arm/iterators.md (BF_MA): New int iterator.
10633 (bt): New int attribute.
10634 (VQXBF): Copy of VQX with V8BF.
10635 * config/arm/neon.md (neon_vmmlav8bf): New insn.
10636 (neon_vfma<bt>v8bf): New insn.
10637 (neon_vfma<bt>_lanev8bf): New insn.
10638 (neon_vfma<bt>_laneqv8bf): New expand.
10639 (neon_vget_high<mode>): Changed iterator to VQXBF.
10640 * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC.
10641 (UNSPEC_BFMAB): New UNSPEC.
10642 (UNSPEC_BFMAT): New UNSPEC.
10644 2020-03-05 Jakub Jelinek <jakub@redhat.com>
10646 PR middle-end/93399
10647 * tree-pretty-print.h (pretty_print_string): Declare.
10648 * tree-pretty-print.c (pretty_print_string): Remove forward
10649 declaration, no longer static. Change nbytes parameter type
10650 from unsigned to size_t.
10651 * print-rtl.c (print_value) <case CONST_STRING>: Use
10652 pretty_print_string and for shrink way too long strings.
10654 2020-03-05 Richard Biener <rguenther@suse.de>
10655 Jakub Jelinek <jakub@redhat.com>
10657 PR tree-optimization/93582
10658 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR
10659 last operand as signed when looking for memset offset. Formatting
10662 2020-03-04 Andrew Pinski <apinski@marvell.com>
10665 * value-prof.c (dump_histogram_value): Use std::abs.
10667 2020-03-04 Martin Sebor <msebor@redhat.com>
10669 PR tree-optimization/93986
10670 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int
10671 operands to the same precision widest_int to avoid ICEs.
10673 2020-03-04 Bill Schmidt <wschmidt@linux.ibm.com>
10676 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define.
10677 * rs6000.c (rs6000_disable_incompatible_switches): Add table entry
10678 for OPTION_MASK_ALTIVEC.
10680 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
10682 * config.gcc: Include the glibc-stdint.h header for zTPF.
10684 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
10686 * config/s390/s390.c (s390_secondary_memory_needed): Disallow
10687 direct FPR-GPR copies.
10688 (s390_register_info_gprtofpr): Disallow GPR content to be saved in
10691 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
10693 * config/s390/s390.c (s390_emit_prologue): Specify the 2 new
10694 operands to the prologue_tpf expander.
10695 (s390_emit_epilogue): Likewise.
10696 (s390_option_override_internal): Do error checking and setup for
10698 * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK)
10699 (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET)
10700 (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET)
10701 (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions.
10702 * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new
10703 operands for the check flag and the branch target.
10704 * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check")
10705 ("mtpf-trace-hook-prologue-target")
10706 ("mtpf-trace-hook-epilogue-check")
10707 ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New
10709 * doc/invoke.texi: Document -mtpf-trace-skip option. The other
10710 options are for debugging purposes and will not be documented
10713 2020-03-04 Jakub Jelinek <jakub@redhat.com>
10716 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag.
10718 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti
10719 argument. Change pd argument so that it can be modified. Turn
10720 constant non-CONSTRUCTOR store into non-constant if it is too large.
10721 Adjust offset and size of CONSTRUCTOR or non-constant store to avoid
10723 (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust
10726 2020-02-04 Richard Biener <rguenther@suse.de>
10728 PR tree-optimization/93964
10729 * graphite-isl-ast-to-gimple.c
10730 (gcc_expression_from_isl_ast_expr_id): Add intermediate
10731 conversion for pointer to integer converts.
10732 * graphite-scop-detection.c (assign_parameter_index_in_region):
10735 2020-03-04 Martin Liska <mliska@suse.cz>
10739 * doc/invoke.texi: Clarify --help=language and --help=common
10742 2020-03-04 Jakub Jelinek <jakub@redhat.com>
10744 PR tree-optimization/94001
10745 * tree-tailcall.c (process_assignment): Before comparing op1 to
10746 *ass_var, verify *ass_var is non-NULL.
10748 2020-03-04 Kito Cheng <kito.cheng@sifive.com>
10751 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
10754 2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
10756 * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
10757 * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New.
10758 (vcvtq_high_f32_bf16, vcvt_bf16_f32): New.
10759 (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New.
10760 * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries.
10761 (vbfcvtv4sf, vbfcvtv4sf_high): Likewise.
10762 * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators.
10763 (V_bf_low, V_bf_cvt_m): New mode attributes.
10764 * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New.
10765 (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New.
10766 (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New.
10767 (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New
10768 * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New.
10770 2020-03-03 Jakub Jelinek <jakub@redhat.com>
10772 PR tree-optimization/93582
10773 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument.
10774 * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result
10775 members, initialize them in the constructor and if mask is non-NULL,
10776 artificially push_partial_def {} for the portions of the mask that
10778 (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to
10779 val and return (void *)-1. Formatting fix.
10780 (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization.
10782 (vn_reference_lookup): Add mask argument. If non-NULL, don't call
10783 fully_constant_vn_reference_p nor vn_reference_lookup_1 and return
10785 (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST
10787 (visit_stmt): Formatting fix.
10789 2020-03-03 Richard Biener <rguenther@suse.de>
10791 PR tree-optimization/93946
10792 * alias.h (refs_same_for_tbaa_p): Declare.
10793 * alias.c (refs_same_for_tbaa_p): New function.
10794 * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return
10796 * tree-ssa-scopedtables.h
10797 (avail_exprs_stack::lookup_avail_expr): Add output argument
10798 giving access to the hashtable entry.
10799 * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
10801 * tree-ssa-dom.c: Include alias.h.
10802 (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before
10803 removing redundant store.
10804 * tree-ssa-sccvn.h (vn_reference_s::base_set): New member.
10805 (ao_ref_init_from_vn_reference): Adjust prototype.
10806 (vn_reference_lookup_pieces): Likewise.
10807 (vn_reference_insert_pieces): Likewise.
10808 * tree-ssa-sccvn.c: Track base alias set in addition to alias
10810 (eliminate_dom_walker::eliminate_stmt): Also check base alias
10811 set when removing redundant stores.
10812 (visit_reference_op_store): Likewise.
10813 * dse.c (record_store): Adjust valdity check for redundant
10816 2020-03-03 Jakub Jelinek <jakub@redhat.com>
10819 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder.
10821 PR rtl-optimization/94002
10822 * explow.c (plus_constant): Punt if cst has VOIDmode and
10823 get_pool_mode is different from mode.
10825 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
10827 * config/arc/arc.c (leigitimate_small_data_address_p): Check if an
10828 address has an offset which fits the scalling constraint for a
10829 load/store operation.
10830 (legitimate_scaled_address_p): Update use
10831 leigitimate_small_data_address_p.
10832 (arc_print_operand): Likewise.
10833 (arc_legitimate_address_p): Likewise.
10834 (legitimate_small_data_address_p): Likewise.
10836 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
10838 * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate.
10839 (fnmasf4_fpu): Likewise.
10841 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
10843 * config/arc/arc.md (adddi3): Early expand the 64bit operation into
10845 (subdi3): Likewise.
10846 (adddi3_i): Remove pattern.
10847 (subdi3_i): Likewise.
10849 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
10851 * config/arc/arc.md (eh_return): Add length info.
10853 2020-03-02 David Malcolm <dmalcolm@redhat.com>
10855 * doc/invoke.texi (-fanalyzer-show-duplicate-count): New.
10857 2020-03-02 David Malcolm <dmalcolm@redhat.com>
10859 * doc/invoke.texi (Static Analyzer Options): Add
10860 -Wanalyzer-stale-setjmp-buffer to the list of options enabled
10863 2020-03-02 Uroš Bizjak <ubizjak@gmail.com>
10866 * config/i386/i386.md (movstrict<mode>): Allow only
10867 registers with VALID_INT_MODE_P modes.
10869 2020-03-02 Andrew Stubbs <ams@codesourcery.com>
10871 * config/gcn/gcn-valu.md (dpp_move<mode>): New.
10872 (reduc_insn): Use 'U' and 'B' operand codes.
10873 (reduc_<reduc_op>_scal_<mode>): Allow all types.
10874 (reduc_<reduc_op>_scal_v64di): Delete.
10875 (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types.
10876 (*plus_carry_dpp_shr_v64si): Change to ...
10877 (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types.
10878 (mov_from_lane63_v64di): Change to ...
10879 (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes.
10880 * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size.
10881 Support UNSPEC_MOV_DPP_SHR output formats.
10882 (gcn_expand_reduc_scalar): Add "use_moves" reductions.
10883 Add "use_extends" reductions.
10884 (print_operand_address): Add 'I' and 'U' codes.
10885 * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR.
10887 2020-03-02 Martin Liska <mliska@suse.cz>
10889 * lto-wrapper.c: Fix typo in comment about
10890 C++ standard version.
10892 2020-03-01 Martin Sebor <msebor@redhat.com>
10895 * calls.c (init_attr_rdwr_indices): Correctly handle attribute.
10897 2020-03-01 Martin Sebor <msebor@redhat.com>
10899 PR middle-end/93829
10900 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that
10901 of a pointer in the outermost ADDR_EXPRs.
10903 2020-02-28 Jeff Law <law@redhat.com>
10905 * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19.
10906 * config/v850/v850.c (v850_asm_trampoline_template): Update
10909 2020-02-28 Michael Meissner <meissner@linux.ibm.com>
10912 * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var):
10915 2020-02-28 Martin Liska <mliska@suse.cz>
10918 * configure.ac: Improve detection of ld_date by requiring
10919 either two dashes or none.
10920 * configure: Regenerate.
10922 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
10924 PR rtl-optimization/93564
10925 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
10926 do not honor reg alloc order.
10928 2020-02-27 Joel Hutton <Joel.Hutton@arm.com>
10931 * config/aarch64/aarch64.c (aarch64_override_options): Fix
10932 misleading warning string.
10934 2020-02-27 Martin Sebor <msebor@redhat.com>
10936 * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo.
10938 2020-02-27 Michael Meissner <meissner@linux.ibm.com>
10941 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
10942 Split the insn into two parts. This insn only does variable
10943 extract from a register.
10944 (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
10945 variable extract from memory.
10946 (vsx_extract_v4sf_var): Split the insn into two parts. This insn
10947 only does variable extract from a register.
10948 (vsx_extract_v4sf_var_load): New insn, do variable extract from
10950 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
10951 into two parts. This insn only does variable extract from a
10953 (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
10954 do variable extract from memory.
10956 2020-02-27 Martin Jambor <mjambor@suse.cz>
10957 Feng Xue <fxue@os.amperecomputing.com>
10960 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with
10961 new function calls_same_node_or_its_all_contexts_clone_p.
10962 (cgraph_edge_brings_value_p): Use it.
10963 (cgraph_edge_brings_value_p): Likewise.
10964 (self_recursive_pass_through_p): Return false if caller is a clone.
10965 (self_recursive_agg_pass_through_p): Likewise.
10967 2020-02-27 Jan Hubicka <hubicka@ucw.cz>
10969 PR middle-end/92152
10970 * alias.c (ends_tbaa_access_path_p): Break out from ...
10971 (component_uses_parent_alias_set_from): ... here.
10972 * alias.h (ends_tbaa_access_path_p): Declare.
10973 * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...;
10974 handle trailing arrays past end of tbaa access path.
10975 (aliasing_component_refs_p): ... here; likewise.
10976 (nonoverlapping_refs_since_match_p): Track TBAA segment of the access
10977 path; disambiguate also past end of it.
10978 (nonoverlapping_component_refs_p): Use only TBAA segment of the access
10981 2020-02-27 Mihail Ionescu <mihail.ionescu@arm.com>
10983 * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the
10984 beginning of the file.
10985 (vcreate_bf16, vcombine_bf16): New.
10986 (vdup_n_bf16, vdupq_n_bf16): New.
10987 (vdup_lane_bf16, vdup_laneq_bf16): New.
10988 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
10989 (vduph_lane_bf16, vduph_laneq_bf16): New.
10990 (vset_lane_bf16, vsetq_lane_bf16): New.
10991 (vget_lane_bf16, vgetq_lane_bf16): New.
10992 (vget_high_bf16, vget_low_bf16): New.
10993 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
10994 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
10995 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
10996 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
10997 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
10998 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
10999 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
11000 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
11001 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
11002 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
11003 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New.
11004 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
11005 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
11006 (vreinterpretq_bf16_p128): New.
11007 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
11008 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
11009 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
11010 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
11011 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
11012 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
11013 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
11014 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
11015 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
11016 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
11017 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
11018 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
11019 (vreinterpretq_p128_bf16): New.
11020 * config/arm/arm_neon_builtins.def (VDX): Add V4BF.
11021 (V_elem): Likewise.
11022 (V_elem_l): Likewise.
11023 (VD_LANE): Likewise.
11025 (V_DOUBLE): Likewise.
11026 (VDQX): Add V4BF and V8BF.
11027 (V_two_elem, V_three_elem, V_four_elem): Likewise.
11029 (V_HALF): Likewise.
11030 (V_double_vector_mode): Likewise.
11031 (V_cmp_result): Likewise.
11032 (V_uf_sclr): Likewise.
11033 (V_sz_elem): Likewise.
11034 (Is_d_reg): Likewise.
11035 (V_mode_nunits): Likewise.
11036 * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16.
11038 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
11040 * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator.
11041 (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE.
11042 (<expander><mode>3<exec>): Likewise.
11043 (<expander><mode>3): New.
11044 (v<expander><mode>3): New.
11045 (<expander><mode>3): New.
11046 (<expander><mode>3<exec>): Rename to ...
11047 (<expander>v64si3<exec>): ... this, and change modes to V64SI.
11048 * config/gcn/gcn.md (mnemonic): Use '%B' for not.
11050 2020-02-27 Alexandre Oliva <oliva@adacore.com>
11052 * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave
11055 2020-02-27 Richard Biener <rguenther@suse.de>
11057 PR tree-optimization/93508
11058 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like
11059 non-_CHK variants. Valueize their length arguments.
11061 2020-02-27 Richard Biener <rguenther@suse.de>
11063 PR tree-optimization/93953
11064 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference
11065 to the hash-map entry.
11067 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
11069 * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs.
11071 2020-02-27 Mark Williams <mwilliams@fb.com>
11073 * dwarf2out.c (file_name_acquire): Call remap_debug_filename.
11074 * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map,
11075 -ffile-prefix-map and -fmacro-prefix-map.
11076 * lto-streamer-out.c: Include file-prefix-map.h.
11077 (lto_output_location): Remap the file part of locations.
11079 2020-02-27 Jakub Jelinek <jakub@redhat.com>
11082 * gimplify.c (gimplify_init_constructor): Don't promote readonly
11083 DECL_REGISTER variables to TREE_STATIC.
11085 PR tree-optimization/93582
11086 PR tree-optimization/93945
11087 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with
11088 non-zero INTEGER_CST second argument and ref->offset or ref->size
11089 not a multiple of BITS_PER_UNIT.
11091 2020-02-27 Jonathan Wakely <jwakely@redhat.com>
11093 * doc/install.texi (Binaries): Update description of BullFreeware.
11095 2020-02-26 Sandra Loosemore <sandra@codesourcery.com>
11099 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in
11100 C++ Language Options, Warning Options, and Static Analyzer
11101 Options lists. Document negative form of options enabled by
11102 default. Move some things around to more accurately sort
11103 warnings by category.
11104 (C++ Dialect Options, Warning Options, Static Analyzer
11105 Options): Document negative form of options when enabled by
11106 default. Move some things around to more accurately sort
11107 warnings by category. Add some missing index entries.
11108 Light copy-editing.
11110 2020-02-26 Carl Love <cel@us.ibm.com>
11113 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on
11114 ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only
11115 for the vector unsigned short arguments. It is also listed as the
11116 name of the built-in for arguments vector unsigned short,
11117 vector unsigned int and vector unsigned long long built-ins. The
11118 name of the builtins for these arguments should be:
11119 __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and
11120 __builtin_crypto_vpmsumd respectively.
11122 2020-02-26 Richard Biener <rguenther@suse.de>
11124 * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count
11125 and load permutation.
11127 2020-02-26 Richard Sandiford <richard.sandiford@arm.com>
11129 PR middle-end/93843
11130 * optabs-tree.c (supportable_convert_operation): Reject types with
11133 2020-02-26 David Malcolm <dmalcolm@redhat.com>
11135 * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o.
11137 2020-02-26 Jakub Jelinek <jakub@redhat.com>
11139 PR tree-optimization/93820
11140 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE
11141 argument to ALL_INTEGER_CST_P boolean.
11142 (imm_store_chain_info::try_coalesce_bswap): Adjust caller.
11143 (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle
11144 adjacent INTEGER_CST store into merged_store->only_constants like
11147 2020-02-25 Jakub Jelinek <jakub@redhat.com>
11150 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity
11152 * cfghooks.c (verify_flow_info): Likewise.
11153 * predict.c (combine_predictions_for_bb): Likewise.
11154 * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo,
11155 sucessor -> successor.
11156 (find_traces_1_round): Fix comment typo, destinarion -> destination.
11157 * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors ->
11159 * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump
11160 message typo, sucessors -> successors.
11162 2020-02-25 Martin Sebor <msebor@redhat.com>
11164 * doc/extend.texi (attribute access): Correct an example.
11166 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
11168 * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
11170 (aarch64_init_simd_builtin_scalar_types): Register simd_bf.
11171 (VAR15, VAR16): New.
11172 * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
11173 (VD): Enable for V4BF.
11175 (VQ): Enable for V8BF.
11177 (VQ_NO2E): Likewise.
11178 (VDBL, Vdbl): Add V4BF.
11179 (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
11180 * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
11181 (bfloat16x8x2_t): Likewise.
11182 (bfloat16x4x3_t): Likewise.
11183 (bfloat16x8x3_t): Likewise.
11184 (bfloat16x4x4_t): Likewise.
11185 (bfloat16x8x4_t): Likewise.
11186 (vcombine_bf16): New.
11187 (vld1_bf16, vld1_bf16_x2): New.
11188 (vld1_bf16_x3, vld1_bf16_x4): New.
11189 (vld1q_bf16, vld1q_bf16_x2): New.
11190 (vld1q_bf16_x3, vld1q_bf16_x4): New.
11191 (vld1_lane_bf16): New.
11192 (vld1q_lane_bf16): New.
11193 (vld1_dup_bf16): New.
11194 (vld1q_dup_bf16): New.
11197 (vld2_dup_bf16): New.
11198 (vld2q_dup_bf16): New.
11201 (vld3_dup_bf16): New.
11202 (vld3q_dup_bf16): New.
11205 (vld4_dup_bf16): New.
11206 (vld4q_dup_bf16): New.
11207 (vst1_bf16, vst1_bf16_x2): New.
11208 (vst1_bf16_x3, vst1_bf16_x4): New.
11209 (vst1q_bf16, vst1q_bf16_x2): New.
11210 (vst1q_bf16_x3, vst1q_bf16_x4): New.
11211 (vst1_lane_bf16): New.
11212 (vst1q_lane_bf16): New.
11220 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
11222 * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF.
11223 (VALL_F16): Likewise.
11224 (VALLDI_F16): Likewise.
11226 (Vetype): Likewise.
11227 (vswap_width_name): Likewise.
11228 (VSWAP_WIDTH): Likewise.
11232 * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New.
11233 (vget_lane_bf16, vgetq_lane_bf16): New.
11234 (vcreate_bf16): New.
11235 (vdup_n_bf16, vdupq_n_bf16): New.
11236 (vdup_lane_bf16, vdup_laneq_bf16): New.
11237 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
11238 (vduph_lane_bf16, vduph_laneq_bf16): New.
11239 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
11240 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
11241 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
11242 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
11243 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
11244 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
11245 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
11246 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
11247 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
11248 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
11249 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New
11250 (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New
11251 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
11252 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
11253 (vreinterpretq_bf16_p128): New.
11254 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
11255 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
11256 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
11257 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
11258 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
11259 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
11260 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
11261 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
11262 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
11263 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
11264 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
11265 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
11266 (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New.
11267 (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New.
11268 (vreinterpretq_p128_bf16): New.
11270 2020-02-25 Dennis Zhang <dennis.zhang@arm.com>
11272 * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New
11273 (vbfdot_lane_f32, vbfdotq_laneq_f32): New.
11274 (vbfdot_laneq_f32, vbfdotq_lane_f32): New.
11275 * config/arm/arm_neon_builtins.def (vbfdot): New entry.
11276 (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise.
11277 * config/arm/iterators.md (VSF2BF): New attribute.
11278 * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry.
11279 (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise.
11280 (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise.
11282 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org>
11284 * config/arm/arm.md (required_for_purecode): New attribute.
11285 (enabled): Handle required_for_purecode.
11286 * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to
11287 work with -mpure-code.
11289 2020-02-25 Jakub Jelinek <jakub@redhat.com>
11291 PR rtl-optimization/93908
11292 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src
11295 2019-02-25 Eric Botcazou <ebotcazou@adacore.com>
11297 * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode.
11299 2020-02-25 Roman Zhuykov <zhroma@ispras.ru>
11301 * doc/install.texi (--enable-checking): Adjust wording.
11303 2020-02-25 Richard Biener <rguenther@suse.de>
11305 PR tree-optimization/93868
11306 * tree-vect-slp.c (slp_copy_subtree): New function.
11307 (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before
11308 re-arranging stmts in it.
11310 2020-02-25 Jakub Jelinek <jakub@redhat.com>
11312 PR middle-end/93874
11313 * passes.c (pass_manager::dump_passes): Create a cgraph node for the
11314 dummy function and remove it at the end.
11316 PR translation/93864
11317 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo
11318 paramter -> parameter.
11319 * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise.
11320 * ipa-prop.h (struct ipa_agg_replacement_value): Likewise.
11322 2020-02-24 Roman Zhuykov <zhroma@ispras.ru>
11324 * doc/install.texi (--enable-checking): Properly document current
11326 (--enable-stage1-checking): Minor clarification about bootstrap.
11328 2020-02-24 David Malcolm <dmalcolm@redhat.com>
11331 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that
11332 -fanalyzer-checker=taint is also required.
11333 (-fanalyzer-checker=): Note that providing this option enables the
11334 given checker, and doing so may be required for checkers that are
11335 disabled by default.
11337 2020-02-24 David Malcolm <dmalcolm@redhat.com>
11339 * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows
11340 significant control flow events; add a "3" which shows all
11341 control flow events; the old "3" becomes "4".
11343 2020-02-24 Jakub Jelinek <jakub@redhat.com>
11345 PR tree-optimization/93582
11346 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider
11347 pd.offset and pd.size to be counted in bits rather than bytes, add
11348 support for maxsizei that is not a multiple of BITS_PER_UNIT and
11349 handle bitfield stores and loads.
11350 (vn_reference_lookup_3): Don't call ranges_known_overlap_p with
11351 uncomparable quantities - bytes vs. bits. Allow push_partial_def
11352 on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust
11353 pd.offset/pd.size to be counted in bits rather than bytes.
11354 Formatting fix. Rename shadowed len variable to buflen.
11356 2020-02-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
11357 Kugan Vivekandarajah <kugan.vivekanandarajah@linaro.org>
11360 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function.
11361 (driver::main): Call putenv_COLLECT_AS_OPTIONS.
11362 * opts-common.c (parse_options_from_collect_gcc_options): New function.
11363 (prepend_xassembler_to_collect_as_options): Likewise.
11364 * opts.h (parse_options_from_collect_gcc_options): Declare prototype.
11365 (prepend_xassembler_to_collect_as_options): Likewise.
11366 * lto-opts.c (lto_write_options): Stream assembler options
11367 in COLLECT_AS_OPTIONS.
11368 * lto-wrapper.c (xassembler_options_error): New static variable.
11369 (get_options_from_collect_gcc_options): Move parsing options code to
11370 parse_options_from_collect_gcc_options and call it.
11371 (merge_and_complain): Validate -Xassembler options.
11372 (append_compiler_options): Handle OPT_Xassembler.
11373 (run_gcc): Append command line -Xassembler options to
11374 collect_gcc_options.
11375 * doc/invoke.texi: Add documentation about using Xassembler
11378 2020-02-24 Kito Cheng <kito.cheng@sifive.com>
11380 * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen
11382 (riscv_rtx_costs): Update cost model for LTGT.
11384 2020-02-23 Vladimir Makarov <vmakarov@redhat.com>
11386 PR rtl-optimization/93564
11387 * ira-color.c (struct update_cost_queue_elem): New member start.
11388 (queue_update_cost, get_next_update_cost): Add new arg start.
11389 (allocnos_conflict_p): New function.
11390 (update_costs_from_allocno): Add new arg conflict_cost_update_p.
11391 Add checking conflicts with allocnos_conflict_p.
11392 (update_costs_from_prefs, restore_costs_from_copies): Adjust
11393 update_costs_from_allocno calls.
11394 (update_conflict_hard_regno_costs): Add checking conflicts with
11395 allocnos_conflict_p. Adjust calls of queue_update_cost and
11396 get_next_update_cost.
11397 (assign_hard_reg): Adjust calls of queue_update_cost. Add
11399 (bucket_allocno_compare_func): Restore previous version.
11401 2020-02-21 John David Anglin <danglin@gcc.gnu.org>
11403 * gcc/config/pa/pa.c (pa_function_value): Fix check for word and
11404 double-word size when handling aggregate return values.
11405 * gcc/config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate
11406 that homogeneous SFmode and DFmode aggregates are passed and returned
11407 in general registers.
11409 2020-02-21 Jakub Jelinek <jakub@redhat.com>
11411 PR translation/93759
11412 * opts.c (print_filtered_help): Translate help before appending
11413 messages to it rather than after that.
11415 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
11417 PR rtl-optimization/PR92989
11418 * lra-lives.c (process_bb_lives): Restore the original order
11419 of the bb liveness update. Call make_hard_regno_dead for each
11420 register clobbered at the start of an EH receiver.
11422 2020-02-18 Feng Xue <fxue@os.amperecomputing.com>
11425 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as
11426 self-recursively generated.
11428 2020-02-21 Iain Sandoe <iain@sandoe.co.uk>
11431 * config/darwin-c.c (pop_field_alignment): Adjust quoting of
11434 2020-02-21 Mihail Ionescu <mihail.ionescu@arm.com>
11436 * doc/sourcebuild.texi (arm_v8_1m_mve_ok):
11437 Document new target supports option.
11439 2020-02-21 Dennis Zhang <dennis.zhang@arm.com>
11441 * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New.
11442 * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New.
11443 * config/arm/iterators.md (MATMUL): New iterator.
11444 (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US.
11445 (mmla_sfx): New attribute.
11446 * config/arm/neon.md (neon_<sup>mmlav16qi): New.
11447 * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New.
11448 (UNSPEC_MATMUL_US): New.
11450 2020-02-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
11452 * config/arm/arm.md: Prevent scalar shifts from being used when big
11455 2020-02-21 Jan Hubicka <hubicka@ucw.cz>
11456 Richard Biener <rguenther@suse.de>
11458 PR tree-optimization/93586
11459 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk
11460 after mismatched array refs; do not sure type size information to
11461 recover from unmatched referneces with !flag_strict_aliasing_p.
11463 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
11465 * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ...
11466 (gather_load<mode>v64si): ... this and set operand 2 to V64SI.
11467 (scatter_store<mode>): Rename to ...
11468 (scatter_store<mode>v64si): ... this and set operand 1 to V64SI.
11469 (scatter<mode>_exec): Delete. Move contents ...
11470 (mask_scatter_store<mode>): ... here, and rename that to ...
11471 (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI.
11472 Remove mode conversion.
11473 (mask_gather_load<mode>): Rename to ...
11474 (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI.
11475 Remove mode conversion.
11476 * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
11478 2020-02-21 Martin Jambor <mjambor@suse.cz>
11480 PR tree-optimization/93845
11481 * tree-sra.c (verify_sra_access_forest): Only test access size of
11484 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
11486 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs.
11487 * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber.
11488 (addv64di3_exec): Likewise.
11489 (subv64di3): Likewise.
11490 (subv64di3_exec): Likewise.
11491 (addv64di3_zext): Likewise.
11492 (addv64di3_zext_exec): Likewise.
11493 (addv64di3_zext_dup): Likewise.
11494 (addv64di3_zext_dup_exec): Likewise.
11495 (addv64di3_zext_dup2): Likewise.
11496 (addv64di3_zext_dup2_exec): Likewise.
11497 (addv64di3_sext_dup2): Likewise.
11498 (addv64di3_sext_dup2_exec): Likewise.
11499 (<expander>v64di3): Likewise.
11500 (<expander>v64di3_exec): Likewise.
11501 (*<reduc_op>_dpp_shr_v64di): Likewise.
11502 (*plus_carry_dpp_shr_v64di): Likewise.
11503 * config/gcn/gcn.md (adddi3): Likewise.
11504 (addptrdi3): Likewise.
11505 (<expander>di3): Likewise.
11507 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
11509 * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
11511 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
11513 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE
11514 support. Use aarch64_emit_mult instead of emitting multiplication
11515 instructions directly.
11516 * config/aarch64/aarch64-sve.md (sqrt<mode>2, rsqrt<mode>2)
11517 (@aarch64_rsqrte<mode>, @aarch64_rsqrts<mode>): New expanders.
11519 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
11521 * config/aarch64/aarch64.c (aarch64_emit_mult): New function.
11522 (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult
11523 instead of emitting multiplication instructions directly.
11524 * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator.
11525 * config/aarch64/aarch64-sve.md (div<mode>3, @aarch64_frecpe<mode>)
11526 (@aarch64_frecps<mode>): New expanders.
11528 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
11530 * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate
11531 on and produce uint64_ts rather than ints.
11532 (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts.
11533 (cpu_approx_modes): Change the fields from unsigned int to uint64_t.
11535 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
11537 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create
11538 an unused xmsk register when handling approximate rsqrt.
11540 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
11542 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted
11543 flag_finite_math_only condition.
11545 2020-02-20 Uroš Bizjak <ubizjak@gmail.com>
11548 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand
11549 to destination operand for shufps alternative.
11550 (*vec_extractv2si_1): Ditto.
11552 2020-02-20 Peter Bergner <bergner@linux.ibm.com>
11555 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX
11558 2020-02-20 Martin Liska <mliska@suse.cz>
11560 PR translation/93831
11561 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode.
11563 2020-02-20 Martin Liska <mliska@suse.cz>
11565 PR translation/93830
11566 * common/config/avr/avr-common.c: Remote trailing "|".
11568 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
11570 * collect2.c (maybe_run_lto_and_relink): Fix typo in
11573 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
11575 PR tree-optimization/93767
11576 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the
11577 access-size bias from the offset calculations for negative strides.
11579 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
11581 * collect2.c (c_file, o_file): Make const again.
11582 (ldout,lderrout, dump_ld_file): Remove.
11583 (tool_cleanup): Avoid calling not signal-safe functions.
11584 (maybe_run_lto_and_relink): Avoid possible signal handler
11585 access to unintialzed memory (lto_o_files).
11586 (main): Avoid leaking temp files in $TMPDIR.
11587 Initialize c_file/o_file with concat, which avoids exposing
11588 uninitialized memory to signal handler, which calls unlink(!).
11589 Avoid calling maybe_unlink when the main function returns,
11590 since the atexit handler is already doing this.
11591 * collect2.h (dump_ld_file, ldout, lderrout): Remove.
11593 2020-02-19 Martin Jambor <mjambor@suse.cz>
11595 PR tree-optimization/93776
11596 * tree-sra.c (create_access): Do not create zero size accesses.
11597 (get_access_for_expr): Do not search for zero sized accesses.
11599 2020-02-19 Martin Jambor <mjambor@suse.cz>
11601 PR tree-optimization/93667
11602 * tree-sra.c (scalarizable_type_p): Return false if record fields
11603 do not follow wach other.
11605 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
11607 * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
11608 rather than fmv.x.s/fmv.s.x.
11610 2020-02-18 James Greenhalgh <james.greenhalgh@arm.com>
11612 * config/aarch64/aarch64-simd-builtins.def
11613 (intrinsic_vec_smult_lo_): New.
11614 (intrinsic_vec_umult_lo_): Likewise.
11615 (vec_widen_smult_hi_): Likewise.
11616 (vec_widen_umult_hi_): Likewise.
11617 * config/aarch64/aarch64-simd.md
11618 (aarch64_intrinsic_vec_<su>mult_lo_<mode>): New.
11619 * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics.
11620 (vmull_high_s16): Likewise.
11621 (vmull_high_s32): Likewise.
11622 (vmull_high_u8): Likewise.
11623 (vmull_high_u16): Likewise.
11624 (vmull_high_u32): Likewise.
11625 (vmull_s8): Likewise.
11626 (vmull_s16): Likewise.
11627 (vmull_s32): Likewise.
11628 (vmull_u8): Likewise.
11629 (vmull_u16): Likewise.
11630 (vmull_u32): Likewise.
11632 2020-02-18 Martin Liska <mliska@suse.cz>
11634 * value-prof.c (stream_out_histogram_value): Restore LTO PGO
11635 bootstrap by missing removal of invalid sanity check.
11637 2020-02-18 Martin Liska <mliska@suse.cz>
11640 * ipa-icf-gimple.c (func_checker::compare_gimple_assign):
11641 Always compare LHS of gimple_assign.
11643 2020-02-18 Martin Liska <mliska@suse.cz>
11646 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute
11647 and return type of functions.
11648 * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl):
11649 Drop MALLOC attribute for void functions.
11650 * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop
11651 malloc_state for a new VOID clone.
11653 2020-02-18 Martin Liska <mliska@suse.cz>
11656 * common.opt: Add -fprofile-reproducibility.
11657 * doc/invoke.texi: Document it.
11658 * value-prof.c (dump_histogram_value):
11659 Document and support behavior for counters[0]
11660 being a negative value.
11661 (get_nth_most_common_value): Handle negative
11662 counters[0] in respect to flag_profile_reproducible.
11664 2020-02-18 Jakub Jelinek <jakub@redhat.com>
11667 * cgraph.c (verify_speculative_call): Use speculative_id instead of
11668 speculative_uid in messages. Remove trailing whitespace from error
11669 message. Use num_speculative_call_targets instead of
11670 num_speculative_targets in a message.
11671 (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in
11672 edge messages and stmt instead of cal_stmt in reference message.
11674 PR tree-optimization/93780
11675 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p
11676 before calling build_vector_type.
11677 (execute_update_addresses_taken): Likewise.
11680 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help
11681 typo, functoin -> function.
11682 * tree.c (free_lang_data_in_decl): Fix comment typo,
11683 functoin -> function.
11684 * ipa-visibility.c (cgraph_externally_visible_p): Likewise.
11686 2020-02-17 David Malcolm <dmalcolm@redhat.com>
11688 * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs
11690 (print_option_information): Don't call get_option_url if URLs
11693 2020-02-17 Alexandre Oliva <oliva@adacore.com>
11695 * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete
11696 handling of register_common-less targets.
11698 2020-02-17 Martin Liska <mliska@suse.cz>
11701 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar.
11703 2020-02-17 Martin Liska <mliska@suse.cz>
11705 PR translation/93755
11706 * config/rs6000/rs6000.c (rs6000_option_override_internal):
11709 2020-02-17 Martin Liska <mliska@suse.cz>
11712 * config/rx/elf.opt: Fix typo.
11714 2020-02-17 Richard Biener <rguenther@suse.de>
11717 * opts-global.c (print_ignored_options): Use inform and
11720 2020-02-17 Jiufu Guo <guojiufu@linux.ibm.com>
11723 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber.
11725 2020-02-16 Uroš Bizjak <ubizjak@gmail.com>
11728 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2.
11729 (atan2<mode>3): Update operand order in the call to gen_atan2xf3.
11731 2020-02-15 Jason Merrill <jason@redhat.com>
11733 * doc/invoke.texi (C Dialect Options): Add -std=c++20.
11735 2020-02-15 Jakub Jelinek <jakub@redhat.com>
11737 PR tree-optimization/93744
11738 * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0,
11739 A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A,
11740 A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make
11741 sure @2 in the first and @1 in the other patterns has no side-effects.
11743 2020-02-15 David Malcolm <dmalcolm@redhat.com>
11744 Bernd Edlinger <bernd.edlinger@hotmail.de>
11748 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define.
11749 * configure.ac (--with-diagnostics-urls): New configuration
11750 option, based on --with-diagnostics-color.
11751 (DIAGNOSTICS_URLS_DEFAULT): New define.
11752 * config.h: Regenerate.
11753 * configure: Regenerate.
11754 * diagnostic.c (diagnostic_urls_init): Handle -1 for
11755 DIAGNOSTICS_URLS_DEFAULT from configure-time
11756 --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS
11757 and TERM_URLS environment variable.
11758 * diagnostic-url.h (diagnostic_url_format): New enum type.
11759 (diagnostic_urls_enabled_p): rename to...
11760 (determine_url_format): ... this, and change return type.
11761 * diagnostic-color.c (parse_env_vars_for_urls): New helper function.
11762 (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal,
11763 the linux console, and mingw.
11764 (diagnostic_urls_enabled_p): rename to...
11765 (determine_url_format): ... this, and adjust.
11766 * pretty-print.h (pretty_printer::show_urls): rename to...
11767 (pretty_printer::url_format): ... this, and change to enum.
11768 * pretty-print.c (pretty_printer::pretty_printer,
11769 pp_begin_url, pp_end_url, test_urls): Adjust.
11770 * doc/install.texi (--with-diagnostics-urls): Document the new
11771 configuration option.
11772 (--with-diagnostics-color): Document the existing interaction
11773 with GCC_COLORS better.
11774 * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS
11775 vindex reference. Update description of defaults based on the above.
11776 (-fdiagnostics-color): Update description of how -fdiagnostics-color
11777 interacts with GCC_COLORS.
11779 2020-02-14 Eric Botcazou <ebotcazou@adacore.com>
11782 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in
11783 conjunction with TARGET_GNU_TLS in early return.
11785 2020-02-14 Alexander Monakov <amonakov@ispras.ru>
11787 * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if
11788 the mode is not wider than UNITS_PER_WORD.
11790 2020-02-14 Martin Jambor <mjambor@suse.cz>
11792 PR tree-optimization/93516
11793 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create
11794 access of the same type as the parent.
11795 (propagate_subaccesses_from_lhs): Likewise.
11797 2020-02-14 Hongtao Liu <hongtao.liu@intel.com>
11800 * config/i386/avx512vbmi2intrin.h
11801 (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16,
11802 _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32,
11803 _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32,
11804 _m512_shrdi_epi64, _m512_mask_shrdi_epi64,
11805 _m512_maskz_shrdi_epi64, _mm512_shldi_epi16,
11806 _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16,
11807 _mm512_shldi_epi32, _mm512_mask_shldi_epi32,
11808 _mm512_maskz_shldi_epi32, _mm512_shldi_epi64,
11809 _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo
11810 of lacking a closing parenthesis.
11811 * config/i386/avx512vbmi2vlintrin.h
11812 (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16,
11813 _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32,
11814 _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32,
11815 _m256_shrdi_epi64, _m256_mask_shrdi_epi64,
11816 _m256_maskz_shrdi_epi64, _mm256_shldi_epi16,
11817 _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16,
11818 _mm256_shldi_epi32, _mm256_mask_shldi_epi32,
11819 _mm256_maskz_shldi_epi32, _mm256_shldi_epi64,
11820 _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64,
11821 _mm_shrdi_epi16, _mm_mask_shrdi_epi16,
11822 _mm_maskz_shrdi_epi16, _mm_shrdi_epi32,
11823 _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32,
11824 _mm_shrdi_epi64, _mm_mask_shrdi_epi64,
11825 _m_maskz_shrdi_epi64, _mm_shldi_epi16,
11826 _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16,
11827 _mm_shldi_epi32, _mm_mask_shldi_epi32,
11828 _mm_maskz_shldi_epi32, _mm_shldi_epi64,
11829 _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto.
11831 2020-02-13 H.J. Lu <hongjiu.lu@intel.com>
11834 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
11835 the target function entry.
11837 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
11839 * common/config/arc/arc-common.c (arc_option_optimization_table):
11840 Disable if-conversion step when optimized for size.
11842 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
11844 * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
11845 R12-R15 are always in ARCOMPACT16_REGS register class.
11846 * config/arc/arc.opt (mq-class): Deprecate.
11847 * config/arc/constraint.md ("q"): Remove dependency on mq-class
11849 * doc/invoke.texi (mq-class): Update text.
11850 * common/config/arc/arc-common.c (arc_option_optimization_table):
11853 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
11855 * config/arc/arc.c (arc_insn_cost): New function.
11856 (TARGET_INSN_COST): Define.
11857 * config/arc/arc.md (cost): New attribute.
11858 (add_n): Use arc_nonmemory_operand.
11859 (ashlsi3_insn): Likewise, also update constraints.
11860 (ashrsi3_insn): Likewise.
11861 (rotrsi3): Likewise.
11862 (add_shift): Likewise.
11863 * config/arc/predicates.md (arc_nonmemory_operand): New predicate.
11865 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
11867 * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi
11869 (umulsidi_600): Likewise.
11871 2020-02-13 Jakub Jelinek <jakub@redhat.com>
11874 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8,
11875 _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8,
11876 _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8,
11877 _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W,
11878 pass __A to the builtin followed by __W instead of __A followed by
11880 * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32,
11881 _mm512_mask_popcnt_epi64): Likewise.
11882 * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32,
11883 _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64,
11884 _mm256_mask_popcnt_epi64): Likewise.
11886 PR tree-optimization/93582
11887 * fold-const.h (shift_bytes_in_array_left,
11888 shift_bytes_in_array_right): Declare.
11889 * fold-const.c (shift_bytes_in_array_left,
11890 shift_bytes_in_array_right): New function, moved from
11891 gimple-ssa-store-merging.c, no longer static.
11892 * gimple-ssa-store-merging.c (shift_bytes_in_array): Move
11893 to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left.
11894 (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c.
11895 (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of
11896 shift_bytes_in_array.
11897 (verify_shift_bytes_in_array): Rename to ...
11898 (verify_shift_bytes_in_array_left): ... this. Use
11899 shift_bytes_in_array_left instead of shift_bytes_in_array.
11900 (store_merging_c_tests): Call verify_shift_bytes_in_array_left
11901 instead of verify_shift_bytes_in_array.
11902 * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr
11903 / native_interpret_expr where the store covers all needed bits,
11904 punt on PDP-endian, otherwise allow all involved offsets and sizes
11905 not to be byte-aligned.
11908 * config/i386/sse.md (k<code><mode>): Drop mode from last operand and
11909 use const_0_to_255_operand predicate instead of immediate_operand.
11910 (avx512dq_fpclass<mode><mask_scalar_merge_name>,
11911 avx512dq_vmfpclass<mode><mask_scalar_merge_name>,
11912 vgf2p8affineinvqb_<mode><mask_name>,
11913 vgf2p8affineqb_<mode><mask_name>): Drop mode from
11914 const_0_to_255_operand predicated operands.
11916 2020-02-12 Jeff Law <law@redhat.com>
11918 * config/h8300/h8300.md (comparison shortening peepholes): Use
11919 a mode iterator to merge the HImode and SImode peepholes.
11921 2020-02-12 Jakub Jelinek <jakub@redhat.com>
11923 PR middle-end/93663
11924 * real.c (is_even): Make static. Function comment fix.
11925 (is_halfway_below): Make static, don't assert R is not inf/nan,
11926 instead return false for those. Small formatting fixes.
11928 2020-02-12 Martin Sebor <msebor@redhat.com>
11930 PR middle-end/93646
11931 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename...
11932 (handle_builtin_stxncpy_strncat): ...to this. Change first argument.
11933 Issue only -Wstringop-overflow strncat, never -Wstringop-truncation.
11934 (strlen_check_and_optimize_call): Adjust callee name.
11936 2020-02-12 Jeff Law <law@redhat.com>
11938 * config/h8300/h8300.md (comparison shortening peepholes): Drop
11939 (and (xor)) variant. Combine other two into single peephole.
11941 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
11943 PR rtl-optimization/93565
11944 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs.
11946 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
11948 * config/aarch64/aarch64-simd.md
11949 (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern.
11950 * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of
11951 generating separate ADDV and zero_extend patterns.
11952 * config/aarch64/iterators.md (VDQV_E): New iterator.
11954 2020-02-12 Jeff Law <law@redhat.com>
11956 * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns,
11957 expanders, splits, etc.
11958 (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise.
11959 (stpcpy_internal_<mode>, stpcpy splitter): Likewise.
11960 (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise.
11961 * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function.
11962 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise
11963 * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused
11964 function prototype.
11965 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise.
11967 2020-02-12 Jakub Jelinek <jakub@redhat.com>
11970 * config/i386/sse.md (VI48F_256_DQ): New mode iterator.
11971 (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove
11972 TARGET_AVX512DQ from condition.
11973 (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition>
11974 instead of <mask_mode512bit_condition> in condition. If
11975 TARGET_AVX512DQ is false, emit vextract*64x4 instead of
11977 (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition>
11980 2020-02-12 Kewen Lin <linkw@gcc.gnu.org>
11983 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn.
11985 2020-02-12 Segher Boessenkool <segher@kernel.crashing.org>
11987 * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof
11988 where strlen is more legible.
11989 (rs6000_builtin_vectorized_libmass): Ditto.
11990 (rs6000_print_options_internal): Ditto.
11992 2020-02-11 Martin Sebor <msebor@redhat.com>
11994 PR tree-optimization/93683
11995 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set.
11997 2020-02-11 Michael Meissner <meissner@linux.ibm.com>
11999 * config/rs6000/predicates.md (cint34_operand): Rename the
12000 -mprefixed-addr option to be -mprefixed.
12001 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename
12002 the -mprefixed-addr option to be -mprefixed.
12003 (OTHER_FUTURE_MASKS): Likewise.
12004 (POWERPC_MASKS): Likewise.
12005 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
12006 the -mprefixed-addr option to be -mprefixed. Change error
12007 messages to refer to -mprefixed.
12008 (num_insns_constant_gpr): Rename the -mprefixed-addr option to be
12010 (rs6000_legitimate_offset_address_p): Likewise.
12011 (rs6000_mode_dependent_address): Likewise.
12012 (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be
12013 "-mprefixed" for target attributes and pragmas.
12014 (address_to_insn_form): Rename the -mprefixed-addr option to be
12016 (rs6000_adjust_insn_length): Likewise.
12017 * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the
12018 -mprefixed-addr option to be -mprefixed.
12019 (ASM_OUTPUT_OPCODE): Likewise.
12020 * config/rs6000/rs6000.md (prefixed insn attribute): Rename the
12021 -mprefixed-addr option to be -mprefixed.
12022 * config/rs6000/rs6000.opt (-mprefixed): Rename the
12023 -mprefixed-addr option to be prefixed. Change the option from
12024 being undocumented to being documented.
12025 * doc/invoke.texi (RS/6000 and PowerPC Options): Document the
12026 -mprefixed option. Update the -mpcrel documentation to mention
12029 2020-02-11 Hans-Peter Nilsson <hp@axis.com>
12031 * ira-conflicts.c (print_hard_reg_set): Correct output for sets
12032 including FIRST_PSEUDO_REGISTER - 1.
12033 * ira-color.c (print_hard_reg_set): Ditto.
12035 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com>
12037 * config/arm/arm-builtins.c (enum arm_type_qualifiers):
12038 (USTERNOP_QUALIFIERS): New define.
12039 (USMAC_LANE_QUADTUP_QUALIFIERS): New define.
12040 (SUMAC_LANE_QUADTUP_QUALIFIERS): New define.
12041 (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX.
12042 (arm_expand_builtin_1): Add qualifier_lane_quadtup_index.
12043 * config/arm/arm_neon.h (vusdot_s32): New.
12044 (vusdot_lane_s32): New.
12045 (vusdotq_lane_s32): New.
12046 (vsudot_lane_s32): New.
12047 (vsudotq_lane_s32): New.
12048 * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New.
12049 * config/arm/iterators.md (DOTPROD_I8MM): New.
12050 (sup, opsuffix): Add <us/su>.
12051 * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New.
12052 * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New.
12054 2020-02-11 Richard Biener <rguenther@suse.de>
12056 PR tree-optimization/93661
12057 PR tree-optimization/93662
12058 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard
12059 tree_to_poly_int64.
12060 * tree-sra.c (get_access_for_expr): Likewise.
12062 2020-02-10 Jakub Jelinek <jakub@redhat.com>
12065 * config/i386/sse.md (VI_256_AVX2): New mode iterator.
12066 (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256.
12067 Change condition from TARGET_AVX2 to TARGET_AVX.
12069 2020-02-10 Iain Sandoe <iain@sandoe.co.uk>
12072 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last
12073 argument of strncmp.
12075 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
12077 Try to generate zero-based comparisons.
12078 * config/cris/cris.c (cris_reduce_compare): New function.
12079 * config/cris/cris-protos.h (cris_reduce_compare): Add prototype.
12080 * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4")
12081 (cstore<mode>4"): Apply cris_reduce_compare in expanders.
12083 2020-02-10 Richard Earnshaw <rearnsha@arm.com>
12086 * config/arm/arm.md (movsi_compare0): Allow SP as a source register
12087 in Thumb state and also as a destination in Arm state. Add T16
12090 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
12092 * md.texi (Define Subst): Match closing paren in example.
12094 2020-02-10 Jakub Jelinek <jakub@redhat.com>
12098 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last
12099 arguments of strncmp.
12101 2020-02-10 Feng Xue <fxue@os.amperecomputing.com>
12104 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge
12105 but different source value.
12106 (adjust_callers_for_value_intersection): New function.
12107 (gather_edges_for_value): Adjust order of callers to let a
12108 non-self-recursive caller be the first element.
12109 (self_recursive_pass_through_p): Add a new parameter "simple", and
12110 check generalized self-recursive pass-through jump function.
12111 (self_recursive_agg_pass_through_p): Likewise.
12112 (find_more_scalar_values_for_callers_subset): Compute value from
12113 pass-through jump function for self-recursive.
12114 (intersect_with_plats): Cleanup previous implementation code for value
12115 itersection with self-recursive call edge.
12116 (intersect_with_agg_replacements): Likewise.
12117 (intersect_aggregates_with_edge): Deduce value from pass-through jump
12118 function for self-recursive call edge. Cleanup previous implementation
12119 code for value intersection with self-recursive call edge.
12120 (decide_whether_version_node): Remove dead callers and adjust order
12121 to let a non-self-recursive caller be the first element.
12123 2020-02-09 Uroš Bizjak <ubizjak@gmail.com>
12125 * recog.c: Move pass_split_before_sched2 code in front of
12126 pass_split_before_regstack.
12127 (pass_data_split_before_sched2): Rename pass to split3 from split4.
12128 (pass_data_split_before_regstack): Rename pass to split4 from split3.
12129 (rest_of_handle_split_before_sched2): Remove.
12130 (pass_split_before_sched2::execute): Unconditionally call
12132 (enable_split_before_sched2): New function.
12133 (pass_split_before_sched2::gate): Use enable_split_before_sched2.
12134 (pass_split_before_regstack::gate): Ditto.
12135 * config/nds32/nds32.c (nds32_split_double_word_load_store_p):
12136 Update name check for renamed split4 pass.
12137 * config/sh/sh.c (register_sh_passes): Update pass insertion
12138 point for renamed split4 pass.
12140 2020-02-09 Jakub Jelinek <jakub@redhat.com>
12142 * gimplify.c (gimplify_adjust_omp_clauses_1): Promote
12143 DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid
12144 copying them around between host and target.
12146 2020-02-08 Andrew Pinski <apinski@marvell.com>
12149 * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
12150 STRICT_ALIGNMENT also.
12152 2020-02-08 Jim Wilson <jimw@sifive.com>
12155 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
12157 2020-02-08 Uroš Bizjak <ubizjak@gmail.com>
12158 Jakub Jelinek <jakub@redhat.com>
12161 * config/i386/i386.h (CALL_USED_REGISTERS): Make
12162 xmm16-xmm31 call-used even in 64-bit ms-abi.
12164 2020-02-07 Dennis Zhang <dennis.zhang@arm.com>
12166 * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry.
12167 (simd_ummla, simd_usmmla): Likewise.
12168 * config/aarch64/aarch64-simd.md (aarch64_simd_<sur>mmlav16qi): New.
12169 * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New.
12170 (vusmmlaq_s32): New.
12172 2020-02-07 Richard Biener <rguenther@suse.de>
12174 PR middle-end/93519
12175 * tree-inline.c (fold_marked_statements): Do a PRE walk,
12176 skipping unreachable regions.
12177 (optimize_inline_calls): Skip folding stmts when we didn't
12180 2020-02-07 H.J. Lu <hongjiu.lu@intel.com>
12183 * config/i386/i386.c (function_arg_ms_64): Add a type argument.
12184 Don't return aggregates with only SFmode and DFmode in SSE
12186 (ix86_function_arg): Pass arg.type to function_arg_ms_64.
12188 2020-02-07 Jakub Jelinek <jakub@redhat.com>
12191 * config/rs6000/rs6000-logue.c
12192 (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn,
12193 if it fails, move rs into end_addr and retry. Add
12194 REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or
12195 the insn pattern doesn't describe well what exactly happens to
12199 * config/i386/predicates.md (avx_identity_operand): Remove.
12200 * config/i386/sse.md (*avx_vec_concat<mode>_1): Remove.
12201 (avx_<castmode><avxsizesuffix>_<castmode>,
12202 avx512f_<castmode><avxsizesuffix>_256<castmode>): Change patterns to
12203 a VEC_CONCAT of the operand and UNSPEC_CAST.
12204 (avx512f_<castmode><avxsizesuffix>_<castmode>): Change pattern to
12205 a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with
12209 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear
12210 recog_data.insn if distance_non_agu_define changed it.
12212 2020-02-06 Michael Meissner <meissner@linux.ibm.com>
12215 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
12216 we only had X-FORM (reg+reg) addressing for vectors. Also before
12217 ISA 3.0, we only had X-FORM addressing for scalars in the
12218 traditional Altivec registers.
12220 2020-02-06 <zhongyunde@huawei.com>
12221 Vladimir Makarov <vmakarov@redhat.com>
12223 PR rtl-optimization/93561
12224 * lra-assigns.c (spill_for): Check that tested hard regno is not out of
12225 hard register range.
12227 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
12229 * config/aarch64/aarch64.md (aarch64_movk<mode>): Add a type
12232 2020-02-06 Segher Boessenkool <segher@kernel.crashing.org>
12234 * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case
12235 where the low and the high 32 bits are equal to each other specially,
12236 with an rldimi instruction.
12238 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
12240 * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main.
12242 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
12244 * config/arm/arm-tables.opt: Regenerate.
12246 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
12249 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare.
12250 * config/aarch64/aarch64.c (aarch64_movk_shift): New function.
12251 * config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern.
12253 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
12255 PR rtl-optimization/87763
12256 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern.
12258 2020-02-06 Delia Burduv <delia.burduv@arm.com>
12260 * config/aarch64/aarch64-simd-builtins.def
12261 (bfmlaq): New built-in function.
12262 (bfmlalb): New built-in function.
12263 (bfmlalt): New built-in function.
12264 (bfmlalb_lane): New built-in function.
12265 (bfmlalt_lane): New built-in function.
12266 * config/aarch64/aarch64-simd.md
12267 (aarch64_bfmmlaqv4sf): New pattern.
12268 (aarch64_bfmlal<bt>v4sf): New pattern.
12269 (aarch64_bfmlal<bt>_lane<q>v4sf): New pattern.
12270 * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic.
12271 (vbfmlalbq_f32): New intrinsic.
12272 (vbfmlaltq_f32): New intrinsic.
12273 (vbfmlalbq_lane_f32): New intrinsic.
12274 (vbfmlaltq_lane_f32): New intrinsic.
12275 (vbfmlalbq_laneq_f32): New intrinsic.
12276 (vbfmlaltq_laneq_f32): New intrinsic.
12277 * config/aarch64/iterators.md (BF_MLA): New int iterator.
12278 (bt): New int attribute.
12280 2020-02-06 Uroš Bizjak <ubizjak@gmail.com>
12282 * config/i386/i386.md (*pushtf): Emit "#" instead of
12283 calling gcc_unreachable in insn output.
12286 (*pushsf_rex64): Ditto for alternatives other than 1.
12287 (*pushsf): Ditto for alternatives other than 1.
12289 2020-02-06 Martin Liska <mliska@suse.cz>
12291 PR gcov-profile/91971
12292 PR gcov-profile/93466
12293 * coverage.c (coverage_init): Revert mangling of
12294 path into filename. It can lead to huge filename length.
12295 Creation of subfolders seem more natural.
12297 2020-02-06 Stam Markianos-Wright <stam.markianos-wright@arm.com>
12300 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New.
12301 (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs.
12302 Use arm_block_arith_comp_libfuncs_for_mode for HFmode.
12304 2020-02-06 Jakub Jelinek <jakub@redhat.com>
12307 * config/i386/predicates.md (avx_identity_operand): New predicate.
12308 * config/i386/sse.md (*avx_vec_concat<mode>_1): New
12309 define_insn_and_split.
12312 * omp-low.c (use_pointer_for_field): For nested constructs, also
12313 look for map clauses on target construct.
12314 (scan_omp_1_stmt) <case GIMPLE_OMP_TARGET>: Bump temporarily
12315 taskreg_nesting_level.
12318 * gimplify.c (gimplify_scan_omp_clauses) <do_notice>: If adding
12319 shared clause, call omp_notice_variable on outer context if any.
12321 2020-02-05 Jason Merrill <jason@redhat.com>
12324 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has
12325 non-zero address even if weak and not yet defined.
12327 2020-02-05 Martin Sebor <msebor@redhat.com>
12329 PR tree-optimization/92765
12330 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL.
12331 * tree-ssa-strlen.c (compute_string_length): Remove.
12332 (determine_min_objsize): Remove.
12333 (get_len_or_size): Add an argument. Call get_range_strlen_dynamic.
12334 Avoid using type size as the upper bound on string length.
12335 (handle_builtin_string_cmp): Add an argument. Adjust.
12336 (strlen_check_and_optimize_call): Pass additional argument to
12337 handle_builtin_string_cmp.
12339 2020-02-05 Uroš Bizjak <ubizjak@gmail.com>
12341 * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove.
12342 (*pushdi2_rex64 peephole2): Unconditionally split after
12343 epilogue_completed.
12344 (*ashl<mode>3_doubleword): Ditto.
12345 (*<shift_insn><mode>3_doubleword): Ditto.
12347 2020-02-05 Michael Meissner <meissner@linux.ibm.com>
12350 * config/rs6000/rs6000.c (get_vector_offset): Fix
12352 2020-02-05 Andrew Stubbs <ams@codesourcery.com>
12354 * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space.
12356 2020-02-05 David Malcolm <dmalcolm@redhat.com>
12358 * doc/analyzer.texi
12359 (Special Functions for Debugging the Analyzer): Update description
12360 of __analyzer_dump_exploded_nodes.
12362 2020-02-05 Jakub Jelinek <jakub@redhat.com>
12365 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only
12366 include sets and not clobbers in the vzeroupper pattern.
12367 * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that
12368 the parallel has 17 (64-bit) or 9 (32-bit) elts.
12369 (*avx_vzeroupper_1): New define_insn_and_split.
12372 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets,
12373 don't run when !optimize.
12374 (pass_split_before_regstack::gate): For STACK_REGS targets, run even
12377 2020-02-05 Richard Biener <rguenther@suse.de>
12379 PR middle-end/90648
12380 * genmatch.c (dt_node::gen_kids_1): Emit number of argument
12381 checks before matching calls.
12383 2020-02-05 Jakub Jelinek <jakub@redhat.com>
12385 * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up
12386 function comment typo.
12388 PR middle-end/93555
12389 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or
12390 simd_clone_create failed when i == 0, adjust clone->nargs by
12393 2020-02-05 Martin Liska <mliska@suse.cz>
12396 * doc/invoke.texi: Document that one should
12397 not combine ASLR and -fpch.
12399 2020-02-04 Richard Biener <rguenther@suse.de>
12401 PR tree-optimization/93538
12402 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr.
12404 2020-02-04 Richard Biener <rguenther@suse.de>
12406 PR tree-optimization/91123
12407 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method.
12408 (vn_walk_cb_data::last_vuse): New member.
12409 (vn_walk_cb_data::saved_operands): Likewsie.
12410 (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands.
12411 (vn_walk_cb_data::push_partial_def): Use finish.
12412 (vn_reference_lookup_2): Update last_vuse and use finish if
12413 we've saved operands.
12414 (vn_reference_lookup_3): Use finish and update calls to
12415 push_partial_defs everywhere. When translating through
12416 memcpy or aggregate copies save off operands and alias-set.
12417 (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE
12418 operation for redundant store removal.
12420 2020-02-04 Richard Biener <rguenther@suse.de>
12422 PR tree-optimization/92819
12423 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid
12424 generating more stmts than before.
12426 2020-02-04 Martin Liska <mliska@suse.cz>
12428 * config/arm/arm.c (arm_gen_far_branch): Move the function
12429 outside of selftests.
12431 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
12433 * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper
12434 function to adjust PC-relative vector addresses.
12435 (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to
12436 handle vectors with PC-relative addresses.
12438 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
12440 * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
12442 (hard_reg_and_mode_to_addr_mask): Delete.
12443 (rs6000_adjust_vec_address): If the original vector address
12444 was REG+REG or REG+OFFSET and the element is not zero, do the add
12445 of the elements in the original address before adding the offset
12446 for the vector element. Use address_to_insn_form to validate the
12447 address using the register being loaded, rather than guessing
12448 whether the address is a DS-FORM or DQ-FORM address.
12450 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
12452 * config/rs6000/rs6000.c (get_vector_offset): New helper function
12453 to calculate the offset in memory from the start of a vector of a
12454 particular element. Add code to keep the element number in
12455 bounds if the element number is variable.
12456 (rs6000_adjust_vec_address): Move calculation of offset of the
12457 vector element to get_vector_offset.
12458 (rs6000_split_vec_extract_var): Do not do the initial AND of
12459 element here, move the code to get_vector_offset.
12461 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
12463 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
12466 2020-02-03 Segher Boessenkool <segher@kernel.crashing.org>
12468 * config/rs6000/constraints.md: Improve documentation.
12470 2020-02-03 Richard Earnshaw <rearnsha@arm.com>
12473 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md)
12474 ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change.
12476 2020-02-03 Andrew Stubbs <ams@codesourcery.com>
12478 * config.gcc: Remove "carrizo" support.
12479 * config/gcn/gcn-opts.h (processor_type): Likewise.
12480 * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise.
12481 * config/gcn/gcn.opt (gpu_type): Likewise.
12482 * config/gcn/t-omp-device: Likewise.
12484 2020-02-03 Stam Markianos-Wright <stam.markianos-wright@arm.com>
12487 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
12488 * config/arm/arm.c (arm_gen_far_branch): New function
12489 arm_gen_far_branch.
12490 * config/arm/arm.md: Update b<cond> for Thumb2 range checks.
12492 2020-02-03 Julian Brown <julian@codesourcery.com>
12493 Tobias Burnus <tobias@codesourcery.com>
12495 * doc/invoke.texi: Update mention of OpenACC version to 2.6.
12497 2020-02-03 Jakub Jelinek <jakub@redhat.com>
12500 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit
12501 valid RTL to sum up the lowest and second lowest bytes of the popcnt
12504 2020-02-02 Vladimir Makarov <vmakarov@redhat.com>
12506 PR rtl-optimization/91333
12507 * ira-color.c (struct allocno_color_data): Add member
12509 (init_allocno_threads): Set the member up.
12510 (bucket_allocno_compare_func): Add compare hard reg
12513 2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
12515 nios2: Support for GOT-relative DW_EH_PE_datarel encoding.
12517 * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION.
12518 * config.in: Regenerated.
12519 * configure: Regenerated.
12520 * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling
12521 for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION.
12522 (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New.
12524 2020-02-01 Andrew Burgess <andrew.burgess@embecosm.com>
12526 * configure: Regenerate.
12528 2020-01-31 Vladimir Makarov <vmakarov@redhat.com>
12530 PR rtl-optimization/91333
12531 * ira-color.c (bucket_allocno_compare_func): Move conflict hard
12532 reg preferences comparison up.
12534 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
12536 * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro.
12537 * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to
12538 aarch64-sve-builtins-base.h.
12539 * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to
12540 aarch64-sve-builtins-base.cc.
12541 * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane)
12542 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
12543 (svcvtnt): Declare.
12544 * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane)
12545 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
12546 (svcvtnt): New functions.
12547 * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane)
12548 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
12549 (svcvtnt): New functions.
12550 (svcvt): Add a form that converts f32 to bf16.
12551 * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat)
12552 (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n):
12554 * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type):
12555 Treat B as bfloat16_t.
12556 (ternary_bfloat_lane_base): New class.
12557 (ternary_bfloat_def): Likewise.
12558 (ternary_bfloat): New shape.
12559 (ternary_bfloat_lane_def): New class.
12560 (ternary_bfloat_lane): New shape.
12561 (ternary_bfloat_lanex2_def): New class.
12562 (ternary_bfloat_lanex2): New shape.
12563 (ternary_bfloat_opt_n_def): New class.
12564 (ternary_bfloat_opt_n): New shape.
12565 * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro.
12566 * config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf)
12567 (@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns.
12568 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
12569 (@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
12570 (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
12571 (@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise.
12572 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key
12573 the pattern off the narrow mode instead of the wider one.
12574 * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator.
12575 (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs.
12576 (sve_fp_op): Handle them.
12577 (SVE_BFLOAT_TERNARY_LONG): New int itertor.
12578 (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
12580 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
12582 * config/aarch64/arm_sve.h: Include arm_bf16.h.
12583 * config/aarch64/aarch64-modes.def (BF): Move definition before
12584 VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF.
12585 (SVE_MODES): Handle BF modes.
12586 * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
12588 (aarch64_full_sve_mode): Likewise.
12589 * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF
12591 (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF.
12592 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore)
12593 (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count)
12594 (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the
12596 * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New
12598 * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro.
12599 (TYPES_all_data): Add bf16.
12600 (TYPES_reinterpret1, TYPES_reinterpret): Likewise.
12601 (register_tuple_type): Increase buffer size.
12602 * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type.
12603 (bf16): New type suffix.
12604 * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv)
12605 (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax)
12606 (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr):
12607 Change type from all_data to all_arith.
12608 * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp)
12609 (svminp): Likewise.
12611 2020-01-31 Dennis Zhang <dennis.zhang@arm.com>
12612 Matthew Malcomson <matthew.malcomson@arm.com>
12613 Richard Sandiford <richard.sandiford@arm.com>
12615 * doc/invoke.texi (f32mm): Document new AArch64 -march= extension.
12616 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
12617 __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and
12618 __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define
12619 __ARM_FEATURE_MATMUL_FP64.
12620 * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16)
12621 (sve): Add AARCH64_FL_F32MM to the list of extensions that should
12622 be disabled at the same time.
12623 (f32mm): New extension.
12624 * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro.
12625 (AARCH64_FL_F64MM): Bump to the next bit up.
12626 (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM)
12627 (TARGET_SVE_F64MM): New macros.
12628 * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator.
12629 (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL)
12630 (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q)
12631 (UNSPEC_ZIP2Q): New unspeccs.
12632 (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators.
12633 (optab, sur, perm_insn): Handle the new unspecs.
12634 (sve_fp_op): Handle UNSPEC_FMMLA. Resort.
12635 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
12636 TARGET_SVE_F64MM instead of separate tests.
12637 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern.
12638 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise.
12639 (@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise.
12640 (@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise.
12641 (@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise.
12642 * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro.
12643 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it.
12644 (TYPES_s_signed): New macro.
12645 (TYPES_s_integer): Use it.
12646 (TYPES_d_float): New macro.
12647 (TYPES_d_data): Use it.
12648 * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare.
12649 (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq)
12650 (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise.
12651 * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class.
12652 (svmmla): New shape.
12653 (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3
12654 template parameters.
12655 (ternary_resize2_lane_base): Likewise.
12656 (ternary_resize2_base): New class.
12657 (ternary_qq_lane_base): Likewise.
12658 (ternary_intq_uintq_lane_def): Likewise.
12659 (ternary_intq_uintq_lane): New shape.
12660 (ternary_intq_uintq_opt_n_def): New class
12661 (ternary_intq_uintq_opt_n): New shape.
12662 (ternary_qq_lane_def): Inherit from ternary_qq_lane_base.
12663 (ternary_uintq_intq_def): New class.
12664 (ternary_uintq_intq): New shape.
12665 (ternary_uintq_intq_lane_def): New class.
12666 (ternary_uintq_intq_lane): New shape.
12667 (ternary_uintq_intq_opt_n_def): New class.
12668 (ternary_uintq_intq_opt_n): New shape.
12669 * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot)
12670 (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla)
12671 (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare.
12672 * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl):
12674 (svdotprod_lane_impl): ...this new class.
12675 (svmmla_impl, svusdot_impl): New classes.
12676 (svdot_lane): Update to use svdotprod_lane_impl.
12677 (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot)
12678 (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New
12680 * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base
12681 function, with no types defined.
12682 (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New
12683 AARCH64_FL_I8MM functions.
12684 (svmmla): New AARCH64_FL_F32MM function.
12685 (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6.
12686 (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New
12687 AARCH64_FL_F64MM function.
12688 (REQUIRED_EXTENSIONS):
12690 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
12692 * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each
12695 2020-01-31 Uroš Bizjak <ubizjak@gmail.com>
12697 * config/i386/i386.md (*movoi_internal_avx): Do not check for
12698 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling.
12699 (*movti_internal): Do not check for
12700 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
12701 (*movtf_internal): Move check for TARGET_SSE2 and size optimization
12702 just after check for TARGET_AVX.
12703 (*movdf_internal): Ditto.
12704 * config/i386/mmx.md (*mov<mode>_internal): Do not check for
12705 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
12706 * config/i386/sse.md (mov<mode>_internal): Only check
12707 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check
12708 for TARGET_SSE2 and size optimization just after check for TARGET_AVX.
12709 (<sse>_andnot<mode>3<mask_name>): Move check for
12710 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX.
12711 (<code><mode>3<mask_name>): Ditto.
12712 (*andnot<mode>3): Ditto.
12713 (*andnottf3): Ditto.
12714 (*<code><mode>3): Ditto.
12715 (*<code>tf3): Ditto.
12716 (*andnot<VI:mode>3): Remove
12717 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling.
12718 (<mask_codefor><code><VI48_AVX_AVX512F:mode>3<mask_name>): Ditto.
12719 (*<code><VI12_AVX_AVX512F:mode>3): Ditto.
12720 (sse4_1_blendv<ssemodesuffix>): Ditto.
12721 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL):
12722 Explain that tune applies to 128bit instructions only.
12724 2020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com>
12726 * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count
12727 to definition of hsa_kernel_description. Parse assembly to find SGPR
12728 and VGPR count of kernel and store in hsa_kernel_description.
12730 2020-01-31 Tamar Christina <tamar.christina@arm.com>
12732 PR rtl-optimization/91838
12733 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case
12734 to truncate if allowed or reject combination.
12736 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
12738 * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step.
12739 (find_inv_vars_cb): Likewise.
12741 2020-01-31 David Malcolm <dmalcolm@redhat.com>
12743 * calls.c (special_function_p): Split out the check for DECL_NAME
12744 being non-NULL and fndecl being extern at file scope into a
12745 new maybe_special_function_p and call it. Drop check for fndecl
12746 being non-NULL that was after a usage of DECL_NAME (fndecl).
12747 * tree.h (maybe_special_function_p): New inline function.
12749 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
12751 * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ...
12752 (mask_gather_load<mode>): ... here, and zero-initialize the
12754 (maskload<mode>di): Zero-initialize the destination.
12755 * config/gcn/gcn.c:
12757 2020-01-30 David Malcolm <dmalcolm@redhat.com>
12760 * doc/analyzer.texi (Limitations): Note that constraints on
12761 floating-point values are currently ignored.
12763 2020-01-30 Jakub Jelinek <jakub@redhat.com>
12766 * symtab.c (symtab_node::noninterposable_alias): If localalias
12767 already exists, but is not usable, append numbers after it until
12768 a unique name is found. Formatting fix.
12770 PR middle-end/93505
12771 * combine.c (simplify_comparison) <case ROTATE>: Punt on out of range
12774 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
12776 * config/gcn/gcn.c (print_operand): Handle LTGT.
12777 * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt.
12779 2020-01-30 Richard Biener <rguenther@suse.de>
12781 * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST
12782 and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE.
12784 2020-01-30 John David Anglin <danglin@gcc.gnu.org>
12786 * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers
12787 without a DECL in .data.rel.ro.local.
12789 2020-01-30 Jakub Jelinek <jakub@redhat.com>
12792 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4
12796 * config/i386/sse.md
12797 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ...
12798 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use
12799 any_extend code iterator instead of always zero_extend.
12800 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ...
12801 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this.
12802 Use any_extend code iterator instead of always zero_extend.
12803 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ...
12804 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this.
12805 Use any_extend code iterator instead of always zero_extend.
12806 (*sse2_pmovmskb_ext): New define_insn.
12807 (*sse2_pmovmskb_ext_lt): New define_insn_and_split.
12810 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split.
12811 (*popcountsi2_zext_falsedep): New define_insn.
12813 2020-01-30 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
12815 * config.in: Regenerated.
12816 * configure: Regenerated.
12818 2020-01-29 Tobias Burnus <tobias@codesourcery.com>
12821 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as
12822 LLVM's assembler changed the default in version 9.
12824 2020-01-24 Jeff Law <law@redhat.com>
12826 PR tree-optimization/89689
12827 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure.
12829 2020-01-29 Richard Sandiford <richard.sandiford@arm.com>
12833 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
12835 PR rtl-optimization/87763
12836 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
12837 simplification to handle subregs as well as bare regs.
12838 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
12840 2020-01-29 Joel Hutton <Joel.Hutton@arm.com>
12843 * ira.c (ira): Revert use of simplified LRA algorithm.
12845 2020-01-29 Martin Jambor <mjambor@suse.cz>
12847 PR tree-optimization/92706
12848 * tree-sra.c (struct access): Fields first_link, last_link,
12849 next_queued and grp_queued renamed to first_rhs_link, last_rhs_link,
12850 next_rhs_queued and grp_rhs_queued respectively, new fields
12851 first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued.
12852 (struct assign_link): Field next renamed to next_rhs, new field
12853 next_lhs. Updated comment.
12854 (work_queue_head): Renamed to rhs_work_queue_head.
12855 (lhs_work_queue_head): New variable.
12856 (add_link_to_lhs): New function.
12857 (relink_to_new_repr): Also relink LHS lists.
12858 (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue.
12859 (add_access_to_lhs_work_queue): New function.
12860 (pop_access_from_work_queue): Renamed to
12861 pop_access_from_rhs_work_queue.
12862 (pop_access_from_lhs_work_queue): New function.
12863 (build_accesses_from_assign): Also add links to LHS lists and to LHS
12865 (child_would_conflict_in_lacc): Renamed to
12866 child_would_conflict_in_acc. Adjusted parameter names.
12867 (create_artificial_child_access): New parameter set_grp_read, use it.
12868 (subtree_mark_written_and_enqueue): Renamed to
12869 subtree_mark_written_and_rhs_enqueue.
12870 (propagate_subaccesses_across_link): Renamed to
12871 propagate_subaccesses_from_rhs.
12872 (propagate_subaccesses_from_lhs): New function.
12873 (propagate_all_subaccesses): Also propagate subaccesses from LHSs to
12876 2020-01-29 Martin Jambor <mjambor@suse.cz>
12878 PR tree-optimization/92706
12879 * tree-sra.c (struct access): Adjust comment of
12880 grp_total_scalarization.
12881 (find_access_in_subtree): Look for single children spanning an entire
12883 (scalarizable_type_p): Allow register accesses, adjust callers.
12884 (completely_scalarize): Remove function.
12885 (scalarize_elem): Likewise.
12886 (create_total_scalarization_access): Likewise.
12887 (sort_and_splice_var_accesses): Do not track total scalarization
12889 (analyze_access_subtree): New parameter totally, adjust to new meaning
12890 of grp_total_scalarization.
12891 (analyze_access_trees): Pass new parameter to analyze_access_subtree.
12892 (can_totally_scalarize_forest_p): New function.
12893 (create_total_scalarization_access): Likewise.
12894 (create_total_access_and_reshape): Likewise.
12895 (total_should_skip_creating_access): Likewise.
12896 (totally_scalarize_subtree): Likewise.
12897 (analyze_all_variable_accesses): Perform total scalarization after
12898 subaccess propagation using the new functions above.
12899 (initialize_constant_pool_replacements): Output initializers by
12900 traversing the access tree.
12902 2020-01-29 Martin Jambor <mjambor@suse.cz>
12904 * tree-sra.c (verify_sra_access_forest): New function.
12905 (verify_all_sra_access_forests): Likewise.
12906 (create_artificial_child_access): Set parent.
12907 (analyze_all_variable_accesses): Call the verifier.
12909 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12911 * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge
12912 if called on indirect edge.
12913 (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of
12914 speculative call if needed.
12916 2020-01-29 Richard Biener <rguenther@suse.de>
12918 PR tree-optimization/93428
12919 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load
12920 permutation when the load node is created.
12921 (vect_analyze_slp_instance): Re-use it here.
12923 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12925 * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning.
12927 2020-01-28 Vladimir Makarov <vmakarov@redhat.com>
12929 PR rtl-optimization/93272
12930 * ira-lives.c (process_out_of_region_eh_regs): New function.
12931 (process_bb_node_lives): Call it.
12933 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12935 * coverage.c (read_counts_file): Make error message lowercase.
12937 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12939 * profile-count.c (profile_quality_display_names): Fix ordering.
12941 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12944 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site
12945 hash only when edge is first within the sequence.
12946 (cgraph_edge::set_call_stmt): Update handling of speculative calls.
12947 (symbol_table::create_edge): Do not set target_prob.
12948 (cgraph_edge::remove_caller): Watch for speculative calls when updating
12949 the call site hash.
12950 (cgraph_edge::make_speculative): Drop target_prob parameter.
12951 (cgraph_edge::speculative_call_info): Remove.
12952 (cgraph_edge::first_speculative_call_target): New member function.
12953 (update_call_stmt_hash_for_removing_direct_edge): New function.
12954 (cgraph_edge::resolve_speculation): Rewrite to new API.
12955 (cgraph_edge::speculative_call_for_target): New member function.
12956 (cgraph_edge::make_direct): Rewrite to new API; fix handling of
12957 multiple speculation targets.
12958 (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating
12960 (verify_speculative_call): Verify that targets form an interval.
12961 * cgraph.h (cgraph_edge::speculative_call_info): Remove.
12962 (cgraph_edge::first_speculative_call_target): New member function.
12963 (cgraph_edge::next_speculative_call_target): New member function.
12964 (cgraph_edge::speculative_call_target_ref): New member function.
12965 (cgraph_edge;:speculative_call_indirect_edge): New member funtion.
12966 (cgraph_edge): Remove target_prob.
12967 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
12968 Fix handling of speculative calls.
12969 * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals.
12970 * ipa-fnsummary.c (analyze_function_body): Likewise.
12971 * ipa-inline.c (speculation_useful_p): Use new speculative call API.
12972 * ipa-profile.c (dump_histogram): Fix formating.
12973 (ipa_profile_generate_summary): Watch for overflows.
12974 (ipa_profile): Do not require probablity to be 1/2; update to new API.
12975 * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API.
12976 (update_indirect_edges_after_inlining): Update to new API.
12977 * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call
12979 * profile-count.h: (profile_probability::adjusted): New.
12980 * tree-inline.c (copy_bb): Update to new speculative call API; fix
12981 updating of profile.
12982 * value-prof.c (gimple_ic_transform): Rename to ...
12983 (dump_ic_profile): ... this one; update dumping.
12984 (stream_in_histogram_value): Fix formating.
12985 (gimple_value_profile_transformations): Update.
12987 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
12990 * config/i386/i386.md (*movoi_internal_avx): Remove
12991 TARGET_SSE_TYPELESS_STORES check.
12992 (*movti_internal): Prefer TARGET_AVX over
12993 TARGET_SSE_TYPELESS_STORES.
12994 (*movtf_internal): Likewise.
12995 * config/i386/sse.md (mov<mode>_internal): Prefer TARGET_AVX over
12996 TARGET_SSE_TYPELESS_STORES. Remove "<MODE_SIZE> == 16" check
12997 from TARGET_SSE_TYPELESS_STORES.
12999 2020-01-28 David Malcolm <dmalcolm@redhat.com>
13001 * diagnostic-core.h (warning_at): Rename overload to...
13002 (warning_meta): ...this.
13003 (emit_diagnostic_valist): Delete decl of overload taking
13004 diagnostic_metadata.
13005 * diagnostic.c (emit_diagnostic_valist): Likewise for defn.
13006 (warning_at): Rename overload taking diagnostic_metadata to...
13007 (warning_meta): ...this.
13009 2020-01-28 Richard Biener <rguenther@suse.de>
13011 PR tree-optimization/93439
13012 * tree-parloops.c (create_loop_fn): Move clique bookkeeping...
13013 * tree-cfg.c (move_sese_region_to_fn): ... here.
13014 (verify_types_in_gimple_reference): Verify used cliques are
13017 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
13020 * config/i386/i386-options.c (set_ix86_tune_features): Add an
13021 argument of a pointer to struct gcc_options and pass it to
13022 parse_mtune_ctrl_str.
13023 (ix86_function_specific_restore): Pass opts to
13024 set_ix86_tune_features.
13025 (ix86_option_override_internal): Likewise.
13026 (parse_mtune_ctrl_str): Add an argument of a pointer to struct
13027 gcc_options and use it for x_ix86_tune_ctrl_string.
13029 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
13031 PR rtl-optimization/87763
13032 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
13033 simplification to handle subregs as well as bare regs.
13034 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
13036 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
13038 * tree-vect-loop.c (vectorizable_reduction): Fail gracefully
13039 for reduction chains that (now) include a call.
13041 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
13043 PR tree-optimization/92822
13044 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling
13045 out the don't-care elements of a vector whose significant elements
13046 are duplicates, make the don't-care elements duplicates too.
13048 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
13050 PR tree-optimization/93434
13051 * tree-predcom.c (split_data_refs_to_components): Record which
13052 components have had aliasing loads removed. Prevent store-store
13053 commoning for all such components.
13055 2020-01-28 Jakub Jelinek <jakub@redhat.com>
13058 * config/i386/i386.c (ix86_fold_builtin) <do_shift>: If mask is not
13059 -1 or is_vshift is true, use new_vector with number of elts npatterns
13060 rather than new_unary_operation.
13062 PR tree-optimization/93454
13063 * gimple-fold.c (fold_array_ctor_reference): Perform
13064 elt_size.to_uhwi () just once, instead of calling it in every
13065 iteration. Punt if that value is above size of the temporary
13066 buffer. Decrease third native_encode_expr argument when
13067 bufoff + elt_sz is above size of buf.
13069 2020-01-27 Joseph Myers <joseph@codesourcery.com>
13071 * config/mips/mips.c (mips_declare_object_name)
13072 [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object.
13074 2020-01-27 Martin Liska <mliska@suse.cz>
13076 PR gcov-profile/93403
13077 * tree-profile.c (gimple_init_gcov_profiler): Generate
13078 both __gcov_indirect_call_profiler_v4 and
13079 __gcov_indirect_call_profiler_v4_atomic.
13081 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
13084 * config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
13086 (@aarch64_split_simd_mov<mode>): Use it.
13087 (aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
13088 Leave the vec_extract patterns to handle 2-element vectors.
13089 (aarch64_simd_mov_from_<mode>high): Likewise.
13090 (vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
13091 (vec_extractv2dfv1df): Likewise.
13093 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
13095 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match
13096 jump conditions for *compare_condjump<GPI:mode>.
13098 2020-01-27 David Malcolm <dmalcolm@redhat.com>
13101 * digraph.cc (test_edge::test_edge): Specify template for base
13104 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
13106 * config/arc/arc.c (arc_rtx_costs): Update mul64 cost.
13108 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
13110 * config/arc/arc-protos.h (gen_mlo): Remove.
13111 (gen_mhi): Likewise.
13112 * config/arc/arc.c (AUX_MULHI): Define.
13113 (arc_must_save_reister): Special handling for r58/59.
13114 (arc_compute_frame_size): Consider mlo/mhi registers.
13115 (arc_save_callee_saves): Emit fp/sp move only when emit_move
13117 (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from
13118 mlo/mhi name selection.
13119 (arc_restore_callee_saves): Don't early restore blink when ISR.
13120 (arc_expand_prologue): Add mlo/mhi saving.
13121 (arc_expand_epilogue): Add mlo/mhi restoring.
13124 * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register
13125 numbering when MUL64 option is used.
13126 (DWARF2_FRAME_REG_OUT): Define.
13127 * config/arc/arc.md (arc600_stall): New pattern.
13128 (VUNSPEC_ARC_ARC600_STALL): Define.
13129 (mulsi64): Use correct mlo/mhi registers.
13130 (mulsi_600): Clean it up.
13131 * config/arc/predicates.md (mlo_operand): Remove any dependency on
13133 (mhi_operand): Likewise.
13135 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
13136 Petro Karashchenko <petro.karashchenko@ring.com>
13138 * config/arc/arc.c (arc_is_uncached_mem_p): Check struct
13139 attributes if needed.
13140 (prepare_move_operands): Generate special unspec instruction for
13142 (arc_isuncached_mem_p): Propagate uncached attribute to each
13144 * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define.
13145 (VUNSPEC_ARC_STDI): Likewise.
13146 (ALLI): New mode iterator.
13147 (mALLI): New mode attribute.
13148 (lddi): New instruction pattern.
13150 (stdidi_split): Split instruction for architectures which are not
13151 supporting ll64 option.
13152 (lddidi_split): Likewise.
13154 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
13156 PR rtl-optimization/92989
13157 * lra-lives.c (process_bb_lives): Update the live-in set before
13158 processing additional clobbers.
13160 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
13162 PR rtl-optimization/93170
13163 * cselib.c (cselib_invalidate_regno_val): New function, split out
13165 (cselib_invalidate_regno): ...here.
13166 (cselib_invalidated_by_call_p): New function.
13167 (cselib_process_insn): Iterate over all the hard-register entries in
13168 REG_VALUES and invalidate any that cross call-clobbered registers.
13170 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
13172 * dojump.c (split_comparison): Use HONOR_NANS rather than
13173 HONOR_SNANS when splitting LTGT.
13175 2020-01-27 Martin Liska <mliska@suse.cz>
13178 * opts.c (print_filtered_help): Exclude language-specific
13179 options from --help=common unless enabled in all FEs.
13181 2020-01-27 Martin Liska <mliska@suse.cz>
13183 * opts.c (print_help): Exclude params from
13184 all except --help=param.
13186 2020-01-27 Martin Liska <mliska@suse.cz>
13189 * config/i386/i386-features.c (make_resolver_func):
13190 Align the code with ppc64 target implementation.
13191 Do not generate a unique name for resolver function.
13193 2020-01-27 Richard Biener <rguenther@suse.de>
13195 PR tree-optimization/93397
13196 * tree-vect-slp.c (vect_analyze_slp_instance): Delay
13197 converted reduction chain SLP graph adjustment.
13199 2020-01-26 Marek Polacek <polacek@redhat.com>
13202 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on
13205 2020-01-26 Jason Merrill <jason@redhat.com>
13208 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING
13211 2020-01-26 Darius Galis <darius.galis@cyberthorstudios.com>
13213 * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint
13214 (rx_setmem): Likewise.
13216 2020-01-26 Jakub Jelinek <jakub@redhat.com>
13219 * config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword):
13220 Use nonimmediate_operand instead of x86_64_hilo_general_operand and
13221 drop <di> from constraint of last operand.
13224 * config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for
13225 TARGET_AVX2 and V4DFmode not in the split condition, but in the
13226 pattern condition, though allow { 0, 0, 0, 0 } broadcast always.
13228 2020-01-25 Feng Xue <fxue@os.amperecomputing.com>
13231 * ipa-cp.c (get_info_about_necessary_edges): Remove value
13234 2020-01-24 Jeff Law <law@redhat.com>
13236 PR tree-optimization/92788
13237 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX
13240 2020-01-24 Jakub Jelinek <jakub@redhat.com>
13243 * config/i386/sse.md (*avx_vperm_broadcast_v4sf,
13244 *avx_vperm_broadcast_<mode>,
13245 <sse2_avx_avx512f>_vpermil<mode><mask_name>,
13246 *<sse2_avx_avx512f>_vpermilp<mode><mask_name>):
13247 Move before avx2_perm<mode>/avx512f_perm<mode>.
13250 * simplify-rtx.c (simplify_const_unary_operation,
13251 simplify_const_binary_operation): Punt for mode precision above
13252 MAX_BITSIZE_MODE_ANY_INT.
13254 2020-01-24 Andrew Pinski <apinski@marvell.com>
13256 * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change
13257 alu.shift_reg to 0.
13259 2020-01-24 Jeff Law <law@redhat.com>
13262 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg
13263 for REGs. Call output_operand_lossage to get more reasonable
13266 2020-01-24 Andrew Stubbs <ams@codesourcery.com>
13268 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use
13269 gcn_fp_compare_operator.
13270 (vec_cmpu<mode>di): Use gcn_compare_operator.
13271 (vec_cmp<u>v64qidi): Use gcn_compare_operator.
13272 (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator.
13273 (vec_cmpu<mode>di_exec): Use gcn_compare_operator.
13274 (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator.
13275 (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator.
13276 (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator.
13277 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use
13278 gcn_fp_compare_operator.
13279 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use
13280 gcn_fp_compare_operator.
13281 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use
13282 gcn_fp_compare_operator.
13283 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use
13284 gcn_fp_compare_operator.
13286 2020-01-24 Maciej W. Rozycki <macro@wdc.com>
13288 * doc/install.texi (Cross-Compiler-Specific Options): Document
13289 `--with-toolexeclibdir' option.
13291 2020-01-24 Hans-Peter Nilsson <hp@axis.com>
13293 * target.def (flags_regnum): Also mention effect on delay slot filling.
13294 * doc/tm.texi: Regenerate.
13296 2020-01-23 Jeff Law <law@redhat.com>
13298 PR translation/90162
13299 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text.
13301 2020-01-23 Mikael Tillenius <mti-1@tillenius.com>
13304 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of
13307 2020-01-23 Jakub Jelinek <jakub@redhat.com>
13309 PR rtl-optimization/93402
13310 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust
13313 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
13315 * config.in: Regenerated.
13316 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
13317 for TARGET_LIBC_GNUSTACK.
13318 * configure: Regenerated.
13319 * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
13320 found to be 2.31 or greater.
13322 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
13324 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
13326 * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
13327 (mips_asm_file_end): New function. Delegate to
13328 file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true.
13329 * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0.
13331 2020-01-23 Jakub Jelinek <jakub@redhat.com>
13334 * config/i386/i386-modes.def (POImode): New mode.
13335 (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160.
13336 * config/i386/i386.md (DPWI): New mode attribute.
13337 (addv<mode>4, subv<mode>4): Use <DPWI> instead of <DWI>.
13338 (QWI): Rename to...
13339 (QPWI): ... this. Use POI instead of OI for TImode.
13340 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1,
13341 *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1): Use <QPWI>
13344 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
13347 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New
13349 (speculation_tracker_rev): New pattern.
13350 * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation):
13351 Use speculation_tracker_rev to track the inverse condition.
13353 2020-01-23 Richard Biener <rguenther@suse.de>
13355 PR tree-optimization/93381
13356 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take
13357 alias-set of the def as argument and record the first one.
13358 (vn_walk_cb_data::first_set): New member.
13359 (vn_reference_lookup_3): Pass the alias-set of the current def
13360 to push_partial_def. Fix alias-set used in the aggregate copy
13362 (vn_reference_lookup): Consistently set *last_vuse_ptr.
13363 * real.c (clear_significand_below): Fix out-of-bound access.
13365 2020-01-23 Jakub Jelinek <jakub@redhat.com>
13368 * config/i386/i386.md (*bmi2_bzhi_<mode>3_2, *bmi2_bzhi_<mode>3_3):
13369 New define_insn patterns.
13371 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
13373 * doc/sourcebuild.texi (check-function-bodies): Add an
13374 optional target/xfail selector.
13376 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
13378 PR rtl-optimization/93124
13379 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to
13380 bare USE and CLOBBER insns.
13382 2020-01-22 Andrew Pinski <apinski@marvell.com>
13384 * config/arc/arc.c (output_short_suffix): Check insn for nullness.
13386 2020-01-22 David Malcolm <dmalcolm@redhat.com>
13389 * gdbinit.in (break-on-saved-diagnostic): Update for move of
13390 diagnostic_manager into "ana" namespace.
13391 * selftest-run-tests.c (selftest::run_tests): Update for move of
13392 selftest::run_analyzer_selftests to
13393 ana::selftest::run_analyzer_selftests.
13395 2020-01-22 Richard Sandiford <richard.sandiford@arm.com>
13397 * cfgexpand.c (union_stack_vars): Update the size.
13399 2020-01-22 Richard Biener <rguenther@suse.de>
13401 PR tree-optimization/93381
13402 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting
13403 throughout, handle all conversions the same.
13405 2020-01-22 Jakub Jelinek <jakub@redhat.com>
13408 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use
13409 gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate
13410 predicate, not whenever it is CONST_INT. Otherwise, force_reg it.
13411 Call force_reg on high_in2 unconditionally.
13413 2020-01-22 Martin Liska <mliska@suse.cz>
13415 PR tree-optimization/92924
13416 * profile.c (compute_value_histograms): Divide
13417 all counter values.
13419 2020-01-22 Jakub Jelinek <jakub@redhat.com>
13422 * output.h (assemble_name_resolve): Declare.
13423 * varasm.c (assemble_name_resolve): New function.
13424 (assemble_name): Use it.
13425 * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define.
13427 2020-01-22 Joseph Myers <joseph@codesourcery.com>
13429 * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to
13430 update_web_docs_git instead of update_web_docs_svn.
13432 2020-01-21 Andrew Pinski <apinski@marvell.com>
13435 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0
13436 as PTR mode. Have operand 1 as being modeless, it can be P mode.
13437 (*tlsgd_small_<mode>): Likewise.
13438 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately)
13439 <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode
13440 register. Convert that register back to dest using convert_mode.
13442 2020-01-21 Jim Wilson <jimw@sifive.com>
13444 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL
13447 2020-01-21 H.J. Lu <hongjiu.lu@intel.com>
13448 Uros Bizjak <ubizjak@gmail.com>
13451 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode
13453 (legitimize_tls_address): Do GNU2 TLS address computation in
13454 ptr_mode and zero-extend result to Pmode.
13455 * config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace
13456 :P with :PTR and Pmode with ptr_mode.
13457 (*tls_dynamic_gnu2_lea_64_<mode>): Likewise.
13458 (*tls_dynamic_gnu2_call_64_<mode>): Likewise.
13459 (*tls_dynamic_gnu2_combine_64_<mode>): Likewise.
13461 2020-01-21 Jakub Jelinek <jakub@redhat.com>
13464 * config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify
13465 the last two operands are CONST_INT_P before using them as such.
13467 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
13469 * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name
13470 to get the integer element types.
13472 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
13474 * config/aarch64/aarch64-sve-builtins.h
13475 (function_expander::convert_to_pmode): Declare.
13476 * config/aarch64/aarch64-sve-builtins.cc
13477 (function_expander::convert_to_pmode): New function.
13478 (function_expander::get_contiguous_base): Use it.
13479 (function_expander::prepare_gather_address_operands): Likewise.
13480 * config/aarch64/aarch64-sve-builtins-sve2.cc
13481 (svwhilerw_svwhilewr_impl::expand): Likewise.
13483 2020-01-21 Szabolcs Nagy <szabolcs.nagy@arm.com>
13486 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set
13487 cfun->machine->label_is_assembled.
13488 (aarch64_print_patchable_function_entry): New.
13489 (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define.
13490 * config/aarch64/aarch64.h (struct machine_function): New field,
13491 label_is_assembled.
13493 2020-01-21 David Malcolm <dmalcolm@redhat.com>
13496 * ipa-profile.c (ipa_profile): Delete call_sums and set it to
13499 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
13502 * cgraph.c (cgraph_edge::resolve_speculation,
13503 cgraph_edge::redirect_call_stmt_to_callee): Fix update of
13504 call_stmt_site_hash.
13506 2020-01-21 Martin Liska <mliska@suse.cz>
13508 * config/rs6000/rs6000.c (common_mode_defined): Remove
13511 2020-01-21 Richard Biener <rguenther@suse.de>
13513 PR tree-optimization/92328
13514 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve
13515 type when value-numbering same-sized store by inserting a
13517 (eliminate_dom_walker::eliminate_stmt): When eliminating
13518 a redundant store handle bit-reinterpretation of the same value.
13520 2020-01-21 Andrew Pinski <apinski@marvel.com>
13523 * tree-into-ssa.c (prepare_block_for_update_1): Split out
13525 (prepare_block_for_update): This. Use a worklist instead of
13528 2020-01-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13530 * gcc/config/arm/arm.c (clear_operation_p):
13531 Initialise last_regno, skip first iteration
13532 based on the first_set value and use ints instead
13533 of the unnecessary HOST_WIDE_INTs.
13535 2020-01-21 Jakub Jelinek <jakub@redhat.com>
13538 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for
13539 compare_mode other than SFmode or DFmode.
13541 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
13544 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
13545 * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
13546 * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
13548 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
13550 * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.
13552 2020-01-20 Andrew Pinski <apinski@marvell.com>
13554 PR middle-end/93242
13555 * targhooks.c (default_print_patchable_function_entry): Use
13556 output_asm_insn to emit the nop instruction.
13558 2020-01-20 Fangrui Song <maskray@google.com>
13560 PR middle-end/93194
13561 * targhooks.c (default_print_patchable_function_entry): Align to
13564 2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
13567 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to
13568 gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode.
13569 * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ...
13570 (@tls_dynamic_gnu2_64_<mode>): This. Replace DI with P.
13571 (*tls_dynamic_gnu2_lea_64): Renamed to ...
13572 (*tls_dynamic_gnu2_lea_64_<mode>): This. Replace DI with P.
13573 Remove the {q} suffix from lea.
13574 (*tls_dynamic_gnu2_call_64): Renamed to ...
13575 (*tls_dynamic_gnu2_call_64_<mode>): This. Replace DI with P.
13576 (*tls_dynamic_gnu2_combine_64): Renamed to ...
13577 (*tls_dynamic_gnu2_combine_64_<mode>): This. Replace DI with P.
13578 Pass Pmode to gen_tls_dynamic_gnu2_64.
13580 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
13582 * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1.
13584 2020-01-20 Richard Sandiford <richard.sandiford@arm.com>
13586 * config/aarch64/aarch64-sve-builtins-base.cc
13587 (svld1ro_impl::memory_vector_mode): Remove parameter name.
13589 2020-01-20 Richard Biener <rguenther@suse.de>
13592 * dwarf2out.c (prune_unused_types): Unconditionally mark
13593 called function DIEs.
13595 2020-01-20 Martin Liska <mliska@suse.cz>
13597 PR tree-optimization/93199
13598 * tree-eh.c (struct leh_state): Add
13599 new field outer_non_cleanup.
13600 (cleanup_is_dead_in): Pass leh_state instead
13601 of eh_region. Add a checking that state->outer_non_cleanup
13602 points to outer non-clean up region.
13603 (lower_try_finally): Record outer_non_cleanup
13605 (lower_catch): Likewise.
13606 (lower_eh_filter): Likewise.
13607 (lower_eh_must_not_throw): Likewise.
13608 (lower_cleanup): Likewise.
13610 2020-01-20 Richard Biener <rguenther@suse.de>
13612 PR tree-optimization/93094
13613 * tree-vectorizer.h (vect_loop_versioning): Adjust.
13614 (vect_transform_loop): Likewise.
13615 * tree-vectorizer.c (try_vectorize_loop_1): Pass down
13616 loop_vectorized_call to vect_transform_loop.
13617 * tree-vect-loop.c (vect_transform_loop): Pass down
13618 loop_vectorized_call to vect_loop_versioning.
13619 * tree-vect-loop-manip.c (vect_loop_versioning): Use
13620 the earlier discovered loop_vectorized_call.
13622 2020-01-19 Eric S. Raymond <esr@thyrsus.com>
13624 * doc/contribute.texi: Update for SVN -> Git transition.
13625 * doc/install.texi: Likewise.
13627 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
13630 * cgraph.c (cgraph_edge::make_speculative): Increase number of
13631 speculative targets.
13632 (verify_speculative_call): New function
13633 (cgraph_node::verify_node): Use it.
13634 * ipa-profile.c (ipa_profile): Fix formating; do not set number of
13637 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
13640 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting.
13641 (cgraph_edge::make_direct): Remove all indirect targets.
13642 (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct..
13643 (cgraph_node::verify_node): Verify that only one call_stmt or
13644 lto_stmt_uid is set.
13645 * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or
13647 * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt.
13648 (lto_output_ref): Simplify streaming of stmt.
13649 * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid.
13651 2020-01-18 Tamar Christina <tamar.christina@arm.com>
13653 * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode):
13654 Mark parameter unused.
13656 2020-01-18 Hans-Peter Nilsson <hp@axis.com>
13658 * config.gcc <obsolete targets>: Add crisv32-*-* and cris-*-linux*
13660 2019-01-18 Gerald Pfeifer <gerald@pfeifer.com>
13662 * varpool.c (ctor_useable_for_folding_p): Fix grammar.
13664 2020-01-18 Iain Sandoe <iain@sandoe.co.uk>
13666 * Makefile.in: Add coroutine-passes.o.
13667 * builtin-types.def (BT_CONST_SIZE): New.
13668 (BT_FN_BOOL_PTR): New.
13669 (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New.
13670 * builtins.def (DEF_COROUTINE_BUILTIN): New.
13671 * coroutine-builtins.def: New file.
13672 * coroutine-passes.cc: New file.
13673 * function.h (struct GTY function): Add a bit to indicate that the
13674 function is a coroutine component.
13675 * internal-fn.c (expand_CO_FRAME): New.
13676 (expand_CO_YIELD): New.
13677 (expand_CO_SUSPN): New.
13678 (expand_CO_ACTOR): New.
13679 * internal-fn.def (CO_ACTOR): New.
13683 * passes.def: Add pass_coroutine_lower_builtins,
13684 pass_coroutine_early_expand_ifns.
13685 * tree-pass.h (make_pass_coroutine_lower_builtins): New.
13686 (make_pass_coroutine_early_expand_ifns): New.
13687 * doc/invoke.texi: Document the fcoroutines command line
13690 2020-01-18 Jakub Jelinek <jakub@redhat.com>
13692 * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable.
13695 * config/arm/arm.c (clear_operation_p): Don't use REGNO until
13696 after checking the argument is a REG. Don't use REGNO (reg)
13697 again to set last_regno, reuse regno variable instead.
13699 2020-01-17 David Malcolm <dmalcolm@redhat.com>
13701 * doc/analyzer.texi (Limitations): Add note about NaN.
13703 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13704 Sudakshina Das <sudi.das@arm.com>
13706 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
13707 and valid immediate.
13708 (ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
13709 (lshrdi3): Generate thumb2_lsrl for valid immediates.
13710 * config/arm/constraints.md (Pg): New.
13711 * config/arm/predicates.md (long_shift_imm): New.
13712 (arm_reg_or_long_shift_imm): Likewise.
13713 * config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
13714 (thumb2_lsll): Likewise.
13715 (thumb2_lsrl): New.
13717 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13718 Sudakshina Das <sudi.das@arm.com>
13720 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
13721 (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
13722 * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
13723 register pairs for doubleword quantities for ARMv8.1M-Mainline.
13724 * config/arm/thumb2.md (thumb2_asrl): New.
13725 (thumb2_lsll): Likewise.
13727 2020-01-17 Jakub Jelinek <jakub@redhat.com>
13729 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove
13732 2020-01-17 Alexander Monakov <amonakov@ispras.ru>
13734 * gdbinit.in (help-gcc-hooks): New command.
13735 (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc,
13736 pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update
13739 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
13741 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the
13742 correct target macro.
13744 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
13746 * config/aarch64/aarch64-protos.h
13747 (aarch64_sve_ld1ro_operand_p): New.
13748 * config/aarch64/aarch64-sve-builtins-base.cc
13749 (class load_replicate): New.
13750 (class svld1ro_impl): New.
13751 (class svld1rq_impl): Change to inherit from load_replicate.
13752 (svld1ro): New sve intrinsic function base.
13753 * config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
13754 New DEF_SVE_FUNCTION.
13755 * config/aarch64/aarch64-sve-builtins-base.h
13756 (svld1ro): New decl.
13757 * config/aarch64/aarch64-sve-builtins.cc
13758 (function_expander::add_mem_operand): Modify assert to allow
13760 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
13762 * config/aarch64/aarch64.c
13763 (aarch64_sve_ld1rq_operand_p): Implement in terms of ...
13764 (aarch64_sve_ld1rq_ld1ro_operand_p): This.
13765 (aarch64_sve_ld1ro_operand_p): New.
13766 * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
13767 * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
13768 * config/aarch64/predicates.md
13769 (aarch64_sve_ld1ro_operand_{b,h,w,d}): New.
13771 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
13773 * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
13774 Introduce this ACLE specified predefined macro.
13775 * config/aarch64/aarch64-option-extensions.def (f64mm): New.
13776 (fp): Disabling this disables f64mm.
13777 (simd): Disabling this disables f64mm.
13778 (fp16): Disabling this disables f64mm.
13779 (sve): Disabling this disables f64mm.
13780 * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
13781 (AARCH64_ISA_F64MM): New.
13782 (TARGET_F64MM): New.
13783 * doc/invoke.texi (f64mm): Document new option.
13785 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
13787 * config/aarch64/aarch64.c (generic_tunings): Add branch fusion.
13788 (neoversen1_tunings): Likewise.
13790 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
13793 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
13794 Add assert to ensure prolog has been emitted.
13795 (aarch64_split_atomic_op): Likewise.
13796 * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
13797 Use epilogue_completed rather than reload_completed.
13798 (aarch64_atomic_exchange<mode>): Likewise.
13799 (aarch64_atomic_<atomic_optab><mode>): Likewise.
13800 (atomic_nand<mode>): Likewise.
13801 (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
13802 (atomic_fetch_nand<mode>): Likewise.
13803 (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
13804 (atomic_nand_fetch<mode>): Likewise.
13806 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
13809 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false
13811 (REVERSE_CONDITION): Delete.
13812 * config/aarch64/iterators.md (CC_ONLY): New mode iterator.
13813 (CCFP_CCFPE): Likewise.
13814 (e): New mode attribute.
13815 * config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to...
13816 (@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC.
13817 (fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into...
13818 (@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern.
13819 (@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern.
13820 (@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise.
13821 * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update
13822 name of generator from gen_ccmpdi to gen_ccmpccdi.
13823 (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse
13824 the previous comparison but aren't able to, use the new ccmp_rev
13827 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
13829 * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather
13830 than testing directly for INTEGER_CST.
13831 (gimplify_target_expr, gimplify_omp_depend): Likewise.
13833 2020-01-17 Jakub Jelinek <jakub@redhat.com>
13835 PR tree-optimization/93292
13836 * tree-vect-stmts.c (vectorizable_comparison): Punt also if
13837 get_vectype_for_scalar_type returns NULL.
13839 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
13841 * params.opt (-param=max-predicted-iterations): Increase range from 0.
13842 * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations.
13844 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
13846 * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of
13848 * params.opt: (max-predicted-iterations): Set bounds.
13849 * predict.c (real_almost_one, real_br_prob_base,
13850 real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove.
13851 (propagate_freq): Add max_cyclic_prob parameter; cap cyclic
13852 probabilities; do not truncate to reg_br_prob_bases.
13853 (estimate_loops_at_level): Pass max_cyclic_prob.
13854 (estimate_loops): Compute max_cyclic_prob.
13855 (estimate_bb_frequencies): Do not initialize real_*; update calculation
13857 * profile-count.c (profile_probability::to_sreal): New.
13858 * profile-count.h (class sreal): Move up in file.
13859 (profile_probability::to_sreal): Declare.
13861 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13864 (arm_invalid_conversion): New function for target hook.
13865 (arm_invalid_unary_op): New function for target hook.
13866 (arm_invalid_binary_op): New function for target hook.
13868 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13870 * config.gcc: Add arm_bf16.h.
13871 * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
13872 (arm_simd_builtin_std_type): Add BFmode.
13873 (arm_init_simd_builtin_types): Define element types for vector types.
13874 (arm_init_bf16_types): New function.
13875 (arm_init_builtins): Add arm_init_bf16_types function call.
13876 * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
13877 * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
13878 * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode.
13879 (arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
13880 (arm_vector_mode_supported_p): Add V4BF, V8BF.
13881 (arm_mangle_type): Add __bf16.
13882 * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
13883 VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
13884 arm_bf16_ptr_type_node.
13885 * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
13886 define_split between ARM registers.
13887 * config/arm/arm_bf16.h: New file.
13888 * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
13889 * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
13890 (VQXMOV): Add V8BF.
13891 * config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
13892 * config/arm/vfp.md: Add BFmode to movhf patterns.
13894 2020-01-16 Mihail Ionescu <mihail.ionescu@arm.com>
13895 Andre Vieira <andre.simoesdiasvieira@arm.com>
13897 * config/arm/arm-cpus.in (mve, mve_float): New features.
13898 (dsp, mve, mve.fp): New options.
13899 * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define.
13900 * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M.
13901 * doc/invoke.texi: Document the armv8.1-m mve and dps options.
13903 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13904 Thomas Preud'homme <thomas.preudhomme@arm.com>
13906 * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to
13908 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove
13909 error for using -mcmse when targeting Armv8.1-M Mainline.
13911 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13912 Thomas Preud'homme <thomas.preudhomme@arm.com>
13914 * config/arm/arm.md (nonsecure_call_internal): Do not force memory
13915 address in r4 when targeting Armv8.1-M Mainline.
13916 (nonsecure_call_value_internal): Likewise.
13917 * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address
13918 a register match_operand again. Emit BLXNS when targeting
13919 Armv8.1-M Mainline.
13920 (nonsecure_call_value_reg_thumb2): Likewise.
13922 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13923 Thomas Preud'homme <thomas.preudhomme@arm.com>
13925 * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early.
13926 (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear
13927 variable as true when floating-point ABI is not hard. Replace
13928 check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear.
13929 Generate VLSTM and VLLDM instruction respectively before and
13930 after a function call to cmse_nonsecure_call function.
13931 * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec.
13932 (VUNSPEC_VLLDM): Likewise.
13933 * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn.
13934 (lazy_load_multiple_insn): Likewise.
13936 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13937 Thomas Preud'homme <thomas.preudhomme@arm.com>
13939 * config/arm/arm.c (vfp_emit_fstmd): Declare early.
13940 (arm_emit_vfp_multi_reg_pop): Likewise.
13941 (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP
13942 registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and
13943 restore callee-saved VFP registers.
13945 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13946 Thomas Preud'homme <thomas.preudhomme@arm.com>
13948 * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early.
13949 (cmse_nonsecure_call_clear_caller_saved): Rename into ...
13950 (cmse_nonsecure_call_inline_register_clear): This. Save and clear
13951 callee-saved GPRs as well as clear ip register before doing a nonsecure
13952 call then restore callee-saved GPRs after it when targeting
13953 Armv8.1-M Mainline.
13954 (arm_reorg): Adapt to function rename.
13956 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13957 Thomas Preud'homme <thomas.preudhomme@arm.com>
13959 * config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
13960 * config/arm/arm.c (clear_operation_p): Extend to be able to check a
13961 clear_vfp_multiple pattern based on a new vfp parameter.
13962 (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
13963 targeting Armv8.1-M Mainline.
13964 (cmse_nonsecure_entry_clear_before_return): Clear VFP registers
13965 unconditionally when targeting Armv8.1-M Mainline architecture. Check
13966 whether VFP registers are available before looking call_used_regs for a
13968 * config/arm/predicates.md (clear_multiple_operation): Adapt to change
13969 of prototype of clear_operation_p.
13970 (clear_vfp_multiple_operation): New predicate.
13971 * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
13972 * config/arm/vfp.md (clear_vfp_multiple): New define_insn.
13974 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13975 Thomas Preud'homme <thomas.preudhomme@arm.com>
13977 * config/arm/arm-protos.h (clear_operation_p): Declare.
13978 * config/arm/arm.c (clear_operation_p): New function.
13979 (cmse_clear_registers): Generate clear_multiple instruction pattern if
13980 targeting Armv8.1-M Mainline or successor.
13981 (output_return_instruction): Only output APSR register clearing if
13982 Armv8.1-M Mainline instructions not available.
13983 (thumb_exit): Likewise.
13984 * config/arm/predicates.md (clear_multiple_operation): New predicate.
13985 * config/arm/thumb2.md (clear_apsr): New define_insn.
13986 (clear_multiple): Likewise.
13987 * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec.
13989 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13990 Thomas Preud'homme <thomas.preudhomme@arm.com>
13992 * config/arm/arm.c (fp_sysreg_names): Declare and define.
13993 (use_return_insn): Also return false for Armv8.1-M Mainline.
13994 (output_return_instruction): Skip FPSCR clearing if Armv8.1-M
13995 Mainline instructions are available.
13996 (arm_compute_frame_layout): Allocate space in frame for FPCXTNS
13997 when targeting Armv8.1-M Mainline Security Extensions.
13998 (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
13999 Mainline entry function.
14000 (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
14001 targeting Armv8.1-M Mainline or successor.
14002 (arm_expand_epilogue): Fix indentation of caller-saved register
14003 clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline
14005 * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
14006 (FP_SYSREGS): Likewise.
14007 (enum vfp_sysregs_encoding): Define enum.
14008 (fp_sysreg_names): Declare.
14009 * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
14010 * config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
14011 (pop_fpsysreg_insn): Likewise.
14013 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
14014 Thomas Preud'homme <thomas.preudhomme@arm.com>
14016 * config/arm/arm-cpus.in (armv8_1m_main): New feature.
14017 (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
14018 ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
14019 ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
14020 ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
14021 (ARMv8_1m_main): New feature group.
14022 (armv8.1-m.main): New architecture.
14023 * config/arm/arm-tables.opt: Regenerate.
14024 * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
14025 (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
14026 (arm_options_perform_arch_sanity_checks): Error out when targeting
14027 Armv8.1-M Mainline Security Extensions.
14028 * config/arm/arm.h (arm_arch8_1m_main): Declare.
14030 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14032 * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot,
14033 aarch64_bfdot_lane, aarch64_bfdot_laneq): New.
14034 * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane,
14035 aarch64_bfdot_laneq): New.
14036 * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32,
14037 vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32,
14038 vbfdotq_laneq_f32): New.
14039 * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype,
14040 VBFMLA_W, VBF): New.
14041 (isquadop): Add V4BF, V8BF.
14043 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14045 * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
14046 New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
14047 TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
14048 (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
14049 (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
14050 * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
14051 usdot_laneq, sudot_lane,sudot_laneq): New.
14052 * config/aarch64/aarch64-simd.md (aarch64_usdot): New.
14053 (aarch64_<sur>dot_lane): New.
14054 * config/aarch64/arm_neon.h (vusdot_s32): New.
14055 (vusdotq_s32): New.
14056 (vusdot_lane_s32): New.
14057 (vsudot_lane_s32): New.
14058 * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
14059 (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.
14061 2020-01-16 Martin Liska <mliska@suse.cz>
14063 * value-prof.c (dump_histogram_value): Fix
14064 obvious spacing issue.
14066 2020-01-16 Andrew Pinski <apinski@marvell.com>
14068 * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for
14069 !storage_order_barrier_p.
14071 2020-01-16 Andrew Pinski <apinski@marvell.com>
14073 * sched-int.h (_dep): Add unused bit-field field for the padding.
14074 * sched-deps.c (init_dep_1): Init unused field.
14076 2020-01-16 Andrew Pinski <apinski@marvell.com>
14078 * optabs.h (create_expand_operand): Initialize target field also.
14080 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
14082 PR tree-optimization/92429
14083 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter.
14084 * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to
14086 * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing
14089 2020-01-16 Richard Sandiford <richard.sandiford@arm.com>
14091 * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply
14092 aarch64_sve_int_mode to each mode.
14094 2020-01-15 David Malcolm <dmalcolm@redhat.com>
14096 * doc/analyzer.texi (Overview): Add note about
14097 -fdump-ipa-analyzer.
14099 2020-01-15 Wilco Dijkstra <wdijkstr@arm.com>
14101 PR tree-optimization/93231
14102 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check
14103 input_type is unsigned. Use tree_to_shwi for shift constant.
14104 Check CST_STRING element size is CHAR_TYPE_SIZE bits.
14105 (simplify_count_trailing_zeroes): Add test to handle known non-zero
14106 inputs more efficiently.
14108 2020-01-15 Uroš Bizjak <ubizjak@gmail.com>
14110 * config/i386/i386.md (*movsf_internal): Do not require
14111 SSE2 ISA for alternatives 14 and 15.
14113 2020-01-15 Richard Biener <rguenther@suse.de>
14115 PR middle-end/93273
14116 * tree-eh.c (sink_clobbers): If we already visited the destination
14117 block do not defer insertion.
14118 (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for
14119 the purpose of defered insertion.
14121 2020-01-15 Jakub Jelinek <jakub@redhat.com>
14123 * BASE-VER: Bump to 10.0.1.
14125 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
14127 PR tree-optimization/93247
14128 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access
14129 type of the stmt that we're going to vectorize.
14131 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
14133 * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a
14134 VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent
14137 2020-01-15 Martin Liska <mliska@suse.cz>
14139 * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow
14140 2 calls of streamer_read_hwi in a function call.
14142 2020-01-15 Richard Biener <rguenther@suse.de>
14144 * alias.c (record_alias_subset): Avoid redundant work when
14145 subset is already recorded.
14147 2020-01-14 David Malcolm <dmalcolm@redhat.com>
14149 * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of
14150 the analyzer options provide CWE identifiers.
14152 2020-01-14 David Malcolm <dmalcolm@redhat.com>
14154 * tree-diagnostic-path.cc (path_summary::event_range::print):
14155 When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers
14156 using get_pure_location.
14158 2020-01-15 Jakub Jelinek <jakub@redhat.com>
14160 PR tree-optimization/93262
14161 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins,
14162 perform head trimming only if the last argument is constant,
14163 either all ones, or larger or equal to head trim, in the latter
14164 case decrease the last argument by head_trim.
14166 PR tree-optimization/93249
14167 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h.
14168 (maybe_trim_memstar_call): Move head_trim and tail_trim vars to
14169 function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't
14170 perform head trim unless we can prove there are no '\0' chars
14171 from the source among the first head_trim chars.
14173 2020-01-14 David Malcolm <dmalcolm@redhat.com>
14175 * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o.
14177 2020-01-15 Jakub Jelinek <jakub@redhat.com>
14180 * config/i386/sse.md
14181 (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1,
14182 *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1,
14183 *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1,
14184 *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use
14185 just a single alternative instead of two, make operands 1 and 2
14188 2020-01-14 Jan Hubicka <hubicka@ucw.cz>
14191 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and
14194 2020-01-14 David Malcolm <dmalcolm@redhat.com>
14196 * Makefile.in (lang_opt_files): Add analyzer.opt.
14197 (ANALYZER_OBJS): New.
14198 (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o,
14199 tristate.o and ANALYZER_OBJS.
14200 (TEXI_GCCINT_FILES): Add analyzer.texi.
14201 * common.opt (-fanalyzer): New driver option.
14202 * config.in: Regenerate.
14203 * configure: Regenerate.
14204 * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option.
14205 (gccdepdir): Also create depdir for "analyzer" subdir.
14206 * digraph.cc: New file.
14207 * digraph.h: New file.
14208 * doc/analyzer.texi: New file.
14209 * doc/gccint.texi ("Static Analyzer") New menu item.
14210 (analyzer.texi): Include it.
14211 * doc/invoke.texi ("Static Analyzer Options"): New list and new section.
14212 ("Warning Options"): Add static analysis warnings to the list.
14213 (-Wno-analyzer-double-fclose): New option.
14214 (-Wno-analyzer-double-free): New option.
14215 (-Wno-analyzer-exposure-through-output-file): New option.
14216 (-Wno-analyzer-file-leak): New option.
14217 (-Wno-analyzer-free-of-non-heap): New option.
14218 (-Wno-analyzer-malloc-leak): New option.
14219 (-Wno-analyzer-possible-null-argument): New option.
14220 (-Wno-analyzer-possible-null-dereference): New option.
14221 (-Wno-analyzer-null-argument): New option.
14222 (-Wno-analyzer-null-dereference): New option.
14223 (-Wno-analyzer-stale-setjmp-buffer): New option.
14224 (-Wno-analyzer-tainted-array-index): New option.
14225 (-Wno-analyzer-use-after-free): New option.
14226 (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option.
14227 (-Wno-analyzer-use-of-uninitialized-value): New option.
14228 (-Wanalyzer-too-complex): New option.
14229 (-fanalyzer-call-summaries): New warning.
14230 (-fanalyzer-checker=): New warning.
14231 (-fanalyzer-fine-grained): New warning.
14232 (-fno-analyzer-state-merge): New warning.
14233 (-fno-analyzer-state-purge): New warning.
14234 (-fanalyzer-transitivity): New warning.
14235 (-fanalyzer-verbose-edges): New warning.
14236 (-fanalyzer-verbose-state-changes): New warning.
14237 (-fanalyzer-verbosity=): New warning.
14238 (-fdump-analyzer): New warning.
14239 (-fdump-analyzer-callgraph): New warning.
14240 (-fdump-analyzer-exploded-graph): New warning.
14241 (-fdump-analyzer-exploded-nodes): New warning.
14242 (-fdump-analyzer-exploded-nodes-2): New warning.
14243 (-fdump-analyzer-exploded-nodes-3): New warning.
14244 (-fdump-analyzer-supergraph): New warning.
14245 * doc/sourcebuild.texi (dg-require-dot): New.
14246 (dg-check-dot): New.
14247 * gdbinit.in (break-on-saved-diagnostic): New command.
14248 * graphviz.cc: New file.
14249 * graphviz.h: New file.
14250 * ordered-hash-map-tests.cc: New file.
14251 * ordered-hash-map.h: New file.
14252 * passes.def (pass_analyzer): Add before
14253 pass_ipa_whole_program_visibility.
14254 * selftest-run-tests.c (selftest::run_tests): Call
14255 selftest::ordered_hash_map_tests_cc_tests.
14256 * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New
14258 * shortest-paths.h: New file.
14259 * timevar.def (TV_ANALYZER): New timevar.
14260 (TV_ANALYZER_SUPERGRAPH): Likewise.
14261 (TV_ANALYZER_STATE_PURGE): Likewise.
14262 (TV_ANALYZER_PLAN): Likewise.
14263 (TV_ANALYZER_SCC): Likewise.
14264 (TV_ANALYZER_WORKLIST): Likewise.
14265 (TV_ANALYZER_DUMP): Likewise.
14266 (TV_ANALYZER_DIAGNOSTICS): Likewise.
14267 (TV_ANALYZER_SHORTEST_PATHS): Likewise.
14268 * tree-pass.h (make_pass_analyzer): New decl.
14269 * tristate.cc: New file.
14270 * tristate.h: New file.
14272 2020-01-14 Uroš Bizjak <ubizjak@gmail.com>
14275 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for
14276 alternatives 9 and 10.
14278 2020-01-14 David Malcolm <dmalcolm@redhat.com>
14280 * attribs.c (excl_hash_traits::empty_zero_p): New static constant.
14281 * gcov.c (function_start_pair_hash::empty_zero_p): Likewise.
14282 * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise.
14283 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest.
14284 (selftest::hash_map_tests_c_tests): Call it.
14285 * hash-map-traits.h (simple_hashmap_traits::empty_zero_p):
14286 New static constant, using the value of = H::empty_zero_p.
14287 (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value
14288 from default_hash_traits <Value>.
14289 * hash-map.h (hash_map::empty_zero_p): Likewise, using the value
14291 * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise.
14292 * hash-table.h (hash_table::alloc_entries): Guard the loop of
14293 calls to mark_empty with !Descriptor::empty_zero_p.
14294 (hash_table::empty_slow): Conditionalize the memset call with a
14295 check that Descriptor::empty_zero_p; otherwise, loop through the
14296 entries calling mark_empty on them.
14297 * hash-traits.h (int_hash::empty_zero_p): New static constant.
14298 (pointer_hash::empty_zero_p): Likewise.
14299 (pair_hash::empty_zero_p): Likewise.
14300 * ipa-devirt.c (default_hash_traits <type_pair>::empty_zero_p):
14302 * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise.
14303 (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise.
14304 * profile.c (location_triplet_hash::empty_zero_p): Likewise.
14305 * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise.
14306 (sanopt_tree_couple_hash::empty_zero_p): Likewise.
14307 * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise.
14308 * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise.
14309 * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise.
14310 * tree-vectorizer.h
14311 (default_hash_traits<scalar_cond_masked_key>::empty_zero_p):
14314 2020-01-14 Kewen Lin <linkw@gcc.gnu.org>
14316 * cfgloopanal.c (average_num_loop_insns): Free bbs when early return,
14317 fix typo on return value.
14319 2020-01-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
14322 * cgraph.c (symbol_table::create_edge): Init speculative_id and
14324 (cgraph_edge::make_speculative): Add param for setting speculative_id
14326 (cgraph_edge::speculative_call_info): Update comments and find reference
14327 by speculative_id for multiple indirect targets.
14328 (cgraph_edge::resolve_speculation): Decrease the speculations
14329 for indirect edge, drop it's speculative if not direct target
14330 left. Update comments.
14331 (cgraph_edge::redirect_call_stmt_to_callee): Likewise.
14332 (cgraph_node::dump): Print num_speculative_call_targets.
14333 (cgraph_node::verify_node): Don't report error if speculative
14334 edge not include statement.
14335 (cgraph_edge::num_speculative_call_targets_p): New function.
14336 * cgraph.h (int common_target_id): Remove.
14337 (int common_target_probability): Remove.
14338 (num_speculative_call_targets): New variable.
14339 (make_speculative): Add param for setting speculative_id.
14340 (cgraph_edge::num_speculative_call_targets_p): New declare.
14341 (target_prob): New variable.
14342 (speculative_id): New variable.
14343 * ipa-fnsummary.c (analyze_function_body): Create and duplicate
14344 call summaries for multiple speculative call targets.
14345 * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id.
14346 * ipa-profile.c (struct speculative_call_target): New struct.
14347 (class speculative_call_summary): New class.
14348 (class speculative_call_summaries): New class.
14349 (call_sums): New variable.
14350 (ipa_profile_generate_summary): Generate indirect multiple targets summaries.
14351 (ipa_profile_write_edge_summary): New function.
14352 (ipa_profile_write_summary): Stream out indirect multiple targets summaries.
14353 (ipa_profile_dump_all_summaries): New function.
14354 (ipa_profile_read_edge_summary): New function.
14355 (ipa_profile_read_summary_section): New function.
14356 (ipa_profile_read_summary): Stream in indirect multiple targets summaries.
14357 (ipa_profile): Generate num_speculative_call_targets from
14359 * ipa-ref.h (speculative_id): New variable.
14360 * ipa-utils.c (ipa_merge_profiles): Update with target_prob.
14361 * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and
14362 common_target_probability. Stream out speculative_id and
14363 num_speculative_call_targets.
14364 (input_edge): Likewise.
14365 * predict.c (dump_prediction): Remove edges count assert to be
14367 * symtab.c (symtab_node::create_reference): Init speculative_id.
14368 (symtab_node::clone_references): Clone speculative_id.
14369 (symtab_node::clone_referring): Clone speculative_id.
14370 (symtab_node::clone_reference): Clone speculative_id.
14371 (symtab_node::clear_stmts_in_references): Clear speculative_id.
14372 * tree-inline.c (copy_bb): Duplicate all the speculative edges
14373 if indirect call contains multiple speculative targets.
14374 * value-prof.h (check_ic_target): Remove.
14375 * value-prof.c (gimple_value_profile_transformations):
14376 Use void function gimple_ic_transform.
14377 * value-prof.c (gimple_ic_transform): Handle topn case.
14378 Fix comment typos. Change it to a void function.
14380 2020-01-13 Andrew Pinski <apinski@marvell.com>
14382 * config/aarch64/aarch64-cores.def (octeontx2): New define.
14383 (octeontx2t98): New define.
14384 (octeontx2t96): New define.
14385 (octeontx2t93): New define.
14386 (octeontx2f95): New define.
14387 (octeontx2f95n): New define.
14388 (octeontx2f95mm): New define.
14389 * config/aarch64/aarch64-tune.md: Regenerate.
14390 * doc/invoke.texi (-mcpu=): Document the new cpu types.
14392 2020-01-13 Jason Merrill <jason@redhat.com>
14394 PR c++/33799 - destroy return value if local cleanup throws.
14395 * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR.
14397 2020-01-13 Martin Liska <mliska@suse.cz>
14399 * ipa-cp.c (get_max_overall_size): Use newly
14400 renamed param param_ipa_cp_unit_growth.
14401 * params.opt: Remove legacy param name.
14403 2020-01-13 Martin Sebor <msebor@redhat.com>
14405 PR tree-optimization/93213
14406 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul
14407 stores to be eliminated.
14409 2020-01-13 Martin Liska <mliska@suse.cz>
14411 * opts.c (print_help): Do not print CL_PARAM
14412 and CL_WARNING for CL_OPTIMIZATION.
14414 2020-01-13 Jonathan Wakely <jwakely@redhat.com>
14417 * doc/invoke.texi (Warning Options): Add caveat about some warnings
14418 depending on optimization settings.
14420 2020-01-13 Jakub Jelinek <jakub@redhat.com>
14422 PR tree-optimization/90838
14423 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
14424 SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro
14425 argument rather than to initialize temporary for targets that
14426 don't use the mode argument at all. Initialize ctzval to avoid
14429 2020-01-10 Thomas Schwinge <thomas@codesourcery.com>
14431 * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition.
14432 * tree-core.h: Document it.
14433 * gimplify.c (gimplify_omp_workshare): Set it.
14434 * omp-low.c (lower_omp_target): Use it.
14435 * tree-pretty-print.c (dump_omp_clause): Print it.
14437 * omp-low.c (lower_omp_target) <OMP_CLAUSE_USE_DEVICE_PTR etc.>:
14438 Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'.
14440 2020-01-10 David Malcolm <dmalcolm@redhat.com>
14442 * Makefile.in (OBJS): Add tree-diagnostic-path.o.
14443 * common.opt (fdiagnostics-path-format=): New option.
14444 (diagnostic_path_format): New enum.
14445 (fdiagnostics-show-path-depths): New option.
14446 * coretypes.h (diagnostic_event_id_t): New forward decl.
14447 * diagnostic-color.c (color_dict): Add "path".
14448 * diagnostic-event-id.h: New file.
14449 * diagnostic-format-json.cc (json_from_expanded_location): Make
14451 (json_end_diagnostic): Call context->make_json_for_path if it
14452 exists and the diagnostic has a path.
14453 (diagnostic_output_format_init): Clear context->print_path.
14454 * diagnostic-path.h: New file.
14455 * diagnostic-show-locus.c (colorizer::set_range): Special-case
14456 when printing a run of events in a diagnostic_path so that they
14457 all get the same color.
14458 (layout::m_diagnostic_path_p): New field.
14459 (layout::layout): Initialize it.
14460 (layout::print_any_labels): Don't colorize the label text for an
14461 event in a diagnostic_path.
14462 (gcc_rich_location::add_location_if_nearby): Add
14463 "restrict_to_current_line_spans" and "label" params. Pass the
14464 former to layout.maybe_add_location_range; pass the latter
14465 when calling add_range.
14466 * diagnostic.c: Include "diagnostic-path.h".
14467 (diagnostic_initialize): Initialize context->path_format and
14468 context->show_path_depths.
14469 (diagnostic_show_any_path): New function.
14470 (diagnostic_path::interprocedural_p): New function.
14471 (diagnostic_report_diagnostic): Call diagnostic_show_any_path.
14472 (simple_diagnostic_path::num_events): New function.
14473 (simple_diagnostic_path::get_event): New function.
14474 (simple_diagnostic_path::add_event): New function.
14475 (simple_diagnostic_event::simple_diagnostic_event): New ctor.
14476 (simple_diagnostic_event::~simple_diagnostic_event): New dtor.
14477 (debug): New overload taking a diagnostic_path *.
14478 * diagnostic.def (DK_DIAGNOSTIC_PATH): New.
14479 * diagnostic.h (enum diagnostic_path_format): New enum.
14480 (json::value): New forward decl.
14481 (diagnostic_context::path_format): New field.
14482 (diagnostic_context::show_path_depths): New field.
14483 (diagnostic_context::print_path): New callback field.
14484 (diagnostic_context::make_json_for_path): New callback field.
14485 (diagnostic_show_any_path): New decl.
14486 (json_from_expanded_location): New decl.
14487 * doc/invoke.texi (-fdiagnostics-path-format=): New option.
14488 (-fdiagnostics-show-path-depths): New option.
14489 (-fdiagnostics-color): Add "path" to description of default
14490 GCC_COLORS; describe it.
14491 (-fdiagnostics-format=json): Document how diagnostic paths are
14492 represented in the JSON output format.
14493 * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
14494 Add optional params "restrict_to_current_line_spans" and "label".
14495 * opts.c (common_handle_option): Handle
14496 OPT_fdiagnostics_path_format_ and
14497 OPT_fdiagnostics_show_path_depths.
14498 * pretty-print.c: Include "diagnostic-event-id.h".
14499 (pp_format): Implement "%@" format code for printing
14500 diagnostic_event_id_t *.
14501 (selftest::test_pp_format): Add tests for "%@".
14502 * selftest-run-tests.c (selftest::run_tests): Call
14503 selftest::tree_diagnostic_path_cc_tests.
14504 * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl.
14505 * toplev.c (general_init): Initialize global_dc->path_format and
14506 global_dc->show_path_depths.
14507 * tree-diagnostic-path.cc: New file.
14508 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make
14509 non-static. Drop "diagnostic" param in favor of storing the
14510 original value of "where" and re-using it.
14511 (virt_loc_aware_diagnostic_finalizer): Update for dropped param of
14512 maybe_unwind_expanded_macro_loc.
14513 (tree_diagnostics_defaults): Initialize context->print_path and
14514 context->make_json_for_path.
14515 * tree-diagnostic.h (default_tree_diagnostic_path_printer): New
14517 (default_tree_make_json_for_path): New decl.
14518 (maybe_unwind_expanded_macro_loc): New decl.
14520 2020-01-10 Jakub Jelinek <jakub@redhat.com>
14522 PR tree-optimization/93210
14523 * fold-const.h (native_encode_initializer,
14524 can_native_interpret_type_p): Declare.
14525 * fold-const.c (native_encode_string): Fix up handling with off != -1,
14527 (native_encode_initializer): New function, moved from dwarf2out.c.
14528 Adjust to native_encode_expr compatible arguments, including dry-run
14529 and partial extraction modes. Don't handle STRING_CST.
14530 (can_native_interpret_type_p): No longer static.
14531 * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify
14532 offset / BITS_PER_UNIT fits into int and don't call it if
14533 can_native_interpret_type_p fails. If suboff is NULL and for
14534 CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with
14535 native_encode_initializer.
14536 (fold_const_aggregate_ref_1): Formatting fix.
14537 * dwarf2out.c (native_encode_initializer): Moved to fold-const.c.
14538 (tree_add_const_value_attribute): Adjust caller.
14540 PR tree-optimization/90838
14541 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
14542 SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of
14543 CTZ_DEFINED_VALUE_AT_ZERO.
14545 2020-01-10 Vladimir Makarov <vmakarov@redhat.com>
14547 PR inline-asm/93027
14548 * lra-constraints.c (match_reload): Permit input operands have the
14549 same mode as output while other input operands have a different
14552 2020-01-10 Wilco Dijkstra <wdijkstr@arm.com>
14554 PR tree-optimization/90838
14555 * tree-ssa-forwprop.c (check_ctz_array): Add new function.
14556 (check_ctz_string): Likewise.
14557 (optimize_count_trailing_zeroes): Likewise.
14558 (simplify_count_trailing_zeroes): Likewise.
14559 (pass_forwprop::execute): Try ctz simplification.
14560 * match.pd: Add matching for ctz idioms.
14562 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14564 * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function
14566 (aarch64_invalid_unary_op): New function for target hook.
14567 (aarch64_invalid_binary_op): New function for target hook.
14569 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14571 * config.gcc: Add arm_bf16.h.
14572 * config/aarch64/aarch64-builtins.c
14573 (aarch64_simd_builtin_std_type): Add BFmode.
14574 (aarch64_init_simd_builtin_types): Define element types for vector
14576 (aarch64_init_bf16_types): New function.
14577 (aarch64_general_init_builtins): Add arm_init_bf16_types function call.
14578 * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector
14580 * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types.
14581 * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move
14583 * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF.
14584 (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF.
14585 * config/aarch64/aarch64.c
14586 (aarch64_classify_vector_mode): Add support for BF types.
14587 (aarch64_gimplify_va_arg_expr): Add support for BF types.
14588 (aarch64_vq_mode): Add support for BF types.
14589 (aarch64_simd_container_mode): Add support for BF types.
14590 (aarch64_mangle_type): Add support for BF scalar type.
14591 * config/aarch64/aarch64.md: Add BFmode to movhf pattern.
14592 * config/aarch64/arm_bf16.h: New file.
14593 * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
14594 * config/aarch64/iterators.md: Add BF types to mode attributes.
14595 (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New.
14597 2020-01-10 Jason Merrill <jason@redhat.com>
14599 PR c++/93173 - incorrect tree sharing.
14600 * gimplify.c (copy_if_shared): No longer static.
14601 * gimplify.h: Declare it.
14603 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
14605 * doc/invoke.texi (-msve-vector-bits=): Document that
14606 -msve-vector-bits=128 now generates VL-specific code for
14607 little-endian targets.
14608 * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use
14609 build_vector_type_for_mode to construct the data vector types.
14610 * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate
14611 VL-specific code for -msve-vector-bits=128 on little-endian targets.
14612 (aarch64_simd_container_mode): Always prefer Advanced SIMD modes
14613 for 128-bit vectors.
14615 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
14617 * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask
14620 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
14622 * config/aarch64/aarch64-builtins.c
14623 (aarch64_builtin_vectorized_function): Check for specific vector modes,
14624 rather than checking the number of elements and the element mode.
14626 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
14628 * tree-vect-loop.c (vect_create_epilog_for_reduction): Use
14629 get_related_vectype_for_scalar_type rather than build_vector_type
14630 to create the index type for a conditional reduction.
14632 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
14634 * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF
14635 for any type of gather or scatter, including strided accesses.
14637 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
14639 * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function
14642 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
14644 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use
14645 get_dr_vinfo_offset
14646 * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init
14647 parameter and its use to reset DR_OFFSET's.
14648 (vect_transform_loop): Remove orig_drs_init argument.
14649 * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset
14650 member of dr_vec_info rather than the offset of the associated
14651 data_reference's innermost_loop_behavior.
14652 (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference.
14653 (vect_do_peeling): Remove orig_drs_init parameter and its construction.
14654 * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with
14655 get_dr_vinfo_offset.
14656 (vectorizable_store): Likewise.
14657 (vectorizable_load): Likewise.
14659 2020-01-10 Richard Biener <rguenther@suse.de>
14661 * gimple-ssa-store-merging
14662 (pass_store_merging::terminate_all_aliasing_chains): Cache alias info.
14664 2020-01-10 Martin Liska <mliska@suse.cz>
14667 * ipa-inline-analysis.c (offline_size): Make proper parenthesis
14668 encapsulation that was there before r280040.
14670 2020-01-10 Richard Biener <rguenther@suse.de>
14672 PR middle-end/93199
14673 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL
14674 sequences to avoid walking them again for secondary opportunities.
14675 (pass_lower_eh_dispatch::execute): Instead actually insert
14678 2020-01-10 Richard Biener <rguenther@suse.de>
14680 PR middle-end/93199
14681 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible.
14682 (cleanup_all_empty_eh): Walk landing pads in reverse order to
14683 avoid quadraticness.
14685 2020-01-10 Martin Jambor <mjambor@suse.cz>
14687 * params.opt (param_ipa_sra_max_replacements): Mark as Optimization.
14688 * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it
14689 to get param_ipa_sra_max_replacements.
14690 (param_splitting_across_edge): Pass the caller to
14691 pull_accesses_from_callee.
14693 2020-01-10 Martin Jambor <mjambor@suse.cz>
14695 * params.opt (param_ipcp_unit_growth): Mark as Optimization.
14696 * ipa-cp.c (max_new_size): Removed.
14697 (orig_overall_size): New variable.
14698 (get_max_overall_size): New function.
14699 (estimate_local_effects): Use it. Adjust dump.
14700 (decide_about_value): Likewise.
14701 (ipcp_propagate_stage): Do not calculate max_new_size, just store
14702 orig_overall_size. Adjust dump.
14703 (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size.
14705 2020-01-10 Martin Jambor <mjambor@suse.cz>
14707 * params.opt (param_ipa_max_agg_items): Mark as Optimization
14708 * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use
14709 instead of param_ipa_max_agg_items.
14710 (merge_aggregate_lattices): Extract param_ipa_max_agg_items from
14711 optimization info for the callee.
14713 2020-01-09 Kwok Cheung Yeung <kcy@codesourcery.com>
14715 * lto-streamer-in.c (input_function): Remove streamed-in inline debug
14716 markers if debug_inline_points is false.
14718 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14720 * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to
14722 * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
14723 aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and
14724 aarch64-sve-builtins-sve2.h.
14725 (aarch64-sve-builtins-sve2.o): New rule.
14726 * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro.
14727 (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise.
14728 (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise.
14729 (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise.
14730 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
14731 TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and
14733 * config/aarch64/aarch64-sve.md: Update comments with SVE2
14734 instructions that are handled here.
14735 (@cond_asrd<mode>): Generalize to...
14736 (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this.
14737 (*cond_asrd<mode>_2): Generalize to...
14738 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this.
14739 (*cond_asrd<mode>_z): Generalize to...
14740 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this.
14741 * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec.
14742 (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise.
14743 (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise.
14744 * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New
14746 (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
14747 (@aarch64_scatter_stnt<mode>): Likewise.
14748 (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
14749 (@aarch64_mul_lane_<mode>): Likewise.
14750 (@aarch64_sve_suqadd<mode>_const): Likewise.
14751 (*<sur>h<addsub><mode>): Generalize to...
14752 (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this
14754 (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander.
14755 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern.
14756 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise.
14757 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise.
14758 (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise.
14759 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise.
14760 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise.
14761 (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise.
14762 (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander.
14763 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern.
14764 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise.
14765 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise.
14766 (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise.
14767 (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>)
14768 (@aarch64_sve_add_mul_lane_<mode>): Likewise.
14769 (@aarch64_sve_sub_mul_lane_<mode>): Likewise.
14770 (@aarch64_sve2_xar<mode>): Likewise.
14771 (@aarch64_sve2_bcax<mode>): Likewise.
14772 (*aarch64_sve2_eor3<mode>): Rename to...
14773 (@aarch64_sve2_eor3<mode>): ...this.
14774 (@aarch64_sve2_bsl<mode>): New expander.
14775 (@aarch64_sve2_nbsl<mode>): Likewise.
14776 (@aarch64_sve2_bsl1n<mode>): Likewise.
14777 (@aarch64_sve2_bsl2n<mode>): Likewise.
14778 (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise.
14779 (*aarch64_sve2_sra<mode>): Add MOVPRFX support.
14780 (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern.
14781 (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise.
14782 (@aarch64_sve2_<USMAX:su>aba<mode>): New expander.
14783 (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern.
14784 (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise.
14785 (<su>mull<bt><Vwide>): Generalize to...
14786 (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new
14788 (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>)
14789 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>)
14790 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>)
14791 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
14792 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>)
14793 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
14794 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>)
14795 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
14796 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>)
14797 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
14798 (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns.
14799 (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>)
14800 (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise.
14801 (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise.
14802 (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise.
14803 (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise.
14804 (<SHRNB:r>shrnb<mode>): Generalize to...
14805 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this
14807 (<SHRNT:r>shrnt<mode>): Generalize to...
14808 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this
14810 (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern.
14811 (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise.
14812 (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander.
14813 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern.
14814 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise.
14815 (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise.
14816 (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise.
14817 (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise.
14818 (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise.
14819 (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise.
14820 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise.
14821 (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander.
14822 (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern.
14823 (@aarch64_sve2_cvtnt<mode>): Likewise.
14824 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise.
14825 (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander.
14826 (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern.
14827 (@aarch64_sve2_cvtxnt<mode>): Likewise.
14828 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise.
14829 (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander.
14830 (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern.
14831 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise.
14832 (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander.
14833 (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern.
14834 (@aarch64_sve2_pmul<mode>): Likewise.
14835 (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise.
14836 (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise.
14837 (@aarch64_sve2_tbl2<mode>): Likewise.
14838 (@aarch64_sve2_tbx<mode>): Likewise.
14839 (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise.
14840 (@aarch64_sve2_histcnt<mode>): Likewise.
14841 (@aarch64_sve2_histseg<mode>): Likewise.
14842 (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
14843 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
14844 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
14845 (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise.
14846 (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise.
14847 (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise.
14848 (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise.
14849 (<su>mulh<r>s<mode>3): Update after above pattern name changes.
14850 * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY)
14851 (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI)
14852 (SVE2_PMULL_PAIR_I): New mode iterators.
14853 (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP)
14854 (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT)
14855 (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA)
14856 (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT)
14857 (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT)
14858 (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP)
14859 (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT)
14860 (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP)
14861 (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH)
14862 (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR)
14863 (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT)
14864 (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB)
14865 (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT)
14866 (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP)
14867 (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT)
14868 (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90)
14869 (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB)
14870 (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB)
14871 (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB)
14872 (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB)
14873 (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT)
14874 (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB)
14875 (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT)
14876 (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT)
14877 (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT)
14878 (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT)
14879 (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT)
14880 (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs.
14881 (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT)
14882 (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS)
14883 (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move
14885 (VNARROW, Ventype): New mode attributes.
14886 (Vewtype): Handle VNx2DI. Fix typo in comment.
14887 (VDOUBLE): New mode attribute.
14888 (sve_lane_con): Handle VNx8HI.
14889 (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2.
14890 (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus.
14891 (sve_int_op, sve_int_op_rev): Handle the above codes.
14892 (sve_pred_int_rhs2_operand): Likewise.
14893 (MULLBT, SHRNB, SHRNT): Delete.
14894 (SVE_INT_SHIFT_IMM): New int iterator.
14895 (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI
14896 and UNSPEC_WHILEHS for TARGET_SVE2.
14897 (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT)
14898 (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG)
14899 (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB)
14900 (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR)
14901 (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators.
14902 (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise.
14903 (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD)
14904 (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise.
14905 (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA)
14906 (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG)
14907 (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise.
14908 (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE)
14909 (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE)
14910 (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise.
14911 (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise.
14912 (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise.
14913 (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise.
14914 (optab): Handle the new unspecs.
14915 (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB
14917 (lr): Handle the new unspecs.
14919 (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs.
14920 (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op)
14921 (sve_int_qsub_op): New int attributes.
14922 (sve_fp_op, rot): Handle the new unspecs.
14923 * config/aarch64/aarch64-sve-builtins.h
14924 (function_resolver::require_matching_pointer_type): Declare.
14925 (function_resolver::resolve_unary): Add an optional boolean argument.
14926 (function_resolver::finish_opt_n_resolution): Add an optional
14927 type_suffix_index argument.
14928 (gimple_folder::redirect_call): Declare.
14929 (gimple_expander::prepare_gather_address_operands): Add an optional
14931 * config/aarch64/aarch64-sve-builtins.cc: Include
14932 aarch64-sve-builtins-sve2.h.
14933 (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros.
14934 (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise.
14935 (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise.
14936 (TYPES_hsd_integer): Use TYPES_hsd_signed.
14937 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros.
14938 (TYPES_s_unsigned): Likewise.
14939 (TYPES_s_integer): Use TYPES_s_unsigned.
14940 (TYPES_sd_signed, TYPES_sd_unsigned): New macros.
14941 (TYPES_sd_integer): Use them.
14942 (TYPES_d_unsigned): New macro.
14943 (TYPES_d_integer): Use it.
14944 (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros.
14945 (TYPES_cvt_narrow): Likewise.
14946 (DEF_SVE_TYPES_ARRAY): Include the new types macros above.
14947 (preds_mx): New variable.
14948 (function_builder::add_overloaded_function): Allow the new feature
14949 set to be more restrictive than the original one.
14950 (function_resolver::infer_pointer_type): Remove qualifiers from
14951 the pointer type before printing it.
14952 (function_resolver::require_matching_pointer_type): New function.
14953 (function_resolver::resolve_sv_displacement): Handle functions
14954 that don't support 32-bit vector indices or svint32_t vector offsets.
14955 (function_resolver::finish_opt_n_resolution): Take the inferred type
14956 as a separate argument.
14957 (function_resolver::resolve_unary): Optionally treat all forms in
14958 the same way as normal merging functions.
14959 (gimple_folder::redirect_call): New function.
14960 (function_expander::prepare_gather_address_operands): Add an argument
14961 that says whether scaled forms are available. If they aren't,
14962 handle scaling of vector indices and don't add the extension and
14964 (function_expander::map_to_unspecs): If aarch64_sve isn't available,
14965 fall back to using cond_* instead.
14966 * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function):
14967 Split out the member variables into...
14968 (rtx_code_function_base): ...this new base class.
14969 (rtx_code_function_rotated): Inherit rtx_code_function_base.
14970 (unspec_based_function): Split out the member variables into...
14971 (unspec_based_function_base): ...this new base class.
14972 (unspec_based_function_rotated): Inherit unspec_based_function_base.
14973 (unspec_based_function_exact_insn): New class.
14974 (unspec_based_add_function, unspec_based_add_lane_function)
14975 (unspec_based_lane_function, unspec_based_pred_function)
14976 (unspec_based_qadd_function, unspec_based_qadd_lane_function)
14977 (unspec_based_qsub_function, unspec_based_qsub_lane_function)
14978 (unspec_based_sub_function, unspec_based_sub_lane_function): New
14980 (unspec_based_fused_function): New class.
14981 (unspec_based_mla_function, unspec_based_mls_function): New typedefs.
14982 (unspec_based_fused_lane_function): New class.
14983 (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New
14985 (CODE_FOR_MODE1): New macro.
14986 (fixed_insn_function): New class.
14987 (while_comparison): Likewise.
14988 * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane)
14989 (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n)
14990 (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr)
14991 (load_ext_gather_index_restricted, load_ext_gather_offset_restricted)
14992 (load_gather_sv_restricted, shift_left_imm_long): Declare.
14993 (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise.
14994 (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise.
14995 (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted)
14996 (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane)
14997 (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate)
14998 (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint)
14999 (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt)
15000 (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise.
15001 * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
15002 Also add an initial argument for unary_convert_narrowt, regardless
15003 of the predication type.
15004 (build_32_64): Allow loads and stores to specify MODE_none.
15005 (build_sv_index64, build_sv_uint_offset): New functions.
15006 (long_type_suffix): New function.
15007 (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes.
15008 (binary_imm_long_base, load_gather_sv_base): Likewise.
15009 (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise.
15010 (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise.
15011 (unary_narrowb_base, unary_narrowt_base): Likewise.
15012 (binary_long_lane_def, binary_long_lane): New shape.
15013 (binary_long_opt_n_def, binary_long_opt_n): Likewise.
15014 (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise.
15015 (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise.
15016 (binary_to_uint_def, binary_to_uint): Likewise.
15017 (binary_wide_def, binary_wide): Likewise.
15018 (binary_wide_opt_n_def, binary_wide_opt_n): Likewise.
15019 (compare_def, compare): Likewise.
15020 (compare_ptr_def, compare_ptr): Likewise.
15021 (load_ext_gather_index_restricted_def,
15022 load_ext_gather_index_restricted): Likewise.
15023 (load_ext_gather_offset_restricted_def,
15024 load_ext_gather_offset_restricted): Likewise.
15025 (load_gather_sv_def): Inherit from load_gather_sv_base.
15026 (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape.
15027 (shift_left_imm_def, shift_left_imm): Likewise.
15028 (shift_left_imm_long_def, shift_left_imm_long): Likewise.
15029 (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise.
15030 (store_scatter_index_restricted_def,
15031 store_scatter_index_restricted): Likewise.
15032 (store_scatter_offset_restricted_def,
15033 store_scatter_offset_restricted): Likewise.
15034 (tbl_tuple_def, tbl_tuple): Likewise.
15035 (ternary_long_lane_def, ternary_long_lane): Likewise.
15036 (ternary_long_opt_n_def, ternary_long_opt_n): Likewise.
15037 (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base.
15038 (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape
15039 (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base.
15040 (ternary_qq_rotate_def, ternary_qq_rotate): New shape.
15041 (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise.
15042 (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise.
15043 (ternary_uint_def, ternary_uint): Likewise.
15044 (unary_convert): Fix typo in comment.
15045 (unary_convert_narrowt_def, unary_convert_narrowt): New shape.
15046 (unary_long_def, unary_long): Likewise.
15047 (unary_narrowb_def, unary_narrowb): Likewise.
15048 (unary_narrowt_def, unary_narrowt): Likewise.
15049 (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise.
15050 (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise.
15051 (unary_to_int_def, unary_to_int): Likewise.
15052 * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla)
15053 (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions.
15054 (svasrd_impl): Delete.
15055 (svcadd_impl::expand): Handle integer operations too.
15056 (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the
15057 new functions to derive the unspec numbers.
15058 (svmla_svmls_lane_impl): Replace with...
15059 (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle
15060 integer operations too.
15061 (svwhile_impl): Rename to...
15062 (svwhilelx_impl): ...this and inherit from while_comparison.
15063 (svasrd): Use unspec_based_function.
15064 (svmla_lane): Use svmla_lane_impl.
15065 (svmls_lane): Use svmls_lane_impl.
15066 (svrecpe, svrsqrte): Handle unsigned integer operations too.
15067 (svwhilele, svwhilelt): Use svwhilelx_impl.
15068 * config/aarch64/aarch64-sve-builtins-sve2.h: New file.
15069 * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
15070 * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
15071 * config/aarch64/aarch64-sve-builtins.def: Include
15072 aarch64-sve-builtins-sve2.def.
15074 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
15076 * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
15077 (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
15078 * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
15079 (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar
15080 immediates as well as vector ones.
15081 * config/aarch64/predicates.md (aarch64_sve_arith_immediate)
15082 (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
15083 (aarch64_sve_qsub_immediate): Update calls accordingly.
15085 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
15087 * config/aarch64/aarch64-sve2.md: Add banner comments.
15088 (<su>mulh<r>s<mode>3): Move further up file.
15089 (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>)
15090 (*aarch64_sve2_sra<mode>): Move further down file.
15091 * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too.
15093 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
15095 * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW
15096 and UNSPEC_WHILEWR.
15097 (while_optab_cmp): Handle them.
15098 * config/aarch64/aarch64-sve.md
15099 (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public
15100 and add a "@" marker.
15101 * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it
15102 instead of gen_aarch64_sve2_while_ptest.
15103 (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete.
15105 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
15107 * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to...
15108 (UNSPEC_WHILELE): ...this.
15109 (UNSPEC_WHILE_LO): Rename to...
15110 (UNSPEC_WHILELO): ...this.
15111 (UNSPEC_WHILE_LS): Rename to...
15112 (UNSPEC_WHILELS): ...this.
15113 (UNSPEC_WHILE_LT): Rename to...
15114 (UNSPEC_WHILELT): ...this.
15115 * config/aarch64/iterators.md (SVE_WHILE): Update accordingly.
15116 (cmp_op, while_optab_cmp): Likewise.
15117 * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise.
15118 * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise.
15119 (svwhilelt): Likewise.
15121 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
15123 * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete.
15124 (unary_to_uint): Define.
15125 * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def)
15126 (unary_count): Rename to...
15127 (unary_to_uint_def, unary_to_uint): ...this.
15128 * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly.
15130 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
15132 * config/aarch64/aarch64-sve-builtins-functions.h
15133 (code_for_mode_function): New class.
15134 (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros.
15135 * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl)
15136 (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete.
15137 (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0.
15138 (svmul_lane, svtmad): Use CODE_FOR_MODE0.
15140 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
15142 * config/aarch64/iterators.md (addsub): New code attribute.
15143 * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>):
15145 (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change
15146 in the asm string and attributes. Fix indentation.
15147 * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>):
15149 (@aarch64_sve_<optab><mode>): ...this.
15150 * config/aarch64/aarch64-sve-builtins.h
15151 (function_expander::expand_signed_unpred_op): Delete.
15152 * config/aarch64/aarch64-sve-builtins.cc
15153 (function_expander::expand_signed_unpred_op): Likewise.
15154 (function_expander::map_to_rtx_codes): If the optab isn't defined,
15155 try using code_for_aarch64_sve instead.
15156 * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete.
15157 (svqsub_impl): Likewise.
15158 (svqadd, svqsub): Use rtx_code_function instead.
15160 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
15162 * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete.
15163 (HADDSUB, sur, addsub): Remove them.
15165 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
15167 * tree-nrv.c (pass_return_slot::execute): Handle all internal
15168 functions the same way, rather than singling out those that
15169 aren't mapped directly to optabs.
15171 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
15173 * target.def (compatible_vector_types_p): New target hook.
15174 * hooks.h (hook_bool_const_tree_const_tree_true): Declare.
15175 * hooks.c (hook_bool_const_tree_const_tree_true): New function.
15176 * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook.
15177 * doc/tm.texi: Regenerate.
15178 * gimple-expr.c: Include target.h.
15179 (useless_type_conversion_p): Use targetm.compatible_vector_types_p.
15180 * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New
15182 (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define.
15183 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred):
15184 Use the original predicate if it already has a suitable type.
15186 2020-01-09 Martin Jambor <mjambor@suse.cz>
15188 * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct,
15189 resolve_speculation and redirect_call_stmt_to_callee static. Change
15190 return type of set_call_stmt to cgraph_edge *.
15191 * auto-profile.c (afdo_indirect_call): Adjust call to
15192 redirect_call_stmt_to_callee.
15193 * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *,
15194 make the this pointer explicit, adjust self-recursive calls and the
15195 call top make_direct. Return the resulting edge.
15196 (cgraph_edge::remove): Make this pointer explicit.
15197 (cgraph_edge::resolve_speculation): Likewise, adjust call to remove.
15198 (cgraph_edge::make_direct): Likewise, adjust call to
15199 resolve_speculation.
15200 (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust
15201 call to set_call_stmt.
15202 (cgraph_update_edges_for_call_stmt_node): Update call to
15203 set_call_stmt and remove.
15204 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
15205 Renamed edge to master_edge. Adjusted calls to set_call_stmt.
15206 (cgraph_node::create_edge_including_clones): Moved "first" definition
15207 of edge to the block where it was used. Adjusted calls to
15209 (cgraph_node::remove_symbol_and_inline_clones): Adjust call to
15210 cgraph_edge::remove.
15211 * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to
15212 make_direct and redirect_call_stmt_to_callee.
15213 * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to
15214 resolve_speculation and make_direct.
15215 * ipa-inline-transform.c (inline_transform): Adjust call to
15216 redirect_call_stmt_to_callee.
15217 (check_speculations_1):: Adjust call to resolve_speculation.
15218 * ipa-inline.c (resolve_noninline_speculation): Adjust call to
15219 resolve-speculation.
15220 (inline_small_functions): Adjust call to resolve_speculation.
15221 (ipa_inline): Likewise.
15222 * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to
15224 * ipa-visibility.c (function_and_variable_visibility): Make iteration
15225 safe with regards to edge removal, adjust calls to
15226 redirect_call_stmt_to_callee.
15227 * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct
15228 and redirect_call_stmt_to_callee.
15229 * multiple_target.c (create_dispatcher_calls): Adjust call to
15230 redirect_call_stmt_to_callee
15231 (redirect_to_specific_clone): Likewise.
15232 * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph):
15233 Adjust calls to cgraph_edge::remove.
15234 * tree-inline.c (copy_bb): Adjust call to set_call_stmt.
15235 (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee.
15236 (expand_call_inline): Adjust call to cgraph_edge::remove.
15238 2020-01-09 Martin Liska <mliska@suse.cz>
15240 * params.opt: Set Optimization for
15241 param_max_speculative_devirt_maydefs.
15243 2020-01-09 Martin Sebor <msebor@redhat.com>
15245 PR middle-end/93200
15247 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type.
15249 2020-01-09 Martin Liska <mliska@suse.cz>
15251 * auto-profile.c (auto_profile): Use opt_for_fn
15253 * ipa-cp.c (ipcp_lattice::add_value): Likewise.
15254 (propagate_vals_across_arith_jfunc): Likewise.
15255 (hint_time_bonus): Likewise.
15256 (incorporate_penalties): Likewise.
15257 (good_cloning_opportunity_p): Likewise.
15258 (perform_estimation_of_a_value): Likewise.
15259 (estimate_local_effects): Likewise.
15260 (ipcp_propagate_stage): Likewise.
15261 * ipa-fnsummary.c (decompose_param_expr): Likewise.
15262 (set_switch_stmt_execution_predicate): Likewise.
15263 (analyze_function_body): Likewise.
15264 * ipa-inline-analysis.c (offline_size): Likewise.
15265 * ipa-inline.c (early_inliner): Likewise.
15266 * ipa-prop.c (ipa_analyze_node): Likewise.
15267 (ipcp_transform_function): Likewise.
15268 * ipa-sra.c (process_scan_results): Likewise.
15269 (ipa_sra_summarize_function): Likewise.
15270 * params.opt: Rename ipcp-unit-growth to
15271 ipa-cp-unit-growth. Add Optimization for various
15272 IPA-related parameters.
15274 2020-01-09 Richard Biener <rguenther@suse.de>
15276 PR middle-end/93054
15277 * gimplify.c (gimplify_expr): Deal with NOP definitions.
15279 2020-01-09 Richard Biener <rguenther@suse.de>
15281 PR tree-optimization/93040
15282 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit.
15284 2020-01-09 Georg-Johann Lay <avr@gjlay.de>
15286 * common/config/avr/avr-common.c (avr_option_optimization_table)
15287 [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early.
15289 2020-01-09 Martin Liska <mliska@suse.cz>
15291 * cgraphclones.c (symbol_table::materialize_all_clones):
15292 Use cgraph_node::dump_name.
15294 2020-01-09 Jakub Jelinek <jakub@redhat.com>
15296 PR inline-asm/93202
15297 * config/riscv/riscv.c (riscv_print_operand_reloc): Use
15298 output_operand_lossage instead of gcc_unreachable.
15299 * doc/md.texi (riscv f constraint): Fix typo.
15302 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of
15303 SWI. Use <general_hilo_operand> instead of <general_operand>. Use
15304 CONST_SCALAR_INT_P instead of CONST_INT_P.
15305 (*subv<mode>4_1): Rename to ...
15306 (subv<mode>4_1): ... this.
15307 (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
15308 define_insn_and_split patterns.
15309 (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
15312 2020-01-08 David Malcolm <dmalcolm@redhat.com>
15314 * vec.c (class selftest::count_dtor): New class.
15315 (selftest::test_auto_delete_vec): New test.
15316 (selftest::vec_c_tests): Call it.
15317 * vec.h (class auto_delete_vec): New class template.
15318 (auto_delete_vec<T>::~auto_delete_vec): New dtor.
15320 2020-01-08 David Malcolm <dmalcolm@redhat.com>
15322 * sbitmap.h (auto_sbitmap): Add operator const_sbitmap.
15324 2020-01-08 Jim Wilson <jimw@sifive.com>
15326 * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out
15327 use of TLS_MODEL_LOCAL_EXEC when not pic.
15329 2020-01-08 David Malcolm <dmalcolm@redhat.com>
15331 * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix
15334 2020-01-08 Jakub Jelinek <jakub@redhat.com>
15337 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2,
15338 *stack_protect_set_3 peephole2): Also check that the second
15339 insns source is general_operand.
15342 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand
15343 predicate for output operand instead of register_operand.
15344 (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with
15345 memory destination and non-memory operands[2].
15347 2020-01-08 Martin Liska <mliska@suse.cz>
15349 * cgraph.c (cgraph_node::dump): Use ::dump_name or
15350 ::dump_asm_name instead of (::name or ::asm_name).
15351 * cgraphclones.c (symbol_table::materialize_all_clones): Likewise.
15352 * cgraphunit.c (walk_polymorphic_call_targets): Likewise.
15353 (analyze_functions): Likewise.
15354 (expand_all_functions): Likewise.
15355 * ipa-cp.c (ipcp_cloning_candidate_p): Likewise.
15356 (propagate_bits_across_jump_function): Likewise.
15357 (dump_profile_updates): Likewise.
15358 (ipcp_store_bits_results): Likewise.
15359 (ipcp_store_vr_results): Likewise.
15360 * ipa-devirt.c (dump_targets): Likewise.
15361 * ipa-fnsummary.c (analyze_function_body): Likewise.
15362 * ipa-hsa.c (check_warn_node_versionable): Likewise.
15363 (process_hsa_functions): Likewise.
15364 * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise.
15365 (set_alias_uids): Likewise.
15366 * ipa-inline-transform.c (save_inline_function_body): Likewise.
15367 * ipa-inline.c (recursive_inlining): Likewise.
15368 (inline_to_all_callers_1): Likewise.
15369 (ipa_inline): Likewise.
15370 * ipa-profile.c (ipa_propagate_frequency_1): Likewise.
15371 (ipa_propagate_frequency): Likewise.
15372 * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.
15373 (remove_described_reference): Likewise.
15374 * ipa-pure-const.c (worse_state): Likewise.
15375 (check_retval_uses): Likewise.
15376 (analyze_function): Likewise.
15377 (propagate_pure_const): Likewise.
15378 (propagate_nothrow): Likewise.
15379 (dump_malloc_lattice): Likewise.
15380 (propagate_malloc): Likewise.
15381 (pass_local_pure_const::execute): Likewise.
15382 * ipa-visibility.c (optimize_weakref): Likewise.
15383 (function_and_variable_visibility): Likewise.
15384 * ipa.c (symbol_table::remove_unreachable_nodes): Likewise.
15385 (ipa_discover_variable_flags): Likewise.
15386 * lto-streamer-out.c (output_function): Likewise.
15387 (output_constructor): Likewise.
15388 * tree-inline.c (copy_bb): Likewise.
15389 * tree-ssa-structalias.c (ipa_pta_execute): Likewise.
15390 * varpool.c (symbol_table::remove_unreferenced_decls): Likewise.
15392 2020-01-08 Richard Biener <rguenther@suse.de>
15394 PR middle-end/93199
15395 * tree-eh.c (sink_clobbers): Update virtual operands for
15396 the first and last stmt only. Add a dry-run capability.
15397 (pass_lower_eh_dispatch::execute): Perform clobber sinking
15398 after CFG manipulations and in RPO order to catch all
15399 secondary opportunities reliably.
15401 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
15404 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
15406 2019-01-08 Richard Biener <rguenther@suse.de>
15408 PR middle-end/93199
15409 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified.
15410 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust
15411 virtual operand, also updating SSA use.
15412 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction):
15413 Update stmt after resetting virtual operand.
15414 (tree_loop_interchange::move_code_to_inner_loop): Likewise.
15415 * gimple-iterator.c (gsi_remove): When not removing the stmt
15416 permanently do not delink immediate uses or mark the stmt modified.
15418 2020-01-08 Martin Liska <mliska@suse.cz>
15420 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name.
15421 (ipa_call_context::estimate_size_and_time): Likewise.
15422 (inline_analyze_function): Likewise.
15424 2020-01-08 Martin Liska <mliska@suse.cz>
15426 * cgraph.c (cgraph_node::dump): Use systematically
15429 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
15431 Add -nodevicespecs option for avr.
15434 * config/avr/avr.opt (-nodevicespecs): New driver option.
15435 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue
15436 "-specs=device-specs/..." if that option is not set.
15437 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
15439 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
15441 Implement 64-bit double functions for avr.
15444 * config.gcc (tm_defines) [target=avr]: Support --with-libf7,
15445 --with-double-comparison.
15446 * doc/install.texi: Document them.
15447 * config/avr/avr-c.c (avr_cpu_cpp_builtins)
15448 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS>
15449 <WITH_DOUBLE_COMPARISON>: New built-in defines.
15450 * doc/invoke.texi (AVR Built-in Macros): Document them.
15451 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New.
15452 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function.
15453 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro.
15455 2020-01-08 Richard Earnshaw <rearnsha@arm.com>
15458 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
15459 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
15460 when only building rm-profile multilibs.
15462 2020-01-08 Feng Xue <fxue@os.amperecomputing.com>
15465 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate
15466 lattice for a value to check.
15467 (propagate_vals_across_arith_jfunc): Add an assertion to ensure
15468 finite propagation in self-recursive scc.
15470 2020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com>
15472 * ipa-inline.c (caller_growth_limits): Restore the AND.
15474 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
15476 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
15477 (VEC_ALLREG_ALT): New iterator.
15478 (VEC_ALLREG_INT_MODE): New iterator.
15479 (VCMP_MODE): New iterator.
15480 (VCMP_MODE_INT): New iterator.
15481 (vec_cmpu<mode>di): Use VCMP_MODE_INT.
15482 (vec_cmp<u>v64qidi): New define_expand.
15483 (vec_cmp<mode>di_exec): Use VCMP_MODE.
15484 (vec_cmpu<mode>di_exec): New define_expand.
15485 (vec_cmp<u>v64qidi_exec): New define_expand.
15486 (vec_cmp<mode>di_dup): Use VCMP_MODE.
15487 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
15488 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
15489 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
15490 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
15491 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
15492 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
15493 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
15494 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
15495 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
15497 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
15498 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend.
15500 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
15502 * config/gcn/constraints.md (DA): Update description and match.
15504 (Db): New constraint.
15505 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
15507 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
15508 Implement 'Db' mixed immediate type.
15509 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
15510 (addcv64si3_dup<exec_vcc>): Delete.
15511 (subcv64si3<exec_vcc>): Rework constraints.
15512 (addv64di3): Rework constraints.
15513 (addv64di3_exec): Rework constraints.
15514 (subv64di3): Rework constraints.
15515 (addv64di3_dup): Delete.
15516 (addv64di3_dup_exec): Delete.
15517 (addv64di3_zext): Rework constraints.
15518 (addv64di3_zext_exec): Rework constraints.
15519 (addv64di3_zext_dup): Rework constraints.
15520 (addv64di3_zext_dup_exec): Rework constraints.
15521 (addv64di3_zext_dup2): Rework constraints.
15522 (addv64di3_zext_dup2_exec): Rework constraints.
15523 (addv64di3_sext_dup2): Rework constraints.
15524 (addv64di3_sext_dup2_exec): Rework constraints.
15526 2020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
15528 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
15529 existing target checks.
15531 2020-01-07 Richard Biener <rguenther@suse.de>
15533 * doc/install.texi: Bump minimal supported MPC version.
15535 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
15537 * langhooks-def.h (lhd_simulate_enum_decl): Declare.
15538 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
15539 * langhooks.c: Include stor-layout.h.
15540 (lhd_simulate_enum_decl): New function.
15541 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
15542 handle_arm_sve_h for the LTO frontend.
15543 (register_vector_type): Cope with null returns from pushdecl.
15545 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
15547 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
15548 (aarch64_sve::nvectors_if_data_type): Replace with...
15549 (aarch64_sve::builtin_type_p): ...this.
15550 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
15551 (find_vector_type): Delete.
15552 (add_sve_type_attribute): New function.
15553 (lookup_sve_type_attribute): Likewise.
15554 (register_builtin_types): Add an "SVE type" attribute to each type.
15555 (register_tuple_type): Likewise.
15556 (svbool_type_p, nvectors_if_data_type): Delete.
15557 (mangle_builtin_type): Use lookup_sve_type_attribute.
15558 (builtin_type_p): Likewise. Add an overload that returns the
15559 number of constituent vector and predicate registers.
15560 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
15561 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
15562 instead of aarch64_sve_argument_p.
15563 (aarch64_takes_arguments_in_sve_regs_p): Likewise.
15564 (aarch64_pass_by_reference): Likewise.
15565 (aarch64_function_value_1): Likewise.
15566 (aarch64_return_in_memory): Likewise.
15567 (aarch64_layout_arg): Likewise.
15569 2020-01-07 Jakub Jelinek <jakub@redhat.com>
15571 PR tree-optimization/93156
15572 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
15573 least significant bit is always clear.
15575 PR tree-optimization/93118
15576 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new
15577 simplifier with two intermediate conversions.
15579 2020-01-07 Martin Liska <mliska@suse.cz>
15581 * params.opt: Add Optimization for various parameters.
15583 2020-01-07 Martin Liska <mliska@suse.cz>
15586 * doc/extend.texi: Explain cloning for target_clone
15589 2020-01-07 Martin Liska <mliska@suse.cz>
15591 PR tree-optimization/92860
15592 * common.opt: Make in Optimization option
15593 as it is affected by -O0, which is an Optimization
15595 * tree-inline.c (tree_inlinable_function_p):
15596 Use opt_for_fn for warn_inline.
15597 (expand_call_inline): Likewise.
15599 2020-01-07 Martin Liska <mliska@suse.cz>
15601 PR tree-optimization/92860
15602 * common.opt: Make flag_ree as optimization
15605 2020-01-07 Martin Liska <mliska@suse.cz>
15607 PR optimization/92860
15608 * params.opt: Mark param_min_crossjump_insns with Optimization
15611 2020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com>
15613 * ipa-inline-analysis.c (estimate_growth): Fix typo.
15614 * ipa-inline.c (caller_growth_limits): Use OR instead of AND.
15616 2020-01-06 Michael Meissner <meissner@linux.ibm.com>
15618 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
15619 helper function to return the valid addressing formats for a given
15620 hard register and mode.
15621 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.
15623 * config/rs6000/constraints.md (Q constraint): Update
15625 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
15628 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
15629 Use 'Q' for doing vector extract from memory.
15630 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
15632 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
15633 doing vector extract from memory.
15634 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
15635 extract from memory.
15637 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
15638 for the offset being 34-bits when -mcpu=future is used.
15640 2020-01-06 John David Anglin <danglin@gcc.gnu.org>
15642 * config/pa/pa.md: Revert change to use ordered_comparison_operator
15643 instead of cmpib_comparison_operator in cmpib patterns.
15644 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal
15645 of cmpib_comparison_operator. Revise comment.
15647 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
15649 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
15650 in an IFN_DIV_POW2 node to be equal.
15652 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
15654 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
15655 (vect_check_scalar_mask): ...this.
15656 (vectorizable_store, vectorizable_load): Update call accordingly.
15657 (vectorizable_call): Use vect_check_scalar_mask to check the mask
15658 argument in calls to conditional internal functions.
15660 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
15662 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
15663 '0' matching inputs.
15664 (subv64di3_exec): Likewise.
15666 2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
15668 * config/mips/mips.c (vr4130_align_insns): Fix typo.
15669 * doc/md.texi (movstr): Likewise.
15671 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
15673 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
15676 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
15678 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):
15680 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents
15681 to a temporary file and use move-if-change to update the real
15682 file where necessary.
15684 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
15686 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
15687 rather than Upa for CPY /M.
15689 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
15691 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline
15694 2020-01-06 Martin Liska <mliska@suse.cz>
15696 PR tree-optimization/92860
15697 * params.opt: Mark param_max_combine_insns with Optimization
15700 2020-01-05 Jakub Jelinek <jakub@redhat.com>
15703 * config/i386/i386.md (SWIDWI): New mode iterator.
15704 (DWI, dwi): Add TImode variants.
15705 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use
15706 <general_hilo_operand> instead of <general_operand>. Use
15707 CONST_SCALAR_INT_P instead of CONST_INT_P.
15708 (*addv<mode>4_1): Rename to ...
15709 (addv<mode>4_1): ... this.
15710 (QWI): New mode attribute.
15711 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
15712 define_insn_and_split patterns.
15713 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
15715 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use
15716 <general_hilo_operand> instead of <general_operand>.
15717 (*addcarry<mode>_1): New define_insn.
15718 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split.
15720 2020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru>
15722 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm):
15723 Use "call" instead of "set".
15725 2020-01-03 Martin Jambor <mjambor@suse.cz>
15728 * ipa-cp.c (print_all_lattices): Skip functions without info.
15730 2020-01-03 Jakub Jelinek <jakub@redhat.com>
15733 * config/i386/i386-options.c (ix86_simd_clone_adjust): If
15734 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd'
15735 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512
15736 for 'e' simd clones.
15739 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave
15741 (mprefer-vector-width=): Add Save.
15742 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print
15743 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment.
15744 (ix86_debug_options, ix86_function_specific_print): Adjust
15745 ix86_target_string callers.
15746 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=.
15747 (ix86_valid_target_attribute_tree): Likewise.
15748 * config/i386/i386-options.h (ix86_target_string): Add PVW argument.
15749 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust
15750 ix86_target_string caller.
15753 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of
15754 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode
15755 instead of gen_int_shift_amount + convert_modes.
15757 PR rtl-optimization/93088
15758 * loop-iv.c (find_single_def_src): Punt after looking through
15759 128 reg copies for regs with single definitions. Move definitions
15762 2020-01-02 Dennis Zhang <dennis.zhang@arm.com>
15764 * config/arm/arm-c.c (arm_cpu_builtins): Define
15765 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC,
15766 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and
15767 __ARM_BF16_FORMAT_ALTERNATIVE when enabled.
15768 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features.
15769 * config/arm/arm-tables.opt: Regenerated.
15770 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize
15771 arm_arch_i8mm and arm_arch_bf16 when enabled.
15772 * config/arm/arm.h (TARGET_I8MM): New macro.
15773 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
15774 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a.
15775 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a.
15776 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a.
15777 (v8_6_a_simd_variants): New.
15778 (v8_*_a_simd_variants): Add i8mm and bf16.
15779 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
15781 2020-01-02 Jakub Jelinek <jakub@redhat.com>
15784 * predict.c (compute_function_frequency): Don't call
15785 warn_function_cold on functions that already have cold attribute.
15787 2020-01-01 John David Anglin <danglin@gcc.gnu.org>
15790 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to
15791 COMDAT group function labels in .data.rel.ro.local section.
15792 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define.
15795 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of
15796 comparison_operator in B and S integer comparisons. Likewise, use
15797 ordered_comparison_operator instead of cmpib_comparison_operator in
15799 * config/pa/predicates.md (cmpib_comparison_operator): Remove.
15801 2020-01-01 Jakub Jelinek <jakub@redhat.com>
15803 Update copyright years.
15805 * gcc.c (process_command): Update copyright notice dates.
15806 * gcov-dump.c (print_version): Ditto.
15807 * gcov.c (print_version): Ditto.
15808 * gcov-tool.c (print_version): Ditto.
15809 * gengtype.c (create_file): Ditto.
15810 * doc/cpp.texi: Bump @copying's copyright year.
15811 * doc/cppinternals.texi: Ditto.
15812 * doc/gcc.texi: Ditto.
15813 * doc/gccint.texi: Ditto.
15814 * doc/gcov.texi: Ditto.
15815 * doc/install.texi: Ditto.
15816 * doc/invoke.texi: Ditto.
15818 2020-01-01 Jan Hubicka <hubicka@ucw.cz>
15820 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall
15823 2020-01-01 Jakub Jelinek <jakub@redhat.com>
15825 PR tree-optimization/93098
15826 * match.pd (popcount): For shift amounts, use integer_onep
15827 or wi::to_widest () == cst instead of tree_to_uhwi () == cst
15828 tests. Make sure that precision is power of two larger than or equal
15829 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro
15830 instead of ULL suffixed constants. Formatting fixes.
15832 Copyright (C) 2020 Free Software Foundation, Inc.
15834 Copying and distribution of this file, with or without modification,
15835 are permitted in any medium without royalty provided the copyright
15836 notice and this notice are preserved.