1 2024-03-14 Jason Merrill <jason@redhat.com>
3 * tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
6 2024-03-14 John David Anglin <danglin@gcc.gnu.org>
9 * config/pa/pa.cc (pa_legitimate_address_p): Don't allow
10 14-bit displacements before reload for modes that may use
11 a floating-point load or store.
13 2024-03-14 David Faust <david.faust@oracle.com>
15 * config/bpf/bpf.h (INT8_TYPE): Change to signed char.
17 2024-03-14 Max Filippov <jcmvbkbc@gmail.com>
19 * config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
20 patterns ahead of the l32i.n and s32i.n.
22 2024-03-14 Jakub Jelinek <jakub@redhat.com>
24 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.
26 2024-03-14 Jakub Jelinek <jakub@redhat.com>
29 * ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
30 SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
33 2024-03-14 Xi Ruoyao <xry111@xry111.site>
35 * config/loongarch/loongarch.md (any_ge): Remove.
36 (sge<u>_<X:mode><GPR:mode>): Remove.
38 2024-03-14 Jakub Jelinek <jakub@redhat.com>
41 * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
42 TImode force newval into a register.
44 2024-03-14 Chung-Lin Tang <cltang@baylibre.com>
46 * tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
47 (OMP_CLAUSE__CACHE__READONLY): New macro.
48 * tree-core.h (struct GTY(()) tree_base): Adjust comments for new
49 uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
50 OMP_CLAUSE__CACHE__READONLY.
51 * tree-pretty-print.cc (dump_omp_clause): Add support for printing
52 OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.
54 2024-03-14 Andreas Krebbel <krebbel@linux.ibm.com>
56 * config/s390/s390.cc (s390_encode_section_info): Adjust the check
57 for misaligned symbols.
58 * config/s390/s390.opt: Improve documentation.
60 2024-03-14 Jakub Jelinek <jakub@redhat.com>
62 * gimple-iterator.cc (edge_before_returns_twice_call): Copy all
63 flags and probability from ad_edge to e edge. If CDI_DOMINATORS
64 are computed, recompute immediate dominator of other_edge->src
66 (gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
67 for the returns_twice call case to the gsi_for_stmt (stmt) to deal
68 with update it for bb splitting.
70 2024-03-14 liuhongt <hongtao.liu@intel.com>
72 * config/i386/i386-features.cc
73 (general_scalar_chain::convert_op): Handle REG_EH_REGION note.
74 (convert_scalars_to_vector): Ditto.
75 * config/i386/i386-features.h (class scalar_chain): New
76 memeber control_flow_insns.
78 2024-03-13 Jakub Jelinek <jakub@redhat.com>
81 * gimple-ssa-store-merging.cc
82 (imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
83 allow matching __builtin_bswap64 if there is bswapsi2 optab.
85 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
87 * config/s390/s390.cc (s390_secondary_reload): Guard
88 SYMBOL_FLAG_NOTALIGN2_P.
90 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
92 * config/s390/s390-builtin-types.def: Update to reflect latest
94 * config/s390/s390-builtins.def: Streamline vector builtins with
97 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
99 * config/s390/s390-builtins.def (vec_permi): Deprecate.
100 (vec_ctd): Deprecate.
101 (vec_ctd_s64): Deprecate.
102 (vec_ctd_u64): Deprecate.
103 (vec_ctsl): Deprecate.
104 (vec_ctul): Deprecate.
105 (vec_ld2f): Deprecate.
106 (vec_st2f): Deprecate.
107 (vec_insert): Deprecate overloads with bool vectors.
109 2024-03-13 Jakub Jelinek <jakub@redhat.com>
112 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
113 TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
114 (bitint_large_huge::handle_load): Pass NULL_TREE rather than
115 rhs_type to limb_access for the bitfield load cases.
116 (bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
117 lhs_type to limb_access if nlhs is non-NULL.
119 2024-03-13 Jakub Jelinek <jakub@redhat.com>
122 * asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
123 build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
124 gsi_safe_insert_before instead of gsi_insert_before.
126 2024-03-13 Jakub Jelinek <jakub@redhat.com>
129 * gimple-iterator.h (gsi_safe_insert_before,
130 gsi_safe_insert_seq_before): Declare.
131 * gimple-iterator.cc: Include gimplify.h.
132 (edge_before_returns_twice_call, adjust_before_returns_twice_call,
133 gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
134 * ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
135 instrument_nonnull_arg, instrument_nonnull_return): Use
136 gsi_safe_insert_before instead of gsi_insert_before.
137 (maybe_instrument_pointer_overflow): Use force_gimple_operand,
138 gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
139 instead of force_gimple_operand_gsi.
140 (instrument_object_size): Likewise. Use gsi_safe_insert_before
141 instead of gsi_insert_before.
143 2024-03-12 Richard Biener <rguenther@suse.de>
145 PR tree-optimization/114121
146 * tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
147 converted operand properly.
148 (chrec_fold_multiply): Likewise. Handle missed recursion.
150 2024-03-12 Jakub Jelinek <jakub@redhat.com>
153 * asan.cc (has_stmt_been_instrumented_p): Don't instrument call
154 stores on the caller side unless it is a call to a builtin or
155 internal function or function doesn't return by hidden reference.
156 (maybe_instrument_call): Likewise.
157 (instrument_derefs): Instrument stores to RESULT_DECL if
158 returning by hidden reference.
160 2024-03-12 Jakub Jelinek <jakub@redhat.com>
162 PR tree-optimization/114293
163 * tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
164 max is smaller than min, set max to ~(size_t)0.
166 2024-03-12 Pan Li <pan2.li@intel.com>
168 * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
169 code style greater than 80 chars.
170 (riscv_cpu_cpp_builtins): Fix useless empty line, indent
171 with 3 space(s) and argument unalignment.
173 2024-03-12 Richard Biener <rguenther@suse.de>
175 PR tree-optimization/114297
176 * tree-vect-loop.cc (vectorizable_live_operation): Pass in the
177 live stmts SLP node to vect_create_epilog_for_reduction.
179 2024-03-12 Andrew Pinski <quic_apinski@quicinc.com>
182 * common.opt (fmultiflags): Add RejectNegative.
184 2024-03-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
186 * config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
187 * config/aarch64/aarch64.opt: Likewise.
188 * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
189 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
190 (aarch64_expand_epilogue): Likewise.
191 (aarch64_post_cfi_startproc): Likewise.
192 (aarch64_handle_no_branch_protection): Copy and rename.
193 (aarch64_handle_standard_branch_protection): Likewise.
194 (aarch64_handle_pac_ret_protection): Likewise.
195 (aarch64_handle_pac_ret_leaf): Likewise.
196 (aarch64_handle_pac_ret_b_key): Likewise.
197 (aarch64_handle_bti_protection): Likewise.
198 (aarch64_override_options): Update branch protection validation.
199 (aarch64_handle_attr_branch_protection): Likewise.
200 * config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
201 Pass branch protection type description as argument.
202 (struct aarch_branch_protect_type): Move from aarch-common.h.
203 * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
205 (aarch_handle_standard_branch_protection): Remove.
206 (aarch_handle_pac_ret_protection): Remove.
207 (aarch_handle_pac_ret_leaf): Remove.
208 (aarch_handle_pac_ret_b_key): Remove.
209 (aarch_handle_bti_protection): Remove.
210 (aarch_validate_mbranch_protection): Pass branch protection type
211 description as argument.
212 * config/arm/aarch-common.h (enum aarch_key_type): Remove.
213 (struct aarch_branch_protect_type): Remove.
214 * config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
215 * config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
216 (arm_handle_standard_branch_protection): Likewise.
217 (arm_handle_pac_ret_protection): Likewise.
218 (arm_handle_pac_ret_leaf): Likewise.
219 (arm_handle_bti_protection): Likewise.
220 (arm_configure_build_target): Update branch protection validation.
221 * config/arm/arm.opt: Remove aarch_ra_sign_key.
223 2024-03-11 Richard Biener <rguenther@suse.de>
226 * gimplify.cc (internal_get_tmp_var): When gimplification
227 of VAL failed, return a decl.
229 2024-03-11 Jakub Jelinek <jakub@redhat.com>
231 PR tree-optimization/114278
232 * tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
233 longer addressable, set DECL_NOT_GIMPLE_REG_P on them.
235 2024-03-11 Eric Botcazou <ebotcazou@adacore.com>
239 * dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
240 generate the DIE with the same parent as in the regular case.
242 2024-03-11 Andrew Pinski <quic_apinski@quicinc.com>
245 * fold-const.cc (merge_truthop_with_opposite_arm): Use
246 the type of the operands of the comparison and not the type
249 2024-03-10 jlaw <jeffreyalaw@gmail.com>
251 PR tree-optimization/110199
252 * tree-ssa-scopedtables.cc
253 (avail_exprs_stack::simplify_binary_operation): Generalize handling
254 of MIN_EXPR/MAX_EXPR to allow additional simplifications. Canonicalize
255 comparison operands for other cases.
257 2024-03-10 Pan Li <pan2.li@intel.com>
259 * tree-vect-stmts.cc (vectorizable_store): Enable the assert
260 during transform process.
261 (vectorizable_load): Ditto.
263 2024-03-10 jlaw <jeffreyalaw@gmail.com>
266 * doc/install.texi: Document need for python when building
269 2024-03-10 jlaw <jeffreyalaw@gmail.com>
272 * mode-switching.cc (optimize_mode_switching): Only process
275 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
277 * config/avr/avr.md: Fix typos in comment, indentation glitches
280 2024-03-09 Jakub Jelinek <jakub@redhat.com>
283 * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
284 src containing MEMs unless prop.likely_profitable_p ().
286 2024-03-09 Xi Ruoyao <xry111@xry111.site>
288 * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
289 Support 'Q' for R_LARCH_RELAX for TLS IE.
290 (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
292 * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
294 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
296 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
297 usum_widenqihi and add_zero_extend1.
298 [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
300 * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
301 Compute exact insn lengths.
302 (*usum_widenqihi3): Allow input operands to commute.
304 2024-03-09 Jakub Jelinek <jakub@redhat.com>
306 * config/i386/i386.opt.urls: Regenerate.
308 2024-03-09 Lulu Cheng <chenglulu@loongson.cn>
310 * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
311 In loongarch64, a sign extension operation is added when
312 operands[2] is a register operand and the mode is SImode.
314 2024-03-08 Martin Jambor <mjambor@suse.cz>
317 * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
318 id->killed_new_ssa_names.
320 2024-03-08 Vladimir N. Makarov <vmakarov@redhat.com>
323 * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
324 for non-reload pseudo too.
326 2024-03-08 David Faust <david.faust@oracle.com>
328 * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
329 not attempt inline expansion if size is above threshold.
330 * config/bpf/bpf.opt (-minline-memops-threshold): New option.
331 * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
334 2024-03-08 Richard Biener <rguenther@suse.de>
336 PR tree-optimization/114269
337 PR tree-optimization/114074
338 * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
339 in the third CASE_CONVERT case as well.
340 (chrec_fold_multiply): Handle sign-conversions from unsigned
341 by performing the operation in the unsigned type.
343 2024-03-08 Georg-Johann Lay <avr@gjlay.de>
345 * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
346 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
348 2024-03-08 Jakub Jelinek <jakub@redhat.com>
350 * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
351 asm_noperands < 0 means it is not asm goto too.
353 2024-03-08 Jakub Jelinek <jakub@redhat.com>
356 * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
358 * config/i386/i386-options.cc (ix86_set_func_type): Don't use
359 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
360 ix86_noreturn_no_callee_saved_registers is enabled.
361 * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
363 2024-03-08 Jakub Jelinek <jakub@redhat.com>
366 * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
367 on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
369 2024-03-08 demin.han <demin.han@starfivetech.com>
372 * config/riscv/riscv-vector-costs.cc: Fix ICE
374 2024-03-08 Haochen Gui <guihaoc@gcc.gnu.org>
376 * fwprop.cc (forward_propagate_into): Return false for volatile set
379 2024-03-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
382 * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
383 (aarch64_expand_cpymem): Emit single load/store only.
384 (aarch64_set_one_block): Emit single stores only.
386 2024-03-07 Robin Dapp <rdapp@ventanamicro.com>
389 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
390 vectorization guards.
392 2024-03-07 Jonathan Wakely <jwakely@redhat.com>
394 * doc/cppopts.texi: Remove incorrect claim about -dD not
395 outputting predefined macros.
397 2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
400 * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
401 and simplify else if with else.
403 2024-03-07 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
405 * system.h: Include safe-ctype.h after C++ standard headers.
407 2024-03-07 Jakub Jelinek <jakub@redhat.com>
409 PR rtl-optimization/110079
410 * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
413 2024-03-07 Jakub Jelinek <jakub@redhat.com>
416 * expmed.cc (choose_mult_variant): Only try the val - 1 variant
417 if val is not HOST_WIDE_INT_MIN or if mode has exactly
418 HOST_BITS_PER_WIDE_INT precision. Avoid triggering UB while computing
421 2024-03-07 Jakub Jelinek <jakub@redhat.com>
424 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
425 Multiple op->off by BITS_PER_UNIT instead of shifting it left by
428 2024-03-07 Yang Yujie <yangyujie@loongson.cn>
430 * config.gcc: Add a case for loongarch*-*-linux-musl*.
431 * config/loongarch/linux.h: Disable the multilib-compatible
432 treatment for *musl* targets.
433 * config/loongarch/musl.h: New file.
435 2024-03-07 Jakub Jelinek <jakub@redhat.com>
437 PR tree-optimization/114009
438 * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
439 argument even for GENERIC, not just for GIMPLE.
440 * match.pd (a * !a -> 0): New simplifications.
442 2024-03-07 demin.han <demin.han@starfivetech.com>
444 * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
445 * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
446 (expand_vec_cmp_float): Adapt arguments
448 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
451 * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
452 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
453 (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
454 (<plusminus:insn>v2qi3): Enable for optimize_size instead
455 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
456 (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
457 (<any_shift:insn>v2qi3): Enable for optimize_size instead
458 of optimize_function_for_size_p.
460 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
464 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
466 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
468 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
469 (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
471 (costs::add_stmt_cost): Also adjust cost for statements without
473 * config/riscv/riscv-vector-costs.h: Define zero constant.
475 2024-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
478 * config/arm/arm.md (NOCOND): Improve comment.
479 (arm_rev*) Add predicable.
480 * config/arm/arm.cc (arm_final_prescan_insn): Add check for
483 2024-03-06 Jeff Law <jlaw@ventanamicro.com>
487 * config/riscv/riscv.cc (expand_conditional_move): Do not swap
488 operands when the comparison operand is the same as the false
491 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
493 * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
494 Eliminate common code and use generic code instead.
496 2024-03-06 Georg-Johann Lay <avr@gjlay.de>
498 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
501 2024-03-06 Richard Biener <rguenther@suse.de>
503 PR tree-optimization/114239
504 * tree-vect-loop.cc (vect_get_vect_def): Remove.
505 (vect_create_epilog_for_reduction): The passed in stmt_info
506 should now be the live stmt that produces the scalar reduction
507 result. Revert PR114192 fix. Base reduction info off
508 info_for_reduction. Remove special handling of
509 early-break/peeled, restore original vector def gathering.
510 Make sure to pick the correct exit PHIs.
511 (vectorizable_live_operation): Pass in the proper stmt_info
512 for early break exits.
514 2024-03-06 Richard Sandiford <richard.sandiford@arm.com>
516 * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
517 out-of-class definitions of static constants.
519 2024-03-06 Richard Biener <rguenther@suse.de>
521 PR tree-optimization/114249
522 * tree-vect-slp.cc (vect_build_slp_instance): Move making
523 a BB reduction lane number even ...
524 (vect_slp_check_for_roots): ... here to avoid leaking
527 2024-03-06 Richard Biener <rguenther@suse.de>
529 PR tree-optimization/114246
530 * tree-ssa-dse.cc (increment_start_addr): Strip useless
531 type conversions from the adjusted address.
533 2024-03-06 Jakub Jelinek <jakub@redhat.com>
535 PR rtl-optimization/114190
536 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
537 Call df_remove_problem for df_note before calling df_analyze.
539 2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
540 Indu Bhagat <indu.bhagat@oracle.com>
543 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
544 in the correct order of the dimensions.
545 (gen_ctf_subrange_type): Refactor out handling of
546 DW_TAG_subrange_type DIE to here.
548 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
551 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
553 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
555 * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
557 * config/aarch64/aarch64-sme.md
558 (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
559 (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
560 (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
561 * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
562 (early_ra::maybe_convert_to_strided_access): Remove support for
563 strided LUTI2 and LUTI4.
565 2024-03-05 Richard Earnshaw <rearnsha@arm.com>
568 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
569 low_register_operand.
571 2024-03-05 Georg-Johann Lay <avr@gjlay.de>
573 * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
574 in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
575 to "X = Y, X o= CST".
577 2024-03-05 Xi Ruoyao <xry111@xry111.site>
579 * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
580 s9 as an alias of r22.
582 2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
584 * config/avr/avr-protos.h (avr_out_insv): New proto.
585 * config/avr/avr.cc (avr_out_insv): New function.
586 (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
587 (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
588 * config/avr/avr.md (define_attr "adjust_len") Add insv.
589 (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
590 Add constraint alternative where the 3rd operand is a power
591 of 2, and the source register may differ from the destination.
592 (*insv.any_shift.<mode>_split): Call avr_out_insv to output
593 instructions. Set attr "length" to "insv".
594 * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
596 2024-03-05 Richard Biener <rguenther@suse.de>
598 PR tree-optimization/114231
599 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
600 processing a BB SLP root.
602 2024-03-05 Jakub Jelinek <jakub@redhat.com>
604 PR rtl-optimization/114211
605 * lower-subreg.cc (resolve_simple_move): For double-word
606 rotates by BITS_PER_WORD if there is overlap between source
607 and destination use a temporary.
609 2024-03-05 Jakub Jelinek <jakub@redhat.com>
612 * gimple-lower-bitint.cc: Include stor-layout.h.
613 (mergeable_op): Return true for BIT_FIELD_REF.
614 (struct bitint_large_huge): Declare handle_bit_field_ref method.
615 (bitint_large_huge::handle_bit_field_ref): New method.
616 (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
618 2024-03-05 Jakub Jelinek <jakub@redhat.com>
621 * config/i386/i386.h (enum call_saved_registers_type): Add
622 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
623 * config/i386/i386-options.cc (ix86_set_func_type): Remove
624 has_no_callee_saved_registers variable, add no_callee_saved_registers
625 instead, initialize it depending on whether it is
626 no_callee_saved_registers function or not. Don't set it if
627 no_caller_saved_registers attribute is present. Adjust users.
628 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
629 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
630 TYPE_NO_CALLEE_SAVED_REGISTERS.
631 (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
633 2024-03-05 Pan Li <pan2.li@intel.com>
635 * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
636 mode_size related code.
638 2024-03-05 Patrick Palka <ppalka@redhat.com>
640 * doc/invoke.texi (-Wno-global-module): Document.
642 2024-03-04 David Faust <david.faust@oracle.com>
644 * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
645 * config/bpf/bpf.cc (bpf_expand_setmem): New.
646 * config/bpf/bpf.md (setmemdi): New define_expand.
648 2024-03-04 Jakub Jelinek <jakub@redhat.com>
650 PR rtl-optimization/113010
651 * combine.cc (simplify_comparison): Guard the
652 WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
653 and initialize inner_mode.
655 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
657 * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
659 (VMLALDAVXQ): Remove iterator.
660 (VMLALDAVXQ_P): Likewise.
661 (VMLALDAVAXQ): Likewise.
662 * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
663 mode iterator attribute with V4BI mode.
664 * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
665 VMLALDAVAXQ_U): Remove unused unspecs.
667 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
669 * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
670 * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
672 * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
673 vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
674 vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
675 vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
676 vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
677 vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
678 vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
679 vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
680 vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
681 vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
683 2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
685 * config/arm/arm.md (mve_unpredicated_insn): New attribute.
686 * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
687 (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
688 (MVE_VPT_PREDICABLE_INSN_P): Likewise.
689 * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
690 * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
691 (arm_vcx1q<a>v16qi): Likewise.
692 (arm_vcx1qav16qi): Likewise.
693 (arm_vcx1qv16qi): Likewise.
694 (arm_vcx2q<a>_p_v16qi): Likewise.
695 (arm_vcx2q<a>v16qi): Likewise.
696 (arm_vcx2qav16qi): Likewise.
697 (arm_vcx2qv16qi): Likewise.
698 (arm_vcx3q<a>_p_v16qi): Likewise.
699 (arm_vcx3q<a>v16qi): Likewise.
700 (arm_vcx3qav16qi): Likewise.
701 (arm_vcx3qv16qi): Likewise.
702 (@mve_<mve_insn>q_<supf><mode>): Likewise.
703 (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
704 (@mve_<mve_insn>q_<supf>v4si): Likewise.
705 (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
706 (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
707 (@mve_<mve_insn>q_f<mode>): Likewise.
708 (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
709 (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
710 (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
711 (@mve_<mve_insn>q_m_f<mode>): Likewise.
712 (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
713 (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
714 (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
715 (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
716 (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
717 (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
718 (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
719 (mve_v<absneg_str>q_f<mode>): Likewise.
720 (mve_<mve_addsubmul>q<mode>): Likewise.
721 (mve_<mve_addsubmul>q_f<mode>): Likewise.
722 (mve_vadciq_<supf>v4si): Likewise.
723 (mve_vadciq_m_<supf>v4si): Likewise.
724 (mve_vadcq_<supf>v4si): Likewise.
725 (mve_vadcq_m_<supf>v4si): Likewise.
726 (mve_vandq_<supf><mode>): Likewise.
727 (mve_vandq_f<mode>): Likewise.
728 (mve_vandq_m_<supf><mode>): Likewise.
729 (mve_vandq_m_f<mode>): Likewise.
730 (mve_vandq_s<mode>): Likewise.
731 (mve_vandq_u<mode>): Likewise.
732 (mve_vbicq_<supf><mode>): Likewise.
733 (mve_vbicq_f<mode>): Likewise.
734 (mve_vbicq_m_<supf><mode>): Likewise.
735 (mve_vbicq_m_f<mode>): Likewise.
736 (mve_vbicq_m_n_<supf><mode>): Likewise.
737 (mve_vbicq_n_<supf><mode>): Likewise.
738 (mve_vbicq_s<mode>): Likewise.
739 (mve_vbicq_u<mode>): Likewise.
740 (@mve_vclzq_s<mode>): Likewise.
741 (mve_vclzq_u<mode>): Likewise.
742 (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
743 (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
744 (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
745 (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
746 (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
747 (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
748 (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
749 (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
750 (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
751 (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
752 (mve_vcvtaq_<supf><mode>): Likewise.
753 (mve_vcvtaq_m_<supf><mode>): Likewise.
754 (mve_vcvtbq_f16_f32v8hf): Likewise.
755 (mve_vcvtbq_f32_f16v4sf): Likewise.
756 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
757 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
758 (mve_vcvtmq_<supf><mode>): Likewise.
759 (mve_vcvtmq_m_<supf><mode>): Likewise.
760 (mve_vcvtnq_<supf><mode>): Likewise.
761 (mve_vcvtnq_m_<supf><mode>): Likewise.
762 (mve_vcvtpq_<supf><mode>): Likewise.
763 (mve_vcvtpq_m_<supf><mode>): Likewise.
764 (mve_vcvtq_from_f_<supf><mode>): Likewise.
765 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
766 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
767 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
768 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
769 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
770 (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
771 (mve_vcvtq_to_f_<supf><mode>): Likewise.
772 (mve_vcvttq_f16_f32v8hf): Likewise.
773 (mve_vcvttq_f32_f16v4sf): Likewise.
774 (mve_vcvttq_m_f16_f32v8hf): Likewise.
775 (mve_vcvttq_m_f32_f16v4sf): Likewise.
776 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
777 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
778 (mve_veorq_s><mode>): Likewise.
779 (mve_veorq_u><mode>): Likewise.
780 (mve_veorq_f<mode>): Likewise.
781 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
782 (mve_vidupq_u<mode>_insn): Likewise.
783 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
784 (mve_viwdupq_wb_u<mode>_insn): Likewise.
785 (mve_vldrbq_<supf><mode>): Likewise.
786 (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
787 (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
788 (mve_vldrbq_z_<supf><mode>): Likewise.
789 (mve_vldrdq_gather_base_<supf>v2di): Likewise.
790 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
791 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
792 (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
793 (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
794 (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
795 (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
796 (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
797 (mve_vldrhq_<supf><mode>): Likewise.
798 (mve_vldrhq_fv8hf): Likewise.
799 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
800 (mve_vldrhq_gather_offset_fv8hf): Likewise.
801 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
802 (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
803 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
804 (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
805 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
806 (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
807 (mve_vldrhq_z_<supf><mode>): Likewise.
808 (mve_vldrhq_z_fv8hf): Likewise.
809 (mve_vldrwq_<supf>v4si): Likewise.
810 (mve_vldrwq_fv4sf): Likewise.
811 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
812 (mve_vldrwq_gather_base_fv4sf): Likewise.
813 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
814 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
815 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
816 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
817 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
818 (mve_vldrwq_gather_base_z_fv4sf): Likewise.
819 (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
820 (mve_vldrwq_gather_offset_fv4sf): Likewise.
821 (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
822 (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
823 (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
824 (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
825 (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
826 (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
827 (mve_vldrwq_z_<supf>v4si): Likewise.
828 (mve_vldrwq_z_fv4sf): Likewise.
829 (mve_vmvnq_s<mode>): Likewise.
830 (mve_vmvnq_u<mode>): Likewise.
831 (mve_vornq_<supf><mode>): Likewise.
832 (mve_vornq_f<mode>): Likewise.
833 (mve_vornq_m_<supf><mode>): Likewise.
834 (mve_vornq_m_f<mode>): Likewise.
835 (mve_vornq_s<mode>): Likewise.
836 (mve_vornq_u<mode>): Likewise.
837 (mve_vorrq_<supf><mode>): Likewise.
838 (mve_vorrq_f<mode>): Likewise.
839 (mve_vorrq_m_<supf><mode>): Likewise.
840 (mve_vorrq_m_f<mode>): Likewise.
841 (mve_vorrq_m_n_<supf><mode>): Likewise.
842 (mve_vorrq_n_<supf><mode>): Likewise.
843 (mve_vorrq_s<mode>): Likewise.
844 (mve_vorrq_s<mode>): Likewise.
845 (mve_vsbciq_<supf>v4si): Likewise.
846 (mve_vsbciq_m_<supf>v4si): Likewise.
847 (mve_vsbcq_<supf>v4si): Likewise.
848 (mve_vsbcq_m_<supf>v4si): Likewise.
849 (mve_vshlcq_<supf><mode>): Likewise.
850 (mve_vshlcq_m_<supf><mode>): Likewise.
851 (mve_vshrq_m_n_<supf><mode>): Likewise.
852 (mve_vshrq_n_<supf><mode>): Likewise.
853 (mve_vstrbq_<supf><mode>): Likewise.
854 (mve_vstrbq_p_<supf><mode>): Likewise.
855 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
856 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
857 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
858 (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
859 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
860 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
861 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
862 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
863 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
864 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
865 (mve_vstrhq_<supf><mode>): Likewise.
866 (mve_vstrhq_fv8hf): Likewise.
867 (mve_vstrhq_p_<supf><mode>): Likewise.
868 (mve_vstrhq_p_fv8hf): Likewise.
869 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
870 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
871 (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
872 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
873 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
874 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
875 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
876 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
877 (mve_vstrwq_<supf>v4si): Likewise.
878 (mve_vstrwq_fv4sf): Likewise.
879 (mve_vstrwq_p_<supf>v4si): Likewise.
880 (mve_vstrwq_p_fv4sf): Likewise.
881 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
882 (mve_vstrwq_scatter_base_fv4sf): Likewise.
883 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
884 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
885 (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
886 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
887 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
888 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
889 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
890 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
891 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
892 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
893 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
894 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
895 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
896 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
898 2024-03-04 Marek Polacek <polacek@redhat.com>
900 * doc/extend.texi: Update [[gnu::no_dangling]].
902 2024-03-04 Andrew Stubbs <ams@baylibre.com>
904 * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
905 * expr.cc (store_constructor): Likewise.
906 (do_store_flag): Likewise.
908 2024-03-04 Mark Wielaard <mark@klomp.org>
910 * common.opt.urls: Regenerate.
911 * config/avr/avr.opt.urls: Likewise.
912 * config/i386/i386.opt.urls: Likewise.
913 * config/pru/pru.opt.urls: Likewise.
914 * config/riscv/riscv.opt.urls: Likewise.
915 * config/rs6000/rs6000.opt.urls: Likewise.
917 2024-03-04 Richard Biener <rguenther@suse.de>
919 PR tree-optimization/114197
920 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
921 there are volatile bitfield accesses.
922 (pass_if_conversion::execute): Throw away result if the
923 if-converted and original loops are not nested as expected.
925 2024-03-04 Richard Biener <rguenther@suse.de>
927 PR tree-optimization/114164
928 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
929 the code generated for mask argument setup is not supported.
931 2024-03-04 Richard Biener <rguenther@suse.de>
933 PR tree-optimization/114203
934 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
935 adjustment before making the result defined at zero.
937 2024-03-04 Richard Biener <rguenther@suse.de>
939 PR tree-optimization/114192
940 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
941 appropriate def for the live out stmt in case of an alternate
944 2024-03-04 Jakub Jelinek <jakub@redhat.com>
947 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
948 unshare_expr when creating a MEM_REF from MEM_REF.
949 (bitint_large_huge::lower_stmt): Call unshare_expr.
951 2024-03-04 Jakub Jelinek <jakub@redhat.com>
954 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
955 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
958 2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
961 * simplify-rtx.cc (simplify_context::simplify_subreg): Call
962 lowpart_subreg to perform type conversion, to avoid confusion
963 over the offset to use in the call to simplify_reg_subreg.
965 2024-03-03 Greg McGary <gkm@rivosinc.com>
967 PR rtl-optimization/113010
968 * combine.cc (simplify_comparison): Simplify a SUBREG on
969 WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
972 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
974 * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
975 Use bool in place of int for boolean logic (if possible).
976 Move declarations to definitions (if possible).
977 * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
978 * config/avr/avr-dimode.md: Same.
979 * config/avr/constraints.md: Same.
980 * config/avr/predicates.md: Same.
982 2024-03-03 Uros Bizjak <ubizjak@gmail.com>
985 * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
986 (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
987 simplify insn RTX using UMUL_HIGHPART rtx_code.
988 (*umuldi3_highpart_const): Remove.
990 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
993 * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
994 * config/avr/avr.cc (_reg_unused_after): Make static. And
995 add 3rd argument to skip the current insn.
996 (reg_unused_after): Adjust call of reg_unused_after.
997 (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
998 unneeded frame pointer adjustments.
1000 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1003 * config/avr/avr.md (define_attr "cc"): Remove.
1004 * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
1006 * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
1007 its uses. Add insn argument.
1008 (avr_out_plus_symbol): Remove pcc argument and its uses.
1009 (avr_out_plus): Remove pcc argument and its uses.
1010 Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
1011 (avr_out_round): Adjust call of avr_out_plus.
1013 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1015 * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
1018 2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
1021 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
1022 is not an insn, but e.g. a code label.
1024 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1026 * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
1027 * config/avr/avr.cc: Use them instead of magic numbers when it
1028 means a register number.
1030 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1032 * config/avr/avr.cc: Adjust some comments.
1034 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1037 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
1038 the low part of the frame pointer with 8-bit stack pointer.
1040 2024-03-01 Patrick Palka <ppalka@redhat.com>
1044 * tree-inline.cc (remap_decl): Handle copy_decl returning the
1046 (remap_decls): Handle remap_decl returning the original decl.
1047 (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
1050 2024-03-01 Jeff Law <jlaw@ventanamicro.com>
1052 * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
1054 (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
1055 (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
1056 (movhi_internal, movqi_internal): Likewise.
1057 (movsf_softfloat, movsf_hardfloat): Likewise.
1058 (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
1059 (movdf_softfloat): Likewise.
1061 2024-03-01 Marek Polacek <polacek@redhat.com>
1065 * doc/extend.texi: Document gnu::no_dangling.
1066 * doc/invoke.texi: Mention that gnu::no_dangling disables
1067 -Wdangling-reference.
1069 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
1071 * config/avr/avr.opt: Overhaul help screen.
1073 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1074 Tobias Burnus <tburnus@baylibre.com>
1077 * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
1078 lang_hooks.decls.omp_disregard_value_expr for
1079 (first)private in target regions.
1081 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1083 PR middle-end/114136
1084 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
1085 n_named_args initially before INIT_CUMULATIVE_ARGS to
1086 structure_value_addr_parm rather than 0, after it don't modify
1087 it if strict_argument_naming and clear only if
1088 !pretend_outgoing_varargs_named.
1090 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1093 * dwarf2out.cc (should_move_die_to_comdat): Return false for
1094 aggregates without DW_AT_byte_size attribute or with non-constant
1097 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
1099 * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
1100 valid values for level.
1102 2024-03-01 Richard Biener <rguenther@suse.de>
1104 PR middle-end/114070
1105 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
1106 Allow the folding if before lowering and the current IL
1107 isn't supported with vcond_mask.
1109 2024-03-01 xuli <xuli1@eswincomputing.com>
1111 * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
1112 attribute to riscv_attribute_table.
1113 (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
1114 (riscv_fntype_abi): Add riscv_vector_cc attribute check.
1115 * doc/extend.texi: Add riscv_vector_cc attribute description.
1117 2024-03-01 Pan Li <pan2.li@intel.com>
1120 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
1121 RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
1122 * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
1123 (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
1124 * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
1125 comments for option replacement.
1126 * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
1127 riscv_autovec_preference to rvv_vector_bits.
1128 (vls_mode_valid_p): Ditto.
1129 (estimated_poly_value): Ditto.
1130 * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
1131 vector chunks and honor new option mrvv-vector-bits.
1132 (riscv_override_options_internal): Update comments and rename the
1134 * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
1135 internal option param=riscv-autovec-preference.
1137 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1139 * function.cc (assign_parms): Only call assign_parms_setup_varargs
1140 early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
1142 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1144 PR middle-end/114156
1145 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
1146 rhs1 of a VCE to have no underlying variable if it is a load and
1149 2024-02-29 David Malcolm <dmalcolm@redhat.com>
1152 * function.cc (function_name): Make param const.
1153 * function.h (function_name): Likewise.
1155 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
1158 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
1159 * config/avr/avr.opt (-mfuse-add=): New target option.
1160 * common/config/avr/avr-common.cc (avr_option_optimization_table)
1161 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
1162 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
1163 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
1164 * config/avr/avr-protos.h (avr_split_tiny_move)
1165 (make_avr_pass_fuse_add): New protos.
1166 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
1167 avr_split_tiny_move to split indirect memory accesses.
1168 (gen_move_clobbercc): New define_expand helper.
1169 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
1170 (avr_pass_fuse_add): New class from rtl_opt_pass.
1171 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
1172 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
1173 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
1174 of PLUS addressing for AVR_TINY.
1175 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
1176 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
1177 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
1179 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
1182 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
1183 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
1184 (avr_function_arg): Set it.
1185 (avr_frame_pointer_required_p): Use it instead of .nregs.
1187 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
1190 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
1191 static and mark with GTY.
1193 2024-02-29 Xi Ruoyao <xry111@xry111.site>
1195 * config/loongarch/loongarch.md
1196 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
1198 2024-02-29 Xi Ruoyao <xry111@xry111.site>
1200 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
1201 (crc): New define_int_attr.
1202 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
1204 (loongarch_<crc>_w_<size>_w): ... here.
1206 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
1209 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
1210 extend the expected value if needed.
1212 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1214 * config.gcc (target_gtfiles): Change coreout to btfext-out.
1215 (extra_objs): Change coreout to btfext-out.
1216 * config/bpf/coreout.cc: Rename to btfext-out.cc.
1217 * config/bpf/btfext-out.cc: Add.
1218 * config/bpf/coreout.h: Rename to btfext-out.h.
1219 * config/bpf/btfext-out.h: Add.
1220 * config/bpf/core-builtins.cc: Change include.
1221 * config/bpf/core-builtins.h: Change include.
1222 * config/bpf/t-bpf: Accomodate renamed files.
1224 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1227 * config/bpf/bpf.cc (bpf_function_prologue): Define target
1229 * config/bpf/coreout.cc (brf_ext_info_section)
1230 (btf_ext_info): Move from coreout.h
1231 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
1232 (bpf_core_reloc): Rename to btf_ext_core_reloc.
1233 (btf_ext): Add static variable.
1234 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
1235 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
1236 (btf_ext_add_string, btf_funcinfo_type_callback)
1237 (btf_add_func_info_for, btf_validate_funcinfo)
1238 (btf_ext_info_len, output_btfext_func_info): Add function.
1239 (output_btfext_header, bpf_core_reloc_add)
1240 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
1241 Change to support new structs.
1242 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
1243 Move and change in coreout.cc.
1244 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
1246 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1248 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
1249 enabled by default for BPF.
1250 (bpf_file_end): Call BTF deallocation.
1251 (bpf_asm_init_sections): Correct condition.
1252 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
1254 (ctf_debuf_finish): Correct condition for calling
1257 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1259 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
1260 (traverse_btf_func_types): Define function.
1261 * ctfc.h (funcs_traverse_callback): Typedef for function
1263 (traverse_btf_func_types): Add prototype.
1265 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1267 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
1269 2024-02-28 Richard Biener <rguenther@suse.de>
1271 PR tree-optimization/113831
1272 PR tree-optimization/108355
1273 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
1276 2024-02-28 Richard Biener <rguenther@suse.de>
1278 PR tree-optimization/114121
1279 * tree-ssa-sccvn.h (vn_reference_s::offset,
1280 vn_reference_s::max_size): New fields.
1281 (vn_reference_insert_pieces): Adjust prototype.
1282 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
1283 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
1284 size, allow using "don't know" state.
1285 (vn_walk_cb_data::finish): Pass along offset/max_size.
1286 (vn_reference_lookup_or_insert_for_pieces): Take offset and
1287 max_size as argument and use it.
1288 (vn_reference_lookup_3): Properly adjust offset and max_size
1289 according to the adjusted ao_ref.
1290 (vn_reference_lookup_pieces): Initialize offset and max_size.
1291 (vn_reference_lookup): Likewise.
1292 (vn_reference_lookup_call): Likewise.
1293 (vn_reference_insert): Likewise.
1294 (visit_reference_op_call): Likewise.
1295 (vn_reference_insert_pieces): Take offset and max_size
1296 as argument and use it.
1298 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
1300 PR tree-optimization/114075
1301 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
1304 2024-02-28 Jakub Jelinek <jakub@redhat.com>
1306 PR tree-optimization/114041
1307 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
1308 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
1310 2024-02-28 Jakub Jelinek <jakub@redhat.com>
1312 PR tree-optimization/113988
1313 * stor-layout.h (bitwise_mode_for_size): Declare.
1314 * stor-layout.cc (bitwise_mode_for_size): New function.
1315 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
1316 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
1317 Use BITS_PER_UNIT instead of 8.
1319 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
1322 * config/i386/mmx.md (V248FI): Add V2BF mode.
1325 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
1327 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
1328 if either ref->offset is not byte aligned or ref->size is not known
1329 to be equal to ref->max_size.
1330 (maybe_trim_complex_store): Fix description.
1331 (maybe_trim_constructor_store): Likewise.
1332 (maybe_trim_partially_dead_store): Likewise.
1334 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
1336 * config/arm/mmintrin.h: Warn if this header is included without
1337 defining __ENABLE_DEPRECATED_IWMMXT.
1339 2024-02-27 Richard Biener <rguenther@suse.de>
1341 PR tree-optimization/114074
1342 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
1343 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
1344 Handle poly vs. non-poly multiplication correctly with respect
1345 to undefined behavior on overflow.
1347 2024-02-27 Jakub Jelinek <jakub@redhat.com>
1349 PR rtl-optimization/114044
1350 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
1351 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
1352 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
1353 expand_PARITY): Declare.
1354 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
1355 expand_CTZ, expand_FFS, expand_PARITY): New functions.
1356 (expand_POPCOUNT): Use expand_bitquery.
1358 2024-02-27 Richard Biener <rguenther@suse.de>
1360 PR tree-optimization/114081
1361 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1362 Perform manual dominator update for prologue peeling.
1363 (vect_do_peeling): Properly update dominators after adding the
1364 prologue-around guard.
1366 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
1368 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
1369 (mstrict-X): Tag as "Optimization".
1371 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
1373 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
1374 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
1376 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1377 H.J. Lu <hjl.tools@gmail.com>
1379 PR rtl-optimization/113617
1380 * varasm.cc (default_elf_select_rtx_section): For
1381 references to private symbols in comdat sections
1382 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
1383 or .rodata.<comdat> comdat sections.
1385 2024-02-26 Richard Biener <rguenther@suse.de>
1387 PR tree-optimization/114099
1388 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1389 Create and fill in a needed virtual LC PHI for the alternate
1390 exits. Remove code dealing with that missing.
1392 2024-02-26 Richard Biener <rguenther@suse.de>
1394 PR tree-optimization/114068
1395 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
1397 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
1398 on the main exit if needed. Remove band-aid for the case
1401 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
1404 * config/i386/i386-options.cc (ix86_set_func_type): Check
1405 interrupt instead of noreturn attribute.
1407 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1409 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
1412 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1414 PR tree-optimization/114090
1415 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
1416 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
1418 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
1420 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1422 PR middle-end/114084
1423 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
1424 if all subtrees of var0 come from one of the op0 or op1 operands
1425 and all subtrees of con0 come from the other one. Don't clear
1426 variables which are never used afterwards.
1428 2024-02-26 Richard Biener <rguenther@suse.de>
1430 PR middle-end/114070
1431 * genmatch.cc (parser::parse_c_expr): Do not record operand
1432 lists but only mark operators used.
1433 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
1434 Properly guard the case of tcc_comparison changing the VEC_COND
1437 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1440 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
1441 to printed instruction.
1443 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
1446 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
1447 __builtin_ia32_ldtilecfg.
1448 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
1449 * config/i386/i386-builtin.def (BDESC): Add
1450 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
1451 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
1452 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
1453 * config/i386/i386.md (ldtilecfg): New pattern.
1454 (sttilecfg): Likewise.
1456 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
1458 PR tree-optimization/113205
1459 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
1460 the proposed layout if it does not allow a source partition with
1461 layout 2 to keep that layout.
1463 2024-02-24 Jakub Jelinek <jakub@redhat.com>
1465 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
1466 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
1467 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
1468 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
1469 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
1470 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
1472 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
1473 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
1474 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
1475 HOST_WIDE_INT_UC macros.
1476 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
1477 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
1478 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
1479 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
1481 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
1482 * config/i386/constraints.md (define_constraint "L"): Use
1483 HOST_WIDE_INT_C macro.
1484 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
1486 (movl + movb peephole2): Likewise.
1487 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
1488 (const_32bit_mask): Likewise.
1490 2024-02-24 Jakub Jelinek <jakub@redhat.com>
1492 PR middle-end/114073
1493 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
1494 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
1495 types like vector or complex types.
1496 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
1497 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
1498 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
1500 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
1503 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
1504 Return false if inner mode is already Pmode.
1505 (rvv_builder::is_all_same_sequence): New function.
1506 (expand_vec_init): Emit broadcast if sequence is all same.
1508 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
1511 * config/aarch64/aarch64-early-ra.cc
1512 (early_ra::m_current_region): New member variable.
1513 (early_ra::m_fpr_recency): Likewise.
1514 (early_ra::start_new_region): Bump m_current_region.
1515 (early_ra::allocate_colors): Prefer less recently used registers
1516 in the event of a tie. Add a comment to explain why we prefer(ed)
1517 higher-numbered registers.
1518 (early_ra::find_oldest_color): Prefer less recently used registers
1520 (early_ra::finalize_allocation): Update recency information for
1521 allocated registers.
1522 (early_ra::process_blocks): Initialize m_current_region and
1525 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
1528 * config/aarch64/aarch64-early-ra.cc
1529 (early_ra::test_strictness): New enum.
1530 (early_ra::is_chain_candidate): Add a strictness parameter to
1531 control whether only correctness matters, or whether both correctness
1532 and heuristics should be used. Handle multiple levels of equivalence.
1533 (early_ra::find_related_start): Update call accordingly.
1534 (early_ra::strided_polarity_pref): Likewise.
1535 (early_ra::form_chains): Likewise.
1536 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
1537 correctness mode rather than trying to inline the test.
1539 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
1542 * config/aarch64/aarch64-early-ra.cc
1543 (early_ra::find_related_start): Account for definitions by shared
1544 registers when testing for a single register definition.
1545 (early_ra::accumulate_defs): New function.
1546 (early_ra::record_copy): If A shares B's register, fold A's
1547 definition information into B's. Fold A's use information into B's.
1549 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
1551 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
1552 if R_X86_64_CODE_6_GOTTPOFF is supported.
1553 * config.in: Regenerated.
1554 * configure: Likewise.
1555 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
1556 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
1558 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
1561 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
1562 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
1564 2024-02-23 Jakub Jelinek <jakub@redhat.com>
1566 PR rtl-optimization/114054
1567 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
1568 temp variable instead of target parameter for result.
1570 2024-02-23 Jakub Jelinek <jakub@redhat.com>
1572 PR tree-optimization/114040
1573 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
1574 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
1575 probability from likely to unlikely. When handling the true true
1576 store, first cast to limb_access_type and then to l's type.
1578 2024-02-23 Richard Biener <rguenther@suse.de>
1581 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
1583 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
1586 * config/riscv/arch-canonicalize: Move to python3
1587 * config/riscv/multilib-generator: Likewise
1589 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
1591 * doc/invoke.texi: Document -mcpu.
1593 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
1595 * configure: Regenerate.
1596 * configure.ac: Add parameter "--fatal-warnings" to assemble
1597 when checking whether the assemble support conditional branch
1600 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1603 * doc/extend.texi: (__extension__): Remove comments about scope
1604 tokens vs. two colons.
1606 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
1608 PR tree-optimization/109804
1609 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
1610 DEMANGLE_COMPONENT_UNNAMED_TYPE.
1612 2024-02-22 Richard Biener <rguenther@suse.de>
1614 PR tree-optimization/114048
1615 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
1616 can also produce -1 off.
1618 2024-02-22 Richard Biener <rguenther@suse.de>
1620 PR tree-optimization/114027
1621 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
1622 condition reduction classification only for single-element
1625 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1628 * profile-count.h (profile_count::dump): Remove overload with
1629 char * first argument.
1630 * profile-count.cc (profile_count::dump): Change overload with char *
1631 first argument which uses sprintf into the overfload with FILE *
1632 first argument and use fprintf instead. Remove overload which wrapped
1635 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1637 PR tree-optimization/113993
1638 * tree-call-cdce.cc (get_no_error_domain): Handle
1639 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
1640 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
1641 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1642 the as the F128 suffixed cases, otherwise as non-suffixed ones.
1643 Handle BUILT_IN_{EXP,POW}10L for
1644 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1647 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1649 PR tree-optimization/114038
1650 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
1651 loop exit condition if end is divisible by limb_prec.
1653 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
1655 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
1656 problem of mabi=, mno-flush-func, mexplicit-relocs;
1657 add missing leading - of mbranch-cost option.
1658 * config/mips/mips.opt.urls: Regenerate.
1660 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
1663 * config/rs6000/constraints.md (we): Update internal doc without
1664 referring to option -mpower9-vector.
1665 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
1667 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
1668 OTHER_P8_VECTOR_MASKS): Merge to ...
1669 (OTHER_VSX_VECTOR_MASKS): ... here.
1670 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
1671 some error message handlings and explicit option mask adjustments on
1672 explicit option power{8,9}-vector conflicting with other options.
1673 (rs6000_print_isa_options): Update comments.
1674 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
1675 related array items and handlings.
1676 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
1678 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
1680 * doc/extend.texi: Remove documentation referring to option
1682 * doc/invoke.texi: Remove documentation for option
1683 -mpower{8,9}-vector and adjust some documentation referring to them.
1684 * doc/md.texi: Update documentation for constraint we.
1685 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
1687 2024-02-22 Pan Li <pan2.li@intel.com>
1690 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
1691 the version to 0.12.
1693 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1695 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
1697 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1698 Robin Dapp <rdapp.gcc@gmail.com>
1700 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1701 (generic_ooo_vec_load): Ditto
1702 (generic_ooo_vec_store): Ditto
1703 (generic_ooo_vec_loadstore_seg): Ditto
1704 (generic_ooo_vec_alu): Ditto
1705 (generic_ooo_vec_fcmp): Ditto
1706 (generic_ooo_vec_imul): Ditto
1707 (generic_ooo_vec_fadd): Ditto
1708 (generic_ooo_vec_fmul): Ditto
1709 (generic_ooo_crypto): Ditto
1710 (generic_ooo_perm): Ditto
1711 (generic_ooo_vec_reduction): Ditto
1712 (generic_ooo_vec_ordered_reduction): Ditto
1713 (generic_ooo_vec_idiv): Ditto
1714 (generic_ooo_vec_float_divsqrt): Ditto
1715 (generic_ooo_vec_mask): Ditto
1716 (generic_ooo_vec_vesetvl): Ditto
1717 (generic_ooo_vec_setrm): Ditto
1718 (generic_ooo_vec_readlen): Ditto
1719 * config/riscv/riscv.md: Include generic-vector-ooo
1720 * config/riscv/generic-vector-ooo.md: New file. To here
1722 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1724 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1725 (generic_ooo_branch): Ditto
1726 * config/riscv/generic.md (generic_sfb_alu): Ditto
1727 (generic_fmul_half): Ditto
1728 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1729 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
1730 (sifive_7_popcount): Ditto
1731 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
1732 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
1733 * config/riscv/vector.md: Change rdfrm to fmove
1734 * config/riscv/zc.md: Change pushpop to load/store
1736 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
1738 * doc/invoke.texi (Warning Options): Fix typos.
1740 2024-02-21 David Faust <david.faust@oracle.com>
1742 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
1743 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
1744 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
1746 2024-02-21 Martin Jambor <mjambor@suse.cz>
1749 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
1750 initializers in the contructor.
1751 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
1752 * ipa-cp.h: New file.
1753 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
1754 (ipcp_value_source): Move to ipa-cp.h.
1755 (ipcp_value_base): Likewise.
1756 (ipcp_value): Likewise.
1757 (ipcp_lattice): Likewise.
1758 (ipcp_agg_lattice): Likewise.
1759 (ipcp_bits_lattice): Likewise.
1760 (ipcp_vr_lattice): Likewise.
1761 (ipcp_param_lattices): Likewise.
1762 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
1763 (ipa_value_from_jfunc): Adjust a check for empty lattices.
1764 (ipa_context_from_jfunc): Likewise.
1765 (ipa_agg_value_from_jfunc): Likewise.
1766 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
1767 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
1768 just in contiguous memory.
1769 (ipcp_store_vr_results): Adjust a check for empty lattices.
1770 * auto-profile.cc: Include sreal.h and ipa-cp.h.
1771 * cgraph.cc: Likewise.
1772 * cgraphclones.cc: Likewise.
1773 * cgraphunit.cc: Likewise.
1774 * config/aarch64/aarch64.cc: Likewise.
1775 * config/i386/i386-builtins.cc: Likewise.
1776 * config/i386/i386-expand.cc: Likewise.
1777 * config/i386/i386-features.cc: Likewise.
1778 * config/i386/i386-options.cc: Likewise.
1779 * config/i386/i386.cc: Likewise.
1780 * config/rs6000/rs6000.cc: Likewise.
1781 * config/s390/s390.cc: Likewise.
1782 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
1783 files to be included in gtype-desc.cc.
1784 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
1785 * ipa-devirt.cc: Likewise.
1786 * ipa-fnsummary.cc: Likewise.
1787 * ipa-icf.cc: Likewise.
1788 * ipa-inline-analysis.cc: Likewise.
1789 * ipa-inline-transform.cc: Likewise.
1790 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
1791 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
1792 * ipa-param-manipulation.cc: Likewise.
1793 * ipa-predicate.cc: Likewise.
1794 * ipa-profile.cc: Likewise.
1795 * ipa-prop.cc: Likewise.
1796 (ipa_node_params_t::duplicate): Assert new lattices remain empty
1797 instead of setting them to NULL.
1798 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
1799 * ipa-split.cc: Likewise.
1800 * ipa-sra.cc: Likewise.
1801 * ipa-strub.cc: Likewise.
1802 * ipa-utils.cc: Likewise.
1804 * toplev.cc: Likewise.
1805 * tree-ssa-ccp.cc: Likewise.
1806 * tree-ssa-sccvn.cc: Likewise.
1807 * tree-vrp.cc: Likewise.
1809 2024-02-21 Tamar Christina <tamar.christina@arm.com>
1811 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
1814 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1816 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1817 Use aarch64_gen_compare_zero_and_branch rather than emitting
1820 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1822 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
1823 Remove duplicated call.
1825 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1827 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
1828 Check that each individual piece of state is shared in the same
1829 way, rather than using an aggregate check for PSTATE.ZA.
1831 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1833 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1834 In the code that commits a lazy save, only zero ZA if the function
1835 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
1837 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1839 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
1840 directly inserting the associated sequence
1841 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1844 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1847 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
1848 fold the SVE allocation into the initial allocation if the
1849 initial allocation includes a VG save.
1851 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1854 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
1855 contain jumps even if called after initial RTL expansion.
1856 * mode-switching.cc: Include cfgbuild.h.
1857 (optimize_mode_switching): Allow the sequence returned by the
1858 emit hook to contain internal jumps. Record which blocks
1859 contain such jumps and split the blocks at the end.
1860 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
1861 non-debug insns when scanning the sequence.
1863 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
1865 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
1866 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
1868 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
1870 * doc/invoke.texi (-mmcu): Add information about MCU specs.
1872 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
1874 * doc/invoke.texi (-minrt): Clarify that main
1875 must take no arguments.
1877 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
1879 * config/avr/builtins.def: Use function prototypes of given size
1881 * config/avr/avr.cc (avr_init_builtins): Adjust types required
1883 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
1885 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
1887 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
1890 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
1892 * config/bpf/bpf.opt: Add help information for -mcpu.
1894 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
1897 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
1899 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
1901 * config/aarch64/aarch64.md (is_call): New attribute.
1902 (*and<mode>3nr_compare0): Rename to...
1903 (@aarch64_and<mode>3nr_compare0): ...this.
1904 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
1905 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
1906 * config/aarch64/aarch64-speculation.cc: Update file comment to
1907 describe the new late pass.
1908 (aarch64_do_track_speculation): Handle is_call insns like other calls.
1909 (pass_track_speculation): Add an is_late member variable.
1910 (pass_track_speculation::gate): Run the late pass for streaming-
1911 compatible functions and the early pass for other functions.
1912 (make_pass_track_speculation): Update accordingly.
1913 (make_pass_late_track_speculation): New function.
1914 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
1916 (aarch64_guard_switch_pstate_sm): Use it.
1918 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
1920 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
1921 Register these builtins with a pointer to uint64_t rather than unsigned
1924 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
1927 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
1928 Conditionalize on '!TARGET_RDNA2_PLUS'.
1929 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
1930 (gcn_expand_reduc_scalar):
1931 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
1933 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
1935 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
1936 '__gfx90a__' target CPU definition. Add some safeguards for the future.
1938 2024-02-19 Richard Biener <rguenther@suse.de>
1940 PR rtl-optimization/54052
1941 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
1942 local defs by LR_OUT.
1944 2024-02-19 Jakub Jelinek <jakub@redhat.com>
1946 PR tree-optimization/113967
1947 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
1948 in condition that @rpos is multiple of vector element size.
1950 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1953 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
1954 Suppress vsetvl fusion.
1956 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
1959 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
1960 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
1961 (ix86_emit_save_regs): Don't generate push2 if
1962 ix86_can_use_push2pop2 return false.
1963 (ix86_expand_epilogue): Don't generate pop2 if
1964 ix86_can_use_push2pop2 return false.
1966 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
1968 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
1969 Note on complete device support.
1971 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
1973 * doc/extend.texi (AVR Function Attributes): Fuse description
1974 of "signal" and "interrupt" attribute. Link pseudo instruction.
1976 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
1978 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
1979 symbol type conversions.
1980 (__cacop_d): Likewise.
1981 (__cpucfg): Likewise.
1982 (__asrtle_d): Likewise.
1983 (__asrtgt_d): Likewise.
1984 (__lddir_d): Likewise.
1985 (__ldpte_d): Likewise.
1986 (__crc_w_b_w): Likewise.
1987 (__crc_w_h_w): Likewise.
1988 (__crc_w_w_w): Likewise.
1989 (__crc_w_d_w): Likewise.
1990 (__crcc_w_b_w): Likewise.
1991 (__crcc_w_h_w): Likewise.
1992 (__crcc_w_w_w): Likewise.
1993 (__crcc_w_d_w): Likewise.
1994 (__csrrd_w): Likewise.
1995 (__csrwr_w): Likewise.
1996 (__csrxchg_w): Likewise.
1997 (__csrrd_d): Likewise.
1998 (__csrwr_d): Likewise.
1999 (__csrxchg_d): Likewise.
2000 (__iocsrrd_b): Likewise.
2001 (__iocsrrd_h): Likewise.
2002 (__iocsrrd_w): Likewise.
2003 (__iocsrrd_d): Likewise.
2004 (__iocsrwr_b): Likewise.
2005 (__iocsrwr_h): Likewise.
2006 (__iocsrwr_w): Likewise.
2007 (__iocsrwr_d): Likewise.
2008 (__frecipe_s): Likewise.
2009 (__frecipe_d): Likewise.
2010 (__frsqrte_s): Likewise.
2011 (__frsqrte_d): Likewise.
2013 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
2015 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
2016 function return value type to unsigned short.
2018 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
2020 * doc/sourcebuild.texi: add scan-assembler-bound
2022 2024-02-16 Jason Merrill <jason@redhat.com>
2024 * gdbhooks.py: Fix regex syntax.
2026 2024-02-16 Richard Biener <rguenther@suse.de>
2028 PR tree-optimization/113895
2029 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
2030 consistency checking when there are out-of-bound array
2031 accesses. Allow -1 off when from an array reference with
2034 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
2037 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
2040 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
2042 * doc/sourcebuild.texi (Effective-Target Keywords, Other
2043 attribugs): Document linker_plugin.
2044 (Require Support): Document dg-require-linker-plugin.
2046 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
2049 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
2050 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
2051 (RISCV_MINOR_VERSION_BASE): Ditto.
2052 (RISCV_REVISION_VERSION_BASE): Ditto.
2053 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
2054 rather than magic number.
2055 * config/riscv/riscv.h (riscv_arch_help): New.
2056 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
2057 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
2058 --print-supported-extensions.
2059 * config/riscv/riscv.opt (march=help): New.
2060 (print-supported-extensions): New.
2061 (-print-supported-extensions): New.
2062 * doc/invoke.texi (RISC-V Options): Document -march=help.
2064 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
2067 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
2068 for indirect calls with 4 or more arguments in pac-enabled functions.
2070 2024-02-15 David Faust <david.faust@oracle.com>
2072 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
2073 use ldxb instead of ldxh.
2075 2024-02-15 Jakub Jelinek <jakub@redhat.com>
2077 PR middle-end/113921
2078 * cfgrtl.h (prepend_insn_to_edge): New declaration.
2079 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
2081 (prepend_insn_to_edge): New function.
2082 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
2083 insert_insn_on_edge.
2085 2024-02-15 Richard Biener <rguenther@suse.de>
2087 PR tree-optimization/111156
2088 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
2089 at the pattern stmt if any.
2091 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
2094 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
2095 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
2096 * config/avr/avr.cc (avr_adiw_reg_p): New function.
2097 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
2098 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
2099 * config/avr/avr.md: Same.
2100 (attr "isa") <tiny, no_tiny>: Remove.
2101 <adiw, no_adiw>: Add.
2102 (define_insn, define_insn_and_split): When an alternative has
2103 constraint "w", then set attribute "isa" to "adiw".
2104 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
2105 Built-in define __AVR_HAVE_ADIW__.
2106 * doc/invoke.texi (AVR Options): Document it.
2108 2024-02-15 Andrew Stubbs <ams@baylibre.com>
2110 * config/gcn/gcn-valu.md
2111 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
2112 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
2113 details are supported on RDNA devices.
2115 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
2117 PR middle-end/113508
2118 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
2119 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
2120 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
2121 Add sentence about what the mode m is.
2123 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
2125 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
2126 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
2129 2024-02-15 Richard Biener <rguenther@suse.de>
2131 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
2134 2024-02-15 Jakub Jelinek <jakub@redhat.com>
2136 PR tree-optimization/113567
2137 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
2138 _BitInt multiplication, division or modulo with
2139 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
2140 force the affected inputs into a new SSA_NAME.
2142 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
2145 * config/i386/mmx.md (V248FI): New mode iterator.
2147 (vec_shl_<V248FI:mode>): New expander.
2148 (vec_shl_<V24FI_32:mode>): Ditto.
2149 (vec_shr_<V248FI:mode>): Ditto.
2150 (vec_shr_<V24FI_32:mode>): Ditto.
2151 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
2152 (vec_shr_<V248FI:mode>): Ditto.
2154 2024-02-14 Jan Hubicka <jh@suse.cz>
2156 PR tree-optimization/111054
2157 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
2159 2024-02-14 Tamar Christina <tamar.christina@arm.com>
2161 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
2163 2024-02-14 Richard Biener <rguenther@suse.de>
2165 PR tree-optimization/113910
2166 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
2169 2024-02-14 Jakub Jelinek <jakub@redhat.com>
2171 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
2172 (pp_integer_with_precision): For unsigned ptrdiff_t printing
2173 with u, o or x print ptrdiff_t argument converted to
2174 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
2176 2024-02-14 Richard Biener <rguenther@suse.de>
2178 PR middle-end/113576
2179 * expr.cc (do_store_flag): For vector bool compares of vectors
2180 with padding zero that.
2181 * dojump.cc (do_compare_and_jump): Likewise.
2183 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
2185 * doc/install.texi (Prerequisites): Update gettext link.
2187 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
2190 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
2191 Return false if the incoming stack isn't 16-byte aligned.
2193 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
2195 PR middle-end/113904
2196 * omp-general.cc (struct omp_ts_info): Update for splitting of
2197 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2198 * omp-selectors.h (enum omp_tp_type): Replace
2199 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2201 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
2204 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
2205 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
2207 2024-02-13 Richard Biener <rguenther@suse.de>
2209 PR tree-optimization/113895
2210 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
2211 offset to discover constant array indices in bits, handle
2212 COMPONENT_REF to bitfields.
2214 2024-02-13 Richard Biener <rguenther@suse.de>
2216 PR tree-optimization/113831
2217 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
2220 2024-02-13 Richard Biener <rguenther@suse.de>
2222 PR tree-optimization/113902
2223 * tree-vect-loop.cc (move_early_exit_stmts): Track
2224 last_seen_vuse for VUSE updating.
2226 2024-02-13 Tamar Christina <tamar.christina@arm.com>
2228 PR tree-optimization/113734
2229 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
2230 an early break loop as partial.
2232 2024-02-13 Richard Biener <rguenther@suse.de>
2234 PR tree-optimization/113898
2235 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
2236 missing accumulated off adjustment.
2238 2024-02-13 Jakub Jelinek <jakub@redhat.com>
2240 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
2241 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
2242 it against UINT_MAX and ULONG_MAX.
2244 2024-02-13 David Malcolm <dmalcolm@redhat.com>
2246 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
2248 (emit_diagnostic_valist_meta): ...this.
2249 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
2250 (emit_diagnostic_valist_meta): ...this.
2252 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2254 PR tree-optimization/113849
2255 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
2256 fast path for widening casts where !m_upwards_2limb and lhs_type
2257 has precision which is a multiple of limb_prec.
2259 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2262 * attribs.cc (extract_attribute_substring): Remove.
2263 (lookup_scoped_attribute_spec): Don't call it.
2265 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2267 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
2268 and cast to fmt_size_t instead of %lu and cast to unsigned long.
2270 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
2272 * Makefile.in: Add no-info dependency.
2273 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
2275 * configure: Regenerate.
2277 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
2280 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
2281 available to all sub-targets.
2282 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2283 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2285 2024-02-12 Richard Biener <rguenther@suse.de>
2287 PR tree-optimization/113831
2288 PR tree-optimization/108355
2289 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
2290 we see variable array indices and get_ref_base_and_extent
2291 can resolve those to constants fix up the ops to constants
2293 (ao_ref_init_from_vn_reference): Use 'off' member for
2294 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
2295 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
2297 2024-02-12 Pan Li <pan2.li@intel.com>
2299 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
2300 Replace args to arguments for misspelled term.
2302 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
2305 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
2306 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
2307 when not linked with -mrodata-in-ram.
2309 2024-02-12 Richard Biener <rguenther@suse.de>
2311 PR tree-optimization/113863
2312 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2313 Record crossed virtual PHIs.
2314 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
2317 2024-02-10 Marek Polacek <polacek@redhat.com>
2322 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
2324 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2326 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
2327 computation of idx for i == 4 of bitint_prec_huge.
2329 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2331 PR middle-end/110754
2332 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
2333 decls create PARM_DECL with pointer to original type, set
2334 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
2335 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
2336 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
2337 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
2338 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
2339 of the var as argument.
2341 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2343 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
2344 size_t and precision 4 for ptrdiff_t. Formatting fix.
2345 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
2347 (test_pp_format): Test t and z modifiers.
2348 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
2350 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2352 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
2353 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
2354 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
2355 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
2356 and casts to fmt_size_t instead of "%ld" and casts to long.
2357 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
2358 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
2359 instead of "%lu" and casts to unsigned long.
2360 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
2362 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
2363 and casts to fmt_size_t instead of "%ld" and casts to long.
2364 * cfgexpand.cc (dump_stack_var_partition): Use
2365 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
2366 and casts to unsigned long.
2367 * gengtype.cc (adjust_field_rtx_def): Likewise.
2368 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
2369 and casts to fmt_size_t instead of "%ld" and casts to long.
2370 * postreload-gcse.cc (dump_hash_table): Likewise.
2371 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
2372 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
2373 (ggc_internal_alloc, ggc_free): Likewise.
2374 * genpreds.cc (write_lookup_constraint_1): Likewise.
2375 (write_insn_constraint_len): Likewise.
2376 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
2377 and casts to fmt_size_t instead of "%ld" and casts to long.
2378 * varasm.cc (output_constant_pool_contents): Use
2379 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
2380 * var-tracking.cc (dump_var): Likewise.
2382 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2384 PR tree-optimization/113783
2385 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
2386 through VIEW_CONVERT_EXPR for final cast checks. Handle
2387 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
2389 (gimple_lower_bitint): Don't merge mergeable operations or other
2390 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
2391 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
2394 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2396 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
2397 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
2398 HOST_SIZE_T_PRINT_HEX_PURE): Define.
2399 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
2402 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2404 PR middle-end/113415
2405 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
2406 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
2407 of hand written loop with emit_insn of copy_insn and emit original
2408 after_rtl_seq on the last edge.
2410 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2412 PR tree-optimization/113818
2413 * gimple-lower-bitint.cc (add_eh_edge): New function.
2414 (bitint_large_huge::handle_load,
2415 bitint_large_huge::lower_mergeable_stmt,
2416 bitint_large_huge::lower_muldiv_stmt): Use it.
2418 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2420 PR tree-optimization/113774
2421 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
2422 emit any comparison if m_first and low + 1 is equal to
2423 m_upwards_2limb, simplify condition for that. If not
2424 single_comparison, not m_first and we can prove that the idx <= low
2425 comparison will be always true, emit instead of idx <= low
2426 comparison low <= low such that cfg cleanup will optimize it at
2427 the end of the pass.
2429 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
2431 PR tree-optimization/113735
2432 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
2435 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2437 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
2438 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
2440 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
2444 * config/i386/constraints.md: List all constraints with j prefix.
2445 (j>): Change auto-dec to auto-inc in documentation.
2446 (je): Changed to a memory constraint with APX NDD TLS operand
2448 (jM): New memory constraint for APX NDD instructions.
2450 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
2451 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
2452 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
2453 (*add<mode>_1[SWI48]): Use je and jM.
2454 (addsi_1_zext): Use jM.
2455 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
2456 (*sub<mode>_1[SWI]): Use jM.
2457 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
2458 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
2459 (*and<dwi>3_doubleword): Likewise.
2461 (*andsi_1_zext): Likewise.
2462 (*and<mode>_1[SWI24]): Likewise.
2463 (*<code><dwi>3_doubleword[any_or]): Use rjO
2464 (*code<mode>_1[any_or SWI248]): Use jM.
2465 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
2466 * config/i386/predicates.md (apx_ndd_memory_operand): New.
2467 (apx_ndd_add_memory_operand): Likewise.
2469 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2472 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
2473 * doc/avr-mmcu.texi: Rebuild.
2475 2024-02-08 Tamar Christina <tamar.christina@arm.com>
2477 PR tree-optimization/113808
2478 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
2479 value cross iterations.
2481 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2483 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
2484 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
2486 2024-02-08 Richard Biener <rguenther@suse.de>
2488 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2489 Revert last change to dr_may_alias_p.
2491 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2493 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
2494 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
2495 Remove spec asm_misc.
2496 * config/avr/specs.h: Same.
2498 2024-02-08 Pan Li <pan2.li@intel.com>
2501 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
2502 sure the c.arg_num is >= 2 before checking.
2503 (struct build_frm_base): Ditto.
2504 (struct narrow_alu_def): Ditto.
2506 2024-02-07 Richard Biener <rguenther@suse.de>
2508 PR tree-optimization/113796
2509 * tree-if-conv.cc (combine_blocks): Wipe range-info before
2510 replacing PHIs and inserting predicates.
2512 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
2513 Uros Bizjak <ubizjak@gmail.com>
2516 * config/i386/i386-features.cc (timode_convert_cst): New helper
2517 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
2519 (timode_scalar_chain::convert_op): Use timode_convert_cst.
2520 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
2521 Use timode_convert_cst.
2523 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
2525 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
2526 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
2527 (AARCH64_FL_DEBUGv8p9): Likewise.
2528 (AARCH64_FL_FGT2): Likewise.Likewise.
2529 (AARCH64_FL_ITE): Likewise.
2530 (AARCH64_FL_PFAR): Likewise.
2531 (AARCH64_FL_PMUv3_ICNTR): Likewise.
2532 (AARCH64_FL_PMUv3_SS): Likewise.
2533 (AARCH64_FL_PMUv3p9): Likewise.
2534 (AARCH64_FL_RASv2): Likewise.
2535 (AARCH64_FL_S1PIE): Likewise.
2536 (AARCH64_FL_S1POE): Likewise.
2537 (AARCH64_FL_S2PIE): Likewise.
2538 (AARCH64_FL_S2POE): Likewise.
2539 (AARCH64_FL_SCTLR2): Likewise.
2540 (AARCH64_FL_SEBEP): Likewise.
2541 (AARCH64_FL_SPE_FDS): Likewise.
2542 (AARCH64_FL_TCR2): Likewise.
2544 2024-02-07 Richard Biener <rguenther@suse.de>
2546 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2547 Only check whether reads are in-bound in places that are not safe.
2548 Fix dependence check. Add missing newline. Clarify comments.
2550 2024-02-07 Tamar Christina <tamar.christina@arm.com>
2552 PR tree-optimization/113750
2553 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
2554 for single predecessor when doing early break vect.
2555 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
2558 2024-02-07 Tamar Christina <tamar.christina@arm.com>
2560 PR tree-optimization/113731
2561 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
2563 * gimple-iterator.h (gsi_move_before): Default new param to
2565 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
2568 2024-02-07 Jakub Jelinek <jakub@redhat.com>
2570 PR tree-optimization/113756
2571 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
2572 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
2573 of lh_bits value and mask.
2575 2024-02-07 Jakub Jelinek <jakub@redhat.com>
2577 PR tree-optimization/113753
2578 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
2579 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
2580 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
2581 so that they start with r[half_blocks_needed] lowest bit. Fix up
2582 computation of top mask for SIGNED.
2584 2024-02-07 Pan Li <pan2.li@intel.com>
2587 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
2588 the signature of func.
2589 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
2590 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
2591 overloaded func with empty args error.
2593 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
2596 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
2597 R10_REG after sorry.
2599 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
2601 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
2602 Move before new caller, and add ".default" suffix.
2603 (get_suffixed_assembler_name): New.
2604 (make_resolver_func): Use get_suffixed_assembler_name.
2605 (aarch64_generate_version_dispatcher_body): Redo name mangling.
2607 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2610 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
2611 element from std::pair<unsigned int, char> to an unnamed struct.
2612 Adjust uses of tile range variable.
2614 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2616 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
2617 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
2619 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2622 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
2623 reset maxlen to sizetype maximum.
2625 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2627 PR tree-optimization/113736
2628 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
2629 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
2631 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2633 PR tree-optimization/113759
2634 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
2635 or from_unsignedN differs from properties of typeN, update typeN
2636 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
2637 uselessly convertible to typeN, convert it using fold_convert or
2638 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
2639 (convert_plusminus_to_widen): Likewise.
2641 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
2644 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
2645 vector structure modes correctly.
2647 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
2649 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
2652 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
2655 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
2656 (x86_function_profiler): Call x86_64_select_profile_regnum to
2657 get a scratch register for large model profiling.
2659 2024-02-05 Richard Ball <richard.ball@arm.com>
2661 * config/arm/arm.cc (arm_output_mi_thunk): Emit
2662 insn for bti_c when bti is enabled.
2664 2024-02-05 Xi Ruoyao <xry111@xry111.site>
2666 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
2669 2024-02-05 Xi Ruoyao <xry111@xry111.site>
2671 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
2672 (neg<mode>2): Change the mode iterator from MSA to IMSA because
2673 in FP arithmetic we cannot use (0 - x) for -x.
2674 (neg<mode>2): New define_insn to implement FP vector negation,
2675 using a bnegi instruction to negate the sign bit.
2677 2024-02-05 Richard Biener <rguenther@suse.de>
2679 PR tree-optimization/113707
2680 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
2681 checking the avail set treat out-of-region defines as
2684 2024-02-05 Richard Biener <rguenther@suse.de>
2686 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
2687 the default mode when building a pointer.
2689 2024-02-05 Jakub Jelinek <jakub@redhat.com>
2691 PR tree-optimization/113737
2692 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
2693 has just a single label, remove it and make single successor edge
2696 2024-02-05 Jakub Jelinek <jakub@redhat.com>
2699 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
2700 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
2703 2024-02-05 Richard Biener <rguenther@suse.de>
2706 * config/i386/i386-expand.cc
2707 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
2708 Use a new pseudo for the skipped number of bytes.
2710 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
2712 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
2713 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
2716 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
2718 * config/riscv/riscv.md: Include sifive-p400.md.
2719 * config/riscv/sifive-p400.md: New file.
2720 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
2721 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
2723 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
2724 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
2725 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
2727 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2729 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
2730 Add missing ":SI" to the match_operator.
2732 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2734 * config/xtensa/xtensa.md (SHI): New mode iterator.
2735 (2 split patterns related to constsynth):
2736 Change to also accept HImode operands.
2738 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
2740 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
2743 2024-02-04 Xi Ruoyao <xry111@xry111.site>
2745 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
2747 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
2748 (elmsgnbit): Likewise.
2749 (neg<mode:FVEC>2): New define_insn.
2750 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
2751 are now instantiated in simd.md.
2753 2024-02-04 Xi Ruoyao <xry111@xry111.site>
2755 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
2756 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
2759 2024-02-04 Li Wei <liwei@loongson.cn>
2761 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
2762 (loongarch_expand_vselect_vconcat): Ditto.
2763 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
2764 all 128-bit constant permutation situations.
2765 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
2766 (loongarch_is_imm_set_shuffle): Renamed function name.
2767 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
2768 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
2769 extract-even and extract-odd permutations.
2770 (loongarch_is_odd_extraction): Delete.
2771 (loongarch_is_even_extraction): Ditto.
2772 (loongarch_expand_vec_perm_const): Adjust.
2774 2024-02-03 Jakub Jelinek <jakub@redhat.com>
2776 PR middle-end/113722
2777 * wide-int.cc (wi::bswap_large): Rename third argument from
2778 len to xlen and adjust use in safe_uhwi. Add len variable, set
2779 it to BLOCKS_NEEDED (precision) and use it for clearing of val
2780 and as canonize argument. Clear val using memset instead of
2783 2024-02-03 Jakub Jelinek <jakub@redhat.com>
2785 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
2786 mmi.preferred_base + mmi.size - sizeof (void *).
2788 2024-02-03 Xi Ruoyao <xry111@xry111.site>
2790 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
2791 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
2792 the ODR-violating locale declaration.
2794 2024-02-02 Tamar Christina <tamar.christina@arm.com>
2796 PR tree-optimization/113588
2797 PR tree-optimization/113467
2798 * tree-vect-data-refs.cc
2799 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
2800 (vect_analyze_early_break_dependences): Update comments.
2802 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
2805 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
2806 and PA_BUILTIN_SET_FPSR builtins.
2807 * (pa_builtins_icode): Declare.
2808 * (def_builtin, pa_fpu_init_builtins): New.
2809 * (pa_init_builtins): Initialize FPU builtins.
2810 * (pa_builtin_decl, pa_expand_builtin_1): New.
2811 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
2812 PA_BUILTIN_SET_FPSR builtins.
2813 * (pa_atomic_assign_expand_fenv): New.
2814 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
2816 (get_fpsr, put_fpsr): New expanders.
2817 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
2820 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2823 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
2825 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
2827 * doc/extend.texi (Common Type Attributes): Fix typo in
2828 description of hardbool.
2830 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2832 PR tree-optimization/113692
2833 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
2834 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
2837 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2839 PR middle-end/113699
2840 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
2841 uninitialized large/huge _BitInt SSA_NAME inputs.
2843 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2845 PR middle-end/113705
2846 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
2847 around wi::to_wide in order to compare value in prec precision.
2849 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
2852 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2854 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2856 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2858 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2860 2024-02-02 Pan Li <pan2.li@intel.com>
2862 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
2863 (riscv_pass_by_reference): Ditto.
2864 (riscv_fntype_abi): Ditto.
2866 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2868 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
2869 (pre_vsetvl::cleaup): Remove vsetvl_pre.
2870 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
2872 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
2874 * config/loongarch/larchintrin.h
2875 (__frecipe_s): Update function return type.
2876 (__frecipe_d): Ditto.
2877 (__frsqrte_s): Ditto.
2878 (__frsqrte_d): Ditto.
2880 2024-02-02 Li Wei <liwei@loongson.cn>
2882 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
2883 (loongarch_vector_costs::add_stmt_cost): Adjust.
2885 2024-02-02 Xi Ruoyao <xry111@xry111.site>
2887 * config/loongarch/loongarch.md (unspec): Add
2888 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
2889 (la_pcrel64_two_parts): New define_insn.
2890 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
2891 typo in the comment.
2892 (loongarch_call_tls_get_addr): If -mcmodel=extreme
2893 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
2894 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
2895 note to allow CSE addressing __tls_get_addr.
2896 (loongarch_legitimize_tls_address): If -mcmodel=extreme
2897 -mexplicit-relocs={always,auto}, address TLS IE symbols with
2898 la_pcrel64_two_parts.
2899 (loongarch_split_symbol): If -mcmodel=extreme
2900 -mexplicit-relocs={always,auto}, address symbols with
2901 la_pcrel64_two_parts.
2902 (loongarch_output_mi_thunk): Clean up unreachable code. If
2903 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
2904 thunks with la_pcrel64_two_parts.
2906 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2908 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
2909 Add support for call36.
2911 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2913 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
2914 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
2915 the macro instruction loading symbol address is not applicable.
2916 (loongarch_call_tls_get_addr): Adjust code.
2917 (loongarch_legitimize_tls_address): Likewise.
2919 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2921 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
2922 Add function declaration.
2923 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
2924 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
2926 (loongarch_load_tls): Added macro support in extreme mode.
2927 (loongarch_call_tls_get_addr): Likewise.
2928 (loongarch_legitimize_tls_address): Likewise.
2929 (loongarch_force_address): Likewise.
2930 (loongarch_legitimize_move): Likewise.
2931 (loongarch_output_mi_thunk): Likewise.
2932 (loongarch_option_override_internal): Remove the code that detects
2933 explicit relocs status.
2934 (loongarch_handle_model_attribute): Likewise.
2935 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
2936 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
2937 (symbolic_off64_or_reg_operand): Likewise.
2939 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2941 * config/loongarch/loongarch.cc (loongarch_load_tls):
2942 Load all types of tls symbols through one function.
2943 (loongarch_got_load_tls_gd): Delete.
2944 (loongarch_got_load_tls_ld): Delete.
2945 (loongarch_got_load_tls_ie): Delete.
2946 (loongarch_got_load_tls_le): Delete.
2947 (loongarch_call_tls_get_addr): Modify the called function name.
2948 (loongarch_legitimize_tls_address): Likewise.
2949 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
2950 (@load_tls<mode>): New template.
2951 (@got_load_tls_ld<mode>): Delete.
2952 (@got_load_tls_le<mode>): Delete.
2953 (@got_load_tls_ie<mode>): Delete.
2955 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2957 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
2958 (loongarch_legitimize_address): Add logical transformation code.
2960 2024-02-01 Marek Polacek <polacek@redhat.com>
2962 * doc/invoke.texi: Update -Wdangling-reference documentation.
2964 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
2967 * config/i386/i386.md (*cmp<dwi>_doubleword):
2968 Do not force SUBREG pieces to pseudos.
2970 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
2972 * config/pa/pa.md (atomic_storedi_1): Fix bug in
2975 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
2977 * config/avr/avr.cc: Tabify.
2979 2024-02-01 Richard Ball <richard.ball@arm.com>
2981 PR tree-optimization/111268
2982 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
2983 Add variable-length check for vector input arguments
2986 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2988 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
2989 hard-code number of SGPR/VGPR/AVGPR registers.
2990 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
2991 SGPR/VGPR/AVGPR registers.
2993 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
2995 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
2996 attribute, and include sifive-p600.md.
2997 * config/riscv/generic-ooo.md: Update type attribute.
2998 * config/riscv/generic.md: Update type attribute.
2999 * config/riscv/sifive-7.md: Update type attribute.
3000 * config/riscv/sifive-p600.md: New file.
3001 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3002 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3004 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
3005 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3006 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
3008 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
3010 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
3011 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
3012 * config/riscv/riscv.opt: New macro for 7 new unprivileged
3014 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
3015 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
3017 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3019 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
3020 -static-libasan. Add missing whitespace.
3022 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3024 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
3025 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
3026 Don't 'define_constants'.
3028 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3030 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
3032 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3034 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
3035 [TARGET_RDNA3]: Adjust.
3037 2024-02-01 Richard Biener <rguenther@suse.de>
3039 PR tree-optimization/113693
3040 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
3041 data when available.
3043 2024-02-01 Jakub Jelinek <jakub@redhat.com>
3044 Jason Merrill <jason@redhat.com>
3047 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
3048 on variables which were promoted to TREE_STATIC.
3050 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
3051 Richard Biener <rguenther@suse.de>
3054 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
3055 information via tree_non_zero_bits to check if this operand
3056 is suitably extended for a widening (or highpart) multiplication.
3057 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
3058 isn't already of the claimed type.
3060 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3063 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3065 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3066 (generic_ooo_branch): ditto
3067 * config/riscv/generic.md (generic_sfb_alu): ditto
3068 (generic_fmul_half): ditto
3069 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3070 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3071 (sifive_7_popcount): ditto
3072 * config/riscv/vector.md: change rdfrm to fmove
3073 * config/riscv/zc.md: change pushpop to load/store
3075 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3078 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3079 Robin Dapp <rdapp.gcc@gmail.com>
3081 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3082 (generic_ooo_vec_load): ditto
3083 (generic_ooo_vec_store): ditto
3084 (generic_ooo_vec_loadstore_seg): ditto
3085 (generic_ooo_vec_alu): ditto
3086 (generic_ooo_vec_fcmp): ditto
3087 (generic_ooo_vec_imul): ditto
3088 (generic_ooo_vec_fadd): ditto
3089 (generic_ooo_vec_fmul): ditto
3090 (generic_ooo_crypto): ditto
3091 (generic_ooo_perm): ditto
3092 (generic_ooo_vec_reduction): ditto
3093 (generic_ooo_vec_ordered_reduction): ditto
3094 (generic_ooo_vec_idiv): ditto
3095 (generic_ooo_vec_float_divsqrt): ditto
3096 (generic_ooo_vec_mask): ditto
3097 (generic_ooo_vec_vesetvl): ditto
3098 (generic_ooo_vec_setrm): ditto
3099 (generic_ooo_vec_readlen): ditto
3100 * config/riscv/riscv.md: include generic-vector-ooo
3101 * config/riscv/generic-vector-ooo.md: New file. to here
3103 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3106 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3108 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3110 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3112 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3114 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3115 Robin Dapp <rdapp.gcc@gmail.com>
3117 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3118 (generic_ooo_vec_load): ditto
3119 (generic_ooo_vec_store): ditto
3120 (generic_ooo_vec_loadstore_seg): ditto
3121 (generic_ooo_vec_alu): ditto
3122 (generic_ooo_vec_fcmp): ditto
3123 (generic_ooo_vec_imul): ditto
3124 (generic_ooo_vec_fadd): ditto
3125 (generic_ooo_vec_fmul): ditto
3126 (generic_ooo_crypto): ditto
3127 (generic_ooo_perm): ditto
3128 (generic_ooo_vec_reduction): ditto
3129 (generic_ooo_vec_ordered_reduction): ditto
3130 (generic_ooo_vec_idiv): ditto
3131 (generic_ooo_vec_float_divsqrt): ditto
3132 (generic_ooo_vec_mask): ditto
3133 (generic_ooo_vec_vesetvl): ditto
3134 (generic_ooo_vec_setrm): ditto
3135 (generic_ooo_vec_readlen): ditto
3136 * config/riscv/riscv.md: include generic-vector-ooo
3137 * config/riscv/generic-vector-ooo.md: New file. to here
3139 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3141 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3142 (generic_ooo_branch): ditto
3143 * config/riscv/generic.md (generic_sfb_alu): ditto
3144 (generic_fmul_half): ditto
3145 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3146 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3147 (sifive_7_popcount): ditto
3148 * config/riscv/vector.md: change rdfrm to fmove
3149 * config/riscv/zc.md: change pushpop to load/store
3151 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
3154 * config/aarch64/aarch64-simd.md (split for movv8di):
3155 For strict aligned mode, use DImode instead of TImode.
3157 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
3159 PR middle-end/113607
3160 * match.pd: Make sure else values match when folding a
3161 vec_cond into a conditional operation.
3163 2024-01-31 Marek Polacek <polacek@redhat.com>
3165 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
3167 2024-01-31 Tamar Christina <tamar.christina@arm.com>
3168 Matthew Malcomson <matthew.malcomson@arm.com>
3171 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
3173 * builtins.cc (expand_builtin): Include HWASAN when checking for
3176 2024-01-31 Richard Biener <rguenther@suse.de>
3178 PR middle-end/110176
3179 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
3180 to match INTEGER_CST only without outstanding conversion.
3182 2024-01-31 Alex Coplan <alex.coplan@arm.com>
3185 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
3186 V16QImode for the full 16-byte FPR saves in the vector PCS case.
3188 2024-01-31 Richard Biener <rguenther@suse.de>
3190 PR tree-optimization/111444
3191 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
3192 vn_reference_lookup_2 when optimistically skipping may-defs.
3194 2024-01-31 Richard Biener <rguenther@suse.de>
3196 PR tree-optimization/113630
3197 * tree-ssa-pre.cc (compute_avail): Avoid registering a
3198 reference with a representation with not matching base
3201 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3203 PR rtl-optimization/113656
3204 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
3205 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
3207 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3210 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
3211 with BLKmode are larger than DWARF2_ADDR_SIZE.
3213 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3215 PR tree-optimization/113639
3216 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
3217 For VIEW_CONVERT_EXPR set rhs1 to its operand.
3219 2024-01-31 Richard Biener <rguenther@suse.de>
3221 PR tree-optimization/113670
3222 * tree-vect-data-refs.cc (vect_check_gather_scatter):
3223 Make sure we can take the address of the reference base.
3225 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
3227 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
3228 ATA5835, ATtiny64AUTO, ATA5700M322.
3229 * doc/avr-mmcu.texi: Rebuild.
3231 2024-01-31 Alexandre Oliva <oliva@adacore.com>
3234 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
3237 2024-01-31 Alexandre Oliva <oliva@adacore.com>
3239 PR middle-end/112917
3240 PR middle-end/113100
3241 * builtins.cc (expand_builtin_stack_address): Use
3242 STACK_ADDRESS_OFFSET.
3243 * doc/extend.texi (__builtin_stack_address): Adjust.
3244 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
3245 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
3246 * doc/tm.texi: Rebuilt.
3248 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3251 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
3252 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
3253 (pre_vsetvl::compute_transparent): New function.
3254 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
3256 2024-01-30 Fangrui Song <maskray@google.com>
3259 * config/i386/constraints.md: Define constraint "Ws".
3260 * doc/md.texi: Document it.
3262 2024-01-30 Marek Polacek <polacek@redhat.com>
3266 * doc/invoke.texi: Update -Wdangling-reference description.
3268 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3270 * config/xtensa/constraints.md (R, T, U):
3271 Change define_constraint to define_memory_constraint.
3272 * config/xtensa/predicates.md (move_operand): Don't check that a
3273 constant pool operand size is a multiple of UNITS_PER_WORD.
3274 * config/xtensa/xtensa.cc
3275 (xtensa_lra_p, TARGET_LRA_P): Remove.
3276 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
3277 clause as it can no longer be true.
3278 (fixup_subreg_mem): Drop function.
3279 (xtensa_output_integer_literal_parts): Consider 16-bit wide
3281 (xtensa_legitimate_constant_p): Add short-circuit path for
3282 integer load instructions. Don't check that mode size is
3283 at least UNITS_PER_WORD.
3284 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
3285 rather reload_in_progress and reload_completed.
3286 (doloop_end): Drop operand 2.
3287 (movhi_internal): Add alternative loading constant from a
3289 (define_split for DI register_operand): Don't limit to
3290 !TARGET_AUTO_LITPOOLS.
3291 * config/xtensa/xtensa.opt (mlra): Change to no effect.
3293 2024-01-30 Pan Li <pan2.li@intel.com>
3295 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
3296 calculate the gpr count required by vls mode.
3297 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
3298 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
3300 (riscv_get_arg_info): Add vls mode handling.
3301 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
3303 2024-01-30 Richard Biener <rguenther@suse.de>
3305 PR tree-optimization/113659
3306 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3307 Handle main exit without virtual use.
3309 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
3311 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
3313 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
3316 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
3317 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
3318 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
3319 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
3320 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
3321 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
3323 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
3326 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
3327 Mark all registers that occur in addresses as needing a GPR.
3329 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
3332 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
3333 the containing insn as an extra parameter. Reset debug instructions
3334 if they reference a register that is no longer used by real insns.
3335 (early_ra::apply_allocation): Update calls accordingly.
3337 2024-01-30 Jakub Jelinek <jakub@redhat.com>
3339 PR tree-optimization/113603
3340 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
3341 count_nonzero_bytes call refetch si using get_strinfo in case it
3342 has been unshared in the meantime.
3344 2024-01-30 Jakub Jelinek <jakub@redhat.com>
3346 PR middle-end/101195
3347 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
3348 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
3350 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
3352 * config/riscv/thead.cc (th_print_operand_address): Change %ld
3355 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
3356 Manolis Tsamis <manolis.tsamis@vrull.eu>
3357 Philipp Tomsich <philipp.tomsich@vrull.eu>
3359 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
3360 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
3362 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
3363 Call on framework moved later.
3365 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
3367 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
3368 instruction in naked function epilogues.
3370 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
3373 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
3374 gcc_cv_as_mips_explicit_relocs.
3375 * configure: Regnerated.
3377 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
3380 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
3381 Correct generated RTL.
3382 (arm_rev16si2_alt1): Correctly handle conditional execution.
3383 (arm_rev16si2_alt2): Likewise.
3385 2024-01-29 Richard Biener <rguenther@suse.de>
3387 PR middle-end/113622
3388 * expr.cc (expand_assignment): Spill hard registers if
3389 we index them with a variable offset.
3391 2024-01-29 Richard Biener <rguenther@suse.de>
3393 PR middle-end/113622
3394 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
3395 Also allow DECL_HARD_REGISTER variables.
3397 2024-01-29 Alex Coplan <alex.coplan@arm.com>
3400 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
3401 Use iterate_safely when iterating over debug uses.
3402 (fixup_debug_uses): Likewise.
3403 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
3404 over nondebug insns instead of manually maintaining the next insn.
3405 * iterator-utils.h (class safe_iterator): New.
3406 (iterate_safely): New.
3408 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
3411 * config/i386/i386-options.cc (ix86_set_func_type): Save
3412 callee-saved registers in noreturn functions for -O0/-Og.
3414 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3417 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
3418 define for !TARGET_RDNA2_PLUS.
3420 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
3423 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
3424 workaround for right shifts.
3425 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
3426 (vect_determine_precisions_from_range): Be more selective about
3427 which codes can be narrowed based on their input and output ranges.
3428 For shifts, require at least one more bit of precision than the
3429 maximum shift amount.
3431 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3433 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
3435 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3437 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
3438 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
3441 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3444 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
3445 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
3446 (SET_SRAM_ECC_UNSET): ... this.
3447 (copy_early_debug_info): Remove gfx900 special case, now handled as
3448 part of the generic handling.
3449 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
3451 2024-01-29 Jakub Jelinek <jakub@redhat.com>
3453 PR tree-optimization/110603
3454 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
3455 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
3456 overwritten anyway). Avoid creating invalid range with minlen
3457 larger than maxlen. Formatting fix.
3459 2024-01-29 Richard Biener <rguenther@suse.de>
3462 * tree-inline.cc (initialize_inlined_parameters): Reverse
3463 the decl chain of inlined parameters.
3465 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
3467 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
3468 alignment of CFString constants by setting DECL_USER_ALIGN.
3470 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
3471 Jakub Jelinek <jakub@redhat.com>
3474 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
3475 and BUILT_IN_GCC_NESTED_PTR_DELETED.
3476 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
3477 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
3478 rename the library fallbacks to __gcc_nested_func_ptr_created and
3479 __gcc_nested_func_ptr_deleted.
3480 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
3481 and __gcc_nested_func_ptr_deleted.
3482 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
3483 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
3484 * tree.cc (build_common_builtin_nodes): Build the
3485 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
3486 builtins only for non-explicit.
3488 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
3490 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
3492 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
3495 * config/i386/i386-options.cc (ix86_set_func_type): Don't
3496 save and restore callee saved registers for a noreturn function
3497 with nothrow or compiled with -fno-exceptions.
3499 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
3503 * config/i386/i386-expand.cc (ix86_expand_call): Replace
3504 no_caller_saved_registers check with call_saved_registers check.
3505 Clobber all registers that are not used by the callee with
3506 no_callee_saved_registers attribute.
3507 * config/i386/i386-options.cc (ix86_set_func_type): Set
3508 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
3509 noreturn function. Disallow no_callee_saved_registers with
3510 interrupt or no_caller_saved_registers attributes together.
3511 (ix86_set_current_function): Replace no_caller_saved_registers
3512 check with call_saved_registers check.
3513 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
3514 (ix86_handle_call_saved_registers_attribute): This.
3515 (ix86_gnu_attributes): Add
3516 ix86_handle_call_saved_registers_attribute.
3517 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
3518 no_caller_saved_registers check with call_saved_registers check.
3519 (ix86_function_ok_for_sibcall): Don't allow callee with
3520 no_callee_saved_registers attribute when the calling function
3521 has callee-saved registers.
3522 (ix86_comp_type_attributes): Also check
3523 no_callee_saved_registers.
3524 (ix86_epilogue_uses): Replace no_caller_saved_registers check
3525 with call_saved_registers check.
3526 (ix86_hard_regno_scratch_ok): Likewise.
3527 (ix86_save_reg): Replace no_caller_saved_registers check with
3528 call_saved_registers check. Don't save any registers for
3529 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
3530 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
3531 no_callee_saved_registers attribute is called.
3532 (find_drap_reg): Replace no_caller_saved_registers check with
3533 call_saved_registers check.
3534 * config/i386/i386.h (call_saved_registers_type): New enum.
3535 (machine_function): Replace no_caller_saved_registers with
3536 call_saved_registers.
3537 * doc/extend.texi: Document no_callee_saved_registers attribute.
3539 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3541 PR tree-optimization/113614
3542 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
3543 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
3544 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
3546 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3548 PR tree-optimization/113568
3549 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
3550 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
3551 in the widening extension checks.
3553 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3555 * gimple-lower-bitint.cc (gimple_lower_bitint): For
3556 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
3558 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
3560 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
3561 the warning for an attribute-always_inline without inline declaration.
3563 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
3566 * genopinit.cc (main): Split init_all_optabs into functions
3567 of 1000 patterns each.
3569 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
3571 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
3573 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
3574 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
3577 2024-01-26 Andrew Stubbs <ams@baylibre.com>
3579 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
3580 * config/gcn/gcn-valu.md (all_convert): New iterator.
3581 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
3582 define_expand, and rename the old one to ...
3583 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
3584 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
3585 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
3586 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
3587 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
3588 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
3589 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
3590 (<u>mulqihi3_scalar): Likewise.
3592 2024-01-26 Richard Biener <rguenther@suse.de>
3594 PR tree-optimization/113602
3595 * tree-data-ref.cc (dr_analyze_innermost): Fail when
3596 the base object isn't addressable.
3598 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
3600 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
3601 "--amdhsa-code-object-version=" argument.
3602 (ASM_SPEC): Use it; replace previous version of it.
3604 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3606 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
3607 (pre_vsetvl::emit_vsetvl): Ditto.
3609 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
3611 * config/loongarch/lasx.md (vec_extract<mode>_0):
3612 New define_insn_and_split patten.
3614 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
3616 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
3618 2024-01-26 Li Wei <liwei@loongson.cn>
3620 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
3622 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3625 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
3627 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
3630 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
3631 undefined shift after the call to exact_log2.
3633 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
3636 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
3637 before taking the negative of it.
3639 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
3642 * lra-constraints.cc (curr_insn_transform): Change class even for
3643 spilled pseudo successfully matched with with NO_REGS.
3645 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
3648 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
3650 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
3653 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
3654 (aarch64_expand_epilogue): Use the new function.
3655 (aarch64_split_compare_and_swap): Likewise.
3656 (aarch64_split_atomic_op): Likewise.
3658 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
3660 PR middle-end/112971
3661 * fold-const.cc (simplify_const_binop): New function for binop
3662 simplification of two constant vectors when element-wise
3663 handling is not necessary.
3664 (const_binop): Call new function.
3666 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
3668 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
3669 * config/riscv/constraints.md: Likewise.
3670 * config/riscv/corev.def: Likewise.
3671 * config/riscv/corev.md: Likewise.
3672 * config/riscv/predicates.md: Likewise.
3673 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
3674 * config/riscv/riscv-ftypes.def: Likewise.
3675 * config/riscv/riscv.opt: Likewise.
3676 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
3677 * doc/extend.texi: Add XCVbitmanip builtin documentation.
3678 * doc/sourcebuild.texi: Likewise.
3680 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
3682 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
3684 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
3687 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
3688 (riscv_fntype_abi): Ditto.
3689 * config/riscv/riscv.opt: Ditto.
3691 2024-01-25 Jakub Jelinek <jakub@redhat.com>
3693 PR middle-end/113574
3694 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
3695 count against TYPE_PRECISION rather than TYPE_SIZE.
3697 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3700 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
3701 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
3703 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3706 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
3707 whether each split instruction is a load that clobbers the source
3708 address. Emit that instruction last if so.
3710 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3713 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
3715 (<optab><Vnarrowq><mode>2): Use it instead of generating a
3716 paradoxical subreg for the input.
3718 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3720 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
3721 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
3722 predecessors dump information.
3724 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3726 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
3727 redundant full available computation.
3728 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3730 2024-01-25 Jakub Jelinek <jakub@redhat.com>
3732 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
3733 * doc/rtl.texi (CONST_VECTOR): Likewise.
3735 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3737 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
3738 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
3739 (pass_vsetvl::execute): Ditto.
3740 * config/riscv/riscv.opt: Ditto.
3742 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
3744 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
3745 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
3747 2024-01-25 Richard Biener <rguenther@suse.de>
3749 PR tree-optimization/113576
3750 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
3751 exits with may_be_zero niters when its the last one.
3753 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
3755 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3756 For symbols of type tls, non-zero Offset is not generated.
3758 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
3760 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
3761 P9 with m32 and mpowerpc64.
3763 2024-01-25 liuhongt <hongtao.liu@intel.com>
3765 * config/i386/i386-options.cc (ix86_option_override_internal):
3766 Enable -mlam=u57 by default when compiled with
3767 -fsanitize=hwaddress.
3769 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
3771 * common/config/riscv/riscv-common.cc (riscv_implied_info):
3772 Remove {"ztso", "a"}.
3774 2024-01-24 Martin Jambor <mjambor@suse.cz>
3778 * cgraph.h (cgraph_edge): Add a parameter to
3779 redirect_call_stmt_to_callee.
3780 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
3781 parameter to modify_call.
3782 (ipa_release_ssas_in_hash): Declare.
3783 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
3784 parameter killed_ssas, pass it to padjs->modify_call.
3785 * ipa-param-manipulation.cc (purge_all_uses): New function.
3786 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
3787 Instead of substituting uses, invoke purge_all_uses. If
3788 hash of killed SSAs has not been provided, create a temporary one
3789 and release SSAs that have been added to it.
3790 (compare_ssa_versions): New function.
3791 (ipa_release_ssas_in_hash): Likewise.
3792 * tree-inline.cc (redirect_all_calls): Create
3793 id->killed_new_ssa_names earlier, pass it to edge redirection,
3795 (copy_body): Release SSAs in id->killed_new_ssa_names.
3797 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
3800 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
3801 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
3803 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
3806 * config/riscv/sfb.md: New splitters to rewrite single bit
3807 sign extension as the condition to SFB instructions.
3809 2024-01-24 Jan Hubicka <jh@suse.cz>
3812 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
3813 (fmin-function-alignment): New parameter.
3814 * doc/invoke.texi: (-fmin-function-alignment): Document.
3815 (-falign-functions,-falign-loops,-falign-labels): Mention that
3816 aglinments are ignored in cold code.
3817 * varasm.cc (assemble_start_function): Handle min-function-alignment.
3819 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3822 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
3824 * config/aarch64/iterators.md (VQDIV): Remove.
3825 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
3826 SVE_I_SIMD_DI): New.
3827 (VPRED, sve_lane_con): Add V4SI and V2DI.
3828 * config/aarch64/aarch64-sve.md (<optab><mode>3,
3829 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
3830 (mul<mode>3): New, split from <optab><mode>3.
3831 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
3832 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
3833 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
3834 SVE_FULL_HSDI_SIMD_DI.
3836 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3838 PR tree-optimization/113552
3839 * config/aarch64/aarch64.cc
3840 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
3842 2024-01-24 Martin Jambor <mjambor@suse.cz>
3845 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
3846 count is equal or greater than the limit. Use the limit from the
3849 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
3851 * configure.ac: Detect the explicit relocs support for
3852 mips, and define C macro MIPS_EXPLICIT_RELOCS.
3853 * config.in: Regenerated.
3854 * configure: Regenerated.
3855 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
3856 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
3857 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
3858 !TARGET_EXPLICIT_RELOCS instead of just set it.
3859 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
3860 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
3861 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
3862 and define -m(no-)explicit-relocs as aliases.
3864 2024-01-24 Alex Coplan <alex.coplan@arm.com>
3866 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
3868 (-mlate-ldp-fusion): Likewise.
3870 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3872 * tree-vect-loop.cc (vect_get_vect_def,
3873 vect_create_epilog_for_reduction): Rename main_exit_p to
3876 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3878 PR tree-optimization/113364
3879 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
3880 early exits then we must reduce from the first offset for all of them.
3882 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3885 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
3887 (get_bb_index): Ditto.
3888 (pre_vsetvl::compute_avl_def_data): Ditto.
3889 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
3890 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3892 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
3893 Richard Sandiford <richard.sandiford@arm.com>
3896 * ccmp.cc (ccmp_candidate_p): Add outer argument.
3897 Allow if the outer is true and the lhs is used more
3899 (expand_ccmp_expr): Update call to ccmp_candidate_p.
3900 * expr.h (expand_expr_real_gassign): Declare.
3901 * expr.cc (expand_expr_real_gassign): New function, split out from...
3902 (expand_expr_real_1): ...here.
3903 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
3905 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3908 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
3909 (fixup_debug_use): New.
3910 (fixup_debug_uses_trailing_add): New.
3911 (fixup_debug_uses): New. Use it ...
3912 (ldp_bb_info::fuse_pair): ... here.
3913 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
3914 fix up debug uses of the base register that are affected by
3915 folding in the trailing add insn.
3917 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3920 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
3921 Update trailing nondebug uses of the base register in the case
3922 of cancelling writeback.
3924 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3927 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
3928 (debug_insn_use_iterator): New.
3929 (set_info::first_debug_insn_use): New.
3930 (set_info::debug_insn_uses): New.
3931 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
3932 (set_info::first_debug_insn_use): New.
3933 (set_info::debug_insn_uses): New.
3935 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3938 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
3939 Don't record hazards against the opposite insn in the pair.
3941 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3944 * config/aarch64/aarch64-ldp-fusion.cc
3945 (struct stp_change_builder): New.
3946 (decide_stp_strategy): Reanme to ...
3947 (try_repurpose_store): ... this.
3948 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
3949 construct stp changes. Fix up uses when inserting new stp insns.
3951 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3954 * rtl-ssa.h: Include hash-set.h.
3955 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
3956 new_sets parameter and use it to keep track of new user-created sets.
3957 (function_info::apply_changes_to_insn): Also call add_def on new sets.
3958 (function_info::change_insns): Add hash_set to keep track of new
3959 user-created defs. Plumb it through.
3960 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
3961 apply_changes_to_insn.
3963 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3966 * rtl-ssa/accesses.cc (function_info::create_use): New.
3967 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
3968 Ensure new uses end up referring to permanent defs.
3969 * rtl-ssa/functions.h (function_info::create_use): Declare.
3971 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3974 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
3975 to finalize_new_accesses from the backwards placement loop, run it
3976 forwards in a separate loop.
3978 2024-01-23 Richard Biener <rguenther@suse.de>
3980 PR tree-optimization/113552
3981 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
3982 floor_log2 instead of exact_log2 on the number of calls.
3984 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
3985 Jakub Jelinek <jakub@redhat.com>
3987 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
3990 2024-01-23 Richard Biener <rguenther@suse.de>
3992 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3993 Separate single and multi-exit case when creating PHIs between
3994 the main and epilogue.
3996 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
3999 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
4000 MODE_single variants of functions that don't take tuple arguments.
4002 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4005 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
4006 Don't assert recog success, just punt if the writeback pair
4009 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4011 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
4012 ATTRIBUTE_UNUSED to decl.
4014 2024-01-23 Richard Biener <rguenther@suse.de>
4017 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
4018 handle unexpected but bogus DIE contexts when not checking
4021 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4023 PR tree-optimization/113462
4024 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
4025 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
4026 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
4027 sizes between 129 and 8192 bytes.
4029 2024-01-23 Xi Ruoyao <xry111@xry111.site>
4031 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
4032 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
4033 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
4034 (loongarch_call_tls_get_addr): Do not split symbols of
4035 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
4036 EXPLICIT_RELOCS_AUTO.
4038 2024-01-23 Richard Biener <rguenther@suse.de>
4040 * alias.cc (known_base_value_p): Remove.
4041 (find_base_value): Remove PLUS/MINUS handling
4042 when both operands are not CONST_INT_P.
4044 2024-01-23 Richard Biener <rguenther@suse.de>
4046 PR rtl-optimization/113255
4047 * alias.cc (find_base_term): Remove PLUS/MINUS handling
4048 when both operands are not CONST_INT_P.
4050 2024-01-23 Richard Biener <rguenther@suse.de>
4053 * dwarf2out.cc (dwarf2out_finish): Reset all type units
4054 for the fat part of an LTO compile.
4056 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
4058 * doc/sourcebuild.texi: Add attributes for keywords.
4060 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
4063 * doc/invoke.texi (Warning Options): Correct lists of options
4064 enabled by -Wall and -Wextra by checking against common.opt
4067 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
4070 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
4071 instead of cpu_optaliases.
4072 (check_arch): Use arch_opt_alias instead of arch_optaliases.
4074 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4076 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
4077 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
4078 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
4080 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4083 * config/riscv/riscv.md: Use reg instead of subreg.
4085 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
4088 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
4089 to match the compiler default.
4090 (simple_object_copy_lto_debug_sections): Never unlink the outfile
4091 on error as the caller does so.
4092 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
4093 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
4095 2024-01-22 Richard Biener <rguenther@suse.de>
4097 PR tree-optimization/113373
4098 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4099 Create LC PHIs in the exit blocks where necessary.
4100 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
4101 to handle missing LC PHIs.
4102 (find_connected_edge): Remove.
4103 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
4105 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4107 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
4109 2024-01-22 xuli <xuli1@eswincomputing.com>
4112 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
4113 (registered_function::overloaded_hash):refactor.
4114 (resolve_overloaded_builtin):avoid internal ICE.
4116 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
4120 * calls.cc (emit_library_call_value_1): Pass valid TYPE
4122 * expr.cc (emit_push_insn): Likewise.
4124 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
4126 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
4127 correcction version of last change.
4129 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
4131 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
4132 fix bugs in signature.
4134 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
4135 Richard Biener <rguenther@suse.de>
4137 PR rtl-optimization/111267
4138 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
4139 profitable_p method to likely_profitable_p.
4140 (try_fwprop_subst_node): Update call to likely_profitable_p.
4141 Only bail-out early when !prop.likely_profitable_p for instructions
4142 that are not single sets. When comparing costs, bail-out if the
4143 cost is unchanged and !prop.likely_profitable_p.
4145 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
4148 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
4149 isn't enabled by -Wunused unless -Wextra is provided, and that
4150 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
4151 -Wunused doesn't enable -Wunused-* options documented as behaving
4152 otherwise, and list them explicitly.
4154 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
4157 * doc/invoke.texi (Warning Options): Fix broken example and
4158 clean up/reorganize the others. Also describe what the short-form
4161 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
4164 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
4165 (Warning Options): Correct/edit discussion of -Warray-parameter
4166 to make the first example less confusing, and fill in missing info.
4168 2024-01-20 Jakub Jelinek <jakub@redhat.com>
4170 PR tree-optimization/113462
4171 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
4172 Handle rhs1 INTEGER_CST like SSA_NAME.
4174 2024-01-20 Jakub Jelinek <jakub@redhat.com>
4176 PR tree-optimization/113491
4177 * tree-switch-conversion.cc (switch_conversion::build_constructors):
4178 If elt.index has precision higher than sizetype, fold_convert it to
4180 (switch_conversion::array_value_type): Return type if type is
4181 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
4182 (switch_conversion::build_arrays): Use unsigned_type_for rather than
4183 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
4184 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
4185 higher than sizetype, use sizetype as tidx type and fold_convert the
4186 subtraction to sizetype.
4188 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4190 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
4191 (riscv_vector_mode_supported_any_target_p): Ditto.
4193 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
4196 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
4197 (TARGET_ZERO_CALL_USED_REGS): Define.
4199 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
4202 * config/m68k/m68k.cc (output_andsi3): Use QImode for
4203 address adjusted for 1-byte RMW access.
4204 (output_iorsi3): Likewise.
4205 (output_xorsi3): Likewise.
4207 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4209 * doc/invoke.texi (RISC-V Options): Add list of supported
4212 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4215 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
4216 (RVV_VUNDEF): Ditto.
4217 * config/riscv/riscv-vsetvl.cc: Add timevar.
4219 2024-01-19 Richard Biener <rguenther@suse.de>
4222 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
4223 an early DIE but there should be, do not pretend there is.
4225 2024-01-19 Richard Biener <rguenther@suse.de>
4227 PR tree-optimization/113494
4228 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4229 Handle endless loop on exit. Handle re-allocated PHI.
4231 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4233 PR tree-optimization/113464
4234 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
4235 optimize loads into GIMPLE_ASM stmts.
4237 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4239 PR tree-optimization/113463
4240 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
4241 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
4244 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4246 PR tree-optimization/113459
4247 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
4248 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
4249 of SCALAR_INT_TYPE_MODE if type has BLKmode.
4250 (vn_reference_lookup_3): Likewise. Formatting fix.
4252 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4253 Richard Biener <rguenther@suse.de>
4255 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
4256 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
4257 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
4258 but adjust_address also for BLKmode mode and MEM op0.
4260 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
4262 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
4265 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4267 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
4269 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4271 * common/config/riscv/riscv-common.cc
4272 (riscv_subset_list::parse_std_ext): Remove.
4273 (riscv_subset_list::parse_multiletter_ext): Remove.
4274 * config/riscv/riscv-subset.h
4275 (riscv_subset_list::parse_std_ext): Remove.
4276 (riscv_subset_list::parse_multiletter_ext): Remove.
4278 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4280 * common/config/riscv/riscv-common.cc
4281 (riscv_subset_list::parse_single_std_ext): New parameter.
4282 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4283 (riscv_subset_list::parse_single_ext): Ditto.
4284 (riscv_subset_list::parse): Relax the order for the input of ISA
4286 * config/riscv/riscv-subset.h
4287 (riscv_subset_list::parse_single_std_ext): New parameter.
4288 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4289 (riscv_subset_list::parse_single_ext): Ditto.
4291 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4293 * common/config/riscv/riscv-common.cc
4294 (riscv_subset_list::parse_base_ext): New.
4295 (riscv_subset_list::parse): Extract part of logic into
4296 riscv_subset_list::parse_base_ext.
4297 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
4300 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4302 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
4305 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
4307 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
4310 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
4313 * doc/extend.texi (Common Variable Attributes): Explain what
4314 happens when multiple variables with cleanups are in the same scope.
4316 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4319 * doc/extend.texi (Common Function Attributes): Document that
4320 noinline also disables some interprocedural optimizations and
4321 improve flow to the part about using inline asm instead to
4322 disable calls from being optimized away completely. Remove the
4323 sentence that says noipa is mainly for internal compiler testing.
4325 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
4327 PR tree-optimization/69807
4328 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
4330 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
4333 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
4334 from x86 Windows Options.
4336 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4339 * doc/extend.texi (C Extensions): Add new section to menu.
4340 (Function Attributes): Move dangling index entries to....
4341 (Const and Volatile Functions): New section.
4343 2024-01-18 David Malcolm <dmalcolm@redhat.com>
4345 PR middle-end/112684
4346 * toplev.cc (toplev::main): Don't ICE in
4347 -fdiagnostics-generate-patch when exiting after options,
4348 since no edit context will have been created.
4350 2024-01-18 Richard Biener <rguenther@suse.de>
4352 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
4355 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4357 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
4358 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
4360 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4361 Jin Ma <jinma@linux.alibaba.com>
4362 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4363 Christoph Müllner <christoph.muellner@vrull.eu>
4365 * config/riscv/thead.cc
4366 (th_asm_output_opcode): Rewrite some instructions.
4368 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4369 Jin Ma <jinma@linux.alibaba.com>
4370 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4371 Christoph Müllner <christoph.muellner@vrull.eu>
4373 * config/riscv/riscv.md (none,thv,rvv): New attribute.
4374 (no,yes): Add an attribute to disable alternative
4375 for xtheadvector or RVV1.0.
4376 * config/riscv/vector.md:
4377 Disable alternatives that destination register overlaps
4378 source register group for xtheadvector.
4380 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4381 Jin Ma <jinma@linux.alibaba.com>
4382 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4383 Christoph Müllner <christoph.muellner@vrull.eu>
4385 * config/riscv/riscv-vector-builtins-bases.cc
4386 (class th_loadstore_width): Define new builtin bases.
4387 (class th_extract): Define new builtin bases.
4388 (BASE): Define new builtin bases.
4389 * config/riscv/riscv-vector-builtins-bases.h:
4390 Define new builtin class.
4391 * config/riscv/riscv-vector-builtins-shapes.cc
4392 (struct th_loadstore_width_def): Define new builtin shapes.
4393 (struct th_indexed_loadstore_width_def):
4394 Define new builtin shapes.
4395 (struct th_extract_def): Define new builtin shapes.
4396 (SHAPE): Define new builtin shapes.
4397 * config/riscv/riscv-vector-builtins-shapes.h:
4398 Define new builtin shapes.
4399 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
4400 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
4401 * config/riscv/riscv-vector-builtins.h
4402 (enum required_ext): Add new XTheadVector member.
4403 (struct function_group_info): Likewise.
4404 * config/riscv/t-riscv:
4405 Add thead-vector-builtins-functions.def
4406 * config/riscv/thead-vector.md
4407 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
4408 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
4409 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
4410 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
4411 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
4412 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
4413 (@pred_th_extract<mode>): Likewise.
4414 (*pred_th_extract<mode>): Likewise.
4415 * config/riscv/thead-vector-builtins-functions.def: New file.
4417 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4418 Jin Ma <jinma@linux.alibaba.com>
4419 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4420 Christoph Müllner <christoph.muellner@vrull.eu>
4422 * config.gcc: Add files for XTheadVector intrinsics.
4423 * config/riscv/autovec.md: Guard XTheadVector.
4424 * config/riscv/predicates.md: Disable immediate vl
4426 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
4427 Add pragma for XTheadVector.
4428 * config/riscv/riscv-string.cc (riscv_expand_block_move):
4430 * config/riscv/riscv-v.cc (vls_mode_valid_p):
4432 * config/riscv/riscv-vector-builtins-bases.cc:
4433 Do not normalize vsetvl instructions for XTheadVector.
4434 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
4435 New check type function.
4436 (build_one): Adjust for XTheadVector.
4437 * config/riscv/riscv-vector-switch.def (ENTRY):
4438 Disable fractional mode for the XTheadVector extension.
4439 (TUPLE_ENTRY): Likewise.
4440 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
4442 (riscv_preferred_simd_mode): Likewsie.
4443 (riscv_autovectorize_vector_modes): Likewise.
4444 (riscv_vector_mode_supported_any_target_p): Likewise.
4445 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
4446 * config/riscv/thead.cc (th_asm_output_opcode):
4447 Rewrite vsetvl instructions.
4448 * config/riscv/vector.md:
4449 Include thead-vector.md and change fractional LMUL
4451 * config/riscv/riscv_th_vector.h: New file.
4452 * config/riscv/thead-vector.md: New file.
4454 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4455 Jin Ma <jinma@linux.alibaba.com>
4456 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4457 Christoph Müllner <christoph.muellner@vrull.eu>
4459 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
4460 Add new function to add assembler insn code prefix/suffix.
4461 (th_asm_output_opcode):
4462 Add Thead function to add assembler insn code prefix/suffix.
4463 * config/riscv/riscv.cc (riscv_asm_output_opcode):
4464 Implement function to add assembler insn code prefix/suffix.
4465 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
4466 Add new function to add assembler insn code prefix/suffix.
4467 * config/riscv/thead.cc (th_asm_output_opcode):
4468 Implement Thead function to add assembler insn code
4471 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4472 Jin Ma <jinma@linux.alibaba.com>
4473 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4474 Christoph Müllner <christoph.muellner@vrull.eu>
4476 * common/config/riscv/riscv-common.cc
4477 (riscv_subset_list::parse): Add new vendor extension.
4478 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
4480 * config/riscv/riscv.opt: Add new mask.
4482 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4484 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
4485 to be conditional on macosx-version-min.
4487 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4489 * config/darwin.cc (darwin_objc1_section): Use the correct
4490 meta-data version for constant strings.
4491 (machopic_select_section): Assert if we fail to handle CFString
4492 sections as Obejctive-C meta-data or drectly.
4494 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4496 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
4497 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
4498 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
4499 versions when the object format is Mach-O.
4501 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4504 * config/darwin.cc (machopic_select_section): Handle C and C++
4506 (darwin_rename_builtins): Move this out of the CFString code.
4507 (darwin_libc_has_function): Likewise.
4508 (darwin_build_constant_cfstring): Create an anonymous var to
4510 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
4513 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
4516 * haifa-sched.cc (dep_list_size): Make global.
4517 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
4518 * sched-int.h (dep_list_size): Declare.
4520 2024-01-18 Martin Jambor <mjambor@suse.cz>
4522 PR tree-optimization/110422
4523 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
4526 2024-01-18 Richard Biener <rguenther@suse.de>
4528 PR tree-optimization/113475
4529 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
4530 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
4531 (phi_analyzer::~phi_analyzer): Deallocate and free collected
4533 (phi_analyzer::process_phi): Record allocated phi_groups.
4535 2024-01-18 Richard Biener <rguenther@suse.de>
4537 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
4538 storage for gvec_oprnds elements.
4540 2024-01-18 Richard Biener <rguenther@suse.de>
4542 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
4543 prefer all later exits we can handle.
4544 (vect_analyze_loop_form): Free the allocated loop body.
4547 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4549 * config/avr/avr-log.cc: Tabify.
4551 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4553 * config/riscv/autovec.md: Support vi variant.
4555 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4557 * config/avr/avr-devices.cc: Tabify.
4559 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4561 * config/avr/avr-c.cc: Tabify.
4563 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4565 * config/avr/driver-avr.cc: Tabify.
4567 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4569 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
4571 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4573 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
4575 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4577 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
4578 minline-strcmp, minline-strncmp, minline-strlen,
4579 -param=riscv-vector-abi): Remove Bool keywords.
4581 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4584 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
4585 support. Add missing space after , in emitted assembly in some
4586 cases. Formatting fixes.
4588 2024-01-18 Xi Ruoyao <xry111@xry111.site>
4590 * config/loongarch/loongarch.md (movsi_internal): Remove
4593 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4595 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
4596 in the diagnostic, and capitalize the device name.
4597 (print_mcu): Generate specs such that:
4598 <*check_rodata_in_ram>: New.
4599 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
4600 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
4601 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
4603 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4606 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
4607 Common and Optimization.
4609 2024-01-18 Richard Biener <rguenther@suse.de>
4611 PR tree-optimization/113431
4612 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
4613 When there is an invariant load we might not preserve
4616 2024-01-18 Richard Biener <rguenther@suse.de>
4618 PR tree-optimization/113374
4619 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
4620 * tree-vect-loop.cc (move_early_exit_stmts): Update
4622 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4623 Refactor. Preserve virtual LC PHIs on all exits.
4625 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
4627 * config/loongarch/loongarch.cc (loongarch_split_symbol):
4628 Assign the '/u' attribute to the mem.
4630 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4632 PR middle-end/110847
4633 * doc/invoke.texi (Option Summary): Document negative forms of
4634 -Wtsan and -Wxor-used-as-pow.
4635 (Warning Options): Likewise.
4637 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4640 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
4642 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4644 * doc/extend.texi (Common Function Attributes): Re-alphabetize
4646 (Common Variable Attributes): Likewise.
4647 (Common Type Attributes): Likewise.
4649 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4651 PR middle-end/111659
4652 * doc/extend.texi (Common Variable Attributes): Fix long lines
4653 in documentation of strict_flex_array + other minor copy-editing.
4654 Add a cross-reference to -Wstrict-flex-arrays.
4655 * doc/invoke.texi (Option Summary): Fix whitespace in tables
4656 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
4657 (C Dialect Options): Combine the docs for the two
4658 -fstrict-flex-arrays forms into a single entry. Note this option
4659 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
4660 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
4661 Minor copy-editing. Add cross references to the strict_flex_array
4662 attribute and -fstrict-flex-arrays option. Add note that this
4663 option depends on -ftree-vrp.
4665 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
4668 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
4669 only allow REG operands instead of allowing all.
4671 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
4673 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
4674 Remove redundant checks in else condition for readablity.
4675 (earliest_fuse_vsetvl_info) Print iteration count in debug
4677 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
4678 dump details in certain cases.
4680 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
4682 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
4683 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
4684 * config/riscv/riscv-vsetvl.cc
4685 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
4686 (pass_vsetvl::execute): Use vsetvl_strategy.
4688 2024-01-17 Jan Hubicka <jh@suse.cz>
4690 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
4691 accidental hack reseting offset.
4693 2024-01-17 Jan Hubicka <jh@suse.cz>
4695 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
4696 handling of X86_TUNE_AVOID_512FMA_CHAINS.
4698 2024-01-17 Jan Hubicka <jh@suse.cz>
4699 Jakub Jelinek <jakub@redhat.com>
4701 PR tree-optimization/110852
4702 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
4704 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
4705 PRED_COMBINED_VALUE_PREDICTIONS_PHI
4706 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
4707 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
4709 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4711 PR tree-optimization/113421
4712 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
4714 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
4715 formatting. Start at vop rather than cvop even if stmt is a store
4716 and needs_operand_addr.
4718 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4720 PR middle-end/113410
4721 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
4722 If access_nelts is integral with larger precision than sizetype,
4723 fold_convert it to sizetype.
4725 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4727 PR tree-optimization/113408
4728 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
4729 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
4732 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4734 PR middle-end/113406
4735 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
4736 regardless of whether is_gimple_reg_type (restype) or not.
4738 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4740 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
4741 funcions -> functions, and use were instead of was.
4742 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
4743 and guaranteee -> guarantee.
4744 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
4746 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4748 PR middle-end/113409
4749 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
4751 (omp_extract_for_data): Use build_bitint_type rather than
4752 build_nonstandard_integer_type if either iter_type or loop->v type
4754 * omp-expand.cc (expand_omp_for_generic,
4755 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
4756 BITINT_TYPE like INTEGER_TYPE.
4758 2024-01-17 Richard Biener <rguenther@suse.de>
4760 PR tree-optimization/113371
4761 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
4762 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4763 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
4764 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4766 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
4768 PR rtl-optimization/96388
4769 PR rtl-optimization/111554
4770 * sched-deps.cc (find_inc): Avoid exponential behavior.
4772 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4775 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
4776 from C++ Language Options to Warning Options. Add entry for
4778 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
4780 (Warning Options): ...to here. Minor copy-editing to fix typo
4783 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
4785 * config/mips/mips.cc (mips_compute_frame_info): If another
4786 register is used as global_pointer, mark $GP live false.
4788 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4791 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
4792 give the section a light copy-editing pass.
4794 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
4796 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
4797 * config/aarch64/aarch64-tune.md: Regenerated.
4798 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
4800 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
4803 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
4804 badly formed CONST expressions.
4806 2024-01-16 Daniel Cederman <cederman@gaisler.com>
4808 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
4810 2024-01-16 Daniel Cederman <cederman@gaisler.com>
4812 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
4813 * config/sparc/sync.md (membar_storeload): Turn into named insn
4814 and add GR712RC errata workaround.
4815 (membar_v8): Add GR712RC errata workaround.
4817 2024-01-16 Andreas Larsson <andreas@gaisler.com>
4819 * config/sparc/sync.md (*membar_storeload_leon3): Remove
4820 (*membar_storeload): Enable for LEON
4822 2024-01-16 Jakub Jelinek <jakub@redhat.com>
4824 PR tree-optimization/113372
4826 PR middle-end/110115
4827 PR middle-end/111422
4828 * cfgexpand.cc (add_scope_conflicts_2): New function.
4829 (add_scope_conflicts_1): Use it.
4831 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
4833 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
4834 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
4835 * doc/avr-mmcu.texi: Regenerate.
4837 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
4839 PR tree-optimization/113091
4840 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
4841 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
4842 scalar use with new function.
4843 (vect_bb_slp_mark_live_stmts): New function as entry to existing
4844 overriden functions with same name.
4845 (vect_slp_analyze_operations): Call new entry function to mark
4848 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4851 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
4852 for RVV in big-endian mode.
4854 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
4856 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
4857 (riscv_pass_in_vector_p): Delete.
4858 (riscv_init_cumulative_args): Delete the checking.
4859 (riscv_get_arg_info): Delete the checking.
4860 (riscv_function_value): Delete the checking.
4861 * config/riscv/riscv.h: Delete the member for checking.
4863 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
4865 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
4867 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
4869 * config.gcc: Include riscv_bitmanip.h.
4870 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
4871 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
4872 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
4873 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
4874 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
4875 * config/riscv/riscv-ftypes.def (2): New ftypes.
4876 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
4877 (RISCV_BUILTIN_NO_PREFIX): Likewise.
4878 * config/riscv/riscv_bitmanip.h: New file.
4880 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
4882 * config.gcc: Include riscv_crypto.h.
4883 * config/riscv/riscv_crypto.h: New file.
4885 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
4887 PR middle-end/113354
4888 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
4889 in the insn if the corresponding operand does not require hard
4892 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
4895 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
4896 * config/avr/driver-avr.cc (avr_no_devlib): New function.
4897 (avr_devicespecs_file): Use it to remove -nodevicelib from the
4898 options for cores only.
4899 * config/avr/avr-arch.h (avr_get_parch): New prototype.
4900 * config/avr/avr-devices.cc (avr_get_parch): New function.
4902 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4905 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
4906 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
4907 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
4909 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4912 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
4913 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
4914 * config/riscv/riscv-vector-costs.h: New function.
4916 2024-01-15 Richard Biener <rguenther@suse.de>
4918 PR tree-optimization/113385
4919 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4920 First redirect, then split the exit edge.
4922 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4924 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
4925 Remove m_num_vector_iterations.
4926 * config/riscv/riscv-vector-costs.h: Ditto.
4928 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
4931 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
4932 (-mbranch-cost): Set "Optimization" flag.
4934 2024-01-15 Jakub Jelinek <jakub@redhat.com>
4936 PR tree-optimization/113370
4937 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
4938 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
4939 set it to just prec % limb_prec.
4941 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4944 * config/riscv/vector.md: Fix ternary attributes.
4946 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
4949 * configure.ac [target=avr]: Check availability of emulations
4950 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
4951 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
4952 * configure: Regenerate.
4953 * config.in: Regenerate.
4954 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
4955 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
4956 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
4957 * config/avr/avr-arch.h (enum avr_device_specific_features):
4959 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
4961 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
4962 (avr_set_core_architecture): Set avr_arch_index.
4963 (have_avrxmega2_flmap, have_avrxmega4_flmap)
4964 (have_avrxmega3_rodata_in_flash): Set new static const bool according
4965 to configure results.
4966 (avr_rodata_in_flash_p): New function using them.
4967 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
4968 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
4969 (avr_asm_named_section): Track avr_has_rodata_p.
4970 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
4971 and not avr_rodata_in_flash_p ().
4972 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
4973 (LINK_SPEC): Add %(link_rodata_in_ram).
4974 (LINK_ARCH_SPEC): Remove.
4975 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
4976 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
4977 const bool according to configure results.
4978 (diagnose_mrodata_in_ram): New function.
4979 (print_mcu): Generate specs with the following changes:
4980 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
4981 need to extend avr/specs.h each time we add a new bell or whistle.
4982 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
4983 -m[no-]rodata-in-ram.
4984 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
4985 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
4986 <*cpp>: Add %(cpp_rodata_in_ram).
4987 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
4989 <*self_spec>: Add -mflmap or %<mflmap as needed.
4991 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
4993 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
4994 not the GPR iterator. Adjust pattern name and mode attribute
4997 2024-01-13 Jakub Jelinek <jakub@redhat.com>
4999 PR tree-optimization/113361
5000 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
5001 Fix up determination of the type for > limb_prec constants.
5003 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5005 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
5006 Add web-link to the avr-gcc wiki.
5008 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5010 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
5011 documentation for a version without argument, which is not supported.
5013 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5015 * config/arm/arm_neon.h
5016 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
5017 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
5018 (vld1_f16_x4, vld1_f32_x4): New.
5019 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
5020 (vld1_bf16_x4): New.
5021 (vld1q_types_x4): Updated to use vld1q_x4
5022 from arm_neon_builtins.def
5023 * config/arm/arm_neon_builtins.def
5024 (vld1_x4): Updated entries.
5025 (vld1q_x4): New entries, but comes from the old vld1_x4
5026 * config/arm/neon.md
5027 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
5029 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5031 * config/arm/arm_neon.h
5032 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
5033 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
5034 (vld1_f16_x3, vld1_f32_x3): New.
5035 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
5036 (vld1_bf16_x3): New.
5037 (vld1q_types_x3): Updated to use vld1q_x3 from
5038 arm_neon_builtins.def
5039 * config/arm/arm_neon_builtins.def
5040 (vld1_x3): Updated entries.
5041 (vld1q_x3): New entries, but comes from the old vld1_x2
5042 * config/arm/neon.md
5043 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
5045 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5047 * config/arm/arm_neon.h
5048 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
5049 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
5050 (vld1_f16_x2, vld1_f32_x2): New.
5051 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
5052 (vld1_bf16_x2): New.
5053 (vld1q_types_x2): Updated to use vld1q_x2 from
5054 arm_neon_builtins.def
5055 * config/arm/arm_neon_builtins.def
5056 (vld1_x2): Updated entries.
5057 (vld1q_x2): New entries, but comes from the old vld1_x2
5058 * config/arm/neon.md
5059 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5062 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5064 * config/arm/arm_neon.h
5065 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
5066 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
5067 (vst1q_f16_x4, vst1q_f32_x4): New.
5068 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
5069 (vst1q_bf16_x4): New.
5070 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
5071 * config/arm/neon.md
5072 (neon_vst1q_x4<mode>): New.
5073 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
5074 * config/arm/unspecs.md
5075 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
5077 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5079 * config/arm/arm_neon.h
5080 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
5081 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
5082 (vst1q_f16_x3, vst1q_f32_x3): New.
5083 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
5084 (vst1q_bf16_x3): New.
5085 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
5086 * config/arm/neon.md
5087 (neon_vst1q_x3<mode>): New.
5088 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
5089 * config/arm/unspecs.md
5090 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
5092 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5094 * config/arm/arm_neon.h
5095 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
5096 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
5097 (vst1q_f16_x2, vst1q_f32_x2): New.
5098 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
5099 (vst1q_bf16_x2): New.
5100 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
5101 * config/arm/neon.md
5102 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5104 * config/arm/iterators.md
5105 (VMEMX2): New mode iterator.
5106 (VMEMX2_q): New mode attribute.
5108 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5110 * config/arm/arm_neon.h
5111 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
5112 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
5113 (vst1_f16_x4, vst1_f32_x4): New.
5114 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
5115 (vst1_bf16_x4): New.
5116 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
5117 * config/arm/neon.md (vst1_x4<mode>): New.
5119 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5121 * config/arm/arm_neon.h
5122 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
5123 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
5124 (vst1_f16_x3, vst1_f32_x3): New.
5125 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
5126 (vst1_bf16_x3): New.
5127 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
5128 * config/arm/neon.md (vst1_x3<mode>): New.
5130 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5132 * config/arm/arm_neon.h
5133 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
5134 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
5135 (vst1_f16_x2, vst1_f32_x2): New.
5136 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
5137 (vst1_bf16_x2): New.
5138 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
5139 * config/arm/neon.md (vst1_x2<mode>): New.
5141 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5143 * config/arm/arm_neon.h
5144 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
5145 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
5146 (vld1q_f16_x4, vld1q_f32_x4): New.
5147 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
5148 (vld1q_bf16_x4): New.
5149 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
5150 * config/arm/neon.md
5151 (neon_vld1_x4<mode>): New.
5152 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
5153 * config/arm/unspecs.md
5154 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
5156 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5158 * config/arm/arm_neon.h
5159 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
5160 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
5161 (vld1q_f16_x3, vld1q_f32_x3): New.
5162 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
5163 (vld1q_bf16_x3): New.
5164 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
5165 * config/arm/neon.md
5166 (neon_vld1_x3<mode>): New.
5167 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
5168 * config/arm/unspecs.md
5169 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
5171 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5173 * config/arm/arm_neon.h
5174 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
5175 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
5176 (vld1q_f16_x2, vld1q_f32_x2): New.
5177 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
5178 (vld1q_bf16_x2): New.
5179 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
5180 * config/arm/neon.md (vld1_x2<mode>): New.
5182 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5184 PR tree-optimization/113287
5185 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
5187 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5189 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
5190 * tree-vect-loop.cc (vect_transform_loop): Likewise.
5192 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5194 PR tree-optimization/113178
5195 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
5198 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5200 PR tree-optimization/113237
5201 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
5202 existing LCSSA variable for exit when all exits are early break.
5204 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5206 PR tree-optimization/113137
5207 PR tree-optimization/113136
5208 PR tree-optimization/113172
5209 PR tree-optimization/113178
5210 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5211 Maintain PHIs on inverted loops.
5212 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
5213 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
5215 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
5217 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5219 PR tree-optimization/113135
5220 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
5221 dependency analysis.
5223 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
5225 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
5226 diagnostics class member name for abort of error.
5228 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5230 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
5231 format string to %s argument.
5233 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
5234 Jakub Jelinek <jakub@redhat.com>
5236 PR middle-end/113182
5237 * varasm.cc (process_pending_assemble_externals,
5238 assemble_external_libcall): Use targetm.strip_name_encoding
5239 before calling get_identifier.
5241 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5244 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
5245 New member variable.
5246 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
5248 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
5249 * config/aarch64/aarch64-simd.md
5250 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
5251 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
5252 zip2 for zero-extends to...
5253 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
5254 instruction. Fix big-endian handling.
5255 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
5256 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
5257 zip1 for zero-extends to...
5258 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
5259 Fix big-endian handling.
5260 (*aarch64_zip1_uxtl): New pattern.
5261 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
5262 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
5263 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
5264 (aarch64_gen_shareable_zero): Use it.
5265 (aarch64_split_simd_shift_p): New function.
5267 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5269 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
5270 (function_beg_insn): New macro.
5271 * function.cc (expand_function_start): Initialize function_beg_insn.
5273 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5276 * config/aarch64/aarch64-sve-builtins.h
5277 (function_builder::m_overload_names): Replace with...
5278 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
5280 (add_overloaded_function): Update accordingly, using get_identifier
5281 to get a GGC-friendly record of the name.
5283 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5286 * config/aarch64/aarch64-sve-builtins.def: Don't include
5287 aarch64-sve-builtins-sme.def.
5288 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
5289 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
5290 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
5291 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
5292 requires AARCH64_FL_SME2.
5293 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
5294 AARCH64_FL_SME adjustment here.
5295 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
5296 include SME intrinsics.
5297 (sme_function_groups): New array.
5298 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
5299 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
5301 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5304 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
5305 (struct cpu_vector_cost): Add regmove struct.
5306 (get_vector_costs): Export as global.
5307 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
5308 (costs::add_stmt_cost): Ditto.
5309 * config/riscv/riscv.cc (get_common_costs): Export global function.
5311 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5313 PR tree-optimization/113334
5314 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
5315 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
5316 to determine if number should be extended by all ones rather than zero
5319 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5321 PR tree-optimization/113330
5322 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
5325 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5327 PR tree-optimization/113323
5328 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
5329 check for lhs being large/huge _BitInt not in m_names.
5331 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5333 PR tree-optimization/113316
5334 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
5335 uninitialized large/huge _BitInt arguments to calls.
5337 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5339 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
5340 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
5341 CEIL (TYPE_PRECISION (t), limb_prec).
5342 (bitint_large_huge::handle_cast): Likewise.
5344 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
5347 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5348 Use assemble_function_label_final () for Power ELF V1 ABI.
5349 * output.h (assemble_function_label_final): New function.
5350 * varasm.cc (assemble_function_label_raw): Use
5351 assemble_function_label_final ().
5352 (assemble_function_label_final): New function.
5354 2024-01-12 Richard Biener <rguenther@suse.de>
5356 PR middle-end/113344
5357 * match.pd ((double)float CMP (double)float -> float CMP float):
5358 Perform result type check only for vectors.
5359 * fold-const.cc (fold_binary_loc): Likewise.
5361 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
5363 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
5364 (usdot_prod<mode>): Ditto.
5365 (sdot_prod<mode>): Ditto.
5366 (udot_prod<mode>): Ditto.
5368 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
5371 * config/i386/i386-c.cc (ix86_target_macros_internal):
5372 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
5374 2024-01-12 Richard Biener <rguenther@suse.de>
5377 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
5378 Do not generate code when d.testing_p.
5380 2024-01-12 liuhongt <hongtao.liu@intel.com>
5383 * doc/invoke.texi (fcf-protection=): Update documents.
5385 2024-01-12 Pan Li <pan2.li@intel.com>
5387 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
5388 comments of predicate func riscv_v_ext_mode_p.
5390 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
5392 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
5393 Modify ABI-name length of vfloat16m8_t
5395 2024-01-12 Li Wei <liwei@loongson.cn>
5397 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
5400 2024-01-12 Li Wei <liwei@loongson.cn>
5402 * config/loongarch/loongarch.md (add<mode>3): Removed.
5406 (*addsi3_extended): Removed.
5407 (addsi3_extended): New.
5409 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
5411 * config/riscv/thead.md: Add limits for splits.
5413 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
5415 PR middle-end/113322
5416 * expr.cc (do_store_flag): Don't try single bit tests with
5417 comparison on vector types.
5419 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
5421 PR tree-optimization/113301
5422 * match.pd (`1/x`): Delay signed case until late.
5424 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
5426 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
5428 (AVR Internal Options): ...this new @subsubsection.
5430 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
5432 PR rtl-optimization/112918
5433 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
5434 (in_class_p): Restrict condition for narrowing class in case of
5435 allow_all_reload_class_changes_p.
5436 (process_alt_operands): Try to match operand without and with
5437 narrowing reg class. Discourage narrowing the class. Finish insn
5438 matching only if there is no class narrowing.
5439 (curr_insn_transform): Pass true to in_class_p for reg operand win.
5441 2024-01-11 Richard Biener <rguenther@suse.de>
5443 PR tree-optimization/112505
5444 * tree-vect-loop.cc (vectorizable_induction): Reject
5445 bit-precision induction.
5447 2024-01-11 Richard Biener <rguenther@suse.de>
5449 PR tree-optimization/113126
5450 * match.pd ((double)float CMP (double)float -> float CMP float):
5451 Make sure the boolean type is the same.
5452 * fold-const.cc (fold_binary_loc): Likewise.
5454 2024-01-11 Richard Biener <rguenther@suse.de>
5456 PR tree-optimization/112636
5457 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
5458 estimate_numbers_of_iterations before querying
5459 get_max_loop_iterations_int.
5460 (pass_ch::execute): Initialize SCEV and loops appropriately.
5462 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
5464 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
5466 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
5467 * doc/extend.texi (AVR Variable Attributes): Improve documentation
5468 of io, io_low and address attributes.
5469 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
5470 * doc/avr-mmcu.texi: Rebuild.
5472 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
5475 * config/loongarch/genopts/loongarch.opt.in: Mark options with
5476 the "Save" property.
5477 * config/loongarch/loongarch.opt: Same.
5478 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
5479 according to la_target.
5480 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
5481 RESTORE} for the la_target structure; Rename option conditions
5482 to have the same "la_" prefix.
5483 * config/loongarch/loongarch.h: Same.
5485 2024-01-11 Pan Li <pan2.li@intel.com>
5487 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
5488 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
5490 2024-01-11 Alex Coplan <alex.coplan@arm.com>
5493 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
5494 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
5495 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
5496 synthesize these if needed. Update caller ...
5497 (ldp_bb_info::fuse_pair): ... here.
5498 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
5499 and either insn is frame-related.
5500 (find_trailing_add): Punt on frame-related insns.
5501 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
5502 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
5504 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
5506 * config/mips/mips.cc (mips_start_function_definition):
5507 Add ATTRIBUTE_UNUSED.
5509 2024-01-11 Richard Biener <rguenther@suse.de>
5511 PR middle-end/112740
5512 * expr.cc (store_constructor): Check the integer vector
5513 mask has a single bit per element before using sign-extension
5514 to expand an uniform vector.
5516 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5518 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
5519 preempt VLS on unknown NITERS loop.
5521 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
5523 * doc/invoke.texi: Add -mevex512.
5525 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
5527 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
5528 (*nor<mode>3): Likewise.
5529 (nor<mode>3): Likewise.
5530 (*negsi2_extended): New template.
5531 (*<optab>si3_internal): Likewise.
5532 (*one_cmplsi2_internal): Likewise.
5533 (*norsi3_internal): Likewise.
5534 (*<optab>nsi_internal): Likewise.
5535 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
5536 modified bit operation to make the optimization work.
5538 2024-01-11 liuhongt <hongtao.liu@intel.com>
5541 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
5543 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5545 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
5546 (get_vector_costs): Ditto.
5547 (riscv_builtin_vectorization_cost): Ditto.
5549 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5551 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
5553 2024-01-10 Antoni Boucher <bouanto@zoho.com>
5556 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
5557 ipa_free_size_summary.
5558 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
5559 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
5560 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
5561 * ipa-prop.h (ipa_prop_cc_finalize): New function.
5562 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
5563 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
5564 ipa_sra_cc_finalize): New functions.
5565 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
5566 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
5568 Include ipa-utils.h.
5570 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
5572 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
5573 (th_int_get_save_adjustment): Likewise.
5574 (th_int_adjust_cfi_prologue): Likewise.
5575 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
5576 (TH_INT_INTERRUPT): New macro.
5577 (riscv_expand_prologue): Add the processing of XTheadInt.
5578 (riscv_expand_epilogue): Likewise.
5579 * config/riscv/riscv.h (BITSET_P): Moved to here.
5580 * config/riscv/riscv.md: New unspec.
5581 * config/riscv/thead.cc (th_int_get_mask): New function.
5582 (th_int_get_save_adjustment): Likewise.
5583 (th_int_adjust_cfi_prologue): Likewise.
5584 * config/riscv/thead.md (th_int_push): New pattern.
5585 (th_int_pop): new pattern.
5587 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5589 PR tree-optimization/112468
5590 * doc/sourcebuild.texi: Document ifn_copysign.
5591 * match.pd: Only apply transformation if target supports the IFN.
5593 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
5595 PR tree-optimization/112581
5596 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
5597 mark_ssa_maybe_undefs.
5598 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
5599 variables can not be reassociated.
5600 (init_range_entry): Check for uninitialized variables too.
5601 (init_reassoc): Call mark_ssa_maybe_undefs.
5603 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
5605 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
5606 Also handle sign extension.
5608 2024-01-10 Alex Coplan <alex.coplan@arm.com>
5610 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
5612 (-mlate-ldp-fusion): Likewise.
5614 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5616 PR tree-optimization/113287
5617 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
5618 instead of using BRANCH_EDGE to determine true edge.
5620 2024-01-10 Richard Biener <rguenther@suse.de>
5622 PR tree-optimization/113078
5623 * tree-vect-loop.cc (check_reduction_path): Canonicalize
5624 .COND_SUB to .COND_ADD.
5626 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5628 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
5629 Handle prefix mappings before calling find_opt.
5630 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
5631 "-fno-"-prefixed command-line option.
5632 * opts-common.cc (get_option_prefix_remapping): New.
5633 * opts.h (get_option_prefix_remapping): New decl.
5635 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5637 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
5638 m_urlifier to pp_output_formatted_text.
5639 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
5640 (obstack_append_string): New overload, taking a length.
5641 (urlify_quoted_string): Pass in an obstack ptr, rather than using
5642 that of the pp's buffer. Generalize to handle trailing text in
5643 the buffer beyond the run of quoted text.
5644 (class quoting_info): New.
5645 (on_begin_quote): New.
5646 (on_end_quote): New.
5647 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
5648 it to calls to on_begin_quote and on_end_quote.
5649 (struct auto_obstack): New.
5650 (quoting_info::handle_phase_3): New.
5651 (pp_output_formatted_text): Add urlifier param. Use it if there
5652 is deferred urlification. Delete m_quotes.
5653 (selftest::pp_printf_with_urlifier): Pass urlifier to
5654 pp_output_formatted_text.
5655 (selftest::test_urlification): Update results for the existing
5656 case of quoted text stradding chunks; add more such test cases.
5657 * pretty-print.h (class quoting_info): New forward decl.
5658 (chunk_info::m_quotes): New field.
5659 (pp_output_formatted_text): Add optional urlifier param.
5661 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5663 * pretty-print.cc (selftest::test_pp_format): Add selftest
5664 coverage for numbered args.
5666 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5668 PR tree-optimization/113144
5669 PR tree-optimization/113145
5670 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5671 Update all BB that the original exits dominated.
5673 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
5675 * dwarf2out.cc (modified_type_die): Extend the support of reverse
5676 storage order to enumeration types if -gstrict-dwarf is not passed.
5677 (gen_enumeration_type_die): Add REVERSE parameter and generate the
5678 DIE immediately after the existing one if it is true.
5679 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
5680 call to gen_enumeration_type_die.
5681 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
5682 first recursive call as well as the call to gen_tagged_type_die.
5683 (gen_type_die): Add REVERSE parameter and pass it in the call to
5684 gen_type_die_with_usage.
5686 2024-01-10 Jakub Jelinek <jakub@redhat.com>
5688 PR tree-optimization/113120
5689 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
5690 with root->size TYPE_PRECISION don't build anything new.
5691 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
5692 rather than build_nonstandard_integer_type.
5694 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
5696 * config/i386/i386.opt: Adjust document.
5697 * doc/invoke.texi: Add description for
5698 -mapx-inline-asm-use-gpr32.
5700 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5702 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
5703 (avg<v_double_trunc>3_floor): New pattern.
5704 (<u>avg<v_double_trunc>3_ceil): Remove.
5705 (avg<v_double_trunc>3_ceil): New pattern.
5706 (uavg<mode>3_floor): Ditto.
5707 (uavg<mode>3_ceil): Ditto.
5708 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
5709 (enum insn_type): Ditto.
5710 * config/riscv/riscv-v.cc: Ditto.
5711 * config/riscv/vector-iterators.md (ashiftrt): Remove.
5713 * config/riscv/vector.md: Add VLS modes.
5715 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5718 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
5719 (vczlsbb_char): New int attribute.
5720 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
5721 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
5722 (*vctzlsbb_zext_<mode>): Rename to ...
5723 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
5726 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5729 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
5730 of the last argument from altivec_register_operand to any_operand. If
5731 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
5732 otherwise if it doesn't satisfy altivec_register_operand, force it to
5733 REG using copy_to_mode_reg.
5735 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5737 PR middle-end/113100
5738 * builtins.cc (expand_builtin_stack_address): Guard stack point
5739 adjustment with SPARC_STACK_BOUNDARY_HACK.
5741 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5743 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
5744 argument string definitions.
5745 * config/loongarch/loongarch-str.h: Same.
5746 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
5747 as aliases to -mexplicit-relocs={always,none}
5748 * config/loongarch/loongarch.opt: Regenerate.
5749 * config/loongarch/loongarch.cc: Same.
5751 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5753 * config/loongarch/loongarch-def.h: Define constants with
5754 enums instead of Macros.
5756 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5758 * config/loongarch/genopts/loongarch-strings: Rename.
5759 * config/loongarch/genopts/loongarch.opt.in: Same.
5760 * config/loongarch/loongarch-cpu.cc: Same.
5761 * config/loongarch/loongarch-def.cc: Same.
5762 * config/loongarch/loongarch-def.h: Same.
5763 * config/loongarch/loongarch-opts.cc: Same.
5764 * config/loongarch/loongarch-opts.h: Same.
5765 * config/loongarch/loongarch-str.h: Same.
5766 * config/loongarch/loongarch.opt: Same.
5768 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5770 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
5771 variable with the common la_ prefix.
5772 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
5773 flags as saved using TargetVariable.
5774 * config/loongarch/loongarch.opt: Same.
5775 * config/loongarch/loongarch-def.h: Define evolution_set to
5776 mark changes to the -march default.
5777 * config/loongarch/loongarch-driver.cc: Same.
5778 * config/loongarch/loongarch-opts.cc: Same.
5779 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
5780 conditions around the la_target structure.
5781 * config/loongarch/loongarch.cc: Same.
5782 * config/loongarch/loongarch.md: Same.
5783 * config/loongarch/loongarch-builtins.cc: Same.
5784 * config/loongarch/loongarch-c.cc: Same.
5785 * config/loongarch/lasx.md: Same.
5786 * config/loongarch/lsx.md: Same.
5787 * config/loongarch/sync.md: Same.
5789 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
5791 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
5794 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
5796 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
5798 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5800 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
5802 (vectorizable_live_operation): Likewise.
5804 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5806 PR tree-optimization/113199
5807 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
5810 2024-01-09 Jakub Jelinek <jakub@redhat.com>
5813 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
5814 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
5815 GTY(()) declaration before the definition, drop GTY(()) drom the
5818 2024-01-09 Richard Biener <rguenther@suse.de>
5820 PR tree-optimization/113026
5821 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
5822 redundant and wrong niter bound setting. Move niter
5823 bound adjustment down.
5825 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5827 PR middle-end/113163
5828 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
5829 Reject non-linear inductions that aren't supported.
5831 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
5833 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
5834 left shift implementation strategies.
5835 (arc_shift_info): Type for each entry of the shift strategy table.
5836 (arc_shift_context_idx): Return a integer value for each code
5837 generation context, used as an index
5838 (arc_ashl_alg): Table indexed by context and shifted bit count.
5839 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
5840 left shift implementation.
5841 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
5842 provide accurate costs, when optimizing for speed or size.
5844 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5846 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
5848 2024-01-09 Julian Brown <julian@codesourcery.com>
5850 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
5851 processed out before gimplification.
5852 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
5853 * tree.def (OMP_ARRAY_SECTION): New tree code.
5855 2024-01-09 Jakub Jelinek <jakub@redhat.com>
5857 PR tree-optimization/113210
5858 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
5859 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
5860 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
5863 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
5865 PR rtl-optimization/113140
5866 * reorg.cc (fill_slots_from_thread): If we are to branch after the
5867 last instruction of the function, create an end label.
5869 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
5870 Hongtao Liu <hongtao.liu@intel.com>
5873 * config/i386/i386-expand.cc
5874 (ix86_convert_const_wide_int_to_broadcast): Allow call to
5875 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
5876 (ix86_broadcast_from_constant): Revert recent change; Return a
5877 suitable MEMREF independently of mode/target combinations.
5878 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
5879 to decide whether expansion is possible/preferrable. Only try
5880 forcing DImode constants to memory (and trying again) if calling
5881 ix86_expand_vector_init_duplicate fails with an DImode immediate
5883 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
5884 V4SImode for suitable immediate constants.
5885 <case E_V4DImode>: Try using V8SImode for suitable constants.
5886 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
5887 <case E_V2HImode>: Likewise.
5888 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
5889 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
5890 <label widen>: Handle CONT_INTs via simplify_binary_operation.
5891 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
5892 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
5893 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
5894 (ix86_expand_vector_init): Move try using a broadcast for all_same
5895 with ix86_expand_vector_init_duplicate before using constant pool.
5897 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
5899 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
5901 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
5903 * config/arm/arm-cpus.in (cortex-m52): New cpu.
5904 * config/arm/arm-tables.opt: Regenerate.
5905 * config/arm/arm-tune.md: Regenerate.
5907 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
5909 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
5910 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
5911 (@vec_concatz<mode>): New insn pattern.
5912 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
5913 Handle VALS containing two vectors.
5915 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5917 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
5918 (vundefined): Ditto.
5920 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
5922 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5923 Add new function_base for crypto vector.
5924 (class bitmanip): Ditto.
5925 (class b_reverse):Ditto.
5926 (class vwsll): Ditto.
5927 (class clmul): Ditto.
5928 (class vg_nhab): Ditto.
5929 (class crypto_vv):Ditto.
5930 (class crypto_vi):Ditto.
5931 (class vaeskf2_vsm3c):Ditto.
5932 (class vsm3me): Ditto.
5933 (BASE): Add BASE declaration for crypto vector.
5934 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5935 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5936 Add crypto vector intrinsic definition.
5964 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5965 Add new function_shape for crypto vector.
5966 (struct crypto_vi_def): Ditto.
5967 (struct crypto_vv_no_op_type_def): Ditto.
5968 (SHAPE): Add SHAPE declaration of crypto vector.
5969 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5970 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5971 Add new data type for crypto vector.
5972 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5973 (vuint32mf2_t): Ditto.
5974 (vuint32m1_t): Ditto.
5975 (vuint32m2_t): Ditto.
5976 (vuint32m4_t): Ditto.
5977 (vuint32m8_t): Ditto.
5978 (vuint64m1_t): Ditto.
5979 (vuint64m2_t): Ditto.
5980 (vuint64m4_t): Ditto.
5981 (vuint64m8_t): Ditto.
5982 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5983 Add new data struct for crypto vector.
5984 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5985 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5986 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5988 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
5991 * varasm.cc (assemble_function_label_raw): Do not call
5992 asan_function_start () without the current function.
5994 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
5997 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
5998 extern and kernel_helper attributed function decls.
6000 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
6002 * btfout.cc (output_btf_strs): Changed.
6004 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6006 * config/gcn/mkoffload.cc (main): Handle gfx1100
6007 when setting the default XNACK.
6009 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6011 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
6012 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
6013 (ASM_SPEC): Handle gfx1100.
6014 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
6015 (enum gcn_isa): Add ISA_RDNA3.
6016 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
6017 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6018 * config/gcn/gcn.cc (gcn_option_override,
6019 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
6020 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
6021 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6022 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
6024 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
6025 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
6027 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6028 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
6029 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
6030 (isa_has_combined_avgprs, main): Handle gfx1100.
6031 * config/gcn/t-omp-device (isa): Add gfx1100.
6033 2024-01-08 Richard Biener <rguenther@suse.de>
6035 * doc/invoke.texi (-mmovbe): Clarify.
6037 2024-01-08 Richard Biener <rguenther@suse.de>
6039 PR tree-optimization/113026
6040 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
6041 Avoid an epilog in more cases.
6042 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
6043 epilogues niter upper bounds and estimates.
6045 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6047 PR tree-optimization/113228
6048 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
6050 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6052 PR tree-optimization/113120
6053 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
6054 large _BitInt zero INTEGER_CST PHI argument.
6056 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6058 PR tree-optimization/113119
6059 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
6060 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
6061 is before REALPART_EXPR.
6063 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
6066 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
6067 range when diagnosing attribute "io" and "io_low" are out of range.
6068 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
6069 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
6070 in contexts other than static storage.
6071 (avr_asm_output_aligned_decl_common): Move output of decls with
6072 attribute "address", "io", and "io_low" to...
6073 (avr_output_addr_attrib): ...this new function.
6074 (avr_asm_asm_output_aligned_bss): Remove output for decls with
6075 attribute "address", "io", and "io_low".
6076 (avr_encode_section_info): Rectify handling of decls with attribute
6077 "address", "io", and "io_low".
6079 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
6081 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
6082 (elf_flags): Remove XNACK from the default value.
6083 (main): Set a default XNACK according to the arch.
6085 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
6087 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
6088 (process_asm): Don't count avgprs.
6090 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
6092 * config/i386/i386.opt: Add supported sub-features.
6093 * doc/extend.texi: Add description for target attribute.
6095 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
6097 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
6099 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
6100 Uros Bizjak <ubizjak@gmail.com>
6103 * config/i386/i386-features.cc (compute_convert_gain): Include
6104 the overhead of explicit load and store (movd) instructions when
6105 converting non-store scalar operations with memory destinations.
6106 Various indentation whitespace fixes.
6108 2024-01-07 Tamar Christina <tamar.christina@arm.com>
6110 * config/arm/neon.md (cbranch<mode>4): New.
6112 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6114 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
6116 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
6118 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
6120 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6123 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
6126 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6128 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
6129 (variable_vectorized_p): Teach loop invariant.
6130 (has_unexpected_spills_p): Ditto.
6132 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6134 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
6135 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
6136 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
6138 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
6141 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
6142 (aarch64-vect-compare-costs): ...this.
6143 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
6145 (-param=aarch64-vect-compare-costs=): ...this new param.
6146 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
6147 Don't disable it when vectorizing for Advanced SIMD only.
6148 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
6149 whenever aarch64_vect_compare_costs is true.
6151 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
6153 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
6154 Modify the method of determining the memory offset of [x]vld/[x]vst.
6155 (lasx_mxst_<lasxfmt_f>): Likewise.
6156 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
6157 (loongarch_address_insns): Likewise.
6158 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
6159 (lsx_st_<lsxfmt_f>): Likewise.
6160 * config/loongarch/predicates.md (aq10b_operand): Likewise.
6161 (aq10h_operand): Likewise.
6162 (aq10w_operand): Likewise.
6163 (aq10d_operand): Likewise.
6165 2024-01-05 Alex Coplan <alex.coplan@arm.com>
6168 * config/aarch64/aarch64-ldp-fusion.cc
6169 (ldp_bb_info::try_fuse_pair): If the second access can throw,
6170 narrow the move range to exactly that insn.
6172 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
6174 * asan.cc (asan_function_start): Drop switch_to_section ().
6175 (asan_emit_stack_protection): Set .LASANPC alignment.
6176 * config/i386/i386.cc: Use assemble_function_label_raw ()
6177 instead of ASM_OUTPUT_LABEL ().
6178 * config/s390/s390.cc (s390_asm_output_function_label):
6180 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
6181 * final.cc (final_start_function_1): Drop
6182 asan_function_start ().
6183 * output.h (assemble_function_label_raw): New function.
6184 * varasm.cc (assemble_function_label_raw): Likewise.
6186 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
6188 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
6189 Use ASM_OUTPUT_FUNCTION_LABEL ().
6190 * config/alpha/alpha.cc (alpha_start_function): Likewise.
6191 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6192 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
6193 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6194 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6195 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
6196 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6197 * config/ia64/ia64.cc (ia64_start_function): Likewise.
6198 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
6200 * config/microblaze/microblaze.cc (microblaze_function_prologue):
6202 * config/mips/mips.cc (mips_start_unique_function): Return the
6204 (mips_start_function_definition): Use
6205 ASM_OUTPUT_FUNCTION_LABEL ().
6206 (mips_finish_stub): Pass the tree to
6207 mips_start_function_definition ().
6208 (mips16_build_function_stub): Likewise.
6209 (mips16_build_call_stub): Likewise.
6210 (mips_output_function_prologue): Likewise.
6211 * config/pa/pa.cc (pa_output_function_label): Use
6212 ASM_OUTPUT_FUNCTION_LABEL ().
6213 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
6214 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
6216 (rs6000_xcoff_declare_function_name): Likewise.
6218 2024-01-05 Jakub Jelinek <jakub@redhat.com>
6220 PR tree-optimization/113201
6221 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
6222 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
6224 2024-01-05 Jakub Jelinek <jakub@redhat.com>
6226 PR tree-optimization/90693
6227 * tree-ssa-math-opts.cc (match_single_bit_test): If
6228 tree_expr_nonzero_p (arg), remember it in the second argument to
6229 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
6230 arg ^ (arg - 1) > arg - 1.
6231 * internal-fn.cc (expand_POPCOUNT): If second argument to
6232 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
6233 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
6235 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
6237 * config/riscv/riscv-v.cc (expand_load_store):
6239 (expand_cond_len_op): Ditto.
6240 (expand_gather_scatter): Ditto.
6241 (expand_lanes_load_store): Ditto.
6242 (expand_fold_extract_last): Ditto.
6244 2024-01-05 Pan Li <pan2.li@intel.com>
6247 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
6249 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6250 Add new function_base for crypto vector.
6251 (class bitmanip): Ditto.
6252 (class b_reverse):Ditto.
6253 (class vwsll): Ditto.
6254 (class clmul): Ditto.
6255 (class vg_nhab): Ditto.
6256 (class crypto_vv):Ditto.
6257 (class crypto_vi):Ditto.
6258 (class vaeskf2_vsm3c):Ditto.
6259 (class vsm3me): Ditto.
6260 (BASE): Add BASE declaration for crypto vector.
6261 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6262 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6263 Add crypto vector intrinsic definition.
6291 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6292 Add new function_shape for crypto vector.
6293 (struct crypto_vi_def): Ditto.
6294 (struct crypto_vv_no_op_type_def): Ditto.
6295 (SHAPE): Add SHAPE declaration of crypto vector.
6296 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6297 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6298 Add new data type for crypto vector.
6299 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6300 (vuint32mf2_t): Ditto.
6301 (vuint32m1_t): Ditto.
6302 (vuint32m2_t): Ditto.
6303 (vuint32m4_t): Ditto.
6304 (vuint32m8_t): Ditto.
6305 (vuint64m1_t): Ditto.
6306 (vuint64m2_t): Ditto.
6307 (vuint64m4_t): Ditto.
6308 (vuint64m8_t): Ditto.
6309 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6310 Add new data struct for crypto vector.
6311 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6312 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6313 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6315 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
6317 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6318 Add new function_base for crypto vector.
6319 (class bitmanip): Ditto.
6320 (class b_reverse):Ditto.
6321 (class vwsll): Ditto.
6322 (class clmul): Ditto.
6323 (class vg_nhab): Ditto.
6324 (class crypto_vv):Ditto.
6325 (class crypto_vi):Ditto.
6326 (class vaeskf2_vsm3c):Ditto.
6327 (class vsm3me): Ditto.
6328 (BASE): Add BASE declaration for crypto vector.
6329 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6330 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6331 Add crypto vector intrinsic definition.
6359 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6360 Add new function_shape for crypto vector.
6361 (struct crypto_vi_def): Ditto.
6362 (struct crypto_vv_no_op_type_def): Ditto.
6363 (SHAPE): Add SHAPE declaration of crypto vector.
6364 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6365 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6366 Add new data type for crypto vector.
6367 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6368 (vuint32mf2_t): Ditto.
6369 (vuint32m1_t): Ditto.
6370 (vuint32m2_t): Ditto.
6371 (vuint32m4_t): Ditto.
6372 (vuint32m8_t): Ditto.
6373 (vuint64m1_t): Ditto.
6374 (vuint64m2_t): Ditto.
6375 (vuint64m4_t): Ditto.
6376 (vuint64m8_t): Ditto.
6377 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6378 Add new data struct for crypto vector.
6379 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6380 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6381 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6383 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6385 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6387 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
6389 PR tree-optimization/113186
6390 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
6391 Match `^` with the `==` for 1bit integral types.
6392 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
6395 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6397 * toplev.cc (general_init): Pass lang_mask to urlifier.
6399 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6401 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
6403 (diagnostic_context::make_option_url): Update for lang_mask param.
6404 * gcc-urlifier.cc: Include "opts.h" and "options.h".
6405 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
6406 (gcc_urlifier::m_lang_mask): New field.
6407 (doc_urls): Make static.
6408 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
6409 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
6410 Look for an option by name before trying a binary search in
6412 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
6413 (gcc_urlifier::get_url_suffix_for_option): New.
6414 (make_gcc_urlifier): Add lang_mask param.
6415 (selftest::gcc_urlifier_cc_tests): Update for above changes.
6416 Verify that a URL is found for "-fpack-struct".
6417 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
6418 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
6419 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
6420 to make_gcc_urlifier.
6421 * opts-diagnostic.h (get_option_url): Add lang_mask param.
6422 * opts.cc (get_option_html_page): Remove special-casing for
6424 (get_option_url_suffix): New.
6425 (get_option_url): Reimplement.
6426 (selftest::test_get_option_html_page): Rename to...
6427 (selftest::test_get_option_url_suffix): ...this and update for
6429 (selftest::opts_cc_tests): Update for renaming.
6430 * opts.h: Include "rich-location.h".
6431 (get_option_url_suffix): New decl.
6433 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6435 * Makefile.in (ALL_OPT_URL_FILES): New.
6436 (GCC_OBJS): Add options-urls.o.
6438 (OBJS-libcommon): Likewise.
6439 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
6440 inputs to opt-gather.awk.
6441 (options-urls.cc): New Makefile target.
6442 * opt-functions.awk (url_suffix): New function.
6443 (lang_url_suffix): New function.
6444 * options-urls-cc-gen.awk: New file.
6445 * opts.h (get_opt_url_suffix): New decl.
6447 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6449 * params.opt.urls: New file, autogenerated by
6450 regenerate-opt-urls.py.
6452 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6454 * common.opt.urls: New file, autogenerated by
6455 regenerate-opt-urls.py.
6456 * config/aarch64/aarch64.opt.urls: Likewise.
6457 * config/alpha/alpha.opt.urls: Likewise.
6458 * config/alpha/elf.opt.urls: Likewise.
6459 * config/arc/arc-tables.opt.urls: Likewise.
6460 * config/arc/arc.opt.urls: Likewise.
6461 * config/arm/arm-tables.opt.urls: Likewise.
6462 * config/arm/arm.opt.urls: Likewise.
6463 * config/arm/vxworks.opt.urls: Likewise.
6464 * config/avr/avr.opt.urls: Likewise.
6465 * config/bpf/bpf.opt.urls: Likewise.
6466 * config/c6x/c6x-tables.opt.urls: Likewise.
6467 * config/c6x/c6x.opt.urls: Likewise.
6468 * config/cris/cris.opt.urls: Likewise.
6469 * config/cris/elf.opt.urls: Likewise.
6470 * config/csky/csky.opt.urls: Likewise.
6471 * config/csky/csky_tables.opt.urls: Likewise.
6472 * config/darwin.opt.urls: Likewise.
6473 * config/dragonfly.opt.urls: Likewise.
6474 * config/epiphany/epiphany.opt.urls: Likewise.
6475 * config/fr30/fr30.opt.urls: Likewise.
6476 * config/freebsd.opt.urls: Likewise.
6477 * config/frv/frv.opt.urls: Likewise.
6478 * config/ft32/ft32.opt.urls: Likewise.
6479 * config/fused-madd.opt.urls: Likewise.
6480 * config/g.opt.urls: Likewise.
6481 * config/gcn/gcn.opt.urls: Likewise.
6482 * config/gnu-user.opt.urls: Likewise.
6483 * config/h8300/h8300.opt.urls: Likewise.
6484 * config/hpux11.opt.urls: Likewise.
6485 * config/i386/cygming.opt.urls: Likewise.
6486 * config/i386/cygwin.opt.urls: Likewise.
6487 * config/i386/djgpp.opt.urls: Likewise.
6488 * config/i386/i386.opt.urls: Likewise.
6489 * config/i386/mingw-w64.opt.urls: Likewise.
6490 * config/i386/mingw.opt.urls: Likewise.
6491 * config/i386/nto.opt.urls: Likewise.
6492 * config/ia64/ia64.opt.urls: Likewise.
6493 * config/ia64/ilp32.opt.urls: Likewise.
6494 * config/ia64/vms.opt.urls: Likewise.
6495 * config/iq2000/iq2000.opt.urls: Likewise.
6496 * config/linux-android.opt.urls: Likewise.
6497 * config/linux.opt.urls: Likewise.
6498 * config/lm32/lm32.opt.urls: Likewise.
6499 * config/loongarch/loongarch.opt.urls: Likewise.
6500 * config/lynx.opt.urls: Likewise.
6501 * config/m32c/m32c.opt.urls: Likewise.
6502 * config/m32r/m32r.opt.urls: Likewise.
6503 * config/m68k/ieee.opt.urls: Likewise.
6504 * config/m68k/m68k-tables.opt.urls: Likewise.
6505 * config/m68k/m68k.opt.urls: Likewise.
6506 * config/m68k/uclinux.opt.urls: Likewise.
6507 * config/mcore/mcore.opt.urls: Likewise.
6508 * config/microblaze/microblaze.opt.urls: Likewise.
6509 * config/mips/mips-tables.opt.urls: Likewise.
6510 * config/mips/mips.opt.urls: Likewise.
6511 * config/mips/sde.opt.urls: Likewise.
6512 * config/mmix/mmix.opt.urls: Likewise.
6513 * config/mn10300/mn10300.opt.urls: Likewise.
6514 * config/moxie/moxie.opt.urls: Likewise.
6515 * config/msp430/msp430.opt.urls: Likewise.
6516 * config/nds32/nds32-elf.opt.urls: Likewise.
6517 * config/nds32/nds32-linux.opt.urls: Likewise.
6518 * config/nds32/nds32.opt.urls: Likewise.
6519 * config/netbsd-elf.opt.urls: Likewise.
6520 * config/netbsd.opt.urls: Likewise.
6521 * config/nios2/elf.opt.urls: Likewise.
6522 * config/nios2/nios2.opt.urls: Likewise.
6523 * config/nvptx/nvptx-gen.opt.urls: Likewise.
6524 * config/nvptx/nvptx.opt.urls: Likewise.
6525 * config/openbsd.opt.urls: Likewise.
6526 * config/or1k/elf.opt.urls: Likewise.
6527 * config/or1k/or1k.opt.urls: Likewise.
6528 * config/pa/pa-hpux.opt.urls: Likewise.
6529 * config/pa/pa-hpux1010.opt.urls: Likewise.
6530 * config/pa/pa-hpux1111.opt.urls: Likewise.
6531 * config/pa/pa-hpux1131.opt.urls: Likewise.
6532 * config/pa/pa.opt.urls: Likewise.
6533 * config/pa/pa64-hpux.opt.urls: Likewise.
6534 * config/pdp11/pdp11.opt.urls: Likewise.
6535 * config/pru/pru.opt.urls: Likewise.
6536 * config/riscv/riscv.opt.urls: Likewise.
6537 * config/rl78/rl78.opt.urls: Likewise.
6538 * config/rpath.opt.urls: Likewise.
6539 * config/rs6000/476.opt.urls: Likewise.
6540 * config/rs6000/aix64.opt.urls: Likewise.
6541 * config/rs6000/darwin.opt.urls: Likewise.
6542 * config/rs6000/linux64.opt.urls: Likewise.
6543 * config/rs6000/rs6000-tables.opt.urls: Likewise.
6544 * config/rs6000/rs6000.opt.urls: Likewise.
6545 * config/rs6000/sysv4.opt.urls: Likewise.
6546 * config/rtems.opt.urls: Likewise.
6547 * config/rx/elf.opt.urls: Likewise.
6548 * config/rx/rx.opt.urls: Likewise.
6549 * config/s390/s390.opt.urls: Likewise.
6550 * config/s390/tpf.opt.urls: Likewise.
6551 * config/sh/sh.opt.urls: Likewise.
6552 * config/sh/superh.opt.urls: Likewise.
6553 * config/sol2.opt.urls: Likewise.
6554 * config/sparc/long-double-switch.opt.urls: Likewise.
6555 * config/sparc/sparc.opt.urls: Likewise.
6556 * config/stormy16/stormy16.opt.urls: Likewise.
6557 * config/v850/v850.opt.urls: Likewise.
6558 * config/vax/elf.opt.urls: Likewise.
6559 * config/vax/vax.opt.urls: Likewise.
6560 * config/visium/visium.opt.urls: Likewise.
6561 * config/vms/vms.opt.urls: Likewise.
6562 * config/vxworks-smp.opt.urls: Likewise.
6563 * config/vxworks.opt.urls: Likewise.
6564 * config/xtensa/elf.opt.urls: Likewise.
6565 * config/xtensa/uclinux.opt.urls: Likewise.
6566 * config/xtensa/xtensa.opt.urls: Likewise.
6567 * config/bfin/bfin.opt.urls: New file.
6569 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6571 * Makefile.in (OPT_URLS_HTML_DEPS): New.
6572 (regenerate-opt-urls): New target.
6573 (regenerate-opt-urls-unit-test): New target.
6574 * doc/options.texi (Option properties): Add UrlSuffix and
6575 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
6576 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
6577 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
6578 and Makefile.in's OPT_URLS_HTML_DEPS.
6579 (Anatomy of a Target Back End): Add
6580 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
6581 * regenerate-opt-urls.py: New file.
6583 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6585 * diagnostic-format-sarif.cc
6586 (sarif_builder::make_logical_location_object): Convert to...
6587 (make_sarif_logical_location_object): ...this.
6588 (sarif_builder::set_any_logical_locs_arr): Update for above
6590 (sarif_builder::make_thread_flow_location_object): Call
6591 maybe_add_sarif_properties on each diagnostic_event.
6592 * diagnostic-format-sarif.h (class logical_location): New forward
6594 (make_sarif_logical_location_object): New decl.
6595 * diagnostic-path.h (class sarif_object): New forward decl.
6596 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
6598 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
6599 Patrick Lin <patrick@andestech.com>
6600 Rufus Chen <rufus@andestech.com>
6601 Monk Chiang <monk.chiang@sifive.com>
6603 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
6604 with Nan-boxing value.
6605 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
6607 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
6608 Jeff Law <jlaw@ventanamicro.com>
6610 PR rtl-optimization/104914
6611 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
6612 a sign or zero extension is only required if the modified field
6613 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
6614 targets, don't refer to the temporarily incorrectly extended value
6615 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
6617 2024-01-04 Pan Li <pan2.li@intel.com>
6620 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6622 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6624 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6626 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6628 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
6630 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
6633 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6635 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
6636 (compute_nregs_for_mode): Refine LMUL.
6637 (max_number_of_live_regs): Ditto.
6638 (compute_estimated_lmul): Ditto.
6639 (has_unexpected_spills_p): Ditto.
6641 2024-01-04 Li Wei <liwei@loongson.cn>
6643 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
6644 Remove useless forward declaration.
6645 (loongarch_is_even_extraction): Remove useless forward declaration.
6646 (loongarch_try_expand_lsx_vshuf_const): Removed.
6647 (loongarch_expand_vec_perm_const_1): Merged.
6648 (loongarch_is_double_duplicate): Removed.
6649 (loongarch_is_center_extraction): Ditto.
6650 (loongarch_is_reversing_permutation): Ditto.
6651 (loongarch_is_di_misalign_extract): Ditto.
6652 (loongarch_is_si_misalign_extract): Ditto.
6653 (loongarch_is_lasx_lowpart_extract): Ditto.
6654 (loongarch_is_op_reverse_perm): Ditto.
6655 (loongarch_is_single_op_perm): Ditto.
6656 (loongarch_is_divisible_perm): Ditto.
6657 (loongarch_is_triple_stride_extract): Ditto.
6658 (loongarch_expand_vec_perm_const_2): Merged.
6659 (loongarch_expand_vec_perm_const): New.
6660 (loongarch_vectorize_vec_perm_const): Adjust.
6662 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
6664 * omp-general.cc: Fix comment typos and misplaced/confusing
6665 comments. Delete redundant include of omp-general.h.
6667 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6669 PR rtl-optimization/104914
6670 * config/mips/mips.md (insqisi_extended): New patterns.
6671 (inshisi_extended): Ditto.
6673 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6675 * config/mips/mips.cc (mips_insn_cost): New function.
6677 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6679 * config/mips/mips.md (perf_ratio): New attribute.
6681 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6685 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
6686 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
6687 blocks belong to infinite loop.
6688 (pre_vsetvl::emit_vsetvl): Remove fake edges.
6689 * config/riscv/t-riscv: Add a new include file.
6691 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6693 * config/riscv/vector.md: Fix indent.
6695 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
6697 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
6698 OMP_CLAUSE__SIMDUID_.
6699 * tree.cc (omp_clause_num_ops): Update position of entry for
6700 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
6701 (omp_clause_code_name): Likewise.
6703 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
6705 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
6706 printing of FUNC_MAP/IND_FUNC_MAP labels.
6708 2024-01-03 Jakub Jelinek <jakub@redhat.com>
6710 * gcc.cc (process_command): Update copyright notice dates.
6711 * gcov-dump.cc (print_version): Ditto.
6712 * gcov.cc (print_version): Ditto.
6713 * gcov-tool.cc (print_version): Ditto.
6714 * gengtype.cc (create_file): Ditto.
6715 * doc/cpp.texi: Bump @copying's copyright year.
6716 * doc/cppinternals.texi: Ditto.
6717 * doc/gcc.texi: Ditto.
6718 * doc/gccint.texi: Ditto.
6719 * doc/gcov.texi: Ditto.
6720 * doc/install.texi: Ditto.
6721 * doc/invoke.texi: Ditto.
6723 2024-01-03 Xi Ruoyao <xry111@xry111.site>
6725 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
6726 (fmin<mode>3): Likewise.
6727 (reduc_fmax_scal_<mode>3): New define_expand.
6728 (reduc_fmin_scal_<mode>3): Likewise.
6730 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6733 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
6734 (max_number_of_live_regs): Ditto.
6735 (has_unexpected_spills_p): Ditto.
6737 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
6738 Jin Ma <jinma@linux.alibaba.com>
6739 Xianmiao Qu <cooper.qu@linux.alibaba.com>
6740 Christoph Müllner <christoph.muellner@vrull.eu>
6742 * config/riscv/vector.md:
6743 Use vector_length_operand for vsetvl patterns.
6745 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6747 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
6748 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
6750 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
6752 * config/aarch64/aarch64-tuning-flags.def
6753 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
6754 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
6755 * config/aarch64/aarch64.cc
6756 (aarch64_override_options_internal): Set
6757 param_fully_pipelined_fma according to tuning option.
6758 * config/aarch64/tuning_models/ampere1.h: Add
6759 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
6760 * config/aarch64/tuning_models/ampere1a.h: Likewise.
6761 * config/aarch64/tuning_models/ampere1b.h: Likewise.
6763 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
6765 * config/riscv/vector-crypto.md: Modify copyright year.
6767 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6769 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
6771 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
6773 * config.in: Regenerate.
6774 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
6775 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
6776 Added TLS Le Relax support.
6777 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
6778 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
6779 * configure: Regenerate.
6780 * configure.ac: Check if binutils supports TLS le relax.
6782 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
6784 * config/riscv/iterators.md: Add rotate insn name.
6785 * config/riscv/riscv.md: Add new insns name for crypto vector.
6786 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
6787 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
6788 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
6790 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6793 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
6794 pointer type liveness count.
6796 Copyright (C) 2024 Free Software Foundation, Inc.
6798 Copying and distribution of this file, with or without modification,
6799 are permitted in any medium without royalty provided the copyright
6800 notice and this notice are preserved.