1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #ifndef SHIFT_COUNT_TRUNCATED
95 #define SHIFT_COUNT_TRUNCATED 0
98 /* It is not safe to use ordinary gen_lowpart in combine.
99 Use gen_lowpart_for_combine instead. See comments there. */
100 #define gen_lowpart dont_use_gen_lowpart_you_dummy
102 /* Number of attempts to combine instructions in this function. */
104 static int combine_attempts
;
106 /* Number of attempts that got as far as substitution in this function. */
108 static int combine_merges
;
110 /* Number of instructions combined with added SETs in this function. */
112 static int combine_extras
;
114 /* Number of instructions combined in this function. */
116 static int combine_successes
;
118 /* Totals over entire compilation. */
120 static int total_attempts
, total_merges
, total_extras
, total_successes
;
123 /* Vector mapping INSN_UIDs to cuids.
124 The cuids are like uids but increase monotonically always.
125 Combine always uses cuids so that it can compare them.
126 But actually renumbering the uids, which we used to do,
127 proves to be a bad idea because it makes it hard to compare
128 the dumps produced by earlier passes with those from later passes. */
130 static int *uid_cuid
;
131 static int max_uid_cuid
;
133 /* Get the cuid of an insn. */
135 #define INSN_CUID(INSN) \
136 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
138 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
139 BITS_PER_WORD would invoke undefined behavior. Work around it. */
141 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
142 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
144 #define nonzero_bits(X, M) \
145 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
147 #define num_sign_bit_copies(X, M) \
148 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
150 /* Maximum register number, which is the size of the tables below. */
152 static unsigned int combine_max_regno
;
154 /* Record last point of death of (hard or pseudo) register n. */
156 static rtx
*reg_last_death
;
158 /* Record last point of modification of (hard or pseudo) register n. */
160 static rtx
*reg_last_set
;
162 /* Record the cuid of the last insn that invalidated memory
163 (anything that writes memory, and subroutine calls, but not pushes). */
165 static int mem_last_set
;
167 /* Record the cuid of the last CALL_INSN
168 so we can tell whether a potential combination crosses any calls. */
170 static int last_call_cuid
;
172 /* When `subst' is called, this is the insn that is being modified
173 (by combining in a previous insn). The PATTERN of this insn
174 is still the old pattern partially modified and it should not be
175 looked at, but this may be used to examine the successors of the insn
176 to judge whether a simplification is valid. */
178 static rtx subst_insn
;
180 /* This is the lowest CUID that `subst' is currently dealing with.
181 get_last_value will not return a value if the register was set at or
182 after this CUID. If not for this mechanism, we could get confused if
183 I2 or I1 in try_combine were an insn that used the old value of a register
184 to obtain a new value. In that case, we might erroneously get the
185 new value of the register when we wanted the old one. */
187 static int subst_low_cuid
;
189 /* This contains any hard registers that are used in newpat; reg_dead_at_p
190 must consider all these registers to be always live. */
192 static HARD_REG_SET newpat_used_regs
;
194 /* This is an insn to which a LOG_LINKS entry has been added. If this
195 insn is the earlier than I2 or I3, combine should rescan starting at
198 static rtx added_links_insn
;
200 /* Basic block in which we are performing combines. */
201 static basic_block this_basic_block
;
203 /* A bitmap indicating which blocks had registers go dead at entry.
204 After combine, we'll need to re-do global life analysis with
205 those blocks as starting points. */
206 static sbitmap refresh_blocks
;
208 /* The next group of arrays allows the recording of the last value assigned
209 to (hard or pseudo) register n. We use this information to see if an
210 operation being processed is redundant given a prior operation performed
211 on the register. For example, an `and' with a constant is redundant if
212 all the zero bits are already known to be turned off.
214 We use an approach similar to that used by cse, but change it in the
217 (1) We do not want to reinitialize at each label.
218 (2) It is useful, but not critical, to know the actual value assigned
219 to a register. Often just its form is helpful.
221 Therefore, we maintain the following arrays:
223 reg_last_set_value the last value assigned
224 reg_last_set_label records the value of label_tick when the
225 register was assigned
226 reg_last_set_table_tick records the value of label_tick when a
227 value using the register is assigned
228 reg_last_set_invalid set to nonzero when it is not valid
229 to use the value of this register in some
232 To understand the usage of these tables, it is important to understand
233 the distinction between the value in reg_last_set_value being valid
234 and the register being validly contained in some other expression in the
237 Entry I in reg_last_set_value is valid if it is nonzero, and either
238 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
240 Register I may validly appear in any expression returned for the value
241 of another register if reg_n_sets[i] is 1. It may also appear in the
242 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
243 reg_last_set_invalid[j] is zero.
245 If an expression is found in the table containing a register which may
246 not validly appear in an expression, the register is replaced by
247 something that won't match, (clobber (const_int 0)).
249 reg_last_set_invalid[i] is set nonzero when register I is being assigned
250 to and reg_last_set_table_tick[i] == label_tick. */
252 /* Record last value assigned to (hard or pseudo) register n. */
254 static rtx
*reg_last_set_value
;
256 /* Record the value of label_tick when the value for register n is placed in
257 reg_last_set_value[n]. */
259 static int *reg_last_set_label
;
261 /* Record the value of label_tick when an expression involving register n
262 is placed in reg_last_set_value. */
264 static int *reg_last_set_table_tick
;
266 /* Set nonzero if references to register n in expressions should not be
269 static char *reg_last_set_invalid
;
271 /* Incremented for each label. */
273 static int label_tick
;
275 /* Some registers that are set more than once and used in more than one
276 basic block are nevertheless always set in similar ways. For example,
277 a QImode register may be loaded from memory in two places on a machine
278 where byte loads zero extend.
280 We record in the following array what we know about the nonzero
281 bits of a register, specifically which bits are known to be zero.
283 If an entry is zero, it means that we don't know anything special. */
285 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
287 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
288 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
290 static enum machine_mode nonzero_bits_mode
;
292 /* Nonzero if we know that a register has some leading bits that are always
293 equal to the sign bit. */
295 static unsigned char *reg_sign_bit_copies
;
297 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
298 It is zero while computing them and after combine has completed. This
299 former test prevents propagating values based on previously set values,
300 which can be incorrect if a variable is modified in a loop. */
302 static int nonzero_sign_valid
;
304 /* These arrays are maintained in parallel with reg_last_set_value
305 and are used to store the mode in which the register was last set,
306 the bits that were known to be zero when it was last set, and the
307 number of sign bits copies it was known to have when it was last set. */
309 static enum machine_mode
*reg_last_set_mode
;
310 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
311 static char *reg_last_set_sign_bit_copies
;
313 /* Record one modification to rtl structure
314 to be undone by storing old_contents into *where.
315 is_int is 1 if the contents are an int. */
321 union {rtx r
; int i
;} old_contents
;
322 union {rtx
*r
; int *i
;} where
;
325 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
326 num_undo says how many are currently recorded.
328 other_insn is nonzero if we have modified some other insn in the process
329 of working on subst_insn. It must be verified too. */
338 static struct undobuf undobuf
;
340 /* Number of times the pseudo being substituted for
341 was found and replaced. */
343 static int n_occurrences
;
345 static void do_SUBST (rtx
*, rtx
);
346 static void do_SUBST_INT (int *, int);
347 static void init_reg_last_arrays (void);
348 static void setup_incoming_promotions (void);
349 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
350 static int cant_combine_insn_p (rtx
);
351 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
352 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
353 static int contains_muldiv (rtx
);
354 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
355 static void undo_all (void);
356 static void undo_commit (void);
357 static rtx
*find_split_point (rtx
*, rtx
);
358 static rtx
subst (rtx
, rtx
, rtx
, int, int);
359 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
360 static rtx
simplify_if_then_else (rtx
);
361 static rtx
simplify_set (rtx
);
362 static rtx
simplify_logical (rtx
, int);
363 static rtx
expand_compound_operation (rtx
);
364 static rtx
expand_field_assignment (rtx
);
365 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
366 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
367 static rtx
extract_left_shift (rtx
, int);
368 static rtx
make_compound_operation (rtx
, enum rtx_code
);
369 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
370 unsigned HOST_WIDE_INT
*);
371 static rtx
force_to_mode (rtx
, enum machine_mode
,
372 unsigned HOST_WIDE_INT
, rtx
, int);
373 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
374 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
375 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
376 static rtx
make_field_assignment (rtx
);
377 static rtx
apply_distributive_law (rtx
);
378 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
379 unsigned HOST_WIDE_INT
);
380 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
381 rtx
, enum machine_mode
,
382 unsigned HOST_WIDE_INT
);
383 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
385 unsigned HOST_WIDE_INT
);
386 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
389 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
390 enum machine_mode
, unsigned int);
391 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
392 HOST_WIDE_INT
, enum machine_mode
, int *);
393 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
395 static int recog_for_combine (rtx
*, rtx
, rtx
*);
396 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
397 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
398 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
399 static void update_table_tick (rtx
);
400 static void record_value_for_reg (rtx
, rtx
, rtx
);
401 static void check_promoted_subreg (rtx
, rtx
);
402 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
403 static void record_dead_and_set_regs (rtx
);
404 static int get_last_value_validate (rtx
*, rtx
, int, int);
405 static rtx
get_last_value (rtx
);
406 static int use_crosses_set_p (rtx
, int);
407 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
408 static int reg_dead_at_p (rtx
, rtx
);
409 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
410 static int reg_bitfield_target_p (rtx
, rtx
);
411 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
412 static void distribute_links (rtx
);
413 static void mark_used_regs_combine (rtx
);
414 static int insn_cuid (rtx
);
415 static void record_promoted_value (rtx
, rtx
);
416 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
417 static enum rtx_code
combine_reversed_comparison_code (rtx
);
419 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
420 insn. The substitution can be undone by undo_all. If INTO is already
421 set to NEWVAL, do not record this change. Because computing NEWVAL might
422 also call SUBST, we have to compute it before we put anything into
426 do_SUBST (rtx
*into
, rtx newval
)
431 if (oldval
== newval
)
434 /* We'd like to catch as many invalid transformations here as
435 possible. Unfortunately, there are way too many mode changes
436 that are perfectly valid, so we'd waste too much effort for
437 little gain doing the checks here. Focus on catching invalid
438 transformations involving integer constants. */
439 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
440 && GET_CODE (newval
) == CONST_INT
)
442 /* Sanity check that we're replacing oldval with a CONST_INT
443 that is a valid sign-extension for the original mode. */
444 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
448 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
449 CONST_INT is not valid, because after the replacement, the
450 original mode would be gone. Unfortunately, we can't tell
451 when do_SUBST is called to replace the operand thereof, so we
452 perform this test on oldval instead, checking whether an
453 invalid replacement took place before we got here. */
454 if ((GET_CODE (oldval
) == SUBREG
455 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
456 || (GET_CODE (oldval
) == ZERO_EXTEND
457 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
462 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
464 buf
= xmalloc (sizeof (struct undo
));
468 buf
->old_contents
.r
= oldval
;
471 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
474 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
476 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
477 for the value of a HOST_WIDE_INT value (including CONST_INT) is
481 do_SUBST_INT (int *into
, int newval
)
486 if (oldval
== newval
)
490 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
492 buf
= xmalloc (sizeof (struct undo
));
496 buf
->old_contents
.i
= oldval
;
499 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
502 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
504 /* Main entry point for combiner. F is the first insn of the function.
505 NREGS is the first unused pseudo-reg number.
507 Return nonzero if the combiner has turned an indirect jump
508 instruction into a direct jump. */
510 combine_instructions (rtx f
, unsigned int nregs
)
517 rtx links
, nextlinks
;
519 int new_direct_jump_p
= 0;
521 combine_attempts
= 0;
524 combine_successes
= 0;
526 combine_max_regno
= nregs
;
528 reg_nonzero_bits
= xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
));
529 reg_sign_bit_copies
= xcalloc (nregs
, sizeof (unsigned char));
531 reg_last_death
= xmalloc (nregs
* sizeof (rtx
));
532 reg_last_set
= xmalloc (nregs
* sizeof (rtx
));
533 reg_last_set_value
= xmalloc (nregs
* sizeof (rtx
));
534 reg_last_set_table_tick
= xmalloc (nregs
* sizeof (int));
535 reg_last_set_label
= xmalloc (nregs
* sizeof (int));
536 reg_last_set_invalid
= xmalloc (nregs
* sizeof (char));
537 reg_last_set_mode
= xmalloc (nregs
* sizeof (enum machine_mode
));
538 reg_last_set_nonzero_bits
= xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
539 reg_last_set_sign_bit_copies
= xmalloc (nregs
* sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
548 if (INSN_UID (insn
) > i
)
551 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
554 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid
= 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 setup_incoming_promotions ();
576 refresh_blocks
= sbitmap_alloc (last_basic_block
);
577 sbitmap_zero (refresh_blocks
);
579 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
581 uid_cuid
[INSN_UID (insn
)] = ++i
;
587 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
589 record_dead_and_set_regs (insn
);
592 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
593 if (REG_NOTE_KIND (links
) == REG_INC
)
594 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
599 if (GET_CODE (insn
) == CODE_LABEL
)
603 nonzero_sign_valid
= 1;
605 /* Now scan all the insns in forward order. */
610 init_reg_last_arrays ();
611 setup_incoming_promotions ();
613 FOR_EACH_BB (this_basic_block
)
615 for (insn
= BB_HEAD (this_basic_block
);
616 insn
!= NEXT_INSN (BB_END (this_basic_block
));
617 insn
= next
? next
: NEXT_INSN (insn
))
621 if (GET_CODE (insn
) == CODE_LABEL
)
624 else if (INSN_P (insn
))
626 /* See if we know about function return values before this
627 insn based upon SUBREG flags. */
628 check_promoted_subreg (insn
, PATTERN (insn
));
630 /* Try this insn with each insn it links back to. */
632 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
633 if ((next
= try_combine (insn
, XEXP (links
, 0),
634 NULL_RTX
, &new_direct_jump_p
)) != 0)
637 /* Try each sequence of three linked insns ending with this one. */
639 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
641 rtx link
= XEXP (links
, 0);
643 /* If the linked insn has been replaced by a note, then there
644 is no point in pursuing this chain any further. */
645 if (GET_CODE (link
) == NOTE
)
648 for (nextlinks
= LOG_LINKS (link
);
650 nextlinks
= XEXP (nextlinks
, 1))
651 if ((next
= try_combine (insn
, link
,
653 &new_direct_jump_p
)) != 0)
658 /* Try to combine a jump insn that uses CC0
659 with a preceding insn that sets CC0, and maybe with its
660 logical predecessor as well.
661 This is how we make decrement-and-branch insns.
662 We need this special code because data flow connections
663 via CC0 do not get entered in LOG_LINKS. */
665 if (GET_CODE (insn
) == JUMP_INSN
666 && (prev
= prev_nonnote_insn (insn
)) != 0
667 && GET_CODE (prev
) == INSN
668 && sets_cc0_p (PATTERN (prev
)))
670 if ((next
= try_combine (insn
, prev
,
671 NULL_RTX
, &new_direct_jump_p
)) != 0)
674 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
675 nextlinks
= XEXP (nextlinks
, 1))
676 if ((next
= try_combine (insn
, prev
,
678 &new_direct_jump_p
)) != 0)
682 /* Do the same for an insn that explicitly references CC0. */
683 if (GET_CODE (insn
) == INSN
684 && (prev
= prev_nonnote_insn (insn
)) != 0
685 && GET_CODE (prev
) == INSN
686 && sets_cc0_p (PATTERN (prev
))
687 && GET_CODE (PATTERN (insn
)) == SET
688 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
690 if ((next
= try_combine (insn
, prev
,
691 NULL_RTX
, &new_direct_jump_p
)) != 0)
694 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
695 nextlinks
= XEXP (nextlinks
, 1))
696 if ((next
= try_combine (insn
, prev
,
698 &new_direct_jump_p
)) != 0)
702 /* Finally, see if any of the insns that this insn links to
703 explicitly references CC0. If so, try this insn, that insn,
704 and its predecessor if it sets CC0. */
705 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
706 if (GET_CODE (XEXP (links
, 0)) == INSN
707 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
708 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
709 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
710 && GET_CODE (prev
) == INSN
711 && sets_cc0_p (PATTERN (prev
))
712 && (next
= try_combine (insn
, XEXP (links
, 0),
713 prev
, &new_direct_jump_p
)) != 0)
717 /* Try combining an insn with two different insns whose results it
719 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
720 for (nextlinks
= XEXP (links
, 1); nextlinks
;
721 nextlinks
= XEXP (nextlinks
, 1))
722 if ((next
= try_combine (insn
, XEXP (links
, 0),
724 &new_direct_jump_p
)) != 0)
727 if (GET_CODE (insn
) != NOTE
)
728 record_dead_and_set_regs (insn
);
737 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
738 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
739 new_direct_jump_p
|= purge_all_dead_edges (0);
740 delete_noop_moves (f
);
742 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
743 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
744 | PROP_KILL_DEAD_CODE
);
747 sbitmap_free (refresh_blocks
);
748 free (reg_nonzero_bits
);
749 free (reg_sign_bit_copies
);
750 free (reg_last_death
);
752 free (reg_last_set_value
);
753 free (reg_last_set_table_tick
);
754 free (reg_last_set_label
);
755 free (reg_last_set_invalid
);
756 free (reg_last_set_mode
);
757 free (reg_last_set_nonzero_bits
);
758 free (reg_last_set_sign_bit_copies
);
762 struct undo
*undo
, *next
;
763 for (undo
= undobuf
.frees
; undo
; undo
= next
)
771 total_attempts
+= combine_attempts
;
772 total_merges
+= combine_merges
;
773 total_extras
+= combine_extras
;
774 total_successes
+= combine_successes
;
776 nonzero_sign_valid
= 0;
778 /* Make recognizer allow volatile MEMs again. */
781 return new_direct_jump_p
;
784 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
787 init_reg_last_arrays (void)
789 unsigned int nregs
= combine_max_regno
;
791 memset (reg_last_death
, 0, nregs
* sizeof (rtx
));
792 memset (reg_last_set
, 0, nregs
* sizeof (rtx
));
793 memset (reg_last_set_value
, 0, nregs
* sizeof (rtx
));
794 memset (reg_last_set_table_tick
, 0, nregs
* sizeof (int));
795 memset (reg_last_set_label
, 0, nregs
* sizeof (int));
796 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
797 memset (reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
798 memset (reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
799 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
802 /* Set up any promoted values for incoming argument registers. */
805 setup_incoming_promotions (void)
809 enum machine_mode mode
;
811 rtx first
= get_insns ();
813 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
815 #ifndef OUTGOING_REGNO
816 #define OUTGOING_REGNO(N) N
818 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
819 /* Check whether this register can hold an incoming pointer
820 argument. FUNCTION_ARG_REGNO_P tests outgoing register
821 numbers, so translate if necessary due to register windows. */
822 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
823 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
826 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
829 gen_rtx_CLOBBER (mode
, const0_rtx
)));
834 /* Called via note_stores. If X is a pseudo that is narrower than
835 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
837 If we are setting only a portion of X and we can't figure out what
838 portion, assume all bits will be used since we don't know what will
841 Similarly, set how many bits of X are known to be copies of the sign bit
842 at all locations in the function. This is the smallest number implied
846 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
847 void *data ATTRIBUTE_UNUSED
)
851 if (GET_CODE (x
) == REG
852 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
853 /* If this register is undefined at the start of the file, we can't
854 say what its contents were. */
855 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
856 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
858 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
860 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
861 reg_sign_bit_copies
[REGNO (x
)] = 1;
865 /* If this is a complex assignment, see if we can convert it into a
866 simple assignment. */
867 set
= expand_field_assignment (set
);
869 /* If this is a simple assignment, or we have a paradoxical SUBREG,
870 set what we know about X. */
872 if (SET_DEST (set
) == x
873 || (GET_CODE (SET_DEST (set
)) == SUBREG
874 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
875 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
876 && SUBREG_REG (SET_DEST (set
)) == x
))
878 rtx src
= SET_SRC (set
);
880 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
881 /* If X is narrower than a word and SRC is a non-negative
882 constant that would appear negative in the mode of X,
883 sign-extend it for use in reg_nonzero_bits because some
884 machines (maybe most) will actually do the sign-extension
885 and this is the conservative approach.
887 ??? For 2.5, try to tighten up the MD files in this regard
888 instead of this kludge. */
890 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
891 && GET_CODE (src
) == CONST_INT
893 && 0 != (INTVAL (src
)
895 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
896 src
= GEN_INT (INTVAL (src
)
897 | ((HOST_WIDE_INT
) (-1)
898 << GET_MODE_BITSIZE (GET_MODE (x
))));
901 /* Don't call nonzero_bits if it cannot change anything. */
902 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
903 reg_nonzero_bits
[REGNO (x
)]
904 |= nonzero_bits (src
, nonzero_bits_mode
);
905 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
906 if (reg_sign_bit_copies
[REGNO (x
)] == 0
907 || reg_sign_bit_copies
[REGNO (x
)] > num
)
908 reg_sign_bit_copies
[REGNO (x
)] = num
;
912 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
913 reg_sign_bit_copies
[REGNO (x
)] = 1;
918 /* See if INSN can be combined into I3. PRED and SUCC are optionally
919 insns that were previously combined into I3 or that will be combined
920 into the merger of INSN and I3.
922 Return 0 if the combination is not allowed for any reason.
924 If the combination is allowed, *PDEST will be set to the single
925 destination of INSN and *PSRC to the single source, and this function
929 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
930 rtx
*pdest
, rtx
*psrc
)
933 rtx set
= 0, src
, dest
;
938 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
939 && next_active_insn (succ
) == i3
)
940 : next_active_insn (insn
) == i3
);
942 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
943 or a PARALLEL consisting of such a SET and CLOBBERs.
945 If INSN has CLOBBER parallel parts, ignore them for our processing.
946 By definition, these happen during the execution of the insn. When it
947 is merged with another insn, all bets are off. If they are, in fact,
948 needed and aren't also supplied in I3, they may be added by
949 recog_for_combine. Otherwise, it won't match.
951 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
954 Get the source and destination of INSN. If more than one, can't
957 if (GET_CODE (PATTERN (insn
)) == SET
)
958 set
= PATTERN (insn
);
959 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
960 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
962 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
964 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
966 switch (GET_CODE (elt
))
968 /* This is important to combine floating point insns
971 /* Combining an isolated USE doesn't make sense.
972 We depend here on combinable_i3pat to reject them. */
973 /* The code below this loop only verifies that the inputs of
974 the SET in INSN do not change. We call reg_set_between_p
975 to verify that the REG in the USE does not change between
977 If the USE in INSN was for a pseudo register, the matching
978 insn pattern will likely match any register; combining this
979 with any other USE would only be safe if we knew that the
980 used registers have identical values, or if there was
981 something to tell them apart, e.g. different modes. For
982 now, we forgo such complicated tests and simply disallow
983 combining of USES of pseudo registers with any other USE. */
984 if (GET_CODE (XEXP (elt
, 0)) == REG
985 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
987 rtx i3pat
= PATTERN (i3
);
988 int i
= XVECLEN (i3pat
, 0) - 1;
989 unsigned int regno
= REGNO (XEXP (elt
, 0));
993 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
995 if (GET_CODE (i3elt
) == USE
996 && GET_CODE (XEXP (i3elt
, 0)) == REG
997 && (REGNO (XEXP (i3elt
, 0)) == regno
998 ? reg_set_between_p (XEXP (elt
, 0),
999 PREV_INSN (insn
), i3
)
1000 : regno
>= FIRST_PSEUDO_REGISTER
))
1007 /* We can ignore CLOBBERs. */
1012 /* Ignore SETs whose result isn't used but not those that
1013 have side-effects. */
1014 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1015 && ! side_effects_p (elt
))
1018 /* If we have already found a SET, this is a second one and
1019 so we cannot combine with this insn. */
1027 /* Anything else means we can't combine. */
1033 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1034 so don't do anything with it. */
1035 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1044 set
= expand_field_assignment (set
);
1045 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1047 /* Don't eliminate a store in the stack pointer. */
1048 if (dest
== stack_pointer_rtx
1049 /* Don't combine with an insn that sets a register to itself if it has
1050 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1051 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1052 /* Can't merge an ASM_OPERANDS. */
1053 || GET_CODE (src
) == ASM_OPERANDS
1054 /* Can't merge a function call. */
1055 || GET_CODE (src
) == CALL
1056 /* Don't eliminate a function call argument. */
1057 || (GET_CODE (i3
) == CALL_INSN
1058 && (find_reg_fusage (i3
, USE
, dest
)
1059 || (GET_CODE (dest
) == REG
1060 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1061 && global_regs
[REGNO (dest
)])))
1062 /* Don't substitute into an incremented register. */
1063 || FIND_REG_INC_NOTE (i3
, dest
)
1064 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1066 /* Don't combine the end of a libcall into anything. */
1067 /* ??? This gives worse code, and appears to be unnecessary, since no
1068 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1069 use REG_RETVAL notes for noconflict blocks, but other code here
1070 makes sure that those insns don't disappear. */
1071 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1073 /* Make sure that DEST is not used after SUCC but before I3. */
1074 || (succ
&& ! all_adjacent
1075 && reg_used_between_p (dest
, succ
, i3
))
1076 /* Make sure that the value that is to be substituted for the register
1077 does not use any registers whose values alter in between. However,
1078 If the insns are adjacent, a use can't cross a set even though we
1079 think it might (this can happen for a sequence of insns each setting
1080 the same destination; reg_last_set of that register might point to
1081 a NOTE). If INSN has a REG_EQUIV note, the register is always
1082 equivalent to the memory so the substitution is valid even if there
1083 are intervening stores. Also, don't move a volatile asm or
1084 UNSPEC_VOLATILE across any other insns. */
1086 && (((GET_CODE (src
) != MEM
1087 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1088 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1089 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1090 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1091 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1092 better register allocation by not doing the combine. */
1093 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1094 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1095 /* Don't combine across a CALL_INSN, because that would possibly
1096 change whether the life span of some REGs crosses calls or not,
1097 and it is a pain to update that information.
1098 Exception: if source is a constant, moving it later can't hurt.
1099 Accept that special case, because it helps -fforce-addr a lot. */
1100 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1103 /* DEST must either be a REG or CC0. */
1104 if (GET_CODE (dest
) == REG
)
1106 /* If register alignment is being enforced for multi-word items in all
1107 cases except for parameters, it is possible to have a register copy
1108 insn referencing a hard register that is not allowed to contain the
1109 mode being copied and which would not be valid as an operand of most
1110 insns. Eliminate this problem by not combining with such an insn.
1112 Also, on some machines we don't want to extend the life of a hard
1115 if (GET_CODE (src
) == REG
1116 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1117 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1118 /* Don't extend the life of a hard register unless it is
1119 user variable (if we have few registers) or it can't
1120 fit into the desired register (meaning something special
1122 Also avoid substituting a return register into I3, because
1123 reload can't handle a conflict with constraints of other
1125 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1126 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1129 else if (GET_CODE (dest
) != CC0
)
1132 /* Don't substitute for a register intended as a clobberable operand.
1133 Similarly, don't substitute an expression containing a register that
1134 will be clobbered in I3. */
1135 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1136 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1137 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1138 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1140 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1143 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1144 or not), reject, unless nothing volatile comes between it and I3 */
1146 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1148 /* Make sure succ doesn't contain a volatile reference. */
1149 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1152 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1153 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1157 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1158 to be an explicit register variable, and was chosen for a reason. */
1160 if (GET_CODE (src
) == ASM_OPERANDS
1161 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1164 /* If there are any volatile insns between INSN and I3, reject, because
1165 they might affect machine state. */
1167 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1168 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1171 /* If INSN or I2 contains an autoincrement or autodecrement,
1172 make sure that register is not used between there and I3,
1173 and not already used in I3 either.
1174 Also insist that I3 not be a jump; if it were one
1175 and the incremented register were spilled, we would lose. */
1178 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1179 if (REG_NOTE_KIND (link
) == REG_INC
1180 && (GET_CODE (i3
) == JUMP_INSN
1181 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1182 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1187 /* Don't combine an insn that follows a CC0-setting insn.
1188 An insn that uses CC0 must not be separated from the one that sets it.
1189 We do, however, allow I2 to follow a CC0-setting insn if that insn
1190 is passed as I1; in that case it will be deleted also.
1191 We also allow combining in this case if all the insns are adjacent
1192 because that would leave the two CC0 insns adjacent as well.
1193 It would be more logical to test whether CC0 occurs inside I1 or I2,
1194 but that would be much slower, and this ought to be equivalent. */
1196 p
= prev_nonnote_insn (insn
);
1197 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1202 /* If we get here, we have passed all the tests and the combination is
1211 /* LOC is the location within I3 that contains its pattern or the component
1212 of a PARALLEL of the pattern. We validate that it is valid for combining.
1214 One problem is if I3 modifies its output, as opposed to replacing it
1215 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1216 so would produce an insn that is not equivalent to the original insns.
1220 (set (reg:DI 101) (reg:DI 100))
1221 (set (subreg:SI (reg:DI 101) 0) <foo>)
1223 This is NOT equivalent to:
1225 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1226 (set (reg:DI 101) (reg:DI 100))])
1228 Not only does this modify 100 (in which case it might still be valid
1229 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1231 We can also run into a problem if I2 sets a register that I1
1232 uses and I1 gets directly substituted into I3 (not via I2). In that
1233 case, we would be getting the wrong value of I2DEST into I3, so we
1234 must reject the combination. This case occurs when I2 and I1 both
1235 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1236 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1237 of a SET must prevent combination from occurring.
1239 Before doing the above check, we first try to expand a field assignment
1240 into a set of logical operations.
1242 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1243 we place a register that is both set and used within I3. If more than one
1244 such register is detected, we fail.
1246 Return 1 if the combination is valid, zero otherwise. */
1249 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1250 int i1_not_in_src
, rtx
*pi3dest_killed
)
1254 if (GET_CODE (x
) == SET
)
1257 rtx dest
= SET_DEST (set
);
1258 rtx src
= SET_SRC (set
);
1259 rtx inner_dest
= dest
;
1261 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1262 || GET_CODE (inner_dest
) == SUBREG
1263 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1264 inner_dest
= XEXP (inner_dest
, 0);
1266 /* Check for the case where I3 modifies its output, as discussed
1267 above. We don't want to prevent pseudos from being combined
1268 into the address of a MEM, so only prevent the combination if
1269 i1 or i2 set the same MEM. */
1270 if ((inner_dest
!= dest
&&
1271 (GET_CODE (inner_dest
) != MEM
1272 || rtx_equal_p (i2dest
, inner_dest
)
1273 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1274 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1275 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1277 /* This is the same test done in can_combine_p except we can't test
1278 all_adjacent; we don't have to, since this instruction will stay
1279 in place, thus we are not considering increasing the lifetime of
1282 Also, if this insn sets a function argument, combining it with
1283 something that might need a spill could clobber a previous
1284 function argument; the all_adjacent test in can_combine_p also
1285 checks this; here, we do a more specific test for this case. */
1287 || (GET_CODE (inner_dest
) == REG
1288 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1289 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1290 GET_MODE (inner_dest
))))
1291 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1294 /* If DEST is used in I3, it is being killed in this insn,
1295 so record that for later.
1296 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1297 STACK_POINTER_REGNUM, since these are always considered to be
1298 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1299 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1300 && reg_referenced_p (dest
, PATTERN (i3
))
1301 && REGNO (dest
) != FRAME_POINTER_REGNUM
1302 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1303 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1305 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1306 && (REGNO (dest
) != ARG_POINTER_REGNUM
1307 || ! fixed_regs
[REGNO (dest
)])
1309 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1311 if (*pi3dest_killed
)
1314 *pi3dest_killed
= dest
;
1318 else if (GET_CODE (x
) == PARALLEL
)
1322 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1323 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1324 i1_not_in_src
, pi3dest_killed
))
1331 /* Return 1 if X is an arithmetic expression that contains a multiplication
1332 and division. We don't count multiplications by powers of two here. */
1335 contains_muldiv (rtx x
)
1337 switch (GET_CODE (x
))
1339 case MOD
: case DIV
: case UMOD
: case UDIV
:
1343 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1344 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1346 switch (GET_RTX_CLASS (GET_CODE (x
)))
1348 case 'c': case '<': case '2':
1349 return contains_muldiv (XEXP (x
, 0))
1350 || contains_muldiv (XEXP (x
, 1));
1353 return contains_muldiv (XEXP (x
, 0));
1361 /* Determine whether INSN can be used in a combination. Return nonzero if
1362 not. This is used in try_combine to detect early some cases where we
1363 can't perform combinations. */
1366 cant_combine_insn_p (rtx insn
)
1371 /* If this isn't really an insn, we can't do anything.
1372 This can occur when flow deletes an insn that it has merged into an
1373 auto-increment address. */
1374 if (! INSN_P (insn
))
1377 /* Never combine loads and stores involving hard regs that are likely
1378 to be spilled. The register allocator can usually handle such
1379 reg-reg moves by tying. If we allow the combiner to make
1380 substitutions of likely-spilled regs, we may abort in reload.
1381 As an exception, we allow combinations involving fixed regs; these are
1382 not available to the register allocator so there's no risk involved. */
1384 set
= single_set (insn
);
1387 src
= SET_SRC (set
);
1388 dest
= SET_DEST (set
);
1389 if (GET_CODE (src
) == SUBREG
)
1390 src
= SUBREG_REG (src
);
1391 if (GET_CODE (dest
) == SUBREG
)
1392 dest
= SUBREG_REG (dest
);
1393 if (REG_P (src
) && REG_P (dest
)
1394 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1395 && ! fixed_regs
[REGNO (src
)]
1396 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1397 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1398 && ! fixed_regs
[REGNO (dest
)]
1399 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1405 /* Adjust INSN after we made a change to its destination.
1407 Changing the destination can invalidate notes that say something about
1408 the results of the insn and a LOG_LINK pointing to the insn. */
1411 adjust_for_new_dest (rtx insn
)
1415 /* For notes, be conservative and simply remove them. */
1416 loc
= ®_NOTES (insn
);
1419 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1420 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1421 *loc
= XEXP (*loc
, 1);
1423 loc
= &XEXP (*loc
, 1);
1426 /* The new insn will have a destination that was previously the destination
1427 of an insn just above it. Call distribute_links to make a LOG_LINK from
1428 the next use of that destination. */
1429 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1432 /* Try to combine the insns I1 and I2 into I3.
1433 Here I1 and I2 appear earlier than I3.
1434 I1 can be zero; then we combine just I2 into I3.
1436 If we are combining three insns and the resulting insn is not recognized,
1437 try splitting it into two insns. If that happens, I2 and I3 are retained
1438 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1441 Return 0 if the combination does not work. Then nothing is changed.
1442 If we did the combination, return the insn at which combine should
1445 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1446 new direct jump instruction. */
1449 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1451 /* New patterns for I3 and I2, respectively. */
1452 rtx newpat
, newi2pat
= 0;
1453 int substed_i2
= 0, substed_i1
= 0;
1454 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1455 int added_sets_1
, added_sets_2
;
1456 /* Total number of SETs to put into I3. */
1458 /* Nonzero is I2's body now appears in I3. */
1460 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1461 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1462 /* Contains I3 if the destination of I3 is used in its source, which means
1463 that the old life of I3 is being killed. If that usage is placed into
1464 I2 and not in I3, a REG_DEAD note must be made. */
1465 rtx i3dest_killed
= 0;
1466 /* SET_DEST and SET_SRC of I2 and I1. */
1467 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1468 /* PATTERN (I2), or a copy of it in certain cases. */
1470 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1471 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1472 int i1_feeds_i3
= 0;
1473 /* Notes that must be added to REG_NOTES in I3 and I2. */
1474 rtx new_i3_notes
, new_i2_notes
;
1475 /* Notes that we substituted I3 into I2 instead of the normal case. */
1476 int i3_subst_into_i2
= 0;
1477 /* Notes that I1, I2 or I3 is a MULT operation. */
1485 /* Exit early if one of the insns involved can't be used for
1487 if (cant_combine_insn_p (i3
)
1488 || cant_combine_insn_p (i2
)
1489 || (i1
&& cant_combine_insn_p (i1
))
1490 /* We also can't do anything if I3 has a
1491 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1494 /* ??? This gives worse code, and appears to be unnecessary, since no
1495 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1496 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1502 undobuf
.other_insn
= 0;
1504 /* Reset the hard register usage information. */
1505 CLEAR_HARD_REG_SET (newpat_used_regs
);
1507 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1508 code below, set I1 to be the earlier of the two insns. */
1509 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1510 temp
= i1
, i1
= i2
, i2
= temp
;
1512 added_links_insn
= 0;
1514 /* First check for one important special-case that the code below will
1515 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1516 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1517 we may be able to replace that destination with the destination of I3.
1518 This occurs in the common code where we compute both a quotient and
1519 remainder into a structure, in which case we want to do the computation
1520 directly into the structure to avoid register-register copies.
1522 Note that this case handles both multiple sets in I2 and also
1523 cases where I2 has a number of CLOBBER or PARALLELs.
1525 We make very conservative checks below and only try to handle the
1526 most common cases of this. For example, we only handle the case
1527 where I2 and I3 are adjacent to avoid making difficult register
1530 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1531 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1532 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1533 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1534 && GET_CODE (PATTERN (i2
)) == PARALLEL
1535 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1536 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1537 below would need to check what is inside (and reg_overlap_mentioned_p
1538 doesn't support those codes anyway). Don't allow those destinations;
1539 the resulting insn isn't likely to be recognized anyway. */
1540 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1541 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1542 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1543 SET_DEST (PATTERN (i3
)))
1544 && next_real_insn (i2
) == i3
)
1546 rtx p2
= PATTERN (i2
);
1548 /* Make sure that the destination of I3,
1549 which we are going to substitute into one output of I2,
1550 is not used within another output of I2. We must avoid making this:
1551 (parallel [(set (mem (reg 69)) ...)
1552 (set (reg 69) ...)])
1553 which is not well-defined as to order of actions.
1554 (Besides, reload can't handle output reloads for this.)
1556 The problem can also happen if the dest of I3 is a memory ref,
1557 if another dest in I2 is an indirect memory ref. */
1558 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1559 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1560 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1561 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1562 SET_DEST (XVECEXP (p2
, 0, i
))))
1565 if (i
== XVECLEN (p2
, 0))
1566 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1567 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1568 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1569 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1574 subst_low_cuid
= INSN_CUID (i2
);
1576 added_sets_2
= added_sets_1
= 0;
1577 i2dest
= SET_SRC (PATTERN (i3
));
1579 /* Replace the dest in I2 with our dest and make the resulting
1580 insn the new pattern for I3. Then skip to where we
1581 validate the pattern. Everything was set up above. */
1582 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1583 SET_DEST (PATTERN (i3
)));
1586 i3_subst_into_i2
= 1;
1587 goto validate_replacement
;
1591 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1592 one of those words to another constant, merge them by making a new
1595 && (temp
= single_set (i2
)) != 0
1596 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1597 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1598 && GET_CODE (SET_DEST (temp
)) == REG
1599 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1600 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1601 && GET_CODE (PATTERN (i3
)) == SET
1602 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1603 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1604 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1605 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1606 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1608 HOST_WIDE_INT lo
, hi
;
1610 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1611 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1614 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1615 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1618 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1620 /* We don't handle the case of the target word being wider
1621 than a host wide int. */
1622 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1625 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1626 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1627 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1629 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1630 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1631 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1633 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1634 >> (HOST_BITS_PER_WIDE_INT
- 1));
1636 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1637 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1638 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1639 (INTVAL (SET_SRC (PATTERN (i3
)))));
1641 hi
= lo
< 0 ? -1 : 0;
1644 /* We don't handle the case of the higher word not fitting
1645 entirely in either hi or lo. */
1650 subst_low_cuid
= INSN_CUID (i2
);
1651 added_sets_2
= added_sets_1
= 0;
1652 i2dest
= SET_DEST (temp
);
1654 SUBST (SET_SRC (temp
),
1655 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1657 newpat
= PATTERN (i2
);
1658 goto validate_replacement
;
1662 /* If we have no I1 and I2 looks like:
1663 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1665 make up a dummy I1 that is
1668 (set (reg:CC X) (compare:CC Y (const_int 0)))
1670 (We can ignore any trailing CLOBBERs.)
1672 This undoes a previous combination and allows us to match a branch-and-
1675 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1676 && XVECLEN (PATTERN (i2
), 0) >= 2
1677 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1678 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1680 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1681 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1682 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1683 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1684 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1685 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1687 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1688 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1693 /* We make I1 with the same INSN_UID as I2. This gives it
1694 the same INSN_CUID for value tracking. Our fake I1 will
1695 never appear in the insn stream so giving it the same INSN_UID
1696 as I2 will not cause a problem. */
1698 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1699 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1700 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1703 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1704 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1705 SET_DEST (PATTERN (i1
)));
1710 /* Verify that I2 and I1 are valid for combining. */
1711 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1712 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1718 /* Record whether I2DEST is used in I2SRC and similarly for the other
1719 cases. Knowing this will help in register status updating below. */
1720 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1721 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1722 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1724 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1726 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1728 /* Ensure that I3's pattern can be the destination of combines. */
1729 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1730 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1737 /* See if any of the insns is a MULT operation. Unless one is, we will
1738 reject a combination that is, since it must be slower. Be conservative
1740 if (GET_CODE (i2src
) == MULT
1741 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1742 || (GET_CODE (PATTERN (i3
)) == SET
1743 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1746 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1747 We used to do this EXCEPT in one case: I3 has a post-inc in an
1748 output operand. However, that exception can give rise to insns like
1750 which is a famous insn on the PDP-11 where the value of r3 used as the
1751 source was model-dependent. Avoid this sort of thing. */
1754 if (!(GET_CODE (PATTERN (i3
)) == SET
1755 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1756 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1757 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1758 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1759 /* It's not the exception. */
1762 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1763 if (REG_NOTE_KIND (link
) == REG_INC
1764 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1766 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1773 /* See if the SETs in I1 or I2 need to be kept around in the merged
1774 instruction: whenever the value set there is still needed past I3.
1775 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1777 For the SET in I1, we have two cases: If I1 and I2 independently
1778 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1779 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1780 in I1 needs to be kept around unless I1DEST dies or is set in either
1781 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1782 I1DEST. If so, we know I1 feeds into I2. */
1784 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1787 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1788 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1790 /* If the set in I2 needs to be kept around, we must make a copy of
1791 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1792 PATTERN (I2), we are only substituting for the original I1DEST, not into
1793 an already-substituted copy. This also prevents making self-referential
1794 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1797 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1798 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1802 i2pat
= copy_rtx (i2pat
);
1806 /* Substitute in the latest insn for the regs set by the earlier ones. */
1808 maxreg
= max_reg_num ();
1812 /* It is possible that the source of I2 or I1 may be performing an
1813 unneeded operation, such as a ZERO_EXTEND of something that is known
1814 to have the high part zero. Handle that case by letting subst look at
1815 the innermost one of them.
1817 Another way to do this would be to have a function that tries to
1818 simplify a single insn instead of merging two or more insns. We don't
1819 do this because of the potential of infinite loops and because
1820 of the potential extra memory required. However, doing it the way
1821 we are is a bit of a kludge and doesn't catch all cases.
1823 But only do this if -fexpensive-optimizations since it slows things down
1824 and doesn't usually win. */
1826 if (flag_expensive_optimizations
)
1828 /* Pass pc_rtx so no substitutions are done, just simplifications.
1829 The cases that we are interested in here do not involve the few
1830 cases were is_replaced is checked. */
1833 subst_low_cuid
= INSN_CUID (i1
);
1834 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1838 subst_low_cuid
= INSN_CUID (i2
);
1839 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1844 /* Many machines that don't use CC0 have insns that can both perform an
1845 arithmetic operation and set the condition code. These operations will
1846 be represented as a PARALLEL with the first element of the vector
1847 being a COMPARE of an arithmetic operation with the constant zero.
1848 The second element of the vector will set some pseudo to the result
1849 of the same arithmetic operation. If we simplify the COMPARE, we won't
1850 match such a pattern and so will generate an extra insn. Here we test
1851 for this case, where both the comparison and the operation result are
1852 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1853 I2SRC. Later we will make the PARALLEL that contains I2. */
1855 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1856 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1857 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1858 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1860 #ifdef SELECT_CC_MODE
1862 enum machine_mode compare_mode
;
1865 newpat
= PATTERN (i3
);
1866 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1870 #ifdef SELECT_CC_MODE
1871 /* See if a COMPARE with the operand we substituted in should be done
1872 with the mode that is currently being used. If not, do the same
1873 processing we do in `subst' for a SET; namely, if the destination
1874 is used only once, try to replace it with a register of the proper
1875 mode and also replace the COMPARE. */
1876 if (undobuf
.other_insn
== 0
1877 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1878 &undobuf
.other_insn
))
1879 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1881 != GET_MODE (SET_DEST (newpat
))))
1883 unsigned int regno
= REGNO (SET_DEST (newpat
));
1884 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1886 if (regno
< FIRST_PSEUDO_REGISTER
1887 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1888 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1890 if (regno
>= FIRST_PSEUDO_REGISTER
)
1891 SUBST (regno_reg_rtx
[regno
], new_dest
);
1893 SUBST (SET_DEST (newpat
), new_dest
);
1894 SUBST (XEXP (*cc_use
, 0), new_dest
);
1895 SUBST (SET_SRC (newpat
),
1896 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1899 undobuf
.other_insn
= 0;
1906 n_occurrences
= 0; /* `subst' counts here */
1908 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1909 need to make a unique copy of I2SRC each time we substitute it
1910 to avoid self-referential rtl. */
1912 subst_low_cuid
= INSN_CUID (i2
);
1913 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1914 ! i1_feeds_i3
&& i1dest_in_i1src
);
1917 /* Record whether i2's body now appears within i3's body. */
1918 i2_is_used
= n_occurrences
;
1921 /* If we already got a failure, don't try to do more. Otherwise,
1922 try to substitute in I1 if we have it. */
1924 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1926 /* Before we can do this substitution, we must redo the test done
1927 above (see detailed comments there) that ensures that I1DEST
1928 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1930 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1938 subst_low_cuid
= INSN_CUID (i1
);
1939 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1943 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1944 to count all the ways that I2SRC and I1SRC can be used. */
1945 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1946 && i2_is_used
+ added_sets_2
> 1)
1947 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1948 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1950 /* Fail if we tried to make a new register (we used to abort, but there's
1951 really no reason to). */
1952 || max_reg_num () != maxreg
1953 /* Fail if we couldn't do something and have a CLOBBER. */
1954 || GET_CODE (newpat
) == CLOBBER
1955 /* Fail if this new pattern is a MULT and we didn't have one before
1956 at the outer level. */
1957 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1964 /* If the actions of the earlier insns must be kept
1965 in addition to substituting them into the latest one,
1966 we must make a new PARALLEL for the latest insn
1967 to hold additional the SETs. */
1969 if (added_sets_1
|| added_sets_2
)
1973 if (GET_CODE (newpat
) == PARALLEL
)
1975 rtvec old
= XVEC (newpat
, 0);
1976 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1977 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1978 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1979 sizeof (old
->elem
[0]) * old
->num_elem
);
1984 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1985 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1986 XVECEXP (newpat
, 0, 0) = old
;
1990 XVECEXP (newpat
, 0, --total_sets
)
1991 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1992 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1996 /* If there is no I1, use I2's body as is. We used to also not do
1997 the subst call below if I2 was substituted into I3,
1998 but that could lose a simplification. */
2000 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2002 /* See comment where i2pat is assigned. */
2003 XVECEXP (newpat
, 0, --total_sets
)
2004 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2008 /* We come here when we are replacing a destination in I2 with the
2009 destination of I3. */
2010 validate_replacement
:
2012 /* Note which hard regs this insn has as inputs. */
2013 mark_used_regs_combine (newpat
);
2015 /* Is the result of combination a valid instruction? */
2016 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2018 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2019 the second SET's destination is a register that is unused. In that case,
2020 we just need the first SET. This can occur when simplifying a divmod
2021 insn. We *must* test for this case here because the code below that
2022 splits two independent SETs doesn't handle this case correctly when it
2023 updates the register status. Also check the case where the first
2024 SET's destination is unused. That would not cause incorrect code, but
2025 does cause an unneeded insn to remain. */
2027 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2028 && XVECLEN (newpat
, 0) == 2
2029 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2030 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2031 && asm_noperands (newpat
) < 0)
2033 rtx set0
= XVECEXP (newpat
, 0, 0);
2034 rtx set1
= XVECEXP (newpat
, 0, 1);
2036 if (((GET_CODE (SET_DEST (set1
)) == REG
2037 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2038 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2039 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2040 && ! side_effects_p (SET_SRC (set1
)))
2043 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2046 else if (((GET_CODE (SET_DEST (set0
)) == REG
2047 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2048 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2049 && find_reg_note (i3
, REG_UNUSED
,
2050 SUBREG_REG (SET_DEST (set0
)))))
2051 && ! side_effects_p (SET_SRC (set0
)))
2054 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2056 if (insn_code_number
>= 0)
2058 /* If we will be able to accept this, we have made a
2059 change to the destination of I3. This requires us to
2060 do a few adjustments. */
2062 PATTERN (i3
) = newpat
;
2063 adjust_for_new_dest (i3
);
2068 /* If we were combining three insns and the result is a simple SET
2069 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2070 insns. There are two ways to do this. It can be split using a
2071 machine-specific method (like when you have an addition of a large
2072 constant) or by combine in the function find_split_point. */
2074 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2075 && asm_noperands (newpat
) < 0)
2077 rtx m_split
, *split
;
2078 rtx ni2dest
= i2dest
;
2080 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2081 use I2DEST as a scratch register will help. In the latter case,
2082 convert I2DEST to the mode of the source of NEWPAT if we can. */
2084 m_split
= split_insns (newpat
, i3
);
2086 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2087 inputs of NEWPAT. */
2089 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2090 possible to try that as a scratch reg. This would require adding
2091 more code to make it work though. */
2093 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2095 /* If I2DEST is a hard register or the only use of a pseudo,
2096 we can change its mode. */
2097 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2098 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2099 && GET_CODE (i2dest
) == REG
2100 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2101 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2102 && ! REG_USERVAR_P (i2dest
))))
2103 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2106 m_split
= split_insns (gen_rtx_PARALLEL
2108 gen_rtvec (2, newpat
,
2109 gen_rtx_CLOBBER (VOIDmode
,
2112 /* If the split with the mode-changed register didn't work, try
2113 the original register. */
2114 if (! m_split
&& ni2dest
!= i2dest
)
2117 m_split
= split_insns (gen_rtx_PARALLEL
2119 gen_rtvec (2, newpat
,
2120 gen_rtx_CLOBBER (VOIDmode
,
2126 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2128 m_split
= PATTERN (m_split
);
2129 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2130 if (insn_code_number
>= 0)
2133 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2134 && (next_real_insn (i2
) == i3
2135 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2138 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2139 newi2pat
= PATTERN (m_split
);
2141 i3set
= single_set (NEXT_INSN (m_split
));
2142 i2set
= single_set (m_split
);
2144 /* In case we changed the mode of I2DEST, replace it in the
2145 pseudo-register table here. We can't do it above in case this
2146 code doesn't get executed and we do a split the other way. */
2148 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2149 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2151 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2153 /* If I2 or I3 has multiple SETs, we won't know how to track
2154 register status, so don't use these insns. If I2's destination
2155 is used between I2 and I3, we also can't use these insns. */
2157 if (i2_code_number
>= 0 && i2set
&& i3set
2158 && (next_real_insn (i2
) == i3
2159 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2160 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2162 if (insn_code_number
>= 0)
2165 /* It is possible that both insns now set the destination of I3.
2166 If so, we must show an extra use of it. */
2168 if (insn_code_number
>= 0)
2170 rtx new_i3_dest
= SET_DEST (i3set
);
2171 rtx new_i2_dest
= SET_DEST (i2set
);
2173 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2174 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2175 || GET_CODE (new_i3_dest
) == SUBREG
)
2176 new_i3_dest
= XEXP (new_i3_dest
, 0);
2178 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2179 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2180 || GET_CODE (new_i2_dest
) == SUBREG
)
2181 new_i2_dest
= XEXP (new_i2_dest
, 0);
2183 if (GET_CODE (new_i3_dest
) == REG
2184 && GET_CODE (new_i2_dest
) == REG
2185 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2186 REG_N_SETS (REGNO (new_i2_dest
))++;
2190 /* If we can split it and use I2DEST, go ahead and see if that
2191 helps things be recognized. Verify that none of the registers
2192 are set between I2 and I3. */
2193 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2195 && GET_CODE (i2dest
) == REG
2197 /* We need I2DEST in the proper mode. If it is a hard register
2198 or the only use of a pseudo, we can change its mode. */
2199 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2200 || GET_MODE (*split
) == VOIDmode
2201 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2202 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2203 && ! REG_USERVAR_P (i2dest
)))
2204 && (next_real_insn (i2
) == i3
2205 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2206 /* We can't overwrite I2DEST if its value is still used by
2208 && ! reg_referenced_p (i2dest
, newpat
))
2210 rtx newdest
= i2dest
;
2211 enum rtx_code split_code
= GET_CODE (*split
);
2212 enum machine_mode split_mode
= GET_MODE (*split
);
2214 /* Get NEWDEST as a register in the proper mode. We have already
2215 validated that we can do this. */
2216 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2218 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2220 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2221 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2224 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2225 an ASHIFT. This can occur if it was inside a PLUS and hence
2226 appeared to be a memory address. This is a kludge. */
2227 if (split_code
== MULT
2228 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2229 && INTVAL (XEXP (*split
, 1)) > 0
2230 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2232 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2233 XEXP (*split
, 0), GEN_INT (i
)));
2234 /* Update split_code because we may not have a multiply
2236 split_code
= GET_CODE (*split
);
2239 #ifdef INSN_SCHEDULING
2240 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2241 be written as a ZERO_EXTEND. */
2242 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2244 #ifdef LOAD_EXTEND_OP
2245 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2246 what it really is. */
2247 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2249 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2250 SUBREG_REG (*split
)));
2253 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2254 SUBREG_REG (*split
)));
2258 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2259 SUBST (*split
, newdest
);
2260 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2262 /* If the split point was a MULT and we didn't have one before,
2263 don't use one now. */
2264 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2265 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2269 /* Check for a case where we loaded from memory in a narrow mode and
2270 then sign extended it, but we need both registers. In that case,
2271 we have a PARALLEL with both loads from the same memory location.
2272 We can split this into a load from memory followed by a register-register
2273 copy. This saves at least one insn, more if register allocation can
2276 We cannot do this if the destination of the first assignment is a
2277 condition code register or cc0. We eliminate this case by making sure
2278 the SET_DEST and SET_SRC have the same mode.
2280 We cannot do this if the destination of the second assignment is
2281 a register that we have already assumed is zero-extended. Similarly
2282 for a SUBREG of such a register. */
2284 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2285 && GET_CODE (newpat
) == PARALLEL
2286 && XVECLEN (newpat
, 0) == 2
2287 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2288 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2289 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2290 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2291 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2292 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2293 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2294 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2296 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2297 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2298 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2299 (GET_CODE (temp
) == REG
2300 && reg_nonzero_bits
[REGNO (temp
)] != 0
2301 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2302 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2303 && (reg_nonzero_bits
[REGNO (temp
)]
2304 != GET_MODE_MASK (word_mode
))))
2305 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2306 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2307 (GET_CODE (temp
) == REG
2308 && reg_nonzero_bits
[REGNO (temp
)] != 0
2309 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2310 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2311 && (reg_nonzero_bits
[REGNO (temp
)]
2312 != GET_MODE_MASK (word_mode
)))))
2313 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2314 SET_SRC (XVECEXP (newpat
, 0, 1)))
2315 && ! find_reg_note (i3
, REG_UNUSED
,
2316 SET_DEST (XVECEXP (newpat
, 0, 0))))
2320 newi2pat
= XVECEXP (newpat
, 0, 0);
2321 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2322 newpat
= XVECEXP (newpat
, 0, 1);
2323 SUBST (SET_SRC (newpat
),
2324 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2325 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2327 if (i2_code_number
>= 0)
2328 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2330 if (insn_code_number
>= 0)
2335 /* If we will be able to accept this, we have made a change to the
2336 destination of I3. This requires us to do a few adjustments. */
2337 PATTERN (i3
) = newpat
;
2338 adjust_for_new_dest (i3
);
2340 /* I3 now uses what used to be its destination and which is
2341 now I2's destination. That means we need a LOG_LINK from
2342 I3 to I2. But we used to have one, so we still will.
2344 However, some later insn might be using I2's dest and have
2345 a LOG_LINK pointing at I3. We must remove this link.
2346 The simplest way to remove the link is to point it at I1,
2347 which we know will be a NOTE. */
2349 for (insn
= NEXT_INSN (i3
);
2350 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2351 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2352 insn
= NEXT_INSN (insn
))
2354 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2356 for (link
= LOG_LINKS (insn
); link
;
2357 link
= XEXP (link
, 1))
2358 if (XEXP (link
, 0) == i3
)
2359 XEXP (link
, 0) = i1
;
2367 /* Similarly, check for a case where we have a PARALLEL of two independent
2368 SETs but we started with three insns. In this case, we can do the sets
2369 as two separate insns. This case occurs when some SET allows two
2370 other insns to combine, but the destination of that SET is still live. */
2372 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2373 && GET_CODE (newpat
) == PARALLEL
2374 && XVECLEN (newpat
, 0) == 2
2375 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2376 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2377 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2378 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2379 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2380 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2381 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2383 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2384 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2385 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2386 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2387 XVECEXP (newpat
, 0, 0))
2388 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2389 XVECEXP (newpat
, 0, 1))
2390 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2391 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2393 /* Normally, it doesn't matter which of the two is done first,
2394 but it does if one references cc0. In that case, it has to
2397 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2399 newi2pat
= XVECEXP (newpat
, 0, 0);
2400 newpat
= XVECEXP (newpat
, 0, 1);
2405 newi2pat
= XVECEXP (newpat
, 0, 1);
2406 newpat
= XVECEXP (newpat
, 0, 0);
2409 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2411 if (i2_code_number
>= 0)
2412 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2415 /* If it still isn't recognized, fail and change things back the way they
2417 if ((insn_code_number
< 0
2418 /* Is the result a reasonable ASM_OPERANDS? */
2419 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2425 /* If we had to change another insn, make sure it is valid also. */
2426 if (undobuf
.other_insn
)
2428 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2429 rtx new_other_notes
;
2432 CLEAR_HARD_REG_SET (newpat_used_regs
);
2434 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2437 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2443 PATTERN (undobuf
.other_insn
) = other_pat
;
2445 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2446 are still valid. Then add any non-duplicate notes added by
2447 recog_for_combine. */
2448 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2450 next
= XEXP (note
, 1);
2452 if (REG_NOTE_KIND (note
) == REG_UNUSED
2453 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2455 if (GET_CODE (XEXP (note
, 0)) == REG
)
2456 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2458 remove_note (undobuf
.other_insn
, note
);
2462 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2463 if (GET_CODE (XEXP (note
, 0)) == REG
)
2464 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2466 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2467 undobuf
.other_insn
, NULL_RTX
);
2470 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2471 they are adjacent to each other or not. */
2473 rtx p
= prev_nonnote_insn (i3
);
2474 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2475 && sets_cc0_p (newi2pat
))
2483 /* We now know that we can do this combination. Merge the insns and
2484 update the status of registers and LOG_LINKS. */
2487 rtx i3notes
, i2notes
, i1notes
= 0;
2488 rtx i3links
, i2links
, i1links
= 0;
2492 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2494 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2495 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2497 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2499 /* Ensure that we do not have something that should not be shared but
2500 occurs multiple times in the new insns. Check this by first
2501 resetting all the `used' flags and then copying anything is shared. */
2503 reset_used_flags (i3notes
);
2504 reset_used_flags (i2notes
);
2505 reset_used_flags (i1notes
);
2506 reset_used_flags (newpat
);
2507 reset_used_flags (newi2pat
);
2508 if (undobuf
.other_insn
)
2509 reset_used_flags (PATTERN (undobuf
.other_insn
));
2511 i3notes
= copy_rtx_if_shared (i3notes
);
2512 i2notes
= copy_rtx_if_shared (i2notes
);
2513 i1notes
= copy_rtx_if_shared (i1notes
);
2514 newpat
= copy_rtx_if_shared (newpat
);
2515 newi2pat
= copy_rtx_if_shared (newi2pat
);
2516 if (undobuf
.other_insn
)
2517 reset_used_flags (PATTERN (undobuf
.other_insn
));
2519 INSN_CODE (i3
) = insn_code_number
;
2520 PATTERN (i3
) = newpat
;
2522 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2524 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2526 reset_used_flags (call_usage
);
2527 call_usage
= copy_rtx (call_usage
);
2530 replace_rtx (call_usage
, i2dest
, i2src
);
2533 replace_rtx (call_usage
, i1dest
, i1src
);
2535 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2538 if (undobuf
.other_insn
)
2539 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2541 /* We had one special case above where I2 had more than one set and
2542 we replaced a destination of one of those sets with the destination
2543 of I3. In that case, we have to update LOG_LINKS of insns later
2544 in this basic block. Note that this (expensive) case is rare.
2546 Also, in this case, we must pretend that all REG_NOTEs for I2
2547 actually came from I3, so that REG_UNUSED notes from I2 will be
2548 properly handled. */
2550 if (i3_subst_into_i2
)
2552 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2553 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2554 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2555 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2556 && ! find_reg_note (i2
, REG_UNUSED
,
2557 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2558 for (temp
= NEXT_INSN (i2
);
2559 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2560 || BB_HEAD (this_basic_block
) != temp
);
2561 temp
= NEXT_INSN (temp
))
2562 if (temp
!= i3
&& INSN_P (temp
))
2563 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2564 if (XEXP (link
, 0) == i2
)
2565 XEXP (link
, 0) = i3
;
2570 while (XEXP (link
, 1))
2571 link
= XEXP (link
, 1);
2572 XEXP (link
, 1) = i2notes
;
2586 INSN_CODE (i2
) = i2_code_number
;
2587 PATTERN (i2
) = newi2pat
;
2591 PUT_CODE (i2
, NOTE
);
2592 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2593 NOTE_SOURCE_FILE (i2
) = 0;
2600 PUT_CODE (i1
, NOTE
);
2601 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2602 NOTE_SOURCE_FILE (i1
) = 0;
2605 /* Get death notes for everything that is now used in either I3 or
2606 I2 and used to die in a previous insn. If we built two new
2607 patterns, move from I1 to I2 then I2 to I3 so that we get the
2608 proper movement on registers that I2 modifies. */
2612 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2613 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2616 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2619 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2621 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2623 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2625 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2627 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2629 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2630 know these are REG_UNUSED and want them to go to the desired insn,
2631 so we always pass it as i3. We have not counted the notes in
2632 reg_n_deaths yet, so we need to do so now. */
2634 if (newi2pat
&& new_i2_notes
)
2636 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2637 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2638 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2640 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2645 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2646 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2647 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2649 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2652 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2653 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2654 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2655 in that case, it might delete I2. Similarly for I2 and I1.
2656 Show an additional death due to the REG_DEAD note we make here. If
2657 we discard it in distribute_notes, we will decrement it again. */
2661 if (GET_CODE (i3dest_killed
) == REG
)
2662 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2664 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2665 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2667 NULL_RTX
, i2
, NULL_RTX
);
2669 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2671 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2674 if (i2dest_in_i2src
)
2676 if (GET_CODE (i2dest
) == REG
)
2677 REG_N_DEATHS (REGNO (i2dest
))++;
2679 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2680 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2681 NULL_RTX
, i2
, NULL_RTX
);
2683 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2684 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2687 if (i1dest_in_i1src
)
2689 if (GET_CODE (i1dest
) == REG
)
2690 REG_N_DEATHS (REGNO (i1dest
))++;
2692 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2693 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2694 NULL_RTX
, i2
, NULL_RTX
);
2696 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2697 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2700 distribute_links (i3links
);
2701 distribute_links (i2links
);
2702 distribute_links (i1links
);
2704 if (GET_CODE (i2dest
) == REG
)
2707 rtx i2_insn
= 0, i2_val
= 0, set
;
2709 /* The insn that used to set this register doesn't exist, and
2710 this life of the register may not exist either. See if one of
2711 I3's links points to an insn that sets I2DEST. If it does,
2712 that is now the last known value for I2DEST. If we don't update
2713 this and I2 set the register to a value that depended on its old
2714 contents, we will get confused. If this insn is used, thing
2715 will be set correctly in combine_instructions. */
2717 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2718 if ((set
= single_set (XEXP (link
, 0))) != 0
2719 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2720 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2722 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2724 /* If the reg formerly set in I2 died only once and that was in I3,
2725 zero its use count so it won't make `reload' do any work. */
2727 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2728 && ! i2dest_in_i2src
)
2730 regno
= REGNO (i2dest
);
2731 REG_N_SETS (regno
)--;
2735 if (i1
&& GET_CODE (i1dest
) == REG
)
2738 rtx i1_insn
= 0, i1_val
= 0, set
;
2740 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2741 if ((set
= single_set (XEXP (link
, 0))) != 0
2742 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2743 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2745 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2747 regno
= REGNO (i1dest
);
2748 if (! added_sets_1
&& ! i1dest_in_i1src
)
2749 REG_N_SETS (regno
)--;
2752 /* Update reg_nonzero_bits et al for any changes that may have been made
2753 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2754 important. Because newi2pat can affect nonzero_bits of newpat */
2756 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2757 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2759 /* Set new_direct_jump_p if a new return or simple jump instruction
2762 If I3 is now an unconditional jump, ensure that it has a
2763 BARRIER following it since it may have initially been a
2764 conditional jump. It may also be the last nonnote insn. */
2766 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2768 *new_direct_jump_p
= 1;
2769 mark_jump_label (PATTERN (i3
), i3
, 0);
2771 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2772 || GET_CODE (temp
) != BARRIER
)
2773 emit_barrier_after (i3
);
2776 if (undobuf
.other_insn
!= NULL_RTX
2777 && (returnjump_p (undobuf
.other_insn
)
2778 || any_uncondjump_p (undobuf
.other_insn
)))
2780 *new_direct_jump_p
= 1;
2782 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2783 || GET_CODE (temp
) != BARRIER
)
2784 emit_barrier_after (undobuf
.other_insn
);
2787 /* An NOOP jump does not need barrier, but it does need cleaning up
2789 if (GET_CODE (newpat
) == SET
2790 && SET_SRC (newpat
) == pc_rtx
2791 && SET_DEST (newpat
) == pc_rtx
)
2792 *new_direct_jump_p
= 1;
2795 combine_successes
++;
2798 if (added_links_insn
2799 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2800 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2801 return added_links_insn
;
2803 return newi2pat
? i2
: i3
;
2806 /* Undo all the modifications recorded in undobuf. */
2811 struct undo
*undo
, *next
;
2813 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2817 *undo
->where
.i
= undo
->old_contents
.i
;
2819 *undo
->where
.r
= undo
->old_contents
.r
;
2821 undo
->next
= undobuf
.frees
;
2822 undobuf
.frees
= undo
;
2828 /* We've committed to accepting the changes we made. Move all
2829 of the undos to the free list. */
2834 struct undo
*undo
, *next
;
2836 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2839 undo
->next
= undobuf
.frees
;
2840 undobuf
.frees
= undo
;
2846 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2847 where we have an arithmetic expression and return that point. LOC will
2850 try_combine will call this function to see if an insn can be split into
2854 find_split_point (rtx
*loc
, rtx insn
)
2857 enum rtx_code code
= GET_CODE (x
);
2859 unsigned HOST_WIDE_INT len
= 0;
2860 HOST_WIDE_INT pos
= 0;
2862 rtx inner
= NULL_RTX
;
2864 /* First special-case some codes. */
2868 #ifdef INSN_SCHEDULING
2869 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2871 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2874 return find_split_point (&SUBREG_REG (x
), insn
);
2878 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2879 using LO_SUM and HIGH. */
2880 if (GET_CODE (XEXP (x
, 0)) == CONST
2881 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2884 gen_rtx_LO_SUM (Pmode
,
2885 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2887 return &XEXP (XEXP (x
, 0), 0);
2891 /* If we have a PLUS whose second operand is a constant and the
2892 address is not valid, perhaps will can split it up using
2893 the machine-specific way to split large constants. We use
2894 the first pseudo-reg (one of the virtual regs) as a placeholder;
2895 it will not remain in the result. */
2896 if (GET_CODE (XEXP (x
, 0)) == PLUS
2897 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2898 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2900 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2901 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2904 /* This should have produced two insns, each of which sets our
2905 placeholder. If the source of the second is a valid address,
2906 we can make put both sources together and make a split point
2910 && NEXT_INSN (seq
) != NULL_RTX
2911 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2912 && GET_CODE (seq
) == INSN
2913 && GET_CODE (PATTERN (seq
)) == SET
2914 && SET_DEST (PATTERN (seq
)) == reg
2915 && ! reg_mentioned_p (reg
,
2916 SET_SRC (PATTERN (seq
)))
2917 && GET_CODE (NEXT_INSN (seq
)) == INSN
2918 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2919 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2920 && memory_address_p (GET_MODE (x
),
2921 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2923 rtx src1
= SET_SRC (PATTERN (seq
));
2924 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2926 /* Replace the placeholder in SRC2 with SRC1. If we can
2927 find where in SRC2 it was placed, that can become our
2928 split point and we can replace this address with SRC2.
2929 Just try two obvious places. */
2931 src2
= replace_rtx (src2
, reg
, src1
);
2933 if (XEXP (src2
, 0) == src1
)
2934 split
= &XEXP (src2
, 0);
2935 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2936 && XEXP (XEXP (src2
, 0), 0) == src1
)
2937 split
= &XEXP (XEXP (src2
, 0), 0);
2941 SUBST (XEXP (x
, 0), src2
);
2946 /* If that didn't work, perhaps the first operand is complex and
2947 needs to be computed separately, so make a split point there.
2948 This will occur on machines that just support REG + CONST
2949 and have a constant moved through some previous computation. */
2951 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2952 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2953 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2955 return &XEXP (XEXP (x
, 0), 0);
2961 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2962 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2963 we need to put the operand into a register. So split at that
2966 if (SET_DEST (x
) == cc0_rtx
2967 && GET_CODE (SET_SRC (x
)) != COMPARE
2968 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2969 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2970 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2971 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2972 return &SET_SRC (x
);
2975 /* See if we can split SET_SRC as it stands. */
2976 split
= find_split_point (&SET_SRC (x
), insn
);
2977 if (split
&& split
!= &SET_SRC (x
))
2980 /* See if we can split SET_DEST as it stands. */
2981 split
= find_split_point (&SET_DEST (x
), insn
);
2982 if (split
&& split
!= &SET_DEST (x
))
2985 /* See if this is a bitfield assignment with everything constant. If
2986 so, this is an IOR of an AND, so split it into that. */
2987 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2988 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2989 <= HOST_BITS_PER_WIDE_INT
)
2990 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2991 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2992 && GET_CODE (SET_SRC (x
)) == CONST_INT
2993 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2994 + INTVAL (XEXP (SET_DEST (x
), 2)))
2995 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2996 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2998 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2999 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3000 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3001 rtx dest
= XEXP (SET_DEST (x
), 0);
3002 enum machine_mode mode
= GET_MODE (dest
);
3003 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3005 if (BITS_BIG_ENDIAN
)
3006 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3010 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3013 gen_binary (IOR
, mode
,
3014 gen_binary (AND
, mode
, dest
,
3015 gen_int_mode (~(mask
<< pos
),
3017 GEN_INT (src
<< pos
)));
3019 SUBST (SET_DEST (x
), dest
);
3021 split
= find_split_point (&SET_SRC (x
), insn
);
3022 if (split
&& split
!= &SET_SRC (x
))
3026 /* Otherwise, see if this is an operation that we can split into two.
3027 If so, try to split that. */
3028 code
= GET_CODE (SET_SRC (x
));
3033 /* If we are AND'ing with a large constant that is only a single
3034 bit and the result is only being used in a context where we
3035 need to know if it is zero or nonzero, replace it with a bit
3036 extraction. This will avoid the large constant, which might
3037 have taken more than one insn to make. If the constant were
3038 not a valid argument to the AND but took only one insn to make,
3039 this is no worse, but if it took more than one insn, it will
3042 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3043 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3044 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3045 && GET_CODE (SET_DEST (x
)) == REG
3046 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3047 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3048 && XEXP (*split
, 0) == SET_DEST (x
)
3049 && XEXP (*split
, 1) == const0_rtx
)
3051 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3052 XEXP (SET_SRC (x
), 0),
3053 pos
, NULL_RTX
, 1, 1, 0, 0);
3054 if (extraction
!= 0)
3056 SUBST (SET_SRC (x
), extraction
);
3057 return find_split_point (loc
, insn
);
3063 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3064 is known to be on, this can be converted into a NEG of a shift. */
3065 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3066 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3067 && 1 <= (pos
= exact_log2
3068 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3069 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3071 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3075 gen_rtx_LSHIFTRT (mode
,
3076 XEXP (SET_SRC (x
), 0),
3079 split
= find_split_point (&SET_SRC (x
), insn
);
3080 if (split
&& split
!= &SET_SRC (x
))
3086 inner
= XEXP (SET_SRC (x
), 0);
3088 /* We can't optimize if either mode is a partial integer
3089 mode as we don't know how many bits are significant
3091 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3092 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3096 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3102 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3103 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3105 inner
= XEXP (SET_SRC (x
), 0);
3106 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3107 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3109 if (BITS_BIG_ENDIAN
)
3110 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3111 unsignedp
= (code
== ZERO_EXTRACT
);
3119 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3121 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3123 /* For unsigned, we have a choice of a shift followed by an
3124 AND or two shifts. Use two shifts for field sizes where the
3125 constant might be too large. We assume here that we can
3126 always at least get 8-bit constants in an AND insn, which is
3127 true for every current RISC. */
3129 if (unsignedp
&& len
<= 8)
3134 (mode
, gen_lowpart_for_combine (mode
, inner
),
3136 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3138 split
= find_split_point (&SET_SRC (x
), insn
);
3139 if (split
&& split
!= &SET_SRC (x
))
3146 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3147 gen_rtx_ASHIFT (mode
,
3148 gen_lowpart_for_combine (mode
, inner
),
3149 GEN_INT (GET_MODE_BITSIZE (mode
)
3151 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3153 split
= find_split_point (&SET_SRC (x
), insn
);
3154 if (split
&& split
!= &SET_SRC (x
))
3159 /* See if this is a simple operation with a constant as the second
3160 operand. It might be that this constant is out of range and hence
3161 could be used as a split point. */
3162 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3163 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3164 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3165 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3166 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3167 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3168 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3170 return &XEXP (SET_SRC (x
), 1);
3172 /* Finally, see if this is a simple operation with its first operand
3173 not in a register. The operation might require this operand in a
3174 register, so return it as a split point. We can always do this
3175 because if the first operand were another operation, we would have
3176 already found it as a split point. */
3177 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3178 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3179 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3180 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3181 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3182 return &XEXP (SET_SRC (x
), 0);
3188 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3189 it is better to write this as (not (ior A B)) so we can split it.
3190 Similarly for IOR. */
3191 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3194 gen_rtx_NOT (GET_MODE (x
),
3195 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3197 XEXP (XEXP (x
, 0), 0),
3198 XEXP (XEXP (x
, 1), 0))));
3199 return find_split_point (loc
, insn
);
3202 /* Many RISC machines have a large set of logical insns. If the
3203 second operand is a NOT, put it first so we will try to split the
3204 other operand first. */
3205 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3207 rtx tem
= XEXP (x
, 0);
3208 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3209 SUBST (XEXP (x
, 1), tem
);
3217 /* Otherwise, select our actions depending on our rtx class. */
3218 switch (GET_RTX_CLASS (code
))
3220 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3222 split
= find_split_point (&XEXP (x
, 2), insn
);
3225 /* ... fall through ... */
3229 split
= find_split_point (&XEXP (x
, 1), insn
);
3232 /* ... fall through ... */
3234 /* Some machines have (and (shift ...) ...) insns. If X is not
3235 an AND, but XEXP (X, 0) is, use it as our split point. */
3236 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3237 return &XEXP (x
, 0);
3239 split
= find_split_point (&XEXP (x
, 0), insn
);
3245 /* Otherwise, we don't have a split point. */
3249 /* Throughout X, replace FROM with TO, and return the result.
3250 The result is TO if X is FROM;
3251 otherwise the result is X, but its contents may have been modified.
3252 If they were modified, a record was made in undobuf so that
3253 undo_all will (among other things) return X to its original state.
3255 If the number of changes necessary is too much to record to undo,
3256 the excess changes are not made, so the result is invalid.
3257 The changes already made can still be undone.
3258 undobuf.num_undo is incremented for such changes, so by testing that
3259 the caller can tell whether the result is valid.
3261 `n_occurrences' is incremented each time FROM is replaced.
3263 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3265 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3266 by copying if `n_occurrences' is nonzero. */
3269 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3271 enum rtx_code code
= GET_CODE (x
);
3272 enum machine_mode op0_mode
= VOIDmode
;
3277 /* Two expressions are equal if they are identical copies of a shared
3278 RTX or if they are both registers with the same register number
3281 #define COMBINE_RTX_EQUAL_P(X,Y) \
3283 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3284 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3286 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3289 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3292 /* If X and FROM are the same register but different modes, they will
3293 not have been seen as equal above. However, flow.c will make a
3294 LOG_LINKS entry for that case. If we do nothing, we will try to
3295 rerecognize our original insn and, when it succeeds, we will
3296 delete the feeding insn, which is incorrect.
3298 So force this insn not to match in this (rare) case. */
3299 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3300 && REGNO (x
) == REGNO (from
))
3301 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3303 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3304 of which may contain things that can be combined. */
3305 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3308 /* It is possible to have a subexpression appear twice in the insn.
3309 Suppose that FROM is a register that appears within TO.
3310 Then, after that subexpression has been scanned once by `subst',
3311 the second time it is scanned, TO may be found. If we were
3312 to scan TO here, we would find FROM within it and create a
3313 self-referent rtl structure which is completely wrong. */
3314 if (COMBINE_RTX_EQUAL_P (x
, to
))
3317 /* Parallel asm_operands need special attention because all of the
3318 inputs are shared across the arms. Furthermore, unsharing the
3319 rtl results in recognition failures. Failure to handle this case
3320 specially can result in circular rtl.
3322 Solve this by doing a normal pass across the first entry of the
3323 parallel, and only processing the SET_DESTs of the subsequent
3326 if (code
== PARALLEL
3327 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3328 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3330 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3332 /* If this substitution failed, this whole thing fails. */
3333 if (GET_CODE (new) == CLOBBER
3334 && XEXP (new, 0) == const0_rtx
)
3337 SUBST (XVECEXP (x
, 0, 0), new);
3339 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3341 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3343 if (GET_CODE (dest
) != REG
3344 && GET_CODE (dest
) != CC0
3345 && GET_CODE (dest
) != PC
)
3347 new = subst (dest
, from
, to
, 0, unique_copy
);
3349 /* If this substitution failed, this whole thing fails. */
3350 if (GET_CODE (new) == CLOBBER
3351 && XEXP (new, 0) == const0_rtx
)
3354 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3360 len
= GET_RTX_LENGTH (code
);
3361 fmt
= GET_RTX_FORMAT (code
);
3363 /* We don't need to process a SET_DEST that is a register, CC0,
3364 or PC, so set up to skip this common case. All other cases
3365 where we want to suppress replacing something inside a
3366 SET_SRC are handled via the IN_DEST operand. */
3368 && (GET_CODE (SET_DEST (x
)) == REG
3369 || GET_CODE (SET_DEST (x
)) == CC0
3370 || GET_CODE (SET_DEST (x
)) == PC
))
3373 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3376 op0_mode
= GET_MODE (XEXP (x
, 0));
3378 for (i
= 0; i
< len
; i
++)
3383 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3385 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3387 new = (unique_copy
&& n_occurrences
3388 ? copy_rtx (to
) : to
);
3393 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3396 /* If this substitution failed, this whole thing
3398 if (GET_CODE (new) == CLOBBER
3399 && XEXP (new, 0) == const0_rtx
)
3403 SUBST (XVECEXP (x
, i
, j
), new);
3406 else if (fmt
[i
] == 'e')
3408 /* If this is a register being set, ignore it. */
3411 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3412 || code
== ZERO_EXTRACT
)
3414 && GET_CODE (new) == REG
)
3417 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3419 /* In general, don't install a subreg involving two
3420 modes not tieable. It can worsen register
3421 allocation, and can even make invalid reload
3422 insns, since the reg inside may need to be copied
3423 from in the outside mode, and that may be invalid
3424 if it is an fp reg copied in integer mode.
3426 We allow two exceptions to this: It is valid if
3427 it is inside another SUBREG and the mode of that
3428 SUBREG and the mode of the inside of TO is
3429 tieable and it is valid if X is a SET that copies
3432 if (GET_CODE (to
) == SUBREG
3433 && ! MODES_TIEABLE_P (GET_MODE (to
),
3434 GET_MODE (SUBREG_REG (to
)))
3435 && ! (code
== SUBREG
3436 && MODES_TIEABLE_P (GET_MODE (x
),
3437 GET_MODE (SUBREG_REG (to
))))
3439 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3442 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3444 #ifdef CANNOT_CHANGE_MODE_CLASS
3446 && GET_CODE (to
) == REG
3447 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3448 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3451 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3454 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3458 /* If we are in a SET_DEST, suppress most cases unless we
3459 have gone inside a MEM, in which case we want to
3460 simplify the address. We assume here that things that
3461 are actually part of the destination have their inner
3462 parts in the first expression. This is true for SUBREG,
3463 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3464 things aside from REG and MEM that should appear in a
3466 new = subst (XEXP (x
, i
), from
, to
,
3468 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3469 || code
== ZERO_EXTRACT
))
3471 && i
== 0), unique_copy
);
3473 /* If we found that we will have to reject this combination,
3474 indicate that by returning the CLOBBER ourselves, rather than
3475 an expression containing it. This will speed things up as
3476 well as prevent accidents where two CLOBBERs are considered
3477 to be equal, thus producing an incorrect simplification. */
3479 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3482 if (GET_CODE (x
) == SUBREG
3483 && (GET_CODE (new) == CONST_INT
3484 || GET_CODE (new) == CONST_DOUBLE
))
3486 enum machine_mode mode
= GET_MODE (x
);
3488 x
= simplify_subreg (GET_MODE (x
), new,
3489 GET_MODE (SUBREG_REG (x
)),
3492 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3494 else if (GET_CODE (new) == CONST_INT
3495 && GET_CODE (x
) == ZERO_EXTEND
)
3497 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3498 new, GET_MODE (XEXP (x
, 0)));
3503 SUBST (XEXP (x
, i
), new);
3508 /* Try to simplify X. If the simplification changed the code, it is likely
3509 that further simplification will help, so loop, but limit the number
3510 of repetitions that will be performed. */
3512 for (i
= 0; i
< 4; i
++)
3514 /* If X is sufficiently simple, don't bother trying to do anything
3516 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3517 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3519 if (GET_CODE (x
) == code
)
3522 code
= GET_CODE (x
);
3524 /* We no longer know the original mode of operand 0 since we
3525 have changed the form of X) */
3526 op0_mode
= VOIDmode
;
3532 /* Simplify X, a piece of RTL. We just operate on the expression at the
3533 outer level; call `subst' to simplify recursively. Return the new
3536 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3537 will be the iteration even if an expression with a code different from
3538 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3541 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int last
,
3544 enum rtx_code code
= GET_CODE (x
);
3545 enum machine_mode mode
= GET_MODE (x
);
3550 /* If this is a commutative operation, put a constant last and a complex
3551 expression first. We don't need to do this for comparisons here. */
3552 if (GET_RTX_CLASS (code
) == 'c'
3553 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3556 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3557 SUBST (XEXP (x
, 1), temp
);
3560 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3561 sign extension of a PLUS with a constant, reverse the order of the sign
3562 extension and the addition. Note that this not the same as the original
3563 code, but overflow is undefined for signed values. Also note that the
3564 PLUS will have been partially moved "inside" the sign-extension, so that
3565 the first operand of X will really look like:
3566 (ashiftrt (plus (ashift A C4) C5) C4).
3568 (plus (ashiftrt (ashift A C4) C2) C4)
3569 and replace the first operand of X with that expression. Later parts
3570 of this function may simplify the expression further.
3572 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3573 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3574 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3576 We do this to simplify address expressions. */
3578 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3579 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3580 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3581 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3582 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3583 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3584 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3585 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3586 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3587 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3588 XEXP (XEXP (x
, 0), 1))) != 0)
3591 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3592 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3593 INTVAL (XEXP (XEXP (x
, 0), 1)));
3595 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3596 INTVAL (XEXP (XEXP (x
, 0), 1)));
3598 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3601 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3602 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3603 things. Check for cases where both arms are testing the same
3606 Don't do anything if all operands are very simple. */
3608 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3609 || GET_RTX_CLASS (code
) == '<')
3610 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3611 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3612 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3614 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3615 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3616 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3618 || (GET_RTX_CLASS (code
) == '1'
3619 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3620 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3621 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3624 rtx cond
, true_rtx
, false_rtx
;
3626 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3628 /* If everything is a comparison, what we have is highly unlikely
3629 to be simpler, so don't use it. */
3630 && ! (GET_RTX_CLASS (code
) == '<'
3631 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3632 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3634 rtx cop1
= const0_rtx
;
3635 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3637 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3640 /* Simplify the alternative arms; this may collapse the true and
3641 false arms to store-flag values. Be careful to use copy_rtx
3642 here since true_rtx or false_rtx might share RTL with x as a
3643 result of the if_then_else_cond call above. */
3644 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3645 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3647 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3648 is unlikely to be simpler. */
3649 if (general_operand (true_rtx
, VOIDmode
)
3650 && general_operand (false_rtx
, VOIDmode
))
3652 enum rtx_code reversed
;
3654 /* Restarting if we generate a store-flag expression will cause
3655 us to loop. Just drop through in this case. */
3657 /* If the result values are STORE_FLAG_VALUE and zero, we can
3658 just make the comparison operation. */
3659 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3660 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3661 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3662 && ((reversed
= reversed_comparison_code_parts
3663 (cond_code
, cond
, cop1
, NULL
))
3665 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3667 /* Likewise, we can make the negate of a comparison operation
3668 if the result values are - STORE_FLAG_VALUE and zero. */
3669 else if (GET_CODE (true_rtx
) == CONST_INT
3670 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3671 && false_rtx
== const0_rtx
)
3672 x
= simplify_gen_unary (NEG
, mode
,
3673 gen_binary (cond_code
, mode
, cond
,
3676 else if (GET_CODE (false_rtx
) == CONST_INT
3677 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3678 && true_rtx
== const0_rtx
3679 && ((reversed
= reversed_comparison_code_parts
3680 (cond_code
, cond
, cop1
, NULL
))
3682 x
= simplify_gen_unary (NEG
, mode
,
3683 gen_binary (reversed
, mode
,
3687 return gen_rtx_IF_THEN_ELSE (mode
,
3688 gen_binary (cond_code
, VOIDmode
,
3690 true_rtx
, false_rtx
);
3692 code
= GET_CODE (x
);
3693 op0_mode
= VOIDmode
;
3698 /* Try to fold this expression in case we have constants that weren't
3701 switch (GET_RTX_CLASS (code
))
3704 if (op0_mode
== VOIDmode
)
3705 op0_mode
= GET_MODE (XEXP (x
, 0));
3706 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3710 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3711 if (cmp_mode
== VOIDmode
)
3713 cmp_mode
= GET_MODE (XEXP (x
, 1));
3714 if (cmp_mode
== VOIDmode
)
3715 cmp_mode
= op0_mode
;
3717 temp
= simplify_relational_operation (code
, cmp_mode
,
3718 XEXP (x
, 0), XEXP (x
, 1));
3720 #ifdef FLOAT_STORE_FLAG_VALUE
3721 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3723 if (temp
== const0_rtx
)
3724 temp
= CONST0_RTX (mode
);
3726 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3733 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3737 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3738 XEXP (x
, 1), XEXP (x
, 2));
3745 code
= GET_CODE (temp
);
3746 op0_mode
= VOIDmode
;
3747 mode
= GET_MODE (temp
);
3750 /* First see if we can apply the inverse distributive law. */
3751 if (code
== PLUS
|| code
== MINUS
3752 || code
== AND
|| code
== IOR
|| code
== XOR
)
3754 x
= apply_distributive_law (x
);
3755 code
= GET_CODE (x
);
3756 op0_mode
= VOIDmode
;
3759 /* If CODE is an associative operation not otherwise handled, see if we
3760 can associate some operands. This can win if they are constants or
3761 if they are logically related (i.e. (a & b) & a). */
3762 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3763 || code
== AND
|| code
== IOR
|| code
== XOR
3764 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3765 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3766 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3768 if (GET_CODE (XEXP (x
, 0)) == code
)
3770 rtx other
= XEXP (XEXP (x
, 0), 0);
3771 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3772 rtx inner_op1
= XEXP (x
, 1);
3775 /* Make sure we pass the constant operand if any as the second
3776 one if this is a commutative operation. */
3777 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3779 rtx tem
= inner_op0
;
3780 inner_op0
= inner_op1
;
3783 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3784 : code
== DIV
? MULT
3786 mode
, inner_op0
, inner_op1
);
3788 /* For commutative operations, try the other pair if that one
3790 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3792 other
= XEXP (XEXP (x
, 0), 1);
3793 inner
= simplify_binary_operation (code
, mode
,
3794 XEXP (XEXP (x
, 0), 0),
3799 return gen_binary (code
, mode
, other
, inner
);
3803 /* A little bit of algebraic simplification here. */
3807 /* Ensure that our address has any ASHIFTs converted to MULT in case
3808 address-recognizing predicates are called later. */
3809 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3810 SUBST (XEXP (x
, 0), temp
);
3814 if (op0_mode
== VOIDmode
)
3815 op0_mode
= GET_MODE (SUBREG_REG (x
));
3817 /* simplify_subreg can't use gen_lowpart_for_combine. */
3818 if (CONSTANT_P (SUBREG_REG (x
))
3819 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3820 /* Don't call gen_lowpart_for_combine if the inner mode
3821 is VOIDmode and we cannot simplify it, as SUBREG without
3822 inner mode is invalid. */
3823 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3824 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3825 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3827 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3831 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3837 /* Don't change the mode of the MEM if that would change the meaning
3839 if (GET_CODE (SUBREG_REG (x
)) == MEM
3840 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3841 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3842 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3844 /* Note that we cannot do any narrowing for non-constants since
3845 we might have been counting on using the fact that some bits were
3846 zero. We now do this in the SET. */
3851 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3852 && subreg_lowpart_p (XEXP (x
, 0))
3853 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3854 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3855 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3856 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3858 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3860 x
= gen_rtx_ROTATE (inner_mode
,
3861 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3863 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3864 return gen_lowpart_for_combine (mode
, x
);
3867 /* Apply De Morgan's laws to reduce number of patterns for machines
3868 with negating logical insns (and-not, nand, etc.). If result has
3869 only one NOT, put it first, since that is how the patterns are
3872 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3874 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3875 enum machine_mode op_mode
;
3877 op_mode
= GET_MODE (in1
);
3878 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3880 op_mode
= GET_MODE (in2
);
3881 if (op_mode
== VOIDmode
)
3883 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3885 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3888 in2
= in1
; in1
= tem
;
3891 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3897 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3898 if (GET_CODE (XEXP (x
, 0)) == XOR
3899 && XEXP (XEXP (x
, 0), 1) == const1_rtx
3900 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3901 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3903 temp
= expand_compound_operation (XEXP (x
, 0));
3905 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3906 replaced by (lshiftrt X C). This will convert
3907 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3909 if (GET_CODE (temp
) == ASHIFTRT
3910 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3911 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3912 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3913 INTVAL (XEXP (temp
, 1)));
3915 /* If X has only a single bit that might be nonzero, say, bit I, convert
3916 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3917 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3918 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3919 or a SUBREG of one since we'd be making the expression more
3920 complex if it was just a register. */
3922 if (GET_CODE (temp
) != REG
3923 && ! (GET_CODE (temp
) == SUBREG
3924 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3925 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3927 rtx temp1
= simplify_shift_const
3928 (NULL_RTX
, ASHIFTRT
, mode
,
3929 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3930 GET_MODE_BITSIZE (mode
) - 1 - i
),
3931 GET_MODE_BITSIZE (mode
) - 1 - i
);
3933 /* If all we did was surround TEMP with the two shifts, we
3934 haven't improved anything, so don't use it. Otherwise,
3935 we are better off with TEMP1. */
3936 if (GET_CODE (temp1
) != ASHIFTRT
3937 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3938 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3944 /* We can't handle truncation to a partial integer mode here
3945 because we don't know the real bitsize of the partial
3947 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3950 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3951 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3952 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3954 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3955 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3957 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3958 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3959 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3960 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3961 return XEXP (XEXP (x
, 0), 0);
3963 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3964 (OP:SI foo:SI) if OP is NEG or ABS. */
3965 if ((GET_CODE (XEXP (x
, 0)) == ABS
3966 || GET_CODE (XEXP (x
, 0)) == NEG
)
3967 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3968 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3969 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3970 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3971 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
3973 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3975 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3976 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3977 && subreg_lowpart_p (XEXP (x
, 0)))
3978 return SUBREG_REG (XEXP (x
, 0));
3980 /* If we know that the value is already truncated, we can
3981 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3982 is nonzero for the corresponding modes. But don't do this
3983 for an (LSHIFTRT (MULT ...)) since this will cause problems
3984 with the umulXi3_highpart patterns. */
3985 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3986 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3987 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3988 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
3989 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3990 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
3991 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3993 /* A truncate of a comparison can be replaced with a subreg if
3994 STORE_FLAG_VALUE permits. This is like the previous test,
3995 but it works even if the comparison is done in a mode larger
3996 than HOST_BITS_PER_WIDE_INT. */
3997 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3998 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3999 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4000 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4002 /* Similarly, a truncate of a register whose value is a
4003 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4005 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4006 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4007 && (temp
= get_last_value (XEXP (x
, 0)))
4008 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4009 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4013 case FLOAT_TRUNCATE
:
4014 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4015 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4016 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4017 return XEXP (XEXP (x
, 0), 0);
4019 /* (float_truncate:SF (float_truncate:DF foo:XF))
4020 = (float_truncate:SF foo:XF).
4021 This may eliminate double rounding, so it is unsafe.
4023 (float_truncate:SF (float_extend:XF foo:DF))
4024 = (float_truncate:SF foo:DF).
4026 (float_truncate:DF (float_extend:XF foo:SF))
4027 = (float_extend:SF foo:DF). */
4028 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4029 && flag_unsafe_math_optimizations
)
4030 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4031 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4033 > GET_MODE_SIZE (mode
)
4034 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4036 XEXP (XEXP (x
, 0), 0), mode
);
4038 /* (float_truncate (float x)) is (float x) */
4039 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4040 && (flag_unsafe_math_optimizations
4041 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4042 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4043 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4044 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4045 return simplify_gen_unary (FLOAT
, mode
,
4046 XEXP (XEXP (x
, 0), 0),
4047 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4049 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4050 (OP:SF foo:SF) if OP is NEG or ABS. */
4051 if ((GET_CODE (XEXP (x
, 0)) == ABS
4052 || GET_CODE (XEXP (x
, 0)) == NEG
)
4053 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4054 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4055 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4056 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4058 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4059 is (float_truncate:SF x). */
4060 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4061 && subreg_lowpart_p (XEXP (x
, 0))
4062 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4063 return SUBREG_REG (XEXP (x
, 0));
4066 /* (float_extend (float_extend x)) is (float_extend x)
4068 (float_extend (float x)) is (float x) assuming that double
4069 rounding can't happen.
4071 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4072 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4073 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4074 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4075 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4076 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4077 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4078 XEXP (XEXP (x
, 0), 0),
4079 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4084 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4085 using cc0, in which case we want to leave it as a COMPARE
4086 so we can distinguish it from a register-register-copy. */
4087 if (XEXP (x
, 1) == const0_rtx
)
4090 /* x - 0 is the same as x unless x's mode has signed zeros and
4091 allows rounding towards -infinity. Under those conditions,
4093 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4094 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4095 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4101 /* (const (const X)) can become (const X). Do it this way rather than
4102 returning the inner CONST since CONST can be shared with a
4104 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4105 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4110 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4111 can add in an offset. find_split_point will split this address up
4112 again if it doesn't match. */
4113 if (GET_CODE (XEXP (x
, 0)) == HIGH
4114 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4120 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4122 if (GET_CODE (XEXP (x
, 0)) == MULT
4123 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4127 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4128 in2
= XEXP (XEXP (x
, 0), 1);
4129 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4130 gen_binary (MULT
, mode
, in1
, in2
));
4133 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4134 outermost. That's because that's the way indexed addresses are
4135 supposed to appear. This code used to check many more cases, but
4136 they are now checked elsewhere. */
4137 if (GET_CODE (XEXP (x
, 0)) == PLUS
4138 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4139 return gen_binary (PLUS
, mode
,
4140 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4142 XEXP (XEXP (x
, 0), 1));
4144 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4145 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4146 bit-field and can be replaced by either a sign_extend or a
4147 sign_extract. The `and' may be a zero_extend and the two
4148 <c>, -<c> constants may be reversed. */
4149 if (GET_CODE (XEXP (x
, 0)) == XOR
4150 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4151 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4152 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4153 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4154 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4155 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4156 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4157 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4158 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4159 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4160 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4161 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4162 == (unsigned int) i
+ 1))))
4163 return simplify_shift_const
4164 (NULL_RTX
, ASHIFTRT
, mode
,
4165 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4166 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4167 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4168 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4170 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4171 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4172 is 1. This produces better code than the alternative immediately
4174 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4175 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4176 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4177 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4178 XEXP (XEXP (x
, 0), 0),
4179 XEXP (XEXP (x
, 0), 1))))
4181 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4183 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4184 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4185 the bitsize of the mode - 1. This allows simplification of
4186 "a = (b & 8) == 0;" */
4187 if (XEXP (x
, 1) == constm1_rtx
4188 && GET_CODE (XEXP (x
, 0)) != REG
4189 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4190 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4191 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4192 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4193 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4194 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4195 GET_MODE_BITSIZE (mode
) - 1),
4196 GET_MODE_BITSIZE (mode
) - 1);
4198 /* If we are adding two things that have no bits in common, convert
4199 the addition into an IOR. This will often be further simplified,
4200 for example in cases like ((a & 1) + (a & 2)), which can
4203 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4204 && (nonzero_bits (XEXP (x
, 0), mode
)
4205 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4207 /* Try to simplify the expression further. */
4208 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4209 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4211 /* If we could, great. If not, do not go ahead with the IOR
4212 replacement, since PLUS appears in many special purpose
4213 address arithmetic instructions. */
4214 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4220 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4221 by reversing the comparison code if valid. */
4222 if (STORE_FLAG_VALUE
== 1
4223 && XEXP (x
, 0) == const1_rtx
4224 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4225 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4226 XEXP (XEXP (x
, 1), 0),
4227 XEXP (XEXP (x
, 1), 1))))
4230 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4231 (and <foo> (const_int pow2-1)) */
4232 if (GET_CODE (XEXP (x
, 1)) == AND
4233 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4234 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4235 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4236 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4237 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4239 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4241 if (GET_CODE (XEXP (x
, 1)) == MULT
4242 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4246 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4247 in2
= XEXP (XEXP (x
, 1), 1);
4248 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4252 /* Canonicalize (minus (neg A) (mult B C)) to
4253 (minus (mult (neg B) C) A). */
4254 if (GET_CODE (XEXP (x
, 1)) == MULT
4255 && GET_CODE (XEXP (x
, 0)) == NEG
)
4259 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4260 in2
= XEXP (XEXP (x
, 1), 1);
4261 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4262 XEXP (XEXP (x
, 0), 0));
4265 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4267 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4268 return gen_binary (MINUS
, mode
,
4269 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4270 XEXP (XEXP (x
, 1), 0)),
4271 XEXP (XEXP (x
, 1), 1));
4275 /* If we have (mult (plus A B) C), apply the distributive law and then
4276 the inverse distributive law to see if things simplify. This
4277 occurs mostly in addresses, often when unrolling loops. */
4279 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4281 x
= apply_distributive_law
4282 (gen_binary (PLUS
, mode
,
4283 gen_binary (MULT
, mode
,
4284 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4285 gen_binary (MULT
, mode
,
4286 XEXP (XEXP (x
, 0), 1),
4287 copy_rtx (XEXP (x
, 1)))));
4289 if (GET_CODE (x
) != MULT
)
4292 /* Try simplify a*(b/c) as (a*b)/c. */
4293 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4294 && GET_CODE (XEXP (x
, 0)) == DIV
)
4296 rtx tem
= simplify_binary_operation (MULT
, mode
,
4297 XEXP (XEXP (x
, 0), 0),
4300 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4305 /* If this is a divide by a power of two, treat it as a shift if
4306 its first operand is a shift. */
4307 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4308 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4309 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4310 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4311 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4312 || GET_CODE (XEXP (x
, 0)) == ROTATE
4313 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4314 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4318 case GT
: case GTU
: case GE
: case GEU
:
4319 case LT
: case LTU
: case LE
: case LEU
:
4320 case UNEQ
: case LTGT
:
4321 case UNGT
: case UNGE
:
4322 case UNLT
: case UNLE
:
4323 case UNORDERED
: case ORDERED
:
4324 /* If the first operand is a condition code, we can't do anything
4326 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4327 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4328 && ! CC0_P (XEXP (x
, 0))))
4330 rtx op0
= XEXP (x
, 0);
4331 rtx op1
= XEXP (x
, 1);
4332 enum rtx_code new_code
;
4334 if (GET_CODE (op0
) == COMPARE
)
4335 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4337 /* Simplify our comparison, if possible. */
4338 new_code
= simplify_comparison (code
, &op0
, &op1
);
4340 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4341 if only the low-order bit is possibly nonzero in X (such as when
4342 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4343 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4344 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4347 Remove any ZERO_EXTRACT we made when thinking this was a
4348 comparison. It may now be simpler to use, e.g., an AND. If a
4349 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4350 the call to make_compound_operation in the SET case. */
4352 if (STORE_FLAG_VALUE
== 1
4353 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4354 && op1
== const0_rtx
4355 && mode
== GET_MODE (op0
)
4356 && nonzero_bits (op0
, mode
) == 1)
4357 return gen_lowpart_for_combine (mode
,
4358 expand_compound_operation (op0
));
4360 else if (STORE_FLAG_VALUE
== 1
4361 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4362 && op1
== const0_rtx
4363 && mode
== GET_MODE (op0
)
4364 && (num_sign_bit_copies (op0
, mode
)
4365 == GET_MODE_BITSIZE (mode
)))
4367 op0
= expand_compound_operation (op0
);
4368 return simplify_gen_unary (NEG
, mode
,
4369 gen_lowpart_for_combine (mode
, op0
),
4373 else if (STORE_FLAG_VALUE
== 1
4374 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4375 && op1
== const0_rtx
4376 && mode
== GET_MODE (op0
)
4377 && nonzero_bits (op0
, mode
) == 1)
4379 op0
= expand_compound_operation (op0
);
4380 return gen_binary (XOR
, mode
,
4381 gen_lowpart_for_combine (mode
, op0
),
4385 else if (STORE_FLAG_VALUE
== 1
4386 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4387 && op1
== const0_rtx
4388 && mode
== GET_MODE (op0
)
4389 && (num_sign_bit_copies (op0
, mode
)
4390 == GET_MODE_BITSIZE (mode
)))
4392 op0
= expand_compound_operation (op0
);
4393 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4396 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4398 if (STORE_FLAG_VALUE
== -1
4399 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4400 && op1
== const0_rtx
4401 && (num_sign_bit_copies (op0
, mode
)
4402 == GET_MODE_BITSIZE (mode
)))
4403 return gen_lowpart_for_combine (mode
,
4404 expand_compound_operation (op0
));
4406 else if (STORE_FLAG_VALUE
== -1
4407 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4408 && op1
== const0_rtx
4409 && mode
== GET_MODE (op0
)
4410 && nonzero_bits (op0
, mode
) == 1)
4412 op0
= expand_compound_operation (op0
);
4413 return simplify_gen_unary (NEG
, mode
,
4414 gen_lowpart_for_combine (mode
, op0
),
4418 else if (STORE_FLAG_VALUE
== -1
4419 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4420 && op1
== const0_rtx
4421 && mode
== GET_MODE (op0
)
4422 && (num_sign_bit_copies (op0
, mode
)
4423 == GET_MODE_BITSIZE (mode
)))
4425 op0
= expand_compound_operation (op0
);
4426 return simplify_gen_unary (NOT
, mode
,
4427 gen_lowpart_for_combine (mode
, op0
),
4431 /* If X is 0/1, (eq X 0) is X-1. */
4432 else if (STORE_FLAG_VALUE
== -1
4433 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4434 && op1
== const0_rtx
4435 && mode
== GET_MODE (op0
)
4436 && nonzero_bits (op0
, mode
) == 1)
4438 op0
= expand_compound_operation (op0
);
4439 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4442 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4443 one bit that might be nonzero, we can convert (ne x 0) to
4444 (ashift x c) where C puts the bit in the sign bit. Remove any
4445 AND with STORE_FLAG_VALUE when we are done, since we are only
4446 going to test the sign bit. */
4447 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4448 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4449 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4450 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4451 && op1
== const0_rtx
4452 && mode
== GET_MODE (op0
)
4453 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4455 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4456 expand_compound_operation (op0
),
4457 GET_MODE_BITSIZE (mode
) - 1 - i
);
4458 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4464 /* If the code changed, return a whole new comparison. */
4465 if (new_code
!= code
)
4466 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4468 /* Otherwise, keep this operation, but maybe change its operands.
4469 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4470 SUBST (XEXP (x
, 0), op0
);
4471 SUBST (XEXP (x
, 1), op1
);
4476 return simplify_if_then_else (x
);
4482 /* If we are processing SET_DEST, we are done. */
4486 return expand_compound_operation (x
);
4489 return simplify_set (x
);
4494 return simplify_logical (x
, last
);
4497 /* (abs (neg <foo>)) -> (abs <foo>) */
4498 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4499 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4501 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4503 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4506 /* If operand is something known to be positive, ignore the ABS. */
4507 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4508 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4509 <= HOST_BITS_PER_WIDE_INT
)
4510 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4511 & ((HOST_WIDE_INT
) 1
4512 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4516 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4517 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4518 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4523 /* (ffs (*_extend <X>)) = (ffs <X>) */
4524 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4525 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4526 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4531 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4532 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4533 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4537 /* (float (sign_extend <X>)) = (float <X>). */
4538 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4539 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4547 /* If this is a shift by a constant amount, simplify it. */
4548 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4549 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4550 INTVAL (XEXP (x
, 1)));
4552 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4554 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4556 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4563 rtx op0
= XEXP (x
, 0);
4564 rtx op1
= XEXP (x
, 1);
4567 if (GET_CODE (op1
) != PARALLEL
)
4569 len
= XVECLEN (op1
, 0);
4571 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4572 && GET_CODE (op0
) == VEC_CONCAT
)
4574 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4576 /* Try to find the element in the VEC_CONCAT. */
4579 if (GET_MODE (op0
) == GET_MODE (x
))
4581 if (GET_CODE (op0
) == VEC_CONCAT
)
4583 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4584 if (op0_size
< offset
)
4585 op0
= XEXP (op0
, 0);
4589 op0
= XEXP (op0
, 1);
4607 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4610 simplify_if_then_else (rtx x
)
4612 enum machine_mode mode
= GET_MODE (x
);
4613 rtx cond
= XEXP (x
, 0);
4614 rtx true_rtx
= XEXP (x
, 1);
4615 rtx false_rtx
= XEXP (x
, 2);
4616 enum rtx_code true_code
= GET_CODE (cond
);
4617 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4620 enum rtx_code false_code
;
4623 /* Simplify storing of the truth value. */
4624 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4625 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4627 /* Also when the truth value has to be reversed. */
4629 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4630 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4634 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4635 in it is being compared against certain values. Get the true and false
4636 comparisons and see if that says anything about the value of each arm. */
4639 && ((false_code
= combine_reversed_comparison_code (cond
))
4641 && GET_CODE (XEXP (cond
, 0)) == REG
)
4644 rtx from
= XEXP (cond
, 0);
4645 rtx true_val
= XEXP (cond
, 1);
4646 rtx false_val
= true_val
;
4649 /* If FALSE_CODE is EQ, swap the codes and arms. */
4651 if (false_code
== EQ
)
4653 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4654 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4657 /* If we are comparing against zero and the expression being tested has
4658 only a single bit that might be nonzero, that is its value when it is
4659 not equal to zero. Similarly if it is known to be -1 or 0. */
4661 if (true_code
== EQ
&& true_val
== const0_rtx
4662 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4663 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4664 else if (true_code
== EQ
&& true_val
== const0_rtx
4665 && (num_sign_bit_copies (from
, GET_MODE (from
))
4666 == GET_MODE_BITSIZE (GET_MODE (from
))))
4667 false_code
= EQ
, false_val
= constm1_rtx
;
4669 /* Now simplify an arm if we know the value of the register in the
4670 branch and it is used in the arm. Be careful due to the potential
4671 of locally-shared RTL. */
4673 if (reg_mentioned_p (from
, true_rtx
))
4674 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4676 pc_rtx
, pc_rtx
, 0, 0);
4677 if (reg_mentioned_p (from
, false_rtx
))
4678 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4680 pc_rtx
, pc_rtx
, 0, 0);
4682 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4683 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4685 true_rtx
= XEXP (x
, 1);
4686 false_rtx
= XEXP (x
, 2);
4687 true_code
= GET_CODE (cond
);
4690 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4691 reversed, do so to avoid needing two sets of patterns for
4692 subtract-and-branch insns. Similarly if we have a constant in the true
4693 arm, the false arm is the same as the first operand of the comparison, or
4694 the false arm is more complicated than the true arm. */
4697 && combine_reversed_comparison_code (cond
) != UNKNOWN
4698 && (true_rtx
== pc_rtx
4699 || (CONSTANT_P (true_rtx
)
4700 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4701 || true_rtx
== const0_rtx
4702 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4703 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4704 || (GET_CODE (true_rtx
) == SUBREG
4705 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4706 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4707 || reg_mentioned_p (true_rtx
, false_rtx
)
4708 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4710 true_code
= reversed_comparison_code (cond
, NULL
);
4712 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4715 SUBST (XEXP (x
, 1), false_rtx
);
4716 SUBST (XEXP (x
, 2), true_rtx
);
4718 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4721 /* It is possible that the conditional has been simplified out. */
4722 true_code
= GET_CODE (cond
);
4723 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4726 /* If the two arms are identical, we don't need the comparison. */
4728 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4731 /* Convert a == b ? b : a to "a". */
4732 if (true_code
== EQ
&& ! side_effects_p (cond
)
4733 && !HONOR_NANS (mode
)
4734 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4735 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4737 else if (true_code
== NE
&& ! side_effects_p (cond
)
4738 && !HONOR_NANS (mode
)
4739 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4740 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4743 /* Look for cases where we have (abs x) or (neg (abs X)). */
4745 if (GET_MODE_CLASS (mode
) == MODE_INT
4746 && GET_CODE (false_rtx
) == NEG
4747 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4749 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4750 && ! side_effects_p (true_rtx
))
4755 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4759 simplify_gen_unary (NEG
, mode
,
4760 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4766 /* Look for MIN or MAX. */
4768 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4770 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4771 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4772 && ! side_effects_p (cond
))
4777 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4780 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4783 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4786 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4791 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4792 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4793 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4794 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4795 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4796 neither 1 or -1, but it isn't worth checking for. */
4798 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4800 && GET_MODE_CLASS (mode
) == MODE_INT
4801 && ! side_effects_p (x
))
4803 rtx t
= make_compound_operation (true_rtx
, SET
);
4804 rtx f
= make_compound_operation (false_rtx
, SET
);
4805 rtx cond_op0
= XEXP (cond
, 0);
4806 rtx cond_op1
= XEXP (cond
, 1);
4807 enum rtx_code op
= NIL
, extend_op
= NIL
;
4808 enum machine_mode m
= mode
;
4809 rtx z
= 0, c1
= NULL_RTX
;
4811 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4812 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4813 || GET_CODE (t
) == ASHIFT
4814 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4815 && rtx_equal_p (XEXP (t
, 0), f
))
4816 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4818 /* If an identity-zero op is commutative, check whether there
4819 would be a match if we swapped the operands. */
4820 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4821 || GET_CODE (t
) == XOR
)
4822 && rtx_equal_p (XEXP (t
, 1), f
))
4823 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4824 else if (GET_CODE (t
) == SIGN_EXTEND
4825 && (GET_CODE (XEXP (t
, 0)) == PLUS
4826 || GET_CODE (XEXP (t
, 0)) == MINUS
4827 || GET_CODE (XEXP (t
, 0)) == IOR
4828 || GET_CODE (XEXP (t
, 0)) == XOR
4829 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4830 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4831 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4832 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4833 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4834 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4835 && (num_sign_bit_copies (f
, GET_MODE (f
))
4837 (GET_MODE_BITSIZE (mode
)
4838 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4840 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4841 extend_op
= SIGN_EXTEND
;
4842 m
= GET_MODE (XEXP (t
, 0));
4844 else if (GET_CODE (t
) == SIGN_EXTEND
4845 && (GET_CODE (XEXP (t
, 0)) == PLUS
4846 || GET_CODE (XEXP (t
, 0)) == IOR
4847 || GET_CODE (XEXP (t
, 0)) == XOR
)
4848 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4849 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4850 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4851 && (num_sign_bit_copies (f
, GET_MODE (f
))
4853 (GET_MODE_BITSIZE (mode
)
4854 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4856 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4857 extend_op
= SIGN_EXTEND
;
4858 m
= GET_MODE (XEXP (t
, 0));
4860 else if (GET_CODE (t
) == ZERO_EXTEND
4861 && (GET_CODE (XEXP (t
, 0)) == PLUS
4862 || GET_CODE (XEXP (t
, 0)) == MINUS
4863 || GET_CODE (XEXP (t
, 0)) == IOR
4864 || GET_CODE (XEXP (t
, 0)) == XOR
4865 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4866 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4867 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4868 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4869 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4870 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4871 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4872 && ((nonzero_bits (f
, GET_MODE (f
))
4873 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4876 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4877 extend_op
= ZERO_EXTEND
;
4878 m
= GET_MODE (XEXP (t
, 0));
4880 else if (GET_CODE (t
) == ZERO_EXTEND
4881 && (GET_CODE (XEXP (t
, 0)) == PLUS
4882 || GET_CODE (XEXP (t
, 0)) == IOR
4883 || GET_CODE (XEXP (t
, 0)) == XOR
)
4884 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4885 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4886 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4887 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4888 && ((nonzero_bits (f
, GET_MODE (f
))
4889 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4892 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4893 extend_op
= ZERO_EXTEND
;
4894 m
= GET_MODE (XEXP (t
, 0));
4899 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4900 pc_rtx
, pc_rtx
, 0, 0);
4901 temp
= gen_binary (MULT
, m
, temp
,
4902 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4903 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4904 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4906 if (extend_op
!= NIL
)
4907 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4913 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4914 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4915 negation of a single bit, we can convert this operation to a shift. We
4916 can actually do this more generally, but it doesn't seem worth it. */
4918 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4919 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4920 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4921 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4922 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4923 == GET_MODE_BITSIZE (mode
))
4924 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4926 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4927 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4929 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4930 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4931 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4932 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
4933 == nonzero_bits (XEXP (cond
, 0), mode
)
4934 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
4935 return XEXP (cond
, 0);
4940 /* Simplify X, a SET expression. Return the new expression. */
4943 simplify_set (rtx x
)
4945 rtx src
= SET_SRC (x
);
4946 rtx dest
= SET_DEST (x
);
4947 enum machine_mode mode
4948 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4952 /* (set (pc) (return)) gets written as (return). */
4953 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4956 /* Now that we know for sure which bits of SRC we are using, see if we can
4957 simplify the expression for the object knowing that we only need the
4960 if (GET_MODE_CLASS (mode
) == MODE_INT
4961 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4963 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4964 SUBST (SET_SRC (x
), src
);
4967 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4968 the comparison result and try to simplify it unless we already have used
4969 undobuf.other_insn. */
4970 if ((GET_MODE_CLASS (mode
) == MODE_CC
4971 || GET_CODE (src
) == COMPARE
4973 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4974 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4975 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4976 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4978 enum rtx_code old_code
= GET_CODE (*cc_use
);
4979 enum rtx_code new_code
;
4981 int other_changed
= 0;
4982 enum machine_mode compare_mode
= GET_MODE (dest
);
4983 enum machine_mode tmp_mode
;
4985 if (GET_CODE (src
) == COMPARE
)
4986 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4988 op0
= src
, op1
= const0_rtx
;
4990 /* Check whether the comparison is known at compile time. */
4991 if (GET_MODE (op0
) != VOIDmode
)
4992 tmp_mode
= GET_MODE (op0
);
4993 else if (GET_MODE (op1
) != VOIDmode
)
4994 tmp_mode
= GET_MODE (op1
);
4996 tmp_mode
= compare_mode
;
4997 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
4998 if (tmp
!= NULL_RTX
)
5000 rtx pat
= PATTERN (other_insn
);
5001 undobuf
.other_insn
= other_insn
;
5002 SUBST (*cc_use
, tmp
);
5004 /* Attempt to simplify CC user. */
5005 if (GET_CODE (pat
) == SET
)
5007 rtx
new = simplify_rtx (SET_SRC (pat
));
5008 if (new != NULL_RTX
)
5009 SUBST (SET_SRC (pat
), new);
5012 /* Convert X into a no-op move. */
5013 SUBST (SET_DEST (x
), pc_rtx
);
5014 SUBST (SET_SRC (x
), pc_rtx
);
5018 /* Simplify our comparison, if possible. */
5019 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5021 #ifdef SELECT_CC_MODE
5022 /* If this machine has CC modes other than CCmode, check to see if we
5023 need to use a different CC mode here. */
5024 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5027 /* If the mode changed, we have to change SET_DEST, the mode in the
5028 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5029 a hard register, just build new versions with the proper mode. If it
5030 is a pseudo, we lose unless it is only time we set the pseudo, in
5031 which case we can safely change its mode. */
5032 if (compare_mode
!= GET_MODE (dest
))
5034 unsigned int regno
= REGNO (dest
);
5035 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5037 if (regno
< FIRST_PSEUDO_REGISTER
5038 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5040 if (regno
>= FIRST_PSEUDO_REGISTER
)
5041 SUBST (regno_reg_rtx
[regno
], new_dest
);
5043 SUBST (SET_DEST (x
), new_dest
);
5044 SUBST (XEXP (*cc_use
, 0), new_dest
);
5051 #endif /* SELECT_CC_MODE */
5053 /* If the code changed, we have to build a new comparison in
5054 undobuf.other_insn. */
5055 if (new_code
!= old_code
)
5057 int other_changed_previously
= other_changed
;
5058 unsigned HOST_WIDE_INT mask
;
5060 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5064 /* If the only change we made was to change an EQ into an NE or
5065 vice versa, OP0 has only one bit that might be nonzero, and OP1
5066 is zero, check if changing the user of the condition code will
5067 produce a valid insn. If it won't, we can keep the original code
5068 in that insn by surrounding our operation with an XOR. */
5070 if (((old_code
== NE
&& new_code
== EQ
)
5071 || (old_code
== EQ
&& new_code
== NE
))
5072 && ! other_changed_previously
&& op1
== const0_rtx
5073 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5074 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5076 rtx pat
= PATTERN (other_insn
), note
= 0;
5078 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5079 && ! check_asm_operands (pat
)))
5081 PUT_CODE (*cc_use
, old_code
);
5084 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5090 undobuf
.other_insn
= other_insn
;
5093 /* If we are now comparing against zero, change our source if
5094 needed. If we do not use cc0, we always have a COMPARE. */
5095 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5097 SUBST (SET_SRC (x
), op0
);
5103 /* Otherwise, if we didn't previously have a COMPARE in the
5104 correct mode, we need one. */
5105 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5107 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5112 /* Otherwise, update the COMPARE if needed. */
5113 SUBST (XEXP (src
, 0), op0
);
5114 SUBST (XEXP (src
, 1), op1
);
5119 /* Get SET_SRC in a form where we have placed back any
5120 compound expressions. Then do the checks below. */
5121 src
= make_compound_operation (src
, SET
);
5122 SUBST (SET_SRC (x
), src
);
5125 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5126 and X being a REG or (subreg (reg)), we may be able to convert this to
5127 (set (subreg:m2 x) (op)).
5129 We can always do this if M1 is narrower than M2 because that means that
5130 we only care about the low bits of the result.
5132 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5133 perform a narrower operation than requested since the high-order bits will
5134 be undefined. On machine where it is defined, this transformation is safe
5135 as long as M1 and M2 have the same number of words. */
5137 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5138 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5139 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5141 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5142 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5143 #ifndef WORD_REGISTER_OPERATIONS
5144 && (GET_MODE_SIZE (GET_MODE (src
))
5145 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5147 #ifdef CANNOT_CHANGE_MODE_CLASS
5148 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5149 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5150 GET_MODE (SUBREG_REG (src
)),
5153 && (GET_CODE (dest
) == REG
5154 || (GET_CODE (dest
) == SUBREG
5155 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5157 SUBST (SET_DEST (x
),
5158 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5160 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5162 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5166 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5169 && GET_CODE (src
) == SUBREG
5170 && subreg_lowpart_p (src
)
5171 && (GET_MODE_BITSIZE (GET_MODE (src
))
5172 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5174 rtx inner
= SUBREG_REG (src
);
5175 enum machine_mode inner_mode
= GET_MODE (inner
);
5177 /* Here we make sure that we don't have a sign bit on. */
5178 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5179 && (nonzero_bits (inner
, inner_mode
)
5180 < ((unsigned HOST_WIDE_INT
) 1
5181 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5183 SUBST (SET_SRC (x
), inner
);
5189 #ifdef LOAD_EXTEND_OP
5190 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5191 would require a paradoxical subreg. Replace the subreg with a
5192 zero_extend to avoid the reload that would otherwise be required. */
5194 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5195 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5196 && SUBREG_BYTE (src
) == 0
5197 && (GET_MODE_SIZE (GET_MODE (src
))
5198 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5199 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5202 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5203 GET_MODE (src
), SUBREG_REG (src
)));
5209 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5210 are comparing an item known to be 0 or -1 against 0, use a logical
5211 operation instead. Check for one of the arms being an IOR of the other
5212 arm with some value. We compute three terms to be IOR'ed together. In
5213 practice, at most two will be nonzero. Then we do the IOR's. */
5215 if (GET_CODE (dest
) != PC
5216 && GET_CODE (src
) == IF_THEN_ELSE
5217 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5218 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5219 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5220 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5221 #ifdef HAVE_conditional_move
5222 && ! can_conditionally_move_p (GET_MODE (src
))
5224 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5225 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5226 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5227 && ! side_effects_p (src
))
5229 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5230 ? XEXP (src
, 1) : XEXP (src
, 2));
5231 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5232 ? XEXP (src
, 2) : XEXP (src
, 1));
5233 rtx term1
= const0_rtx
, term2
, term3
;
5235 if (GET_CODE (true_rtx
) == IOR
5236 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5237 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5238 else if (GET_CODE (true_rtx
) == IOR
5239 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5240 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5241 else if (GET_CODE (false_rtx
) == IOR
5242 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5243 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5244 else if (GET_CODE (false_rtx
) == IOR
5245 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5246 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5248 term2
= gen_binary (AND
, GET_MODE (src
),
5249 XEXP (XEXP (src
, 0), 0), true_rtx
);
5250 term3
= gen_binary (AND
, GET_MODE (src
),
5251 simplify_gen_unary (NOT
, GET_MODE (src
),
5252 XEXP (XEXP (src
, 0), 0),
5257 gen_binary (IOR
, GET_MODE (src
),
5258 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5264 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5265 whole thing fail. */
5266 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5268 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5271 /* Convert this into a field assignment operation, if possible. */
5272 return make_field_assignment (x
);
5275 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5276 result. LAST is nonzero if this is the last retry. */
5279 simplify_logical (rtx x
, int last
)
5281 enum machine_mode mode
= GET_MODE (x
);
5282 rtx op0
= XEXP (x
, 0);
5283 rtx op1
= XEXP (x
, 1);
5286 switch (GET_CODE (x
))
5289 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5290 insn (and may simplify more). */
5291 if (GET_CODE (op0
) == XOR
5292 && rtx_equal_p (XEXP (op0
, 0), op1
)
5293 && ! side_effects_p (op1
))
5294 x
= gen_binary (AND
, mode
,
5295 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5298 if (GET_CODE (op0
) == XOR
5299 && rtx_equal_p (XEXP (op0
, 1), op1
)
5300 && ! side_effects_p (op1
))
5301 x
= gen_binary (AND
, mode
,
5302 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5305 /* Similarly for (~(A ^ B)) & A. */
5306 if (GET_CODE (op0
) == NOT
5307 && GET_CODE (XEXP (op0
, 0)) == XOR
5308 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5309 && ! side_effects_p (op1
))
5310 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5312 if (GET_CODE (op0
) == NOT
5313 && GET_CODE (XEXP (op0
, 0)) == XOR
5314 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5315 && ! side_effects_p (op1
))
5316 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5318 /* We can call simplify_and_const_int only if we don't lose
5319 any (sign) bits when converting INTVAL (op1) to
5320 "unsigned HOST_WIDE_INT". */
5321 if (GET_CODE (op1
) == CONST_INT
5322 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5323 || INTVAL (op1
) > 0))
5325 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5327 /* If we have (ior (and (X C1) C2)) and the next restart would be
5328 the last, simplify this by making C1 as small as possible
5331 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5332 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5333 && GET_CODE (op1
) == CONST_INT
)
5334 return gen_binary (IOR
, mode
,
5335 gen_binary (AND
, mode
, XEXP (op0
, 0),
5336 GEN_INT (INTVAL (XEXP (op0
, 1))
5337 & ~INTVAL (op1
))), op1
);
5339 if (GET_CODE (x
) != AND
)
5342 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5343 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5344 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5347 /* Convert (A | B) & A to A. */
5348 if (GET_CODE (op0
) == IOR
5349 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5350 || rtx_equal_p (XEXP (op0
, 1), op1
))
5351 && ! side_effects_p (XEXP (op0
, 0))
5352 && ! side_effects_p (XEXP (op0
, 1)))
5355 /* In the following group of tests (and those in case IOR below),
5356 we start with some combination of logical operations and apply
5357 the distributive law followed by the inverse distributive law.
5358 Most of the time, this results in no change. However, if some of
5359 the operands are the same or inverses of each other, simplifications
5362 For example, (and (ior A B) (not B)) can occur as the result of
5363 expanding a bit field assignment. When we apply the distributive
5364 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5365 which then simplifies to (and (A (not B))).
5367 If we have (and (ior A B) C), apply the distributive law and then
5368 the inverse distributive law to see if things simplify. */
5370 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5372 x
= apply_distributive_law
5373 (gen_binary (GET_CODE (op0
), mode
,
5374 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5375 gen_binary (AND
, mode
, XEXP (op0
, 1),
5377 if (GET_CODE (x
) != AND
)
5381 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5382 return apply_distributive_law
5383 (gen_binary (GET_CODE (op1
), mode
,
5384 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5385 gen_binary (AND
, mode
, XEXP (op1
, 1),
5388 /* Similarly, taking advantage of the fact that
5389 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5391 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5392 return apply_distributive_law
5393 (gen_binary (XOR
, mode
,
5394 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5395 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5398 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5399 return apply_distributive_law
5400 (gen_binary (XOR
, mode
,
5401 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5402 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5406 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5407 if (GET_CODE (op1
) == CONST_INT
5408 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5409 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5412 /* Convert (A & B) | A to A. */
5413 if (GET_CODE (op0
) == AND
5414 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5415 || rtx_equal_p (XEXP (op0
, 1), op1
))
5416 && ! side_effects_p (XEXP (op0
, 0))
5417 && ! side_effects_p (XEXP (op0
, 1)))
5420 /* If we have (ior (and A B) C), apply the distributive law and then
5421 the inverse distributive law to see if things simplify. */
5423 if (GET_CODE (op0
) == AND
)
5425 x
= apply_distributive_law
5426 (gen_binary (AND
, mode
,
5427 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5428 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5431 if (GET_CODE (x
) != IOR
)
5435 if (GET_CODE (op1
) == AND
)
5437 x
= apply_distributive_law
5438 (gen_binary (AND
, mode
,
5439 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5440 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5443 if (GET_CODE (x
) != IOR
)
5447 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5448 mode size to (rotate A CX). */
5450 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5451 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5452 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5453 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5454 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5455 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5456 == GET_MODE_BITSIZE (mode
)))
5457 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5458 (GET_CODE (op0
) == ASHIFT
5459 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5461 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5462 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5463 does not affect any of the bits in OP1, it can really be done
5464 as a PLUS and we can associate. We do this by seeing if OP1
5465 can be safely shifted left C bits. */
5466 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5467 && GET_CODE (XEXP (op0
, 0)) == PLUS
5468 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5469 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5470 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5472 int count
= INTVAL (XEXP (op0
, 1));
5473 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5475 if (mask
>> count
== INTVAL (op1
)
5476 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5478 SUBST (XEXP (XEXP (op0
, 0), 1),
5479 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5486 /* If we are XORing two things that have no bits in common,
5487 convert them into an IOR. This helps to detect rotation encoded
5488 using those methods and possibly other simplifications. */
5490 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5491 && (nonzero_bits (op0
, mode
)
5492 & nonzero_bits (op1
, mode
)) == 0)
5493 return (gen_binary (IOR
, mode
, op0
, op1
));
5495 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5496 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5499 int num_negated
= 0;
5501 if (GET_CODE (op0
) == NOT
)
5502 num_negated
++, op0
= XEXP (op0
, 0);
5503 if (GET_CODE (op1
) == NOT
)
5504 num_negated
++, op1
= XEXP (op1
, 0);
5506 if (num_negated
== 2)
5508 SUBST (XEXP (x
, 0), op0
);
5509 SUBST (XEXP (x
, 1), op1
);
5511 else if (num_negated
== 1)
5513 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5517 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5518 correspond to a machine insn or result in further simplifications
5519 if B is a constant. */
5521 if (GET_CODE (op0
) == AND
5522 && rtx_equal_p (XEXP (op0
, 1), op1
)
5523 && ! side_effects_p (op1
))
5524 return gen_binary (AND
, mode
,
5525 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5528 else if (GET_CODE (op0
) == AND
5529 && rtx_equal_p (XEXP (op0
, 0), op1
)
5530 && ! side_effects_p (op1
))
5531 return gen_binary (AND
, mode
,
5532 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5535 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5536 comparison if STORE_FLAG_VALUE is 1. */
5537 if (STORE_FLAG_VALUE
== 1
5538 && op1
== const1_rtx
5539 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5540 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5544 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5545 is (lt foo (const_int 0)), so we can perform the above
5546 simplification if STORE_FLAG_VALUE is 1. */
5548 if (STORE_FLAG_VALUE
== 1
5549 && op1
== const1_rtx
5550 && GET_CODE (op0
) == LSHIFTRT
5551 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5552 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5553 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5555 /* (xor (comparison foo bar) (const_int sign-bit))
5556 when STORE_FLAG_VALUE is the sign bit. */
5557 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5558 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5559 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5560 && op1
== const_true_rtx
5561 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5562 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5575 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5576 operations" because they can be replaced with two more basic operations.
5577 ZERO_EXTEND is also considered "compound" because it can be replaced with
5578 an AND operation, which is simpler, though only one operation.
5580 The function expand_compound_operation is called with an rtx expression
5581 and will convert it to the appropriate shifts and AND operations,
5582 simplifying at each stage.
5584 The function make_compound_operation is called to convert an expression
5585 consisting of shifts and ANDs into the equivalent compound expression.
5586 It is the inverse of this function, loosely speaking. */
5589 expand_compound_operation (rtx x
)
5591 unsigned HOST_WIDE_INT pos
= 0, len
;
5593 unsigned int modewidth
;
5596 switch (GET_CODE (x
))
5601 /* We can't necessarily use a const_int for a multiword mode;
5602 it depends on implicitly extending the value.
5603 Since we don't know the right way to extend it,
5604 we can't tell whether the implicit way is right.
5606 Even for a mode that is no wider than a const_int,
5607 we can't win, because we need to sign extend one of its bits through
5608 the rest of it, and we don't know which bit. */
5609 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5612 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5613 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5614 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5615 reloaded. If not for that, MEM's would very rarely be safe.
5617 Reject MODEs bigger than a word, because we might not be able
5618 to reference a two-register group starting with an arbitrary register
5619 (and currently gen_lowpart might crash for a SUBREG). */
5621 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5624 /* Reject MODEs that aren't scalar integers because turning vector
5625 or complex modes into shifts causes problems. */
5627 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5630 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5631 /* If the inner object has VOIDmode (the only way this can happen
5632 is if it is an ASM_OPERANDS), we can't do anything since we don't
5633 know how much masking to do. */
5642 /* If the operand is a CLOBBER, just return it. */
5643 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5646 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5647 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5648 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5651 /* Reject MODEs that aren't scalar integers because turning vector
5652 or complex modes into shifts causes problems. */
5654 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5657 len
= INTVAL (XEXP (x
, 1));
5658 pos
= INTVAL (XEXP (x
, 2));
5660 /* If this goes outside the object being extracted, replace the object
5661 with a (use (mem ...)) construct that only combine understands
5662 and is used only for this purpose. */
5663 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5664 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5666 if (BITS_BIG_ENDIAN
)
5667 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5674 /* Convert sign extension to zero extension, if we know that the high
5675 bit is not set, as this is easier to optimize. It will be converted
5676 back to cheaper alternative in make_extraction. */
5677 if (GET_CODE (x
) == SIGN_EXTEND
5678 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5679 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5680 & ~(((unsigned HOST_WIDE_INT
)
5681 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5685 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5686 rtx temp2
= expand_compound_operation (temp
);
5688 /* Make sure this is a profitable operation. */
5689 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5691 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5697 /* We can optimize some special cases of ZERO_EXTEND. */
5698 if (GET_CODE (x
) == ZERO_EXTEND
)
5700 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5701 know that the last value didn't have any inappropriate bits
5703 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5704 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5705 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5706 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5707 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5708 return XEXP (XEXP (x
, 0), 0);
5710 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5711 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5712 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5713 && subreg_lowpart_p (XEXP (x
, 0))
5714 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5715 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5716 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5717 return SUBREG_REG (XEXP (x
, 0));
5719 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5720 is a comparison and STORE_FLAG_VALUE permits. This is like
5721 the first case, but it works even when GET_MODE (x) is larger
5722 than HOST_WIDE_INT. */
5723 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5724 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5725 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5726 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5727 <= HOST_BITS_PER_WIDE_INT
)
5728 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5729 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5730 return XEXP (XEXP (x
, 0), 0);
5732 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5733 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5734 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5735 && subreg_lowpart_p (XEXP (x
, 0))
5736 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5737 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5738 <= HOST_BITS_PER_WIDE_INT
)
5739 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5740 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5741 return SUBREG_REG (XEXP (x
, 0));
5745 /* If we reach here, we want to return a pair of shifts. The inner
5746 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5747 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5748 logical depending on the value of UNSIGNEDP.
5750 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5751 converted into an AND of a shift.
5753 We must check for the case where the left shift would have a negative
5754 count. This can happen in a case like (x >> 31) & 255 on machines
5755 that can't shift by a constant. On those machines, we would first
5756 combine the shift with the AND to produce a variable-position
5757 extraction. Then the constant of 31 would be substituted in to produce
5758 a such a position. */
5760 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5761 if (modewidth
+ len
>= pos
)
5762 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5764 simplify_shift_const (NULL_RTX
, ASHIFT
,
5767 modewidth
- pos
- len
),
5770 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5771 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5772 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5775 ((HOST_WIDE_INT
) 1 << len
) - 1);
5777 /* Any other cases we can't handle. */
5780 /* If we couldn't do this for some reason, return the original
5782 if (GET_CODE (tem
) == CLOBBER
)
5788 /* X is a SET which contains an assignment of one object into
5789 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5790 or certain SUBREGS). If possible, convert it into a series of
5793 We half-heartedly support variable positions, but do not at all
5794 support variable lengths. */
5797 expand_field_assignment (rtx x
)
5800 rtx pos
; /* Always counts from low bit. */
5803 enum machine_mode compute_mode
;
5805 /* Loop until we find something we can't simplify. */
5808 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5809 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5811 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5812 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5813 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5815 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5816 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5818 inner
= XEXP (SET_DEST (x
), 0);
5819 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5820 pos
= XEXP (SET_DEST (x
), 2);
5822 /* If the position is constant and spans the width of INNER,
5823 surround INNER with a USE to indicate this. */
5824 if (GET_CODE (pos
) == CONST_INT
5825 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5826 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5828 if (BITS_BIG_ENDIAN
)
5830 if (GET_CODE (pos
) == CONST_INT
)
5831 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5833 else if (GET_CODE (pos
) == MINUS
5834 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5835 && (INTVAL (XEXP (pos
, 1))
5836 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5837 /* If position is ADJUST - X, new position is X. */
5838 pos
= XEXP (pos
, 0);
5840 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5841 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5847 /* A SUBREG between two modes that occupy the same numbers of words
5848 can be done by moving the SUBREG to the source. */
5849 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5850 /* We need SUBREGs to compute nonzero_bits properly. */
5851 && nonzero_sign_valid
5852 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5853 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5854 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5855 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5857 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5858 gen_lowpart_for_combine
5859 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5866 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5867 inner
= SUBREG_REG (inner
);
5869 compute_mode
= GET_MODE (inner
);
5871 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5872 if (! SCALAR_INT_MODE_P (compute_mode
))
5874 enum machine_mode imode
;
5876 /* Don't do anything for vector or complex integral types. */
5877 if (! FLOAT_MODE_P (compute_mode
))
5880 /* Try to find an integral mode to pun with. */
5881 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5882 if (imode
== BLKmode
)
5885 compute_mode
= imode
;
5886 inner
= gen_lowpart_for_combine (imode
, inner
);
5889 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5890 if (len
< HOST_BITS_PER_WIDE_INT
)
5891 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5895 /* Now compute the equivalent expression. Make a copy of INNER
5896 for the SET_DEST in case it is a MEM into which we will substitute;
5897 we don't want shared RTL in that case. */
5899 (VOIDmode
, copy_rtx (inner
),
5900 gen_binary (IOR
, compute_mode
,
5901 gen_binary (AND
, compute_mode
,
5902 simplify_gen_unary (NOT
, compute_mode
,
5908 gen_binary (ASHIFT
, compute_mode
,
5909 gen_binary (AND
, compute_mode
,
5910 gen_lowpart_for_combine
5911 (compute_mode
, SET_SRC (x
)),
5919 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5920 it is an RTX that represents a variable starting position; otherwise,
5921 POS is the (constant) starting bit position (counted from the LSB).
5923 INNER may be a USE. This will occur when we started with a bitfield
5924 that went outside the boundary of the object in memory, which is
5925 allowed on most machines. To isolate this case, we produce a USE
5926 whose mode is wide enough and surround the MEM with it. The only
5927 code that understands the USE is this routine. If it is not removed,
5928 it will cause the resulting insn not to match.
5930 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5933 IN_DEST is nonzero if this is a reference in the destination of a
5934 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5935 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5938 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5939 ZERO_EXTRACT should be built even for bits starting at bit 0.
5941 MODE is the desired mode of the result (if IN_DEST == 0).
5943 The result is an RTX for the extraction or NULL_RTX if the target
5947 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5948 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5949 int in_dest
, int in_compare
)
5951 /* This mode describes the size of the storage area
5952 to fetch the overall value from. Within that, we
5953 ignore the POS lowest bits, etc. */
5954 enum machine_mode is_mode
= GET_MODE (inner
);
5955 enum machine_mode inner_mode
;
5956 enum machine_mode wanted_inner_mode
= byte_mode
;
5957 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5958 enum machine_mode pos_mode
= word_mode
;
5959 enum machine_mode extraction_mode
= word_mode
;
5960 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5963 rtx orig_pos_rtx
= pos_rtx
;
5964 HOST_WIDE_INT orig_pos
;
5966 /* Get some information about INNER and get the innermost object. */
5967 if (GET_CODE (inner
) == USE
)
5968 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5969 /* We don't need to adjust the position because we set up the USE
5970 to pretend that it was a full-word object. */
5971 spans_byte
= 1, inner
= XEXP (inner
, 0);
5972 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5974 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5975 consider just the QI as the memory to extract from.
5976 The subreg adds or removes high bits; its mode is
5977 irrelevant to the meaning of this extraction,
5978 since POS and LEN count from the lsb. */
5979 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5980 is_mode
= GET_MODE (SUBREG_REG (inner
));
5981 inner
= SUBREG_REG (inner
);
5983 else if (GET_CODE (inner
) == ASHIFT
5984 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5985 && pos_rtx
== 0 && pos
== 0
5986 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
5988 /* We're extracting the least significant bits of an rtx
5989 (ashift X (const_int C)), where LEN > C. Extract the
5990 least significant (LEN - C) bits of X, giving an rtx
5991 whose mode is MODE, then shift it left C times. */
5992 new = make_extraction (mode
, XEXP (inner
, 0),
5993 0, 0, len
- INTVAL (XEXP (inner
, 1)),
5994 unsignedp
, in_dest
, in_compare
);
5996 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
5999 inner_mode
= GET_MODE (inner
);
6001 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6002 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6004 /* See if this can be done without an extraction. We never can if the
6005 width of the field is not the same as that of some integer mode. For
6006 registers, we can only avoid the extraction if the position is at the
6007 low-order bit and this is either not in the destination or we have the
6008 appropriate STRICT_LOW_PART operation available.
6010 For MEM, we can avoid an extract if the field starts on an appropriate
6011 boundary and we can change the mode of the memory reference. However,
6012 we cannot directly access the MEM if we have a USE and the underlying
6013 MEM is not TMODE. This combination means that MEM was being used in a
6014 context where bits outside its mode were being referenced; that is only
6015 valid in bit-field insns. */
6017 if (tmode
!= BLKmode
6018 && ! (spans_byte
&& inner_mode
!= tmode
)
6019 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6020 && GET_CODE (inner
) != MEM
6022 || (GET_CODE (inner
) == REG
6023 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6024 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6026 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6027 : BITS_PER_UNIT
)) == 0
6028 /* We can't do this if we are widening INNER_MODE (it
6029 may not be aligned, for one thing). */
6030 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6031 && (inner_mode
== tmode
6032 || (! mode_dependent_address_p (XEXP (inner
, 0))
6033 && ! MEM_VOLATILE_P (inner
))))))
6035 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6036 field. If the original and current mode are the same, we need not
6037 adjust the offset. Otherwise, we do if bytes big endian.
6039 If INNER is not a MEM, get a piece consisting of just the field
6040 of interest (in this case POS % BITS_PER_WORD must be 0). */
6042 if (GET_CODE (inner
) == MEM
)
6044 HOST_WIDE_INT offset
;
6046 /* POS counts from lsb, but make OFFSET count in memory order. */
6047 if (BYTES_BIG_ENDIAN
)
6048 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6050 offset
= pos
/ BITS_PER_UNIT
;
6052 new = adjust_address_nv (inner
, tmode
, offset
);
6054 else if (GET_CODE (inner
) == REG
)
6056 if (tmode
!= inner_mode
)
6058 /* We can't call gen_lowpart_for_combine in a DEST since we
6059 always want a SUBREG (see below) and it would sometimes
6060 return a new hard register. */
6063 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6065 if (WORDS_BIG_ENDIAN
6066 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6067 final_word
= ((GET_MODE_SIZE (inner_mode
)
6068 - GET_MODE_SIZE (tmode
))
6069 / UNITS_PER_WORD
) - final_word
;
6071 final_word
*= UNITS_PER_WORD
;
6072 if (BYTES_BIG_ENDIAN
&&
6073 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6074 final_word
+= (GET_MODE_SIZE (inner_mode
)
6075 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6077 /* Avoid creating invalid subregs, for example when
6078 simplifying (x>>32)&255. */
6079 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6082 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6085 new = gen_lowpart_for_combine (tmode
, inner
);
6091 new = force_to_mode (inner
, tmode
,
6092 len
>= HOST_BITS_PER_WIDE_INT
6093 ? ~(unsigned HOST_WIDE_INT
) 0
6094 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6097 /* If this extraction is going into the destination of a SET,
6098 make a STRICT_LOW_PART unless we made a MEM. */
6101 return (GET_CODE (new) == MEM
? new
6102 : (GET_CODE (new) != SUBREG
6103 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6104 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6109 if (GET_CODE (new) == CONST_INT
)
6110 return gen_int_mode (INTVAL (new), mode
);
6112 /* If we know that no extraneous bits are set, and that the high
6113 bit is not set, convert the extraction to the cheaper of
6114 sign and zero extension, that are equivalent in these cases. */
6115 if (flag_expensive_optimizations
6116 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6117 && ((nonzero_bits (new, tmode
)
6118 & ~(((unsigned HOST_WIDE_INT
)
6119 GET_MODE_MASK (tmode
))
6123 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6124 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6126 /* Prefer ZERO_EXTENSION, since it gives more information to
6128 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6133 /* Otherwise, sign- or zero-extend unless we already are in the
6136 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6140 /* Unless this is a COMPARE or we have a funny memory reference,
6141 don't do anything with zero-extending field extracts starting at
6142 the low-order bit since they are simple AND operations. */
6143 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6144 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6147 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6148 we would be spanning bytes or if the position is not a constant and the
6149 length is not 1. In all other cases, we would only be going outside
6150 our object in cases when an original shift would have been
6152 if (! spans_byte
&& GET_CODE (inner
) == MEM
6153 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6154 || (pos_rtx
!= 0 && len
!= 1)))
6157 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6158 and the mode for the result. */
6159 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6161 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6162 pos_mode
= mode_for_extraction (EP_insv
, 2);
6163 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6166 if (! in_dest
&& unsignedp
6167 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6169 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6170 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6171 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6174 if (! in_dest
&& ! unsignedp
6175 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6177 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6178 pos_mode
= mode_for_extraction (EP_extv
, 3);
6179 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6182 /* Never narrow an object, since that might not be safe. */
6184 if (mode
!= VOIDmode
6185 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6186 extraction_mode
= mode
;
6188 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6189 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6190 pos_mode
= GET_MODE (pos_rtx
);
6192 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6193 if we have to change the mode of memory and cannot, the desired mode is
6195 if (GET_CODE (inner
) != MEM
)
6196 wanted_inner_mode
= wanted_inner_reg_mode
;
6197 else if (inner_mode
!= wanted_inner_mode
6198 && (mode_dependent_address_p (XEXP (inner
, 0))
6199 || MEM_VOLATILE_P (inner
)))
6200 wanted_inner_mode
= extraction_mode
;
6204 if (BITS_BIG_ENDIAN
)
6206 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6207 BITS_BIG_ENDIAN style. If position is constant, compute new
6208 position. Otherwise, build subtraction.
6209 Note that POS is relative to the mode of the original argument.
6210 If it's a MEM we need to recompute POS relative to that.
6211 However, if we're extracting from (or inserting into) a register,
6212 we want to recompute POS relative to wanted_inner_mode. */
6213 int width
= (GET_CODE (inner
) == MEM
6214 ? GET_MODE_BITSIZE (is_mode
)
6215 : GET_MODE_BITSIZE (wanted_inner_mode
));
6218 pos
= width
- len
- pos
;
6221 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6222 /* POS may be less than 0 now, but we check for that below.
6223 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6226 /* If INNER has a wider mode, make it smaller. If this is a constant
6227 extract, try to adjust the byte to point to the byte containing
6229 if (wanted_inner_mode
!= VOIDmode
6230 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6231 && ((GET_CODE (inner
) == MEM
6232 && (inner_mode
== wanted_inner_mode
6233 || (! mode_dependent_address_p (XEXP (inner
, 0))
6234 && ! MEM_VOLATILE_P (inner
))))))
6238 /* The computations below will be correct if the machine is big
6239 endian in both bits and bytes or little endian in bits and bytes.
6240 If it is mixed, we must adjust. */
6242 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6243 adjust OFFSET to compensate. */
6244 if (BYTES_BIG_ENDIAN
6246 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6247 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6249 /* If this is a constant position, we can move to the desired byte. */
6252 offset
+= pos
/ BITS_PER_UNIT
;
6253 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6256 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6258 && is_mode
!= wanted_inner_mode
)
6259 offset
= (GET_MODE_SIZE (is_mode
)
6260 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6262 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6263 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6266 /* If INNER is not memory, we can always get it into the proper mode. If we
6267 are changing its mode, POS must be a constant and smaller than the size
6269 else if (GET_CODE (inner
) != MEM
)
6271 if (GET_MODE (inner
) != wanted_inner_mode
6273 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6276 inner
= force_to_mode (inner
, wanted_inner_mode
,
6278 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6279 ? ~(unsigned HOST_WIDE_INT
) 0
6280 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6285 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6286 have to zero extend. Otherwise, we can just use a SUBREG. */
6288 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6290 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6292 /* If we know that no extraneous bits are set, and that the high
6293 bit is not set, convert extraction to cheaper one - either
6294 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6296 if (flag_expensive_optimizations
6297 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6298 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6299 & ~(((unsigned HOST_WIDE_INT
)
6300 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6304 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6306 /* Prefer ZERO_EXTENSION, since it gives more information to
6308 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6313 else if (pos_rtx
!= 0
6314 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6315 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6317 /* Make POS_RTX unless we already have it and it is correct. If we don't
6318 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6320 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6321 pos_rtx
= orig_pos_rtx
;
6323 else if (pos_rtx
== 0)
6324 pos_rtx
= GEN_INT (pos
);
6326 /* Make the required operation. See if we can use existing rtx. */
6327 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6328 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6330 new = gen_lowpart_for_combine (mode
, new);
6335 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6336 with any other operations in X. Return X without that shift if so. */
6339 extract_left_shift (rtx x
, int count
)
6341 enum rtx_code code
= GET_CODE (x
);
6342 enum machine_mode mode
= GET_MODE (x
);
6348 /* This is the shift itself. If it is wide enough, we will return
6349 either the value being shifted if the shift count is equal to
6350 COUNT or a shift for the difference. */
6351 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6352 && INTVAL (XEXP (x
, 1)) >= count
)
6353 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6354 INTVAL (XEXP (x
, 1)) - count
);
6358 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6359 return simplify_gen_unary (code
, mode
, tem
, mode
);
6363 case PLUS
: case IOR
: case XOR
: case AND
:
6364 /* If we can safely shift this constant and we find the inner shift,
6365 make a new operation. */
6366 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6367 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6368 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6369 return gen_binary (code
, mode
, tem
,
6370 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6381 /* Look at the expression rooted at X. Look for expressions
6382 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6383 Form these expressions.
6385 Return the new rtx, usually just X.
6387 Also, for machines like the VAX that don't have logical shift insns,
6388 try to convert logical to arithmetic shift operations in cases where
6389 they are equivalent. This undoes the canonicalizations to logical
6390 shifts done elsewhere.
6392 We try, as much as possible, to re-use rtl expressions to save memory.
6394 IN_CODE says what kind of expression we are processing. Normally, it is
6395 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6396 being kludges), it is MEM. When processing the arguments of a comparison
6397 or a COMPARE against zero, it is COMPARE. */
6400 make_compound_operation (rtx x
, enum rtx_code in_code
)
6402 enum rtx_code code
= GET_CODE (x
);
6403 enum machine_mode mode
= GET_MODE (x
);
6404 int mode_width
= GET_MODE_BITSIZE (mode
);
6406 enum rtx_code next_code
;
6412 /* Select the code to be used in recursive calls. Once we are inside an
6413 address, we stay there. If we have a comparison, set to COMPARE,
6414 but once inside, go back to our default of SET. */
6416 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6417 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6418 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6419 : in_code
== COMPARE
? SET
: in_code
);
6421 /* Process depending on the code of this operation. If NEW is set
6422 nonzero, it will be returned. */
6427 /* Convert shifts by constants into multiplications if inside
6429 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6430 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6431 && INTVAL (XEXP (x
, 1)) >= 0)
6433 new = make_compound_operation (XEXP (x
, 0), next_code
);
6434 new = gen_rtx_MULT (mode
, new,
6435 GEN_INT ((HOST_WIDE_INT
) 1
6436 << INTVAL (XEXP (x
, 1))));
6441 /* If the second operand is not a constant, we can't do anything
6443 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6446 /* If the constant is a power of two minus one and the first operand
6447 is a logical right shift, make an extraction. */
6448 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6449 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6451 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6452 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6453 0, in_code
== COMPARE
);
6456 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6457 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6458 && subreg_lowpart_p (XEXP (x
, 0))
6459 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6460 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6462 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6464 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6465 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6466 0, in_code
== COMPARE
);
6468 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6469 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6470 || GET_CODE (XEXP (x
, 0)) == IOR
)
6471 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6472 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6473 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6475 /* Apply the distributive law, and then try to make extractions. */
6476 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6477 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6479 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6481 new = make_compound_operation (new, in_code
);
6484 /* If we are have (and (rotate X C) M) and C is larger than the number
6485 of bits in M, this is an extraction. */
6487 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6488 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6489 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6490 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6492 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6493 new = make_extraction (mode
, new,
6494 (GET_MODE_BITSIZE (mode
)
6495 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6496 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6499 /* On machines without logical shifts, if the operand of the AND is
6500 a logical shift and our mask turns off all the propagated sign
6501 bits, we can replace the logical shift with an arithmetic shift. */
6502 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6503 && !have_insn_for (LSHIFTRT
, mode
)
6504 && have_insn_for (ASHIFTRT
, mode
)
6505 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6506 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6507 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6508 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6510 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6512 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6513 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6515 gen_rtx_ASHIFTRT (mode
,
6516 make_compound_operation
6517 (XEXP (XEXP (x
, 0), 0), next_code
),
6518 XEXP (XEXP (x
, 0), 1)));
6521 /* If the constant is one less than a power of two, this might be
6522 representable by an extraction even if no shift is present.
6523 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6524 we are in a COMPARE. */
6525 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6526 new = make_extraction (mode
,
6527 make_compound_operation (XEXP (x
, 0),
6529 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6531 /* If we are in a comparison and this is an AND with a power of two,
6532 convert this into the appropriate bit extract. */
6533 else if (in_code
== COMPARE
6534 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6535 new = make_extraction (mode
,
6536 make_compound_operation (XEXP (x
, 0),
6538 i
, NULL_RTX
, 1, 1, 0, 1);
6543 /* If the sign bit is known to be zero, replace this with an
6544 arithmetic shift. */
6545 if (have_insn_for (ASHIFTRT
, mode
)
6546 && ! have_insn_for (LSHIFTRT
, mode
)
6547 && mode_width
<= HOST_BITS_PER_WIDE_INT
6548 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6550 new = gen_rtx_ASHIFTRT (mode
,
6551 make_compound_operation (XEXP (x
, 0),
6557 /* ... fall through ... */
6563 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6564 this is a SIGN_EXTRACT. */
6565 if (GET_CODE (rhs
) == CONST_INT
6566 && GET_CODE (lhs
) == ASHIFT
6567 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6568 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6570 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6571 new = make_extraction (mode
, new,
6572 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6573 NULL_RTX
, mode_width
- INTVAL (rhs
),
6574 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6578 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6579 If so, try to merge the shifts into a SIGN_EXTEND. We could
6580 also do this for some cases of SIGN_EXTRACT, but it doesn't
6581 seem worth the effort; the case checked for occurs on Alpha. */
6583 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6584 && ! (GET_CODE (lhs
) == SUBREG
6585 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6586 && GET_CODE (rhs
) == CONST_INT
6587 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6588 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6589 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6590 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6591 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6596 /* Call ourselves recursively on the inner expression. If we are
6597 narrowing the object and it has a different RTL code from
6598 what it originally did, do this SUBREG as a force_to_mode. */
6600 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6601 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6602 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6603 && subreg_lowpart_p (x
))
6605 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6608 /* If we have something other than a SUBREG, we might have
6609 done an expansion, so rerun ourselves. */
6610 if (GET_CODE (newer
) != SUBREG
)
6611 newer
= make_compound_operation (newer
, in_code
);
6616 /* If this is a paradoxical subreg, and the new code is a sign or
6617 zero extension, omit the subreg and widen the extension. If it
6618 is a regular subreg, we can still get rid of the subreg by not
6619 widening so much, or in fact removing the extension entirely. */
6620 if ((GET_CODE (tem
) == SIGN_EXTEND
6621 || GET_CODE (tem
) == ZERO_EXTEND
)
6622 && subreg_lowpart_p (x
))
6624 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6625 || (GET_MODE_SIZE (mode
) >
6626 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6628 if (! SCALAR_INT_MODE_P (mode
))
6630 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6633 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6644 x
= gen_lowpart_for_combine (mode
, new);
6645 code
= GET_CODE (x
);
6648 /* Now recursively process each operand of this operation. */
6649 fmt
= GET_RTX_FORMAT (code
);
6650 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6653 new = make_compound_operation (XEXP (x
, i
), next_code
);
6654 SUBST (XEXP (x
, i
), new);
6660 /* Given M see if it is a value that would select a field of bits
6661 within an item, but not the entire word. Return -1 if not.
6662 Otherwise, return the starting position of the field, where 0 is the
6665 *PLEN is set to the length of the field. */
6668 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6670 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6671 int pos
= exact_log2 (m
& -m
);
6677 /* Now shift off the low-order zero bits and see if we have a power of
6679 len
= exact_log2 ((m
>> pos
) + 1);
6688 /* See if X can be simplified knowing that we will only refer to it in
6689 MODE and will only refer to those bits that are nonzero in MASK.
6690 If other bits are being computed or if masking operations are done
6691 that select a superset of the bits in MASK, they can sometimes be
6694 Return a possibly simplified expression, but always convert X to
6695 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6697 Also, if REG is nonzero and X is a register equal in value to REG,
6700 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6701 are all off in X. This is used when X will be complemented, by either
6702 NOT, NEG, or XOR. */
6705 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6706 rtx reg
, int just_select
)
6708 enum rtx_code code
= GET_CODE (x
);
6709 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6710 enum machine_mode op_mode
;
6711 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6714 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6715 code below will do the wrong thing since the mode of such an
6716 expression is VOIDmode.
6718 Also do nothing if X is a CLOBBER; this can happen if X was
6719 the return value from a call to gen_lowpart_for_combine. */
6720 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6723 /* We want to perform the operation is its present mode unless we know
6724 that the operation is valid in MODE, in which case we do the operation
6726 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6727 && have_insn_for (code
, mode
))
6728 ? mode
: GET_MODE (x
));
6730 /* It is not valid to do a right-shift in a narrower mode
6731 than the one it came in with. */
6732 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6733 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6734 op_mode
= GET_MODE (x
);
6736 /* Truncate MASK to fit OP_MODE. */
6738 mask
&= GET_MODE_MASK (op_mode
);
6740 /* When we have an arithmetic operation, or a shift whose count we
6741 do not know, we need to assume that all bits up to the highest-order
6742 bit in MASK will be needed. This is how we form such a mask. */
6743 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6744 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6746 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6749 /* Determine what bits of X are guaranteed to be (non)zero. */
6750 nonzero
= nonzero_bits (x
, mode
);
6752 /* If none of the bits in X are needed, return a zero. */
6753 if (! just_select
&& (nonzero
& mask
) == 0)
6756 /* If X is a CONST_INT, return a new one. Do this here since the
6757 test below will fail. */
6758 if (GET_CODE (x
) == CONST_INT
)
6760 if (SCALAR_INT_MODE_P (mode
))
6761 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6764 x
= GEN_INT (INTVAL (x
) & mask
);
6765 return gen_lowpart_common (mode
, x
);
6769 /* If X is narrower than MODE and we want all the bits in X's mode, just
6770 get X in the proper mode. */
6771 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6772 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6773 return gen_lowpart_for_combine (mode
, x
);
6775 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6776 MASK are already known to be zero in X, we need not do anything. */
6777 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6783 /* If X is a (clobber (const_int)), return it since we know we are
6784 generating something that won't match. */
6788 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6789 spanned the boundary of the MEM. If we are now masking so it is
6790 within that boundary, we don't need the USE any more. */
6791 if (! BITS_BIG_ENDIAN
6792 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6793 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6800 x
= expand_compound_operation (x
);
6801 if (GET_CODE (x
) != code
)
6802 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6806 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6807 || rtx_equal_p (reg
, get_last_value (x
))))
6812 if (subreg_lowpart_p (x
)
6813 /* We can ignore the effect of this SUBREG if it narrows the mode or
6814 if the constant masks to zero all the bits the mode doesn't
6816 && ((GET_MODE_SIZE (GET_MODE (x
))
6817 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6819 & GET_MODE_MASK (GET_MODE (x
))
6820 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6821 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6825 /* If this is an AND with a constant, convert it into an AND
6826 whose constant is the AND of that constant with MASK. If it
6827 remains an AND of MASK, delete it since it is redundant. */
6829 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6831 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6832 mask
& INTVAL (XEXP (x
, 1)));
6834 /* If X is still an AND, see if it is an AND with a mask that
6835 is just some low-order bits. If so, and it is MASK, we don't
6838 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6839 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6843 /* If it remains an AND, try making another AND with the bits
6844 in the mode mask that aren't in MASK turned on. If the
6845 constant in the AND is wide enough, this might make a
6846 cheaper constant. */
6848 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6849 && GET_MODE_MASK (GET_MODE (x
)) != mask
6850 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6852 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6853 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6854 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6857 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6858 number, sign extend it. */
6859 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6860 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6861 cval
|= (HOST_WIDE_INT
) -1 << width
;
6863 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6864 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6874 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6875 low-order bits (as in an alignment operation) and FOO is already
6876 aligned to that boundary, mask C1 to that boundary as well.
6877 This may eliminate that PLUS and, later, the AND. */
6880 unsigned int width
= GET_MODE_BITSIZE (mode
);
6881 unsigned HOST_WIDE_INT smask
= mask
;
6883 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6884 number, sign extend it. */
6886 if (width
< HOST_BITS_PER_WIDE_INT
6887 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6888 smask
|= (HOST_WIDE_INT
) -1 << width
;
6890 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6891 && exact_log2 (- smask
) >= 0
6892 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6893 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6894 return force_to_mode (plus_constant (XEXP (x
, 0),
6895 (INTVAL (XEXP (x
, 1)) & smask
)),
6896 mode
, smask
, reg
, next_select
);
6899 /* ... fall through ... */
6902 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6903 most significant bit in MASK since carries from those bits will
6904 affect the bits we are interested in. */
6909 /* If X is (minus C Y) where C's least set bit is larger than any bit
6910 in the mask, then we may replace with (neg Y). */
6911 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6912 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6913 & -INTVAL (XEXP (x
, 0))))
6916 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6918 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6921 /* Similarly, if C contains every bit in the fuller_mask, then we may
6922 replace with (not Y). */
6923 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6924 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6925 == INTVAL (XEXP (x
, 0))))
6927 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6928 XEXP (x
, 1), GET_MODE (x
));
6929 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6937 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6938 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6939 operation which may be a bitfield extraction. Ensure that the
6940 constant we form is not wider than the mode of X. */
6942 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6943 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6944 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6945 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6946 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6947 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6948 + floor_log2 (INTVAL (XEXP (x
, 1))))
6949 < GET_MODE_BITSIZE (GET_MODE (x
)))
6950 && (INTVAL (XEXP (x
, 1))
6951 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6953 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6954 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6955 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6956 XEXP (XEXP (x
, 0), 0), temp
);
6957 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6958 XEXP (XEXP (x
, 0), 1));
6959 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6963 /* For most binary operations, just propagate into the operation and
6964 change the mode if we have an operation of that mode. */
6966 op0
= gen_lowpart_for_combine (op_mode
,
6967 force_to_mode (XEXP (x
, 0), mode
, mask
,
6969 op1
= gen_lowpart_for_combine (op_mode
,
6970 force_to_mode (XEXP (x
, 1), mode
, mask
,
6973 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6974 x
= gen_binary (code
, op_mode
, op0
, op1
);
6978 /* For left shifts, do the same, but just for the first operand.
6979 However, we cannot do anything with shifts where we cannot
6980 guarantee that the counts are smaller than the size of the mode
6981 because such a count will have a different meaning in a
6984 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6985 && INTVAL (XEXP (x
, 1)) >= 0
6986 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6987 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6988 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6989 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6992 /* If the shift count is a constant and we can do arithmetic in
6993 the mode of the shift, refine which bits we need. Otherwise, use the
6994 conservative form of the mask. */
6995 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6996 && INTVAL (XEXP (x
, 1)) >= 0
6997 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6998 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6999 mask
>>= INTVAL (XEXP (x
, 1));
7003 op0
= gen_lowpart_for_combine (op_mode
,
7004 force_to_mode (XEXP (x
, 0), op_mode
,
7005 mask
, reg
, next_select
));
7007 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7008 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7012 /* Here we can only do something if the shift count is a constant,
7013 this shift constant is valid for the host, and we can do arithmetic
7016 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7017 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7018 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7020 rtx inner
= XEXP (x
, 0);
7021 unsigned HOST_WIDE_INT inner_mask
;
7023 /* Select the mask of the bits we need for the shift operand. */
7024 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7026 /* We can only change the mode of the shift if we can do arithmetic
7027 in the mode of the shift and INNER_MASK is no wider than the
7028 width of OP_MODE. */
7029 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7030 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7031 op_mode
= GET_MODE (x
);
7033 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7035 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7036 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7039 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7040 shift and AND produces only copies of the sign bit (C2 is one less
7041 than a power of two), we can do this with just a shift. */
7043 if (GET_CODE (x
) == LSHIFTRT
7044 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7045 /* The shift puts one of the sign bit copies in the least significant
7047 && ((INTVAL (XEXP (x
, 1))
7048 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7049 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7050 && exact_log2 (mask
+ 1) >= 0
7051 /* Number of bits left after the shift must be more than the mask
7053 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7054 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7055 /* Must be more sign bit copies than the mask needs. */
7056 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7057 >= exact_log2 (mask
+ 1)))
7058 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7059 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7060 - exact_log2 (mask
+ 1)));
7065 /* If we are just looking for the sign bit, we don't need this shift at
7066 all, even if it has a variable count. */
7067 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7068 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7069 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7070 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7072 /* If this is a shift by a constant, get a mask that contains those bits
7073 that are not copies of the sign bit. We then have two cases: If
7074 MASK only includes those bits, this can be a logical shift, which may
7075 allow simplifications. If MASK is a single-bit field not within
7076 those bits, we are requesting a copy of the sign bit and hence can
7077 shift the sign bit to the appropriate location. */
7079 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7080 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7084 /* If the considered data is wider than HOST_WIDE_INT, we can't
7085 represent a mask for all its bits in a single scalar.
7086 But we only care about the lower bits, so calculate these. */
7088 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7090 nonzero
= ~(HOST_WIDE_INT
) 0;
7092 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7093 is the number of bits a full-width mask would have set.
7094 We need only shift if these are fewer than nonzero can
7095 hold. If not, we must keep all bits set in nonzero. */
7097 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7098 < HOST_BITS_PER_WIDE_INT
)
7099 nonzero
>>= INTVAL (XEXP (x
, 1))
7100 + HOST_BITS_PER_WIDE_INT
7101 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7105 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7106 nonzero
>>= INTVAL (XEXP (x
, 1));
7109 if ((mask
& ~nonzero
) == 0
7110 || (i
= exact_log2 (mask
)) >= 0)
7112 x
= simplify_shift_const
7113 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7114 i
< 0 ? INTVAL (XEXP (x
, 1))
7115 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7117 if (GET_CODE (x
) != ASHIFTRT
)
7118 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7122 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7123 even if the shift count isn't a constant. */
7125 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7129 /* If this is a zero- or sign-extension operation that just affects bits
7130 we don't care about, remove it. Be sure the call above returned
7131 something that is still a shift. */
7133 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7134 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7135 && INTVAL (XEXP (x
, 1)) >= 0
7136 && (INTVAL (XEXP (x
, 1))
7137 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7138 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7139 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7140 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7147 /* If the shift count is constant and we can do computations
7148 in the mode of X, compute where the bits we care about are.
7149 Otherwise, we can't do anything. Don't change the mode of
7150 the shift or propagate MODE into the shift, though. */
7151 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7152 && INTVAL (XEXP (x
, 1)) >= 0)
7154 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7155 GET_MODE (x
), GEN_INT (mask
),
7157 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7159 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7160 INTVAL (temp
), reg
, next_select
));
7165 /* If we just want the low-order bit, the NEG isn't needed since it
7166 won't change the low-order bit. */
7168 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7170 /* We need any bits less significant than the most significant bit in
7171 MASK since carries from those bits will affect the bits we are
7177 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7178 same as the XOR case above. Ensure that the constant we form is not
7179 wider than the mode of X. */
7181 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7182 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7183 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7184 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7185 < GET_MODE_BITSIZE (GET_MODE (x
)))
7186 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7188 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7190 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7191 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7193 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7196 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7197 use the full mask inside the NOT. */
7201 op0
= gen_lowpart_for_combine (op_mode
,
7202 force_to_mode (XEXP (x
, 0), mode
, mask
,
7204 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7205 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7209 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7210 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7211 which is equal to STORE_FLAG_VALUE. */
7212 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7213 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7214 && (nonzero_bits (XEXP (x
, 0), mode
)
7215 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7216 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7221 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7222 written in a narrower mode. We play it safe and do not do so. */
7225 gen_lowpart_for_combine (GET_MODE (x
),
7226 force_to_mode (XEXP (x
, 1), mode
,
7227 mask
, reg
, next_select
)));
7229 gen_lowpart_for_combine (GET_MODE (x
),
7230 force_to_mode (XEXP (x
, 2), mode
,
7231 mask
, reg
, next_select
)));
7238 /* Ensure we return a value of the proper mode. */
7239 return gen_lowpart_for_combine (mode
, x
);
7242 /* Return nonzero if X is an expression that has one of two values depending on
7243 whether some other value is zero or nonzero. In that case, we return the
7244 value that is being tested, *PTRUE is set to the value if the rtx being
7245 returned has a nonzero value, and *PFALSE is set to the other alternative.
7247 If we return zero, we set *PTRUE and *PFALSE to X. */
7250 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7252 enum machine_mode mode
= GET_MODE (x
);
7253 enum rtx_code code
= GET_CODE (x
);
7254 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7255 unsigned HOST_WIDE_INT nz
;
7257 /* If we are comparing a value against zero, we are done. */
7258 if ((code
== NE
|| code
== EQ
)
7259 && XEXP (x
, 1) == const0_rtx
)
7261 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7262 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7266 /* If this is a unary operation whose operand has one of two values, apply
7267 our opcode to compute those values. */
7268 else if (GET_RTX_CLASS (code
) == '1'
7269 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7271 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7272 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7273 GET_MODE (XEXP (x
, 0)));
7277 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7278 make can't possibly match and would suppress other optimizations. */
7279 else if (code
== COMPARE
)
7282 /* If this is a binary operation, see if either side has only one of two
7283 values. If either one does or if both do and they are conditional on
7284 the same value, compute the new true and false values. */
7285 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7286 || GET_RTX_CLASS (code
) == '<')
7288 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7289 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7291 if ((cond0
!= 0 || cond1
!= 0)
7292 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7294 /* If if_then_else_cond returned zero, then true/false are the
7295 same rtl. We must copy one of them to prevent invalid rtl
7298 true0
= copy_rtx (true0
);
7299 else if (cond1
== 0)
7300 true1
= copy_rtx (true1
);
7302 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7303 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7304 return cond0
? cond0
: cond1
;
7307 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7308 operands is zero when the other is nonzero, and vice-versa,
7309 and STORE_FLAG_VALUE is 1 or -1. */
7311 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7312 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7314 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7316 rtx op0
= XEXP (XEXP (x
, 0), 1);
7317 rtx op1
= XEXP (XEXP (x
, 1), 1);
7319 cond0
= XEXP (XEXP (x
, 0), 0);
7320 cond1
= XEXP (XEXP (x
, 1), 0);
7322 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7323 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7324 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7325 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7326 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7327 || ((swap_condition (GET_CODE (cond0
))
7328 == combine_reversed_comparison_code (cond1
))
7329 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7330 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7331 && ! side_effects_p (x
))
7333 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7334 *pfalse
= gen_binary (MULT
, mode
,
7336 ? simplify_gen_unary (NEG
, mode
, op1
,
7344 /* Similarly for MULT, AND and UMIN, except that for these the result
7346 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7347 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7348 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7350 cond0
= XEXP (XEXP (x
, 0), 0);
7351 cond1
= XEXP (XEXP (x
, 1), 0);
7353 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7354 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7355 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7356 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7357 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7358 || ((swap_condition (GET_CODE (cond0
))
7359 == combine_reversed_comparison_code (cond1
))
7360 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7361 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7362 && ! side_effects_p (x
))
7364 *ptrue
= *pfalse
= const0_rtx
;
7370 else if (code
== IF_THEN_ELSE
)
7372 /* If we have IF_THEN_ELSE already, extract the condition and
7373 canonicalize it if it is NE or EQ. */
7374 cond0
= XEXP (x
, 0);
7375 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7376 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7377 return XEXP (cond0
, 0);
7378 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7380 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7381 return XEXP (cond0
, 0);
7387 /* If X is a SUBREG, we can narrow both the true and false values
7388 if the inner expression, if there is a condition. */
7389 else if (code
== SUBREG
7390 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7393 *ptrue
= simplify_gen_subreg (mode
, true0
,
7394 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7395 *pfalse
= simplify_gen_subreg (mode
, false0
,
7396 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7401 /* If X is a constant, this isn't special and will cause confusions
7402 if we treat it as such. Likewise if it is equivalent to a constant. */
7403 else if (CONSTANT_P (x
)
7404 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7407 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7408 will be least confusing to the rest of the compiler. */
7409 else if (mode
== BImode
)
7411 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7415 /* If X is known to be either 0 or -1, those are the true and
7416 false values when testing X. */
7417 else if (x
== constm1_rtx
|| x
== const0_rtx
7418 || (mode
!= VOIDmode
7419 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7421 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7425 /* Likewise for 0 or a single bit. */
7426 else if (SCALAR_INT_MODE_P (mode
)
7427 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7428 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7430 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7434 /* Otherwise fail; show no condition with true and false values the same. */
7435 *ptrue
= *pfalse
= x
;
7439 /* Return the value of expression X given the fact that condition COND
7440 is known to be true when applied to REG as its first operand and VAL
7441 as its second. X is known to not be shared and so can be modified in
7444 We only handle the simplest cases, and specifically those cases that
7445 arise with IF_THEN_ELSE expressions. */
7448 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7450 enum rtx_code code
= GET_CODE (x
);
7455 if (side_effects_p (x
))
7458 /* If either operand of the condition is a floating point value,
7459 then we have to avoid collapsing an EQ comparison. */
7461 && rtx_equal_p (x
, reg
)
7462 && ! FLOAT_MODE_P (GET_MODE (x
))
7463 && ! FLOAT_MODE_P (GET_MODE (val
)))
7466 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7469 /* If X is (abs REG) and we know something about REG's relationship
7470 with zero, we may be able to simplify this. */
7472 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7475 case GE
: case GT
: case EQ
:
7478 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7480 GET_MODE (XEXP (x
, 0)));
7485 /* The only other cases we handle are MIN, MAX, and comparisons if the
7486 operands are the same as REG and VAL. */
7488 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7490 if (rtx_equal_p (XEXP (x
, 0), val
))
7491 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7493 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7495 if (GET_RTX_CLASS (code
) == '<')
7497 if (comparison_dominates_p (cond
, code
))
7498 return const_true_rtx
;
7500 code
= combine_reversed_comparison_code (x
);
7502 && comparison_dominates_p (cond
, code
))
7507 else if (code
== SMAX
|| code
== SMIN
7508 || code
== UMIN
|| code
== UMAX
)
7510 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7512 /* Do not reverse the condition when it is NE or EQ.
7513 This is because we cannot conclude anything about
7514 the value of 'SMAX (x, y)' when x is not equal to y,
7515 but we can when x equals y. */
7516 if ((code
== SMAX
|| code
== UMAX
)
7517 && ! (cond
== EQ
|| cond
== NE
))
7518 cond
= reverse_condition (cond
);
7523 return unsignedp
? x
: XEXP (x
, 1);
7525 return unsignedp
? x
: XEXP (x
, 0);
7527 return unsignedp
? XEXP (x
, 1) : x
;
7529 return unsignedp
? XEXP (x
, 0) : x
;
7536 else if (code
== SUBREG
)
7538 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7539 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7541 if (SUBREG_REG (x
) != r
)
7543 /* We must simplify subreg here, before we lose track of the
7544 original inner_mode. */
7545 new = simplify_subreg (GET_MODE (x
), r
,
7546 inner_mode
, SUBREG_BYTE (x
));
7550 SUBST (SUBREG_REG (x
), r
);
7555 /* We don't have to handle SIGN_EXTEND here, because even in the
7556 case of replacing something with a modeless CONST_INT, a
7557 CONST_INT is already (supposed to be) a valid sign extension for
7558 its narrower mode, which implies it's already properly
7559 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7560 story is different. */
7561 else if (code
== ZERO_EXTEND
)
7563 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7564 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7566 if (XEXP (x
, 0) != r
)
7568 /* We must simplify the zero_extend here, before we lose
7569 track of the original inner_mode. */
7570 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7575 SUBST (XEXP (x
, 0), r
);
7581 fmt
= GET_RTX_FORMAT (code
);
7582 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7585 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7586 else if (fmt
[i
] == 'E')
7587 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7588 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7595 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7596 assignment as a field assignment. */
7599 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7601 if (x
== y
|| rtx_equal_p (x
, y
))
7604 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7607 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7608 Note that all SUBREGs of MEM are paradoxical; otherwise they
7609 would have been rewritten. */
7610 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7611 && GET_CODE (SUBREG_REG (y
)) == MEM
7612 && rtx_equal_p (SUBREG_REG (y
),
7613 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7616 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7617 && GET_CODE (SUBREG_REG (x
)) == MEM
7618 && rtx_equal_p (SUBREG_REG (x
),
7619 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7622 /* We used to see if get_last_value of X and Y were the same but that's
7623 not correct. In one direction, we'll cause the assignment to have
7624 the wrong destination and in the case, we'll import a register into this
7625 insn that might have already have been dead. So fail if none of the
7626 above cases are true. */
7630 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7631 Return that assignment if so.
7633 We only handle the most common cases. */
7636 make_field_assignment (rtx x
)
7638 rtx dest
= SET_DEST (x
);
7639 rtx src
= SET_SRC (x
);
7644 unsigned HOST_WIDE_INT len
;
7646 enum machine_mode mode
;
7648 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7649 a clear of a one-bit field. We will have changed it to
7650 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7653 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7654 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7655 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7656 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7658 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7661 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7665 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7666 && subreg_lowpart_p (XEXP (src
, 0))
7667 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7668 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7669 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7670 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7671 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7672 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7674 assign
= make_extraction (VOIDmode
, dest
, 0,
7675 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7678 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7682 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7684 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7685 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7686 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7688 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7691 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7695 /* The other case we handle is assignments into a constant-position
7696 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7697 a mask that has all one bits except for a group of zero bits and
7698 OTHER is known to have zeros where C1 has ones, this is such an
7699 assignment. Compute the position and length from C1. Shift OTHER
7700 to the appropriate position, force it to the required mode, and
7701 make the extraction. Check for the AND in both operands. */
7703 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7706 rhs
= expand_compound_operation (XEXP (src
, 0));
7707 lhs
= expand_compound_operation (XEXP (src
, 1));
7709 if (GET_CODE (rhs
) == AND
7710 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7711 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7712 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7713 else if (GET_CODE (lhs
) == AND
7714 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7715 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7716 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7720 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7721 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7722 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7723 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7726 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7730 /* The mode to use for the source is the mode of the assignment, or of
7731 what is inside a possible STRICT_LOW_PART. */
7732 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7733 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7735 /* Shift OTHER right POS places and make it the source, restricting it
7736 to the proper length and mode. */
7738 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7739 GET_MODE (src
), other
, pos
),
7741 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7742 ? ~(unsigned HOST_WIDE_INT
) 0
7743 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7746 /* If SRC is masked by an AND that does not make a difference in
7747 the value being stored, strip it. */
7748 if (GET_CODE (assign
) == ZERO_EXTRACT
7749 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7750 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7751 && GET_CODE (src
) == AND
7752 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7753 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7754 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7755 src
= XEXP (src
, 0);
7757 return gen_rtx_SET (VOIDmode
, assign
, src
);
7760 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7764 apply_distributive_law (rtx x
)
7766 enum rtx_code code
= GET_CODE (x
);
7767 enum rtx_code inner_code
;
7768 rtx lhs
, rhs
, other
;
7771 /* Distributivity is not true for floating point as it can change the
7772 value. So we don't do it unless -funsafe-math-optimizations. */
7773 if (FLOAT_MODE_P (GET_MODE (x
))
7774 && ! flag_unsafe_math_optimizations
)
7777 /* The outer operation can only be one of the following: */
7778 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7779 && code
!= PLUS
&& code
!= MINUS
)
7785 /* If either operand is a primitive we can't do anything, so get out
7787 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7788 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7791 lhs
= expand_compound_operation (lhs
);
7792 rhs
= expand_compound_operation (rhs
);
7793 inner_code
= GET_CODE (lhs
);
7794 if (inner_code
!= GET_CODE (rhs
))
7797 /* See if the inner and outer operations distribute. */
7804 /* These all distribute except over PLUS. */
7805 if (code
== PLUS
|| code
== MINUS
)
7810 if (code
!= PLUS
&& code
!= MINUS
)
7815 /* This is also a multiply, so it distributes over everything. */
7819 /* Non-paradoxical SUBREGs distributes over all operations, provided
7820 the inner modes and byte offsets are the same, this is an extraction
7821 of a low-order part, we don't convert an fp operation to int or
7822 vice versa, and we would not be converting a single-word
7823 operation into a multi-word operation. The latter test is not
7824 required, but it prevents generating unneeded multi-word operations.
7825 Some of the previous tests are redundant given the latter test, but
7826 are retained because they are required for correctness.
7828 We produce the result slightly differently in this case. */
7830 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7831 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7832 || ! subreg_lowpart_p (lhs
)
7833 || (GET_MODE_CLASS (GET_MODE (lhs
))
7834 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7835 || (GET_MODE_SIZE (GET_MODE (lhs
))
7836 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7837 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7840 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7841 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7842 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7848 /* Set LHS and RHS to the inner operands (A and B in the example
7849 above) and set OTHER to the common operand (C in the example).
7850 These is only one way to do this unless the inner operation is
7852 if (GET_RTX_CLASS (inner_code
) == 'c'
7853 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7854 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7855 else if (GET_RTX_CLASS (inner_code
) == 'c'
7856 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7857 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7858 else if (GET_RTX_CLASS (inner_code
) == 'c'
7859 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7860 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7861 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7862 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7866 /* Form the new inner operation, seeing if it simplifies first. */
7867 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7869 /* There is one exception to the general way of distributing:
7870 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7871 if (code
== XOR
&& inner_code
== IOR
)
7874 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7877 /* We may be able to continuing distributing the result, so call
7878 ourselves recursively on the inner operation before forming the
7879 outer operation, which we return. */
7880 return gen_binary (inner_code
, GET_MODE (x
),
7881 apply_distributive_law (tem
), other
);
7884 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7887 Return an equivalent form, if different from X. Otherwise, return X. If
7888 X is zero, we are to always construct the equivalent form. */
7891 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7892 unsigned HOST_WIDE_INT constop
)
7894 unsigned HOST_WIDE_INT nonzero
;
7897 /* Simplify VAROP knowing that we will be only looking at some of the
7900 Note by passing in CONSTOP, we guarantee that the bits not set in
7901 CONSTOP are not significant and will never be examined. We must
7902 ensure that is the case by explicitly masking out those bits
7903 before returning. */
7904 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7906 /* If VAROP is a CLOBBER, we will fail so return it. */
7907 if (GET_CODE (varop
) == CLOBBER
)
7910 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7911 to VAROP and return the new constant. */
7912 if (GET_CODE (varop
) == CONST_INT
)
7913 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7915 /* See what bits may be nonzero in VAROP. Unlike the general case of
7916 a call to nonzero_bits, here we don't care about bits outside
7919 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7921 /* Turn off all bits in the constant that are known to already be zero.
7922 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7923 which is tested below. */
7927 /* If we don't have any bits left, return zero. */
7931 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7932 a power of two, we can replace this with an ASHIFT. */
7933 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7934 && (i
= exact_log2 (constop
)) >= 0)
7935 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7937 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7938 or XOR, then try to apply the distributive law. This may eliminate
7939 operations if either branch can be simplified because of the AND.
7940 It may also make some cases more complex, but those cases probably
7941 won't match a pattern either with or without this. */
7943 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7945 gen_lowpart_for_combine
7947 apply_distributive_law
7948 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7949 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7950 XEXP (varop
, 0), constop
),
7951 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7952 XEXP (varop
, 1), constop
))));
7954 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7955 the AND and see if one of the operands simplifies to zero. If so, we
7956 may eliminate it. */
7958 if (GET_CODE (varop
) == PLUS
7959 && exact_log2 (constop
+ 1) >= 0)
7963 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
7964 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
7965 if (o0
== const0_rtx
)
7967 if (o1
== const0_rtx
)
7971 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7972 if we already had one (just check for the simplest cases). */
7973 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7974 && GET_MODE (XEXP (x
, 0)) == mode
7975 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7976 varop
= XEXP (x
, 0);
7978 varop
= gen_lowpart_for_combine (mode
, varop
);
7980 /* If we can't make the SUBREG, try to return what we were given. */
7981 if (GET_CODE (varop
) == CLOBBER
)
7982 return x
? x
: varop
;
7984 /* If we are only masking insignificant bits, return VAROP. */
7985 if (constop
== nonzero
)
7989 /* Otherwise, return an AND. */
7990 constop
= trunc_int_for_mode (constop
, mode
);
7991 /* See how much, if any, of X we can use. */
7992 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7993 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7997 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7998 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7999 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8001 SUBST (XEXP (x
, 0), varop
);
8008 #define nonzero_bits_with_known(X, MODE) \
8009 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8011 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8012 It avoids exponential behavior in nonzero_bits1 when X has
8013 identical subexpressions on the first or the second level. */
8015 static unsigned HOST_WIDE_INT
8016 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8017 enum machine_mode known_mode
,
8018 unsigned HOST_WIDE_INT known_ret
)
8020 if (x
== known_x
&& mode
== known_mode
)
8023 /* Try to find identical subexpressions. If found call
8024 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8025 precomputed value for the subexpression as KNOWN_RET. */
8027 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8028 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8030 rtx x0
= XEXP (x
, 0);
8031 rtx x1
= XEXP (x
, 1);
8033 /* Check the first level. */
8035 return nonzero_bits1 (x
, mode
, x0
, mode
,
8036 nonzero_bits_with_known (x0
, mode
));
8038 /* Check the second level. */
8039 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8040 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8041 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8042 return nonzero_bits1 (x
, mode
, x1
, mode
,
8043 nonzero_bits_with_known (x1
, mode
));
8045 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8046 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8047 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8048 return nonzero_bits1 (x
, mode
, x0
, mode
,
8049 nonzero_bits_with_known (x0
, mode
));
8052 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8055 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8056 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8057 is less useful. We can't allow both, because that results in exponential
8058 run time recursion. There is a nullstone testcase that triggered
8059 this. This macro avoids accidental uses of num_sign_bit_copies. */
8060 #define cached_num_sign_bit_copies()
8062 /* Given an expression, X, compute which bits in X can be nonzero.
8063 We don't care about bits outside of those defined in MODE.
8065 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8066 a shift, AND, or zero_extract, we can do better. */
8068 static unsigned HOST_WIDE_INT
8069 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8070 enum machine_mode known_mode
,
8071 unsigned HOST_WIDE_INT known_ret
)
8073 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8074 unsigned HOST_WIDE_INT inner_nz
;
8076 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8079 /* For floating-point values, assume all bits are needed. */
8080 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8083 /* If X is wider than MODE, use its mode instead. */
8084 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8086 mode
= GET_MODE (x
);
8087 nonzero
= GET_MODE_MASK (mode
);
8088 mode_width
= GET_MODE_BITSIZE (mode
);
8091 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8092 /* Our only callers in this case look for single bit values. So
8093 just return the mode mask. Those tests will then be false. */
8096 #ifndef WORD_REGISTER_OPERATIONS
8097 /* If MODE is wider than X, but both are a single word for both the host
8098 and target machines, we can compute this from which bits of the
8099 object might be nonzero in its own mode, taking into account the fact
8100 that on many CISC machines, accessing an object in a wider mode
8101 causes the high-order bits to become undefined. So they are
8102 not known to be zero. */
8104 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8105 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8106 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8107 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8109 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8110 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8115 code
= GET_CODE (x
);
8119 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8120 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8121 all the bits above ptr_mode are known to be zero. */
8122 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8124 nonzero
&= GET_MODE_MASK (ptr_mode
);
8127 /* Include declared information about alignment of pointers. */
8128 /* ??? We don't properly preserve REG_POINTER changes across
8129 pointer-to-integer casts, so we can't trust it except for
8130 things that we know must be pointers. See execute/960116-1.c. */
8131 if ((x
== stack_pointer_rtx
8132 || x
== frame_pointer_rtx
8133 || x
== arg_pointer_rtx
)
8134 && REGNO_POINTER_ALIGN (REGNO (x
)))
8136 unsigned HOST_WIDE_INT alignment
8137 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8139 #ifdef PUSH_ROUNDING
8140 /* If PUSH_ROUNDING is defined, it is possible for the
8141 stack to be momentarily aligned only to that amount,
8142 so we pick the least alignment. */
8143 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8144 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8148 nonzero
&= ~(alignment
- 1);
8151 /* If X is a register whose nonzero bits value is current, use it.
8152 Otherwise, if X is a register whose value we can find, use that
8153 value. Otherwise, use the previously-computed global nonzero bits
8154 for this register. */
8156 if (reg_last_set_value
[REGNO (x
)] != 0
8157 && (reg_last_set_mode
[REGNO (x
)] == mode
8158 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8159 && GET_MODE_CLASS (mode
) == MODE_INT
))
8160 && (reg_last_set_label
[REGNO (x
)] == label_tick
8161 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8162 && REG_N_SETS (REGNO (x
)) == 1
8163 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8165 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8166 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8168 tem
= get_last_value (x
);
8172 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8173 /* If X is narrower than MODE and TEM is a non-negative
8174 constant that would appear negative in the mode of X,
8175 sign-extend it for use in reg_nonzero_bits because some
8176 machines (maybe most) will actually do the sign-extension
8177 and this is the conservative approach.
8179 ??? For 2.5, try to tighten up the MD files in this regard
8180 instead of this kludge. */
8182 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8183 && GET_CODE (tem
) == CONST_INT
8185 && 0 != (INTVAL (tem
)
8186 & ((HOST_WIDE_INT
) 1
8187 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8188 tem
= GEN_INT (INTVAL (tem
)
8189 | ((HOST_WIDE_INT
) (-1)
8190 << GET_MODE_BITSIZE (GET_MODE (x
))));
8192 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8194 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8196 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8198 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8199 /* We don't know anything about the upper bits. */
8200 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8201 return nonzero
& mask
;
8207 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8208 /* If X is negative in MODE, sign-extend the value. */
8209 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8210 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8211 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8217 #ifdef LOAD_EXTEND_OP
8218 /* In many, if not most, RISC machines, reading a byte from memory
8219 zeros the rest of the register. Noticing that fact saves a lot
8220 of extra zero-extends. */
8221 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8222 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8227 case UNEQ
: case LTGT
:
8228 case GT
: case GTU
: case UNGT
:
8229 case LT
: case LTU
: case UNLT
:
8230 case GE
: case GEU
: case UNGE
:
8231 case LE
: case LEU
: case UNLE
:
8232 case UNORDERED
: case ORDERED
:
8234 /* If this produces an integer result, we know which bits are set.
8235 Code here used to clear bits outside the mode of X, but that is
8238 if (GET_MODE_CLASS (mode
) == MODE_INT
8239 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8240 nonzero
= STORE_FLAG_VALUE
;
8245 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8246 and num_sign_bit_copies. */
8247 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8248 == GET_MODE_BITSIZE (GET_MODE (x
)))
8252 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8253 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8258 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8259 and num_sign_bit_copies. */
8260 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8261 == GET_MODE_BITSIZE (GET_MODE (x
)))
8267 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8268 & GET_MODE_MASK (mode
));
8272 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8273 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8274 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8278 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8279 Otherwise, show all the bits in the outer mode but not the inner
8281 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8282 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8284 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8286 & (((HOST_WIDE_INT
) 1
8287 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8288 inner_nz
|= (GET_MODE_MASK (mode
)
8289 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8292 nonzero
&= inner_nz
;
8296 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8297 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8301 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8303 unsigned HOST_WIDE_INT nonzero0
=
8304 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8306 /* Don't call nonzero_bits for the second time if it cannot change
8308 if ((nonzero
& nonzero0
) != nonzero
)
8309 nonzero
&= (nonzero0
8310 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8314 case PLUS
: case MINUS
:
8316 case DIV
: case UDIV
:
8317 case MOD
: case UMOD
:
8318 /* We can apply the rules of arithmetic to compute the number of
8319 high- and low-order zero bits of these operations. We start by
8320 computing the width (position of the highest-order nonzero bit)
8321 and the number of low-order zero bits for each value. */
8323 unsigned HOST_WIDE_INT nz0
=
8324 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8325 unsigned HOST_WIDE_INT nz1
=
8326 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8327 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8328 int width0
= floor_log2 (nz0
) + 1;
8329 int width1
= floor_log2 (nz1
) + 1;
8330 int low0
= floor_log2 (nz0
& -nz0
);
8331 int low1
= floor_log2 (nz1
& -nz1
);
8332 HOST_WIDE_INT op0_maybe_minusp
8333 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8334 HOST_WIDE_INT op1_maybe_minusp
8335 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8336 unsigned int result_width
= mode_width
;
8342 result_width
= MAX (width0
, width1
) + 1;
8343 result_low
= MIN (low0
, low1
);
8346 result_low
= MIN (low0
, low1
);
8349 result_width
= width0
+ width1
;
8350 result_low
= low0
+ low1
;
8355 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8356 result_width
= width0
;
8361 result_width
= width0
;
8366 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8367 result_width
= MIN (width0
, width1
);
8368 result_low
= MIN (low0
, low1
);
8373 result_width
= MIN (width0
, width1
);
8374 result_low
= MIN (low0
, low1
);
8380 if (result_width
< mode_width
)
8381 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8384 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8386 #ifdef POINTERS_EXTEND_UNSIGNED
8387 /* If pointers extend unsigned and this is an addition or subtraction
8388 to a pointer in Pmode, all the bits above ptr_mode are known to be
8390 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8391 && (code
== PLUS
|| code
== MINUS
)
8392 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8393 nonzero
&= GET_MODE_MASK (ptr_mode
);
8399 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8400 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8401 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8405 /* If this is a SUBREG formed for a promoted variable that has
8406 been zero-extended, we know that at least the high-order bits
8407 are zero, though others might be too. */
8409 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8410 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8411 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8413 /* If the inner mode is a single word for both the host and target
8414 machines, we can compute this from which bits of the inner
8415 object might be nonzero. */
8416 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8417 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8418 <= HOST_BITS_PER_WIDE_INT
))
8420 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8422 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8423 /* If this is a typical RISC machine, we only have to worry
8424 about the way loads are extended. */
8425 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8427 & (((unsigned HOST_WIDE_INT
) 1
8428 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8430 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8431 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8434 /* On many CISC machines, accessing an object in a wider mode
8435 causes the high-order bits to become undefined. So they are
8436 not known to be zero. */
8437 if (GET_MODE_SIZE (GET_MODE (x
))
8438 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8439 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8440 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8449 /* The nonzero bits are in two classes: any bits within MODE
8450 that aren't in GET_MODE (x) are always significant. The rest of the
8451 nonzero bits are those that are significant in the operand of
8452 the shift when shifted the appropriate number of bits. This
8453 shows that high-order bits are cleared by the right shift and
8454 low-order bits by left shifts. */
8455 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8456 && INTVAL (XEXP (x
, 1)) >= 0
8457 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8459 enum machine_mode inner_mode
= GET_MODE (x
);
8460 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8461 int count
= INTVAL (XEXP (x
, 1));
8462 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8463 unsigned HOST_WIDE_INT op_nonzero
=
8464 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8465 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8466 unsigned HOST_WIDE_INT outer
= 0;
8468 if (mode_width
> width
)
8469 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8471 if (code
== LSHIFTRT
)
8473 else if (code
== ASHIFTRT
)
8477 /* If the sign bit may have been nonzero before the shift, we
8478 need to mark all the places it could have been copied to
8479 by the shift as possibly nonzero. */
8480 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8481 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8483 else if (code
== ASHIFT
)
8486 inner
= ((inner
<< (count
% width
)
8487 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8489 nonzero
&= (outer
| inner
);
8495 /* This is at most the number of bits in the mode. */
8496 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8500 /* If CLZ has a known value at zero, then the nonzero bits are
8501 that value, plus the number of bits in the mode minus one. */
8502 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8503 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8509 /* If CTZ has a known value at zero, then the nonzero bits are
8510 that value, plus the number of bits in the mode minus one. */
8511 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8512 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8522 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8523 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8533 /* See the macro definition above. */
8534 #undef cached_num_sign_bit_copies
8536 #define num_sign_bit_copies_with_known(X, M) \
8537 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8539 /* The function cached_num_sign_bit_copies is a wrapper around
8540 num_sign_bit_copies1. It avoids exponential behavior in
8541 num_sign_bit_copies1 when X has identical subexpressions on the
8542 first or the second level. */
8545 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8546 enum machine_mode known_mode
,
8547 unsigned int known_ret
)
8549 if (x
== known_x
&& mode
== known_mode
)
8552 /* Try to find identical subexpressions. If found call
8553 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8554 the precomputed value for the subexpression as KNOWN_RET. */
8556 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8557 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8559 rtx x0
= XEXP (x
, 0);
8560 rtx x1
= XEXP (x
, 1);
8562 /* Check the first level. */
8565 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8566 num_sign_bit_copies_with_known (x0
, mode
));
8568 /* Check the second level. */
8569 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8570 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8571 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8573 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8574 num_sign_bit_copies_with_known (x1
, mode
));
8576 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8577 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8578 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8580 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8581 num_sign_bit_copies_with_known (x0
, mode
));
8584 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8587 /* Return the number of bits at the high-order end of X that are known to
8588 be equal to the sign bit. X will be used in mode MODE; if MODE is
8589 VOIDmode, X will be used in its own mode. The returned value will always
8590 be between 1 and the number of bits in MODE. */
8593 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8594 enum machine_mode known_mode
,
8595 unsigned int known_ret
)
8597 enum rtx_code code
= GET_CODE (x
);
8598 unsigned int bitwidth
;
8599 int num0
, num1
, result
;
8600 unsigned HOST_WIDE_INT nonzero
;
8603 /* If we weren't given a mode, use the mode of X. If the mode is still
8604 VOIDmode, we don't know anything. Likewise if one of the modes is
8607 if (mode
== VOIDmode
)
8608 mode
= GET_MODE (x
);
8610 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8613 bitwidth
= GET_MODE_BITSIZE (mode
);
8615 /* For a smaller object, just ignore the high bits. */
8616 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8618 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8620 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8623 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8625 #ifndef WORD_REGISTER_OPERATIONS
8626 /* If this machine does not do all register operations on the entire
8627 register and MODE is wider than the mode of X, we can say nothing
8628 at all about the high-order bits. */
8631 /* Likewise on machines that do, if the mode of the object is smaller
8632 than a word and loads of that size don't sign extend, we can say
8633 nothing about the high order bits. */
8634 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8635 #ifdef LOAD_EXTEND_OP
8636 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8647 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8648 /* If pointers extend signed and this is a pointer in Pmode, say that
8649 all the bits above ptr_mode are known to be sign bit copies. */
8650 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8652 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8655 if (reg_last_set_value
[REGNO (x
)] != 0
8656 && reg_last_set_mode
[REGNO (x
)] == mode
8657 && (reg_last_set_label
[REGNO (x
)] == label_tick
8658 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8659 && REG_N_SETS (REGNO (x
)) == 1
8660 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8662 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8663 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8665 tem
= get_last_value (x
);
8667 return num_sign_bit_copies_with_known (tem
, mode
);
8669 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8670 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8671 return reg_sign_bit_copies
[REGNO (x
)];
8675 #ifdef LOAD_EXTEND_OP
8676 /* Some RISC machines sign-extend all loads of smaller than a word. */
8677 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8678 return MAX (1, ((int) bitwidth
8679 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8684 /* If the constant is negative, take its 1's complement and remask.
8685 Then see how many zero bits we have. */
8686 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8687 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8688 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8689 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8691 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8694 /* If this is a SUBREG for a promoted object that is sign-extended
8695 and we are looking at it in a wider mode, we know that at least the
8696 high-order bits are known to be sign bit copies. */
8698 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8700 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8701 return MAX ((int) bitwidth
8702 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8706 /* For a smaller object, just ignore the high bits. */
8707 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8709 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8710 return MAX (1, (num0
8711 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8715 #ifdef WORD_REGISTER_OPERATIONS
8716 #ifdef LOAD_EXTEND_OP
8717 /* For paradoxical SUBREGs on machines where all register operations
8718 affect the entire register, just look inside. Note that we are
8719 passing MODE to the recursive call, so the number of sign bit copies
8720 will remain relative to that mode, not the inner mode. */
8722 /* This works only if loads sign extend. Otherwise, if we get a
8723 reload for the inner part, it may be loaded from the stack, and
8724 then we lose all sign bit copies that existed before the store
8727 if ((GET_MODE_SIZE (GET_MODE (x
))
8728 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8729 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8730 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8731 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8737 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8738 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8742 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8743 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8746 /* For a smaller object, just ignore the high bits. */
8747 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8748 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8752 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8754 case ROTATE
: case ROTATERT
:
8755 /* If we are rotating left by a number of bits less than the number
8756 of sign bit copies, we can just subtract that amount from the
8758 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8759 && INTVAL (XEXP (x
, 1)) >= 0
8760 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8762 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8763 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8764 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8769 /* In general, this subtracts one sign bit copy. But if the value
8770 is known to be positive, the number of sign bit copies is the
8771 same as that of the input. Finally, if the input has just one bit
8772 that might be nonzero, all the bits are copies of the sign bit. */
8773 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8774 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8775 return num0
> 1 ? num0
- 1 : 1;
8777 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8782 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8787 case IOR
: case AND
: case XOR
:
8788 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8789 /* Logical operations will preserve the number of sign-bit copies.
8790 MIN and MAX operations always return one of the operands. */
8791 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8792 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8793 return MIN (num0
, num1
);
8795 case PLUS
: case MINUS
:
8796 /* For addition and subtraction, we can have a 1-bit carry. However,
8797 if we are subtracting 1 from a positive number, there will not
8798 be such a carry. Furthermore, if the positive number is known to
8799 be 0 or 1, we know the result is either -1 or 0. */
8801 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8802 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8804 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8805 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8806 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8807 : bitwidth
- floor_log2 (nonzero
) - 1);
8810 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8811 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8812 result
= MAX (1, MIN (num0
, num1
) - 1);
8814 #ifdef POINTERS_EXTEND_UNSIGNED
8815 /* If pointers extend signed and this is an addition or subtraction
8816 to a pointer in Pmode, all the bits above ptr_mode are known to be
8818 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8819 && (code
== PLUS
|| code
== MINUS
)
8820 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8821 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8822 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8828 /* The number of bits of the product is the sum of the number of
8829 bits of both terms. However, unless one of the terms if known
8830 to be positive, we must allow for an additional bit since negating
8831 a negative number can remove one sign bit copy. */
8833 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8834 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8836 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8838 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8839 || (((nonzero_bits (XEXP (x
, 0), mode
)
8840 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8841 && ((nonzero_bits (XEXP (x
, 1), mode
)
8842 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8845 return MAX (1, result
);
8848 /* The result must be <= the first operand. If the first operand
8849 has the high bit set, we know nothing about the number of sign
8851 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8853 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8854 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8857 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8860 /* The result must be <= the second operand. */
8861 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8864 /* Similar to unsigned division, except that we have to worry about
8865 the case where the divisor is negative, in which case we have
8867 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8869 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8870 || (nonzero_bits (XEXP (x
, 1), mode
)
8871 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8877 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8879 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8880 || (nonzero_bits (XEXP (x
, 1), mode
)
8881 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8887 /* Shifts by a constant add to the number of bits equal to the
8889 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8890 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8891 && INTVAL (XEXP (x
, 1)) > 0)
8892 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8897 /* Left shifts destroy copies. */
8898 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8899 || INTVAL (XEXP (x
, 1)) < 0
8900 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8903 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8904 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8907 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8908 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8909 return MIN (num0
, num1
);
8911 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8912 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8913 case GEU
: case GTU
: case LEU
: case LTU
:
8914 case UNORDERED
: case ORDERED
:
8915 /* If the constant is negative, take its 1's complement and remask.
8916 Then see how many zero bits we have. */
8917 nonzero
= STORE_FLAG_VALUE
;
8918 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8919 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8920 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8922 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8929 /* If we haven't been able to figure it out by one of the above rules,
8930 see if some of the high-order bits are known to be zero. If so,
8931 count those bits and return one less than that amount. If we can't
8932 safely compute the mask for this mode, always return BITWIDTH. */
8934 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8937 nonzero
= nonzero_bits (x
, mode
);
8938 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8939 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8942 /* Return the number of "extended" bits there are in X, when interpreted
8943 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8944 unsigned quantities, this is the number of high-order zero bits.
8945 For signed quantities, this is the number of copies of the sign bit
8946 minus 1. In both case, this function returns the number of "spare"
8947 bits. For example, if two quantities for which this function returns
8948 at least 1 are added, the addition is known not to overflow.
8950 This function will always return 0 unless called during combine, which
8951 implies that it must be called from a define_split. */
8954 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8956 if (nonzero_sign_valid
== 0)
8960 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8961 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8962 - floor_log2 (nonzero_bits (x
, mode
)))
8964 : num_sign_bit_copies (x
, mode
) - 1);
8967 /* This function is called from `simplify_shift_const' to merge two
8968 outer operations. Specifically, we have already found that we need
8969 to perform operation *POP0 with constant *PCONST0 at the outermost
8970 position. We would now like to also perform OP1 with constant CONST1
8971 (with *POP0 being done last).
8973 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8974 the resulting operation. *PCOMP_P is set to 1 if we would need to
8975 complement the innermost operand, otherwise it is unchanged.
8977 MODE is the mode in which the operation will be done. No bits outside
8978 the width of this mode matter. It is assumed that the width of this mode
8979 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8981 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8982 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8983 result is simply *PCONST0.
8985 If the resulting operation cannot be expressed as one operation, we
8986 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8989 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8991 enum rtx_code op0
= *pop0
;
8992 HOST_WIDE_INT const0
= *pconst0
;
8994 const0
&= GET_MODE_MASK (mode
);
8995 const1
&= GET_MODE_MASK (mode
);
8997 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9001 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9004 if (op1
== NIL
|| op0
== SET
)
9007 else if (op0
== NIL
)
9008 op0
= op1
, const0
= const1
;
9010 else if (op0
== op1
)
9034 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9035 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9038 /* If the two constants aren't the same, we can't do anything. The
9039 remaining six cases can all be done. */
9040 else if (const0
!= const1
)
9048 /* (a & b) | b == b */
9050 else /* op1 == XOR */
9051 /* (a ^ b) | b == a | b */
9057 /* (a & b) ^ b == (~a) & b */
9058 op0
= AND
, *pcomp_p
= 1;
9059 else /* op1 == IOR */
9060 /* (a | b) ^ b == a & ~b */
9061 op0
= AND
, const0
= ~const0
;
9066 /* (a | b) & b == b */
9068 else /* op1 == XOR */
9069 /* (a ^ b) & b) == (~a) & b */
9076 /* Check for NO-OP cases. */
9077 const0
&= GET_MODE_MASK (mode
);
9079 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9081 else if (const0
== 0 && op0
== AND
)
9083 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9087 /* ??? Slightly redundant with the above mask, but not entirely.
9088 Moving this above means we'd have to sign-extend the mode mask
9089 for the final test. */
9090 const0
= trunc_int_for_mode (const0
, mode
);
9098 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9099 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9100 that we started with.
9102 The shift is normally computed in the widest mode we find in VAROP, as
9103 long as it isn't a different number of words than RESULT_MODE. Exceptions
9104 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9107 simplify_shift_const (rtx x
, enum rtx_code code
,
9108 enum machine_mode result_mode
, rtx varop
,
9111 enum rtx_code orig_code
= code
;
9114 enum machine_mode mode
= result_mode
;
9115 enum machine_mode shift_mode
, tmode
;
9116 unsigned int mode_words
9117 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9118 /* We form (outer_op (code varop count) (outer_const)). */
9119 enum rtx_code outer_op
= NIL
;
9120 HOST_WIDE_INT outer_const
= 0;
9122 int complement_p
= 0;
9125 /* Make sure and truncate the "natural" shift on the way in. We don't
9126 want to do this inside the loop as it makes it more difficult to
9128 if (SHIFT_COUNT_TRUNCATED
)
9129 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9131 /* If we were given an invalid count, don't do anything except exactly
9132 what was requested. */
9134 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9139 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9144 /* Unless one of the branches of the `if' in this loop does a `continue',
9145 we will `break' the loop after the `if'. */
9149 /* If we have an operand of (clobber (const_int 0)), just return that
9151 if (GET_CODE (varop
) == CLOBBER
)
9154 /* If we discovered we had to complement VAROP, leave. Making a NOT
9155 here would cause an infinite loop. */
9159 /* Convert ROTATERT to ROTATE. */
9160 if (code
== ROTATERT
)
9162 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9164 if (VECTOR_MODE_P (result_mode
))
9165 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9167 count
= bitsize
- count
;
9170 /* We need to determine what mode we will do the shift in. If the
9171 shift is a right shift or a ROTATE, we must always do it in the mode
9172 it was originally done in. Otherwise, we can do it in MODE, the
9173 widest mode encountered. */
9175 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9176 ? result_mode
: mode
);
9178 /* Handle cases where the count is greater than the size of the mode
9179 minus 1. For ASHIFT, use the size minus one as the count (this can
9180 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9181 take the count modulo the size. For other shifts, the result is
9184 Since these shifts are being produced by the compiler by combining
9185 multiple operations, each of which are defined, we know what the
9186 result is supposed to be. */
9188 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9190 if (code
== ASHIFTRT
)
9191 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9192 else if (code
== ROTATE
|| code
== ROTATERT
)
9193 count
%= GET_MODE_BITSIZE (shift_mode
);
9196 /* We can't simply return zero because there may be an
9204 /* An arithmetic right shift of a quantity known to be -1 or 0
9206 if (code
== ASHIFTRT
9207 && (num_sign_bit_copies (varop
, shift_mode
)
9208 == GET_MODE_BITSIZE (shift_mode
)))
9214 /* If we are doing an arithmetic right shift and discarding all but
9215 the sign bit copies, this is equivalent to doing a shift by the
9216 bitsize minus one. Convert it into that shift because it will often
9217 allow other simplifications. */
9219 if (code
== ASHIFTRT
9220 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9221 >= GET_MODE_BITSIZE (shift_mode
)))
9222 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9224 /* We simplify the tests below and elsewhere by converting
9225 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9226 `make_compound_operation' will convert it to an ASHIFTRT for
9227 those machines (such as VAX) that don't have an LSHIFTRT. */
9228 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9230 && ((nonzero_bits (varop
, shift_mode
)
9231 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9235 if (code
== LSHIFTRT
9236 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9237 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9240 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9241 && !((nonzero_bits (varop
, shift_mode
) << count
)
9242 & GET_MODE_MASK (shift_mode
)))
9245 switch (GET_CODE (varop
))
9251 new = expand_compound_operation (varop
);
9260 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9261 minus the width of a smaller mode, we can do this with a
9262 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9263 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9264 && ! mode_dependent_address_p (XEXP (varop
, 0))
9265 && ! MEM_VOLATILE_P (varop
)
9266 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9267 MODE_INT
, 1)) != BLKmode
)
9269 new = adjust_address_nv (varop
, tmode
,
9270 BYTES_BIG_ENDIAN
? 0
9271 : count
/ BITS_PER_UNIT
);
9273 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9274 : ZERO_EXTEND
, mode
, new);
9281 /* Similar to the case above, except that we can only do this if
9282 the resulting mode is the same as that of the underlying
9283 MEM and adjust the address depending on the *bits* endianness
9284 because of the way that bit-field extract insns are defined. */
9285 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9286 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9287 MODE_INT
, 1)) != BLKmode
9288 && tmode
== GET_MODE (XEXP (varop
, 0)))
9290 if (BITS_BIG_ENDIAN
)
9291 new = XEXP (varop
, 0);
9294 new = copy_rtx (XEXP (varop
, 0));
9295 SUBST (XEXP (new, 0),
9296 plus_constant (XEXP (new, 0),
9297 count
/ BITS_PER_UNIT
));
9300 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9301 : ZERO_EXTEND
, mode
, new);
9308 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9309 the same number of words as what we've seen so far. Then store
9310 the widest mode in MODE. */
9311 if (subreg_lowpart_p (varop
)
9312 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9313 > GET_MODE_SIZE (GET_MODE (varop
)))
9314 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9315 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9318 varop
= SUBREG_REG (varop
);
9319 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9320 mode
= GET_MODE (varop
);
9326 /* Some machines use MULT instead of ASHIFT because MULT
9327 is cheaper. But it is still better on those machines to
9328 merge two shifts into one. */
9329 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9330 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9333 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9334 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9340 /* Similar, for when divides are cheaper. */
9341 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9342 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9345 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9346 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9352 /* If we are extracting just the sign bit of an arithmetic
9353 right shift, that shift is not needed. However, the sign
9354 bit of a wider mode may be different from what would be
9355 interpreted as the sign bit in a narrower mode, so, if
9356 the result is narrower, don't discard the shift. */
9357 if (code
== LSHIFTRT
9358 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9359 && (GET_MODE_BITSIZE (result_mode
)
9360 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9362 varop
= XEXP (varop
, 0);
9366 /* ... fall through ... */
9371 /* Here we have two nested shifts. The result is usually the
9372 AND of a new shift with a mask. We compute the result below. */
9373 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9374 && INTVAL (XEXP (varop
, 1)) >= 0
9375 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9376 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9377 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9379 enum rtx_code first_code
= GET_CODE (varop
);
9380 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9381 unsigned HOST_WIDE_INT mask
;
9384 /* We have one common special case. We can't do any merging if
9385 the inner code is an ASHIFTRT of a smaller mode. However, if
9386 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9387 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9388 we can convert it to
9389 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9390 This simplifies certain SIGN_EXTEND operations. */
9391 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9392 && count
== (unsigned int)
9393 (GET_MODE_BITSIZE (result_mode
)
9394 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9396 /* C3 has the low-order C1 bits zero. */
9398 mask
= (GET_MODE_MASK (mode
)
9399 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9401 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9402 XEXP (varop
, 0), mask
);
9403 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9405 count
= first_count
;
9410 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9411 than C1 high-order bits equal to the sign bit, we can convert
9412 this to either an ASHIFT or an ASHIFTRT depending on the
9415 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9417 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9418 && GET_MODE (varop
) == shift_mode
9419 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9422 varop
= XEXP (varop
, 0);
9424 signed_count
= count
- first_count
;
9425 if (signed_count
< 0)
9426 count
= -signed_count
, code
= ASHIFT
;
9428 count
= signed_count
;
9433 /* There are some cases we can't do. If CODE is ASHIFTRT,
9434 we can only do this if FIRST_CODE is also ASHIFTRT.
9436 We can't do the case when CODE is ROTATE and FIRST_CODE is
9439 If the mode of this shift is not the mode of the outer shift,
9440 we can't do this if either shift is a right shift or ROTATE.
9442 Finally, we can't do any of these if the mode is too wide
9443 unless the codes are the same.
9445 Handle the case where the shift codes are the same
9448 if (code
== first_code
)
9450 if (GET_MODE (varop
) != result_mode
9451 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9455 count
+= first_count
;
9456 varop
= XEXP (varop
, 0);
9460 if (code
== ASHIFTRT
9461 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9462 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9463 || (GET_MODE (varop
) != result_mode
9464 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9465 || first_code
== ROTATE
9466 || code
== ROTATE
)))
9469 /* To compute the mask to apply after the shift, shift the
9470 nonzero bits of the inner shift the same way the
9471 outer shift will. */
9473 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9476 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9479 /* Give up if we can't compute an outer operation to use. */
9481 || GET_CODE (mask_rtx
) != CONST_INT
9482 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9484 result_mode
, &complement_p
))
9487 /* If the shifts are in the same direction, we add the
9488 counts. Otherwise, we subtract them. */
9489 signed_count
= count
;
9490 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9491 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9492 signed_count
+= first_count
;
9494 signed_count
-= first_count
;
9496 /* If COUNT is positive, the new shift is usually CODE,
9497 except for the two exceptions below, in which case it is
9498 FIRST_CODE. If the count is negative, FIRST_CODE should
9500 if (signed_count
> 0
9501 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9502 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9503 code
= first_code
, count
= signed_count
;
9504 else if (signed_count
< 0)
9505 code
= first_code
, count
= -signed_count
;
9507 count
= signed_count
;
9509 varop
= XEXP (varop
, 0);
9513 /* If we have (A << B << C) for any shift, we can convert this to
9514 (A << C << B). This wins if A is a constant. Only try this if
9515 B is not a constant. */
9517 else if (GET_CODE (varop
) == code
9518 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9520 = simplify_binary_operation (code
, mode
,
9524 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9531 /* Make this fit the case below. */
9532 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9533 GEN_INT (GET_MODE_MASK (mode
)));
9539 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9540 with C the size of VAROP - 1 and the shift is logical if
9541 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9542 we have an (le X 0) operation. If we have an arithmetic shift
9543 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9544 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9546 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9547 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9548 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9549 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9550 && count
== (unsigned int)
9551 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9552 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9555 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9558 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9559 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9564 /* If we have (shift (logical)), move the logical to the outside
9565 to allow it to possibly combine with another logical and the
9566 shift to combine with another shift. This also canonicalizes to
9567 what a ZERO_EXTRACT looks like. Also, some machines have
9568 (and (shift)) insns. */
9570 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9571 /* We can't do this if we have (ashiftrt (xor)) and the
9572 constant has its sign bit set in shift_mode. */
9573 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9574 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9576 && (new = simplify_binary_operation (code
, result_mode
,
9578 GEN_INT (count
))) != 0
9579 && GET_CODE (new) == CONST_INT
9580 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9581 INTVAL (new), result_mode
, &complement_p
))
9583 varop
= XEXP (varop
, 0);
9587 /* If we can't do that, try to simplify the shift in each arm of the
9588 logical expression, make a new logical expression, and apply
9589 the inverse distributive law. This also can't be done
9590 for some (ashiftrt (xor)). */
9591 if (code
!= ASHIFTRT
|| GET_CODE (varop
)!= XOR
9592 || 0 <= trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9595 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9596 XEXP (varop
, 0), count
);
9597 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9598 XEXP (varop
, 1), count
);
9600 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9601 varop
= apply_distributive_law (varop
);
9608 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9609 says that the sign bit can be tested, FOO has mode MODE, C is
9610 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9611 that may be nonzero. */
9612 if (code
== LSHIFTRT
9613 && XEXP (varop
, 1) == const0_rtx
9614 && GET_MODE (XEXP (varop
, 0)) == result_mode
9615 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9616 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9617 && ((STORE_FLAG_VALUE
9618 & ((HOST_WIDE_INT
) 1
9619 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9620 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9621 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9622 (HOST_WIDE_INT
) 1, result_mode
,
9625 varop
= XEXP (varop
, 0);
9632 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9633 than the number of bits in the mode is equivalent to A. */
9634 if (code
== LSHIFTRT
9635 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9636 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9638 varop
= XEXP (varop
, 0);
9643 /* NEG commutes with ASHIFT since it is multiplication. Move the
9644 NEG outside to allow shifts to combine. */
9646 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9647 (HOST_WIDE_INT
) 0, result_mode
,
9650 varop
= XEXP (varop
, 0);
9656 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9657 is one less than the number of bits in the mode is
9658 equivalent to (xor A 1). */
9659 if (code
== LSHIFTRT
9660 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9661 && XEXP (varop
, 1) == constm1_rtx
9662 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9663 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9664 (HOST_WIDE_INT
) 1, result_mode
,
9668 varop
= XEXP (varop
, 0);
9672 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9673 that might be nonzero in BAR are those being shifted out and those
9674 bits are known zero in FOO, we can replace the PLUS with FOO.
9675 Similarly in the other operand order. This code occurs when
9676 we are computing the size of a variable-size array. */
9678 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9679 && count
< HOST_BITS_PER_WIDE_INT
9680 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9681 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9682 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9684 varop
= XEXP (varop
, 0);
9687 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9688 && count
< HOST_BITS_PER_WIDE_INT
9689 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9690 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9692 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9693 & nonzero_bits (XEXP (varop
, 1),
9696 varop
= XEXP (varop
, 1);
9700 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9702 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9703 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9705 GEN_INT (count
))) != 0
9706 && GET_CODE (new) == CONST_INT
9707 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9708 INTVAL (new), result_mode
, &complement_p
))
9710 varop
= XEXP (varop
, 0);
9716 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9717 with C the size of VAROP - 1 and the shift is logical if
9718 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9719 we have a (gt X 0) operation. If the shift is arithmetic with
9720 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9721 we have a (neg (gt X 0)) operation. */
9723 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9724 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9725 && count
== (unsigned int)
9726 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9727 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9728 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9729 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9731 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9734 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9737 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9738 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9745 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9746 if the truncate does not affect the value. */
9747 if (code
== LSHIFTRT
9748 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9749 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9750 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9751 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9752 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9754 rtx varop_inner
= XEXP (varop
, 0);
9757 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9758 XEXP (varop_inner
, 0),
9760 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9761 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9774 /* We need to determine what mode to do the shift in. If the shift is
9775 a right shift or ROTATE, we must always do it in the mode it was
9776 originally done in. Otherwise, we can do it in MODE, the widest mode
9777 encountered. The code we care about is that of the shift that will
9778 actually be done, not the shift that was originally requested. */
9780 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9781 ? result_mode
: mode
);
9783 /* We have now finished analyzing the shift. The result should be
9784 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9785 OUTER_OP is non-NIL, it is an operation that needs to be applied
9786 to the result of the shift. OUTER_CONST is the relevant constant,
9787 but we must turn off all bits turned off in the shift.
9789 If we were passed a value for X, see if we can use any pieces of
9790 it. If not, make new rtx. */
9792 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9793 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9794 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9795 const_rtx
= XEXP (x
, 1);
9797 const_rtx
= GEN_INT (count
);
9799 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9800 && GET_MODE (XEXP (x
, 0)) == shift_mode
9801 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9802 varop
= XEXP (x
, 0);
9803 else if (GET_MODE (varop
) != shift_mode
)
9804 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9806 /* If we can't make the SUBREG, try to return what we were given. */
9807 if (GET_CODE (varop
) == CLOBBER
)
9808 return x
? x
: varop
;
9810 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9814 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9816 /* If we have an outer operation and we just made a shift, it is
9817 possible that we could have simplified the shift were it not
9818 for the outer operation. So try to do the simplification
9821 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9822 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9823 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9824 INTVAL (XEXP (x
, 1)));
9826 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9827 turn off all the bits that the shift would have turned off. */
9828 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9829 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9830 GET_MODE_MASK (result_mode
) >> orig_count
);
9832 /* Do the remainder of the processing in RESULT_MODE. */
9833 x
= gen_lowpart_for_combine (result_mode
, x
);
9835 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9838 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9840 if (outer_op
!= NIL
)
9842 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9843 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9845 if (outer_op
== AND
)
9846 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9847 else if (outer_op
== SET
)
9848 /* This means that we have determined that the result is
9849 equivalent to a constant. This should be rare. */
9850 x
= GEN_INT (outer_const
);
9851 else if (GET_RTX_CLASS (outer_op
) == '1')
9852 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9854 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9860 /* Like recog, but we receive the address of a pointer to a new pattern.
9861 We try to match the rtx that the pointer points to.
9862 If that fails, we may try to modify or replace the pattern,
9863 storing the replacement into the same pointer object.
9865 Modifications include deletion or addition of CLOBBERs.
9867 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9868 the CLOBBERs are placed.
9870 The value is the final insn code from the pattern ultimately matched,
9874 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9877 int insn_code_number
;
9878 int num_clobbers_to_add
= 0;
9881 rtx old_notes
, old_pat
;
9883 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9884 we use to indicate that something didn't match. If we find such a
9885 thing, force rejection. */
9886 if (GET_CODE (pat
) == PARALLEL
)
9887 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9888 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9889 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9892 old_pat
= PATTERN (insn
);
9893 old_notes
= REG_NOTES (insn
);
9894 PATTERN (insn
) = pat
;
9895 REG_NOTES (insn
) = 0;
9897 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9899 /* If it isn't, there is the possibility that we previously had an insn
9900 that clobbered some register as a side effect, but the combined
9901 insn doesn't need to do that. So try once more without the clobbers
9902 unless this represents an ASM insn. */
9904 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9905 && GET_CODE (pat
) == PARALLEL
)
9909 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9910 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9913 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9917 SUBST_INT (XVECLEN (pat
, 0), pos
);
9920 pat
= XVECEXP (pat
, 0, 0);
9922 PATTERN (insn
) = pat
;
9923 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9925 PATTERN (insn
) = old_pat
;
9926 REG_NOTES (insn
) = old_notes
;
9928 /* Recognize all noop sets, these will be killed by followup pass. */
9929 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9930 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9932 /* If we had any clobbers to add, make a new pattern than contains
9933 them. Then check to make sure that all of them are dead. */
9934 if (num_clobbers_to_add
)
9936 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9937 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9939 + num_clobbers_to_add
)
9940 : num_clobbers_to_add
+ 1));
9942 if (GET_CODE (pat
) == PARALLEL
)
9943 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9944 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9946 XVECEXP (newpat
, 0, 0) = pat
;
9948 add_clobbers (newpat
, insn_code_number
);
9950 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9951 i
< XVECLEN (newpat
, 0); i
++)
9953 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9954 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9956 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9957 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9965 return insn_code_number
;
9968 /* Like gen_lowpart but for use by combine. In combine it is not possible
9969 to create any new pseudoregs. However, it is safe to create
9970 invalid memory addresses, because combine will try to recognize
9971 them and all they will do is make the combine attempt fail.
9973 If for some reason this cannot do its job, an rtx
9974 (clobber (const_int 0)) is returned.
9975 An insn containing that will not be recognized. */
9980 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
9984 if (GET_MODE (x
) == mode
)
9987 /* Return identity if this is a CONST or symbolic
9990 && (GET_CODE (x
) == CONST
9991 || GET_CODE (x
) == SYMBOL_REF
9992 || GET_CODE (x
) == LABEL_REF
))
9995 /* We can only support MODE being wider than a word if X is a
9996 constant integer or has a mode the same size. */
9998 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9999 && ! ((GET_MODE (x
) == VOIDmode
10000 && (GET_CODE (x
) == CONST_INT
10001 || GET_CODE (x
) == CONST_DOUBLE
))
10002 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
10003 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10005 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10006 won't know what to do. So we will strip off the SUBREG here and
10007 process normally. */
10008 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
10010 x
= SUBREG_REG (x
);
10011 if (GET_MODE (x
) == mode
)
10015 result
= gen_lowpart_common (mode
, x
);
10016 #ifdef CANNOT_CHANGE_MODE_CLASS
10018 && GET_CODE (result
) == SUBREG
10019 && GET_CODE (SUBREG_REG (result
)) == REG
10020 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10021 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10023 + GET_MODE (result
));
10029 if (GET_CODE (x
) == MEM
)
10033 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10035 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10036 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10038 /* If we want to refer to something bigger than the original memref,
10039 generate a perverse subreg instead. That will force a reload
10040 of the original memref X. */
10041 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10042 return gen_rtx_SUBREG (mode
, x
, 0);
10044 if (WORDS_BIG_ENDIAN
)
10045 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10046 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10048 if (BYTES_BIG_ENDIAN
)
10050 /* Adjust the address so that the address-after-the-data is
10052 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10053 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10056 return adjust_address_nv (x
, mode
, offset
);
10059 /* If X is a comparison operator, rewrite it in a new mode. This
10060 probably won't match, but may allow further simplifications. */
10061 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
10062 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10064 /* If we couldn't simplify X any other way, just enclose it in a
10065 SUBREG. Normally, this SUBREG won't match, but some patterns may
10066 include an explicit SUBREG or we may simplify it further in combine. */
10071 enum machine_mode sub_mode
= GET_MODE (x
);
10073 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10074 if (sub_mode
== VOIDmode
)
10076 sub_mode
= int_mode_for_mode (mode
);
10077 x
= gen_lowpart_common (sub_mode
, x
);
10079 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10081 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10084 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10088 /* These routines make binary and unary operations by first seeing if they
10089 fold; if not, a new expression is allocated. */
10092 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10097 if (GET_CODE (op0
) == CLOBBER
)
10099 else if (GET_CODE (op1
) == CLOBBER
)
10102 if (GET_RTX_CLASS (code
) == 'c'
10103 && swap_commutative_operands_p (op0
, op1
))
10104 tem
= op0
, op0
= op1
, op1
= tem
;
10106 if (GET_RTX_CLASS (code
) == '<')
10108 enum machine_mode op_mode
= GET_MODE (op0
);
10110 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10111 just (REL_OP X Y). */
10112 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10114 op1
= XEXP (op0
, 1);
10115 op0
= XEXP (op0
, 0);
10116 op_mode
= GET_MODE (op0
);
10119 if (op_mode
== VOIDmode
)
10120 op_mode
= GET_MODE (op1
);
10121 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10124 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10129 /* Put complex operands first and constants second. */
10130 if (GET_RTX_CLASS (code
) == 'c'
10131 && swap_commutative_operands_p (op0
, op1
))
10132 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10134 /* If we are turning off bits already known off in OP0, we need not do
10136 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10137 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10138 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10141 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10144 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10145 comparison code that will be tested.
10147 The result is a possibly different comparison code to use. *POP0 and
10148 *POP1 may be updated.
10150 It is possible that we might detect that a comparison is either always
10151 true or always false. However, we do not perform general constant
10152 folding in combine, so this knowledge isn't useful. Such tautologies
10153 should have been detected earlier. Hence we ignore all such cases. */
10155 static enum rtx_code
10156 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10162 enum machine_mode mode
, tmode
;
10164 /* Try a few ways of applying the same transformation to both operands. */
10167 #ifndef WORD_REGISTER_OPERATIONS
10168 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10169 so check specially. */
10170 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10171 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10172 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10173 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10174 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10175 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10176 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10177 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10178 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10179 && XEXP (op0
, 1) == XEXP (op1
, 1)
10180 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10181 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10182 && (INTVAL (XEXP (op0
, 1))
10183 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10184 - (GET_MODE_BITSIZE
10185 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10187 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10188 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10192 /* If both operands are the same constant shift, see if we can ignore the
10193 shift. We can if the shift is a rotate or if the bits shifted out of
10194 this shift are known to be zero for both inputs and if the type of
10195 comparison is compatible with the shift. */
10196 if (GET_CODE (op0
) == GET_CODE (op1
)
10197 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10198 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10199 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10200 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10201 || (GET_CODE (op0
) == ASHIFTRT
10202 && (code
!= GTU
&& code
!= LTU
10203 && code
!= GEU
&& code
!= LEU
)))
10204 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10205 && INTVAL (XEXP (op0
, 1)) >= 0
10206 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10207 && XEXP (op0
, 1) == XEXP (op1
, 1))
10209 enum machine_mode mode
= GET_MODE (op0
);
10210 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10211 int shift_count
= INTVAL (XEXP (op0
, 1));
10213 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10214 mask
&= (mask
>> shift_count
) << shift_count
;
10215 else if (GET_CODE (op0
) == ASHIFT
)
10216 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10218 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10219 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10220 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10225 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10226 SUBREGs are of the same mode, and, in both cases, the AND would
10227 be redundant if the comparison was done in the narrower mode,
10228 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10229 and the operand's possibly nonzero bits are 0xffffff01; in that case
10230 if we only care about QImode, we don't need the AND). This case
10231 occurs if the output mode of an scc insn is not SImode and
10232 STORE_FLAG_VALUE == 1 (e.g., the 386).
10234 Similarly, check for a case where the AND's are ZERO_EXTEND
10235 operations from some narrower mode even though a SUBREG is not
10238 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10239 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10240 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10242 rtx inner_op0
= XEXP (op0
, 0);
10243 rtx inner_op1
= XEXP (op1
, 0);
10244 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10245 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10248 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10249 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10250 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10251 && (GET_MODE (SUBREG_REG (inner_op0
))
10252 == GET_MODE (SUBREG_REG (inner_op1
)))
10253 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10254 <= HOST_BITS_PER_WIDE_INT
)
10255 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10256 GET_MODE (SUBREG_REG (inner_op0
)))))
10257 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10258 GET_MODE (SUBREG_REG (inner_op1
))))))
10260 op0
= SUBREG_REG (inner_op0
);
10261 op1
= SUBREG_REG (inner_op1
);
10263 /* The resulting comparison is always unsigned since we masked
10264 off the original sign bit. */
10265 code
= unsigned_condition (code
);
10271 for (tmode
= GET_CLASS_NARROWEST_MODE
10272 (GET_MODE_CLASS (GET_MODE (op0
)));
10273 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10274 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10276 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10277 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10278 code
= unsigned_condition (code
);
10287 /* If both operands are NOT, we can strip off the outer operation
10288 and adjust the comparison code for swapped operands; similarly for
10289 NEG, except that this must be an equality comparison. */
10290 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10291 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10292 && (code
== EQ
|| code
== NE
)))
10293 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10299 /* If the first operand is a constant, swap the operands and adjust the
10300 comparison code appropriately, but don't do this if the second operand
10301 is already a constant integer. */
10302 if (swap_commutative_operands_p (op0
, op1
))
10304 tem
= op0
, op0
= op1
, op1
= tem
;
10305 code
= swap_condition (code
);
10308 /* We now enter a loop during which we will try to simplify the comparison.
10309 For the most part, we only are concerned with comparisons with zero,
10310 but some things may really be comparisons with zero but not start
10311 out looking that way. */
10313 while (GET_CODE (op1
) == CONST_INT
)
10315 enum machine_mode mode
= GET_MODE (op0
);
10316 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10317 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10318 int equality_comparison_p
;
10319 int sign_bit_comparison_p
;
10320 int unsigned_comparison_p
;
10321 HOST_WIDE_INT const_op
;
10323 /* We only want to handle integral modes. This catches VOIDmode,
10324 CCmode, and the floating-point modes. An exception is that we
10325 can handle VOIDmode if OP0 is a COMPARE or a comparison
10328 if (GET_MODE_CLASS (mode
) != MODE_INT
10329 && ! (mode
== VOIDmode
10330 && (GET_CODE (op0
) == COMPARE
10331 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10334 /* Get the constant we are comparing against and turn off all bits
10335 not on in our mode. */
10336 const_op
= INTVAL (op1
);
10337 if (mode
!= VOIDmode
)
10338 const_op
= trunc_int_for_mode (const_op
, mode
);
10339 op1
= GEN_INT (const_op
);
10341 /* If we are comparing against a constant power of two and the value
10342 being compared can only have that single bit nonzero (e.g., it was
10343 `and'ed with that bit), we can replace this with a comparison
10346 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10347 || code
== LT
|| code
== LTU
)
10348 && mode_width
<= HOST_BITS_PER_WIDE_INT
10349 && exact_log2 (const_op
) >= 0
10350 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10352 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10353 op1
= const0_rtx
, const_op
= 0;
10356 /* Similarly, if we are comparing a value known to be either -1 or
10357 0 with -1, change it to the opposite comparison against zero. */
10360 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10361 || code
== GEU
|| code
== LTU
)
10362 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10364 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10365 op1
= const0_rtx
, const_op
= 0;
10368 /* Do some canonicalizations based on the comparison code. We prefer
10369 comparisons against zero and then prefer equality comparisons.
10370 If we can reduce the size of a constant, we will do that too. */
10375 /* < C is equivalent to <= (C - 1) */
10379 op1
= GEN_INT (const_op
);
10381 /* ... fall through to LE case below. */
10387 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10391 op1
= GEN_INT (const_op
);
10395 /* If we are doing a <= 0 comparison on a value known to have
10396 a zero sign bit, we can replace this with == 0. */
10397 else if (const_op
== 0
10398 && mode_width
<= HOST_BITS_PER_WIDE_INT
10399 && (nonzero_bits (op0
, mode
)
10400 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10405 /* >= C is equivalent to > (C - 1). */
10409 op1
= GEN_INT (const_op
);
10411 /* ... fall through to GT below. */
10417 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10421 op1
= GEN_INT (const_op
);
10425 /* If we are doing a > 0 comparison on a value known to have
10426 a zero sign bit, we can replace this with != 0. */
10427 else if (const_op
== 0
10428 && mode_width
<= HOST_BITS_PER_WIDE_INT
10429 && (nonzero_bits (op0
, mode
)
10430 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10435 /* < C is equivalent to <= (C - 1). */
10439 op1
= GEN_INT (const_op
);
10441 /* ... fall through ... */
10444 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10445 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10446 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10448 const_op
= 0, op1
= const0_rtx
;
10456 /* unsigned <= 0 is equivalent to == 0 */
10460 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10461 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10462 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10464 const_op
= 0, op1
= const0_rtx
;
10470 /* >= C is equivalent to < (C - 1). */
10474 op1
= GEN_INT (const_op
);
10476 /* ... fall through ... */
10479 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10480 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10481 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10483 const_op
= 0, op1
= const0_rtx
;
10491 /* unsigned > 0 is equivalent to != 0 */
10495 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10496 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10497 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10499 const_op
= 0, op1
= const0_rtx
;
10508 /* Compute some predicates to simplify code below. */
10510 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10511 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10512 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10515 /* If this is a sign bit comparison and we can do arithmetic in
10516 MODE, say that we will only be needing the sign bit of OP0. */
10517 if (sign_bit_comparison_p
10518 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10519 op0
= force_to_mode (op0
, mode
,
10521 << (GET_MODE_BITSIZE (mode
) - 1)),
10524 /* Now try cases based on the opcode of OP0. If none of the cases
10525 does a "continue", we exit this loop immediately after the
10528 switch (GET_CODE (op0
))
10531 /* If we are extracting a single bit from a variable position in
10532 a constant that has only a single bit set and are comparing it
10533 with zero, we can convert this into an equality comparison
10534 between the position and the location of the single bit. */
10535 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10536 have already reduced the shift count modulo the word size. */
10537 if (!SHIFT_COUNT_TRUNCATED
10538 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
10539 && XEXP (op0
, 1) == const1_rtx
10540 && equality_comparison_p
&& const_op
== 0
10541 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10543 if (BITS_BIG_ENDIAN
)
10545 enum machine_mode new_mode
10546 = mode_for_extraction (EP_extzv
, 1);
10547 if (new_mode
== MAX_MACHINE_MODE
)
10548 i
= BITS_PER_WORD
- 1 - i
;
10552 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10556 op0
= XEXP (op0
, 2);
10560 /* Result is nonzero iff shift count is equal to I. */
10561 code
= reverse_condition (code
);
10565 /* ... fall through ... */
10568 tem
= expand_compound_operation (op0
);
10577 /* If testing for equality, we can take the NOT of the constant. */
10578 if (equality_comparison_p
10579 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10581 op0
= XEXP (op0
, 0);
10586 /* If just looking at the sign bit, reverse the sense of the
10588 if (sign_bit_comparison_p
)
10590 op0
= XEXP (op0
, 0);
10591 code
= (code
== GE
? LT
: GE
);
10597 /* If testing for equality, we can take the NEG of the constant. */
10598 if (equality_comparison_p
10599 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10601 op0
= XEXP (op0
, 0);
10606 /* The remaining cases only apply to comparisons with zero. */
10610 /* When X is ABS or is known positive,
10611 (neg X) is < 0 if and only if X != 0. */
10613 if (sign_bit_comparison_p
10614 && (GET_CODE (XEXP (op0
, 0)) == ABS
10615 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10616 && (nonzero_bits (XEXP (op0
, 0), mode
)
10617 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10619 op0
= XEXP (op0
, 0);
10620 code
= (code
== LT
? NE
: EQ
);
10624 /* If we have NEG of something whose two high-order bits are the
10625 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10626 if (num_sign_bit_copies (op0
, mode
) >= 2)
10628 op0
= XEXP (op0
, 0);
10629 code
= swap_condition (code
);
10635 /* If we are testing equality and our count is a constant, we
10636 can perform the inverse operation on our RHS. */
10637 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10638 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10639 op1
, XEXP (op0
, 1))) != 0)
10641 op0
= XEXP (op0
, 0);
10646 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10647 a particular bit. Convert it to an AND of a constant of that
10648 bit. This will be converted into a ZERO_EXTRACT. */
10649 if (const_op
== 0 && sign_bit_comparison_p
10650 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10651 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10653 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10656 - INTVAL (XEXP (op0
, 1)))));
10657 code
= (code
== LT
? NE
: EQ
);
10661 /* Fall through. */
10664 /* ABS is ignorable inside an equality comparison with zero. */
10665 if (const_op
== 0 && equality_comparison_p
)
10667 op0
= XEXP (op0
, 0);
10673 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10674 to (compare FOO CONST) if CONST fits in FOO's mode and we
10675 are either testing inequality or have an unsigned comparison
10676 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10677 if (! unsigned_comparison_p
10678 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10679 <= HOST_BITS_PER_WIDE_INT
)
10680 && ((unsigned HOST_WIDE_INT
) const_op
10681 < (((unsigned HOST_WIDE_INT
) 1
10682 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10684 op0
= XEXP (op0
, 0);
10690 /* Check for the case where we are comparing A - C1 with C2,
10691 both constants are smaller than 1/2 the maximum positive
10692 value in MODE, and the comparison is equality or unsigned.
10693 In that case, if A is either zero-extended to MODE or has
10694 sufficient sign bits so that the high-order bit in MODE
10695 is a copy of the sign in the inner mode, we can prove that it is
10696 safe to do the operation in the wider mode. This simplifies
10697 many range checks. */
10699 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10700 && subreg_lowpart_p (op0
)
10701 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10702 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10703 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10704 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10705 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10706 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10707 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10708 GET_MODE (SUBREG_REG (op0
)))
10709 & ~GET_MODE_MASK (mode
))
10710 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10711 GET_MODE (SUBREG_REG (op0
)))
10713 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10714 - GET_MODE_BITSIZE (mode
)))))
10716 op0
= SUBREG_REG (op0
);
10720 /* If the inner mode is narrower and we are extracting the low part,
10721 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10722 if (subreg_lowpart_p (op0
)
10723 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10724 /* Fall through */ ;
10728 /* ... fall through ... */
10731 if ((unsigned_comparison_p
|| equality_comparison_p
)
10732 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10733 <= HOST_BITS_PER_WIDE_INT
)
10734 && ((unsigned HOST_WIDE_INT
) const_op
10735 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10737 op0
= XEXP (op0
, 0);
10743 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10744 this for equality comparisons due to pathological cases involving
10746 if (equality_comparison_p
10747 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10748 op1
, XEXP (op0
, 1))))
10750 op0
= XEXP (op0
, 0);
10755 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10756 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10757 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10759 op0
= XEXP (XEXP (op0
, 0), 0);
10760 code
= (code
== LT
? EQ
: NE
);
10766 /* We used to optimize signed comparisons against zero, but that
10767 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10768 arrive here as equality comparisons, or (GEU, LTU) are
10769 optimized away. No need to special-case them. */
10771 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10772 (eq B (minus A C)), whichever simplifies. We can only do
10773 this for equality comparisons due to pathological cases involving
10775 if (equality_comparison_p
10776 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10777 XEXP (op0
, 1), op1
)))
10779 op0
= XEXP (op0
, 0);
10784 if (equality_comparison_p
10785 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10786 XEXP (op0
, 0), op1
)))
10788 op0
= XEXP (op0
, 1);
10793 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10794 of bits in X minus 1, is one iff X > 0. */
10795 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10796 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10797 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10799 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10801 op0
= XEXP (op0
, 1);
10802 code
= (code
== GE
? LE
: GT
);
10808 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10809 if C is zero or B is a constant. */
10810 if (equality_comparison_p
10811 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10812 XEXP (op0
, 1), op1
)))
10814 op0
= XEXP (op0
, 0);
10821 case UNEQ
: case LTGT
:
10822 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10823 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10824 case UNORDERED
: case ORDERED
:
10825 /* We can't do anything if OP0 is a condition code value, rather
10826 than an actual data value. */
10828 || CC0_P (XEXP (op0
, 0))
10829 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10832 /* Get the two operands being compared. */
10833 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10834 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10836 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10838 /* Check for the cases where we simply want the result of the
10839 earlier test or the opposite of that result. */
10840 if (code
== NE
|| code
== EQ
10841 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10842 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10843 && (STORE_FLAG_VALUE
10844 & (((HOST_WIDE_INT
) 1
10845 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10846 && (code
== LT
|| code
== GE
)))
10848 enum rtx_code new_code
;
10849 if (code
== LT
|| code
== NE
)
10850 new_code
= GET_CODE (op0
);
10852 new_code
= combine_reversed_comparison_code (op0
);
10854 if (new_code
!= UNKNOWN
)
10865 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10867 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10868 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10869 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10871 op0
= XEXP (op0
, 1);
10872 code
= (code
== GE
? GT
: LE
);
10878 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10879 will be converted to a ZERO_EXTRACT later. */
10880 if (const_op
== 0 && equality_comparison_p
10881 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10882 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10884 op0
= simplify_and_const_int
10885 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10887 XEXP (XEXP (op0
, 0), 1)),
10888 (HOST_WIDE_INT
) 1);
10892 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10893 zero and X is a comparison and C1 and C2 describe only bits set
10894 in STORE_FLAG_VALUE, we can compare with X. */
10895 if (const_op
== 0 && equality_comparison_p
10896 && mode_width
<= HOST_BITS_PER_WIDE_INT
10897 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10898 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10899 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10900 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10901 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10903 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10904 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10905 if ((~STORE_FLAG_VALUE
& mask
) == 0
10906 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10907 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10908 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10910 op0
= XEXP (XEXP (op0
, 0), 0);
10915 /* If we are doing an equality comparison of an AND of a bit equal
10916 to the sign bit, replace this with a LT or GE comparison of
10917 the underlying value. */
10918 if (equality_comparison_p
10920 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10921 && mode_width
<= HOST_BITS_PER_WIDE_INT
10922 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10923 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10925 op0
= XEXP (op0
, 0);
10926 code
= (code
== EQ
? GE
: LT
);
10930 /* If this AND operation is really a ZERO_EXTEND from a narrower
10931 mode, the constant fits within that mode, and this is either an
10932 equality or unsigned comparison, try to do this comparison in
10933 the narrower mode. */
10934 if ((equality_comparison_p
|| unsigned_comparison_p
)
10935 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10936 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10937 & GET_MODE_MASK (mode
))
10939 && const_op
>> i
== 0
10940 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10942 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10946 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10947 fits in both M1 and M2 and the SUBREG is either paradoxical
10948 or represents the low part, permute the SUBREG and the AND
10950 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10952 unsigned HOST_WIDE_INT c1
;
10953 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10954 /* Require an integral mode, to avoid creating something like
10956 if (SCALAR_INT_MODE_P (tmode
)
10957 /* It is unsafe to commute the AND into the SUBREG if the
10958 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10959 not defined. As originally written the upper bits
10960 have a defined value due to the AND operation.
10961 However, if we commute the AND inside the SUBREG then
10962 they no longer have defined values and the meaning of
10963 the code has been changed. */
10965 #ifdef WORD_REGISTER_OPERATIONS
10966 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10967 && mode_width
<= BITS_PER_WORD
)
10969 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10970 && subreg_lowpart_p (XEXP (op0
, 0))))
10971 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10972 && mode_width
<= HOST_BITS_PER_WIDE_INT
10973 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10974 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10975 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10977 && c1
!= GET_MODE_MASK (tmode
))
10979 op0
= gen_binary (AND
, tmode
,
10980 SUBREG_REG (XEXP (op0
, 0)),
10981 gen_int_mode (c1
, tmode
));
10982 op0
= gen_lowpart_for_combine (mode
, op0
);
10987 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10988 if (const_op
== 0 && equality_comparison_p
10989 && XEXP (op0
, 1) == const1_rtx
10990 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10992 op0
= simplify_and_const_int
10993 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10994 code
= (code
== NE
? EQ
: NE
);
10998 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10999 (eq (and (lshiftrt X) 1) 0).
11000 Also handle the case where (not X) is expressed using xor. */
11001 if (const_op
== 0 && equality_comparison_p
11002 && XEXP (op0
, 1) == const1_rtx
11003 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11005 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11006 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11008 if (GET_CODE (shift_op
) == NOT
11009 || (GET_CODE (shift_op
) == XOR
11010 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
11011 && GET_CODE (shift_count
) == CONST_INT
11012 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11013 && (INTVAL (XEXP (shift_op
, 1))
11014 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11016 op0
= simplify_and_const_int
11018 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11019 (HOST_WIDE_INT
) 1);
11020 code
= (code
== NE
? EQ
: NE
);
11027 /* If we have (compare (ashift FOO N) (const_int C)) and
11028 the high order N bits of FOO (N+1 if an inequality comparison)
11029 are known to be zero, we can do this by comparing FOO with C
11030 shifted right N bits so long as the low-order N bits of C are
11032 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11033 && INTVAL (XEXP (op0
, 1)) >= 0
11034 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11035 < HOST_BITS_PER_WIDE_INT
)
11037 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11038 && mode_width
<= HOST_BITS_PER_WIDE_INT
11039 && (nonzero_bits (XEXP (op0
, 0), mode
)
11040 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11041 + ! equality_comparison_p
))) == 0)
11043 /* We must perform a logical shift, not an arithmetic one,
11044 as we want the top N bits of C to be zero. */
11045 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11047 temp
>>= INTVAL (XEXP (op0
, 1));
11048 op1
= gen_int_mode (temp
, mode
);
11049 op0
= XEXP (op0
, 0);
11053 /* If we are doing a sign bit comparison, it means we are testing
11054 a particular bit. Convert it to the appropriate AND. */
11055 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11056 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11058 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11061 - INTVAL (XEXP (op0
, 1)))));
11062 code
= (code
== LT
? NE
: EQ
);
11066 /* If this an equality comparison with zero and we are shifting
11067 the low bit to the sign bit, we can convert this to an AND of the
11069 if (const_op
== 0 && equality_comparison_p
11070 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11071 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11074 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11075 (HOST_WIDE_INT
) 1);
11081 /* If this is an equality comparison with zero, we can do this
11082 as a logical shift, which might be much simpler. */
11083 if (equality_comparison_p
&& const_op
== 0
11084 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11086 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11088 INTVAL (XEXP (op0
, 1)));
11092 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11093 do the comparison in a narrower mode. */
11094 if (! unsigned_comparison_p
11095 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11096 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11097 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11098 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11099 MODE_INT
, 1)) != BLKmode
11100 && (((unsigned HOST_WIDE_INT
) const_op
11101 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11102 <= GET_MODE_MASK (tmode
)))
11104 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
11108 /* Likewise if OP0 is a PLUS of a sign extension with a
11109 constant, which is usually represented with the PLUS
11110 between the shifts. */
11111 if (! unsigned_comparison_p
11112 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11113 && GET_CODE (XEXP (op0
, 0)) == PLUS
11114 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11115 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11116 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11117 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11118 MODE_INT
, 1)) != BLKmode
11119 && (((unsigned HOST_WIDE_INT
) const_op
11120 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11121 <= GET_MODE_MASK (tmode
)))
11123 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11124 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11125 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11128 op0
= gen_binary (PLUS
, tmode
,
11129 gen_lowpart_for_combine (tmode
, inner
),
11134 /* ... fall through ... */
11136 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11137 the low order N bits of FOO are known to be zero, we can do this
11138 by comparing FOO with C shifted left N bits so long as no
11139 overflow occurs. */
11140 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11141 && INTVAL (XEXP (op0
, 1)) >= 0
11142 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11143 && mode_width
<= HOST_BITS_PER_WIDE_INT
11144 && (nonzero_bits (XEXP (op0
, 0), mode
)
11145 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11146 && (((unsigned HOST_WIDE_INT
) const_op
11147 + (GET_CODE (op0
) != LSHIFTRT
11148 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11151 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11153 /* If the shift was logical, then we must make the condition
11155 if (GET_CODE (op0
) == LSHIFTRT
)
11156 code
= unsigned_condition (code
);
11158 const_op
<<= INTVAL (XEXP (op0
, 1));
11159 op1
= GEN_INT (const_op
);
11160 op0
= XEXP (op0
, 0);
11164 /* If we are using this shift to extract just the sign bit, we
11165 can replace this with an LT or GE comparison. */
11167 && (equality_comparison_p
|| sign_bit_comparison_p
)
11168 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11169 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11172 op0
= XEXP (op0
, 0);
11173 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11185 /* Now make any compound operations involved in this comparison. Then,
11186 check for an outmost SUBREG on OP0 that is not doing anything or is
11187 paradoxical. The latter transformation must only be performed when
11188 it is known that the "extra" bits will be the same in op0 and op1 or
11189 that they don't matter. There are three cases to consider:
11191 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11192 care bits and we can assume they have any convenient value. So
11193 making the transformation is safe.
11195 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11196 In this case the upper bits of op0 are undefined. We should not make
11197 the simplification in that case as we do not know the contents of
11200 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11201 NIL. In that case we know those bits are zeros or ones. We must
11202 also be sure that they are the same as the upper bits of op1.
11204 We can never remove a SUBREG for a non-equality comparison because
11205 the sign bit is in a different place in the underlying object. */
11207 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11208 op1
= make_compound_operation (op1
, SET
);
11210 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11211 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11212 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11213 && (code
== NE
|| code
== EQ
))
11215 if (GET_MODE_SIZE (GET_MODE (op0
))
11216 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11218 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11220 if (GET_CODE (SUBREG_REG (op0
)) == REG
)
11222 op0
= SUBREG_REG (op0
);
11223 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11226 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11227 <= HOST_BITS_PER_WIDE_INT
)
11228 && (nonzero_bits (SUBREG_REG (op0
),
11229 GET_MODE (SUBREG_REG (op0
)))
11230 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11232 tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)), op1
);
11234 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11235 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11236 op0
= SUBREG_REG (op0
), op1
= tem
;
11240 /* We now do the opposite procedure: Some machines don't have compare
11241 insns in all modes. If OP0's mode is an integer mode smaller than a
11242 word and we can't do a compare in that mode, see if there is a larger
11243 mode for which we can do the compare. There are a number of cases in
11244 which we can use the wider mode. */
11246 mode
= GET_MODE (op0
);
11247 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11248 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11249 && ! have_insn_for (COMPARE
, mode
))
11250 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11252 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11253 tmode
= GET_MODE_WIDER_MODE (tmode
))
11254 if (have_insn_for (COMPARE
, tmode
))
11258 /* If the only nonzero bits in OP0 and OP1 are those in the
11259 narrower mode and this is an equality or unsigned comparison,
11260 we can use the wider mode. Similarly for sign-extended
11261 values, in which case it is true for all comparisons. */
11262 zero_extended
= ((code
== EQ
|| code
== NE
11263 || code
== GEU
|| code
== GTU
11264 || code
== LEU
|| code
== LTU
)
11265 && (nonzero_bits (op0
, tmode
)
11266 & ~GET_MODE_MASK (mode
)) == 0
11267 && ((GET_CODE (op1
) == CONST_INT
11268 || (nonzero_bits (op1
, tmode
)
11269 & ~GET_MODE_MASK (mode
)) == 0)));
11272 || ((num_sign_bit_copies (op0
, tmode
)
11273 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11274 - GET_MODE_BITSIZE (mode
)))
11275 && (num_sign_bit_copies (op1
, tmode
)
11276 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11277 - GET_MODE_BITSIZE (mode
)))))
11279 /* If OP0 is an AND and we don't have an AND in MODE either,
11280 make a new AND in the proper mode. */
11281 if (GET_CODE (op0
) == AND
11282 && !have_insn_for (AND
, mode
))
11283 op0
= gen_binary (AND
, tmode
,
11284 gen_lowpart_for_combine (tmode
,
11286 gen_lowpart_for_combine (tmode
,
11289 op0
= gen_lowpart_for_combine (tmode
, op0
);
11290 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11291 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11292 op1
= gen_lowpart_for_combine (tmode
, op1
);
11296 /* If this is a test for negative, we can make an explicit
11297 test of the sign bit. */
11299 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11300 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11302 op0
= gen_binary (AND
, tmode
,
11303 gen_lowpart_for_combine (tmode
, op0
),
11304 GEN_INT ((HOST_WIDE_INT
) 1
11305 << (GET_MODE_BITSIZE (mode
) - 1)));
11306 code
= (code
== LT
) ? NE
: EQ
;
11311 #ifdef CANONICALIZE_COMPARISON
11312 /* If this machine only supports a subset of valid comparisons, see if we
11313 can convert an unsupported one into a supported one. */
11314 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11323 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11324 searching backward. */
11325 static enum rtx_code
11326 combine_reversed_comparison_code (rtx exp
)
11328 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11331 if (code1
!= UNKNOWN
11332 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11334 /* Otherwise try and find where the condition codes were last set and
11336 x
= get_last_value (XEXP (exp
, 0));
11337 if (!x
|| GET_CODE (x
) != COMPARE
)
11339 return reversed_comparison_code_parts (GET_CODE (exp
),
11340 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11343 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11344 Return NULL_RTX in case we fail to do the reversal. */
11346 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11348 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11349 if (reversed_code
== UNKNOWN
)
11352 return gen_binary (reversed_code
, mode
, op0
, op1
);
11355 /* Utility function for following routine. Called when X is part of a value
11356 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11357 for each register mentioned. Similar to mention_regs in cse.c */
11360 update_table_tick (rtx x
)
11362 enum rtx_code code
= GET_CODE (x
);
11363 const char *fmt
= GET_RTX_FORMAT (code
);
11368 unsigned int regno
= REGNO (x
);
11369 unsigned int endregno
11370 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11371 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11374 for (r
= regno
; r
< endregno
; r
++)
11375 reg_last_set_table_tick
[r
] = label_tick
;
11380 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11381 /* Note that we can't have an "E" in values stored; see
11382 get_last_value_validate. */
11385 /* Check for identical subexpressions. If x contains
11386 identical subexpression we only have to traverse one of
11389 && (GET_RTX_CLASS (code
) == '2'
11390 || GET_RTX_CLASS (code
) == 'c'))
11392 /* Note that at this point x1 has already been
11394 rtx x0
= XEXP (x
, 0);
11395 rtx x1
= XEXP (x
, 1);
11397 /* If x0 and x1 are identical then there is no need to
11402 /* If x0 is identical to a subexpression of x1 then while
11403 processing x1, x0 has already been processed. Thus we
11404 are done with x. */
11405 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11406 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11407 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11410 /* If x1 is identical to a subexpression of x0 then we
11411 still have to process the rest of x0. */
11412 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11413 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11414 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11416 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11421 update_table_tick (XEXP (x
, i
));
11425 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11426 are saying that the register is clobbered and we no longer know its
11427 value. If INSN is zero, don't update reg_last_set; this is only permitted
11428 with VALUE also zero and is used to invalidate the register. */
11431 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11433 unsigned int regno
= REGNO (reg
);
11434 unsigned int endregno
11435 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11436 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11439 /* If VALUE contains REG and we have a previous value for REG, substitute
11440 the previous value. */
11441 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11445 /* Set things up so get_last_value is allowed to see anything set up to
11447 subst_low_cuid
= INSN_CUID (insn
);
11448 tem
= get_last_value (reg
);
11450 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11451 it isn't going to be useful and will take a lot of time to process,
11452 so just use the CLOBBER. */
11456 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11457 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11458 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11459 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11460 tem
= XEXP (tem
, 0);
11462 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11466 /* For each register modified, show we don't know its value, that
11467 we don't know about its bitwise content, that its value has been
11468 updated, and that we don't know the location of the death of the
11470 for (i
= regno
; i
< endregno
; i
++)
11473 reg_last_set
[i
] = insn
;
11475 reg_last_set_value
[i
] = 0;
11476 reg_last_set_mode
[i
] = 0;
11477 reg_last_set_nonzero_bits
[i
] = 0;
11478 reg_last_set_sign_bit_copies
[i
] = 0;
11479 reg_last_death
[i
] = 0;
11482 /* Mark registers that are being referenced in this value. */
11484 update_table_tick (value
);
11486 /* Now update the status of each register being set.
11487 If someone is using this register in this block, set this register
11488 to invalid since we will get confused between the two lives in this
11489 basic block. This makes using this register always invalid. In cse, we
11490 scan the table to invalidate all entries using this register, but this
11491 is too much work for us. */
11493 for (i
= regno
; i
< endregno
; i
++)
11495 reg_last_set_label
[i
] = label_tick
;
11496 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11497 reg_last_set_invalid
[i
] = 1;
11499 reg_last_set_invalid
[i
] = 0;
11502 /* The value being assigned might refer to X (like in "x++;"). In that
11503 case, we must replace it with (clobber (const_int 0)) to prevent
11505 if (value
&& ! get_last_value_validate (&value
, insn
,
11506 reg_last_set_label
[regno
], 0))
11508 value
= copy_rtx (value
);
11509 if (! get_last_value_validate (&value
, insn
,
11510 reg_last_set_label
[regno
], 1))
11514 /* For the main register being modified, update the value, the mode, the
11515 nonzero bits, and the number of sign bit copies. */
11517 reg_last_set_value
[regno
] = value
;
11521 enum machine_mode mode
= GET_MODE (reg
);
11522 subst_low_cuid
= INSN_CUID (insn
);
11523 reg_last_set_mode
[regno
] = mode
;
11524 if (GET_MODE_CLASS (mode
) == MODE_INT
11525 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11526 mode
= nonzero_bits_mode
;
11527 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11528 reg_last_set_sign_bit_copies
[regno
]
11529 = num_sign_bit_copies (value
, GET_MODE (reg
));
11533 /* Called via note_stores from record_dead_and_set_regs to handle one
11534 SET or CLOBBER in an insn. DATA is the instruction in which the
11535 set is occurring. */
11538 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11540 rtx record_dead_insn
= (rtx
) data
;
11542 if (GET_CODE (dest
) == SUBREG
)
11543 dest
= SUBREG_REG (dest
);
11545 if (GET_CODE (dest
) == REG
)
11547 /* If we are setting the whole register, we know its value. Otherwise
11548 show that we don't know the value. We can handle SUBREG in
11550 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11551 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11552 else if (GET_CODE (setter
) == SET
11553 && GET_CODE (SET_DEST (setter
)) == SUBREG
11554 && SUBREG_REG (SET_DEST (setter
)) == dest
11555 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11556 && subreg_lowpart_p (SET_DEST (setter
)))
11557 record_value_for_reg (dest
, record_dead_insn
,
11558 gen_lowpart_for_combine (GET_MODE (dest
),
11559 SET_SRC (setter
)));
11561 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11563 else if (GET_CODE (dest
) == MEM
11564 /* Ignore pushes, they clobber nothing. */
11565 && ! push_operand (dest
, GET_MODE (dest
)))
11566 mem_last_set
= INSN_CUID (record_dead_insn
);
11569 /* Update the records of when each REG was most recently set or killed
11570 for the things done by INSN. This is the last thing done in processing
11571 INSN in the combiner loop.
11573 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11574 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11575 and also the similar information mem_last_set (which insn most recently
11576 modified memory) and last_call_cuid (which insn was the most recent
11577 subroutine call). */
11580 record_dead_and_set_regs (rtx insn
)
11585 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11587 if (REG_NOTE_KIND (link
) == REG_DEAD
11588 && GET_CODE (XEXP (link
, 0)) == REG
)
11590 unsigned int regno
= REGNO (XEXP (link
, 0));
11591 unsigned int endregno
11592 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11593 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11596 for (i
= regno
; i
< endregno
; i
++)
11597 reg_last_death
[i
] = insn
;
11599 else if (REG_NOTE_KIND (link
) == REG_INC
)
11600 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11603 if (GET_CODE (insn
) == CALL_INSN
)
11605 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11606 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11608 reg_last_set_value
[i
] = 0;
11609 reg_last_set_mode
[i
] = 0;
11610 reg_last_set_nonzero_bits
[i
] = 0;
11611 reg_last_set_sign_bit_copies
[i
] = 0;
11612 reg_last_death
[i
] = 0;
11615 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11617 /* Don't bother recording what this insn does. It might set the
11618 return value register, but we can't combine into a call
11619 pattern anyway, so there's no point trying (and it may cause
11620 a crash, if e.g. we wind up asking for last_set_value of a
11621 SUBREG of the return value register). */
11625 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11628 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11629 register present in the SUBREG, so for each such SUBREG go back and
11630 adjust nonzero and sign bit information of the registers that are
11631 known to have some zero/sign bits set.
11633 This is needed because when combine blows the SUBREGs away, the
11634 information on zero/sign bits is lost and further combines can be
11635 missed because of that. */
11638 record_promoted_value (rtx insn
, rtx subreg
)
11641 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11642 enum machine_mode mode
= GET_MODE (subreg
);
11644 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11647 for (links
= LOG_LINKS (insn
); links
;)
11649 insn
= XEXP (links
, 0);
11650 set
= single_set (insn
);
11652 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11653 || REGNO (SET_DEST (set
)) != regno
11654 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11656 links
= XEXP (links
, 1);
11660 if (reg_last_set
[regno
] == insn
)
11662 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11663 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11666 if (GET_CODE (SET_SRC (set
)) == REG
)
11668 regno
= REGNO (SET_SRC (set
));
11669 links
= LOG_LINKS (insn
);
11676 /* Scan X for promoted SUBREGs. For each one found,
11677 note what it implies to the registers used in it. */
11680 check_promoted_subreg (rtx insn
, rtx x
)
11682 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11683 && GET_CODE (SUBREG_REG (x
)) == REG
)
11684 record_promoted_value (insn
, x
);
11687 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11690 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11694 check_promoted_subreg (insn
, XEXP (x
, i
));
11698 if (XVEC (x
, i
) != 0)
11699 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11700 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11706 /* Utility routine for the following function. Verify that all the registers
11707 mentioned in *LOC are valid when *LOC was part of a value set when
11708 label_tick == TICK. Return 0 if some are not.
11710 If REPLACE is nonzero, replace the invalid reference with
11711 (clobber (const_int 0)) and return 1. This replacement is useful because
11712 we often can get useful information about the form of a value (e.g., if
11713 it was produced by a shift that always produces -1 or 0) even though
11714 we don't know exactly what registers it was produced from. */
11717 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11720 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11721 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11724 if (GET_CODE (x
) == REG
)
11726 unsigned int regno
= REGNO (x
);
11727 unsigned int endregno
11728 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11729 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11732 for (j
= regno
; j
< endregno
; j
++)
11733 if (reg_last_set_invalid
[j
]
11734 /* If this is a pseudo-register that was only set once and not
11735 live at the beginning of the function, it is always valid. */
11736 || (! (regno
>= FIRST_PSEUDO_REGISTER
11737 && REG_N_SETS (regno
) == 1
11738 && (! REGNO_REG_SET_P
11739 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11740 && reg_last_set_label
[j
] > tick
))
11743 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11749 /* If this is a memory reference, make sure that there were
11750 no stores after it that might have clobbered the value. We don't
11751 have alias info, so we assume any store invalidates it. */
11752 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11753 && INSN_CUID (insn
) <= mem_last_set
)
11756 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11760 for (i
= 0; i
< len
; i
++)
11764 /* Check for identical subexpressions. If x contains
11765 identical subexpression we only have to traverse one of
11768 && (GET_RTX_CLASS (GET_CODE (x
)) == '2'
11769 || GET_RTX_CLASS (GET_CODE (x
)) == 'c'))
11771 /* Note that at this point x0 has already been checked
11772 and found valid. */
11773 rtx x0
= XEXP (x
, 0);
11774 rtx x1
= XEXP (x
, 1);
11776 /* If x0 and x1 are identical then x is also valid. */
11780 /* If x1 is identical to a subexpression of x0 then
11781 while checking x0, x1 has already been checked. Thus
11782 it is valid and so as x. */
11783 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11784 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11785 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11788 /* If x0 is identical to a subexpression of x1 then x is
11789 valid iff the rest of x1 is valid. */
11790 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11791 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11792 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11794 get_last_value_validate (&XEXP (x1
,
11795 x0
== XEXP (x1
, 0) ? 1 : 0),
11796 insn
, tick
, replace
);
11799 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11803 /* Don't bother with these. They shouldn't occur anyway. */
11804 else if (fmt
[i
] == 'E')
11808 /* If we haven't found a reason for it to be invalid, it is valid. */
11812 /* Get the last value assigned to X, if known. Some registers
11813 in the value may be replaced with (clobber (const_int 0)) if their value
11814 is known longer known reliably. */
11817 get_last_value (rtx x
)
11819 unsigned int regno
;
11822 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11823 then convert it to the desired mode. If this is a paradoxical SUBREG,
11824 we cannot predict what values the "extra" bits might have. */
11825 if (GET_CODE (x
) == SUBREG
11826 && subreg_lowpart_p (x
)
11827 && (GET_MODE_SIZE (GET_MODE (x
))
11828 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11829 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11830 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11832 if (GET_CODE (x
) != REG
)
11836 value
= reg_last_set_value
[regno
];
11838 /* If we don't have a value, or if it isn't for this basic block and
11839 it's either a hard register, set more than once, or it's a live
11840 at the beginning of the function, return 0.
11842 Because if it's not live at the beginning of the function then the reg
11843 is always set before being used (is never used without being set).
11844 And, if it's set only once, and it's always set before use, then all
11845 uses must have the same last value, even if it's not from this basic
11849 || (reg_last_set_label
[regno
] != label_tick
11850 && (regno
< FIRST_PSEUDO_REGISTER
11851 || REG_N_SETS (regno
) != 1
11852 || (REGNO_REG_SET_P
11853 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11856 /* If the value was set in a later insn than the ones we are processing,
11857 we can't use it even if the register was only set once. */
11858 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11861 /* If the value has all its registers valid, return it. */
11862 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11863 reg_last_set_label
[regno
], 0))
11866 /* Otherwise, make a copy and replace any invalid register with
11867 (clobber (const_int 0)). If that fails for some reason, return 0. */
11869 value
= copy_rtx (value
);
11870 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11871 reg_last_set_label
[regno
], 1))
11877 /* Return nonzero if expression X refers to a REG or to memory
11878 that is set in an instruction more recent than FROM_CUID. */
11881 use_crosses_set_p (rtx x
, int from_cuid
)
11885 enum rtx_code code
= GET_CODE (x
);
11889 unsigned int regno
= REGNO (x
);
11890 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11891 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11893 #ifdef PUSH_ROUNDING
11894 /* Don't allow uses of the stack pointer to be moved,
11895 because we don't know whether the move crosses a push insn. */
11896 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11899 for (; regno
< endreg
; regno
++)
11900 if (reg_last_set
[regno
]
11901 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11906 if (code
== MEM
&& mem_last_set
> from_cuid
)
11909 fmt
= GET_RTX_FORMAT (code
);
11911 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11916 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11917 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11920 else if (fmt
[i
] == 'e'
11921 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11927 /* Define three variables used for communication between the following
11930 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11931 static int reg_dead_flag
;
11933 /* Function called via note_stores from reg_dead_at_p.
11935 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11936 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11939 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11941 unsigned int regno
, endregno
;
11943 if (GET_CODE (dest
) != REG
)
11946 regno
= REGNO (dest
);
11947 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11948 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11950 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11951 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11954 /* Return nonzero if REG is known to be dead at INSN.
11956 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11957 referencing REG, it is dead. If we hit a SET referencing REG, it is
11958 live. Otherwise, see if it is live or dead at the start of the basic
11959 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11960 must be assumed to be always live. */
11963 reg_dead_at_p (rtx reg
, rtx insn
)
11968 /* Set variables for reg_dead_at_p_1. */
11969 reg_dead_regno
= REGNO (reg
);
11970 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11971 ? HARD_REGNO_NREGS (reg_dead_regno
,
11977 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11978 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11980 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11981 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11985 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11986 beginning of function. */
11987 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11988 insn
= prev_nonnote_insn (insn
))
11990 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11992 return reg_dead_flag
== 1 ? 1 : 0;
11994 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11998 /* Get the basic block that we were in. */
12000 block
= ENTRY_BLOCK_PTR
->next_bb
;
12003 FOR_EACH_BB (block
)
12004 if (insn
== BB_HEAD (block
))
12007 if (block
== EXIT_BLOCK_PTR
)
12011 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12012 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
12018 /* Note hard registers in X that are used. This code is similar to
12019 that in flow.c, but much simpler since we don't care about pseudos. */
12022 mark_used_regs_combine (rtx x
)
12024 RTX_CODE code
= GET_CODE (x
);
12025 unsigned int regno
;
12038 case ADDR_DIFF_VEC
:
12041 /* CC0 must die in the insn after it is set, so we don't need to take
12042 special note of it here. */
12048 /* If we are clobbering a MEM, mark any hard registers inside the
12049 address as used. */
12050 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12051 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12056 /* A hard reg in a wide mode may really be multiple registers.
12057 If so, mark all of them just like the first. */
12058 if (regno
< FIRST_PSEUDO_REGISTER
)
12060 unsigned int endregno
, r
;
12062 /* None of this applies to the stack, frame or arg pointers. */
12063 if (regno
== STACK_POINTER_REGNUM
12064 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12065 || regno
== HARD_FRAME_POINTER_REGNUM
12067 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12068 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12070 || regno
== FRAME_POINTER_REGNUM
)
12073 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12074 for (r
= regno
; r
< endregno
; r
++)
12075 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12081 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12083 rtx testreg
= SET_DEST (x
);
12085 while (GET_CODE (testreg
) == SUBREG
12086 || GET_CODE (testreg
) == ZERO_EXTRACT
12087 || GET_CODE (testreg
) == SIGN_EXTRACT
12088 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12089 testreg
= XEXP (testreg
, 0);
12091 if (GET_CODE (testreg
) == MEM
)
12092 mark_used_regs_combine (XEXP (testreg
, 0));
12094 mark_used_regs_combine (SET_SRC (x
));
12102 /* Recursively scan the operands of this expression. */
12105 const char *fmt
= GET_RTX_FORMAT (code
);
12107 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12110 mark_used_regs_combine (XEXP (x
, i
));
12111 else if (fmt
[i
] == 'E')
12115 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12116 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12122 /* Remove register number REGNO from the dead registers list of INSN.
12124 Return the note used to record the death, if there was one. */
12127 remove_death (unsigned int regno
, rtx insn
)
12129 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12133 REG_N_DEATHS (regno
)--;
12134 remove_note (insn
, note
);
12140 /* For each register (hardware or pseudo) used within expression X, if its
12141 death is in an instruction with cuid between FROM_CUID (inclusive) and
12142 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12143 list headed by PNOTES.
12145 That said, don't move registers killed by maybe_kill_insn.
12147 This is done when X is being merged by combination into TO_INSN. These
12148 notes will then be distributed as needed. */
12151 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12156 enum rtx_code code
= GET_CODE (x
);
12160 unsigned int regno
= REGNO (x
);
12161 rtx where_dead
= reg_last_death
[regno
];
12162 rtx before_dead
, after_dead
;
12164 /* Don't move the register if it gets killed in between from and to. */
12165 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12166 && ! reg_referenced_p (x
, maybe_kill_insn
))
12169 /* WHERE_DEAD could be a USE insn made by combine, so first we
12170 make sure that we have insns with valid INSN_CUID values. */
12171 before_dead
= where_dead
;
12172 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12173 before_dead
= PREV_INSN (before_dead
);
12175 after_dead
= where_dead
;
12176 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12177 after_dead
= NEXT_INSN (after_dead
);
12179 if (before_dead
&& after_dead
12180 && INSN_CUID (before_dead
) >= from_cuid
12181 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12182 || (where_dead
!= after_dead
12183 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12185 rtx note
= remove_death (regno
, where_dead
);
12187 /* It is possible for the call above to return 0. This can occur
12188 when reg_last_death points to I2 or I1 that we combined with.
12189 In that case make a new note.
12191 We must also check for the case where X is a hard register
12192 and NOTE is a death note for a range of hard registers
12193 including X. In that case, we must put REG_DEAD notes for
12194 the remaining registers in place of NOTE. */
12196 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12197 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12198 > GET_MODE_SIZE (GET_MODE (x
))))
12200 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12201 unsigned int deadend
12202 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
12203 GET_MODE (XEXP (note
, 0))));
12204 unsigned int ourend
12205 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12208 for (i
= deadregno
; i
< deadend
; i
++)
12209 if (i
< regno
|| i
>= ourend
)
12210 REG_NOTES (where_dead
)
12211 = gen_rtx_EXPR_LIST (REG_DEAD
,
12213 REG_NOTES (where_dead
));
12216 /* If we didn't find any note, or if we found a REG_DEAD note that
12217 covers only part of the given reg, and we have a multi-reg hard
12218 register, then to be safe we must check for REG_DEAD notes
12219 for each register other than the first. They could have
12220 their own REG_DEAD notes lying around. */
12221 else if ((note
== 0
12223 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12224 < GET_MODE_SIZE (GET_MODE (x
)))))
12225 && regno
< FIRST_PSEUDO_REGISTER
12226 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12228 unsigned int ourend
12229 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12230 unsigned int i
, offset
;
12234 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12238 for (i
= regno
+ offset
; i
< ourend
; i
++)
12239 move_deaths (regno_reg_rtx
[i
],
12240 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12243 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12245 XEXP (note
, 1) = *pnotes
;
12249 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12251 REG_N_DEATHS (regno
)++;
12257 else if (GET_CODE (x
) == SET
)
12259 rtx dest
= SET_DEST (x
);
12261 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12263 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12264 that accesses one word of a multi-word item, some
12265 piece of everything register in the expression is used by
12266 this insn, so remove any old death. */
12267 /* ??? So why do we test for equality of the sizes? */
12269 if (GET_CODE (dest
) == ZERO_EXTRACT
12270 || GET_CODE (dest
) == STRICT_LOW_PART
12271 || (GET_CODE (dest
) == SUBREG
12272 && (((GET_MODE_SIZE (GET_MODE (dest
))
12273 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12274 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12275 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12277 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12281 /* If this is some other SUBREG, we know it replaces the entire
12282 value, so use that as the destination. */
12283 if (GET_CODE (dest
) == SUBREG
)
12284 dest
= SUBREG_REG (dest
);
12286 /* If this is a MEM, adjust deaths of anything used in the address.
12287 For a REG (the only other possibility), the entire value is
12288 being replaced so the old value is not used in this insn. */
12290 if (GET_CODE (dest
) == MEM
)
12291 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12296 else if (GET_CODE (x
) == CLOBBER
)
12299 len
= GET_RTX_LENGTH (code
);
12300 fmt
= GET_RTX_FORMAT (code
);
12302 for (i
= 0; i
< len
; i
++)
12307 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12308 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12311 else if (fmt
[i
] == 'e')
12312 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12316 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12317 pattern of an insn. X must be a REG. */
12320 reg_bitfield_target_p (rtx x
, rtx body
)
12324 if (GET_CODE (body
) == SET
)
12326 rtx dest
= SET_DEST (body
);
12328 unsigned int regno
, tregno
, endregno
, endtregno
;
12330 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12331 target
= XEXP (dest
, 0);
12332 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12333 target
= SUBREG_REG (XEXP (dest
, 0));
12337 if (GET_CODE (target
) == SUBREG
)
12338 target
= SUBREG_REG (target
);
12340 if (GET_CODE (target
) != REG
)
12343 tregno
= REGNO (target
), regno
= REGNO (x
);
12344 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12345 return target
== x
;
12347 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12348 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12350 return endregno
> tregno
&& regno
< endtregno
;
12353 else if (GET_CODE (body
) == PARALLEL
)
12354 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12355 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12361 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12362 as appropriate. I3 and I2 are the insns resulting from the combination
12363 insns including FROM (I2 may be zero).
12365 Each note in the list is either ignored or placed on some insns, depending
12366 on the type of note. */
12369 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12371 rtx note
, next_note
;
12374 for (note
= notes
; note
; note
= next_note
)
12376 rtx place
= 0, place2
= 0;
12378 /* If this NOTE references a pseudo register, ensure it references
12379 the latest copy of that register. */
12380 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12381 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12382 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12384 next_note
= XEXP (note
, 1);
12385 switch (REG_NOTE_KIND (note
))
12389 /* Doesn't matter much where we put this, as long as it's somewhere.
12390 It is preferable to keep these notes on branches, which is most
12391 likely to be i3. */
12395 case REG_VALUE_PROFILE
:
12396 /* Just get rid of this note, as it is unused later anyway. */
12399 case REG_VTABLE_REF
:
12400 /* ??? Should remain with *a particular* memory load. Given the
12401 nature of vtable data, the last insn seems relatively safe. */
12405 case REG_NON_LOCAL_GOTO
:
12406 if (GET_CODE (i3
) == JUMP_INSN
)
12408 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12414 case REG_EH_REGION
:
12415 /* These notes must remain with the call or trapping instruction. */
12416 if (GET_CODE (i3
) == CALL_INSN
)
12418 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12420 else if (flag_non_call_exceptions
)
12422 if (may_trap_p (i3
))
12424 else if (i2
&& may_trap_p (i2
))
12426 /* ??? Otherwise assume we've combined things such that we
12427 can now prove that the instructions can't trap. Drop the
12428 note in this case. */
12434 case REG_ALWAYS_RETURN
:
12437 /* These notes must remain with the call. It should not be
12438 possible for both I2 and I3 to be a call. */
12439 if (GET_CODE (i3
) == CALL_INSN
)
12441 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12448 /* Any clobbers for i3 may still exist, and so we must process
12449 REG_UNUSED notes from that insn.
12451 Any clobbers from i2 or i1 can only exist if they were added by
12452 recog_for_combine. In that case, recog_for_combine created the
12453 necessary REG_UNUSED notes. Trying to keep any original
12454 REG_UNUSED notes from these insns can cause incorrect output
12455 if it is for the same register as the original i3 dest.
12456 In that case, we will notice that the register is set in i3,
12457 and then add a REG_UNUSED note for the destination of i3, which
12458 is wrong. However, it is possible to have REG_UNUSED notes from
12459 i2 or i1 for register which were both used and clobbered, so
12460 we keep notes from i2 or i1 if they will turn into REG_DEAD
12463 /* If this register is set or clobbered in I3, put the note there
12464 unless there is one already. */
12465 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12467 if (from_insn
!= i3
)
12470 if (! (GET_CODE (XEXP (note
, 0)) == REG
12471 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12472 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12475 /* Otherwise, if this register is used by I3, then this register
12476 now dies here, so we must put a REG_DEAD note here unless there
12478 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12479 && ! (GET_CODE (XEXP (note
, 0)) == REG
12480 ? find_regno_note (i3
, REG_DEAD
,
12481 REGNO (XEXP (note
, 0)))
12482 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12484 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12492 /* These notes say something about results of an insn. We can
12493 only support them if they used to be on I3 in which case they
12494 remain on I3. Otherwise they are ignored.
12496 If the note refers to an expression that is not a constant, we
12497 must also ignore the note since we cannot tell whether the
12498 equivalence is still true. It might be possible to do
12499 slightly better than this (we only have a problem if I2DEST
12500 or I1DEST is present in the expression), but it doesn't
12501 seem worth the trouble. */
12503 if (from_insn
== i3
12504 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12509 case REG_NO_CONFLICT
:
12510 /* These notes say something about how a register is used. They must
12511 be present on any use of the register in I2 or I3. */
12512 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12515 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12525 /* This can show up in several ways -- either directly in the
12526 pattern, or hidden off in the constant pool with (or without?)
12527 a REG_EQUAL note. */
12528 /* ??? Ignore the without-reg_equal-note problem for now. */
12529 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12530 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12531 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12532 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12536 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12537 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12538 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12539 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12547 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12548 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12549 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12551 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12553 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12554 LABEL_NUSES (JUMP_LABEL (place
))--;
12557 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12559 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12561 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12562 LABEL_NUSES (JUMP_LABEL (place2
))--;
12568 /* This note says something about the value of a register prior
12569 to the execution of an insn. It is too much trouble to see
12570 if the note is still correct in all situations. It is better
12571 to simply delete it. */
12575 /* If the insn previously containing this note still exists,
12576 put it back where it was. Otherwise move it to the previous
12577 insn. Adjust the corresponding REG_LIBCALL note. */
12578 if (GET_CODE (from_insn
) != NOTE
)
12582 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12583 place
= prev_real_insn (from_insn
);
12585 XEXP (tem
, 0) = place
;
12586 /* If we're deleting the last remaining instruction of a
12587 libcall sequence, don't add the notes. */
12588 else if (XEXP (note
, 0) == from_insn
)
12594 /* This is handled similarly to REG_RETVAL. */
12595 if (GET_CODE (from_insn
) != NOTE
)
12599 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12600 place
= next_real_insn (from_insn
);
12602 XEXP (tem
, 0) = place
;
12603 /* If we're deleting the last remaining instruction of a
12604 libcall sequence, don't add the notes. */
12605 else if (XEXP (note
, 0) == from_insn
)
12611 /* If the register is used as an input in I3, it dies there.
12612 Similarly for I2, if it is nonzero and adjacent to I3.
12614 If the register is not used as an input in either I3 or I2
12615 and it is not one of the registers we were supposed to eliminate,
12616 there are two possibilities. We might have a non-adjacent I2
12617 or we might have somehow eliminated an additional register
12618 from a computation. For example, we might have had A & B where
12619 we discover that B will always be zero. In this case we will
12620 eliminate the reference to A.
12622 In both cases, we must search to see if we can find a previous
12623 use of A and put the death note there. */
12626 && GET_CODE (from_insn
) == CALL_INSN
12627 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12629 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12631 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12632 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12637 basic_block bb
= this_basic_block
;
12639 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12641 if (! INSN_P (tem
))
12643 if (tem
== BB_HEAD (bb
))
12648 /* If the register is being set at TEM, see if that is all
12649 TEM is doing. If so, delete TEM. Otherwise, make this
12650 into a REG_UNUSED note instead. */
12651 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12653 rtx set
= single_set (tem
);
12654 rtx inner_dest
= 0;
12656 rtx cc0_setter
= NULL_RTX
;
12660 for (inner_dest
= SET_DEST (set
);
12661 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12662 || GET_CODE (inner_dest
) == SUBREG
12663 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12664 inner_dest
= XEXP (inner_dest
, 0))
12667 /* Verify that it was the set, and not a clobber that
12668 modified the register.
12670 CC0 targets must be careful to maintain setter/user
12671 pairs. If we cannot delete the setter due to side
12672 effects, mark the user with an UNUSED note instead
12675 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12676 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12678 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12679 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12680 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12684 /* Move the notes and links of TEM elsewhere.
12685 This might delete other dead insns recursively.
12686 First set the pattern to something that won't use
12688 rtx old_notes
= REG_NOTES (tem
);
12690 PATTERN (tem
) = pc_rtx
;
12691 REG_NOTES (tem
) = NULL
;
12693 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12694 distribute_links (LOG_LINKS (tem
));
12696 PUT_CODE (tem
, NOTE
);
12697 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12698 NOTE_SOURCE_FILE (tem
) = 0;
12701 /* Delete the setter too. */
12704 PATTERN (cc0_setter
) = pc_rtx
;
12705 old_notes
= REG_NOTES (cc0_setter
);
12706 REG_NOTES (cc0_setter
) = NULL
;
12708 distribute_notes (old_notes
, cc0_setter
,
12709 cc0_setter
, NULL_RTX
);
12710 distribute_links (LOG_LINKS (cc0_setter
));
12712 PUT_CODE (cc0_setter
, NOTE
);
12713 NOTE_LINE_NUMBER (cc0_setter
)
12714 = NOTE_INSN_DELETED
;
12715 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12719 /* If the register is both set and used here, put the
12720 REG_DEAD note here, but place a REG_UNUSED note
12721 here too unless there already is one. */
12722 else if (reg_referenced_p (XEXP (note
, 0),
12727 if (! find_regno_note (tem
, REG_UNUSED
,
12728 REGNO (XEXP (note
, 0))))
12730 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12735 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12737 /* If there isn't already a REG_UNUSED note, put one
12739 if (! find_regno_note (tem
, REG_UNUSED
,
12740 REGNO (XEXP (note
, 0))))
12745 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12746 || (GET_CODE (tem
) == CALL_INSN
12747 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12751 /* If we are doing a 3->2 combination, and we have a
12752 register which formerly died in i3 and was not used
12753 by i2, which now no longer dies in i3 and is used in
12754 i2 but does not die in i2, and place is between i2
12755 and i3, then we may need to move a link from place to
12757 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12758 && INSN_CUID (place
) > INSN_CUID (i2
)
12760 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12761 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12763 rtx links
= LOG_LINKS (place
);
12764 LOG_LINKS (place
) = 0;
12765 distribute_links (links
);
12770 if (tem
== BB_HEAD (bb
))
12774 /* We haven't found an insn for the death note and it
12775 is still a REG_DEAD note, but we have hit the beginning
12776 of the block. If the existing life info says the reg
12777 was dead, there's nothing left to do. Otherwise, we'll
12778 need to do a global life update after combine. */
12779 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12780 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12781 REGNO (XEXP (note
, 0))))
12782 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12785 /* If the register is set or already dead at PLACE, we needn't do
12786 anything with this note if it is still a REG_DEAD note.
12787 We can here if it is set at all, not if is it totally replace,
12788 which is what `dead_or_set_p' checks, so also check for it being
12791 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12793 unsigned int regno
= REGNO (XEXP (note
, 0));
12795 /* Similarly, if the instruction on which we want to place
12796 the note is a noop, we'll need do a global live update
12797 after we remove them in delete_noop_moves. */
12798 if (noop_move_p (place
))
12799 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12801 if (dead_or_set_p (place
, XEXP (note
, 0))
12802 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12804 /* Unless the register previously died in PLACE, clear
12805 reg_last_death. [I no longer understand why this is
12807 if (reg_last_death
[regno
] != place
)
12808 reg_last_death
[regno
] = 0;
12812 reg_last_death
[regno
] = place
;
12814 /* If this is a death note for a hard reg that is occupying
12815 multiple registers, ensure that we are still using all
12816 parts of the object. If we find a piece of the object
12817 that is unused, we must arrange for an appropriate REG_DEAD
12818 note to be added for it. However, we can't just emit a USE
12819 and tag the note to it, since the register might actually
12820 be dead; so we recourse, and the recursive call then finds
12821 the previous insn that used this register. */
12823 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12824 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12826 unsigned int endregno
12827 = regno
+ HARD_REGNO_NREGS (regno
,
12828 GET_MODE (XEXP (note
, 0)));
12832 for (i
= regno
; i
< endregno
; i
++)
12833 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12834 && ! find_regno_fusage (place
, USE
, i
))
12835 || dead_or_set_regno_p (place
, i
))
12840 /* Put only REG_DEAD notes for pieces that are
12841 not already dead or set. */
12843 for (i
= regno
; i
< endregno
;
12844 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12846 rtx piece
= regno_reg_rtx
[i
];
12847 basic_block bb
= this_basic_block
;
12849 if (! dead_or_set_p (place
, piece
)
12850 && ! reg_bitfield_target_p (piece
,
12854 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12856 distribute_notes (new_note
, place
, place
,
12859 else if (! refers_to_regno_p (i
, i
+ 1,
12860 PATTERN (place
), 0)
12861 && ! find_regno_fusage (place
, USE
, i
))
12862 for (tem
= PREV_INSN (place
); ;
12863 tem
= PREV_INSN (tem
))
12865 if (! INSN_P (tem
))
12867 if (tem
== BB_HEAD (bb
))
12869 SET_BIT (refresh_blocks
,
12870 this_basic_block
->index
);
12875 if (dead_or_set_p (tem
, piece
)
12876 || reg_bitfield_target_p (piece
,
12880 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12895 /* Any other notes should not be present at this point in the
12902 XEXP (note
, 1) = REG_NOTES (place
);
12903 REG_NOTES (place
) = note
;
12905 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12906 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12907 && GET_CODE (XEXP (note
, 0)) == REG
)
12908 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12912 if ((REG_NOTE_KIND (note
) == REG_DEAD
12913 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12914 && GET_CODE (XEXP (note
, 0)) == REG
)
12915 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12917 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12918 REG_NOTE_KIND (note
),
12920 REG_NOTES (place2
));
12925 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12926 I3, I2, and I1 to new locations. This is also called to add a link
12927 pointing at I3 when I3's destination is changed. */
12930 distribute_links (rtx links
)
12932 rtx link
, next_link
;
12934 for (link
= links
; link
; link
= next_link
)
12940 next_link
= XEXP (link
, 1);
12942 /* If the insn that this link points to is a NOTE or isn't a single
12943 set, ignore it. In the latter case, it isn't clear what we
12944 can do other than ignore the link, since we can't tell which
12945 register it was for. Such links wouldn't be used by combine
12948 It is not possible for the destination of the target of the link to
12949 have been changed by combine. The only potential of this is if we
12950 replace I3, I2, and I1 by I3 and I2. But in that case the
12951 destination of I2 also remains unchanged. */
12953 if (GET_CODE (XEXP (link
, 0)) == NOTE
12954 || (set
= single_set (XEXP (link
, 0))) == 0)
12957 reg
= SET_DEST (set
);
12958 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12959 || GET_CODE (reg
) == SIGN_EXTRACT
12960 || GET_CODE (reg
) == STRICT_LOW_PART
)
12961 reg
= XEXP (reg
, 0);
12963 /* A LOG_LINK is defined as being placed on the first insn that uses
12964 a register and points to the insn that sets the register. Start
12965 searching at the next insn after the target of the link and stop
12966 when we reach a set of the register or the end of the basic block.
12968 Note that this correctly handles the link that used to point from
12969 I3 to I2. Also note that not much searching is typically done here
12970 since most links don't point very far away. */
12972 for (insn
= NEXT_INSN (XEXP (link
, 0));
12973 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12974 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12975 insn
= NEXT_INSN (insn
))
12976 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12978 if (reg_referenced_p (reg
, PATTERN (insn
)))
12982 else if (GET_CODE (insn
) == CALL_INSN
12983 && find_reg_fusage (insn
, USE
, reg
))
12988 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12991 /* If we found a place to put the link, place it there unless there
12992 is already a link to the same insn as LINK at that point. */
12998 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12999 if (XEXP (link2
, 0) == XEXP (link
, 0))
13004 XEXP (link
, 1) = LOG_LINKS (place
);
13005 LOG_LINKS (place
) = link
;
13007 /* Set added_links_insn to the earliest insn we added a
13009 if (added_links_insn
== 0
13010 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
13011 added_links_insn
= place
;
13017 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13020 insn_cuid (rtx insn
)
13022 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13023 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13024 insn
= NEXT_INSN (insn
);
13026 if (INSN_UID (insn
) > max_uid_cuid
)
13029 return INSN_CUID (insn
);
13033 dump_combine_stats (FILE *file
)
13037 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13038 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13042 dump_combine_total_stats (FILE *file
)
13046 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13047 total_attempts
, total_merges
, total_extras
, total_successes
);