gcc/config/1750a/1750a.md

   1 ;;- Machine description for GNU compiler
   2 ;;- MIL-STD-1750A version.
   3 ;; Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
   4 ;; Contributed by O.M.Kellogg, DASA (oliver.kellogg@space.otn.dasa.de).
   5
   6 ;; This file is part of GNU CC.
   7
   8 ;; GNU CC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 1, or (at your option)
  11 ;; any later version.
  12
  13 ;; GNU CC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GNU CC; see the file COPYING.  If not, write to
  20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  21 ;; Boston, MA 02111-1307, USA.
  22
  23
  24 ;;- instruction definitions
  25
  26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
  27
  28 ;;- When naming insn's (operand 0 of define_insn) be careful about using
  29 ;;- names from other targets machine descriptions.
  30
  31 ;; MIL-STD-1750 specific remarks:
  32 ;;
  33 ;; 1) BITS_PER_UNIT = 16
  34 ;;
  35 ;; 2) GCC   to    MIL-STD-1750       data type mappings:
  36 ;;    QImode => single integer (16 bits or 1 reg).
  37 ;;    HImode => double integer (32 bits or 2 regs).
  38 ;;    HFmode => single precision float (32 bits or 2 regs).
  39 ;;    TQFmode => extended precision float (48 bits or 3 regs).
  40 ;;
  41 ;; 3) Immediate integer operands Constraints:
  42 ;;    'I'  1 .. 16
  43 ;;    'J' -1 ..-16
  44 ;;    'K'  0 .. 15
  45 ;;    'L'  0 .. 255
  46 ;;    'M' -32768 .. 32767
  47 ;;    'O' => 0  (for optimizations and GCC quirks)
  48 ;;
  49 ;; Further notes:
  50 ;;-  Assembly output ending in ".M" are macros in file M1750.INC
  51
  52
  53 ;; stackpush
  54 (define_insn ""
  55   [(set (match_operand:QI 0 "push_operand" "=<")
  56         (match_operand:QI 1 "general_operand" "r"))]
  57   ""
  58   "pshm r%1,r%1")
  59
  60 (define_insn ""
  61   [(set (match_operand:HI 0 "push_operand" "=<")
  62         (match_operand:HI 1 "general_operand" "r"))]
  63   ""
  64   "pshm r%1,r%d1")
  65
  66 (define_insn ""
  67   [(set (match_operand:HF 0 "push_operand" "=<")
  68         (match_operand:HF 1 "general_operand" "r"))]
  69   ""
  70   "pshm r%1,r%d1")
  71
  72 (define_insn ""
  73   [(set (match_operand:TQF 0 "push_operand" "=<")
  74         (match_operand:TQF 1 "general_operand" "r"))]
  75   ""
  76   "pshm r%1,r%t1")
  77
  78 ;; stackpop
  79 (define_insn ""
  80   [(set (match_operand:QI 0 "general_operand" "=r")
  81         (match_operand:QI 1 "push_operand" ">"))]
  82   ""
  83   "popm r%1,r%1")
  84
  85 (define_insn ""
  86   [(set (match_operand:HI 0 "general_operand" "=r")
  87         (match_operand:HI 1 "push_operand" ">"))]
  88   ""
  89   "popm r%1,r%d1")
  90
  91 (define_insn ""
  92   [(set (match_operand:HF 0 "general_operand" "=r")
  93         (match_operand:HF 1 "push_operand" ">"))]
  94   ""
  95   "popm r%1,r%d1")
  96
  97 (define_insn ""
  98   [(set (match_operand:TQF 0 "general_operand" "=r")
  99         (match_operand:TQF 1 "push_operand" ">"))]
 100   ""
 101   "popm r%1,r%t1")
 102
 103
 104 ;; Test operations.
 105
 106 (define_insn "tstqi"
 107   [(set (cc0)
 108         (match_operand:QI 0 "register_operand" "r"))]
 109   ""
 110   "lr r%0,r%0   ; from tstqi")
 111
 112 (define_insn "tsthi"
 113   [(set (cc0)
 114         (match_operand:HI 0 "register_operand" "r"))]
 115   ""
 116   "dlr r%0,r%0   ; from tsthi")
 117
 118 ; With 1750A floats, testing the most significant word suffices.
 119
 120 (define_insn "tsthf"
 121   [(set (cc0)
 122         (match_operand:HF 0 "register_operand" "r"))]
 123   ""
 124   "lr r%0,r%0   ; tsthf")
 125
 126 (define_insn "tsttqf"
 127   [(set (cc0)
 128         (match_operand:TQF 0 "register_operand" "r"))]
 129   ""
 130   "lr r%0,r%0   ; tsttqf")
 131
 132
 133 ;; block move.
 134
 135 (define_insn "movstrqi"
 136   [(set (match_operand:BLK 0 "mov_memory_operand" "m")
 137         (match_operand:BLK 1 "mov_memory_operand" "m"))
 138    (use (match_operand:QI 2 "general_operand" "r"))
 139    (match_operand 3 "" "")
 140    (clobber (match_dup 0))
 141    (clobber (match_dup 1))
 142    (clobber (match_dup 2))]
 143   ""
 144   "*
 145    {
 146      rtx regops[3];
 147
 148      regops[0] = XEXP (operands[0], 0);
 149      regops[1] = XEXP (operands[1], 0);
 150      regops[2] = operands[2];
 151
 152      return movcnt_regno_adjust (regops);
 153    } ")
 154
 155
 156 ;; compare instructions.
 157
 158 (define_insn "cmpqi"
 159   [(set (cc0)
 160         (compare (match_operand:QI 0 "register_operand" "r,r,r,r,r")
 161                  (match_operand:QI 1 "general_operand"  "I,J,i,r,m")))]
 162   ""
 163   "*
 164    {
 165      if (next_cc_user_is_unsigned (insn))
 166        switch (which_alternative)
 167          {
 168          case 0:
 169          case 1:
 170          case 2:
 171            return \"ucim.m %0,%1\";
 172          case 3:
 173            return \"ucr.m %0,%1\";
 174          case 4:
 175            return \"uc.m %0,%1\";
 176          }
 177      else
 178        switch (which_alternative)
 179          {
 180          case 0:
 181            return \"cisp r%0,%1\";
 182          case 1:
 183            return \"cisn r%0,%J1\";
 184          case 2:
 185            return \"cim  r%0,%1\";
 186          case 3:
 187            return \"cr   r%0,r%1\";
 188          case 4:
 189            return \"c    r%0,%1\";
 190          }
 191    } ")
 192
 193 (define_insn "cmphi"
 194   [(set (cc0)
 195         (compare (match_operand:HI 0 "general_operand" "r,r")
 196                  (match_operand:HI 1 "general_operand" "r,m")))]
 197   ""
 198   "*
 199    {
 200      if (next_cc_user_is_unsigned (insn))
 201        {
 202          if (which_alternative == 0)
 203            return \"ducr.m %0,%1\";
 204          return \"duc.m %0,%1\";
 205        }
 206      else
 207        {
 208          if (which_alternative == 0)
 209            return \"dcr r%0,r%1\";
 210          return \"dc  r%0,%1\";
 211        }
 212    } ")
 213
 214 (define_insn "cmphf"
 215  [(set (cc0)
 216        (compare (match_operand:HF 0 "general_operand" "r,r")
 217                 (match_operand:HF 1 "general_operand" "r,m")))]
 218  ""
 219  "@
 220    fcr r%0,r%1
 221    fc  r%0,%1 ")
 222
 223 (define_insn "cmptqf"
 224   [(set (cc0)
 225         (compare (match_operand:TQF 0 "general_operand" "r,r")
 226                  (match_operand:TQF 1 "general_operand" "r,m")))]
 227   ""
 228   "@
 229     efcr r%0,r%1
 230     efc  r%0,%1 ")
 231
 232
 233 ;; truncation instructions
 234 ;;- 1750: any needed?
 235
 236 (define_insn "trunchiqi2"
 237   [(set (match_operand:QI 0 "register_operand" "=r")
 238         (truncate:QI (match_operand:HI 1 "register_operand" "r")))]
 239   ""
 240   "lr  r%0,r%d1")
 241
 242
 243 ;; zero extension instructions: not defined, GCC can synthesize
 244
 245 ;; sign extension instructions
 246
 247 (define_insn "extendqihi2"
 248   [(set (match_operand:HI 0 "register_operand" "=r,r")
 249         (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m")) )]
 250   ""
 251   "*
 252     if (which_alternative == 0)
 253       {
 254         if (REGNO (operands [0]) != REGNO (operands [1]))
 255           output_asm_insn (\"lr r%0,r%1\", operands);
 256       }
 257     else
 258       output_asm_insn (\"l  r%0,%1\", operands);
 259     return \"dsra r%0,16  ;extendqihi2\";
 260   ")
 261
 262
 263 ;; Conversions between float and double.
 264
 265 ; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero
 266 (define_insn "extendhftqf2"
 267   [(set (match_operand:TQF 0 "register_operand" "=r,r")
 268         (float_extend:TQF (match_operand:HF 1 "general_operand" "r,m")))]
 269   ""
 270   "*
 271     output_asm_insn(\"xorr r%t0,r%t0   ;extendhftqf2\", operands);
 272     if (which_alternative == 0)
 273       {
 274         if (REGNO (operands[1]) != REGNO (operands[0]))
 275           return \"dlr r%0,r%1\";
 276         else
 277           return \";\";
 278       }
 279     else
 280       return \"dl  r%0,%1\";
 281    ")
 282
 283 ; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
 284 (define_insn "trunctqfhf2"
 285   [(set (match_operand:HF 0 "register_operand" "=r,r")
 286         (float_truncate:HF
 287           (match_operand:TQF 1 "general_operand" "r,m")))]
 288   ""
 289   "@
 290      dlr r%0,r%1  ;trunctqfhf2
 291      dl  r%0,%1   ;trunctqfhf2 ")
 292
 293
 294 ;; Conversion between fixed point and floating point.
 295
 296 (define_insn "floatqihf2"
 297   [(set           (match_operand:HF 0 "register_operand" "=r")
 298         (float:HF (match_operand:QI 1 "register_operand" "r")))]
 299   ""
 300   "flt r%0,r%1")
 301
 302 (define_insn "floathitqf2"
 303   [(set           (match_operand:TQF 0 "register_operand" "=r")
 304         (float:TQF (match_operand:HI 1 "register_operand" "r")))]
 305   ""
 306   "eflt r%0,r%1")
 307
 308
 309 ;; Convert floats to ints
 310
 311 (define_insn "fix_trunchfqi2"
 312   [(set                 (match_operand:QI 0 "register_operand" "=r")
 313         (fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
 314   ""
 315   "fix r%0,r%1")
 316
 317 (define_insn "fix_trunctqfhi2"
 318   [(set                 (match_operand:HI 0 "register_operand" "=r")
 319         (fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))]
 320   ""
 321   "efix r%0,r%1")
 322
 323
 324 ;; Move instructions
 325
 326 ;; We can't deal with normal byte-size characters, only with WIDE characters!
 327 ;; This may appear as a serious restriction, but it also opens the doors
 328 ;; for ISO 10646  :-)
 329
 330 ;; 16-bit moves
 331
 332 ; memory indirect to reg
 333 (define_insn ""
 334   [(set (match_operand:QI 0 "register_operand" "=r")
 335         (mem:QI (match_operand 1 "memory_operand"  "m")))]
 336   ""
 337   "li   r%0,%1")
 338
 339 ; reg/const to memory indirect
 340 (define_insn ""
 341   [(set (mem:QI (match_operand 0 "memory_operand" "=m,m"))
 342         (match_operand:QI 1 "nonmemory_operand"  "r,K"))]
 343   ""
 344   "@
 345      sti  r%1,%0
 346      stci %1,%0")
 347
 348 ; general case
 349 (define_insn "movqi"
 350   [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,m,m")
 351         (match_operand:QI 1 "general_operand"  "O,I,J,i,r,m,r,K"))]
 352   ""
 353   "@
 354      xorr r%0,r%0
 355      lisp r%0,%1
 356      lisn r%0,%J1
 357      lim  r%0,%1
 358      lr   r%0,r%1
 359      l    r%0,%1
 360      st   r%1,%0
 361      stc  %1,%0   ")
 362
 363 ;; 32-bit moves
 364
 365 ; memory indirect to reg
 366 (define_insn ""
 367   [(set (match_operand:HI 0 "register_operand" "=r")
 368         (mem:HI (match_operand 1 "memory_operand"  "m")))]
 369   ""
 370   "dli  r%0,%1")
 371
 372 ; reg to memory indirect
 373 (define_insn ""
 374   [(set (mem:HI (match_operand 0 "memory_operand" "=m"))
 375         (match_operand:HI 1 "register_operand"  "r"))]
 376   ""
 377   "dsti r%1,%0")
 378
 379 ; general case
 380 (define_insn ""
 381   [(set (match_operand:HI 0 "general_operand" "=r,r,r,r,r,m,m")
 382         (match_operand:HI 1 "general_operand"  "O,I,J,r,m,r,K"))]
 383   ""
 384   "@
 385     xorr r%0,r%0\;xorr r%d0,r%d0
 386     xorr r%0,r%0\;lisp r%d0,%1
 387     lisn r%0,1  \;lisn r%d0,%J1
 388     dlr  r%0,r%1
 389     dl   r%0,%1
 390     dst  r%1,%0
 391     stc  0,%0   \;stc  %1,%A0 ")
 392
 393 (define_expand "movhi"
 394   [(set (match_operand:HI 0 "general_operand" "=g")
 395         (match_operand:HI 1 "general_operand"  "g"))]
 396   ""
 397   "
 398    {
 399      rtx op1 = operands[1];
 400      if (GET_CODE (operands[0]) == MEM)
 401        {
 402          if (GET_CODE (op1) == MEM
 403              || (GET_CODE (op1) == CONST_INT
 404                  && (INTVAL (op1) < 0 || INTVAL (op1) > 15)))
 405            operands[1] = force_reg (HImode, operands[1]);
 406        }
 407      else if (GET_CODE (op1) == CONST_INT
 408               && (INTVAL (op1) < -16 || INTVAL (op1) > 16))
 409        operands[1] = force_const_mem (HImode, operands[1]);
 410    }")
 411
 412
 413 ;; Single-Float moves
 414
 415 (define_insn ""
 416   [(set (match_operand:HF 0 "general_operand" "=r,r,m,m")
 417         (match_operand:HF 1 "general_operand"  "r,m,r,G"))]
 418   ""
 419   "@
 420     dlr  r%0,r%1
 421     dl   r%0,%1
 422     dst  r%1,%0
 423     stc  0,%0   \;stc 0,%A0 ")
 424
 425 (define_expand "movhf"
 426   [(set (match_operand:HF 0 "general_operand" "")
 427         (match_operand:HF 1 "general_operand" ""))]
 428   ""
 429   "
 430    {
 431      enum rtx_code op1code = GET_CODE (operands[1]);
 432      if (GET_CODE (operands[0]) == MEM)
 433        {
 434          if (op1code == MEM || (op1code == CONST_DOUBLE
 435              && !rtx_equal_p (operands[1], CONST0_RTX (HFmode))))
 436            operands[1] = force_reg (HFmode, operands[1]);
 437        }
 438      else if (op1code == CONST_DOUBLE)
 439        operands[1] = force_const_mem (HFmode, operands[1]);
 440    }")
 441
 442
 443 ;; Longfloat moves
 444
 445 (define_insn ""
 446   [(set (match_operand:TQF 0 "general_operand" "=r,r,m")
 447         (match_operand:TQF 1 "general_operand"  "r,m,r"))]
 448   ""
 449   "@
 450     eflr.m %0,%1
 451     efl  r%0,%1
 452     efst r%1,%0 ")
 453
 454 (define_expand "movtqf"
 455   [(set (match_operand:TQF 0 "general_operand" "")
 456         (match_operand:TQF 1 "general_operand" ""))]
 457   ""
 458   "
 459    {
 460      enum rtx_code op1code = GET_CODE (operands[1]);
 461      if (GET_CODE (operands[0]) == MEM)
 462        {
 463          if (op1code == MEM || op1code == CONST_DOUBLE)
 464            operands[1] = force_reg (TQFmode, operands[1]);
 465        }
 466      else if (op1code == CONST_DOUBLE)
 467        operands[1] = force_const_mem (TQFmode, operands[1]);
 468    }")
 469
 470
 471 ;; add instructions
 472
 473 ;; single integer
 474
 475 (define_insn "addqi3"
 476   [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m")
 477         (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0")
 478                  (match_operand:QI 2 "general_operand"  "I,J,i,r,m,I,J")))]
 479   ""
 480   "*
 481     switch (which_alternative)
 482       {
 483         case 0:
 484           return \"aisp r%0,%2\";
 485         case 1:
 486           return \"sisp r%0,%J2\";
 487         case 2:
 488           if (INTVAL(operands[2]) < 0)
 489             return \"sim r%0,%J2\";
 490           else
 491             return \"aim r%0,%2\";
 492         case 3:
 493           return \"ar r%0,r%2\";
 494         case 4:
 495           return \"a r%0,%2\";
 496         case 5:
 497           return \"incm %2,%0\";
 498         case 6:
 499           return \"decm %J2,%0\";
 500       } ")
 501
 502 ;; double integer
 503 (define_insn "addhi3"
 504   [(set (match_operand:HI 0 "register_operand" "=r,r")
 505         (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
 506                  (match_operand:HI 2 "general_operand" "r,m")))]
 507   ""
 508   "@
 509     dar r%0,r%2
 510     da  r%0,%2 ")
 511
 512 (define_insn "addhf3"
 513   [(set (match_operand:HF 0 "register_operand" "=r,r")
 514         (plus:HF (match_operand:HF 1 "register_operand" "%0,0")
 515                  (match_operand:HF 2 "general_operand" "r,m")))]
 516   ""
 517   "@
 518     far r%0,r%2
 519     fa  r%0,%2 ")
 520
 521 (define_insn "addtqf3"
 522   [(set (match_operand:TQF 0 "register_operand" "=r,r")
 523         (plus:TQF (match_operand:TQF 1 "register_operand" "%0,0")
 524                  (match_operand:TQF 2 "general_operand" "r,m")))]
 525   ""
 526   "@
 527     efar r%0,r%2
 528     efa  r%0,%2 ")
 529
 530
 531 ;; subtract instructions
 532
 533 ;; single integer
 534 (define_insn "subqi3"
 535   [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m")
 536         (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0")
 537                   (match_operand:QI 2 "general_operand"  "I,i,r,m,I")))]
 538   ""
 539   "@
 540     sisp r%0,%2
 541     sim  r%0,%2
 542     sr   r%0,r%2
 543     s    r%0,%2
 544     decm %2,%0 ")
 545
 546 ;; double integer
 547 (define_insn "subhi3"
 548   [(set (match_operand:HI 0 "register_operand" "=r,r")
 549         (minus:HI (match_operand:HI 1 "register_operand" "0,0")
 550                   (match_operand:HI 2 "general_operand" "r,m")))]
 551   ""
 552   "@
 553     dsr r%0,r%2
 554     ds  r%0,%2 ")
 555
 556 (define_insn "subhf3"
 557   [(set (match_operand:HF 0 "register_operand" "=r,r")
 558         (minus:HF (match_operand:HF 1 "register_operand" "0,0")
 559                   (match_operand:HF 2 "general_operand" "r,m")))]
 560   ""
 561   "@
 562     fsr r%0,r%2
 563     fs  r%0,%2 ")
 564
 565 (define_insn "subtqf3"
 566   [(set (match_operand:TQF 0 "register_operand" "=r,r")
 567         (minus:TQF (match_operand:TQF 1 "register_operand" "0,0")
 568                   (match_operand:TQF 2 "general_operand" "r,m")))]
 569   ""
 570   "@
 571     efsr r%0,r%2
 572     efs  r%0,%2 ")
 573
 574
 575 ;; multiply instructions
 576
 577 (define_insn "mulqi3"
 578   [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
 579         (mult:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
 580                  (match_operand:QI 2 "general_operand"  "I,J,M,r,m")))]
 581   ""
 582   "@
 583      misp r%0,%2
 584      misn r%0,%J2
 585      msim r%0,%2
 586      msr  r%0,r%2
 587      ms   r%0,%2  ")
 588
 589
 590 ; 32-bit product
 591 (define_insn "mulqihi3"
 592   [(set (match_operand:HI 0 "register_operand" "=r,r,r")
 593     (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%r,r,r"))
 594              (sign_extend:HI (match_operand:QI 2 "general_operand" "r,m,i"))))]
 595   ""
 596   "*
 597     if (REGNO (operands[1]) != REGNO (operands[0]))
 598       output_asm_insn (\"lr r%0,r%1\", operands);
 599
 600     switch (which_alternative)
 601       {
 602       case 0:
 603         return \"mr  r%0,r%2\";
 604       case 1:
 605         return \"m   r%0,%2\";
 606       case 2:
 607         return \"mim r%0,%2\";
 608       }
 609   ")
 610
 611
 612 (define_insn "mulhi3"
 613   [(set (match_operand:HI 0 "register_operand" "=r,r")
 614         (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
 615                  (match_operand:HI 2 "general_operand" "r,m")))]
 616   ""
 617   "@
 618     dmr r%0,r%2
 619     dm  r%0,%2 ")
 620
 621 ; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)
 622
 623 (define_insn "mulhf3"
 624   [(set (match_operand:HF 0 "register_operand" "=r,r")
 625         (mult:HF (match_operand:HF 1 "register_operand" "%0,0")
 626                  (match_operand:HF 2 "general_operand" "r,m")))]
 627   ""
 628   "@
 629     fmr r%0,r%2
 630     fm  r%0,%2 ")
 631
 632 (define_insn "multqf3"
 633   [(set (match_operand:TQF 0 "register_operand" "=r,r")
 634         (mult:TQF (match_operand:TQF 1 "register_operand" "%0,0")
 635                  (match_operand:TQF 2 "general_operand" "r,m")))]
 636   ""
 637   "@
 638     efmr r%0,r%2
 639     efm  r%0,%2 ")
 640
 641
 642 ;; divide instructions
 643 ;; The 1750 16bit integer division instructions deliver a 16-bit
 644 ;; quotient and a 16-bit remainder, where the remainder is in the next higher
 645 ;; register number above the quotient. For now, we haven't found a way
 646 ;; to give the reload pass knowledge of this property. So we make do with
 647 ;; whatever registers the allocator wants, and willy-nilly output a pair of
 648 ;; register-copy ops when needed. (See mod_regno_adjust() in file aux-output.c)
 649 ;; A comment in the description of `divmodM4' suggests that one leave the divM3
 650 ;; undefined when there is a divmodM4 available.
 651
 652 (define_insn "divmodqi4"
 653   [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
 654         (div:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
 655                 (match_operand:QI 2 "general_operand"  "I,J,M,r,m")))
 656    (set (match_operand:QI 3 "register_operand" "=r,r,r,r,r")
 657         (mod:QI (match_dup 1) (match_dup 2)))]
 658   ""
 659   "*
 660    {
 661      char *istr;
 662      switch(which_alternative)
 663        {
 664        case 0:
 665          istr = \"disp\";
 666          break;
 667        case 1:
 668          {
 669            rtx new_opnds[4];
 670            new_opnds[0] = operands[0];
 671            new_opnds[1] = operands[1];
 672            new_opnds[2] = GEN_INT (-INTVAL(operands[2]));
 673            new_opnds[3] = operands[3];
 674            istr = \"disn\";
 675            return mod_regno_adjust (istr, new_opnds);
 676          }
 677          break;
 678        case 2:
 679          istr = \"dvim\";
 680          break;
 681        case 3:
 682          istr = \"dvr \";
 683          break;
 684        case 4:
 685          istr = \"dv  \";
 686          break;
 687       }
 688       return mod_regno_adjust (istr, operands);
 689      }")
 690
 691 ;; Division for other types is straightforward.
 692
 693 (define_insn "divhi3"
 694   [(set (match_operand:HI 0 "register_operand" "=r,r")
 695         (div:HI (match_operand:HI 1 "register_operand" "0,0")
 696                 (match_operand:HI 2 "general_operand" "r,m")))]
 697   ""
 698   "@
 699     ddr r%0,r%2
 700     dd  r%0,%2 ")
 701
 702 (define_insn "divhf3"
 703   [(set (match_operand:HF 0 "register_operand" "=r,r")
 704         (div:HF (match_operand:HF 1 "register_operand" "0,0")
 705                 (match_operand:HF 2 "general_operand" "r,m")))]
 706   ""
 707   "@
 708     fdr r%0,r%2
 709     fd  r%0,%2 ")
 710
 711 (define_insn "divtqf3"
 712   [(set (match_operand:TQF 0 "register_operand" "=r,r")
 713         (div:TQF (match_operand:TQF 1 "register_operand" "0,0")
 714                 (match_operand:TQF 2 "general_operand" "r,m")))]
 715   ""
 716   "@
 717     efdr r%0,r%2
 718     efd  r%0,%2 ")
 719
 720
 721 ;; Other arithmetic instructions:
 722
 723 ;; Absolute value
 724
 725 (define_insn "absqi2"
 726   [(set (match_operand:QI 0 "register_operand" "=r")
 727         (abs:QI (match_operand:QI 1 "register_operand" "r")))]
 728   ""
 729   "abs r%0,r%1")
 730
 731 (define_insn "abshi2"
 732   [(set (match_operand:HI 0 "register_operand" "=r")
 733         (abs:HI (match_operand:HI 1 "register_operand" "r")))]
 734   ""
 735   "dabs r%0,r%1")
 736
 737 (define_insn "abshf2"
 738   [(set (match_operand:HF 0 "register_operand" "=r")
 739         (abs:HF (match_operand:HF 1 "register_operand" "r")))]
 740   ""
 741   "fabs r%0,r%1")
 742
 743
 744 ;; Negation
 745
 746 (define_insn "negqi2"
 747   [(set (match_operand:QI 0 "register_operand" "=r")
 748         (neg:QI (match_operand:QI 1 "register_operand" "r")))]
 749   ""
 750   "neg r%0,r%1")
 751
 752 (define_insn "neghi2"
 753   [(set (match_operand:HI 0 "register_operand" "=r")
 754         (neg:HI (match_operand:HI 1 "register_operand" "r")))]
 755   ""
 756   "dneg r%0,r%1")
 757
 758 (define_insn "neghf2"
 759   [(set (match_operand:HF 0 "register_operand" "=r")
 760         (neg:HF (match_operand:HF 1 "register_operand" "r")))]
 761   ""
 762   "fneg r%0,r%1")
 763
 764 ; The 1750A does not have an extended float negate instruction, so simulate.
 765 (define_expand "negtqf2"
 766   [(set (match_operand:TQF 0 "register_operand" "=&r")
 767         (neg:TQF (match_operand:TQF 1 "register_operand" "r")))]
 768   ""
 769   "
 770    emit_insn(gen_rtx(SET,VOIDmode,operands[0],CONST0_RTX(TQFmode)));
 771    emit_insn(gen_rtx(SET,VOIDmode,operands[0],
 772              gen_rtx(MINUS,TQFmode,operands[0],operands[1])));
 773    DONE;
 774   ")
 775
 776
 777 ;; bit-logical instructions
 778
 779 ;; Set Bit
 780 (define_insn ""
 781   [(set (match_operand:QI 0 "general_operand" "=r,m")
 782         (ior:QI  (match_operand:QI 1 "general_operand" "0,0")
 783                  (match_operand:QI 2 "const_int_operand" "i,i")))]
 784   "one_bit_set_p (INTVAL (operands [2]))"
 785   "@
 786     sbr    %b2,r%0
 787     sb     %b2,%0")
 788
 789 ;; Reset Bit
 790 (define_insn ""
 791   [(set (match_operand:QI 0 "general_operand" "=r,m")
 792         (and:QI  (match_operand:QI 1 "general_operand" "0,0")
 793                  (match_operand:QI 2 "const_int_operand" "i,i")))]
 794   "one_bit_set_p ((~INTVAL (operands [2])) & 0xffff)"
 795   "@
 796     rbr    %B2,r%0
 797     rb     %B2,%0")
 798
 799 ;; Set Variable Bit
 800 (define_insn ""
 801   [(set (match_operand:QI 0 "register_operand" "=r")
 802         (ior:QI  (match_operand:QI 1 "register_operand" "0")
 803                  (lshiftrt:QI (const_int 0x8000)
 804                       (match_operand:QI 2 "register_operand" "r"))))]
 805   ""
 806   "svbr   r%2,%r0")
 807
 808 ;; Reset Variable Bit
 809 (define_insn ""
 810   [(set (match_operand:QI 0 "general_operand" "=r")
 811         (and:QI  (match_operand:QI 1 "general_operand" "0")
 812             (not:QI (lshiftrt:QI (const_int 0x8000)
 813                         (match_operand:QI 2 "register_operand" "r")))))]
 814   ""
 815   "rvbr   r%2,%r0")
 816
 817
 818 ;; AND
 819
 820 (define_insn "andqi3"
 821   [(set (match_operand:QI 0 "general_operand" "=r,r,r")
 822         (and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
 823                 (match_operand:QI 2 "general_operand" "M,r,m")))]
 824   ""
 825   "@
 826     andm r%0,%2
 827     andr r%0,r%2
 828     and  r%0,%2 ")
 829
 830 ; This sets incorrect condition codes. See notice_update_cc()
 831 (define_insn "andhi3"
 832   [(set (match_operand:HI 0 "register_operand" "=r")
 833         (and:HI (match_operand:HI 1 "register_operand" "%0")
 834                 (match_operand:HI 2 "register_operand" "r")))]
 835   ""
 836   "danr.m %0,%2")
 837
 838 ;; OR
 839
 840 (define_insn "iorqi3"
 841   [(set (match_operand:QI 0 "general_operand" "=r,r,r")
 842         (ior:QI  (match_operand:QI 1 "general_operand" "%0,0,0")
 843                  (match_operand:QI 2 "general_operand" "M,r,m")))]
 844   ""
 845   "@
 846     orim r%0,%2
 847     orr  r%0,r%2
 848     or   r%0,%2 ")
 849
 850 ; This sets incorrect condition codes. See notice_update_cc()
 851 (define_insn "iorhi3"
 852   [(set (match_operand:HI 0 "register_operand" "=r")
 853         (ior:HI (match_operand:HI 1 "register_operand" "%0")
 854                 (match_operand:HI 2 "register_operand" "r")))]
 855   ""
 856   "dorr.m %0,%2")
 857
 858 ;; XOR
 859
 860 (define_insn "xorqi3"
 861   [(set (match_operand:QI 0 "register_operand" "=r,r,r")
 862         (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0")
 863                 (match_operand:QI 2 "general_operand"  "M,r,m")))]
 864   ""
 865   "@
 866     xorm r%0,%2
 867     xorr r%0,r%2
 868     xor  r%0,%2 ")
 869
 870 ; This sets incorrect condition codes. See notice_update_cc()
 871 (define_insn "xorhi3"
 872   [(set (match_operand:HI 0 "register_operand" "=r")
 873         (xor:HI (match_operand:HI 1 "register_operand" "%0")
 874                 (match_operand:HI 2 "register_operand" "r")))]
 875   ""
 876   "dxrr.m %0,%2")
 877
 878 ;; NAND
 879
 880 (define_insn ""
 881   [(set (match_operand:QI 0 "register_operand" "=r,r,r")
 882         (ior:QI (not:QI (match_operand:QI 1 "register_operand" "%0,0,0"))
 883                 (not:QI (match_operand:QI 2 "general_operand" "M,r,m"))))]
 884   ""
 885   "@
 886     nim r%0,%2
 887     nr  r%0,r%2
 888     n   r%0,%2 ")
 889
 890 ; This sets incorrect condition codes. See notice_update_cc()
 891 (define_insn ""
 892   [(set (match_operand:HI 0 "register_operand" "=r")
 893         (ior:HI (not:HI (match_operand:HI 1 "register_operand" "%0"))
 894                 (not:HI (match_operand:HI 2 "register_operand" "r"))))]
 895   ""
 896   "dnr.m %0,%2")
 897
 898 ;; NOT
 899
 900 (define_insn "one_cmplqi2"
 901   [(set (match_operand:QI 0 "register_operand" "=r")
 902         (not:QI (match_operand:QI 1 "register_operand" "0")))]
 903   ""
 904   "nr r%0,r%0")
 905
 906 ; This sets incorrect condition codes. See notice_update_cc()
 907 (define_insn "one_cmplhi2"
 908   [(set (match_operand:HI 0 "register_operand" "=r")
 909         (not:HI (match_operand:HI 1 "register_operand" "0")))]
 910   ""
 911   "dnr.m %0,%0")
 912
 913
 914 ;; Shift instructions
 915
 916 ; (What to the 1750 is logical-shift-left, GCC likes to call "arithmetic")
 917 (define_insn "ashlqi3"
 918   [(set (match_operand:QI 0 "register_operand" "=r,r")
 919         (ashift:QI (match_operand:QI 1 "register_operand" "0,0")
 920                    (match_operand:QI 2 "nonmemory_operand" "I,r")))]
 921   ""
 922   "@
 923     sll r%0,%2
 924     slr r%0,r%2 ")
 925
 926 (define_insn "ashlhi3"
 927   [(set (match_operand:HI 0 "register_operand" "=r,r")
 928         (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
 929                    (match_operand:QI 2 "nonmemory_operand" "L,r")))]
 930   ""                        ; the 'L' constraint is a slight imprecise...
 931   "*
 932     if (which_alternative == 1)
 933       return \"dslr r%0,r%2\";
 934     else if (INTVAL(operands[2]) <= 16)
 935       return \"dsll r%0,%2\";
 936     else
 937       {
 938         output_asm_insn (\"dsll r%0,16  ; ashlhi3 shiftcnt > 16\", operands);
 939         return \"sll r%0,%w2\";
 940       }
 941   ")
 942
 943
 944 ;; Right shift by a variable shiftcount works by negating the shift count,
 945 ;; then emitting a right shift with the shift count negated.  This means
 946 ;; that all actual shift counts in the RTL will be positive.  This
 947 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
 948 ;; which isn't valid.
 949 (define_expand "lshrqi3"
 950   [(set (match_operand:QI 0 "register_operand" "=r")
 951         (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
 952                      (match_operand:QI 2 "nonmemory_operand" "g")))]
 953   ""
 954   "
 955 {
 956   if (GET_CODE (operands[2]) != CONST_INT)
 957     operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
 958 }")
 959
 960 (define_insn ""
 961   [(set (match_operand:QI 0 "register_operand" "=r")
 962         (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
 963                      (match_operand:QI 2 "immediate_operand" "I")))]
 964   ""
 965   "srl r%0,%2")
 966
 967 (define_insn ""
 968   [(set (match_operand:QI 0 "register_operand" "=r")
 969         (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
 970                      (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
 971   ""
 972   "slr r%0,r%2 ")
 973
 974 ;; Same thing for HImode.
 975
 976 (define_expand "lshrhi3"
 977   [(set (match_operand:HI 0 "register_operand" "=r")
 978         (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
 979                      (match_operand:QI 2 "nonmemory_operand" "g")))]
 980   ""
 981   "
 982   {
 983     if (GET_CODE (operands[2]) != CONST_INT)
 984       operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
 985   }")
 986
 987 (define_insn ""
 988   [(set (match_operand:HI 0 "register_operand" "=r")
 989         (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
 990                      (match_operand:QI 2 "immediate_operand" "L")))]
 991   ""
 992   "*
 993     if (INTVAL (operands[2]) <= 16)
 994       return \"dsrl r%0,%2\";
 995     output_asm_insn (\"dsrl r%0,16  ; lshrhi3 shiftcount > 16\", operands);
 996     return \"srl  r%d0,%w2\";
 997   ")
 998
 999 (define_insn ""
1000   [(set (match_operand:HI 0 "register_operand" "=r")
1001         (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
1002                      (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
1003   ""
1004   "dslr r%0,r%2 ")
1005
1006 ;; Same applies for arithmetic shift right.
1007 (define_expand "ashrqi3"
1008   [(set (match_operand:QI 0 "register_operand" "=r")
1009         (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
1010                      (match_operand:QI 2 "nonmemory_operand" "g")))]
1011   ""
1012   "
1013   {
1014     if (GET_CODE (operands[2]) != CONST_INT)
1015       operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
1016   }")
1017
1018 (define_insn ""
1019   [(set (match_operand:QI 0 "register_operand" "=r")
1020         (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
1021                      (match_operand:QI 2 "immediate_operand" "I")))]
1022   ""
1023   "sra r%0,%2")
1024
1025 (define_insn ""
1026   [(set (match_operand:QI 0 "register_operand" "=r")
1027         (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
1028                      (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
1029   ""
1030   "sar r%0,r%2 ")
1031
1032 ;; HImode arithmetic shift right.
1033 (define_expand "ashrhi3"
1034   [(set (match_operand:HI 0 "register_operand" "=r")
1035         (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
1036                      (match_operand:QI 2 "nonmemory_operand" "g")))]
1037   ""
1038   "
1039   {
1040     if (GET_CODE (operands[2]) != CONST_INT)
1041       operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
1042   }")
1043
1044 (define_insn ""
1045   [(set (match_operand:HI 0 "register_operand" "=r")
1046         (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
1047                      (match_operand:QI 2 "immediate_operand" "L")))]
1048   ""
1049   "*
1050     if (INTVAL (operands[2]) <= 16)
1051       return \"dsra r%0,%2\";
1052     output_asm_insn (\"dsra r%0,16  ; ashrhi3 shiftcount > 16\", operands);
1053     return \"sra  r%d0,%w2\";
1054   ")
1055
1056 (define_insn ""
1057   [(set (match_operand:HI 0 "register_operand" "=r")
1058         (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
1059                      (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
1060   ""
1061   "dsar r%0,r%2 ")
1062
1063
1064 ;; rotate instructions
1065
1066 (define_insn "rotlqi3"
1067   [(set (match_operand:QI 0 "register_operand" "=r,r")
1068         (rotate:QI (match_operand:QI 1 "register_operand" "0,0")
1069                    (match_operand:QI 2 "nonmemory_operand" "I,r")))]
1070   ""
1071   "@
1072     slc r%0,%2
1073     scr r%0,r%2 ")
1074
1075 (define_insn "rotlhi3"
1076   [(set (match_operand:HI 0 "register_operand" "=r,r")
1077         (rotate:HI (match_operand:HI 1 "register_operand" "0,0")
1078                    (match_operand:QI 2 "nonmemory_operand" "I,r")))]
1079   ""
1080   "@
1081     dslc r%0,%2
1082     dscr r%0,r%2 ")
1083
1084 (define_insn "rotrqi3"
1085   [(set (match_operand:QI 0 "register_operand" "=r")
1086         (rotatert:QI (match_operand:QI 1 "register_operand" "0")
1087                      (match_operand:QI 2 "register_operand" "r")))]
1088   ""
1089   "neg r%2,r%2\;scr r%0,r%2 ")
1090
1091 (define_insn "rotrhi3"
1092   [(set (match_operand:HI 0 "register_operand" "=r")
1093         (rotatert:HI (match_operand:HI 1 "register_operand" "0")
1094                      (match_operand:QI 2 "nonmemory_operand" "r")))]
1095   ""
1096   "neg  r%2,r%2\;dscr r%0,r%2 ")
1097
1098
1099
1100 ;; Special cases of bit-field insns which we should
1101 ;; recognize in preference to the general case.
1102 ;; These handle aligned 8-bit and 16-bit fields,
1103 ;; which can usually be done with move instructions.
1104 ;    1750: t.b.d.
1105 ;********************
1106
1107 ;; Bit field instructions, general cases.
1108 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
1109 ;; so that its address is reloaded.
1110
1111 ;; (define_insn "extv" ...
1112
1113 ;; (define_insn "extzv" ...
1114
1115 ;; (define_insn "insv" ...
1116
1117 ;; Now recognize bit field insns that operate on registers
1118 ;; (or at least were intended to do so).
1119 ;[unnamed only]
1120
1121 ;; Special patterns for optimizing bit-field instructions.
1122 ;**************************************
1123
1124 ; cc status test ops n.a. on 1750 ......... e.g. "sleu" on 68k:
1125 ;  [(set (match_operand:QI 0 "general_operand" "=d")
1126 ;        (leu (cc0) (const_int 0)))]
1127 ;  ""
1128 ;  "* cc_status = cc_prev_status;
1129 ;     return \"sls %0\"; ")
1130
1131
1132 ;; Basic conditional jump instructions.
1133
1134 (define_insn "beq"
1135   [(set (pc)
1136         (if_then_else (eq (cc0)
1137                           (const_int 0))
1138                       (label_ref (match_operand 0 "" ""))
1139                       (pc)))]
1140   ""
1141   "* return branch_or_jump (\"ez\", CODE_LABEL_NUMBER (operands[0]));
1142   ")
1143
1144 (define_insn "bne"
1145   [(set (pc)
1146         (if_then_else (ne (cc0)
1147                           (const_int 0))
1148                       (label_ref (match_operand 0 "" ""))
1149                       (pc)))]
1150   ""
1151   "* return branch_or_jump (\"nz\", CODE_LABEL_NUMBER (operands[0]));
1152   ")
1153
1154 (define_insn "bgt"
1155   [(set (pc)
1156         (if_then_else (gt (cc0)
1157                           (const_int 0))
1158                       (label_ref (match_operand 0 "" ""))
1159                       (pc)))]
1160   ""
1161   "* return branch_or_jump (\"gt\", CODE_LABEL_NUMBER (operands[0]));
1162   ")
1163
1164 (define_insn "blt"
1165   [(set (pc)
1166         (if_then_else (lt (cc0)
1167                           (const_int 0))
1168                       (label_ref (match_operand 0 "" ""))
1169                       (pc)))]
1170   ""
1171   "* return branch_or_jump (\"lt\", CODE_LABEL_NUMBER (operands[0]));
1172   ")
1173
1174 (define_insn "bge"
1175   [(set (pc)
1176         (if_then_else (ge (cc0)
1177                           (const_int 0))
1178                       (label_ref (match_operand 0 "" ""))
1179                       (pc)))]
1180   ""
1181   "* return branch_or_jump (\"ge\", CODE_LABEL_NUMBER (operands[0]));
1182   ")
1183
1184 (define_insn "ble"
1185   [(set (pc)
1186         (if_then_else (le (cc0)
1187                           (const_int 0))
1188                       (label_ref (match_operand 0 "" ""))
1189                       (pc)))]
1190   ""
1191   "* return branch_or_jump (\"le\", CODE_LABEL_NUMBER (operands[0]));
1192   ")
1193
1194
1195 ; no unsigned branches available on 1750. But GCC still needs them, so faking:
1196
1197 (define_insn "bgtu"
1198   [(set (pc)
1199         (if_then_else (gtu (cc0)
1200                           (const_int 0))
1201                       (label_ref (match_operand 0 "" ""))
1202                       (pc)))]
1203   ""
1204   "jc gt,%l0 ; Warning: this should be an *unsigned* test!")
1205
1206 (define_insn "bltu"
1207   [(set (pc)
1208         (if_then_else (ltu (cc0)
1209                           (const_int 0))
1210                       (label_ref (match_operand 0 "" ""))
1211                       (pc)))]
1212   ""
1213   "jc lt,%l0 ; Warning: this should be an *unsigned* test!")
1214
1215 (define_insn "bgeu"
1216   [(set (pc)
1217         (if_then_else (geu (cc0)
1218                           (const_int 0))
1219                       (label_ref (match_operand 0 "" ""))
1220                       (pc)))]
1221   ""
1222   "jc ge,%l0 ; Warning: this should be an *unsigned* test!")
1223
1224 (define_insn "bleu"
1225   [(set (pc)
1226         (if_then_else (leu (cc0)
1227                           (const_int 0))
1228                       (label_ref (match_operand 0 "" ""))
1229                       (pc)))]
1230   ""
1231   "jc le,%l0 ; Warning: this should be an *unsigned* test!")
1232
1233
1234 ;; Negated conditional jump instructions.
1235
1236 (define_insn ""
1237   [(set (pc)
1238         (if_then_else (eq (cc0)
1239                           (const_int 0))
1240                       (pc)
1241                       (label_ref (match_operand 0 "" ""))))]
1242   ""
1243   "* return branch_or_jump (\"nz\", CODE_LABEL_NUMBER (operands[0]));
1244   ")
1245
1246 (define_insn ""
1247   [(set (pc)
1248         (if_then_else (ne (cc0)
1249                           (const_int 0))
1250                       (pc)
1251                       (label_ref (match_operand 0 "" ""))))]
1252   ""
1253   "* return branch_or_jump (\"ez\", CODE_LABEL_NUMBER (operands[0]));
1254   ")
1255
1256 (define_insn ""
1257   [(set (pc)
1258         (if_then_else (gt (cc0)
1259                           (const_int 0))
1260                       (pc)
1261                       (label_ref (match_operand 0 "" ""))))]
1262   ""
1263   "* return branch_or_jump (\"le\", CODE_LABEL_NUMBER (operands[0]));
1264   ")
1265
1266 (define_insn ""
1267   [(set (pc)
1268         (if_then_else (lt (cc0)
1269                           (const_int 0))
1270                       (pc)
1271                       (label_ref (match_operand 0 "" ""))))]
1272   ""
1273   "* return branch_or_jump (\"ge\", CODE_LABEL_NUMBER (operands[0]));
1274   ")
1275
1276 (define_insn ""
1277   [(set (pc)
1278         (if_then_else (ge (cc0)
1279                           (const_int 0))
1280                       (pc)
1281                       (label_ref (match_operand 0 "" ""))))]
1282   ""
1283   "* return branch_or_jump (\"lt\", CODE_LABEL_NUMBER (operands[0]));
1284   ")
1285
1286 (define_insn ""
1287   [(set (pc)
1288         (if_then_else (le (cc0)
1289                           (const_int 0))
1290                       (pc)
1291                       (label_ref (match_operand 0 "" ""))))]
1292   ""
1293   "* return branch_or_jump (\"gt\", CODE_LABEL_NUMBER (operands[0]));
1294   ")
1295
1296
1297 ;; Negated unsigned conditional jump instructions (faked for 1750).
1298
1299 (define_insn ""
1300   [(set (pc)
1301         (if_then_else (gtu (cc0)
1302                           (const_int 0))
1303                       (pc)
1304                       (label_ref (match_operand 0 "" ""))))]
1305   ""
1306   "jc le,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1307
1308 (define_insn ""
1309   [(set (pc)
1310         (if_then_else (ltu (cc0)
1311                           (const_int 0))
1312                       (pc)
1313                       (label_ref (match_operand 0 "" ""))))]
1314   ""
1315   "jc ge,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1316
1317 (define_insn ""
1318   [(set (pc)
1319         (if_then_else (geu (cc0)
1320                           (const_int 0))
1321                       (pc)
1322                       (label_ref (match_operand 0 "" ""))))]
1323   ""
1324   "jc lt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1325
1326 (define_insn ""
1327   [(set (pc)
1328         (if_then_else (leu (cc0)
1329                           (const_int 0))
1330                       (pc)
1331                       (label_ref (match_operand 0 "" ""))))]
1332   ""
1333   "jc gt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1334
1335 ;; Tablejump
1336 ;; 1750 note: CASE_VECTOR_PC_RELATIVE is not defined
1337 (define_insn "tablejump"
1338   [(set (pc)
1339         (match_operand:QI 0 "register_operand" "b"))
1340    (use (label_ref (match_operand 1 "" "")))]
1341   ""
1342   "jc 15,0,r%0   ; tablejump label_ref=%1")
1343
1344
1345 ;; Unconditional jump
1346 (define_insn "jump"
1347   [(set (pc)
1348         (label_ref (match_operand 0 "" "")))]
1349   ""
1350   "jc 15,%0")
1351
1352 ;; Call subroutine, returning value in operand 0
1353 ;; (which must be a hard register).
1354 (define_insn "call_value"
1355   [(set (match_operand 0 "register_operand" "r")
1356         (call (match_operand:QI 1 "memory_operand" "m")
1357               (match_operand:QI 2 "general_operand" "g")))]
1358   ;; Operand 2 not really used for 1750.
1359   ""
1360   "sjs r15,%1   ; return value in R0")
1361
1362 ;; Call subroutine with no return value.
1363
1364 ;;  Operand 1 not really used in MIL-STD-1750.
1365 (define_insn ""
1366   [(call (match_operand:QI 0 "memory_operand" "mp")
1367          (match_operand:QI 1 "general_operand" ""))]
1368   ""
1369   "sjs r15,%0   ; no return value")
1370
1371 ;;;;;;;;;;;; 1750: NOT READY YET.
1372 (define_insn "call"
1373   [(call (match_operand:QI 0 "" "")
1374          (match_operand:QI 1 "" ""))]
1375   ""
1376   "ANYCALL %0")
1377
1378
1379 ; (define_insn "return"
1380 ;   [(return)]
1381 ;   ""
1382 ;   "*
1383 ;    {
1384 ;         rtx oprnd = GEN_INT (get_frame_size());
1385 ;         output_asm_insn(\"ret.m  %0\",&oprnd);
1386 ;         return \"\;\";
1387 ;    } ")
1388
1389 (define_insn "indirect_jump"
1390   [(set (pc) (match_operand:QI 0 "address_operand" "p"))]
1391   ""
1392   "jci 15,%0")
1393
1394 (define_insn "nop"
1395   [(const_int 0)]
1396   ""
1397   "nop")
1398
1399
1400 ;; Subtract One and Jump (if non-zero)
1401 (define_peephole
1402   [(set (match_operand:QI 0 "register_operand" "=r")
1403         (plus:QI (match_operand:QI 1 "register_operand" "%0")
1404                  (match_operand:QI 2 "immediate_operand" "J")))
1405    (set (cc0) (match_dup 0))
1406    (set (pc)
1407         (if_then_else (ne (cc0) (const_int 0))
1408          (label_ref (match_operand 3 "" ""))
1409          (pc)))
1410    ]
1411   "INTVAL(operands[2]) == -1"
1412   "soj r%0,%3")
1413
1414 ;; Combine a Load Register with subsequent increment/decrement into a LIM
1415 (define_peephole
1416   [(set (match_operand:QI 0 "register_operand" "=r")
1417         (match_operand:QI 1 "register_operand" "b"))
1418    (set (match_dup 0)
1419         (plus:QI (match_dup 0)
1420                  (match_operand:QI 2 "immediate_operand" "i")))]
1421   "REGNO(operands[1]) > 0"
1422   "lim r%0,%2,r%1  ; LR,inc/dec peephole")
1423
1424 ;; Eliminate the redundant load in a store/load sequence
1425 (define_peephole
1426   [(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "r")
1427                           (match_operand:QI 1 "immediate_operand" "i")))
1428         (match_operand:QI 2 "register_operand" "r"))
1429    (set (match_operand:QI 3 "register_operand" "=r")
1430         (mem:QI (plus:QI (match_dup 0)
1431                          (match_dup 1))))
1432    ]
1433   "REGNO(operands[2]) == REGNO(operands[3])"
1434   "st r%2,%1,r%0  ; eliminated previous redundant load")
1435
1436 ;;;End.