1 /* Tuning model description for AArch64 architecture.
2 Copyright (C) 2009-2024 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #ifndef GCC_AARCH64_H_QDF24XX
21 #define GCC_AARCH64_H_QDF24XX
25 static const struct cpu_addrcost_table qdf24xx_addrcost_table
=
35 1, /* post_modify_ld3_st3 */
36 1, /* post_modify_ld4_st4 */
37 3, /* register_offset */
38 3, /* register_sextend */
39 3, /* register_zextend */
43 static const struct cpu_regmove_cost qdf24xx_regmove_cost
=
46 /* Avoid the use of int<->fp moves for spilling. */
52 static const advsimd_vec_cost qdf24xx_advsimd_vector_cost
=
54 1, /* int_stmt_cost */
56 0, /* ld2_st2_permute_cost */
57 0, /* ld3_st3_permute_cost */
58 0, /* ld4_st4_permute_cost */
60 1, /* reduc_i8_cost */
61 1, /* reduc_i16_cost */
62 1, /* reduc_i32_cost */
63 1, /* reduc_i64_cost */
64 1, /* reduc_f16_cost */
65 1, /* reduc_f32_cost */
66 1, /* reduc_f64_cost */
67 1, /* store_elt_extra_cost */
68 1, /* vec_to_scalar_cost */
69 1, /* scalar_to_vec_cost */
70 1, /* align_load_cost */
71 1, /* unalign_load_cost */
72 1, /* unalign_store_cost */
76 /* QDF24XX costs for vector insn classes. */
77 static const struct cpu_vector_cost qdf24xx_vector_cost
=
79 1, /* scalar_int_stmt_cost */
80 1, /* scalar_fp_stmt_cost */
81 1, /* scalar_load_cost */
82 1, /* scalar_store_cost */
83 3, /* cond_taken_branch_cost */
84 1, /* cond_not_taken_branch_cost */
85 &qdf24xx_advsimd_vector_cost
, /* advsimd */
87 nullptr /* issue_info */
90 static const cpu_prefetch_tune qdf24xx_prefetch_tune
=
93 32, /* l1_cache_size */
94 64, /* l1_cache_line_size */
95 512, /* l2_cache_size */
96 false, /* prefetch_dynamic_strides */
97 2048, /* minimum_stride */
98 3 /* default_opt_level */
101 static const struct tune_params qdf24xx_tunings
=
103 &qdf24xx_extra_costs
,
104 &qdf24xx_addrcost_table
,
105 &qdf24xx_regmove_cost
,
106 &qdf24xx_vector_cost
,
107 &generic_branch_cost
,
108 &generic_approx_modes
,
109 SVE_NOT_IMPLEMENTED
, /* sve_width */
116 }, /* memmov_cost. */
118 (AARCH64_FUSE_MOV_MOVK
| AARCH64_FUSE_ADRP_ADD
119 | AARCH64_FUSE_MOVK_MOVK
), /* fuseable_ops */
120 "16", /* function_align. */
121 "8", /* jump_align. */
122 "16", /* loop_align. */
123 2, /* int_reassoc_width. */
124 4, /* fp_reassoc_width. */
125 1, /* fma_reassoc_width. */
126 1, /* vec_reassoc_width. */
127 2, /* min_div_recip_mul_sf. */
128 2, /* min_div_recip_mul_df. */
129 0, /* max_case_values. */
130 tune_params::AUTOPREFETCHER_WEAK
, /* autoprefetcher_model. */
131 AARCH64_EXTRA_TUNE_RENAME_LOAD_REGS
, /* tune_flags. */
132 &qdf24xx_prefetch_tune
,
133 AARCH64_LDP_STP_POLICY_ALWAYS
, /* ldp_policy_model. */
134 AARCH64_LDP_STP_POLICY_ALWAYS
/* stp_policy_model. */
137 #endif /* GCC_AARCH64_H_QDF24XX. */