1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
44 #include "diagnostic-core.h"
46 #include "integrate.h"
49 #include "target-def.h"
50 #include "common/common-target.h"
52 #include "langhooks.h"
53 #include "splay-tree.h"
54 #include "cfglayout.h"
56 #include "tree-flow.h"
57 #include "tree-stdarg.h"
58 #include "tm-constrs.h"
63 /* Specify which cpu to schedule for. */
64 enum processor_type alpha_tune
;
66 /* Which cpu we're generating code for. */
67 enum processor_type alpha_cpu
;
69 static const char * const alpha_cpu_name
[] =
74 /* Specify how accurate floating-point traps need to be. */
76 enum alpha_trap_precision alpha_tp
;
78 /* Specify the floating-point rounding mode. */
80 enum alpha_fp_rounding_mode alpha_fprm
;
82 /* Specify which things cause traps. */
84 enum alpha_fp_trap_mode alpha_fptm
;
86 /* Nonzero if inside of a function, because the Alpha asm can't
87 handle .files inside of functions. */
89 static int inside_function
= FALSE
;
91 /* The number of cycles of latency we should assume on memory reads. */
93 int alpha_memory_latency
= 3;
95 /* Whether the function needs the GP. */
97 static int alpha_function_needs_gp
;
99 /* The assembler name of the current function. */
101 static const char *alpha_fnname
;
103 /* The next explicit relocation sequence number. */
104 extern GTY(()) int alpha_next_sequence_number
;
105 int alpha_next_sequence_number
= 1;
107 /* The literal and gpdisp sequence numbers for this insn, as printed
108 by %# and %* respectively. */
109 extern GTY(()) int alpha_this_literal_sequence_number
;
110 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
111 int alpha_this_literal_sequence_number
;
112 int alpha_this_gpdisp_sequence_number
;
114 /* Costs of various operations on the different architectures. */
116 struct alpha_rtx_cost_data
118 unsigned char fp_add
;
119 unsigned char fp_mult
;
120 unsigned char fp_div_sf
;
121 unsigned char fp_div_df
;
122 unsigned char int_mult_si
;
123 unsigned char int_mult_di
;
124 unsigned char int_shift
;
125 unsigned char int_cmov
;
126 unsigned short int_div
;
129 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
132 COSTS_N_INSNS (6), /* fp_add */
133 COSTS_N_INSNS (6), /* fp_mult */
134 COSTS_N_INSNS (34), /* fp_div_sf */
135 COSTS_N_INSNS (63), /* fp_div_df */
136 COSTS_N_INSNS (23), /* int_mult_si */
137 COSTS_N_INSNS (23), /* int_mult_di */
138 COSTS_N_INSNS (2), /* int_shift */
139 COSTS_N_INSNS (2), /* int_cmov */
140 COSTS_N_INSNS (97), /* int_div */
143 COSTS_N_INSNS (4), /* fp_add */
144 COSTS_N_INSNS (4), /* fp_mult */
145 COSTS_N_INSNS (15), /* fp_div_sf */
146 COSTS_N_INSNS (22), /* fp_div_df */
147 COSTS_N_INSNS (8), /* int_mult_si */
148 COSTS_N_INSNS (12), /* int_mult_di */
149 COSTS_N_INSNS (1) + 1, /* int_shift */
150 COSTS_N_INSNS (1), /* int_cmov */
151 COSTS_N_INSNS (83), /* int_div */
154 COSTS_N_INSNS (4), /* fp_add */
155 COSTS_N_INSNS (4), /* fp_mult */
156 COSTS_N_INSNS (12), /* fp_div_sf */
157 COSTS_N_INSNS (15), /* fp_div_df */
158 COSTS_N_INSNS (7), /* int_mult_si */
159 COSTS_N_INSNS (7), /* int_mult_di */
160 COSTS_N_INSNS (1), /* int_shift */
161 COSTS_N_INSNS (2), /* int_cmov */
162 COSTS_N_INSNS (86), /* int_div */
166 /* Similar but tuned for code size instead of execution latency. The
167 extra +N is fractional cost tuning based on latency. It's used to
168 encourage use of cheaper insns like shift, but only if there's just
171 static struct alpha_rtx_cost_data
const alpha_rtx_cost_size
=
173 COSTS_N_INSNS (1), /* fp_add */
174 COSTS_N_INSNS (1), /* fp_mult */
175 COSTS_N_INSNS (1), /* fp_div_sf */
176 COSTS_N_INSNS (1) + 1, /* fp_div_df */
177 COSTS_N_INSNS (1) + 1, /* int_mult_si */
178 COSTS_N_INSNS (1) + 2, /* int_mult_di */
179 COSTS_N_INSNS (1), /* int_shift */
180 COSTS_N_INSNS (1), /* int_cmov */
181 COSTS_N_INSNS (6), /* int_div */
184 /* Get the number of args of a function in one of two ways. */
185 #if TARGET_ABI_OPEN_VMS
186 #define NUM_ARGS crtl->args.info.num_args
188 #define NUM_ARGS crtl->args.info
194 /* Declarations of static functions. */
195 static struct machine_function
*alpha_init_machine_status (void);
196 static rtx
alpha_emit_xfloating_compare (enum rtx_code
*, rtx
, rtx
);
198 #if TARGET_ABI_OPEN_VMS
199 static void alpha_write_linkage (FILE *, const char *);
200 static bool vms_valid_pointer_mode (enum machine_mode
);
202 #define vms_patch_builtins() gcc_unreachable()
205 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
206 /* Implement TARGET_MANGLE_TYPE. */
209 alpha_mangle_type (const_tree type
)
211 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
212 && TARGET_LONG_DOUBLE_128
)
215 /* For all other types, use normal C++ mangling. */
220 /* Parse target option strings. */
223 alpha_option_override (void)
225 static const struct cpu_table
{
226 const char *const name
;
227 const enum processor_type processor
;
230 { "ev4", PROCESSOR_EV4
, 0 },
231 { "ev45", PROCESSOR_EV4
, 0 },
232 { "21064", PROCESSOR_EV4
, 0 },
233 { "ev5", PROCESSOR_EV5
, 0 },
234 { "21164", PROCESSOR_EV5
, 0 },
235 { "ev56", PROCESSOR_EV5
, MASK_BWX
},
236 { "21164a", PROCESSOR_EV5
, MASK_BWX
},
237 { "pca56", PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
238 { "21164PC",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
239 { "21164pc",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
240 { "ev6", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
241 { "21264", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
242 { "ev67", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
},
243 { "21264a", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
}
246 int const ct_size
= ARRAY_SIZE (cpu_table
);
249 #ifdef SUBTARGET_OVERRIDE_OPTIONS
250 SUBTARGET_OVERRIDE_OPTIONS
;
253 /* Default to full IEEE compliance mode for Go language. */
254 if (strcmp (lang_hooks
.name
, "GNU Go") == 0
255 && !(target_flags_explicit
& MASK_IEEE
))
256 target_flags
|= MASK_IEEE
;
258 alpha_fprm
= ALPHA_FPRM_NORM
;
259 alpha_tp
= ALPHA_TP_PROG
;
260 alpha_fptm
= ALPHA_FPTM_N
;
264 alpha_tp
= ALPHA_TP_INSN
;
265 alpha_fptm
= ALPHA_FPTM_SU
;
267 if (TARGET_IEEE_WITH_INEXACT
)
269 alpha_tp
= ALPHA_TP_INSN
;
270 alpha_fptm
= ALPHA_FPTM_SUI
;
275 if (! strcmp (alpha_tp_string
, "p"))
276 alpha_tp
= ALPHA_TP_PROG
;
277 else if (! strcmp (alpha_tp_string
, "f"))
278 alpha_tp
= ALPHA_TP_FUNC
;
279 else if (! strcmp (alpha_tp_string
, "i"))
280 alpha_tp
= ALPHA_TP_INSN
;
282 error ("bad value %qs for -mtrap-precision switch", alpha_tp_string
);
285 if (alpha_fprm_string
)
287 if (! strcmp (alpha_fprm_string
, "n"))
288 alpha_fprm
= ALPHA_FPRM_NORM
;
289 else if (! strcmp (alpha_fprm_string
, "m"))
290 alpha_fprm
= ALPHA_FPRM_MINF
;
291 else if (! strcmp (alpha_fprm_string
, "c"))
292 alpha_fprm
= ALPHA_FPRM_CHOP
;
293 else if (! strcmp (alpha_fprm_string
,"d"))
294 alpha_fprm
= ALPHA_FPRM_DYN
;
296 error ("bad value %qs for -mfp-rounding-mode switch",
300 if (alpha_fptm_string
)
302 if (strcmp (alpha_fptm_string
, "n") == 0)
303 alpha_fptm
= ALPHA_FPTM_N
;
304 else if (strcmp (alpha_fptm_string
, "u") == 0)
305 alpha_fptm
= ALPHA_FPTM_U
;
306 else if (strcmp (alpha_fptm_string
, "su") == 0)
307 alpha_fptm
= ALPHA_FPTM_SU
;
308 else if (strcmp (alpha_fptm_string
, "sui") == 0)
309 alpha_fptm
= ALPHA_FPTM_SUI
;
311 error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string
);
314 if (alpha_cpu_string
)
316 for (i
= 0; i
< ct_size
; i
++)
317 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
319 alpha_tune
= alpha_cpu
= cpu_table
[i
].processor
;
320 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
);
321 target_flags
|= cpu_table
[i
].flags
;
325 error ("bad value %qs for -mcpu switch", alpha_cpu_string
);
328 if (alpha_tune_string
)
330 for (i
= 0; i
< ct_size
; i
++)
331 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
333 alpha_tune
= cpu_table
[i
].processor
;
337 error ("bad value %qs for -mtune switch", alpha_tune_string
);
340 /* Do some sanity checks on the above options. */
342 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
343 && alpha_tp
!= ALPHA_TP_INSN
&& alpha_cpu
!= PROCESSOR_EV6
)
345 warning (0, "fp software completion requires -mtrap-precision=i");
346 alpha_tp
= ALPHA_TP_INSN
;
349 if (alpha_cpu
== PROCESSOR_EV6
)
351 /* Except for EV6 pass 1 (not released), we always have precise
352 arithmetic traps. Which means we can do software completion
353 without minding trap shadows. */
354 alpha_tp
= ALPHA_TP_PROG
;
357 if (TARGET_FLOAT_VAX
)
359 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
361 warning (0, "rounding mode not supported for VAX floats");
362 alpha_fprm
= ALPHA_FPRM_NORM
;
364 if (alpha_fptm
== ALPHA_FPTM_SUI
)
366 warning (0, "trap mode not supported for VAX floats");
367 alpha_fptm
= ALPHA_FPTM_SU
;
369 if (target_flags_explicit
& MASK_LONG_DOUBLE_128
)
370 warning (0, "128-bit long double not supported for VAX floats");
371 target_flags
&= ~MASK_LONG_DOUBLE_128
;
378 if (!alpha_mlat_string
)
379 alpha_mlat_string
= "L1";
381 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
382 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
384 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
385 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
386 && alpha_mlat_string
[2] == '\0')
388 static int const cache_latency
[][4] =
390 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
391 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
392 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
395 lat
= alpha_mlat_string
[1] - '0';
396 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_tune
][lat
-1] == -1)
398 warning (0, "L%d cache latency unknown for %s",
399 lat
, alpha_cpu_name
[alpha_tune
]);
403 lat
= cache_latency
[alpha_tune
][lat
-1];
405 else if (! strcmp (alpha_mlat_string
, "main"))
407 /* Most current memories have about 370ns latency. This is
408 a reasonable guess for a fast cpu. */
413 warning (0, "bad value %qs for -mmemory-latency", alpha_mlat_string
);
417 alpha_memory_latency
= lat
;
420 /* Default the definition of "small data" to 8 bytes. */
421 if (!global_options_set
.x_g_switch_value
)
424 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
426 target_flags
|= MASK_SMALL_DATA
;
427 else if (flag_pic
== 2)
428 target_flags
&= ~MASK_SMALL_DATA
;
430 /* Align labels and loops for optimal branching. */
431 /* ??? Kludge these by not doing anything if we don't optimize and also if
432 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
433 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
435 if (align_loops
<= 0)
437 if (align_jumps
<= 0)
440 if (align_functions
<= 0)
441 align_functions
= 16;
443 /* Register variables and functions with the garbage collector. */
445 /* Set up function hooks. */
446 init_machine_status
= alpha_init_machine_status
;
448 /* Tell the compiler when we're using VAX floating point. */
449 if (TARGET_FLOAT_VAX
)
451 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
452 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
453 REAL_MODE_FORMAT (TFmode
) = NULL
;
456 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
457 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
458 target_flags
|= MASK_LONG_DOUBLE_128
;
462 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
465 zap_mask (HOST_WIDE_INT value
)
469 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
471 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
477 /* Return true if OP is valid for a particular TLS relocation.
478 We are already guaranteed that OP is a CONST. */
481 tls_symbolic_operand_1 (rtx op
, int size
, int unspec
)
485 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
487 op
= XVECEXP (op
, 0, 0);
489 if (GET_CODE (op
) != SYMBOL_REF
)
492 switch (SYMBOL_REF_TLS_MODEL (op
))
494 case TLS_MODEL_LOCAL_DYNAMIC
:
495 return unspec
== UNSPEC_DTPREL
&& size
== alpha_tls_size
;
496 case TLS_MODEL_INITIAL_EXEC
:
497 return unspec
== UNSPEC_TPREL
&& size
== 64;
498 case TLS_MODEL_LOCAL_EXEC
:
499 return unspec
== UNSPEC_TPREL
&& size
== alpha_tls_size
;
505 /* Used by aligned_memory_operand and unaligned_memory_operand to
506 resolve what reload is going to do with OP if it's a register. */
509 resolve_reload_operand (rtx op
)
511 if (reload_in_progress
)
514 if (GET_CODE (tmp
) == SUBREG
)
515 tmp
= SUBREG_REG (tmp
);
517 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
519 op
= reg_equiv_memory_loc (REGNO (tmp
));
527 /* The scalar modes supported differs from the default check-what-c-supports
528 version in that sometimes TFmode is available even when long double
529 indicates only DFmode. */
532 alpha_scalar_mode_supported_p (enum machine_mode mode
)
540 case TImode
: /* via optabs.c */
548 return TARGET_HAS_XFLOATING_LIBS
;
555 /* Alpha implements a couple of integer vector mode operations when
556 TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
557 which allows the vectorizer to operate on e.g. move instructions,
558 or when expand_vector_operations can do something useful. */
561 alpha_vector_mode_supported_p (enum machine_mode mode
)
563 return mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
;
566 /* Return 1 if this function can directly return via $26. */
571 return (TARGET_ABI_OSF
573 && alpha_sa_size () == 0
574 && get_frame_size () == 0
575 && crtl
->outgoing_args_size
== 0
576 && crtl
->args
.pretend_args_size
== 0);
579 /* Return the TLS model to use for SYMBOL. */
581 static enum tls_model
582 tls_symbolic_operand_type (rtx symbol
)
584 enum tls_model model
;
586 if (GET_CODE (symbol
) != SYMBOL_REF
)
587 return TLS_MODEL_NONE
;
588 model
= SYMBOL_REF_TLS_MODEL (symbol
);
590 /* Local-exec with a 64-bit size is the same code as initial-exec. */
591 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
592 model
= TLS_MODEL_INITIAL_EXEC
;
597 /* Return true if the function DECL will share the same GP as any
598 function in the current unit of translation. */
601 decl_has_samegp (const_tree decl
)
603 /* Functions that are not local can be overridden, and thus may
604 not share the same gp. */
605 if (!(*targetm
.binds_local_p
) (decl
))
608 /* If -msmall-data is in effect, assume that there is only one GP
609 for the module, and so any local symbol has this property. We
610 need explicit relocations to be able to enforce this for symbols
611 not defined in this unit of translation, however. */
612 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
615 /* Functions that are not external are defined in this UoT. */
616 /* ??? Irritatingly, static functions not yet emitted are still
617 marked "external". Apply this to non-static functions only. */
618 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
621 /* Return true if EXP should be placed in the small data section. */
624 alpha_in_small_data_p (const_tree exp
)
626 /* We want to merge strings, so we never consider them small data. */
627 if (TREE_CODE (exp
) == STRING_CST
)
630 /* Functions are never in the small data area. Duh. */
631 if (TREE_CODE (exp
) == FUNCTION_DECL
)
634 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
636 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
637 if (strcmp (section
, ".sdata") == 0
638 || strcmp (section
, ".sbss") == 0)
643 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
645 /* If this is an incomplete type with size 0, then we can't put it
646 in sdata because it might be too big when completed. */
647 if (size
> 0 && size
<= g_switch_value
)
654 #if TARGET_ABI_OPEN_VMS
656 vms_valid_pointer_mode (enum machine_mode mode
)
658 return (mode
== SImode
|| mode
== DImode
);
662 alpha_linkage_symbol_p (const char *symname
)
664 int symlen
= strlen (symname
);
667 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
672 #define LINKAGE_SYMBOL_REF_P(X) \
673 ((GET_CODE (X) == SYMBOL_REF \
674 && alpha_linkage_symbol_p (XSTR (X, 0))) \
675 || (GET_CODE (X) == CONST \
676 && GET_CODE (XEXP (X, 0)) == PLUS \
677 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
678 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
681 /* legitimate_address_p recognizes an RTL expression that is a valid
682 memory address for an instruction. The MODE argument is the
683 machine mode for the MEM expression that wants to use this address.
685 For Alpha, we have either a constant address or the sum of a
686 register and a constant address, or just a register. For DImode,
687 any of those forms can be surrounded with an AND that clear the
688 low-order three bits; this is an "unaligned" access. */
691 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
693 /* If this is an ldq_u type address, discard the outer AND. */
695 && GET_CODE (x
) == AND
696 && CONST_INT_P (XEXP (x
, 1))
697 && INTVAL (XEXP (x
, 1)) == -8)
700 /* Discard non-paradoxical subregs. */
701 if (GET_CODE (x
) == SUBREG
702 && (GET_MODE_SIZE (GET_MODE (x
))
703 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
706 /* Unadorned general registers are valid. */
709 ? STRICT_REG_OK_FOR_BASE_P (x
)
710 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
713 /* Constant addresses (i.e. +/- 32k) are valid. */
714 if (CONSTANT_ADDRESS_P (x
))
717 #if TARGET_ABI_OPEN_VMS
718 if (LINKAGE_SYMBOL_REF_P (x
))
722 /* Register plus a small constant offset is valid. */
723 if (GET_CODE (x
) == PLUS
)
725 rtx ofs
= XEXP (x
, 1);
728 /* Discard non-paradoxical subregs. */
729 if (GET_CODE (x
) == SUBREG
730 && (GET_MODE_SIZE (GET_MODE (x
))
731 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
737 && NONSTRICT_REG_OK_FP_BASE_P (x
)
738 && CONST_INT_P (ofs
))
741 ? STRICT_REG_OK_FOR_BASE_P (x
)
742 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
743 && CONSTANT_ADDRESS_P (ofs
))
748 /* If we're managing explicit relocations, LO_SUM is valid, as are small
749 data symbols. Avoid explicit relocations of modes larger than word
750 mode since i.e. $LC0+8($1) can fold around +/- 32k offset. */
751 else if (TARGET_EXPLICIT_RELOCS
752 && GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
754 if (small_symbolic_operand (x
, Pmode
))
757 if (GET_CODE (x
) == LO_SUM
)
759 rtx ofs
= XEXP (x
, 1);
762 /* Discard non-paradoxical subregs. */
763 if (GET_CODE (x
) == SUBREG
764 && (GET_MODE_SIZE (GET_MODE (x
))
765 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
768 /* Must have a valid base register. */
771 ? STRICT_REG_OK_FOR_BASE_P (x
)
772 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
775 /* The symbol must be local. */
776 if (local_symbolic_operand (ofs
, Pmode
)
777 || dtp32_symbolic_operand (ofs
, Pmode
)
778 || tp32_symbolic_operand (ofs
, Pmode
))
786 /* Build the SYMBOL_REF for __tls_get_addr. */
788 static GTY(()) rtx tls_get_addr_libfunc
;
791 get_tls_get_addr (void)
793 if (!tls_get_addr_libfunc
)
794 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
795 return tls_get_addr_libfunc
;
798 /* Try machine-dependent ways of modifying an illegitimate address
799 to be legitimate. If we find one, return the new, valid address. */
802 alpha_legitimize_address_1 (rtx x
, rtx scratch
, enum machine_mode mode
)
804 HOST_WIDE_INT addend
;
806 /* If the address is (plus reg const_int) and the CONST_INT is not a
807 valid offset, compute the high part of the constant and add it to
808 the register. Then our address is (plus temp low-part-const). */
809 if (GET_CODE (x
) == PLUS
810 && REG_P (XEXP (x
, 0))
811 && CONST_INT_P (XEXP (x
, 1))
812 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
814 addend
= INTVAL (XEXP (x
, 1));
819 /* If the address is (const (plus FOO const_int)), find the low-order
820 part of the CONST_INT. Then load FOO plus any high-order part of the
821 CONST_INT into a register. Our address is (plus reg low-part-const).
822 This is done to reduce the number of GOT entries. */
823 if (can_create_pseudo_p ()
824 && GET_CODE (x
) == CONST
825 && GET_CODE (XEXP (x
, 0)) == PLUS
826 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)))
828 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
829 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
833 /* If we have a (plus reg const), emit the load as in (2), then add
834 the two registers, and finally generate (plus reg low-part-const) as
836 if (can_create_pseudo_p ()
837 && GET_CODE (x
) == PLUS
838 && REG_P (XEXP (x
, 0))
839 && GET_CODE (XEXP (x
, 1)) == CONST
840 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
841 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 1), 0), 1)))
843 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
844 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
845 XEXP (XEXP (XEXP (x
, 1), 0), 0),
846 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
850 /* If this is a local symbol, split the address into HIGH/LO_SUM parts.
851 Avoid modes larger than word mode since i.e. $LC0+8($1) can fold
852 around +/- 32k offset. */
853 if (TARGET_EXPLICIT_RELOCS
854 && GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
855 && symbolic_operand (x
, Pmode
))
857 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
859 switch (tls_symbolic_operand_type (x
))
864 case TLS_MODEL_GLOBAL_DYNAMIC
:
867 r0
= gen_rtx_REG (Pmode
, 0);
868 r16
= gen_rtx_REG (Pmode
, 16);
869 tga
= get_tls_get_addr ();
870 dest
= gen_reg_rtx (Pmode
);
871 seq
= GEN_INT (alpha_next_sequence_number
++);
873 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
874 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
875 insn
= emit_call_insn (insn
);
876 RTL_CONST_CALL_P (insn
) = 1;
877 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
882 emit_libcall_block (insn
, dest
, r0
, x
);
885 case TLS_MODEL_LOCAL_DYNAMIC
:
888 r0
= gen_rtx_REG (Pmode
, 0);
889 r16
= gen_rtx_REG (Pmode
, 16);
890 tga
= get_tls_get_addr ();
891 scratch
= gen_reg_rtx (Pmode
);
892 seq
= GEN_INT (alpha_next_sequence_number
++);
894 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
895 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
896 insn
= emit_call_insn (insn
);
897 RTL_CONST_CALL_P (insn
) = 1;
898 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
903 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
905 emit_libcall_block (insn
, scratch
, r0
, eqv
);
907 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
908 eqv
= gen_rtx_CONST (Pmode
, eqv
);
910 if (alpha_tls_size
== 64)
912 dest
= gen_reg_rtx (Pmode
);
913 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
914 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
917 if (alpha_tls_size
== 32)
919 insn
= gen_rtx_HIGH (Pmode
, eqv
);
920 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
921 scratch
= gen_reg_rtx (Pmode
);
922 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
924 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
926 case TLS_MODEL_INITIAL_EXEC
:
927 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
928 eqv
= gen_rtx_CONST (Pmode
, eqv
);
929 tp
= gen_reg_rtx (Pmode
);
930 scratch
= gen_reg_rtx (Pmode
);
931 dest
= gen_reg_rtx (Pmode
);
933 emit_insn (gen_load_tp (tp
));
934 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
935 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
938 case TLS_MODEL_LOCAL_EXEC
:
939 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
940 eqv
= gen_rtx_CONST (Pmode
, eqv
);
941 tp
= gen_reg_rtx (Pmode
);
943 emit_insn (gen_load_tp (tp
));
944 if (alpha_tls_size
== 32)
946 insn
= gen_rtx_HIGH (Pmode
, eqv
);
947 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
948 tp
= gen_reg_rtx (Pmode
);
949 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
951 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
957 if (local_symbolic_operand (x
, Pmode
))
959 if (small_symbolic_operand (x
, Pmode
))
963 if (can_create_pseudo_p ())
964 scratch
= gen_reg_rtx (Pmode
);
965 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
966 gen_rtx_HIGH (Pmode
, x
)));
967 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
976 HOST_WIDE_INT low
, high
;
978 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
980 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
984 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
985 (!can_create_pseudo_p () ? scratch
: NULL_RTX
),
988 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
989 (!can_create_pseudo_p () ? scratch
: NULL_RTX
),
992 return plus_constant (x
, low
);
997 /* Try machine-dependent ways of modifying an illegitimate address
998 to be legitimate. Return X or the new, valid address. */
1001 alpha_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1002 enum machine_mode mode
)
1004 rtx new_x
= alpha_legitimize_address_1 (x
, NULL_RTX
, mode
);
1005 return new_x
? new_x
: x
;
1008 /* Primarily this is required for TLS symbols, but given that our move
1009 patterns *ought* to be able to handle any symbol at any time, we
1010 should never be spilling symbolic operands to the constant pool, ever. */
1013 alpha_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1015 enum rtx_code code
= GET_CODE (x
);
1016 return code
== SYMBOL_REF
|| code
== LABEL_REF
|| code
== CONST
;
1019 /* We do not allow indirect calls to be optimized into sibling calls, nor
1020 can we allow a call to a function with a different GP to be optimized
1024 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1026 /* Can't do indirect tail calls, since we don't know if the target
1027 uses the same GP. */
1031 /* Otherwise, we can make a tail call if the target function shares
1033 return decl_has_samegp (decl
);
1037 some_small_symbolic_operand_int (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1041 /* Don't re-split. */
1042 if (GET_CODE (x
) == LO_SUM
)
1045 return small_symbolic_operand (x
, Pmode
) != 0;
1049 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1053 /* Don't re-split. */
1054 if (GET_CODE (x
) == LO_SUM
)
1057 if (small_symbolic_operand (x
, Pmode
))
1059 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
1068 split_small_symbolic_operand (rtx x
)
1071 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
1075 /* Indicate that INSN cannot be duplicated. This is true for any insn
1076 that we've marked with gpdisp relocs, since those have to stay in
1077 1-1 correspondence with one another.
1079 Technically we could copy them if we could set up a mapping from one
1080 sequence number to another, across the set of insns to be duplicated.
1081 This seems overly complicated and error-prone since interblock motion
1082 from sched-ebb could move one of the pair of insns to a different block.
1084 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
1085 then they'll be in a different block from their ldgp. Which could lead
1086 the bb reorder code to think that it would be ok to copy just the block
1087 containing the call and branch to the block containing the ldgp. */
1090 alpha_cannot_copy_insn_p (rtx insn
)
1092 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
1094 if (recog_memoized (insn
) >= 0)
1095 return get_attr_cannot_copy (insn
);
1101 /* Try a machine-dependent way of reloading an illegitimate address
1102 operand. If we find one, push the reload and return the new rtx. */
1105 alpha_legitimize_reload_address (rtx x
,
1106 enum machine_mode mode ATTRIBUTE_UNUSED
,
1107 int opnum
, int type
,
1108 int ind_levels ATTRIBUTE_UNUSED
)
1110 /* We must recognize output that we have already generated ourselves. */
1111 if (GET_CODE (x
) == PLUS
1112 && GET_CODE (XEXP (x
, 0)) == PLUS
1113 && REG_P (XEXP (XEXP (x
, 0), 0))
1114 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
1115 && CONST_INT_P (XEXP (x
, 1)))
1117 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1118 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1119 opnum
, (enum reload_type
) type
);
1123 /* We wish to handle large displacements off a base register by
1124 splitting the addend across an ldah and the mem insn. This
1125 cuts number of extra insns needed from 3 to 1. */
1126 if (GET_CODE (x
) == PLUS
1127 && REG_P (XEXP (x
, 0))
1128 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
1129 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
1130 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1132 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
1133 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
1135 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1137 /* Check for 32-bit overflow. */
1138 if (high
+ low
!= val
)
1141 /* Reload the high part into a base reg; leave the low part
1142 in the mem directly. */
1143 x
= gen_rtx_PLUS (GET_MODE (x
),
1144 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
1148 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1149 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1150 opnum
, (enum reload_type
) type
);
1157 /* Compute a (partial) cost for rtx X. Return true if the complete
1158 cost has been computed, and false if subexpressions should be
1159 scanned. In either case, *TOTAL contains the cost result. */
1162 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
1165 enum machine_mode mode
= GET_MODE (x
);
1166 bool float_mode_p
= FLOAT_MODE_P (mode
);
1167 const struct alpha_rtx_cost_data
*cost_data
;
1170 cost_data
= &alpha_rtx_cost_size
;
1172 cost_data
= &alpha_rtx_cost_data
[alpha_tune
];
1177 /* If this is an 8-bit constant, return zero since it can be used
1178 nearly anywhere with no cost. If it is a valid operand for an
1179 ADD or AND, likewise return 0 if we know it will be used in that
1180 context. Otherwise, return 2 since it might be used there later.
1181 All other constants take at least two insns. */
1182 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
1190 if (x
== CONST0_RTX (mode
))
1192 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
1193 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
1195 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
1198 *total
= COSTS_N_INSNS (2);
1204 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
1205 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
1206 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
1207 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
1208 else if (tls_symbolic_operand_type (x
))
1209 /* Estimate of cost for call_pal rduniq. */
1210 /* ??? How many insns do we emit here? More than one... */
1211 *total
= COSTS_N_INSNS (15);
1213 /* Otherwise we do a load from the GOT. */
1214 *total
= COSTS_N_INSNS (!speed
? 1 : alpha_memory_latency
);
1218 /* This is effectively an add_operand. */
1225 *total
= cost_data
->fp_add
;
1226 else if (GET_CODE (XEXP (x
, 0)) == MULT
1227 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
1229 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0),
1230 (enum rtx_code
) outer_code
, opno
, speed
)
1231 + rtx_cost (XEXP (x
, 1),
1232 (enum rtx_code
) outer_code
, opno
, speed
)
1233 + COSTS_N_INSNS (1));
1240 *total
= cost_data
->fp_mult
;
1241 else if (mode
== DImode
)
1242 *total
= cost_data
->int_mult_di
;
1244 *total
= cost_data
->int_mult_si
;
1248 if (CONST_INT_P (XEXP (x
, 1))
1249 && INTVAL (XEXP (x
, 1)) <= 3)
1251 *total
= COSTS_N_INSNS (1);
1258 *total
= cost_data
->int_shift
;
1263 *total
= cost_data
->fp_add
;
1265 *total
= cost_data
->int_cmov
;
1273 *total
= cost_data
->int_div
;
1274 else if (mode
== SFmode
)
1275 *total
= cost_data
->fp_div_sf
;
1277 *total
= cost_data
->fp_div_df
;
1281 *total
= COSTS_N_INSNS (!speed
? 1 : alpha_memory_latency
);
1287 *total
= COSTS_N_INSNS (1);
1295 *total
= COSTS_N_INSNS (1) + cost_data
->int_cmov
;
1301 case UNSIGNED_FLOAT
:
1304 case FLOAT_TRUNCATE
:
1305 *total
= cost_data
->fp_add
;
1309 if (MEM_P (XEXP (x
, 0)))
1312 *total
= cost_data
->fp_add
;
1320 /* REF is an alignable memory location. Place an aligned SImode
1321 reference into *PALIGNED_MEM and the number of bits to shift into
1322 *PBITNUM. SCRATCH is a free register for use in reloading out
1323 of range stack slots. */
1326 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
1329 HOST_WIDE_INT disp
, offset
;
1331 gcc_assert (MEM_P (ref
));
1333 if (reload_in_progress
1334 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1336 base
= find_replacement (&XEXP (ref
, 0));
1337 gcc_assert (memory_address_p (GET_MODE (ref
), base
));
1340 base
= XEXP (ref
, 0);
1342 if (GET_CODE (base
) == PLUS
)
1343 disp
= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1347 /* Find the byte offset within an aligned word. If the memory itself is
1348 claimed to be aligned, believe it. Otherwise, aligned_memory_operand
1349 will have examined the base register and determined it is aligned, and
1350 thus displacements from it are naturally alignable. */
1351 if (MEM_ALIGN (ref
) >= 32)
1356 /* The location should not cross aligned word boundary. */
1357 gcc_assert (offset
+ GET_MODE_SIZE (GET_MODE (ref
))
1358 <= GET_MODE_SIZE (SImode
));
1360 /* Access the entire aligned word. */
1361 *paligned_mem
= widen_memory_access (ref
, SImode
, -offset
);
1363 /* Convert the byte offset within the word to a bit offset. */
1364 offset
*= BITS_PER_UNIT
;
1365 *pbitnum
= GEN_INT (offset
);
1368 /* Similar, but just get the address. Handle the two reload cases.
1369 Add EXTRA_OFFSET to the address we return. */
1372 get_unaligned_address (rtx ref
)
1375 HOST_WIDE_INT offset
= 0;
1377 gcc_assert (MEM_P (ref
));
1379 if (reload_in_progress
1380 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1382 base
= find_replacement (&XEXP (ref
, 0));
1384 gcc_assert (memory_address_p (GET_MODE (ref
), base
));
1387 base
= XEXP (ref
, 0);
1389 if (GET_CODE (base
) == PLUS
)
1390 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1392 return plus_constant (base
, offset
);
1395 /* Compute a value X, such that X & 7 == (ADDR + OFS) & 7.
1396 X is always returned in a register. */
1399 get_unaligned_offset (rtx addr
, HOST_WIDE_INT ofs
)
1401 if (GET_CODE (addr
) == PLUS
)
1403 ofs
+= INTVAL (XEXP (addr
, 1));
1404 addr
= XEXP (addr
, 0);
1407 return expand_simple_binop (Pmode
, PLUS
, addr
, GEN_INT (ofs
& 7),
1408 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1411 /* On the Alpha, all (non-symbolic) constants except zero go into
1412 a floating-point register via memory. Note that we cannot
1413 return anything that is not a subset of RCLASS, and that some
1414 symbolic constants cannot be dropped to memory. */
1417 alpha_preferred_reload_class(rtx x
, enum reg_class rclass
)
1419 /* Zero is present in any register class. */
1420 if (x
== CONST0_RTX (GET_MODE (x
)))
1423 /* These sorts of constants we can easily drop to memory. */
1425 || GET_CODE (x
) == CONST_DOUBLE
1426 || GET_CODE (x
) == CONST_VECTOR
)
1428 if (rclass
== FLOAT_REGS
)
1430 if (rclass
== ALL_REGS
)
1431 return GENERAL_REGS
;
1435 /* All other kinds of constants should not (and in the case of HIGH
1436 cannot) be dropped to memory -- instead we use a GENERAL_REGS
1437 secondary reload. */
1439 return (rclass
== ALL_REGS
? GENERAL_REGS
: rclass
);
1444 /* Inform reload about cases where moving X with a mode MODE to a register in
1445 RCLASS requires an extra scratch or immediate register. Return the class
1446 needed for the immediate register. */
1449 alpha_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
1450 enum machine_mode mode
, secondary_reload_info
*sri
)
1452 enum reg_class rclass
= (enum reg_class
) rclass_i
;
1454 /* Loading and storing HImode or QImode values to and from memory
1455 usually requires a scratch register. */
1456 if (!TARGET_BWX
&& (mode
== QImode
|| mode
== HImode
|| mode
== CQImode
))
1458 if (any_memory_operand (x
, mode
))
1462 if (!aligned_memory_operand (x
, mode
))
1463 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
1466 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
1471 /* We also cannot do integral arithmetic into FP regs, as might result
1472 from register elimination into a DImode fp register. */
1473 if (rclass
== FLOAT_REGS
)
1475 if (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == AND
)
1476 return GENERAL_REGS
;
1477 if (in_p
&& INTEGRAL_MODE_P (mode
)
1478 && !MEM_P (x
) && !REG_P (x
) && !CONST_INT_P (x
))
1479 return GENERAL_REGS
;
1485 /* Subfunction of the following function. Update the flags of any MEM
1486 found in part of X. */
1489 alpha_set_memflags_1 (rtx
*xp
, void *data
)
1491 rtx x
= *xp
, orig
= (rtx
) data
;
1496 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (orig
);
1497 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (orig
);
1498 MEM_READONLY_P (x
) = MEM_READONLY_P (orig
);
1500 /* Sadly, we cannot use alias sets because the extra aliasing
1501 produced by the AND interferes. Given that two-byte quantities
1502 are the only thing we would be able to differentiate anyway,
1503 there does not seem to be any point in convoluting the early
1504 out of the alias check. */
1509 /* Given SEQ, which is an INSN list, look for any MEMs in either
1510 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
1511 volatile flags from REF into each of the MEMs found. If REF is not
1512 a MEM, don't do anything. */
1515 alpha_set_memflags (rtx seq
, rtx ref
)
1522 /* This is only called from alpha.md, after having had something
1523 generated from one of the insn patterns. So if everything is
1524 zero, the pattern is already up-to-date. */
1525 if (!MEM_VOLATILE_P (ref
)
1526 && !MEM_NOTRAP_P (ref
)
1527 && !MEM_READONLY_P (ref
))
1530 for (insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
1532 for_each_rtx (&PATTERN (insn
), alpha_set_memflags_1
, (void *) ref
);
1537 static rtx
alpha_emit_set_const (rtx
, enum machine_mode
, HOST_WIDE_INT
,
1540 /* Internal routine for alpha_emit_set_const to check for N or below insns.
1541 If NO_OUTPUT is true, then we only check to see if N insns are possible,
1542 and return pc_rtx if successful. */
1545 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
1546 HOST_WIDE_INT c
, int n
, bool no_output
)
1548 HOST_WIDE_INT new_const
;
1550 /* Use a pseudo if highly optimizing and still generating RTL. */
1552 = (flag_expensive_optimizations
&& can_create_pseudo_p () ? 0 : target
);
1555 /* If this is a sign-extended 32-bit constant, we can do this in at most
1556 three insns, so do it if we have enough insns left. We always have
1557 a sign-extended 32-bit constant when compiling on a narrow machine. */
1559 if (HOST_BITS_PER_WIDE_INT
!= 64
1560 || c
>> 31 == -1 || c
>> 31 == 0)
1562 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
1563 HOST_WIDE_INT tmp1
= c
- low
;
1564 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
1565 HOST_WIDE_INT extra
= 0;
1567 /* If HIGH will be interpreted as negative but the constant is
1568 positive, we must adjust it to do two ldha insns. */
1570 if ((high
& 0x8000) != 0 && c
>= 0)
1574 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
1577 if (c
== low
|| (low
== 0 && extra
== 0))
1579 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1580 but that meant that we can't handle INT_MIN on 32-bit machines
1581 (like NT/Alpha), because we recurse indefinitely through
1582 emit_move_insn to gen_movdi. So instead, since we know exactly
1583 what we want, create it explicitly. */
1588 target
= gen_reg_rtx (mode
);
1589 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
1592 else if (n
>= 2 + (extra
!= 0))
1596 if (!can_create_pseudo_p ())
1598 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (high
<< 16)));
1602 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16),
1605 /* As of 2002-02-23, addsi3 is only available when not optimizing.
1606 This means that if we go through expand_binop, we'll try to
1607 generate extensions, etc, which will require new pseudos, which
1608 will fail during some split phases. The SImode add patterns
1609 still exist, but are not named. So build the insns by hand. */
1614 subtarget
= gen_reg_rtx (mode
);
1615 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
1616 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
1622 target
= gen_reg_rtx (mode
);
1623 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
1624 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
1630 /* If we couldn't do it that way, try some other methods. But if we have
1631 no instructions left, don't bother. Likewise, if this is SImode and
1632 we can't make pseudos, we can't do anything since the expand_binop
1633 and expand_unop calls will widen and try to make pseudos. */
1635 if (n
== 1 || (mode
== SImode
&& !can_create_pseudo_p ()))
1638 /* Next, see if we can load a related constant and then shift and possibly
1639 negate it to get the constant we want. Try this once each increasing
1640 numbers of insns. */
1642 for (i
= 1; i
< n
; i
++)
1644 /* First, see if minus some low bits, we've an easy load of
1647 new_const
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
1650 temp
= alpha_emit_set_const (subtarget
, mode
, c
- new_const
, i
, no_output
);
1655 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new_const
),
1656 target
, 0, OPTAB_WIDEN
);
1660 /* Next try complementing. */
1661 temp
= alpha_emit_set_const (subtarget
, mode
, ~c
, i
, no_output
);
1666 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
1669 /* Next try to form a constant and do a left shift. We can do this
1670 if some low-order bits are zero; the exact_log2 call below tells
1671 us that information. The bits we are shifting out could be any
1672 value, but here we'll just try the 0- and sign-extended forms of
1673 the constant. To try to increase the chance of having the same
1674 constant in more than one insn, start at the highest number of
1675 bits to shift, but try all possibilities in case a ZAPNOT will
1678 bits
= exact_log2 (c
& -c
);
1680 for (; bits
> 0; bits
--)
1682 new_const
= c
>> bits
;
1683 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, i
, no_output
);
1686 new_const
= (unsigned HOST_WIDE_INT
)c
>> bits
;
1687 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
,
1694 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
1695 target
, 0, OPTAB_WIDEN
);
1699 /* Now try high-order zero bits. Here we try the shifted-in bits as
1700 all zero and all ones. Be careful to avoid shifting outside the
1701 mode and to avoid shifting outside the host wide int size. */
1702 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1703 confuse the recursive call and set all of the high 32 bits. */
1705 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1706 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64));
1708 for (; bits
> 0; bits
--)
1710 new_const
= c
<< bits
;
1711 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, i
, no_output
);
1714 new_const
= (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1715 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
,
1722 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
1723 target
, 1, OPTAB_WIDEN
);
1727 /* Now try high-order 1 bits. We get that with a sign-extension.
1728 But one bit isn't enough here. Be careful to avoid shifting outside
1729 the mode and to avoid shifting outside the host wide int size. */
1731 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1732 - floor_log2 (~ c
) - 2);
1734 for (; bits
> 0; bits
--)
1736 new_const
= c
<< bits
;
1737 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, i
, no_output
);
1740 new_const
= (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1741 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
,
1748 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
1749 target
, 0, OPTAB_WIDEN
);
1754 #if HOST_BITS_PER_WIDE_INT == 64
1755 /* Finally, see if can load a value into the target that is the same as the
1756 constant except that all bytes that are 0 are changed to be 0xff. If we
1757 can, then we can do a ZAPNOT to obtain the desired constant. */
1760 for (i
= 0; i
< 64; i
+= 8)
1761 if ((new_const
& ((HOST_WIDE_INT
) 0xff << i
)) == 0)
1762 new_const
|= (HOST_WIDE_INT
) 0xff << i
;
1764 /* We are only called for SImode and DImode. If this is SImode, ensure that
1765 we are sign extended to a full word. */
1768 new_const
= ((new_const
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1772 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, n
- 1, no_output
);
1777 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new_const
),
1778 target
, 0, OPTAB_WIDEN
);
1786 /* Try to output insns to set TARGET equal to the constant C if it can be
1787 done in less than N insns. Do all computations in MODE. Returns the place
1788 where the output has been placed if it can be done and the insns have been
1789 emitted. If it would take more than N insns, zero is returned and no
1790 insns and emitted. */
1793 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
1794 HOST_WIDE_INT c
, int n
, bool no_output
)
1796 enum machine_mode orig_mode
= mode
;
1797 rtx orig_target
= target
;
1801 /* If we can't make any pseudos, TARGET is an SImode hard register, we
1802 can't load this constant in one insn, do this in DImode. */
1803 if (!can_create_pseudo_p () && mode
== SImode
1804 && REG_P (target
) && REGNO (target
) < FIRST_PSEUDO_REGISTER
)
1806 result
= alpha_emit_set_const_1 (target
, mode
, c
, 1, no_output
);
1810 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
1813 else if (mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
)
1815 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
1819 /* Try 1 insn, then 2, then up to N. */
1820 for (i
= 1; i
<= n
; i
++)
1822 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
, no_output
);
1830 insn
= get_last_insn ();
1831 set
= single_set (insn
);
1832 if (! CONSTANT_P (SET_SRC (set
)))
1833 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
1838 /* Allow for the case where we changed the mode of TARGET. */
1841 if (result
== target
)
1842 result
= orig_target
;
1843 else if (mode
!= orig_mode
)
1844 result
= gen_lowpart (orig_mode
, result
);
1850 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
1851 fall back to a straight forward decomposition. We do this to avoid
1852 exponential run times encountered when looking for longer sequences
1853 with alpha_emit_set_const. */
1856 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
1858 HOST_WIDE_INT d1
, d2
, d3
, d4
;
1860 /* Decompose the entire word */
1861 #if HOST_BITS_PER_WIDE_INT >= 64
1862 gcc_assert (c2
== -(c1
< 0));
1863 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
1865 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1866 c1
= (c1
- d2
) >> 32;
1867 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
1869 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1870 gcc_assert (c1
== d4
);
1872 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
1874 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1875 gcc_assert (c1
== d2
);
1877 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
1879 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1880 gcc_assert (c2
== d4
);
1883 /* Construct the high word */
1886 emit_move_insn (target
, GEN_INT (d4
));
1888 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
1891 emit_move_insn (target
, GEN_INT (d3
));
1893 /* Shift it into place */
1894 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
1896 /* Add in the low bits. */
1898 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
1900 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
1905 /* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return
1909 alpha_extract_integer (rtx x
, HOST_WIDE_INT
*p0
, HOST_WIDE_INT
*p1
)
1911 HOST_WIDE_INT i0
, i1
;
1913 if (GET_CODE (x
) == CONST_VECTOR
)
1914 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
1917 if (CONST_INT_P (x
))
1922 else if (HOST_BITS_PER_WIDE_INT
>= 64)
1924 i0
= CONST_DOUBLE_LOW (x
);
1929 i0
= CONST_DOUBLE_LOW (x
);
1930 i1
= CONST_DOUBLE_HIGH (x
);
1937 /* Implement TARGET_LEGITIMATE_CONSTANT_P. This is all constants for which
1938 we are willing to load the value into a register via a move pattern.
1939 Normally this is all symbolic constants, integral constants that
1940 take three or fewer instructions, and floating-point zero. */
1943 alpha_legitimate_constant_p (enum machine_mode mode
, rtx x
)
1945 HOST_WIDE_INT i0
, i1
;
1947 switch (GET_CODE (x
))
1954 if (GET_CODE (XEXP (x
, 0)) == PLUS
1955 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1956 x
= XEXP (XEXP (x
, 0), 0);
1960 if (GET_CODE (x
) != SYMBOL_REF
)
1966 /* TLS symbols are never valid. */
1967 return SYMBOL_REF_TLS_MODEL (x
) == 0;
1970 if (x
== CONST0_RTX (mode
))
1972 if (FLOAT_MODE_P (mode
))
1977 if (x
== CONST0_RTX (mode
))
1979 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
1981 if (GET_MODE_SIZE (mode
) != 8)
1987 if (TARGET_BUILD_CONSTANTS
)
1989 alpha_extract_integer (x
, &i0
, &i1
);
1990 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== (-i0
< 0))
1991 return alpha_emit_set_const_1 (x
, mode
, i0
, 3, true) != NULL
;
1999 /* Operand 1 is known to be a constant, and should require more than one
2000 instruction to load. Emit that multi-part load. */
2003 alpha_split_const_mov (enum machine_mode mode
, rtx
*operands
)
2005 HOST_WIDE_INT i0
, i1
;
2006 rtx temp
= NULL_RTX
;
2008 alpha_extract_integer (operands
[1], &i0
, &i1
);
2010 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2011 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3, false);
2013 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2014 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2018 if (!rtx_equal_p (operands
[0], temp
))
2019 emit_move_insn (operands
[0], temp
);
2026 /* Expand a move instruction; return true if all work is done.
2027 We don't handle non-bwx subword loads here. */
2030 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
2034 /* If the output is not a register, the input must be. */
2035 if (MEM_P (operands
[0])
2036 && ! reg_or_0_operand (operands
[1], mode
))
2037 operands
[1] = force_reg (mode
, operands
[1]);
2039 /* Allow legitimize_address to perform some simplifications. */
2040 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2042 tmp
= alpha_legitimize_address_1 (operands
[1], operands
[0], mode
);
2045 if (tmp
== operands
[0])
2052 /* Early out for non-constants and valid constants. */
2053 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2056 /* Split large integers. */
2057 if (CONST_INT_P (operands
[1])
2058 || GET_CODE (operands
[1]) == CONST_DOUBLE
2059 || GET_CODE (operands
[1]) == CONST_VECTOR
)
2061 if (alpha_split_const_mov (mode
, operands
))
2065 /* Otherwise we've nothing left but to drop the thing to memory. */
2066 tmp
= force_const_mem (mode
, operands
[1]);
2068 if (tmp
== NULL_RTX
)
2071 if (reload_in_progress
)
2073 emit_move_insn (operands
[0], XEXP (tmp
, 0));
2074 operands
[1] = replace_equiv_address (tmp
, operands
[0]);
2077 operands
[1] = validize_mem (tmp
);
2081 /* Expand a non-bwx QImode or HImode move instruction;
2082 return true if all work is done. */
2085 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2089 /* If the output is not a register, the input must be. */
2090 if (MEM_P (operands
[0]))
2091 operands
[1] = force_reg (mode
, operands
[1]);
2093 /* Handle four memory cases, unaligned and aligned for either the input
2094 or the output. The only case where we can be called during reload is
2095 for aligned loads; all other cases require temporaries. */
2097 if (any_memory_operand (operands
[1], mode
))
2099 if (aligned_memory_operand (operands
[1], mode
))
2101 if (reload_in_progress
)
2104 seq
= gen_reload_inqi_aligned (operands
[0], operands
[1]);
2106 seq
= gen_reload_inhi_aligned (operands
[0], operands
[1]);
2111 rtx aligned_mem
, bitnum
;
2112 rtx scratch
= gen_reg_rtx (SImode
);
2116 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2118 subtarget
= operands
[0];
2119 if (REG_P (subtarget
))
2120 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2122 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2125 seq
= gen_aligned_loadqi (subtarget
, aligned_mem
,
2128 seq
= gen_aligned_loadhi (subtarget
, aligned_mem
,
2133 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2138 /* Don't pass these as parameters since that makes the generated
2139 code depend on parameter evaluation order which will cause
2140 bootstrap failures. */
2142 rtx temp1
, temp2
, subtarget
, ua
;
2145 temp1
= gen_reg_rtx (DImode
);
2146 temp2
= gen_reg_rtx (DImode
);
2148 subtarget
= operands
[0];
2149 if (REG_P (subtarget
))
2150 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2152 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2154 ua
= get_unaligned_address (operands
[1]);
2156 seq
= gen_unaligned_loadqi (subtarget
, ua
, temp1
, temp2
);
2158 seq
= gen_unaligned_loadhi (subtarget
, ua
, temp1
, temp2
);
2160 alpha_set_memflags (seq
, operands
[1]);
2164 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2169 if (any_memory_operand (operands
[0], mode
))
2171 if (aligned_memory_operand (operands
[0], mode
))
2173 rtx aligned_mem
, bitnum
;
2174 rtx temp1
= gen_reg_rtx (SImode
);
2175 rtx temp2
= gen_reg_rtx (SImode
);
2177 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2179 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2184 rtx temp1
= gen_reg_rtx (DImode
);
2185 rtx temp2
= gen_reg_rtx (DImode
);
2186 rtx temp3
= gen_reg_rtx (DImode
);
2187 rtx ua
= get_unaligned_address (operands
[0]);
2190 seq
= gen_unaligned_storeqi (ua
, operands
[1], temp1
, temp2
, temp3
);
2192 seq
= gen_unaligned_storehi (ua
, operands
[1], temp1
, temp2
, temp3
);
2194 alpha_set_memflags (seq
, operands
[0]);
2203 /* Implement the movmisalign patterns. One of the operands is a memory
2204 that is not naturally aligned. Emit instructions to load it. */
2207 alpha_expand_movmisalign (enum machine_mode mode
, rtx
*operands
)
2209 /* Honor misaligned loads, for those we promised to do so. */
2210 if (MEM_P (operands
[1]))
2214 if (register_operand (operands
[0], mode
))
2217 tmp
= gen_reg_rtx (mode
);
2219 alpha_expand_unaligned_load (tmp
, operands
[1], 8, 0, 0);
2220 if (tmp
!= operands
[0])
2221 emit_move_insn (operands
[0], tmp
);
2223 else if (MEM_P (operands
[0]))
2225 if (!reg_or_0_operand (operands
[1], mode
))
2226 operands
[1] = force_reg (mode
, operands
[1]);
2227 alpha_expand_unaligned_store (operands
[0], operands
[1], 8, 0);
2233 /* Generate an unsigned DImode to FP conversion. This is the same code
2234 optabs would emit if we didn't have TFmode patterns.
2236 For SFmode, this is the only construction I've found that can pass
2237 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2238 intermediates will work, because you'll get intermediate rounding
2239 that ruins the end result. Some of this could be fixed by turning
2240 on round-to-positive-infinity, but that requires diddling the fpsr,
2241 which kills performance. I tried turning this around and converting
2242 to a negative number, so that I could turn on /m, but either I did
2243 it wrong or there's something else cause I wound up with the exact
2244 same single-bit error. There is a branch-less form of this same code:
2255 fcmoveq $f10,$f11,$f0
2257 I'm not using it because it's the same number of instructions as
2258 this branch-full form, and it has more serialized long latency
2259 instructions on the critical path.
2261 For DFmode, we can avoid rounding errors by breaking up the word
2262 into two pieces, converting them separately, and adding them back:
2264 LC0: .long 0,0x5f800000
2269 cpyse $f11,$f31,$f10
2270 cpyse $f31,$f11,$f11
2278 This doesn't seem to be a clear-cut win over the optabs form.
2279 It probably all depends on the distribution of numbers being
2280 converted -- in the optabs form, all but high-bit-set has a
2281 much lower minimum execution time. */
2284 alpha_emit_floatuns (rtx operands
[2])
2286 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
2287 enum machine_mode mode
;
2290 in
= force_reg (DImode
, operands
[1]);
2291 mode
= GET_MODE (out
);
2292 neglab
= gen_label_rtx ();
2293 donelab
= gen_label_rtx ();
2294 i0
= gen_reg_rtx (DImode
);
2295 i1
= gen_reg_rtx (DImode
);
2296 f0
= gen_reg_rtx (mode
);
2298 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
2300 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
2301 emit_jump_insn (gen_jump (donelab
));
2304 emit_label (neglab
);
2306 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
2307 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
2308 emit_insn (gen_iordi3 (i0
, i0
, i1
));
2309 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
2310 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
2312 emit_label (donelab
);
2315 /* Generate the comparison for a conditional branch. */
2318 alpha_emit_conditional_branch (rtx operands
[], enum machine_mode cmp_mode
)
2320 enum rtx_code cmp_code
, branch_code
;
2321 enum machine_mode branch_mode
= VOIDmode
;
2322 enum rtx_code code
= GET_CODE (operands
[0]);
2323 rtx op0
= operands
[1], op1
= operands
[2];
2326 if (cmp_mode
== TFmode
)
2328 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2333 /* The general case: fold the comparison code to the types of compares
2334 that we have, choosing the branch as necessary. */
2337 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2339 /* We have these compares: */
2340 cmp_code
= code
, branch_code
= NE
;
2345 /* These must be reversed. */
2346 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
2349 case GE
: case GT
: case GEU
: case GTU
:
2350 /* For FP, we swap them, for INT, we reverse them. */
2351 if (cmp_mode
== DFmode
)
2353 cmp_code
= swap_condition (code
);
2355 tem
= op0
, op0
= op1
, op1
= tem
;
2359 cmp_code
= reverse_condition (code
);
2368 if (cmp_mode
== DFmode
)
2370 if (flag_unsafe_math_optimizations
&& cmp_code
!= UNORDERED
)
2372 /* When we are not as concerned about non-finite values, and we
2373 are comparing against zero, we can branch directly. */
2374 if (op1
== CONST0_RTX (DFmode
))
2375 cmp_code
= UNKNOWN
, branch_code
= code
;
2376 else if (op0
== CONST0_RTX (DFmode
))
2378 /* Undo the swap we probably did just above. */
2379 tem
= op0
, op0
= op1
, op1
= tem
;
2380 branch_code
= swap_condition (cmp_code
);
2386 /* ??? We mark the branch mode to be CCmode to prevent the
2387 compare and branch from being combined, since the compare
2388 insn follows IEEE rules that the branch does not. */
2389 branch_mode
= CCmode
;
2394 /* The following optimizations are only for signed compares. */
2395 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
2397 /* Whee. Compare and branch against 0 directly. */
2398 if (op1
== const0_rtx
)
2399 cmp_code
= UNKNOWN
, branch_code
= code
;
2401 /* If the constants doesn't fit into an immediate, but can
2402 be generated by lda/ldah, we adjust the argument and
2403 compare against zero, so we can use beq/bne directly. */
2404 /* ??? Don't do this when comparing against symbols, otherwise
2405 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
2406 be declared false out of hand (at least for non-weak). */
2407 else if (CONST_INT_P (op1
)
2408 && (code
== EQ
|| code
== NE
)
2409 && !(symbolic_operand (op0
, VOIDmode
)
2410 || (REG_P (op0
) && REG_POINTER (op0
))))
2412 rtx n_op1
= GEN_INT (-INTVAL (op1
));
2414 if (! satisfies_constraint_I (op1
)
2415 && (satisfies_constraint_K (n_op1
)
2416 || satisfies_constraint_L (n_op1
)))
2417 cmp_code
= PLUS
, branch_code
= code
, op1
= n_op1
;
2421 if (!reg_or_0_operand (op0
, DImode
))
2422 op0
= force_reg (DImode
, op0
);
2423 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
2424 op1
= force_reg (DImode
, op1
);
2427 /* Emit an initial compare instruction, if necessary. */
2429 if (cmp_code
!= UNKNOWN
)
2431 tem
= gen_reg_rtx (cmp_mode
);
2432 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
2435 /* Emit the branch instruction. */
2436 tem
= gen_rtx_SET (VOIDmode
, pc_rtx
,
2437 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2438 gen_rtx_fmt_ee (branch_code
,
2440 CONST0_RTX (cmp_mode
)),
2441 gen_rtx_LABEL_REF (VOIDmode
,
2444 emit_jump_insn (tem
);
2447 /* Certain simplifications can be done to make invalid setcc operations
2448 valid. Return the final comparison, or NULL if we can't work. */
2451 alpha_emit_setcc (rtx operands
[], enum machine_mode cmp_mode
)
2453 enum rtx_code cmp_code
;
2454 enum rtx_code code
= GET_CODE (operands
[1]);
2455 rtx op0
= operands
[2], op1
= operands
[3];
2458 if (cmp_mode
== TFmode
)
2460 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2465 if (cmp_mode
== DFmode
&& !TARGET_FIX
)
2468 /* The general case: fold the comparison code to the types of compares
2469 that we have, choosing the branch as necessary. */
2474 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2476 /* We have these compares. */
2477 if (cmp_mode
== DFmode
)
2478 cmp_code
= code
, code
= NE
;
2482 if (cmp_mode
== DImode
&& op1
== const0_rtx
)
2487 cmp_code
= reverse_condition (code
);
2491 case GE
: case GT
: case GEU
: case GTU
:
2492 /* These normally need swapping, but for integer zero we have
2493 special patterns that recognize swapped operands. */
2494 if (cmp_mode
== DImode
&& op1
== const0_rtx
)
2496 code
= swap_condition (code
);
2497 if (cmp_mode
== DFmode
)
2498 cmp_code
= code
, code
= NE
;
2499 tmp
= op0
, op0
= op1
, op1
= tmp
;
2506 if (cmp_mode
== DImode
)
2508 if (!register_operand (op0
, DImode
))
2509 op0
= force_reg (DImode
, op0
);
2510 if (!reg_or_8bit_operand (op1
, DImode
))
2511 op1
= force_reg (DImode
, op1
);
2514 /* Emit an initial compare instruction, if necessary. */
2515 if (cmp_code
!= UNKNOWN
)
2517 tmp
= gen_reg_rtx (cmp_mode
);
2518 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
2519 gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
)));
2521 op0
= cmp_mode
!= DImode
? gen_lowpart (DImode
, tmp
) : tmp
;
2525 /* Emit the setcc instruction. */
2526 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2527 gen_rtx_fmt_ee (code
, DImode
, op0
, op1
)));
2532 /* Rewrite a comparison against zero CMP of the form
2533 (CODE (cc0) (const_int 0)) so it can be written validly in
2534 a conditional move (if_then_else CMP ...).
2535 If both of the operands that set cc0 are nonzero we must emit
2536 an insn to perform the compare (it can't be done within
2537 the conditional move). */
2540 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
2542 enum rtx_code code
= GET_CODE (cmp
);
2543 enum rtx_code cmov_code
= NE
;
2544 rtx op0
= XEXP (cmp
, 0);
2545 rtx op1
= XEXP (cmp
, 1);
2546 enum machine_mode cmp_mode
2547 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
2548 enum machine_mode cmov_mode
= VOIDmode
;
2549 int local_fast_math
= flag_unsafe_math_optimizations
;
2552 if (cmp_mode
== TFmode
)
2554 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2559 gcc_assert (cmp_mode
== DFmode
|| cmp_mode
== DImode
);
2561 if (FLOAT_MODE_P (cmp_mode
) != FLOAT_MODE_P (mode
))
2563 enum rtx_code cmp_code
;
2568 /* If we have fp<->int register move instructions, do a cmov by
2569 performing the comparison in fp registers, and move the
2570 zero/nonzero value to integer registers, where we can then
2571 use a normal cmov, or vice-versa. */
2575 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2576 /* We have these compares. */
2577 cmp_code
= code
, code
= NE
;
2581 /* This must be reversed. */
2582 cmp_code
= EQ
, code
= EQ
;
2585 case GE
: case GT
: case GEU
: case GTU
:
2586 /* These normally need swapping, but for integer zero we have
2587 special patterns that recognize swapped operands. */
2588 if (cmp_mode
== DImode
&& op1
== const0_rtx
)
2589 cmp_code
= code
, code
= NE
;
2592 cmp_code
= swap_condition (code
);
2594 tem
= op0
, op0
= op1
, op1
= tem
;
2602 tem
= gen_reg_rtx (cmp_mode
);
2603 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
2604 gen_rtx_fmt_ee (cmp_code
, cmp_mode
,
2607 cmp_mode
= cmp_mode
== DImode
? DFmode
: DImode
;
2608 op0
= gen_lowpart (cmp_mode
, tem
);
2609 op1
= CONST0_RTX (cmp_mode
);
2610 local_fast_math
= 1;
2613 /* We may be able to use a conditional move directly.
2614 This avoids emitting spurious compares. */
2615 if (signed_comparison_operator (cmp
, VOIDmode
)
2616 && (cmp_mode
== DImode
|| local_fast_math
)
2617 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
2618 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2620 /* We can't put the comparison inside the conditional move;
2621 emit a compare instruction and put that inside the
2622 conditional move. Make sure we emit only comparisons we have;
2623 swap or reverse as necessary. */
2625 if (!can_create_pseudo_p ())
2630 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2631 /* We have these compares: */
2635 /* This must be reversed. */
2636 code
= reverse_condition (code
);
2640 case GE
: case GT
: case GEU
: case GTU
:
2641 /* These must be swapped. */
2642 if (op1
!= CONST0_RTX (cmp_mode
))
2644 code
= swap_condition (code
);
2645 tem
= op0
, op0
= op1
, op1
= tem
;
2653 if (cmp_mode
== DImode
)
2655 if (!reg_or_0_operand (op0
, DImode
))
2656 op0
= force_reg (DImode
, op0
);
2657 if (!reg_or_8bit_operand (op1
, DImode
))
2658 op1
= force_reg (DImode
, op1
);
2661 /* ??? We mark the branch mode to be CCmode to prevent the compare
2662 and cmov from being combined, since the compare insn follows IEEE
2663 rules that the cmov does not. */
2664 if (cmp_mode
== DFmode
&& !local_fast_math
)
2667 tem
= gen_reg_rtx (cmp_mode
);
2668 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_mode
, op0
, op1
));
2669 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_mode
));
2672 /* Simplify a conditional move of two constants into a setcc with
2673 arithmetic. This is done with a splitter since combine would
2674 just undo the work if done during code generation. It also catches
2675 cases we wouldn't have before cse. */
2678 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
2679 rtx t_rtx
, rtx f_rtx
)
2681 HOST_WIDE_INT t
, f
, diff
;
2682 enum machine_mode mode
;
2683 rtx target
, subtarget
, tmp
;
2685 mode
= GET_MODE (dest
);
2690 if (((code
== NE
|| code
== EQ
) && diff
< 0)
2691 || (code
== GE
|| code
== GT
))
2693 code
= reverse_condition (code
);
2694 diff
= t
, t
= f
, f
= diff
;
2698 subtarget
= target
= dest
;
2701 target
= gen_lowpart (DImode
, dest
);
2702 if (can_create_pseudo_p ())
2703 subtarget
= gen_reg_rtx (DImode
);
2707 /* Below, we must be careful to use copy_rtx on target and subtarget
2708 in intermediate insns, as they may be a subreg rtx, which may not
2711 if (f
== 0 && exact_log2 (diff
) > 0
2712 /* On EV6, we've got enough shifters to make non-arithmetic shifts
2713 viable over a longer latency cmove. On EV5, the E0 slot is a
2714 scarce resource, and on EV4 shift has the same latency as a cmove. */
2715 && (diff
<= 8 || alpha_tune
== PROCESSOR_EV6
))
2717 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2718 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2720 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
2721 GEN_INT (exact_log2 (t
)));
2722 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2724 else if (f
== 0 && t
== -1)
2726 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2727 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2729 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
2731 else if (diff
== 1 || diff
== 4 || diff
== 8)
2735 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2736 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2739 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
2742 add_op
= GEN_INT (f
);
2743 if (sext_add_operand (add_op
, mode
))
2745 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
2747 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
2748 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2760 /* Look up the function X_floating library function name for the
2763 struct GTY(()) xfloating_op
2765 const enum rtx_code code
;
2766 const char *const GTY((skip
)) osf_func
;
2767 const char *const GTY((skip
)) vms_func
;
2771 static GTY(()) struct xfloating_op xfloating_ops
[] =
2773 { PLUS
, "_OtsAddX", "OTS$ADD_X", 0 },
2774 { MINUS
, "_OtsSubX", "OTS$SUB_X", 0 },
2775 { MULT
, "_OtsMulX", "OTS$MUL_X", 0 },
2776 { DIV
, "_OtsDivX", "OTS$DIV_X", 0 },
2777 { EQ
, "_OtsEqlX", "OTS$EQL_X", 0 },
2778 { NE
, "_OtsNeqX", "OTS$NEQ_X", 0 },
2779 { LT
, "_OtsLssX", "OTS$LSS_X", 0 },
2780 { LE
, "_OtsLeqX", "OTS$LEQ_X", 0 },
2781 { GT
, "_OtsGtrX", "OTS$GTR_X", 0 },
2782 { GE
, "_OtsGeqX", "OTS$GEQ_X", 0 },
2783 { FIX
, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
2784 { FLOAT
, "_OtsCvtQX", "OTS$CVTQX", 0 },
2785 { UNSIGNED_FLOAT
, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
2786 { FLOAT_EXTEND
, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
2787 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
2790 static GTY(()) struct xfloating_op vax_cvt_ops
[] =
2792 { FLOAT_EXTEND
, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
2793 { FLOAT_TRUNCATE
, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
2797 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
2799 struct xfloating_op
*ops
= xfloating_ops
;
2800 long n
= ARRAY_SIZE (xfloating_ops
);
2803 gcc_assert (TARGET_HAS_XFLOATING_LIBS
);
2805 /* How irritating. Nothing to key off for the main table. */
2806 if (TARGET_FLOAT_VAX
&& (code
== FLOAT_EXTEND
|| code
== FLOAT_TRUNCATE
))
2809 n
= ARRAY_SIZE (vax_cvt_ops
);
2812 for (i
= 0; i
< n
; ++i
, ++ops
)
2813 if (ops
->code
== code
)
2815 rtx func
= ops
->libcall
;
2818 func
= init_one_libfunc (TARGET_ABI_OPEN_VMS
2819 ? ops
->vms_func
: ops
->osf_func
);
2820 ops
->libcall
= func
;
2828 /* Most X_floating operations take the rounding mode as an argument.
2829 Compute that here. */
2832 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
2833 enum alpha_fp_rounding_mode round
)
2839 case ALPHA_FPRM_NORM
:
2842 case ALPHA_FPRM_MINF
:
2845 case ALPHA_FPRM_CHOP
:
2848 case ALPHA_FPRM_DYN
:
2854 /* XXX For reference, round to +inf is mode = 3. */
2857 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
2863 /* Emit an X_floating library function call.
2865 Note that these functions do not follow normal calling conventions:
2866 TFmode arguments are passed in two integer registers (as opposed to
2867 indirect); TFmode return values appear in R16+R17.
2869 FUNC is the function to call.
2870 TARGET is where the output belongs.
2871 OPERANDS are the inputs.
2872 NOPERANDS is the count of inputs.
2873 EQUIV is the expression equivalent for the function.
2877 alpha_emit_xfloating_libcall (rtx func
, rtx target
, rtx operands
[],
2878 int noperands
, rtx equiv
)
2880 rtx usage
= NULL_RTX
, tmp
, reg
;
2885 for (i
= 0; i
< noperands
; ++i
)
2887 switch (GET_MODE (operands
[i
]))
2890 reg
= gen_rtx_REG (TFmode
, regno
);
2895 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
2900 gcc_assert (CONST_INT_P (operands
[i
]));
2903 reg
= gen_rtx_REG (DImode
, regno
);
2911 emit_move_insn (reg
, operands
[i
]);
2912 use_reg (&usage
, reg
);
2915 switch (GET_MODE (target
))
2918 reg
= gen_rtx_REG (TFmode
, 16);
2921 reg
= gen_rtx_REG (DFmode
, 32);
2924 reg
= gen_rtx_REG (DImode
, 0);
2930 tmp
= gen_rtx_MEM (QImode
, func
);
2931 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
2932 const0_rtx
, const0_rtx
));
2933 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
2934 RTL_CONST_CALL_P (tmp
) = 1;
2939 emit_libcall_block (tmp
, target
, reg
, equiv
);
2942 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
2945 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
2949 rtx out_operands
[3];
2951 func
= alpha_lookup_xfloating_lib_func (code
);
2952 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
2954 out_operands
[0] = operands
[1];
2955 out_operands
[1] = operands
[2];
2956 out_operands
[2] = GEN_INT (mode
);
2957 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
2958 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
2962 /* Emit an X_floating library function call for a comparison. */
2965 alpha_emit_xfloating_compare (enum rtx_code
*pcode
, rtx op0
, rtx op1
)
2967 enum rtx_code cmp_code
, res_code
;
2968 rtx func
, out
, operands
[2], note
;
2970 /* X_floating library comparison functions return
2974 Convert the compare against the raw return value. */
3002 func
= alpha_lookup_xfloating_lib_func (cmp_code
);
3006 out
= gen_reg_rtx (DImode
);
3008 /* What's actually returned is -1,0,1, not a proper boolean value,
3009 so use an EXPR_LIST as with a generic libcall instead of a
3010 comparison type expression. */
3011 note
= gen_rtx_EXPR_LIST (VOIDmode
, op1
, NULL_RTX
);
3012 note
= gen_rtx_EXPR_LIST (VOIDmode
, op0
, note
);
3013 note
= gen_rtx_EXPR_LIST (VOIDmode
, func
, note
);
3014 alpha_emit_xfloating_libcall (func
, out
, operands
, 2, note
);
3019 /* Emit an X_floating library function call for a conversion. */
3022 alpha_emit_xfloating_cvt (enum rtx_code orig_code
, rtx operands
[])
3024 int noperands
= 1, mode
;
3025 rtx out_operands
[2];
3027 enum rtx_code code
= orig_code
;
3029 if (code
== UNSIGNED_FIX
)
3032 func
= alpha_lookup_xfloating_lib_func (code
);
3034 out_operands
[0] = operands
[1];
3039 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3040 out_operands
[1] = GEN_INT (mode
);
3043 case FLOAT_TRUNCATE
:
3044 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3045 out_operands
[1] = GEN_INT (mode
);
3052 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3053 gen_rtx_fmt_e (orig_code
,
3054 GET_MODE (operands
[0]),
3058 /* Split a TImode or TFmode move from OP[1] to OP[0] into a pair of
3059 DImode moves from OP[2,3] to OP[0,1]. If FIXUP_OVERLAP is true,
3060 guarantee that the sequence
3063 is valid. Naturally, output operand ordering is little-endian.
3064 This is used by *movtf_internal and *movti_internal. */
3067 alpha_split_tmode_pair (rtx operands
[4], enum machine_mode mode
,
3070 switch (GET_CODE (operands
[1]))
3073 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3074 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3078 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3079 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3084 gcc_assert (operands
[1] == CONST0_RTX (mode
));
3085 operands
[2] = operands
[3] = const0_rtx
;
3092 switch (GET_CODE (operands
[0]))
3095 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3096 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3100 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3101 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3108 if (fixup_overlap
&& reg_overlap_mentioned_p (operands
[0], operands
[3]))
3111 tmp
= operands
[0], operands
[0] = operands
[1], operands
[1] = tmp
;
3112 tmp
= operands
[2], operands
[2] = operands
[3], operands
[3] = tmp
;
3116 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3117 op2 is a register containing the sign bit, operation is the
3118 logical operation to be performed. */
3121 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3123 rtx high_bit
= operands
[2];
3127 alpha_split_tmode_pair (operands
, TFmode
, false);
3129 /* Detect three flavors of operand overlap. */
3131 if (rtx_equal_p (operands
[0], operands
[2]))
3133 else if (rtx_equal_p (operands
[1], operands
[2]))
3135 if (rtx_equal_p (operands
[0], high_bit
))
3142 emit_move_insn (operands
[0], operands
[2]);
3144 /* ??? If the destination overlaps both source tf and high_bit, then
3145 assume source tf is dead in its entirety and use the other half
3146 for a scratch register. Otherwise "scratch" is just the proper
3147 destination register. */
3148 scratch
= operands
[move
< 2 ? 1 : 3];
3150 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3154 emit_move_insn (operands
[0], operands
[2]);
3156 emit_move_insn (operands
[1], scratch
);
3160 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3164 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3165 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3166 lda r3,X(r11) lda r3,X+2(r11)
3167 extwl r1,r3,r1 extql r1,r3,r1
3168 extwh r2,r3,r2 extqh r2,r3,r2
3169 or r1.r2.r1 or r1,r2,r1
3172 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3173 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3174 lda r3,X(r11) lda r3,X(r11)
3175 extll r1,r3,r1 extll r1,r3,r1
3176 extlh r2,r3,r2 extlh r2,r3,r2
3177 or r1.r2.r1 addl r1,r2,r1
3179 quad: ldq_u r1,X(r11)
3188 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3189 HOST_WIDE_INT ofs
, int sign
)
3191 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3192 enum machine_mode mode
;
3194 if (TARGET_BWX
&& size
== 2)
3196 meml
= adjust_address (mem
, QImode
, ofs
);
3197 memh
= adjust_address (mem
, QImode
, ofs
+1);
3198 extl
= gen_reg_rtx (DImode
);
3199 exth
= gen_reg_rtx (DImode
);
3200 emit_insn (gen_zero_extendqidi2 (extl
, meml
));
3201 emit_insn (gen_zero_extendqidi2 (exth
, memh
));
3202 exth
= expand_simple_binop (DImode
, ASHIFT
, exth
, GEN_INT (8),
3203 NULL
, 1, OPTAB_LIB_WIDEN
);
3204 addr
= expand_simple_binop (DImode
, IOR
, extl
, exth
,
3205 NULL
, 1, OPTAB_LIB_WIDEN
);
3207 if (sign
&& GET_MODE (tgt
) != HImode
)
3209 addr
= gen_lowpart (HImode
, addr
);
3210 emit_insn (gen_extend_insn (tgt
, addr
, GET_MODE (tgt
), HImode
, 0));
3214 if (GET_MODE (tgt
) != DImode
)
3215 addr
= gen_lowpart (GET_MODE (tgt
), addr
);
3216 emit_move_insn (tgt
, addr
);
3221 meml
= gen_reg_rtx (DImode
);
3222 memh
= gen_reg_rtx (DImode
);
3223 addr
= gen_reg_rtx (DImode
);
3224 extl
= gen_reg_rtx (DImode
);
3225 exth
= gen_reg_rtx (DImode
);
3227 mema
= XEXP (mem
, 0);
3228 if (GET_CODE (mema
) == LO_SUM
)
3229 mema
= force_reg (Pmode
, mema
);
3231 /* AND addresses cannot be in any alias set, since they may implicitly
3232 alias surrounding code. Ideally we'd have some alias set that
3233 covered all types except those with alignment 8 or higher. */
3235 tmp
= change_address (mem
, DImode
,
3236 gen_rtx_AND (DImode
,
3237 plus_constant (mema
, ofs
),
3239 set_mem_alias_set (tmp
, 0);
3240 emit_move_insn (meml
, tmp
);
3242 tmp
= change_address (mem
, DImode
,
3243 gen_rtx_AND (DImode
,
3244 plus_constant (mema
, ofs
+ size
- 1),
3246 set_mem_alias_set (tmp
, 0);
3247 emit_move_insn (memh
, tmp
);
3249 if (sign
&& size
== 2)
3251 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3253 emit_insn (gen_extql (extl
, meml
, addr
));
3254 emit_insn (gen_extqh (exth
, memh
, addr
));
3256 /* We must use tgt here for the target. Alpha-vms port fails if we use
3257 addr for the target, because addr is marked as a pointer and combine
3258 knows that pointers are always sign-extended 32-bit values. */
3259 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3260 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3261 addr
, 1, OPTAB_WIDEN
);
3265 emit_move_insn (addr
, plus_constant (mema
, ofs
));
3266 emit_insn (gen_extxl (extl
, meml
, GEN_INT (size
*8), addr
));
3270 emit_insn (gen_extwh (exth
, memh
, addr
));
3274 emit_insn (gen_extlh (exth
, memh
, addr
));
3278 emit_insn (gen_extqh (exth
, memh
, addr
));
3285 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
3286 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
3291 emit_move_insn (tgt
, gen_lowpart (GET_MODE (tgt
), addr
));
3294 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3297 alpha_expand_unaligned_store (rtx dst
, rtx src
,
3298 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
3300 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
3302 if (TARGET_BWX
&& size
== 2)
3304 if (src
!= const0_rtx
)
3306 dstl
= gen_lowpart (QImode
, src
);
3307 dsth
= expand_simple_binop (DImode
, LSHIFTRT
, src
, GEN_INT (8),
3308 NULL
, 1, OPTAB_LIB_WIDEN
);
3309 dsth
= gen_lowpart (QImode
, dsth
);
3312 dstl
= dsth
= const0_rtx
;
3314 meml
= adjust_address (dst
, QImode
, ofs
);
3315 memh
= adjust_address (dst
, QImode
, ofs
+1);
3317 emit_move_insn (meml
, dstl
);
3318 emit_move_insn (memh
, dsth
);
3322 dstl
= gen_reg_rtx (DImode
);
3323 dsth
= gen_reg_rtx (DImode
);
3324 insl
= gen_reg_rtx (DImode
);
3325 insh
= gen_reg_rtx (DImode
);
3327 dsta
= XEXP (dst
, 0);
3328 if (GET_CODE (dsta
) == LO_SUM
)
3329 dsta
= force_reg (Pmode
, dsta
);
3331 /* AND addresses cannot be in any alias set, since they may implicitly
3332 alias surrounding code. Ideally we'd have some alias set that
3333 covered all types except those with alignment 8 or higher. */
3335 meml
= change_address (dst
, DImode
,
3336 gen_rtx_AND (DImode
,
3337 plus_constant (dsta
, ofs
),
3339 set_mem_alias_set (meml
, 0);
3341 memh
= change_address (dst
, DImode
,
3342 gen_rtx_AND (DImode
,
3343 plus_constant (dsta
, ofs
+ size
- 1),
3345 set_mem_alias_set (memh
, 0);
3347 emit_move_insn (dsth
, memh
);
3348 emit_move_insn (dstl
, meml
);
3350 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
3352 if (src
!= CONST0_RTX (GET_MODE (src
)))
3354 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
3355 GEN_INT (size
*8), addr
));
3360 emit_insn (gen_inswl (insl
, gen_lowpart (HImode
, src
), addr
));
3363 emit_insn (gen_insll (insl
, gen_lowpart (SImode
, src
), addr
));
3366 emit_insn (gen_insql (insl
, gen_lowpart (DImode
, src
), addr
));
3373 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
3378 emit_insn (gen_mskwl (dstl
, dstl
, addr
));
3381 emit_insn (gen_mskll (dstl
, dstl
, addr
));
3384 emit_insn (gen_mskql (dstl
, dstl
, addr
));
3390 if (src
!= CONST0_RTX (GET_MODE (src
)))
3392 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
3393 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
3396 /* Must store high before low for degenerate case of aligned. */
3397 emit_move_insn (memh
, dsth
);
3398 emit_move_insn (meml
, dstl
);
3401 /* The block move code tries to maximize speed by separating loads and
3402 stores at the expense of register pressure: we load all of the data
3403 before we store it back out. There are two secondary effects worth
3404 mentioning, that this speeds copying to/from aligned and unaligned
3405 buffers, and that it makes the code significantly easier to write. */
3407 #define MAX_MOVE_WORDS 8
3409 /* Load an integral number of consecutive unaligned quadwords. */
3412 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
3413 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3415 rtx
const im8
= GEN_INT (-8);
3416 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
3417 rtx sreg
, areg
, tmp
, smema
;
3420 smema
= XEXP (smem
, 0);
3421 if (GET_CODE (smema
) == LO_SUM
)
3422 smema
= force_reg (Pmode
, smema
);
3424 /* Generate all the tmp registers we need. */
3425 for (i
= 0; i
< words
; ++i
)
3427 data_regs
[i
] = out_regs
[i
];
3428 ext_tmps
[i
] = gen_reg_rtx (DImode
);
3430 data_regs
[words
] = gen_reg_rtx (DImode
);
3433 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
3435 /* Load up all of the source data. */
3436 for (i
= 0; i
< words
; ++i
)
3438 tmp
= change_address (smem
, DImode
,
3439 gen_rtx_AND (DImode
,
3440 plus_constant (smema
, 8*i
),
3442 set_mem_alias_set (tmp
, 0);
3443 emit_move_insn (data_regs
[i
], tmp
);
3446 tmp
= change_address (smem
, DImode
,
3447 gen_rtx_AND (DImode
,
3448 plus_constant (smema
, 8*words
- 1),
3450 set_mem_alias_set (tmp
, 0);
3451 emit_move_insn (data_regs
[words
], tmp
);
3453 /* Extract the half-word fragments. Unfortunately DEC decided to make
3454 extxh with offset zero a noop instead of zeroing the register, so
3455 we must take care of that edge condition ourselves with cmov. */
3457 sreg
= copy_addr_to_reg (smema
);
3458 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
3460 for (i
= 0; i
< words
; ++i
)
3462 emit_insn (gen_extql (data_regs
[i
], data_regs
[i
], sreg
));
3463 emit_insn (gen_extqh (ext_tmps
[i
], data_regs
[i
+1], sreg
));
3464 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
3465 gen_rtx_IF_THEN_ELSE (DImode
,
3466 gen_rtx_EQ (DImode
, areg
,
3468 const0_rtx
, ext_tmps
[i
])));
3471 /* Merge the half-words into whole words. */
3472 for (i
= 0; i
< words
; ++i
)
3474 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3475 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
3479 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
3480 may be NULL to store zeros. */
3483 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
3484 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3486 rtx
const im8
= GEN_INT (-8);
3487 rtx ins_tmps
[MAX_MOVE_WORDS
];
3488 rtx st_tmp_1
, st_tmp_2
, dreg
;
3489 rtx st_addr_1
, st_addr_2
, dmema
;
3492 dmema
= XEXP (dmem
, 0);
3493 if (GET_CODE (dmema
) == LO_SUM
)
3494 dmema
= force_reg (Pmode
, dmema
);
3496 /* Generate all the tmp registers we need. */
3497 if (data_regs
!= NULL
)
3498 for (i
= 0; i
< words
; ++i
)
3499 ins_tmps
[i
] = gen_reg_rtx(DImode
);
3500 st_tmp_1
= gen_reg_rtx(DImode
);
3501 st_tmp_2
= gen_reg_rtx(DImode
);
3504 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
3506 st_addr_2
= change_address (dmem
, DImode
,
3507 gen_rtx_AND (DImode
,
3508 plus_constant (dmema
, words
*8 - 1),
3510 set_mem_alias_set (st_addr_2
, 0);
3512 st_addr_1
= change_address (dmem
, DImode
,
3513 gen_rtx_AND (DImode
, dmema
, im8
));
3514 set_mem_alias_set (st_addr_1
, 0);
3516 /* Load up the destination end bits. */
3517 emit_move_insn (st_tmp_2
, st_addr_2
);
3518 emit_move_insn (st_tmp_1
, st_addr_1
);
3520 /* Shift the input data into place. */
3521 dreg
= copy_addr_to_reg (dmema
);
3522 if (data_regs
!= NULL
)
3524 for (i
= words
-1; i
>= 0; --i
)
3526 emit_insn (gen_insqh (ins_tmps
[i
], data_regs
[i
], dreg
));
3527 emit_insn (gen_insql (data_regs
[i
], data_regs
[i
], dreg
));
3529 for (i
= words
-1; i
> 0; --i
)
3531 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3532 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
3537 /* Split and merge the ends with the destination data. */
3538 emit_insn (gen_mskqh (st_tmp_2
, st_tmp_2
, dreg
));
3539 emit_insn (gen_mskql (st_tmp_1
, st_tmp_1
, dreg
));
3541 if (data_regs
!= NULL
)
3543 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
3544 st_tmp_2
, 1, OPTAB_WIDEN
);
3545 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
3546 st_tmp_1
, 1, OPTAB_WIDEN
);
3550 emit_move_insn (st_addr_2
, st_tmp_2
);
3551 for (i
= words
-1; i
> 0; --i
)
3553 rtx tmp
= change_address (dmem
, DImode
,
3554 gen_rtx_AND (DImode
,
3555 plus_constant (dmema
, i
*8),
3557 set_mem_alias_set (tmp
, 0);
3558 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
3560 emit_move_insn (st_addr_1
, st_tmp_1
);
3564 /* Expand string/block move operations.
3566 operands[0] is the pointer to the destination.
3567 operands[1] is the pointer to the source.
3568 operands[2] is the number of bytes to move.
3569 operands[3] is the alignment. */
3572 alpha_expand_block_move (rtx operands
[])
3574 rtx bytes_rtx
= operands
[2];
3575 rtx align_rtx
= operands
[3];
3576 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
3577 HOST_WIDE_INT bytes
= orig_bytes
;
3578 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
3579 HOST_WIDE_INT dst_align
= src_align
;
3580 rtx orig_src
= operands
[1];
3581 rtx orig_dst
= operands
[0];
3582 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
3584 unsigned int i
, words
, ofs
, nregs
= 0;
3586 if (orig_bytes
<= 0)
3588 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
3591 /* Look for additional alignment information from recorded register info. */
3593 tmp
= XEXP (orig_src
, 0);
3595 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3596 else if (GET_CODE (tmp
) == PLUS
3597 && REG_P (XEXP (tmp
, 0))
3598 && CONST_INT_P (XEXP (tmp
, 1)))
3600 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3601 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3605 if (a
>= 64 && c
% 8 == 0)
3607 else if (a
>= 32 && c
% 4 == 0)
3609 else if (a
>= 16 && c
% 2 == 0)
3614 tmp
= XEXP (orig_dst
, 0);
3616 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3617 else if (GET_CODE (tmp
) == PLUS
3618 && REG_P (XEXP (tmp
, 0))
3619 && CONST_INT_P (XEXP (tmp
, 1)))
3621 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3622 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3626 if (a
>= 64 && c
% 8 == 0)
3628 else if (a
>= 32 && c
% 4 == 0)
3630 else if (a
>= 16 && c
% 2 == 0)
3636 if (src_align
>= 64 && bytes
>= 8)
3640 for (i
= 0; i
< words
; ++i
)
3641 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3643 for (i
= 0; i
< words
; ++i
)
3644 emit_move_insn (data_regs
[nregs
+ i
],
3645 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
3652 if (src_align
>= 32 && bytes
>= 4)
3656 for (i
= 0; i
< words
; ++i
)
3657 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
3659 for (i
= 0; i
< words
; ++i
)
3660 emit_move_insn (data_regs
[nregs
+ i
],
3661 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
3672 for (i
= 0; i
< words
+1; ++i
)
3673 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3675 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
3683 if (! TARGET_BWX
&& bytes
>= 4)
3685 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
3686 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
3693 if (src_align
>= 16)
3696 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3697 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
3700 } while (bytes
>= 2);
3702 else if (! TARGET_BWX
)
3704 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3705 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
3713 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
3714 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
3719 gcc_assert (nregs
<= ARRAY_SIZE (data_regs
));
3721 /* Now save it back out again. */
3725 /* Write out the data in whatever chunks reading the source allowed. */
3726 if (dst_align
>= 64)
3728 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3730 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
3737 if (dst_align
>= 32)
3739 /* If the source has remaining DImode regs, write them out in
3741 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3743 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
3744 NULL_RTX
, 1, OPTAB_WIDEN
);
3746 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
3747 gen_lowpart (SImode
, data_regs
[i
]));
3748 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
3749 gen_lowpart (SImode
, tmp
));
3754 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
3756 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
3763 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3765 /* Write out a remaining block of words using unaligned methods. */
3767 for (words
= 1; i
+ words
< nregs
; words
++)
3768 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
3772 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
3774 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
3781 /* Due to the above, this won't be aligned. */
3782 /* ??? If we have more than one of these, consider constructing full
3783 words in registers and using alpha_expand_unaligned_store_words. */
3784 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
3786 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
3791 if (dst_align
>= 16)
3792 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
3794 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
3799 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
3801 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
3806 /* The remainder must be byte copies. */
3809 gcc_assert (GET_MODE (data_regs
[i
]) == QImode
);
3810 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
3819 alpha_expand_block_clear (rtx operands
[])
3821 rtx bytes_rtx
= operands
[1];
3822 rtx align_rtx
= operands
[3];
3823 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
3824 HOST_WIDE_INT bytes
= orig_bytes
;
3825 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
3826 HOST_WIDE_INT alignofs
= 0;
3827 rtx orig_dst
= operands
[0];
3829 int i
, words
, ofs
= 0;
3831 if (orig_bytes
<= 0)
3833 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
3836 /* Look for stricter alignment. */
3837 tmp
= XEXP (orig_dst
, 0);
3839 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3840 else if (GET_CODE (tmp
) == PLUS
3841 && REG_P (XEXP (tmp
, 0))
3842 && CONST_INT_P (XEXP (tmp
, 1)))
3844 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3845 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3850 align
= a
, alignofs
= 8 - c
% 8;
3852 align
= a
, alignofs
= 4 - c
% 4;
3854 align
= a
, alignofs
= 2 - c
% 2;
3858 /* Handle an unaligned prefix first. */
3862 #if HOST_BITS_PER_WIDE_INT >= 64
3863 /* Given that alignofs is bounded by align, the only time BWX could
3864 generate three stores is for a 7 byte fill. Prefer two individual
3865 stores over a load/mask/store sequence. */
3866 if ((!TARGET_BWX
|| alignofs
== 7)
3868 && !(alignofs
== 4 && bytes
>= 4))
3870 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
3871 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
3875 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
3876 set_mem_alias_set (mem
, 0);
3878 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
3879 if (bytes
< alignofs
)
3881 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
3892 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
3893 NULL_RTX
, 1, OPTAB_WIDEN
);
3895 emit_move_insn (mem
, tmp
);
3899 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
3901 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
3906 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
3908 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
3913 if (alignofs
== 4 && bytes
>= 4)
3915 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
3921 /* If we've not used the extra lead alignment information by now,
3922 we won't be able to. Downgrade align to match what's left over. */
3925 alignofs
= alignofs
& -alignofs
;
3926 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
3930 /* Handle a block of contiguous long-words. */
3932 if (align
>= 64 && bytes
>= 8)
3936 for (i
= 0; i
< words
; ++i
)
3937 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
3944 /* If the block is large and appropriately aligned, emit a single
3945 store followed by a sequence of stq_u insns. */
3947 if (align
>= 32 && bytes
> 16)
3951 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
3955 orig_dsta
= XEXP (orig_dst
, 0);
3956 if (GET_CODE (orig_dsta
) == LO_SUM
)
3957 orig_dsta
= force_reg (Pmode
, orig_dsta
);
3960 for (i
= 0; i
< words
; ++i
)
3963 = change_address (orig_dst
, DImode
,
3964 gen_rtx_AND (DImode
,
3965 plus_constant (orig_dsta
, ofs
+ i
*8),
3967 set_mem_alias_set (mem
, 0);
3968 emit_move_insn (mem
, const0_rtx
);
3971 /* Depending on the alignment, the first stq_u may have overlapped
3972 with the initial stl, which means that the last stq_u didn't
3973 write as much as it would appear. Leave those questionable bytes
3975 bytes
-= words
* 8 - 4;
3976 ofs
+= words
* 8 - 4;
3979 /* Handle a smaller block of aligned words. */
3981 if ((align
>= 64 && bytes
== 4)
3982 || (align
== 32 && bytes
>= 4))
3986 for (i
= 0; i
< words
; ++i
)
3987 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
3994 /* An unaligned block uses stq_u stores for as many as possible. */
4000 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4006 /* Next clean up any trailing pieces. */
4008 #if HOST_BITS_PER_WIDE_INT >= 64
4009 /* Count the number of bits in BYTES for which aligned stores could
4012 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4016 /* If we have appropriate alignment (and it wouldn't take too many
4017 instructions otherwise), mask out the bytes we need. */
4018 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4025 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4026 set_mem_alias_set (mem
, 0);
4028 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4030 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4031 NULL_RTX
, 1, OPTAB_WIDEN
);
4033 emit_move_insn (mem
, tmp
);
4036 else if (align
>= 32 && bytes
< 4)
4041 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4042 set_mem_alias_set (mem
, 0);
4044 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4046 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4047 NULL_RTX
, 1, OPTAB_WIDEN
);
4049 emit_move_insn (mem
, tmp
);
4055 if (!TARGET_BWX
&& bytes
>= 4)
4057 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4067 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4071 } while (bytes
>= 2);
4073 else if (! TARGET_BWX
)
4075 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4083 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4091 /* Returns a mask so that zap(x, value) == x & mask. */
4094 alpha_expand_zap_mask (HOST_WIDE_INT value
)
4099 if (HOST_BITS_PER_WIDE_INT
>= 64)
4101 HOST_WIDE_INT mask
= 0;
4103 for (i
= 7; i
>= 0; --i
)
4106 if (!((value
>> i
) & 1))
4110 result
= gen_int_mode (mask
, DImode
);
4114 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
4116 gcc_assert (HOST_BITS_PER_WIDE_INT
== 32);
4118 for (i
= 7; i
>= 4; --i
)
4121 if (!((value
>> i
) & 1))
4125 for (i
= 3; i
>= 0; --i
)
4128 if (!((value
>> i
) & 1))
4132 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
4139 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
4140 enum machine_mode mode
,
4141 rtx op0
, rtx op1
, rtx op2
)
4143 op0
= gen_lowpart (mode
, op0
);
4145 if (op1
== const0_rtx
)
4146 op1
= CONST0_RTX (mode
);
4148 op1
= gen_lowpart (mode
, op1
);
4150 if (op2
== const0_rtx
)
4151 op2
= CONST0_RTX (mode
);
4153 op2
= gen_lowpart (mode
, op2
);
4155 emit_insn ((*gen
) (op0
, op1
, op2
));
4158 /* A subroutine of the atomic operation splitters. Jump to LABEL if
4159 COND is true. Mark the jump as unlikely to be taken. */
4162 emit_unlikely_jump (rtx cond
, rtx label
)
4164 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
4167 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
4168 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
4169 add_reg_note (x
, REG_BR_PROB
, very_unlikely
);
4172 /* A subroutine of the atomic operation splitters. Emit a load-locked
4173 instruction in MODE. */
4176 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
4178 rtx (*fn
) (rtx
, rtx
) = NULL
;
4180 fn
= gen_load_locked_si
;
4181 else if (mode
== DImode
)
4182 fn
= gen_load_locked_di
;
4183 emit_insn (fn (reg
, mem
));
4186 /* A subroutine of the atomic operation splitters. Emit a store-conditional
4187 instruction in MODE. */
4190 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
4192 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
4194 fn
= gen_store_conditional_si
;
4195 else if (mode
== DImode
)
4196 fn
= gen_store_conditional_di
;
4197 emit_insn (fn (res
, mem
, val
));
4200 /* Subroutines of the atomic operation splitters. Emit barriers
4201 as needed for the memory MODEL. */
4204 alpha_pre_atomic_barrier (enum memmodel model
)
4208 case MEMMODEL_RELAXED
:
4209 case MEMMODEL_CONSUME
:
4210 case MEMMODEL_ACQUIRE
:
4212 case MEMMODEL_RELEASE
:
4213 case MEMMODEL_ACQ_REL
:
4214 case MEMMODEL_SEQ_CST
:
4215 emit_insn (gen_memory_barrier ());
4223 alpha_post_atomic_barrier (enum memmodel model
)
4227 case MEMMODEL_RELAXED
:
4228 case MEMMODEL_CONSUME
:
4229 case MEMMODEL_RELEASE
:
4231 case MEMMODEL_ACQUIRE
:
4232 case MEMMODEL_ACQ_REL
:
4233 case MEMMODEL_SEQ_CST
:
4234 emit_insn (gen_memory_barrier ());
4241 /* A subroutine of the atomic operation splitters. Emit an insxl
4242 instruction in MODE. */
4245 emit_insxl (enum machine_mode mode
, rtx op1
, rtx op2
)
4247 rtx ret
= gen_reg_rtx (DImode
);
4248 rtx (*fn
) (rtx
, rtx
, rtx
);
4268 op1
= force_reg (mode
, op1
);
4269 emit_insn (fn (ret
, op1
, op2
));
4274 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
4275 to perform. MEM is the memory on which to operate. VAL is the second
4276 operand of the binary operator. BEFORE and AFTER are optional locations to
4277 return the value of MEM either before of after the operation. SCRATCH is
4278 a scratch register. */
4281 alpha_split_atomic_op (enum rtx_code code
, rtx mem
, rtx val
, rtx before
,
4282 rtx after
, rtx scratch
, enum memmodel model
)
4284 enum machine_mode mode
= GET_MODE (mem
);
4285 rtx label
, x
, cond
= gen_rtx_REG (DImode
, REGNO (scratch
));
4287 alpha_pre_atomic_barrier (model
);
4289 label
= gen_label_rtx ();
4291 label
= gen_rtx_LABEL_REF (DImode
, label
);
4295 emit_load_locked (mode
, before
, mem
);
4299 x
= gen_rtx_AND (mode
, before
, val
);
4300 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
4302 x
= gen_rtx_NOT (mode
, val
);
4305 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
4307 emit_insn (gen_rtx_SET (VOIDmode
, after
, copy_rtx (x
)));
4308 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, x
));
4310 emit_store_conditional (mode
, cond
, mem
, scratch
);
4312 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4313 emit_unlikely_jump (x
, label
);
4315 alpha_post_atomic_barrier (model
);
4318 /* Expand a compare and swap operation. */
4321 alpha_split_compare_and_swap (rtx operands
[])
4323 rtx cond
, retval
, mem
, oldval
, newval
;
4325 enum memmodel mod_s
, mod_f
;
4326 enum machine_mode mode
;
4327 rtx label1
, label2
, x
;
4330 retval
= operands
[1];
4332 oldval
= operands
[3];
4333 newval
= operands
[4];
4334 is_weak
= (operands
[5] != const0_rtx
);
4335 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
4336 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
4337 mode
= GET_MODE (mem
);
4339 alpha_pre_atomic_barrier (mod_s
);
4344 label1
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4345 emit_label (XEXP (label1
, 0));
4347 label2
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4349 emit_load_locked (mode
, retval
, mem
);
4351 x
= gen_lowpart (DImode
, retval
);
4352 if (oldval
== const0_rtx
)
4354 emit_move_insn (cond
, const0_rtx
);
4355 x
= gen_rtx_NE (DImode
, x
, const0_rtx
);
4359 x
= gen_rtx_EQ (DImode
, x
, oldval
);
4360 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
4361 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4363 emit_unlikely_jump (x
, label2
);
4365 emit_move_insn (cond
, newval
);
4366 emit_store_conditional (mode
, cond
, mem
, gen_lowpart (mode
, cond
));
4370 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4371 emit_unlikely_jump (x
, label1
);
4374 if (mod_f
!= MEMMODEL_RELAXED
)
4375 emit_label (XEXP (label2
, 0));
4377 alpha_post_atomic_barrier (mod_s
);
4379 if (mod_f
== MEMMODEL_RELAXED
)
4380 emit_label (XEXP (label2
, 0));
4384 alpha_expand_compare_and_swap_12 (rtx operands
[])
4386 rtx cond
, dst
, mem
, oldval
, newval
, is_weak
, mod_s
, mod_f
;
4387 enum machine_mode mode
;
4388 rtx addr
, align
, wdst
;
4389 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
4394 oldval
= operands
[3];
4395 newval
= operands
[4];
4396 is_weak
= operands
[5];
4397 mod_s
= operands
[6];
4398 mod_f
= operands
[7];
4399 mode
= GET_MODE (mem
);
4401 /* We forced the address into a register via mem_noofs_operand. */
4402 addr
= XEXP (mem
, 0);
4403 gcc_assert (register_operand (addr
, DImode
));
4405 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-8),
4406 NULL_RTX
, 1, OPTAB_DIRECT
);
4408 oldval
= convert_modes (DImode
, mode
, oldval
, 1);
4410 if (newval
!= const0_rtx
)
4411 newval
= emit_insxl (mode
, newval
, addr
);
4413 wdst
= gen_reg_rtx (DImode
);
4415 gen
= gen_atomic_compare_and_swapqi_1
;
4417 gen
= gen_atomic_compare_and_swaphi_1
;
4418 emit_insn (gen (cond
, wdst
, mem
, oldval
, newval
, align
,
4419 is_weak
, mod_s
, mod_f
));
4421 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
4425 alpha_split_compare_and_swap_12 (rtx operands
[])
4427 rtx cond
, dest
, orig_mem
, oldval
, newval
, align
, scratch
;
4428 enum machine_mode mode
;
4430 enum memmodel mod_s
, mod_f
;
4431 rtx label1
, label2
, mem
, addr
, width
, mask
, x
;
4435 orig_mem
= operands
[2];
4436 oldval
= operands
[3];
4437 newval
= operands
[4];
4438 align
= operands
[5];
4439 is_weak
= (operands
[6] != const0_rtx
);
4440 mod_s
= (enum memmodel
) INTVAL (operands
[7]);
4441 mod_f
= (enum memmodel
) INTVAL (operands
[8]);
4442 scratch
= operands
[9];
4443 mode
= GET_MODE (orig_mem
);
4444 addr
= XEXP (orig_mem
, 0);
4446 mem
= gen_rtx_MEM (DImode
, align
);
4447 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
4448 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
4449 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
4451 alpha_pre_atomic_barrier (mod_s
);
4456 label1
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4457 emit_label (XEXP (label1
, 0));
4459 label2
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4461 emit_load_locked (DImode
, scratch
, mem
);
4463 width
= GEN_INT (GET_MODE_BITSIZE (mode
));
4464 mask
= GEN_INT (mode
== QImode
? 0xff : 0xffff);
4465 emit_insn (gen_extxl (dest
, scratch
, width
, addr
));
4467 if (oldval
== const0_rtx
)
4469 emit_move_insn (cond
, const0_rtx
);
4470 x
= gen_rtx_NE (DImode
, dest
, const0_rtx
);
4474 x
= gen_rtx_EQ (DImode
, dest
, oldval
);
4475 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
4476 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4478 emit_unlikely_jump (x
, label2
);
4480 emit_insn (gen_mskxl (cond
, scratch
, mask
, addr
));
4482 if (newval
!= const0_rtx
)
4483 emit_insn (gen_iordi3 (cond
, cond
, newval
));
4485 emit_store_conditional (DImode
, cond
, mem
, cond
);
4489 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4490 emit_unlikely_jump (x
, label1
);
4493 if (mod_f
!= MEMMODEL_RELAXED
)
4494 emit_label (XEXP (label2
, 0));
4496 alpha_post_atomic_barrier (mod_s
);
4498 if (mod_f
== MEMMODEL_RELAXED
)
4499 emit_label (XEXP (label2
, 0));
4502 /* Expand an atomic exchange operation. */
4505 alpha_split_atomic_exchange (rtx operands
[])
4507 rtx retval
, mem
, val
, scratch
;
4508 enum memmodel model
;
4509 enum machine_mode mode
;
4512 retval
= operands
[0];
4515 model
= (enum memmodel
) INTVAL (operands
[3]);
4516 scratch
= operands
[4];
4517 mode
= GET_MODE (mem
);
4518 cond
= gen_lowpart (DImode
, scratch
);
4520 alpha_pre_atomic_barrier (model
);
4522 label
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4523 emit_label (XEXP (label
, 0));
4525 emit_load_locked (mode
, retval
, mem
);
4526 emit_move_insn (scratch
, val
);
4527 emit_store_conditional (mode
, cond
, mem
, scratch
);
4529 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4530 emit_unlikely_jump (x
, label
);
4532 alpha_post_atomic_barrier (model
);
4536 alpha_expand_atomic_exchange_12 (rtx operands
[])
4538 rtx dst
, mem
, val
, model
;
4539 enum machine_mode mode
;
4540 rtx addr
, align
, wdst
;
4541 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
, rtx
);
4546 model
= operands
[3];
4547 mode
= GET_MODE (mem
);
4549 /* We forced the address into a register via mem_noofs_operand. */
4550 addr
= XEXP (mem
, 0);
4551 gcc_assert (register_operand (addr
, DImode
));
4553 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-8),
4554 NULL_RTX
, 1, OPTAB_DIRECT
);
4556 /* Insert val into the correct byte location within the word. */
4557 if (val
!= const0_rtx
)
4558 val
= emit_insxl (mode
, val
, addr
);
4560 wdst
= gen_reg_rtx (DImode
);
4562 gen
= gen_atomic_exchangeqi_1
;
4564 gen
= gen_atomic_exchangehi_1
;
4565 emit_insn (gen (wdst
, mem
, val
, align
, model
));
4567 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
4571 alpha_split_atomic_exchange_12 (rtx operands
[])
4573 rtx dest
, orig_mem
, addr
, val
, align
, scratch
;
4574 rtx label
, mem
, width
, mask
, x
;
4575 enum machine_mode mode
;
4576 enum memmodel model
;
4579 orig_mem
= operands
[1];
4581 align
= operands
[3];
4582 model
= (enum memmodel
) INTVAL (operands
[4]);
4583 scratch
= operands
[5];
4584 mode
= GET_MODE (orig_mem
);
4585 addr
= XEXP (orig_mem
, 0);
4587 mem
= gen_rtx_MEM (DImode
, align
);
4588 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
4589 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
4590 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
4592 alpha_pre_atomic_barrier (model
);
4594 label
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4595 emit_label (XEXP (label
, 0));
4597 emit_load_locked (DImode
, scratch
, mem
);
4599 width
= GEN_INT (GET_MODE_BITSIZE (mode
));
4600 mask
= GEN_INT (mode
== QImode
? 0xff : 0xffff);
4601 emit_insn (gen_extxl (dest
, scratch
, width
, addr
));
4602 emit_insn (gen_mskxl (scratch
, scratch
, mask
, addr
));
4603 if (val
!= const0_rtx
)
4604 emit_insn (gen_iordi3 (scratch
, scratch
, val
));
4606 emit_store_conditional (DImode
, scratch
, mem
, scratch
);
4608 x
= gen_rtx_EQ (DImode
, scratch
, const0_rtx
);
4609 emit_unlikely_jump (x
, label
);
4611 alpha_post_atomic_barrier (model
);
4614 /* Adjust the cost of a scheduling dependency. Return the new cost of
4615 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4618 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
4620 enum attr_type dep_insn_type
;
4622 /* If the dependence is an anti-dependence, there is no cost. For an
4623 output dependence, there is sometimes a cost, but it doesn't seem
4624 worth handling those few cases. */
4625 if (REG_NOTE_KIND (link
) != 0)
4628 /* If we can't recognize the insns, we can't really do anything. */
4629 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
4632 dep_insn_type
= get_attr_type (dep_insn
);
4634 /* Bring in the user-defined memory latency. */
4635 if (dep_insn_type
== TYPE_ILD
4636 || dep_insn_type
== TYPE_FLD
4637 || dep_insn_type
== TYPE_LDSYM
)
4638 cost
+= alpha_memory_latency
-1;
4640 /* Everything else handled in DFA bypasses now. */
4645 /* The number of instructions that can be issued per cycle. */
4648 alpha_issue_rate (void)
4650 return (alpha_tune
== PROCESSOR_EV4
? 2 : 4);
4653 /* How many alternative schedules to try. This should be as wide as the
4654 scheduling freedom in the DFA, but no wider. Making this value too
4655 large results extra work for the scheduler.
4657 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
4658 alternative schedules. For EV5, we can choose between E0/E1 and
4659 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
4662 alpha_multipass_dfa_lookahead (void)
4664 return (alpha_tune
== PROCESSOR_EV6
? 4 : 2);
4667 /* Machine-specific function data. */
4669 struct GTY(()) alpha_links
;
4671 struct GTY(()) machine_function
4674 const char *some_ld_name
;
4676 /* For flag_reorder_blocks_and_partition. */
4679 /* For VMS condition handlers. */
4680 bool uses_condition_handler
;
4682 /* Linkage entries. */
4683 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
4687 /* How to allocate a 'struct machine_function'. */
4689 static struct machine_function
*
4690 alpha_init_machine_status (void)
4692 return ggc_alloc_cleared_machine_function ();
4695 /* Support for frame based VMS condition handlers. */
4697 /* A VMS condition handler may be established for a function with a call to
4698 __builtin_establish_vms_condition_handler, and cancelled with a call to
4699 __builtin_revert_vms_condition_handler.
4701 The VMS Condition Handling Facility knows about the existence of a handler
4702 from the procedure descriptor .handler field. As the VMS native compilers,
4703 we store the user specified handler's address at a fixed location in the
4704 stack frame and point the procedure descriptor at a common wrapper which
4705 fetches the real handler's address and issues an indirect call.
4707 The indirection wrapper is "__gcc_shell_handler", provided by libgcc.
4709 We force the procedure kind to PT_STACK, and the fixed frame location is
4710 fp+8, just before the register save area. We use the handler_data field in
4711 the procedure descriptor to state the fp offset at which the installed
4712 handler address can be found. */
4714 #define VMS_COND_HANDLER_FP_OFFSET 8
4716 /* Expand code to store the currently installed user VMS condition handler
4717 into TARGET and install HANDLER as the new condition handler. */
4720 alpha_expand_builtin_establish_vms_condition_handler (rtx target
, rtx handler
)
4722 rtx handler_slot_address
4723 = plus_constant (hard_frame_pointer_rtx
, VMS_COND_HANDLER_FP_OFFSET
);
4726 = gen_rtx_MEM (DImode
, handler_slot_address
);
4728 emit_move_insn (target
, handler_slot
);
4729 emit_move_insn (handler_slot
, handler
);
4731 /* Notify the start/prologue/epilogue emitters that the condition handler
4732 slot is needed. In addition to reserving the slot space, this will force
4733 the procedure kind to PT_STACK so ensure that the hard_frame_pointer_rtx
4734 use above is correct. */
4735 cfun
->machine
->uses_condition_handler
= true;
4738 /* Expand code to store the current VMS condition handler into TARGET and
4742 alpha_expand_builtin_revert_vms_condition_handler (rtx target
)
4744 /* We implement this by establishing a null condition handler, with the tiny
4745 side effect of setting uses_condition_handler. This is a little bit
4746 pessimistic if no actual builtin_establish call is ever issued, which is
4747 not a real problem and expected never to happen anyway. */
4749 alpha_expand_builtin_establish_vms_condition_handler (target
, const0_rtx
);
4752 /* Functions to save and restore alpha_return_addr_rtx. */
4754 /* Start the ball rolling with RETURN_ADDR_RTX. */
4757 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
4762 return get_hard_reg_initial_val (Pmode
, REG_RA
);
4765 /* Return or create a memory slot containing the gp value for the current
4766 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4769 alpha_gp_save_rtx (void)
4771 rtx seq
, m
= cfun
->machine
->gp_save_rtx
;
4777 m
= assign_stack_local (DImode
, UNITS_PER_WORD
, BITS_PER_WORD
);
4778 m
= validize_mem (m
);
4779 emit_move_insn (m
, pic_offset_table_rtx
);
4784 /* We used to simply emit the sequence after entry_of_function.
4785 However this breaks the CFG if the first instruction in the
4786 first block is not the NOTE_INSN_BASIC_BLOCK, for example a
4787 label. Emit the sequence properly on the edge. We are only
4788 invoked from dw2_build_landing_pads and finish_eh_generation
4789 will call commit_edge_insertions thanks to a kludge. */
4790 insert_insn_on_edge (seq
, single_succ_edge (ENTRY_BLOCK_PTR
));
4792 cfun
->machine
->gp_save_rtx
= m
;
4799 alpha_instantiate_decls (void)
4801 if (cfun
->machine
->gp_save_rtx
!= NULL_RTX
)
4802 instantiate_decl_rtl (cfun
->machine
->gp_save_rtx
);
4806 alpha_ra_ever_killed (void)
4810 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
4811 return (int)df_regs_ever_live_p (REG_RA
);
4813 push_topmost_sequence ();
4815 pop_topmost_sequence ();
4817 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
4821 /* Return the trap mode suffix applicable to the current
4822 instruction, or NULL. */
4825 get_trap_mode_suffix (void)
4827 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
4831 case TRAP_SUFFIX_NONE
:
4834 case TRAP_SUFFIX_SU
:
4835 if (alpha_fptm
>= ALPHA_FPTM_SU
)
4839 case TRAP_SUFFIX_SUI
:
4840 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
4844 case TRAP_SUFFIX_V_SV
:
4852 case ALPHA_FPTM_SUI
:
4858 case TRAP_SUFFIX_V_SV_SVI
:
4867 case ALPHA_FPTM_SUI
:
4874 case TRAP_SUFFIX_U_SU_SUI
:
4883 case ALPHA_FPTM_SUI
:
4896 /* Return the rounding mode suffix applicable to the current
4897 instruction, or NULL. */
4900 get_round_mode_suffix (void)
4902 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
4906 case ROUND_SUFFIX_NONE
:
4908 case ROUND_SUFFIX_NORMAL
:
4911 case ALPHA_FPRM_NORM
:
4913 case ALPHA_FPRM_MINF
:
4915 case ALPHA_FPRM_CHOP
:
4917 case ALPHA_FPRM_DYN
:
4924 case ROUND_SUFFIX_C
:
4933 /* Locate some local-dynamic symbol still in use by this function
4934 so that we can print its name in some movdi_er_tlsldm pattern. */
4937 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4941 if (GET_CODE (x
) == SYMBOL_REF
4942 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4944 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
4952 get_some_local_dynamic_name (void)
4956 if (cfun
->machine
->some_ld_name
)
4957 return cfun
->machine
->some_ld_name
;
4959 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4961 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
4962 return cfun
->machine
->some_ld_name
;
4967 /* Print an operand. Recognize special options, documented below. */
4970 print_operand (FILE *file
, rtx x
, int code
)
4977 /* Print the assembler name of the current function. */
4978 assemble_name (file
, alpha_fnname
);
4982 assemble_name (file
, get_some_local_dynamic_name ());
4987 const char *trap
= get_trap_mode_suffix ();
4988 const char *round
= get_round_mode_suffix ();
4991 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
4992 (trap
? trap
: ""), (round
? round
: ""));
4997 /* Generates single precision instruction suffix. */
4998 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5002 /* Generates double precision instruction suffix. */
5003 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5007 if (alpha_this_literal_sequence_number
== 0)
5008 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5009 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5013 if (alpha_this_gpdisp_sequence_number
== 0)
5014 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5015 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5019 if (GET_CODE (x
) == HIGH
)
5020 output_addr_const (file
, XEXP (x
, 0));
5022 output_operand_lossage ("invalid %%H value");
5029 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5031 x
= XVECEXP (x
, 0, 0);
5032 lituse
= "lituse_tlsgd";
5034 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5036 x
= XVECEXP (x
, 0, 0);
5037 lituse
= "lituse_tlsldm";
5039 else if (CONST_INT_P (x
))
5040 lituse
= "lituse_jsr";
5043 output_operand_lossage ("invalid %%J value");
5047 if (x
!= const0_rtx
)
5048 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5056 #ifdef HAVE_AS_JSRDIRECT_RELOCS
5057 lituse
= "lituse_jsrdirect";
5059 lituse
= "lituse_jsr";
5062 gcc_assert (INTVAL (x
) != 0);
5063 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5067 /* If this operand is the constant zero, write it as "$31". */
5069 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5070 else if (x
== CONST0_RTX (GET_MODE (x
)))
5071 fprintf (file
, "$31");
5073 output_operand_lossage ("invalid %%r value");
5077 /* Similar, but for floating-point. */
5079 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5080 else if (x
== CONST0_RTX (GET_MODE (x
)))
5081 fprintf (file
, "$f31");
5083 output_operand_lossage ("invalid %%R value");
5087 /* Write the 1's complement of a constant. */
5088 if (!CONST_INT_P (x
))
5089 output_operand_lossage ("invalid %%N value");
5091 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5095 /* Write 1 << C, for a constant C. */
5096 if (!CONST_INT_P (x
))
5097 output_operand_lossage ("invalid %%P value");
5099 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5103 /* Write the high-order 16 bits of a constant, sign-extended. */
5104 if (!CONST_INT_P (x
))
5105 output_operand_lossage ("invalid %%h value");
5107 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5111 /* Write the low-order 16 bits of a constant, sign-extended. */
5112 if (!CONST_INT_P (x
))
5113 output_operand_lossage ("invalid %%L value");
5115 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5116 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5120 /* Write mask for ZAP insn. */
5121 if (GET_CODE (x
) == CONST_DOUBLE
)
5123 HOST_WIDE_INT mask
= 0;
5124 HOST_WIDE_INT value
;
5126 value
= CONST_DOUBLE_LOW (x
);
5127 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5132 value
= CONST_DOUBLE_HIGH (x
);
5133 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5136 mask
|= (1 << (i
+ sizeof (int)));
5138 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5141 else if (CONST_INT_P (x
))
5143 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5145 for (i
= 0; i
< 8; i
++, value
>>= 8)
5149 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5152 output_operand_lossage ("invalid %%m value");
5156 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5157 if (!CONST_INT_P (x
)
5158 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5159 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5160 output_operand_lossage ("invalid %%M value");
5162 fprintf (file
, "%s",
5163 (INTVAL (x
) == 8 ? "b"
5164 : INTVAL (x
) == 16 ? "w"
5165 : INTVAL (x
) == 32 ? "l"
5170 /* Similar, except do it from the mask. */
5171 if (CONST_INT_P (x
))
5173 HOST_WIDE_INT value
= INTVAL (x
);
5180 if (value
== 0xffff)
5185 if (value
== 0xffffffff)
5196 else if (HOST_BITS_PER_WIDE_INT
== 32
5197 && GET_CODE (x
) == CONST_DOUBLE
5198 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5199 && CONST_DOUBLE_HIGH (x
) == 0)
5204 output_operand_lossage ("invalid %%U value");
5208 /* Write the constant value divided by 8. */
5209 if (!CONST_INT_P (x
)
5210 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5211 || (INTVAL (x
) & 7) != 0)
5212 output_operand_lossage ("invalid %%s value");
5214 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) / 8);
5218 /* Same, except compute (64 - c) / 8 */
5220 if (!CONST_INT_P (x
)
5221 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5222 && (INTVAL (x
) & 7) != 8)
5223 output_operand_lossage ("invalid %%s value");
5225 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5228 case 'C': case 'D': case 'c': case 'd':
5229 /* Write out comparison name. */
5231 enum rtx_code c
= GET_CODE (x
);
5233 if (!COMPARISON_P (x
))
5234 output_operand_lossage ("invalid %%C value");
5236 else if (code
== 'D')
5237 c
= reverse_condition (c
);
5238 else if (code
== 'c')
5239 c
= swap_condition (c
);
5240 else if (code
== 'd')
5241 c
= swap_condition (reverse_condition (c
));
5244 fprintf (file
, "ule");
5246 fprintf (file
, "ult");
5247 else if (c
== UNORDERED
)
5248 fprintf (file
, "un");
5250 fprintf (file
, "%s", GET_RTX_NAME (c
));
5255 /* Write the divide or modulus operator. */
5256 switch (GET_CODE (x
))
5259 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5262 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5265 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5268 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5271 output_operand_lossage ("invalid %%E value");
5277 /* Write "_u" for unaligned access. */
5278 if (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == AND
)
5279 fprintf (file
, "_u");
5284 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5286 output_address (XEXP (x
, 0));
5287 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5289 switch (XINT (XEXP (x
, 0), 1))
5293 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5296 output_operand_lossage ("unknown relocation unspec");
5301 output_addr_const (file
, x
);
5305 output_operand_lossage ("invalid %%xn code");
5310 print_operand_address (FILE *file
, rtx addr
)
5313 HOST_WIDE_INT offset
= 0;
5315 if (GET_CODE (addr
) == AND
)
5316 addr
= XEXP (addr
, 0);
5318 if (GET_CODE (addr
) == PLUS
5319 && CONST_INT_P (XEXP (addr
, 1)))
5321 offset
= INTVAL (XEXP (addr
, 1));
5322 addr
= XEXP (addr
, 0);
5325 if (GET_CODE (addr
) == LO_SUM
)
5327 const char *reloc16
, *reloclo
;
5328 rtx op1
= XEXP (addr
, 1);
5330 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5332 op1
= XEXP (op1
, 0);
5333 switch (XINT (op1
, 1))
5337 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5341 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5344 output_operand_lossage ("unknown relocation unspec");
5348 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5353 reloclo
= "gprellow";
5354 output_addr_const (file
, op1
);
5358 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
5360 addr
= XEXP (addr
, 0);
5361 switch (GET_CODE (addr
))
5364 basereg
= REGNO (addr
);
5368 basereg
= subreg_regno (addr
);
5375 fprintf (file
, "($%d)\t\t!%s", basereg
,
5376 (basereg
== 29 ? reloc16
: reloclo
));
5380 switch (GET_CODE (addr
))
5383 basereg
= REGNO (addr
);
5387 basereg
= subreg_regno (addr
);
5391 offset
= INTVAL (addr
);
5394 #if TARGET_ABI_OPEN_VMS
5396 fprintf (file
, "%s", XSTR (addr
, 0));
5400 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
5401 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
);
5402 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
5403 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5404 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5412 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
5415 /* Emit RTL insns to initialize the variable parts of a trampoline at
5416 M_TRAMP. FNDECL is target function's decl. CHAIN_VALUE is an rtx
5417 for the static chain value for the function. */
5420 alpha_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
5422 rtx fnaddr
, mem
, word1
, word2
;
5424 fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
5426 #ifdef POINTERS_EXTEND_UNSIGNED
5427 fnaddr
= convert_memory_address (Pmode
, fnaddr
);
5428 chain_value
= convert_memory_address (Pmode
, chain_value
);
5431 if (TARGET_ABI_OPEN_VMS
)
5436 /* Construct the name of the trampoline entry point. */
5437 fnname
= XSTR (fnaddr
, 0);
5438 trname
= (char *) alloca (strlen (fnname
) + 5);
5439 strcpy (trname
, fnname
);
5440 strcat (trname
, "..tr");
5441 fnname
= ggc_alloc_string (trname
, strlen (trname
) + 1);
5442 word2
= gen_rtx_SYMBOL_REF (Pmode
, fnname
);
5444 /* Trampoline (or "bounded") procedure descriptor is constructed from
5445 the function's procedure descriptor with certain fields zeroed IAW
5446 the VMS calling standard. This is stored in the first quadword. */
5447 word1
= force_reg (DImode
, gen_const_mem (DImode
, fnaddr
));
5448 word1
= expand_and (DImode
, word1
, GEN_INT (0xffff0fff0000fff0), NULL
);
5452 /* These 4 instructions are:
5457 We don't bother setting the HINT field of the jump; the nop
5458 is merely there for padding. */
5459 word1
= GEN_INT (0xa77b0010a43b0018);
5460 word2
= GEN_INT (0x47ff041f6bfb0000);
5463 /* Store the first two words, as computed above. */
5464 mem
= adjust_address (m_tramp
, DImode
, 0);
5465 emit_move_insn (mem
, word1
);
5466 mem
= adjust_address (m_tramp
, DImode
, 8);
5467 emit_move_insn (mem
, word2
);
5469 /* Store function address and static chain value. */
5470 mem
= adjust_address (m_tramp
, Pmode
, 16);
5471 emit_move_insn (mem
, fnaddr
);
5472 mem
= adjust_address (m_tramp
, Pmode
, 24);
5473 emit_move_insn (mem
, chain_value
);
5477 emit_insn (gen_imb ());
5478 #ifdef HAVE_ENABLE_EXECUTE_STACK
5479 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5480 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
5485 /* Determine where to put an argument to a function.
5486 Value is zero to push the argument on the stack,
5487 or a hard register in which to store the argument.
5489 MODE is the argument's machine mode.
5490 TYPE is the data type of the argument (as a tree).
5491 This is null for libcalls where that information may
5493 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5494 the preceding args and about the function being called.
5495 NAMED is nonzero if this argument is a named parameter
5496 (otherwise it is an extra parameter matching an ellipsis).
5498 On Alpha the first 6 words of args are normally in registers
5499 and the rest are pushed. */
5502 alpha_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
5503 const_tree type
, bool named ATTRIBUTE_UNUSED
)
5505 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5509 /* Don't get confused and pass small structures in FP registers. */
5510 if (type
&& AGGREGATE_TYPE_P (type
))
5514 #ifdef ENABLE_CHECKING
5515 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5517 gcc_assert (!COMPLEX_MODE_P (mode
));
5520 /* Set up defaults for FP operands passed in FP registers, and
5521 integral operands passed in integer registers. */
5522 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5528 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5529 the two platforms, so we can't avoid conditional compilation. */
5530 #if TARGET_ABI_OPEN_VMS
5532 if (mode
== VOIDmode
)
5533 return alpha_arg_info_reg_val (*cum
);
5535 num_args
= cum
->num_args
;
5537 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5540 #elif TARGET_ABI_OSF
5546 /* VOID is passed as a special flag for "last argument". */
5547 if (type
== void_type_node
)
5549 else if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5553 #error Unhandled ABI
5556 return gen_rtx_REG (mode
, num_args
+ basereg
);
5559 /* Update the data in CUM to advance over an argument
5560 of mode MODE and data type TYPE.
5561 (TYPE is null for libcalls where that information may not be available.) */
5564 alpha_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
5565 const_tree type
, bool named ATTRIBUTE_UNUSED
)
5567 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5568 bool onstack
= targetm
.calls
.must_pass_in_stack (mode
, type
);
5569 int increment
= onstack
? 6 : ALPHA_ARG_SIZE (mode
, type
, named
);
5574 if (!onstack
&& cum
->num_args
< 6)
5575 cum
->atypes
[cum
->num_args
] = alpha_arg_type (mode
);
5576 cum
->num_args
+= increment
;
5581 alpha_arg_partial_bytes (cumulative_args_t cum_v
,
5582 enum machine_mode mode ATTRIBUTE_UNUSED
,
5583 tree type ATTRIBUTE_UNUSED
,
5584 bool named ATTRIBUTE_UNUSED
)
5587 CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
= get_cumulative_args (cum_v
);
5589 #if TARGET_ABI_OPEN_VMS
5590 if (cum
->num_args
< 6
5591 && 6 < cum
->num_args
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5592 words
= 6 - cum
->num_args
;
5593 #elif TARGET_ABI_OSF
5594 if (*cum
< 6 && 6 < *cum
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5597 #error Unhandled ABI
5600 return words
* UNITS_PER_WORD
;
5604 /* Return true if TYPE must be returned in memory, instead of in registers. */
5607 alpha_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5609 enum machine_mode mode
= VOIDmode
;
5614 mode
= TYPE_MODE (type
);
5616 /* All aggregates are returned in memory, except on OpenVMS where
5617 records that fit 64 bits should be returned by immediate value
5618 as required by section 3.8.7.1 of the OpenVMS Calling Standard. */
5619 if (TARGET_ABI_OPEN_VMS
5620 && TREE_CODE (type
) != ARRAY_TYPE
5621 && (unsigned HOST_WIDE_INT
) int_size_in_bytes(type
) <= 8)
5624 if (AGGREGATE_TYPE_P (type
))
5628 size
= GET_MODE_SIZE (mode
);
5629 switch (GET_MODE_CLASS (mode
))
5631 case MODE_VECTOR_FLOAT
:
5632 /* Pass all float vectors in memory, like an aggregate. */
5635 case MODE_COMPLEX_FLOAT
:
5636 /* We judge complex floats on the size of their element,
5637 not the size of the whole type. */
5638 size
= GET_MODE_UNIT_SIZE (mode
);
5643 case MODE_COMPLEX_INT
:
5644 case MODE_VECTOR_INT
:
5648 /* ??? We get called on all sorts of random stuff from
5649 aggregate_value_p. We must return something, but it's not
5650 clear what's safe to return. Pretend it's a struct I
5655 /* Otherwise types must fit in one register. */
5656 return size
> UNITS_PER_WORD
;
5659 /* Return true if TYPE should be passed by invisible reference. */
5662 alpha_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
5663 enum machine_mode mode
,
5664 const_tree type ATTRIBUTE_UNUSED
,
5665 bool named ATTRIBUTE_UNUSED
)
5667 return mode
== TFmode
|| mode
== TCmode
;
5670 /* Define how to find the value returned by a function. VALTYPE is the
5671 data type of the value (as a tree). If the precise function being
5672 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5673 MODE is set instead of VALTYPE for libcalls.
5675 On Alpha the value is found in $0 for integer functions and
5676 $f0 for floating-point functions. */
5679 function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
5680 enum machine_mode mode
)
5682 unsigned int regnum
, dummy ATTRIBUTE_UNUSED
;
5683 enum mode_class mclass
;
5685 gcc_assert (!valtype
|| !alpha_return_in_memory (valtype
, func
));
5688 mode
= TYPE_MODE (valtype
);
5690 mclass
= GET_MODE_CLASS (mode
);
5694 /* Do the same thing as PROMOTE_MODE except for libcalls on VMS,
5695 where we have them returning both SImode and DImode. */
5696 if (!(TARGET_ABI_OPEN_VMS
&& valtype
&& AGGREGATE_TYPE_P (valtype
)))
5697 PROMOTE_MODE (mode
, dummy
, valtype
);
5700 case MODE_COMPLEX_INT
:
5701 case MODE_VECTOR_INT
:
5709 case MODE_COMPLEX_FLOAT
:
5711 enum machine_mode cmode
= GET_MODE_INNER (mode
);
5713 return gen_rtx_PARALLEL
5716 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
5718 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
5719 GEN_INT (GET_MODE_SIZE (cmode
)))));
5723 /* We should only reach here for BLKmode on VMS. */
5724 gcc_assert (TARGET_ABI_OPEN_VMS
&& mode
== BLKmode
);
5732 return gen_rtx_REG (mode
, regnum
);
5735 /* TCmode complex values are passed by invisible reference. We
5736 should not split these values. */
5739 alpha_split_complex_arg (const_tree type
)
5741 return TYPE_MODE (type
) != TCmode
;
5745 alpha_build_builtin_va_list (void)
5747 tree base
, ofs
, space
, record
, type_decl
;
5749 if (TARGET_ABI_OPEN_VMS
)
5750 return ptr_type_node
;
5752 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5753 type_decl
= build_decl (BUILTINS_LOCATION
,
5754 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5755 TYPE_STUB_DECL (record
) = type_decl
;
5756 TYPE_NAME (record
) = type_decl
;
5758 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5760 /* Dummy field to prevent alignment warnings. */
5761 space
= build_decl (BUILTINS_LOCATION
,
5762 FIELD_DECL
, NULL_TREE
, integer_type_node
);
5763 DECL_FIELD_CONTEXT (space
) = record
;
5764 DECL_ARTIFICIAL (space
) = 1;
5765 DECL_IGNORED_P (space
) = 1;
5767 ofs
= build_decl (BUILTINS_LOCATION
,
5768 FIELD_DECL
, get_identifier ("__offset"),
5770 DECL_FIELD_CONTEXT (ofs
) = record
;
5771 DECL_CHAIN (ofs
) = space
;
5772 /* ??? This is a hack, __offset is marked volatile to prevent
5773 DCE that confuses stdarg optimization and results in
5774 gcc.c-torture/execute/stdarg-1.c failure. See PR 41089. */
5775 TREE_THIS_VOLATILE (ofs
) = 1;
5777 base
= build_decl (BUILTINS_LOCATION
,
5778 FIELD_DECL
, get_identifier ("__base"),
5780 DECL_FIELD_CONTEXT (base
) = record
;
5781 DECL_CHAIN (base
) = ofs
;
5783 TYPE_FIELDS (record
) = base
;
5784 layout_type (record
);
5786 va_list_gpr_counter_field
= ofs
;
5791 /* Helper function for alpha_stdarg_optimize_hook. Skip over casts
5792 and constant additions. */
5795 va_list_skip_additions (tree lhs
)
5801 enum tree_code code
;
5803 stmt
= SSA_NAME_DEF_STMT (lhs
);
5805 if (gimple_code (stmt
) == GIMPLE_PHI
)
5808 if (!is_gimple_assign (stmt
)
5809 || gimple_assign_lhs (stmt
) != lhs
)
5812 if (TREE_CODE (gimple_assign_rhs1 (stmt
)) != SSA_NAME
)
5814 code
= gimple_assign_rhs_code (stmt
);
5815 if (!CONVERT_EXPR_CODE_P (code
)
5816 && ((code
!= PLUS_EXPR
&& code
!= POINTER_PLUS_EXPR
)
5817 || TREE_CODE (gimple_assign_rhs2 (stmt
)) != INTEGER_CST
5818 || !host_integerp (gimple_assign_rhs2 (stmt
), 1)))
5821 lhs
= gimple_assign_rhs1 (stmt
);
5825 /* Check if LHS = RHS statement is
5826 LHS = *(ap.__base + ap.__offset + cst)
5829 + ((ap.__offset + cst <= 47)
5830 ? ap.__offset + cst - 48 : ap.__offset + cst) + cst2).
5831 If the former, indicate that GPR registers are needed,
5832 if the latter, indicate that FPR registers are needed.
5834 Also look for LHS = (*ptr).field, where ptr is one of the forms
5837 On alpha, cfun->va_list_gpr_size is used as size of the needed
5838 regs and cfun->va_list_fpr_size is a bitmask, bit 0 set if GPR
5839 registers are needed and bit 1 set if FPR registers are needed.
5840 Return true if va_list references should not be scanned for the
5841 current statement. */
5844 alpha_stdarg_optimize_hook (struct stdarg_info
*si
, const_gimple stmt
)
5846 tree base
, offset
, rhs
;
5850 if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt
))
5851 != GIMPLE_SINGLE_RHS
)
5854 rhs
= gimple_assign_rhs1 (stmt
);
5855 while (handled_component_p (rhs
))
5856 rhs
= TREE_OPERAND (rhs
, 0);
5857 if (TREE_CODE (rhs
) != MEM_REF
5858 || TREE_CODE (TREE_OPERAND (rhs
, 0)) != SSA_NAME
)
5861 stmt
= va_list_skip_additions (TREE_OPERAND (rhs
, 0));
5863 || !is_gimple_assign (stmt
)
5864 || gimple_assign_rhs_code (stmt
) != POINTER_PLUS_EXPR
)
5867 base
= gimple_assign_rhs1 (stmt
);
5868 if (TREE_CODE (base
) == SSA_NAME
)
5870 base_stmt
= va_list_skip_additions (base
);
5872 && is_gimple_assign (base_stmt
)
5873 && gimple_assign_rhs_code (base_stmt
) == COMPONENT_REF
)
5874 base
= gimple_assign_rhs1 (base_stmt
);
5877 if (TREE_CODE (base
) != COMPONENT_REF
5878 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
5880 base
= gimple_assign_rhs2 (stmt
);
5881 if (TREE_CODE (base
) == SSA_NAME
)
5883 base_stmt
= va_list_skip_additions (base
);
5885 && is_gimple_assign (base_stmt
)
5886 && gimple_assign_rhs_code (base_stmt
) == COMPONENT_REF
)
5887 base
= gimple_assign_rhs1 (base_stmt
);
5890 if (TREE_CODE (base
) != COMPONENT_REF
5891 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
5897 base
= get_base_address (base
);
5898 if (TREE_CODE (base
) != VAR_DECL
5899 || !bitmap_bit_p (si
->va_list_vars
, DECL_UID (base
)))
5902 offset
= gimple_op (stmt
, 1 + offset_arg
);
5903 if (TREE_CODE (offset
) == SSA_NAME
)
5905 gimple offset_stmt
= va_list_skip_additions (offset
);
5908 && gimple_code (offset_stmt
) == GIMPLE_PHI
)
5911 gimple arg1_stmt
, arg2_stmt
;
5913 enum tree_code code1
, code2
;
5915 if (gimple_phi_num_args (offset_stmt
) != 2)
5919 = va_list_skip_additions (gimple_phi_arg_def (offset_stmt
, 0));
5921 = va_list_skip_additions (gimple_phi_arg_def (offset_stmt
, 1));
5922 if (arg1_stmt
== NULL
5923 || !is_gimple_assign (arg1_stmt
)
5924 || arg2_stmt
== NULL
5925 || !is_gimple_assign (arg2_stmt
))
5928 code1
= gimple_assign_rhs_code (arg1_stmt
);
5929 code2
= gimple_assign_rhs_code (arg2_stmt
);
5930 if (code1
== COMPONENT_REF
5931 && (code2
== MINUS_EXPR
|| code2
== PLUS_EXPR
))
5933 else if (code2
== COMPONENT_REF
5934 && (code1
== MINUS_EXPR
|| code1
== PLUS_EXPR
))
5936 gimple tem
= arg1_stmt
;
5938 arg1_stmt
= arg2_stmt
;
5944 if (!host_integerp (gimple_assign_rhs2 (arg2_stmt
), 0))
5947 sub
= tree_low_cst (gimple_assign_rhs2 (arg2_stmt
), 0);
5948 if (code2
== MINUS_EXPR
)
5950 if (sub
< -48 || sub
> -32)
5953 arg1
= gimple_assign_rhs1 (arg1_stmt
);
5954 arg2
= gimple_assign_rhs1 (arg2_stmt
);
5955 if (TREE_CODE (arg2
) == SSA_NAME
)
5957 arg2_stmt
= va_list_skip_additions (arg2
);
5958 if (arg2_stmt
== NULL
5959 || !is_gimple_assign (arg2_stmt
)
5960 || gimple_assign_rhs_code (arg2_stmt
) != COMPONENT_REF
)
5962 arg2
= gimple_assign_rhs1 (arg2_stmt
);
5967 if (TREE_CODE (arg1
) != COMPONENT_REF
5968 || TREE_OPERAND (arg1
, 1) != va_list_gpr_counter_field
5969 || get_base_address (arg1
) != base
)
5972 /* Need floating point regs. */
5973 cfun
->va_list_fpr_size
|= 2;
5977 && is_gimple_assign (offset_stmt
)
5978 && gimple_assign_rhs_code (offset_stmt
) == COMPONENT_REF
)
5979 offset
= gimple_assign_rhs1 (offset_stmt
);
5981 if (TREE_CODE (offset
) != COMPONENT_REF
5982 || TREE_OPERAND (offset
, 1) != va_list_gpr_counter_field
5983 || get_base_address (offset
) != base
)
5986 /* Need general regs. */
5987 cfun
->va_list_fpr_size
|= 1;
5991 si
->va_list_escapes
= true;
5996 /* Perform any needed actions needed for a function that is receiving a
5997 variable number of arguments. */
6000 alpha_setup_incoming_varargs (cumulative_args_t pcum
, enum machine_mode mode
,
6001 tree type
, int *pretend_size
, int no_rtl
)
6003 CUMULATIVE_ARGS cum
= *get_cumulative_args (pcum
);
6005 /* Skip the current argument. */
6006 targetm
.calls
.function_arg_advance (pack_cumulative_args (&cum
), mode
, type
,
6009 #if TARGET_ABI_OPEN_VMS
6010 /* For VMS, we allocate space for all 6 arg registers plus a count.
6012 However, if NO registers need to be saved, don't allocate any space.
6013 This is not only because we won't need the space, but because AP
6014 includes the current_pretend_args_size and we don't want to mess up
6015 any ap-relative addresses already made. */
6016 if (cum
.num_args
< 6)
6020 emit_move_insn (gen_rtx_REG (DImode
, 1), virtual_incoming_args_rtx
);
6021 emit_insn (gen_arg_home ());
6023 *pretend_size
= 7 * UNITS_PER_WORD
;
6026 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6027 only push those that are remaining. However, if NO registers need to
6028 be saved, don't allocate any space. This is not only because we won't
6029 need the space, but because AP includes the current_pretend_args_size
6030 and we don't want to mess up any ap-relative addresses already made.
6032 If we are not to use the floating-point registers, save the integer
6033 registers where we would put the floating-point registers. This is
6034 not the most efficient way to implement varargs with just one register
6035 class, but it isn't worth doing anything more efficient in this rare
6043 alias_set_type set
= get_varargs_alias_set ();
6046 count
= cfun
->va_list_gpr_size
/ UNITS_PER_WORD
;
6047 if (count
> 6 - cum
)
6050 /* Detect whether integer registers or floating-point registers
6051 are needed by the detected va_arg statements. See above for
6052 how these values are computed. Note that the "escape" value
6053 is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of
6055 gcc_assert ((VA_LIST_MAX_FPR_SIZE
& 3) == 3);
6057 if (cfun
->va_list_fpr_size
& 1)
6059 tmp
= gen_rtx_MEM (BLKmode
,
6060 plus_constant (virtual_incoming_args_rtx
,
6061 (cum
+ 6) * UNITS_PER_WORD
));
6062 MEM_NOTRAP_P (tmp
) = 1;
6063 set_mem_alias_set (tmp
, set
);
6064 move_block_from_reg (16 + cum
, tmp
, count
);
6067 if (cfun
->va_list_fpr_size
& 2)
6069 tmp
= gen_rtx_MEM (BLKmode
,
6070 plus_constant (virtual_incoming_args_rtx
,
6071 cum
* UNITS_PER_WORD
));
6072 MEM_NOTRAP_P (tmp
) = 1;
6073 set_mem_alias_set (tmp
, set
);
6074 move_block_from_reg (16 + cum
+ TARGET_FPREGS
*32, tmp
, count
);
6077 *pretend_size
= 12 * UNITS_PER_WORD
;
6082 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
6084 HOST_WIDE_INT offset
;
6085 tree t
, offset_field
, base_field
;
6087 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6090 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6091 up by 48, storing fp arg registers in the first 48 bytes, and the
6092 integer arg registers in the next 48 bytes. This is only done,
6093 however, if any integer registers need to be stored.
6095 If no integer registers need be stored, then we must subtract 48
6096 in order to account for the integer arg registers which are counted
6097 in argsize above, but which are not actually stored on the stack.
6098 Must further be careful here about structures straddling the last
6099 integer argument register; that futzes with pretend_args_size,
6100 which changes the meaning of AP. */
6103 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6105 offset
= -6 * UNITS_PER_WORD
+ crtl
->args
.pretend_args_size
;
6107 if (TARGET_ABI_OPEN_VMS
)
6109 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6110 t
= fold_build_pointer_plus_hwi (t
, offset
+ NUM_ARGS
* UNITS_PER_WORD
);
6111 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6112 TREE_SIDE_EFFECTS (t
) = 1;
6113 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6117 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6118 offset_field
= DECL_CHAIN (base_field
);
6120 base_field
= build3 (COMPONENT_REF
, TREE_TYPE (base_field
),
6121 valist
, base_field
, NULL_TREE
);
6122 offset_field
= build3 (COMPONENT_REF
, TREE_TYPE (offset_field
),
6123 valist
, offset_field
, NULL_TREE
);
6125 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6126 t
= fold_build_pointer_plus_hwi (t
, offset
);
6127 t
= build2 (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6128 TREE_SIDE_EFFECTS (t
) = 1;
6129 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6131 t
= build_int_cst (NULL_TREE
, NUM_ARGS
* UNITS_PER_WORD
);
6132 t
= build2 (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6133 TREE_SIDE_EFFECTS (t
) = 1;
6134 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6139 alpha_gimplify_va_arg_1 (tree type
, tree base
, tree offset
,
6142 tree type_size
, ptr_type
, addend
, t
, addr
;
6143 gimple_seq internal_post
;
6145 /* If the type could not be passed in registers, skip the block
6146 reserved for the registers. */
6147 if (targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
6149 t
= build_int_cst (TREE_TYPE (offset
), 6*8);
6150 gimplify_assign (offset
,
6151 build2 (MAX_EXPR
, TREE_TYPE (offset
), offset
, t
),
6156 ptr_type
= build_pointer_type_for_mode (type
, ptr_mode
, true);
6158 if (TREE_CODE (type
) == COMPLEX_TYPE
)
6160 tree real_part
, imag_part
, real_temp
;
6162 real_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
6165 /* Copy the value into a new temporary, lest the formal temporary
6166 be reused out from under us. */
6167 real_temp
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
6169 imag_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
6172 return build2 (COMPLEX_EXPR
, type
, real_temp
, imag_part
);
6174 else if (TREE_CODE (type
) == REAL_TYPE
)
6176 tree fpaddend
, cond
, fourtyeight
;
6178 fourtyeight
= build_int_cst (TREE_TYPE (addend
), 6*8);
6179 fpaddend
= fold_build2 (MINUS_EXPR
, TREE_TYPE (addend
),
6180 addend
, fourtyeight
);
6181 cond
= fold_build2 (LT_EXPR
, boolean_type_node
, addend
, fourtyeight
);
6182 addend
= fold_build3 (COND_EXPR
, TREE_TYPE (addend
), cond
,
6186 /* Build the final address and force that value into a temporary. */
6187 addr
= fold_build_pointer_plus (fold_convert (ptr_type
, base
), addend
);
6188 internal_post
= NULL
;
6189 gimplify_expr (&addr
, pre_p
, &internal_post
, is_gimple_val
, fb_rvalue
);
6190 gimple_seq_add_seq (pre_p
, internal_post
);
6192 /* Update the offset field. */
6193 type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
));
6194 if (type_size
== NULL
|| TREE_OVERFLOW (type_size
))
6198 t
= size_binop (PLUS_EXPR
, type_size
, size_int (7));
6199 t
= size_binop (TRUNC_DIV_EXPR
, t
, size_int (8));
6200 t
= size_binop (MULT_EXPR
, t
, size_int (8));
6202 t
= fold_convert (TREE_TYPE (offset
), t
);
6203 gimplify_assign (offset
, build2 (PLUS_EXPR
, TREE_TYPE (offset
), offset
, t
),
6206 return build_va_arg_indirect_ref (addr
);
6210 alpha_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6213 tree offset_field
, base_field
, offset
, base
, t
, r
;
6216 if (TARGET_ABI_OPEN_VMS
)
6217 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6219 base_field
= TYPE_FIELDS (va_list_type_node
);
6220 offset_field
= DECL_CHAIN (base_field
);
6221 base_field
= build3 (COMPONENT_REF
, TREE_TYPE (base_field
),
6222 valist
, base_field
, NULL_TREE
);
6223 offset_field
= build3 (COMPONENT_REF
, TREE_TYPE (offset_field
),
6224 valist
, offset_field
, NULL_TREE
);
6226 /* Pull the fields of the structure out into temporaries. Since we never
6227 modify the base field, we can use a formal temporary. Sign-extend the
6228 offset field so that it's the proper width for pointer arithmetic. */
6229 base
= get_formal_tmp_var (base_field
, pre_p
);
6231 t
= fold_convert (build_nonstandard_integer_type (64, 0), offset_field
);
6232 offset
= get_initialized_tmp_var (t
, pre_p
, NULL
);
6234 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6236 type
= build_pointer_type_for_mode (type
, ptr_mode
, true);
6238 /* Find the value. Note that this will be a stable indirection, or
6239 a composite of stable indirections in the case of complex. */
6240 r
= alpha_gimplify_va_arg_1 (type
, base
, offset
, pre_p
);
6242 /* Stuff the offset temporary back into its field. */
6243 gimplify_assign (unshare_expr (offset_field
),
6244 fold_convert (TREE_TYPE (offset_field
), offset
), pre_p
);
6247 r
= build_va_arg_indirect_ref (r
);
6256 ALPHA_BUILTIN_CMPBGE
,
6257 ALPHA_BUILTIN_EXTBL
,
6258 ALPHA_BUILTIN_EXTWL
,
6259 ALPHA_BUILTIN_EXTLL
,
6260 ALPHA_BUILTIN_EXTQL
,
6261 ALPHA_BUILTIN_EXTWH
,
6262 ALPHA_BUILTIN_EXTLH
,
6263 ALPHA_BUILTIN_EXTQH
,
6264 ALPHA_BUILTIN_INSBL
,
6265 ALPHA_BUILTIN_INSWL
,
6266 ALPHA_BUILTIN_INSLL
,
6267 ALPHA_BUILTIN_INSQL
,
6268 ALPHA_BUILTIN_INSWH
,
6269 ALPHA_BUILTIN_INSLH
,
6270 ALPHA_BUILTIN_INSQH
,
6271 ALPHA_BUILTIN_MSKBL
,
6272 ALPHA_BUILTIN_MSKWL
,
6273 ALPHA_BUILTIN_MSKLL
,
6274 ALPHA_BUILTIN_MSKQL
,
6275 ALPHA_BUILTIN_MSKWH
,
6276 ALPHA_BUILTIN_MSKLH
,
6277 ALPHA_BUILTIN_MSKQH
,
6278 ALPHA_BUILTIN_UMULH
,
6280 ALPHA_BUILTIN_ZAPNOT
,
6281 ALPHA_BUILTIN_AMASK
,
6282 ALPHA_BUILTIN_IMPLVER
,
6284 ALPHA_BUILTIN_THREAD_POINTER
,
6285 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6286 ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER
,
6287 ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER
,
6290 ALPHA_BUILTIN_MINUB8
,
6291 ALPHA_BUILTIN_MINSB8
,
6292 ALPHA_BUILTIN_MINUW4
,
6293 ALPHA_BUILTIN_MINSW4
,
6294 ALPHA_BUILTIN_MAXUB8
,
6295 ALPHA_BUILTIN_MAXSB8
,
6296 ALPHA_BUILTIN_MAXUW4
,
6297 ALPHA_BUILTIN_MAXSW4
,
6301 ALPHA_BUILTIN_UNPKBL
,
6302 ALPHA_BUILTIN_UNPKBW
,
6307 ALPHA_BUILTIN_CTPOP
,
6312 static enum insn_code
const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6313 CODE_FOR_builtin_cmpbge
,
6321 CODE_FOR_builtin_insbl
,
6322 CODE_FOR_builtin_inswl
,
6323 CODE_FOR_builtin_insll
,
6335 CODE_FOR_umuldi3_highpart
,
6336 CODE_FOR_builtin_zap
,
6337 CODE_FOR_builtin_zapnot
,
6338 CODE_FOR_builtin_amask
,
6339 CODE_FOR_builtin_implver
,
6340 CODE_FOR_builtin_rpcc
,
6343 CODE_FOR_builtin_establish_vms_condition_handler
,
6344 CODE_FOR_builtin_revert_vms_condition_handler
,
6347 CODE_FOR_builtin_minub8
,
6348 CODE_FOR_builtin_minsb8
,
6349 CODE_FOR_builtin_minuw4
,
6350 CODE_FOR_builtin_minsw4
,
6351 CODE_FOR_builtin_maxub8
,
6352 CODE_FOR_builtin_maxsb8
,
6353 CODE_FOR_builtin_maxuw4
,
6354 CODE_FOR_builtin_maxsw4
,
6355 CODE_FOR_builtin_perr
,
6356 CODE_FOR_builtin_pklb
,
6357 CODE_FOR_builtin_pkwb
,
6358 CODE_FOR_builtin_unpkbl
,
6359 CODE_FOR_builtin_unpkbw
,
6364 CODE_FOR_popcountdi2
6367 struct alpha_builtin_def
6370 enum alpha_builtin code
;
6371 unsigned int target_mask
;
6375 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6376 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0, true },
6377 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0, false }
6380 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6381 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0, true },
6382 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
, true },
6383 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
, true },
6384 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
, true },
6385 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
, true },
6386 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
, true },
6387 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
, true },
6388 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
, true }
6391 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6392 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0, true },
6393 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0, true },
6394 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0, true },
6395 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0, true },
6396 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0, true },
6397 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0, true },
6398 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0, true },
6399 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0, true },
6400 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0, true },
6401 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0, true },
6402 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0, true },
6403 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0, true },
6404 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0, true },
6405 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0, true },
6406 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0, true },
6407 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0, true },
6408 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0, true },
6409 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0, true },
6410 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0, true },
6411 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0, true },
6412 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0, true },
6413 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0, true },
6414 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0, true },
6415 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0, true },
6416 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0, true },
6417 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
, true },
6418 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
, true },
6419 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
, true },
6420 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
, true },
6421 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
, true },
6422 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
, true },
6423 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
, true },
6424 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
, true },
6425 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
, true }
6428 static GTY(()) tree alpha_v8qi_u
;
6429 static GTY(()) tree alpha_v8qi_s
;
6430 static GTY(()) tree alpha_v4hi_u
;
6431 static GTY(()) tree alpha_v4hi_s
;
6433 static GTY(()) tree alpha_builtins
[(int) ALPHA_BUILTIN_max
];
6435 /* Return the alpha builtin for CODE. */
6438 alpha_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
6440 if (code
>= ALPHA_BUILTIN_max
)
6441 return error_mark_node
;
6442 return alpha_builtins
[code
];
6445 /* Helper function of alpha_init_builtins. Add the built-in specified
6446 by NAME, TYPE, CODE, and ECF. */
6449 alpha_builtin_function (const char *name
, tree ftype
,
6450 enum alpha_builtin code
, unsigned ecf
)
6452 tree decl
= add_builtin_function (name
, ftype
, (int) code
,
6453 BUILT_IN_MD
, NULL
, NULL_TREE
);
6455 if (ecf
& ECF_CONST
)
6456 TREE_READONLY (decl
) = 1;
6457 if (ecf
& ECF_NOTHROW
)
6458 TREE_NOTHROW (decl
) = 1;
6460 alpha_builtins
[(int) code
] = decl
;
6463 /* Helper function of alpha_init_builtins. Add the COUNT built-in
6464 functions pointed to by P, with function type FTYPE. */
6467 alpha_add_builtins (const struct alpha_builtin_def
*p
, size_t count
,
6472 for (i
= 0; i
< count
; ++i
, ++p
)
6473 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6474 alpha_builtin_function (p
->name
, ftype
, p
->code
,
6475 (p
->is_const
? ECF_CONST
: 0) | ECF_NOTHROW
);
6479 alpha_init_builtins (void)
6481 tree dimode_integer_type_node
;
6484 dimode_integer_type_node
= lang_hooks
.types
.type_for_mode (DImode
, 0);
6486 ftype
= build_function_type_list (dimode_integer_type_node
, NULL_TREE
);
6487 alpha_add_builtins (zero_arg_builtins
, ARRAY_SIZE (zero_arg_builtins
),
6490 ftype
= build_function_type_list (dimode_integer_type_node
,
6491 dimode_integer_type_node
, NULL_TREE
);
6492 alpha_add_builtins (one_arg_builtins
, ARRAY_SIZE (one_arg_builtins
),
6495 ftype
= build_function_type_list (dimode_integer_type_node
,
6496 dimode_integer_type_node
,
6497 dimode_integer_type_node
, NULL_TREE
);
6498 alpha_add_builtins (two_arg_builtins
, ARRAY_SIZE (two_arg_builtins
),
6501 ftype
= build_function_type_list (ptr_type_node
, NULL_TREE
);
6502 alpha_builtin_function ("__builtin_thread_pointer", ftype
,
6503 ALPHA_BUILTIN_THREAD_POINTER
, ECF_NOTHROW
);
6505 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6506 alpha_builtin_function ("__builtin_set_thread_pointer", ftype
,
6507 ALPHA_BUILTIN_SET_THREAD_POINTER
, ECF_NOTHROW
);
6509 if (TARGET_ABI_OPEN_VMS
)
6511 ftype
= build_function_type_list (ptr_type_node
, ptr_type_node
,
6513 alpha_builtin_function ("__builtin_establish_vms_condition_handler",
6515 ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER
,
6518 ftype
= build_function_type_list (ptr_type_node
, void_type_node
,
6520 alpha_builtin_function ("__builtin_revert_vms_condition_handler", ftype
,
6521 ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER
, 0);
6523 vms_patch_builtins ();
6526 alpha_v8qi_u
= build_vector_type (unsigned_intQI_type_node
, 8);
6527 alpha_v8qi_s
= build_vector_type (intQI_type_node
, 8);
6528 alpha_v4hi_u
= build_vector_type (unsigned_intHI_type_node
, 4);
6529 alpha_v4hi_s
= build_vector_type (intHI_type_node
, 4);
6532 /* Expand an expression EXP that calls a built-in function,
6533 with result going to TARGET if that's convenient
6534 (and in mode MODE if that's convenient).
6535 SUBTARGET may be used as the target for computing one of EXP's operands.
6536 IGNORE is nonzero if the value is to be ignored. */
6539 alpha_expand_builtin (tree exp
, rtx target
,
6540 rtx subtarget ATTRIBUTE_UNUSED
,
6541 enum machine_mode mode ATTRIBUTE_UNUSED
,
6542 int ignore ATTRIBUTE_UNUSED
)
6546 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
6547 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6549 call_expr_arg_iterator iter
;
6550 enum insn_code icode
;
6551 rtx op
[MAX_ARGS
], pat
;
6555 if (fcode
>= ALPHA_BUILTIN_max
)
6556 internal_error ("bad builtin fcode");
6557 icode
= code_for_builtin
[fcode
];
6559 internal_error ("bad builtin fcode");
6561 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6564 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
6566 const struct insn_operand_data
*insn_op
;
6568 if (arg
== error_mark_node
)
6570 if (arity
> MAX_ARGS
)
6573 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6575 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
6577 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6578 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6584 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6586 || GET_MODE (target
) != tmode
6587 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6588 target
= gen_reg_rtx (tmode
);
6594 pat
= GEN_FCN (icode
) (target
);
6598 pat
= GEN_FCN (icode
) (target
, op
[0]);
6600 pat
= GEN_FCN (icode
) (op
[0]);
6603 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6619 /* Several bits below assume HWI >= 64 bits. This should be enforced
6621 #if HOST_BITS_PER_WIDE_INT < 64
6622 # error "HOST_WIDE_INT too small"
6625 /* Fold the builtin for the CMPBGE instruction. This is a vector comparison
6626 with an 8-bit output vector. OPINT contains the integer operands; bit N
6627 of OP_CONST is set if OPINT[N] is valid. */
6630 alpha_fold_builtin_cmpbge (unsigned HOST_WIDE_INT opint
[], long op_const
)
6635 for (i
= 0, val
= 0; i
< 8; ++i
)
6637 unsigned HOST_WIDE_INT c0
= (opint
[0] >> (i
* 8)) & 0xff;
6638 unsigned HOST_WIDE_INT c1
= (opint
[1] >> (i
* 8)) & 0xff;
6642 return build_int_cst (long_integer_type_node
, val
);
6644 else if (op_const
== 2 && opint
[1] == 0)
6645 return build_int_cst (long_integer_type_node
, 0xff);
6649 /* Fold the builtin for the ZAPNOT instruction. This is essentially a
6650 specialized form of an AND operation. Other byte manipulation instructions
6651 are defined in terms of this instruction, so this is also used as a
6652 subroutine for other builtins.
6654 OP contains the tree operands; OPINT contains the extracted integer values.
6655 Bit N of OP_CONST it set if OPINT[N] is valid. OP may be null if only
6656 OPINT may be considered. */
6659 alpha_fold_builtin_zapnot (tree
*op
, unsigned HOST_WIDE_INT opint
[],
6664 unsigned HOST_WIDE_INT mask
= 0;
6667 for (i
= 0; i
< 8; ++i
)
6668 if ((opint
[1] >> i
) & 1)
6669 mask
|= (unsigned HOST_WIDE_INT
)0xff << (i
* 8);
6672 return build_int_cst (long_integer_type_node
, opint
[0] & mask
);
6675 return fold_build2 (BIT_AND_EXPR
, long_integer_type_node
, op
[0],
6676 build_int_cst (long_integer_type_node
, mask
));
6678 else if ((op_const
& 1) && opint
[0] == 0)
6679 return build_int_cst (long_integer_type_node
, 0);
6683 /* Fold the builtins for the EXT family of instructions. */
6686 alpha_fold_builtin_extxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6687 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6691 tree
*zap_op
= NULL
;
6695 unsigned HOST_WIDE_INT loc
;
6698 loc
*= BITS_PER_UNIT
;
6704 unsigned HOST_WIDE_INT temp
= opint
[0];
6717 opint
[1] = bytemask
;
6718 return alpha_fold_builtin_zapnot (zap_op
, opint
, zap_const
);
6721 /* Fold the builtins for the INS family of instructions. */
6724 alpha_fold_builtin_insxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6725 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6728 if ((op_const
& 1) && opint
[0] == 0)
6729 return build_int_cst (long_integer_type_node
, 0);
6733 unsigned HOST_WIDE_INT temp
, loc
, byteloc
;
6734 tree
*zap_op
= NULL
;
6742 byteloc
= (64 - (loc
* 8)) & 0x3f;
6759 opint
[1] = bytemask
;
6760 return alpha_fold_builtin_zapnot (zap_op
, opint
, op_const
);
6767 alpha_fold_builtin_mskxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6768 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6773 unsigned HOST_WIDE_INT loc
;
6781 opint
[1] = bytemask
^ 0xff;
6784 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
6788 alpha_fold_builtin_umulh (unsigned HOST_WIDE_INT opint
[], long op_const
)
6794 unsigned HOST_WIDE_INT l
;
6797 mul_double (opint
[0], 0, opint
[1], 0, &l
, &h
);
6799 #if HOST_BITS_PER_WIDE_INT > 64
6803 return build_int_cst (long_integer_type_node
, h
);
6807 opint
[1] = opint
[0];
6810 /* Note that (X*1) >> 64 == 0. */
6811 if (opint
[1] == 0 || opint
[1] == 1)
6812 return build_int_cst (long_integer_type_node
, 0);
6819 alpha_fold_vector_minmax (enum tree_code code
, tree op
[], tree vtype
)
6821 tree op0
= fold_convert (vtype
, op
[0]);
6822 tree op1
= fold_convert (vtype
, op
[1]);
6823 tree val
= fold_build2 (code
, vtype
, op0
, op1
);
6824 return fold_build1 (VIEW_CONVERT_EXPR
, long_integer_type_node
, val
);
6828 alpha_fold_builtin_perr (unsigned HOST_WIDE_INT opint
[], long op_const
)
6830 unsigned HOST_WIDE_INT temp
= 0;
6836 for (i
= 0; i
< 8; ++i
)
6838 unsigned HOST_WIDE_INT a
= (opint
[0] >> (i
* 8)) & 0xff;
6839 unsigned HOST_WIDE_INT b
= (opint
[1] >> (i
* 8)) & 0xff;
6846 return build_int_cst (long_integer_type_node
, temp
);
6850 alpha_fold_builtin_pklb (unsigned HOST_WIDE_INT opint
[], long op_const
)
6852 unsigned HOST_WIDE_INT temp
;
6857 temp
= opint
[0] & 0xff;
6858 temp
|= (opint
[0] >> 24) & 0xff00;
6860 return build_int_cst (long_integer_type_node
, temp
);
6864 alpha_fold_builtin_pkwb (unsigned HOST_WIDE_INT opint
[], long op_const
)
6866 unsigned HOST_WIDE_INT temp
;
6871 temp
= opint
[0] & 0xff;
6872 temp
|= (opint
[0] >> 8) & 0xff00;
6873 temp
|= (opint
[0] >> 16) & 0xff0000;
6874 temp
|= (opint
[0] >> 24) & 0xff000000;
6876 return build_int_cst (long_integer_type_node
, temp
);
6880 alpha_fold_builtin_unpkbl (unsigned HOST_WIDE_INT opint
[], long op_const
)
6882 unsigned HOST_WIDE_INT temp
;
6887 temp
= opint
[0] & 0xff;
6888 temp
|= (opint
[0] & 0xff00) << 24;
6890 return build_int_cst (long_integer_type_node
, temp
);
6894 alpha_fold_builtin_unpkbw (unsigned HOST_WIDE_INT opint
[], long op_const
)
6896 unsigned HOST_WIDE_INT temp
;
6901 temp
= opint
[0] & 0xff;
6902 temp
|= (opint
[0] & 0x0000ff00) << 8;
6903 temp
|= (opint
[0] & 0x00ff0000) << 16;
6904 temp
|= (opint
[0] & 0xff000000) << 24;
6906 return build_int_cst (long_integer_type_node
, temp
);
6910 alpha_fold_builtin_cttz (unsigned HOST_WIDE_INT opint
[], long op_const
)
6912 unsigned HOST_WIDE_INT temp
;
6920 temp
= exact_log2 (opint
[0] & -opint
[0]);
6922 return build_int_cst (long_integer_type_node
, temp
);
6926 alpha_fold_builtin_ctlz (unsigned HOST_WIDE_INT opint
[], long op_const
)
6928 unsigned HOST_WIDE_INT temp
;
6936 temp
= 64 - floor_log2 (opint
[0]) - 1;
6938 return build_int_cst (long_integer_type_node
, temp
);
6942 alpha_fold_builtin_ctpop (unsigned HOST_WIDE_INT opint
[], long op_const
)
6944 unsigned HOST_WIDE_INT temp
, op
;
6952 temp
++, op
&= op
- 1;
6954 return build_int_cst (long_integer_type_node
, temp
);
6957 /* Fold one of our builtin functions. */
6960 alpha_fold_builtin (tree fndecl
, int n_args
, tree
*op
,
6961 bool ignore ATTRIBUTE_UNUSED
)
6963 unsigned HOST_WIDE_INT opint
[MAX_ARGS
];
6967 if (n_args
>= MAX_ARGS
)
6970 for (i
= 0; i
< n_args
; i
++)
6973 if (arg
== error_mark_node
)
6977 if (TREE_CODE (arg
) == INTEGER_CST
)
6979 op_const
|= 1L << i
;
6980 opint
[i
] = int_cst_value (arg
);
6984 switch (DECL_FUNCTION_CODE (fndecl
))
6986 case ALPHA_BUILTIN_CMPBGE
:
6987 return alpha_fold_builtin_cmpbge (opint
, op_const
);
6989 case ALPHA_BUILTIN_EXTBL
:
6990 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x01, false);
6991 case ALPHA_BUILTIN_EXTWL
:
6992 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, false);
6993 case ALPHA_BUILTIN_EXTLL
:
6994 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, false);
6995 case ALPHA_BUILTIN_EXTQL
:
6996 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, false);
6997 case ALPHA_BUILTIN_EXTWH
:
6998 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, true);
6999 case ALPHA_BUILTIN_EXTLH
:
7000 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, true);
7001 case ALPHA_BUILTIN_EXTQH
:
7002 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, true);
7004 case ALPHA_BUILTIN_INSBL
:
7005 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x01, false);
7006 case ALPHA_BUILTIN_INSWL
:
7007 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, false);
7008 case ALPHA_BUILTIN_INSLL
:
7009 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, false);
7010 case ALPHA_BUILTIN_INSQL
:
7011 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, false);
7012 case ALPHA_BUILTIN_INSWH
:
7013 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, true);
7014 case ALPHA_BUILTIN_INSLH
:
7015 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, true);
7016 case ALPHA_BUILTIN_INSQH
:
7017 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, true);
7019 case ALPHA_BUILTIN_MSKBL
:
7020 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x01, false);
7021 case ALPHA_BUILTIN_MSKWL
:
7022 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, false);
7023 case ALPHA_BUILTIN_MSKLL
:
7024 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, false);
7025 case ALPHA_BUILTIN_MSKQL
:
7026 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, false);
7027 case ALPHA_BUILTIN_MSKWH
:
7028 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, true);
7029 case ALPHA_BUILTIN_MSKLH
:
7030 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, true);
7031 case ALPHA_BUILTIN_MSKQH
:
7032 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, true);
7034 case ALPHA_BUILTIN_UMULH
:
7035 return alpha_fold_builtin_umulh (opint
, op_const
);
7037 case ALPHA_BUILTIN_ZAP
:
7040 case ALPHA_BUILTIN_ZAPNOT
:
7041 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
7043 case ALPHA_BUILTIN_MINUB8
:
7044 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_u
);
7045 case ALPHA_BUILTIN_MINSB8
:
7046 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_s
);
7047 case ALPHA_BUILTIN_MINUW4
:
7048 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_u
);
7049 case ALPHA_BUILTIN_MINSW4
:
7050 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_s
);
7051 case ALPHA_BUILTIN_MAXUB8
:
7052 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_u
);
7053 case ALPHA_BUILTIN_MAXSB8
:
7054 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_s
);
7055 case ALPHA_BUILTIN_MAXUW4
:
7056 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_u
);
7057 case ALPHA_BUILTIN_MAXSW4
:
7058 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_s
);
7060 case ALPHA_BUILTIN_PERR
:
7061 return alpha_fold_builtin_perr (opint
, op_const
);
7062 case ALPHA_BUILTIN_PKLB
:
7063 return alpha_fold_builtin_pklb (opint
, op_const
);
7064 case ALPHA_BUILTIN_PKWB
:
7065 return alpha_fold_builtin_pkwb (opint
, op_const
);
7066 case ALPHA_BUILTIN_UNPKBL
:
7067 return alpha_fold_builtin_unpkbl (opint
, op_const
);
7068 case ALPHA_BUILTIN_UNPKBW
:
7069 return alpha_fold_builtin_unpkbw (opint
, op_const
);
7071 case ALPHA_BUILTIN_CTTZ
:
7072 return alpha_fold_builtin_cttz (opint
, op_const
);
7073 case ALPHA_BUILTIN_CTLZ
:
7074 return alpha_fold_builtin_ctlz (opint
, op_const
);
7075 case ALPHA_BUILTIN_CTPOP
:
7076 return alpha_fold_builtin_ctpop (opint
, op_const
);
7078 case ALPHA_BUILTIN_AMASK
:
7079 case ALPHA_BUILTIN_IMPLVER
:
7080 case ALPHA_BUILTIN_RPCC
:
7081 case ALPHA_BUILTIN_THREAD_POINTER
:
7082 case ALPHA_BUILTIN_SET_THREAD_POINTER
:
7083 /* None of these are foldable at compile-time. */
7089 /* This page contains routines that are used to determine what the function
7090 prologue and epilogue code will do and write them out. */
7092 /* Compute the size of the save area in the stack. */
7094 /* These variables are used for communication between the following functions.
7095 They indicate various things about the current function being compiled
7096 that are used to tell what kind of prologue, epilogue and procedure
7097 descriptor to generate. */
7099 /* Nonzero if we need a stack procedure. */
7100 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
7101 static enum alpha_procedure_types alpha_procedure_type
;
7103 /* Register number (either FP or SP) that is used to unwind the frame. */
7104 static int vms_unwind_regno
;
7106 /* Register number used to save FP. We need not have one for RA since
7107 we don't modify it for register procedures. This is only defined
7108 for register frame procedures. */
7109 static int vms_save_fp_regno
;
7111 /* Register number used to reference objects off our PV. */
7112 static int vms_base_regno
;
7114 /* Compute register masks for saved registers. */
7117 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
7119 unsigned long imask
= 0;
7120 unsigned long fmask
= 0;
7123 /* When outputting a thunk, we don't have valid register life info,
7124 but assemble_start_function wants to output .frame and .mask
7133 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7134 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
7136 /* One for every register we have to save. */
7137 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
7138 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
7139 && df_regs_ever_live_p (i
) && i
!= REG_RA
)
7142 imask
|= (1UL << i
);
7144 fmask
|= (1UL << (i
- 32));
7147 /* We need to restore these for the handler. */
7148 if (crtl
->calls_eh_return
)
7152 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
7153 if (regno
== INVALID_REGNUM
)
7155 imask
|= 1UL << regno
;
7159 /* If any register spilled, then spill the return address also. */
7160 /* ??? This is required by the Digital stack unwind specification
7161 and isn't needed if we're doing Dwarf2 unwinding. */
7162 if (imask
|| fmask
|| alpha_ra_ever_killed ())
7163 imask
|= (1UL << REG_RA
);
7170 alpha_sa_size (void)
7172 unsigned long mask
[2];
7176 alpha_sa_mask (&mask
[0], &mask
[1]);
7178 for (j
= 0; j
< 2; ++j
)
7179 for (i
= 0; i
< 32; ++i
)
7180 if ((mask
[j
] >> i
) & 1)
7183 if (TARGET_ABI_OPEN_VMS
)
7185 /* Start with a stack procedure if we make any calls (REG_RA used), or
7186 need a frame pointer, with a register procedure if we otherwise need
7187 at least a slot, and with a null procedure in other cases. */
7188 if ((mask
[0] >> REG_RA
) & 1 || frame_pointer_needed
)
7189 alpha_procedure_type
= PT_STACK
;
7190 else if (get_frame_size() != 0)
7191 alpha_procedure_type
= PT_REGISTER
;
7193 alpha_procedure_type
= PT_NULL
;
7195 /* Don't reserve space for saving FP & RA yet. Do that later after we've
7196 made the final decision on stack procedure vs register procedure. */
7197 if (alpha_procedure_type
== PT_STACK
)
7200 /* Decide whether to refer to objects off our PV via FP or PV.
7201 If we need FP for something else or if we receive a nonlocal
7202 goto (which expects PV to contain the value), we must use PV.
7203 Otherwise, start by assuming we can use FP. */
7206 = (frame_pointer_needed
7207 || cfun
->has_nonlocal_label
7208 || alpha_procedure_type
== PT_STACK
7209 || crtl
->outgoing_args_size
)
7210 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
7212 /* If we want to copy PV into FP, we need to find some register
7213 in which to save FP. */
7215 vms_save_fp_regno
= -1;
7216 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
7217 for (i
= 0; i
< 32; i
++)
7218 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! df_regs_ever_live_p (i
))
7219 vms_save_fp_regno
= i
;
7221 /* A VMS condition handler requires a stack procedure in our
7222 implementation. (not required by the calling standard). */
7223 if ((vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
7224 || cfun
->machine
->uses_condition_handler
)
7225 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
7226 else if (alpha_procedure_type
== PT_NULL
)
7227 vms_base_regno
= REG_PV
;
7229 /* Stack unwinding should be done via FP unless we use it for PV. */
7230 vms_unwind_regno
= (vms_base_regno
== REG_PV
7231 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
7233 /* If this is a stack procedure, allow space for saving FP, RA and
7234 a condition handler slot if needed. */
7235 if (alpha_procedure_type
== PT_STACK
)
7236 sa_size
+= 2 + cfun
->machine
->uses_condition_handler
;
7240 /* Our size must be even (multiple of 16 bytes). */
7248 /* Define the offset between two registers, one to be eliminated,
7249 and the other its replacement, at the start of a routine. */
7252 alpha_initial_elimination_offset (unsigned int from
,
7253 unsigned int to ATTRIBUTE_UNUSED
)
7257 ret
= alpha_sa_size ();
7258 ret
+= ALPHA_ROUND (crtl
->outgoing_args_size
);
7262 case FRAME_POINTER_REGNUM
:
7265 case ARG_POINTER_REGNUM
:
7266 ret
+= (ALPHA_ROUND (get_frame_size ()
7267 + crtl
->args
.pretend_args_size
)
7268 - crtl
->args
.pretend_args_size
);
7278 #if TARGET_ABI_OPEN_VMS
7280 /* Worker function for TARGET_CAN_ELIMINATE. */
7283 alpha_vms_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
7285 /* We need the alpha_procedure_type to decide. Evaluate it now. */
7288 switch (alpha_procedure_type
)
7291 /* NULL procedures have no frame of their own and we only
7292 know how to resolve from the current stack pointer. */
7293 return to
== STACK_POINTER_REGNUM
;
7297 /* We always eliminate except to the stack pointer if there is no
7298 usable frame pointer at hand. */
7299 return (to
!= STACK_POINTER_REGNUM
7300 || vms_unwind_regno
!= HARD_FRAME_POINTER_REGNUM
);
7306 /* FROM is to be eliminated for TO. Return the offset so that TO+offset
7307 designates the same location as FROM. */
7310 alpha_vms_initial_elimination_offset (unsigned int from
, unsigned int to
)
7312 /* The only possible attempts we ever expect are ARG or FRAME_PTR to
7313 HARD_FRAME or STACK_PTR. We need the alpha_procedure_type to decide
7314 on the proper computations and will need the register save area size
7317 HOST_WIDE_INT sa_size
= alpha_sa_size ();
7319 /* PT_NULL procedures have no frame of their own and we only allow
7320 elimination to the stack pointer. This is the argument pointer and we
7321 resolve the soft frame pointer to that as well. */
7323 if (alpha_procedure_type
== PT_NULL
)
7326 /* For a PT_STACK procedure the frame layout looks as follows
7328 -----> decreasing addresses
7330 < size rounded up to 16 | likewise >
7331 --------------#------------------------------+++--------------+++-------#
7332 incoming args # pretended args | "frame" | regs sa | PV | outgoing args #
7333 --------------#---------------------------------------------------------#
7335 ARG_PTR FRAME_PTR HARD_FRAME_PTR STACK_PTR
7338 PT_REGISTER procedures are similar in that they may have a frame of their
7339 own. They have no regs-sa/pv/outgoing-args area.
7341 We first compute offset to HARD_FRAME_PTR, then add what we need to get
7342 to STACK_PTR if need be. */
7345 HOST_WIDE_INT offset
;
7346 HOST_WIDE_INT pv_save_size
= alpha_procedure_type
== PT_STACK
? 8 : 0;
7350 case FRAME_POINTER_REGNUM
:
7351 offset
= ALPHA_ROUND (sa_size
+ pv_save_size
);
7353 case ARG_POINTER_REGNUM
:
7354 offset
= (ALPHA_ROUND (sa_size
+ pv_save_size
7356 + crtl
->args
.pretend_args_size
)
7357 - crtl
->args
.pretend_args_size
);
7363 if (to
== STACK_POINTER_REGNUM
)
7364 offset
+= ALPHA_ROUND (crtl
->outgoing_args_size
);
7370 #define COMMON_OBJECT "common_object"
7373 common_object_handler (tree
*node
, tree name ATTRIBUTE_UNUSED
,
7374 tree args ATTRIBUTE_UNUSED
, int flags ATTRIBUTE_UNUSED
,
7375 bool *no_add_attrs ATTRIBUTE_UNUSED
)
7378 gcc_assert (DECL_P (decl
));
7380 DECL_COMMON (decl
) = 1;
7384 static const struct attribute_spec vms_attribute_table
[] =
7386 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
7387 affects_type_identity } */
7388 { COMMON_OBJECT
, 0, 1, true, false, false, common_object_handler
, false },
7389 { NULL
, 0, 0, false, false, false, NULL
, false }
7393 vms_output_aligned_decl_common(FILE *file
, tree decl
, const char *name
,
7394 unsigned HOST_WIDE_INT size
,
7397 tree attr
= DECL_ATTRIBUTES (decl
);
7398 fprintf (file
, "%s", COMMON_ASM_OP
);
7399 assemble_name (file
, name
);
7400 fprintf (file
, "," HOST_WIDE_INT_PRINT_UNSIGNED
, size
);
7401 /* ??? Unlike on OSF/1, the alignment factor is not in log units. */
7402 fprintf (file
, ",%u", align
/ BITS_PER_UNIT
);
7405 attr
= lookup_attribute (COMMON_OBJECT
, attr
);
7407 fprintf (file
, ",%s",
7408 IDENTIFIER_POINTER (TREE_VALUE (TREE_VALUE (attr
))));
7413 #undef COMMON_OBJECT
7418 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
7420 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
7424 alpha_find_lo_sum_using_gp (rtx insn
)
7426 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
7430 alpha_does_function_need_gp (void)
7434 /* The GP being variable is an OSF abi thing. */
7435 if (! TARGET_ABI_OSF
)
7438 /* We need the gp to load the address of __mcount. */
7439 if (TARGET_PROFILING_NEEDS_GP
&& crtl
->profile
)
7442 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
7446 /* The nonlocal receiver pattern assumes that the gp is valid for
7447 the nested function. Reasonable because it's almost always set
7448 correctly already. For the cases where that's wrong, make sure
7449 the nested function loads its gp on entry. */
7450 if (crtl
->has_nonlocal_goto
)
7453 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7454 Even if we are a static function, we still need to do this in case
7455 our address is taken and passed to something like qsort. */
7457 push_topmost_sequence ();
7458 insn
= get_insns ();
7459 pop_topmost_sequence ();
7461 for (; insn
; insn
= NEXT_INSN (insn
))
7462 if (NONDEBUG_INSN_P (insn
)
7463 && ! JUMP_TABLE_DATA_P (insn
)
7464 && GET_CODE (PATTERN (insn
)) != USE
7465 && GET_CODE (PATTERN (insn
)) != CLOBBER
7466 && get_attr_usegp (insn
))
7473 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7477 set_frame_related_p (void)
7479 rtx seq
= get_insns ();
7490 while (insn
!= NULL_RTX
)
7492 RTX_FRAME_RELATED_P (insn
) = 1;
7493 insn
= NEXT_INSN (insn
);
7495 seq
= emit_insn (seq
);
7499 seq
= emit_insn (seq
);
7500 RTX_FRAME_RELATED_P (seq
) = 1;
7505 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7507 /* Generates a store with the proper unwind info attached. VALUE is
7508 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
7509 contains SP+FRAME_BIAS, and that is the unwind info that should be
7510 generated. If FRAME_REG != VALUE, then VALUE is being stored on
7511 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
7514 emit_frame_store_1 (rtx value
, rtx base_reg
, HOST_WIDE_INT frame_bias
,
7515 HOST_WIDE_INT base_ofs
, rtx frame_reg
)
7517 rtx addr
, mem
, insn
;
7519 addr
= plus_constant (base_reg
, base_ofs
);
7520 mem
= gen_frame_mem (DImode
, addr
);
7522 insn
= emit_move_insn (mem
, value
);
7523 RTX_FRAME_RELATED_P (insn
) = 1;
7525 if (frame_bias
|| value
!= frame_reg
)
7529 addr
= plus_constant (stack_pointer_rtx
, frame_bias
+ base_ofs
);
7530 mem
= gen_rtx_MEM (DImode
, addr
);
7533 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
7534 gen_rtx_SET (VOIDmode
, mem
, frame_reg
));
7539 emit_frame_store (unsigned int regno
, rtx base_reg
,
7540 HOST_WIDE_INT frame_bias
, HOST_WIDE_INT base_ofs
)
7542 rtx reg
= gen_rtx_REG (DImode
, regno
);
7543 emit_frame_store_1 (reg
, base_reg
, frame_bias
, base_ofs
, reg
);
7546 /* Compute the frame size. SIZE is the size of the "naked" frame
7547 and SA_SIZE is the size of the register save area. */
7549 static HOST_WIDE_INT
7550 compute_frame_size (HOST_WIDE_INT size
, HOST_WIDE_INT sa_size
)
7552 if (TARGET_ABI_OPEN_VMS
)
7553 return ALPHA_ROUND (sa_size
7554 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7556 + crtl
->args
.pretend_args_size
);
7558 return ALPHA_ROUND (crtl
->outgoing_args_size
)
7561 + crtl
->args
.pretend_args_size
);
7564 /* Write function prologue. */
7566 /* On vms we have two kinds of functions:
7568 - stack frame (PROC_STACK)
7569 these are 'normal' functions with local vars and which are
7570 calling other functions
7571 - register frame (PROC_REGISTER)
7572 keeps all data in registers, needs no stack
7574 We must pass this to the assembler so it can generate the
7575 proper pdsc (procedure descriptor)
7576 This is done with the '.pdesc' command.
7578 On not-vms, we don't really differentiate between the two, as we can
7579 simply allocate stack without saving registers. */
7582 alpha_expand_prologue (void)
7584 /* Registers to save. */
7585 unsigned long imask
= 0;
7586 unsigned long fmask
= 0;
7587 /* Stack space needed for pushing registers clobbered by us. */
7588 HOST_WIDE_INT sa_size
, sa_bias
;
7589 /* Complete stack size needed. */
7590 HOST_WIDE_INT frame_size
;
7591 /* Probed stack size; it additionally includes the size of
7592 the "reserve region" if any. */
7593 HOST_WIDE_INT probed_size
;
7594 /* Offset from base reg to register save area. */
7595 HOST_WIDE_INT reg_offset
;
7599 sa_size
= alpha_sa_size ();
7600 frame_size
= compute_frame_size (get_frame_size (), sa_size
);
7602 if (flag_stack_usage_info
)
7603 current_function_static_stack_size
= frame_size
;
7605 if (TARGET_ABI_OPEN_VMS
)
7606 reg_offset
= 8 + 8 * cfun
->machine
->uses_condition_handler
;
7608 reg_offset
= ALPHA_ROUND (crtl
->outgoing_args_size
);
7610 alpha_sa_mask (&imask
, &fmask
);
7612 /* Emit an insn to reload GP, if needed. */
7615 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7616 if (alpha_function_needs_gp
)
7617 emit_insn (gen_prologue_ldgp ());
7620 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7621 the call to mcount ourselves, rather than having the linker do it
7622 magically in response to -pg. Since _mcount has special linkage,
7623 don't represent the call as a call. */
7624 if (TARGET_PROFILING_NEEDS_GP
&& crtl
->profile
)
7625 emit_insn (gen_prologue_mcount ());
7627 /* Adjust the stack by the frame size. If the frame size is > 4096
7628 bytes, we need to be sure we probe somewhere in the first and last
7629 4096 bytes (we can probably get away without the latter test) and
7630 every 8192 bytes in between. If the frame size is > 32768, we
7631 do this in a loop. Otherwise, we generate the explicit probe
7634 Note that we are only allowed to adjust sp once in the prologue. */
7636 probed_size
= frame_size
;
7637 if (flag_stack_check
)
7638 probed_size
+= STACK_CHECK_PROTECT
;
7640 if (probed_size
<= 32768)
7642 if (probed_size
> 4096)
7646 for (probed
= 4096; probed
< probed_size
; probed
+= 8192)
7647 emit_insn (gen_probe_stack (GEN_INT (-probed
)));
7649 /* We only have to do this probe if we aren't saving registers or
7650 if we are probing beyond the frame because of -fstack-check. */
7651 if ((sa_size
== 0 && probed_size
> probed
- 4096)
7652 || flag_stack_check
)
7653 emit_insn (gen_probe_stack (GEN_INT (-probed_size
)));
7656 if (frame_size
!= 0)
7657 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7658 GEN_INT (-frame_size
))));
7662 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7663 number of 8192 byte blocks to probe. We then probe each block
7664 in the loop and then set SP to the proper location. If the
7665 amount remaining is > 4096, we have to do one more probe if we
7666 are not saving any registers or if we are probing beyond the
7667 frame because of -fstack-check. */
7669 HOST_WIDE_INT blocks
= (probed_size
+ 4096) / 8192;
7670 HOST_WIDE_INT leftover
= probed_size
+ 4096 - blocks
* 8192;
7671 rtx ptr
= gen_rtx_REG (DImode
, 22);
7672 rtx count
= gen_rtx_REG (DImode
, 23);
7675 emit_move_insn (count
, GEN_INT (blocks
));
7676 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
, GEN_INT (4096)));
7678 /* Because of the difficulty in emitting a new basic block this
7679 late in the compilation, generate the loop as a single insn. */
7680 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7682 if ((leftover
> 4096 && sa_size
== 0) || flag_stack_check
)
7684 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7685 MEM_VOLATILE_P (last
) = 1;
7686 emit_move_insn (last
, const0_rtx
);
7689 if (flag_stack_check
)
7691 /* If -fstack-check is specified we have to load the entire
7692 constant into a register and subtract from the sp in one go,
7693 because the probed stack size is not equal to the frame size. */
7694 HOST_WIDE_INT lo
, hi
;
7695 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7696 hi
= frame_size
- lo
;
7698 emit_move_insn (ptr
, GEN_INT (hi
));
7699 emit_insn (gen_adddi3 (ptr
, ptr
, GEN_INT (lo
)));
7700 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7705 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7706 GEN_INT (-leftover
)));
7709 /* This alternative is special, because the DWARF code cannot
7710 possibly intuit through the loop above. So we invent this
7711 note it looks at instead. */
7712 RTX_FRAME_RELATED_P (seq
) = 1;
7713 add_reg_note (seq
, REG_FRAME_RELATED_EXPR
,
7714 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7715 plus_constant (stack_pointer_rtx
,
7719 /* Cope with very large offsets to the register save area. */
7721 sa_reg
= stack_pointer_rtx
;
7722 if (reg_offset
+ sa_size
> 0x8000)
7724 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7727 if (low
+ sa_size
<= 0x8000)
7728 sa_bias
= reg_offset
- low
, reg_offset
= low
;
7730 sa_bias
= reg_offset
, reg_offset
= 0;
7732 sa_reg
= gen_rtx_REG (DImode
, 24);
7733 sa_bias_rtx
= GEN_INT (sa_bias
);
7735 if (add_operand (sa_bias_rtx
, DImode
))
7736 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_bias_rtx
));
7739 emit_move_insn (sa_reg
, sa_bias_rtx
);
7740 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_reg
));
7744 /* Save regs in stack order. Beginning with VMS PV. */
7745 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7746 emit_frame_store (REG_PV
, stack_pointer_rtx
, 0, 0);
7748 /* Save register RA next. */
7749 if (imask
& (1UL << REG_RA
))
7751 emit_frame_store (REG_RA
, sa_reg
, sa_bias
, reg_offset
);
7752 imask
&= ~(1UL << REG_RA
);
7756 /* Now save any other registers required to be saved. */
7757 for (i
= 0; i
< 31; i
++)
7758 if (imask
& (1UL << i
))
7760 emit_frame_store (i
, sa_reg
, sa_bias
, reg_offset
);
7764 for (i
= 0; i
< 31; i
++)
7765 if (fmask
& (1UL << i
))
7767 emit_frame_store (i
+32, sa_reg
, sa_bias
, reg_offset
);
7771 if (TARGET_ABI_OPEN_VMS
)
7773 /* Register frame procedures save the fp. */
7774 if (alpha_procedure_type
== PT_REGISTER
)
7776 rtx insn
= emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7777 hard_frame_pointer_rtx
);
7778 add_reg_note (insn
, REG_CFA_REGISTER
, NULL
);
7779 RTX_FRAME_RELATED_P (insn
) = 1;
7782 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7783 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7784 gen_rtx_REG (DImode
, REG_PV
)));
7786 if (alpha_procedure_type
!= PT_NULL
7787 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7788 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7790 /* If we have to allocate space for outgoing args, do it now. */
7791 if (crtl
->outgoing_args_size
!= 0)
7794 = emit_move_insn (stack_pointer_rtx
,
7796 (hard_frame_pointer_rtx
,
7798 (crtl
->outgoing_args_size
))));
7800 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7801 if ! frame_pointer_needed. Setting the bit will change the CFA
7802 computation rule to use sp again, which would be wrong if we had
7803 frame_pointer_needed, as this means sp might move unpredictably
7807 frame_pointer_needed
7808 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7810 crtl->outgoing_args_size != 0
7811 => alpha_procedure_type != PT_NULL,
7813 so when we are not setting the bit here, we are guaranteed to
7814 have emitted an FRP frame pointer update just before. */
7815 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7820 /* If we need a frame pointer, set it from the stack pointer. */
7821 if (frame_pointer_needed
)
7823 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7824 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7826 /* This must always be the last instruction in the
7827 prologue, thus we emit a special move + clobber. */
7828 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7829 stack_pointer_rtx
, sa_reg
)));
7833 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7834 the prologue, for exception handling reasons, we cannot do this for
7835 any insn that might fault. We could prevent this for mems with a
7836 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7837 have to prevent all such scheduling with a blockage.
7839 Linux, on the other hand, never bothered to implement OSF/1's
7840 exception handling, and so doesn't care about such things. Anyone
7841 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7843 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7844 emit_insn (gen_blockage ());
7847 /* Count the number of .file directives, so that .loc is up to date. */
7848 int num_source_filenames
= 0;
7850 /* Output the textual info surrounding the prologue. */
7853 alpha_start_function (FILE *file
, const char *fnname
,
7854 tree decl ATTRIBUTE_UNUSED
)
7856 unsigned long imask
= 0;
7857 unsigned long fmask
= 0;
7858 /* Stack space needed for pushing registers clobbered by us. */
7859 HOST_WIDE_INT sa_size
;
7860 /* Complete stack size needed. */
7861 unsigned HOST_WIDE_INT frame_size
;
7862 /* The maximum debuggable frame size. */
7863 unsigned HOST_WIDE_INT max_frame_size
= 1UL << 31;
7864 /* Offset from base reg to register save area. */
7865 HOST_WIDE_INT reg_offset
;
7866 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7867 char *tramp_label
= (char *) alloca (strlen (fnname
) + 6);
7870 #if TARGET_ABI_OPEN_VMS
7872 && strncmp (vms_debug_main
, fnname
, strlen (vms_debug_main
)) == 0)
7874 targetm
.asm_out
.globalize_label (asm_out_file
, VMS_DEBUG_MAIN_POINTER
);
7875 ASM_OUTPUT_DEF (asm_out_file
, VMS_DEBUG_MAIN_POINTER
, fnname
);
7876 switch_to_section (text_section
);
7877 vms_debug_main
= NULL
;
7881 alpha_fnname
= fnname
;
7882 sa_size
= alpha_sa_size ();
7883 frame_size
= compute_frame_size (get_frame_size (), sa_size
);
7885 if (TARGET_ABI_OPEN_VMS
)
7886 reg_offset
= 8 + 8 * cfun
->machine
->uses_condition_handler
;
7888 reg_offset
= ALPHA_ROUND (crtl
->outgoing_args_size
);
7890 alpha_sa_mask (&imask
, &fmask
);
7892 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7893 We have to do that before the .ent directive as we cannot switch
7894 files within procedures with native ecoff because line numbers are
7895 linked to procedure descriptors.
7896 Outputting the lineno helps debugging of one line functions as they
7897 would otherwise get no line number at all. Please note that we would
7898 like to put out last_linenum from final.c, but it is not accessible. */
7900 if (write_symbols
== SDB_DEBUG
)
7902 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7903 ASM_OUTPUT_SOURCE_FILENAME (file
,
7904 DECL_SOURCE_FILE (current_function_decl
));
7906 #ifdef SDB_OUTPUT_SOURCE_LINE
7907 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7908 SDB_OUTPUT_SOURCE_LINE (file
,
7909 DECL_SOURCE_LINE (current_function_decl
));
7913 /* Issue function start and label. */
7914 if (TARGET_ABI_OPEN_VMS
|| !flag_inhibit_size_directive
)
7916 fputs ("\t.ent ", file
);
7917 assemble_name (file
, fnname
);
7920 /* If the function needs GP, we'll write the "..ng" label there.
7921 Otherwise, do it here. */
7923 && ! alpha_function_needs_gp
7924 && ! cfun
->is_thunk
)
7927 assemble_name (file
, fnname
);
7928 fputs ("..ng:\n", file
);
7931 /* Nested functions on VMS that are potentially called via trampoline
7932 get a special transfer entry point that loads the called functions
7933 procedure descriptor and static chain. */
7934 if (TARGET_ABI_OPEN_VMS
7935 && !TREE_PUBLIC (decl
)
7936 && DECL_CONTEXT (decl
)
7937 && !TYPE_P (DECL_CONTEXT (decl
))
7938 && TREE_CODE (DECL_CONTEXT (decl
)) != TRANSLATION_UNIT_DECL
)
7940 strcpy (tramp_label
, fnname
);
7941 strcat (tramp_label
, "..tr");
7942 ASM_OUTPUT_LABEL (file
, tramp_label
);
7943 fprintf (file
, "\tldq $1,24($27)\n");
7944 fprintf (file
, "\tldq $27,16($27)\n");
7947 strcpy (entry_label
, fnname
);
7948 if (TARGET_ABI_OPEN_VMS
)
7949 strcat (entry_label
, "..en");
7951 ASM_OUTPUT_LABEL (file
, entry_label
);
7952 inside_function
= TRUE
;
7954 if (TARGET_ABI_OPEN_VMS
)
7955 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7958 && TARGET_IEEE_CONFORMANT
7959 && !flag_inhibit_size_directive
)
7961 /* Set flags in procedure descriptor to request IEEE-conformant
7962 math-library routines. The value we set it to is PDSC_EXC_IEEE
7963 (/usr/include/pdsc.h). */
7964 fputs ("\t.eflag 48\n", file
);
7967 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7968 alpha_auto_offset
= -frame_size
+ crtl
->args
.pretend_args_size
;
7969 alpha_arg_offset
= -frame_size
+ 48;
7971 /* Describe our frame. If the frame size is larger than an integer,
7972 print it as zero to avoid an assembler error. We won't be
7973 properly describing such a frame, but that's the best we can do. */
7974 if (TARGET_ABI_OPEN_VMS
)
7975 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
7976 HOST_WIDE_INT_PRINT_DEC
"\n",
7978 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7980 else if (!flag_inhibit_size_directive
)
7981 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
7982 (frame_pointer_needed
7983 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
7984 frame_size
>= max_frame_size
? 0 : frame_size
,
7985 crtl
->args
.pretend_args_size
);
7987 /* Describe which registers were spilled. */
7988 if (TARGET_ABI_OPEN_VMS
)
7991 /* ??? Does VMS care if mask contains ra? The old code didn't
7992 set it, so I don't here. */
7993 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
7995 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7996 if (alpha_procedure_type
== PT_REGISTER
)
7997 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7999 else if (!flag_inhibit_size_directive
)
8003 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
8004 frame_size
>= max_frame_size
? 0 : reg_offset
- frame_size
);
8006 for (i
= 0; i
< 32; ++i
)
8007 if (imask
& (1UL << i
))
8012 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
8013 frame_size
>= max_frame_size
? 0 : reg_offset
- frame_size
);
8016 #if TARGET_ABI_OPEN_VMS
8017 /* If a user condition handler has been installed at some point, emit
8018 the procedure descriptor bits to point the Condition Handling Facility
8019 at the indirection wrapper, and state the fp offset at which the user
8020 handler may be found. */
8021 if (cfun
->machine
->uses_condition_handler
)
8023 fprintf (file
, "\t.handler __gcc_shell_handler\n");
8024 fprintf (file
, "\t.handler_data %d\n", VMS_COND_HANDLER_FP_OFFSET
);
8027 #ifdef TARGET_VMS_CRASH_DEBUG
8028 /* Support of minimal traceback info. */
8029 switch_to_section (readonly_data_section
);
8030 fprintf (file
, "\t.align 3\n");
8031 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
8032 fputs ("\t.ascii \"", file
);
8033 assemble_name (file
, fnname
);
8034 fputs ("\\0\"\n", file
);
8035 switch_to_section (text_section
);
8037 #endif /* TARGET_ABI_OPEN_VMS */
8040 /* Emit the .prologue note at the scheduled end of the prologue. */
8043 alpha_output_function_end_prologue (FILE *file
)
8045 if (TARGET_ABI_OPEN_VMS
)
8046 fputs ("\t.prologue\n", file
);
8047 else if (!flag_inhibit_size_directive
)
8048 fprintf (file
, "\t.prologue %d\n",
8049 alpha_function_needs_gp
|| cfun
->is_thunk
);
8052 /* Write function epilogue. */
8055 alpha_expand_epilogue (void)
8057 /* Registers to save. */
8058 unsigned long imask
= 0;
8059 unsigned long fmask
= 0;
8060 /* Stack space needed for pushing registers clobbered by us. */
8061 HOST_WIDE_INT sa_size
;
8062 /* Complete stack size needed. */
8063 HOST_WIDE_INT frame_size
;
8064 /* Offset from base reg to register save area. */
8065 HOST_WIDE_INT reg_offset
;
8066 int fp_is_frame_pointer
, fp_offset
;
8067 rtx sa_reg
, sa_reg_exp
= NULL
;
8068 rtx sp_adj1
, sp_adj2
, mem
, reg
, insn
;
8070 rtx cfa_restores
= NULL_RTX
;
8073 sa_size
= alpha_sa_size ();
8074 frame_size
= compute_frame_size (get_frame_size (), sa_size
);
8076 if (TARGET_ABI_OPEN_VMS
)
8078 if (alpha_procedure_type
== PT_STACK
)
8079 reg_offset
= 8 + 8 * cfun
->machine
->uses_condition_handler
;
8084 reg_offset
= ALPHA_ROUND (crtl
->outgoing_args_size
);
8086 alpha_sa_mask (&imask
, &fmask
);
8089 = (TARGET_ABI_OPEN_VMS
8090 ? alpha_procedure_type
== PT_STACK
8091 : frame_pointer_needed
);
8093 sa_reg
= stack_pointer_rtx
;
8095 if (crtl
->calls_eh_return
)
8096 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
8102 /* If we have a frame pointer, restore SP from it. */
8103 if (TARGET_ABI_OPEN_VMS
8104 ? vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
8105 : frame_pointer_needed
)
8106 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
8108 /* Cope with very large offsets to the register save area. */
8109 if (reg_offset
+ sa_size
> 0x8000)
8111 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
8114 if (low
+ sa_size
<= 0x8000)
8115 bias
= reg_offset
- low
, reg_offset
= low
;
8117 bias
= reg_offset
, reg_offset
= 0;
8119 sa_reg
= gen_rtx_REG (DImode
, 22);
8120 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
8122 emit_move_insn (sa_reg
, sa_reg_exp
);
8125 /* Restore registers in order, excepting a true frame pointer. */
8127 mem
= gen_frame_mem (DImode
, plus_constant (sa_reg
, reg_offset
));
8128 reg
= gen_rtx_REG (DImode
, REG_RA
);
8129 emit_move_insn (reg
, mem
);
8130 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8133 imask
&= ~(1UL << REG_RA
);
8135 for (i
= 0; i
< 31; ++i
)
8136 if (imask
& (1UL << i
))
8138 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
8139 fp_offset
= reg_offset
;
8142 mem
= gen_frame_mem (DImode
,
8143 plus_constant (sa_reg
, reg_offset
));
8144 reg
= gen_rtx_REG (DImode
, i
);
8145 emit_move_insn (reg
, mem
);
8146 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
8152 for (i
= 0; i
< 31; ++i
)
8153 if (fmask
& (1UL << i
))
8155 mem
= gen_frame_mem (DFmode
, plus_constant (sa_reg
, reg_offset
));
8156 reg
= gen_rtx_REG (DFmode
, i
+32);
8157 emit_move_insn (reg
, mem
);
8158 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8163 if (frame_size
|| eh_ofs
)
8165 sp_adj1
= stack_pointer_rtx
;
8169 sp_adj1
= gen_rtx_REG (DImode
, 23);
8170 emit_move_insn (sp_adj1
,
8171 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
8174 /* If the stack size is large, begin computation into a temporary
8175 register so as not to interfere with a potential fp restore,
8176 which must be consecutive with an SP restore. */
8177 if (frame_size
< 32768 && !cfun
->calls_alloca
)
8178 sp_adj2
= GEN_INT (frame_size
);
8179 else if (frame_size
< 0x40007fffL
)
8181 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
8183 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
8184 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
8188 sp_adj1
= gen_rtx_REG (DImode
, 23);
8189 emit_move_insn (sp_adj1
, sp_adj2
);
8191 sp_adj2
= GEN_INT (low
);
8195 rtx tmp
= gen_rtx_REG (DImode
, 23);
8196 sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3, false);
8199 /* We can't drop new things to memory this late, afaik,
8200 so build it up by pieces. */
8201 sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
8203 gcc_assert (sp_adj2
);
8207 /* From now on, things must be in order. So emit blockages. */
8209 /* Restore the frame pointer. */
8210 if (fp_is_frame_pointer
)
8212 emit_insn (gen_blockage ());
8213 mem
= gen_frame_mem (DImode
, plus_constant (sa_reg
, fp_offset
));
8214 emit_move_insn (hard_frame_pointer_rtx
, mem
);
8215 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
8216 hard_frame_pointer_rtx
, cfa_restores
);
8218 else if (TARGET_ABI_OPEN_VMS
)
8220 emit_insn (gen_blockage ());
8221 emit_move_insn (hard_frame_pointer_rtx
,
8222 gen_rtx_REG (DImode
, vms_save_fp_regno
));
8223 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
8224 hard_frame_pointer_rtx
, cfa_restores
);
8227 /* Restore the stack pointer. */
8228 emit_insn (gen_blockage ());
8229 if (sp_adj2
== const0_rtx
)
8230 insn
= emit_move_insn (stack_pointer_rtx
, sp_adj1
);
8232 insn
= emit_move_insn (stack_pointer_rtx
,
8233 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
));
8234 REG_NOTES (insn
) = cfa_restores
;
8235 add_reg_note (insn
, REG_CFA_DEF_CFA
, stack_pointer_rtx
);
8236 RTX_FRAME_RELATED_P (insn
) = 1;
8240 gcc_assert (cfa_restores
== NULL
);
8242 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
8244 emit_insn (gen_blockage ());
8245 insn
= emit_move_insn (hard_frame_pointer_rtx
,
8246 gen_rtx_REG (DImode
, vms_save_fp_regno
));
8247 add_reg_note (insn
, REG_CFA_RESTORE
, hard_frame_pointer_rtx
);
8248 RTX_FRAME_RELATED_P (insn
) = 1;
8253 /* Output the rest of the textual info surrounding the epilogue. */
8256 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
8260 /* We output a nop after noreturn calls at the very end of the function to
8261 ensure that the return address always remains in the caller's code range,
8262 as not doing so might confuse unwinding engines. */
8263 insn
= get_last_insn ();
8265 insn
= prev_active_insn (insn
);
8266 if (insn
&& CALL_P (insn
))
8267 output_asm_insn (get_insn_template (CODE_FOR_nop
, NULL
), NULL
);
8269 #if TARGET_ABI_OPEN_VMS
8270 /* Write the linkage entries. */
8271 alpha_write_linkage (file
, fnname
);
8274 /* End the function. */
8275 if (TARGET_ABI_OPEN_VMS
8276 || !flag_inhibit_size_directive
)
8278 fputs ("\t.end ", file
);
8279 assemble_name (file
, fnname
);
8282 inside_function
= FALSE
;
8286 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
8288 In order to avoid the hordes of differences between generated code
8289 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
8290 lots of code loading up large constants, generate rtl and emit it
8291 instead of going straight to text.
8293 Not sure why this idea hasn't been explored before... */
8296 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
8297 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8300 HOST_WIDE_INT hi
, lo
;
8301 rtx this_rtx
, insn
, funexp
;
8303 /* We always require a valid GP. */
8304 emit_insn (gen_prologue_ldgp ());
8305 emit_note (NOTE_INSN_PROLOGUE_END
);
8307 /* Find the "this" pointer. If the function returns a structure,
8308 the structure return pointer is in $16. */
8309 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8310 this_rtx
= gen_rtx_REG (Pmode
, 17);
8312 this_rtx
= gen_rtx_REG (Pmode
, 16);
8314 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8315 entire constant for the add. */
8316 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
8317 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8318 if (hi
+ lo
== delta
)
8321 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, GEN_INT (hi
)));
8323 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, GEN_INT (lo
)));
8327 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
8328 delta
, -(delta
< 0));
8329 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, tmp
));
8332 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8337 tmp
= gen_rtx_REG (Pmode
, 0);
8338 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
8340 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
8341 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8342 if (hi
+ lo
== vcall_offset
)
8345 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
8349 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
8350 vcall_offset
, -(vcall_offset
< 0));
8351 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
8355 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
8358 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
8360 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, tmp
));
8363 /* Generate a tail call to the target function. */
8364 if (! TREE_USED (function
))
8366 assemble_external (function
);
8367 TREE_USED (function
) = 1;
8369 funexp
= XEXP (DECL_RTL (function
), 0);
8370 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8371 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
8372 SIBLING_CALL_P (insn
) = 1;
8374 /* Run just enough of rest_of_compilation to get the insns emitted.
8375 There's not really enough bulk here to make other passes such as
8376 instruction scheduling worth while. Note that use_thunk calls
8377 assemble_start_function and assemble_end_function. */
8378 insn
= get_insns ();
8379 insn_locators_alloc ();
8380 shorten_branches (insn
);
8381 final_start_function (insn
, file
, 1);
8382 final (insn
, file
, 1);
8383 final_end_function ();
8385 #endif /* TARGET_ABI_OSF */
8387 /* Debugging support. */
8391 /* Count the number of sdb related labels are generated (to find block
8392 start and end boundaries). */
8394 int sdb_label_count
= 0;
8396 /* Name of the file containing the current function. */
8398 static const char *current_function_file
= "";
8400 /* Offsets to alpha virtual arg/local debugging pointers. */
8402 long alpha_arg_offset
;
8403 long alpha_auto_offset
;
8405 /* Emit a new filename to a stream. */
8408 alpha_output_filename (FILE *stream
, const char *name
)
8410 static int first_time
= TRUE
;
8415 ++num_source_filenames
;
8416 current_function_file
= name
;
8417 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8418 output_quoted_string (stream
, name
);
8419 fprintf (stream
, "\n");
8420 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8421 fprintf (stream
, "\t#@stabs\n");
8424 else if (write_symbols
== DBX_DEBUG
)
8425 /* dbxout.c will emit an appropriate .stabs directive. */
8428 else if (name
!= current_function_file
8429 && strcmp (name
, current_function_file
) != 0)
8431 if (inside_function
&& ! TARGET_GAS
)
8432 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8435 ++num_source_filenames
;
8436 current_function_file
= name
;
8437 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8440 output_quoted_string (stream
, name
);
8441 fprintf (stream
, "\n");
8445 /* Structure to show the current status of registers and memory. */
8447 struct shadow_summary
8450 unsigned int i
: 31; /* Mask of int regs */
8451 unsigned int fp
: 31; /* Mask of fp regs */
8452 unsigned int mem
: 1; /* mem == imem | fpmem */
8456 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8457 to the summary structure. SET is nonzero if the insn is setting the
8458 object, otherwise zero. */
8461 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
8463 const char *format_ptr
;
8469 switch (GET_CODE (x
))
8471 /* ??? Note that this case would be incorrect if the Alpha had a
8472 ZERO_EXTRACT in SET_DEST. */
8474 summarize_insn (SET_SRC (x
), sum
, 0);
8475 summarize_insn (SET_DEST (x
), sum
, 1);
8479 summarize_insn (XEXP (x
, 0), sum
, 1);
8483 summarize_insn (XEXP (x
, 0), sum
, 0);
8487 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8488 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8492 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8493 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8497 summarize_insn (SUBREG_REG (x
), sum
, 0);
8502 int regno
= REGNO (x
);
8503 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8505 if (regno
== 31 || regno
== 63)
8511 sum
->defd
.i
|= mask
;
8513 sum
->defd
.fp
|= mask
;
8518 sum
->used
.i
|= mask
;
8520 sum
->used
.fp
|= mask
;
8531 /* Find the regs used in memory address computation: */
8532 summarize_insn (XEXP (x
, 0), sum
, 0);
8535 case CONST_INT
: case CONST_DOUBLE
:
8536 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8537 case SCRATCH
: case ASM_INPUT
:
8540 /* Handle common unary and binary ops for efficiency. */
8541 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8542 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8543 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8544 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8545 case NE
: case EQ
: case GE
: case GT
: case LE
:
8546 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8547 summarize_insn (XEXP (x
, 0), sum
, 0);
8548 summarize_insn (XEXP (x
, 1), sum
, 0);
8551 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8552 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8553 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8554 case SQRT
: case FFS
:
8555 summarize_insn (XEXP (x
, 0), sum
, 0);
8559 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8560 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8561 switch (format_ptr
[i
])
8564 summarize_insn (XEXP (x
, i
), sum
, 0);
8568 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8569 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8581 /* Ensure a sufficient number of `trapb' insns are in the code when
8582 the user requests code with a trap precision of functions or
8585 In naive mode, when the user requests a trap-precision of
8586 "instruction", a trapb is needed after every instruction that may
8587 generate a trap. This ensures that the code is resumption safe but
8590 When optimizations are turned on, we delay issuing a trapb as long
8591 as possible. In this context, a trap shadow is the sequence of
8592 instructions that starts with a (potentially) trap generating
8593 instruction and extends to the next trapb or call_pal instruction
8594 (but GCC never generates call_pal by itself). We can delay (and
8595 therefore sometimes omit) a trapb subject to the following
8598 (a) On entry to the trap shadow, if any Alpha register or memory
8599 location contains a value that is used as an operand value by some
8600 instruction in the trap shadow (live on entry), then no instruction
8601 in the trap shadow may modify the register or memory location.
8603 (b) Within the trap shadow, the computation of the base register
8604 for a memory load or store instruction may not involve using the
8605 result of an instruction that might generate an UNPREDICTABLE
8608 (c) Within the trap shadow, no register may be used more than once
8609 as a destination register. (This is to make life easier for the
8612 (d) The trap shadow may not include any branch instructions. */
8615 alpha_handle_trap_shadows (void)
8617 struct shadow_summary shadow
;
8618 int trap_pending
, exception_nesting
;
8622 exception_nesting
= 0;
8625 shadow
.used
.mem
= 0;
8626 shadow
.defd
= shadow
.used
;
8628 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8632 switch (NOTE_KIND (i
))
8634 case NOTE_INSN_EH_REGION_BEG
:
8635 exception_nesting
++;
8640 case NOTE_INSN_EH_REGION_END
:
8641 exception_nesting
--;
8646 case NOTE_INSN_EPILOGUE_BEG
:
8647 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8652 else if (trap_pending
)
8654 if (alpha_tp
== ALPHA_TP_FUNC
)
8657 && GET_CODE (PATTERN (i
)) == RETURN
)
8660 else if (alpha_tp
== ALPHA_TP_INSN
)
8664 struct shadow_summary sum
;
8669 sum
.defd
= sum
.used
;
8671 switch (GET_CODE (i
))
8674 /* Annoyingly, get_attr_trap will die on these. */
8675 if (GET_CODE (PATTERN (i
)) == USE
8676 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8679 summarize_insn (PATTERN (i
), &sum
, 0);
8681 if ((sum
.defd
.i
& shadow
.defd
.i
)
8682 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8684 /* (c) would be violated */
8688 /* Combine shadow with summary of current insn: */
8689 shadow
.used
.i
|= sum
.used
.i
;
8690 shadow
.used
.fp
|= sum
.used
.fp
;
8691 shadow
.used
.mem
|= sum
.used
.mem
;
8692 shadow
.defd
.i
|= sum
.defd
.i
;
8693 shadow
.defd
.fp
|= sum
.defd
.fp
;
8694 shadow
.defd
.mem
|= sum
.defd
.mem
;
8696 if ((sum
.defd
.i
& shadow
.used
.i
)
8697 || (sum
.defd
.fp
& shadow
.used
.fp
)
8698 || (sum
.defd
.mem
& shadow
.used
.mem
))
8700 /* (a) would be violated (also takes care of (b)) */
8701 gcc_assert (get_attr_trap (i
) != TRAP_YES
8702 || (!(sum
.defd
.i
& sum
.used
.i
)
8703 && !(sum
.defd
.fp
& sum
.used
.fp
)));
8721 n
= emit_insn_before (gen_trapb (), i
);
8722 PUT_MODE (n
, TImode
);
8723 PUT_MODE (i
, TImode
);
8727 shadow
.used
.mem
= 0;
8728 shadow
.defd
= shadow
.used
;
8733 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8734 && NONJUMP_INSN_P (i
)
8735 && GET_CODE (PATTERN (i
)) != USE
8736 && GET_CODE (PATTERN (i
)) != CLOBBER
8737 && get_attr_trap (i
) == TRAP_YES
)
8739 if (optimize
&& !trap_pending
)
8740 summarize_insn (PATTERN (i
), &shadow
, 0);
8746 /* Alpha can only issue instruction groups simultaneously if they are
8747 suitably aligned. This is very processor-specific. */
8748 /* There are a number of entries in alphaev4_insn_pipe and alphaev5_insn_pipe
8749 that are marked "fake". These instructions do not exist on that target,
8750 but it is possible to see these insns with deranged combinations of
8751 command-line options, such as "-mtune=ev4 -mmax". Instead of aborting,
8752 choose a result at random. */
8754 enum alphaev4_pipe
{
8761 enum alphaev5_pipe
{
8772 static enum alphaev4_pipe
8773 alphaev4_insn_pipe (rtx insn
)
8775 if (recog_memoized (insn
) < 0)
8777 if (get_attr_length (insn
) != 4)
8780 switch (get_attr_type (insn
))
8796 case TYPE_MVI
: /* fake */
8811 case TYPE_FSQRT
: /* fake */
8812 case TYPE_FTOI
: /* fake */
8813 case TYPE_ITOF
: /* fake */
8821 static enum alphaev5_pipe
8822 alphaev5_insn_pipe (rtx insn
)
8824 if (recog_memoized (insn
) < 0)
8826 if (get_attr_length (insn
) != 4)
8829 switch (get_attr_type (insn
))
8849 case TYPE_FTOI
: /* fake */
8850 case TYPE_ITOF
: /* fake */
8865 case TYPE_FSQRT
: /* fake */
8876 /* IN_USE is a mask of the slots currently filled within the insn group.
8877 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8878 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8880 LEN is, of course, the length of the group in bytes. */
8883 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
8890 || GET_CODE (PATTERN (insn
)) == CLOBBER
8891 || GET_CODE (PATTERN (insn
)) == USE
)
8896 enum alphaev4_pipe pipe
;
8898 pipe
= alphaev4_insn_pipe (insn
);
8902 /* Force complex instructions to start new groups. */
8906 /* If this is a completely unrecognized insn, it's an asm.
8907 We don't know how long it is, so record length as -1 to
8908 signal a needed realignment. */
8909 if (recog_memoized (insn
) < 0)
8912 len
= get_attr_length (insn
);
8916 if (in_use
& EV4_IB0
)
8918 if (in_use
& EV4_IB1
)
8923 in_use
|= EV4_IB0
| EV4_IBX
;
8927 if (in_use
& EV4_IB0
)
8929 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8937 if (in_use
& EV4_IB1
)
8947 /* Haifa doesn't do well scheduling branches. */
8952 insn
= next_nonnote_insn (insn
);
8954 if (!insn
|| ! INSN_P (insn
))
8957 /* Let Haifa tell us where it thinks insn group boundaries are. */
8958 if (GET_MODE (insn
) == TImode
)
8961 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8966 insn
= next_nonnote_insn (insn
);
8974 /* IN_USE is a mask of the slots currently filled within the insn group.
8975 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8976 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8978 LEN is, of course, the length of the group in bytes. */
8981 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
8988 || GET_CODE (PATTERN (insn
)) == CLOBBER
8989 || GET_CODE (PATTERN (insn
)) == USE
)
8994 enum alphaev5_pipe pipe
;
8996 pipe
= alphaev5_insn_pipe (insn
);
9000 /* Force complex instructions to start new groups. */
9004 /* If this is a completely unrecognized insn, it's an asm.
9005 We don't know how long it is, so record length as -1 to
9006 signal a needed realignment. */
9007 if (recog_memoized (insn
) < 0)
9010 len
= get_attr_length (insn
);
9013 /* ??? Most of the places below, we would like to assert never
9014 happen, as it would indicate an error either in Haifa, or
9015 in the scheduling description. Unfortunately, Haifa never
9016 schedules the last instruction of the BB, so we don't have
9017 an accurate TI bit to go off. */
9019 if (in_use
& EV5_E0
)
9021 if (in_use
& EV5_E1
)
9026 in_use
|= EV5_E0
| EV5_E01
;
9030 if (in_use
& EV5_E0
)
9032 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
9040 if (in_use
& EV5_E1
)
9046 if (in_use
& EV5_FA
)
9048 if (in_use
& EV5_FM
)
9053 in_use
|= EV5_FA
| EV5_FAM
;
9057 if (in_use
& EV5_FA
)
9063 if (in_use
& EV5_FM
)
9076 /* Haifa doesn't do well scheduling branches. */
9077 /* ??? If this is predicted not-taken, slotting continues, except
9078 that no more IBR, FBR, or JSR insns may be slotted. */
9083 insn
= next_nonnote_insn (insn
);
9085 if (!insn
|| ! INSN_P (insn
))
9088 /* Let Haifa tell us where it thinks insn group boundaries are. */
9089 if (GET_MODE (insn
) == TImode
)
9092 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
9097 insn
= next_nonnote_insn (insn
);
9106 alphaev4_next_nop (int *pin_use
)
9108 int in_use
= *pin_use
;
9111 if (!(in_use
& EV4_IB0
))
9116 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
9121 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
9134 alphaev5_next_nop (int *pin_use
)
9136 int in_use
= *pin_use
;
9139 if (!(in_use
& EV5_E1
))
9144 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
9149 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
9161 /* The instruction group alignment main loop. */
9164 alpha_align_insns (unsigned int max_align
,
9165 rtx (*next_group
) (rtx
, int *, int *),
9166 rtx (*next_nop
) (int *))
9168 /* ALIGN is the known alignment for the insn group. */
9170 /* OFS is the offset of the current insn in the insn group. */
9172 int prev_in_use
, in_use
, len
, ldgp
;
9175 /* Let shorten branches care for assigning alignments to code labels. */
9176 shorten_branches (get_insns ());
9178 if (align_functions
< 4)
9180 else if ((unsigned int) align_functions
< max_align
)
9181 align
= align_functions
;
9185 ofs
= prev_in_use
= 0;
9188 i
= next_nonnote_insn (i
);
9190 ldgp
= alpha_function_needs_gp
? 8 : 0;
9194 next
= (*next_group
) (i
, &in_use
, &len
);
9196 /* When we see a label, resync alignment etc. */
9199 unsigned int new_align
= 1 << label_to_alignment (i
);
9201 if (new_align
>= align
)
9203 align
= new_align
< max_align
? new_align
: max_align
;
9207 else if (ofs
& (new_align
-1))
9208 ofs
= (ofs
| (new_align
-1)) + 1;
9212 /* Handle complex instructions special. */
9213 else if (in_use
== 0)
9215 /* Asms will have length < 0. This is a signal that we have
9216 lost alignment knowledge. Assume, however, that the asm
9217 will not mis-align instructions. */
9226 /* If the known alignment is smaller than the recognized insn group,
9227 realign the output. */
9228 else if ((int) align
< len
)
9230 unsigned int new_log_align
= len
> 8 ? 4 : 3;
9233 where
= prev
= prev_nonnote_insn (i
);
9234 if (!where
|| !LABEL_P (where
))
9237 /* Can't realign between a call and its gp reload. */
9238 if (! (TARGET_EXPLICIT_RELOCS
9239 && prev
&& CALL_P (prev
)))
9241 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
9242 align
= 1 << new_log_align
;
9247 /* We may not insert padding inside the initial ldgp sequence. */
9251 /* If the group won't fit in the same INT16 as the previous,
9252 we need to add padding to keep the group together. Rather
9253 than simply leaving the insn filling to the assembler, we
9254 can make use of the knowledge of what sorts of instructions
9255 were issued in the previous group to make sure that all of
9256 the added nops are really free. */
9257 else if (ofs
+ len
> (int) align
)
9259 int nop_count
= (align
- ofs
) / 4;
9262 /* Insert nops before labels, branches, and calls to truly merge
9263 the execution of the nops with the previous instruction group. */
9264 where
= prev_nonnote_insn (i
);
9267 if (LABEL_P (where
))
9269 rtx where2
= prev_nonnote_insn (where
);
9270 if (where2
&& JUMP_P (where2
))
9273 else if (NONJUMP_INSN_P (where
))
9280 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
9281 while (--nop_count
);
9285 ofs
= (ofs
+ len
) & (align
- 1);
9286 prev_in_use
= in_use
;
9291 /* Insert an unop between a noreturn function call and GP load. */
9294 alpha_pad_noreturn (void)
9298 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9300 if (! (CALL_P (insn
)
9301 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
)))
9304 /* Make sure we do not split a call and its corresponding
9305 CALL_ARG_LOCATION note. */
9308 next
= NEXT_INSN (insn
);
9309 if (next
&& NOTE_P (next
)
9310 && NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
)
9314 next
= next_active_insn (insn
);
9318 rtx pat
= PATTERN (next
);
9320 if (GET_CODE (pat
) == SET
9321 && GET_CODE (SET_SRC (pat
)) == UNSPEC_VOLATILE
9322 && XINT (SET_SRC (pat
), 1) == UNSPECV_LDGP1
)
9323 emit_insn_after (gen_unop (), insn
);
9328 /* Machine dependent reorg pass. */
9333 /* Workaround for a linker error that triggers when an
9334 exception handler immediatelly follows a noreturn function.
9336 The instruction stream from an object file:
9338 54: 00 40 5b 6b jsr ra,(t12),58 <__func+0x58>
9339 58: 00 00 ba 27 ldah gp,0(ra)
9340 5c: 00 00 bd 23 lda gp,0(gp)
9341 60: 00 00 7d a7 ldq t12,0(gp)
9342 64: 00 40 5b 6b jsr ra,(t12),68 <__func+0x68>
9344 was converted in the final link pass to:
9346 fdb24: a0 03 40 d3 bsr ra,fe9a8 <_called_func+0x8>
9347 fdb28: 00 00 fe 2f unop
9348 fdb2c: 00 00 fe 2f unop
9349 fdb30: 30 82 7d a7 ldq t12,-32208(gp)
9350 fdb34: 00 40 5b 6b jsr ra,(t12),fdb38 <__func+0x68>
9352 GP load instructions were wrongly cleared by the linker relaxation
9353 pass. This workaround prevents removal of GP loads by inserting
9354 an unop instruction between a noreturn function call and
9355 exception handler prologue. */
9357 if (current_function_has_exception_handlers ())
9358 alpha_pad_noreturn ();
9360 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
9361 alpha_handle_trap_shadows ();
9363 /* Due to the number of extra trapb insns, don't bother fixing up
9364 alignment when trap precision is instruction. Moreover, we can
9365 only do our job when sched2 is run. */
9366 if (optimize
&& !optimize_size
9367 && alpha_tp
!= ALPHA_TP_INSN
9368 && flag_schedule_insns_after_reload
)
9370 if (alpha_tune
== PROCESSOR_EV4
)
9371 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
9372 else if (alpha_tune
== PROCESSOR_EV5
)
9373 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
9382 alpha_file_start (void)
9384 #ifdef OBJECT_FORMAT_ELF
9385 /* If emitting dwarf2 debug information, we cannot generate a .file
9386 directive to start the file, as it will conflict with dwarf2out
9387 file numbers. So it's only useful when emitting mdebug output. */
9388 targetm
.asm_file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
9391 default_file_start ();
9393 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
9396 fputs ("\t.set noreorder\n", asm_out_file
);
9397 fputs ("\t.set volatile\n", asm_out_file
);
9399 fputs ("\t.set noat\n", asm_out_file
);
9400 if (TARGET_EXPLICIT_RELOCS
)
9401 fputs ("\t.set nomacro\n", asm_out_file
);
9402 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
9406 if (alpha_cpu
== PROCESSOR_EV6
|| TARGET_FIX
|| TARGET_CIX
)
9408 else if (TARGET_MAX
)
9410 else if (TARGET_BWX
)
9412 else if (alpha_cpu
== PROCESSOR_EV5
)
9417 fprintf (asm_out_file
, "\t.arch %s\n", arch
);
9421 #ifdef OBJECT_FORMAT_ELF
9422 /* Since we don't have a .dynbss section, we should not allow global
9423 relocations in the .rodata section. */
9426 alpha_elf_reloc_rw_mask (void)
9428 return flag_pic
? 3 : 2;
9431 /* Return a section for X. The only special thing we do here is to
9432 honor small data. */
9435 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
9436 unsigned HOST_WIDE_INT align
)
9438 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
9439 /* ??? Consider using mergeable sdata sections. */
9440 return sdata_section
;
9442 return default_elf_select_rtx_section (mode
, x
, align
);
9446 alpha_elf_section_type_flags (tree decl
, const char *name
, int reloc
)
9448 unsigned int flags
= 0;
9450 if (strcmp (name
, ".sdata") == 0
9451 || strncmp (name
, ".sdata.", 7) == 0
9452 || strncmp (name
, ".gnu.linkonce.s.", 16) == 0
9453 || strcmp (name
, ".sbss") == 0
9454 || strncmp (name
, ".sbss.", 6) == 0
9455 || strncmp (name
, ".gnu.linkonce.sb.", 17) == 0)
9456 flags
= SECTION_SMALL
;
9458 flags
|= default_section_type_flags (decl
, name
, reloc
);
9461 #endif /* OBJECT_FORMAT_ELF */
9463 /* Structure to collect function names for final output in link section. */
9464 /* Note that items marked with GTY can't be ifdef'ed out. */
9472 struct GTY(()) alpha_links
9476 enum reloc_kind rkind
;
9479 #if TARGET_ABI_OPEN_VMS
9481 /* Return the VMS argument type corresponding to MODE. */
9484 alpha_arg_type (enum machine_mode mode
)
9489 return TARGET_FLOAT_VAX
? FF
: FS
;
9491 return TARGET_FLOAT_VAX
? FD
: FT
;
9497 /* Return an rtx for an integer representing the VMS Argument Information
9501 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
9503 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9506 for (i
= 0; i
< 6; i
++)
9507 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9509 return GEN_INT (regval
);
9513 /* Return a SYMBOL_REF representing the reference to the .linkage entry
9514 of function FUNC built for calls made from CFUNDECL. LFLAG is 1 if
9515 this is the reference to the linkage pointer value, 0 if this is the
9516 reference to the function entry value. RFLAG is 1 if this a reduced
9517 reference (code address only), 0 if this is a full reference. */
9520 alpha_use_linkage (rtx func
, bool lflag
, bool rflag
)
9522 struct alpha_links
*al
= NULL
;
9523 const char *name
= XSTR (func
, 0);
9525 if (cfun
->machine
->links
)
9527 splay_tree_node lnode
;
9529 /* Is this name already defined? */
9530 lnode
= splay_tree_lookup (cfun
->machine
->links
, (splay_tree_key
) name
);
9532 al
= (struct alpha_links
*) lnode
->value
;
9535 cfun
->machine
->links
= splay_tree_new_ggc
9536 ((splay_tree_compare_fn
) strcmp
,
9537 ggc_alloc_splay_tree_str_alpha_links_splay_tree_s
,
9538 ggc_alloc_splay_tree_str_alpha_links_splay_tree_node_s
);
9549 /* Follow transparent alias, as this is used for CRTL translations. */
9550 id
= maybe_get_identifier (name
);
9553 while (IDENTIFIER_TRANSPARENT_ALIAS (id
))
9554 id
= TREE_CHAIN (id
);
9555 name
= IDENTIFIER_POINTER (id
);
9558 buf_len
= strlen (name
) + 8 + 9;
9559 linksym
= (char *) alloca (buf_len
);
9560 snprintf (linksym
, buf_len
, "$%d..%s..lk", cfun
->funcdef_no
, name
);
9562 al
= ggc_alloc_alpha_links ();
9564 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (linksym
));
9566 splay_tree_insert (cfun
->machine
->links
,
9567 (splay_tree_key
) ggc_strdup (name
),
9568 (splay_tree_value
) al
);
9571 al
->rkind
= rflag
? KIND_CODEADDR
: KIND_LINKAGE
;
9574 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9580 alpha_write_one_linkage (splay_tree_node node
, void *data
)
9582 const char *const name
= (const char *) node
->key
;
9583 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9584 FILE *stream
= (FILE *) data
;
9586 ASM_OUTPUT_INTERNAL_LABEL (stream
, XSTR (link
->linkage
, 0));
9587 if (link
->rkind
== KIND_CODEADDR
)
9589 /* External and used, request code address. */
9590 fprintf (stream
, "\t.code_address ");
9594 if (!SYMBOL_REF_EXTERNAL_P (link
->func
)
9595 && SYMBOL_REF_LOCAL_P (link
->func
))
9597 /* Locally defined, build linkage pair. */
9598 fprintf (stream
, "\t.quad %s..en\n", name
);
9599 fprintf (stream
, "\t.quad ");
9603 /* External, request linkage pair. */
9604 fprintf (stream
, "\t.linkage ");
9607 assemble_name (stream
, name
);
9608 fputs ("\n", stream
);
9614 alpha_write_linkage (FILE *stream
, const char *funname
)
9616 fprintf (stream
, "\t.link\n");
9617 fprintf (stream
, "\t.align 3\n");
9620 #ifdef TARGET_VMS_CRASH_DEBUG
9621 fputs ("\t.name ", stream
);
9622 assemble_name (stream
, funname
);
9623 fputs ("..na\n", stream
);
9626 ASM_OUTPUT_LABEL (stream
, funname
);
9627 fprintf (stream
, "\t.pdesc ");
9628 assemble_name (stream
, funname
);
9629 fprintf (stream
, "..en,%s\n",
9630 alpha_procedure_type
== PT_STACK
? "stack"
9631 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9633 if (cfun
->machine
->links
)
9635 splay_tree_foreach (cfun
->machine
->links
, alpha_write_one_linkage
, stream
);
9636 /* splay_tree_delete (func->links); */
9640 /* Switch to an arbitrary section NAME with attributes as specified
9641 by FLAGS. ALIGN specifies any known alignment requirements for
9642 the section; 0 if the default should be used. */
9645 vms_asm_named_section (const char *name
, unsigned int flags
,
9646 tree decl ATTRIBUTE_UNUSED
)
9648 fputc ('\n', asm_out_file
);
9649 fprintf (asm_out_file
, ".section\t%s", name
);
9651 if (flags
& SECTION_DEBUG
)
9652 fprintf (asm_out_file
, ",NOWRT");
9654 fputc ('\n', asm_out_file
);
9657 /* Record an element in the table of global constructors. SYMBOL is
9658 a SYMBOL_REF of the function to be called; PRIORITY is a number
9659 between 0 and MAX_INIT_PRIORITY.
9661 Differs from default_ctors_section_asm_out_constructor in that the
9662 width of the .ctors entry is always 64 bits, rather than the 32 bits
9663 used by a normal pointer. */
9666 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9668 switch_to_section (ctors_section
);
9669 assemble_align (BITS_PER_WORD
);
9670 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9674 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9676 switch_to_section (dtors_section
);
9677 assemble_align (BITS_PER_WORD
);
9678 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9682 alpha_use_linkage (rtx func ATTRIBUTE_UNUSED
,
9683 bool lflag ATTRIBUTE_UNUSED
,
9684 bool rflag ATTRIBUTE_UNUSED
)
9689 #endif /* TARGET_ABI_OPEN_VMS */
9692 alpha_init_libfuncs (void)
9694 if (TARGET_ABI_OPEN_VMS
)
9696 /* Use the VMS runtime library functions for division and
9698 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
9699 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
9700 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
9701 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
9702 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
9703 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
9704 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
9705 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
9706 abort_libfunc
= init_one_libfunc ("decc$abort");
9707 memcmp_libfunc
= init_one_libfunc ("decc$memcmp");
9708 #ifdef MEM_LIBFUNCS_INIT
9714 /* On the Alpha, we use this to disable the floating-point registers
9715 when they don't exist. */
9718 alpha_conditional_register_usage (void)
9721 if (! TARGET_FPREGS
)
9722 for (i
= 32; i
< 63; i
++)
9723 fixed_regs
[i
] = call_used_regs
[i
] = 1;
9726 /* Initialize the GCC target structure. */
9727 #if TARGET_ABI_OPEN_VMS
9728 # undef TARGET_ATTRIBUTE_TABLE
9729 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
9730 # undef TARGET_CAN_ELIMINATE
9731 # define TARGET_CAN_ELIMINATE alpha_vms_can_eliminate
9734 #undef TARGET_IN_SMALL_DATA_P
9735 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
9737 #undef TARGET_ASM_ALIGNED_HI_OP
9738 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9739 #undef TARGET_ASM_ALIGNED_DI_OP
9740 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9742 /* Default unaligned ops are provided for ELF systems. To get unaligned
9743 data for non-ELF systems, we have to turn off auto alignment. */
9744 #if !defined (OBJECT_FORMAT_ELF) || TARGET_ABI_OPEN_VMS
9745 #undef TARGET_ASM_UNALIGNED_HI_OP
9746 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
9747 #undef TARGET_ASM_UNALIGNED_SI_OP
9748 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
9749 #undef TARGET_ASM_UNALIGNED_DI_OP
9750 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
9753 #ifdef OBJECT_FORMAT_ELF
9754 #undef TARGET_ASM_RELOC_RW_MASK
9755 #define TARGET_ASM_RELOC_RW_MASK alpha_elf_reloc_rw_mask
9756 #undef TARGET_ASM_SELECT_RTX_SECTION
9757 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
9758 #undef TARGET_SECTION_TYPE_FLAGS
9759 #define TARGET_SECTION_TYPE_FLAGS alpha_elf_section_type_flags
9762 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
9763 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
9765 #undef TARGET_INIT_LIBFUNCS
9766 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
9768 #undef TARGET_LEGITIMIZE_ADDRESS
9769 #define TARGET_LEGITIMIZE_ADDRESS alpha_legitimize_address
9771 #undef TARGET_ASM_FILE_START
9772 #define TARGET_ASM_FILE_START alpha_file_start
9773 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
9774 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
9776 #undef TARGET_SCHED_ADJUST_COST
9777 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
9778 #undef TARGET_SCHED_ISSUE_RATE
9779 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
9780 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9781 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
9782 alpha_multipass_dfa_lookahead
9784 #undef TARGET_HAVE_TLS
9785 #define TARGET_HAVE_TLS HAVE_AS_TLS
9787 #undef TARGET_BUILTIN_DECL
9788 #define TARGET_BUILTIN_DECL alpha_builtin_decl
9789 #undef TARGET_INIT_BUILTINS
9790 #define TARGET_INIT_BUILTINS alpha_init_builtins
9791 #undef TARGET_EXPAND_BUILTIN
9792 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
9793 #undef TARGET_FOLD_BUILTIN
9794 #define TARGET_FOLD_BUILTIN alpha_fold_builtin
9796 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9797 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
9798 #undef TARGET_CANNOT_COPY_INSN_P
9799 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
9800 #undef TARGET_LEGITIMATE_CONSTANT_P
9801 #define TARGET_LEGITIMATE_CONSTANT_P alpha_legitimate_constant_p
9802 #undef TARGET_CANNOT_FORCE_CONST_MEM
9803 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
9806 #undef TARGET_ASM_OUTPUT_MI_THUNK
9807 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
9808 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9809 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
9810 #undef TARGET_STDARG_OPTIMIZE_HOOK
9811 #define TARGET_STDARG_OPTIMIZE_HOOK alpha_stdarg_optimize_hook
9814 /* Use 16-bits anchor. */
9815 #undef TARGET_MIN_ANCHOR_OFFSET
9816 #define TARGET_MIN_ANCHOR_OFFSET -0x7fff - 1
9817 #undef TARGET_MAX_ANCHOR_OFFSET
9818 #define TARGET_MAX_ANCHOR_OFFSET 0x7fff
9819 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
9820 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
9822 #undef TARGET_RTX_COSTS
9823 #define TARGET_RTX_COSTS alpha_rtx_costs
9824 #undef TARGET_ADDRESS_COST
9825 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
9827 #undef TARGET_MACHINE_DEPENDENT_REORG
9828 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
9830 #undef TARGET_PROMOTE_FUNCTION_MODE
9831 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
9832 #undef TARGET_PROMOTE_PROTOTYPES
9833 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_false
9834 #undef TARGET_RETURN_IN_MEMORY
9835 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
9836 #undef TARGET_PASS_BY_REFERENCE
9837 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
9838 #undef TARGET_SETUP_INCOMING_VARARGS
9839 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
9840 #undef TARGET_STRICT_ARGUMENT_NAMING
9841 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
9842 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
9843 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
9844 #undef TARGET_SPLIT_COMPLEX_ARG
9845 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
9846 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9847 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
9848 #undef TARGET_ARG_PARTIAL_BYTES
9849 #define TARGET_ARG_PARTIAL_BYTES alpha_arg_partial_bytes
9850 #undef TARGET_FUNCTION_ARG
9851 #define TARGET_FUNCTION_ARG alpha_function_arg
9852 #undef TARGET_FUNCTION_ARG_ADVANCE
9853 #define TARGET_FUNCTION_ARG_ADVANCE alpha_function_arg_advance
9854 #undef TARGET_TRAMPOLINE_INIT
9855 #define TARGET_TRAMPOLINE_INIT alpha_trampoline_init
9857 #undef TARGET_INSTANTIATE_DECLS
9858 #define TARGET_INSTANTIATE_DECLS alpha_instantiate_decls
9860 #undef TARGET_SECONDARY_RELOAD
9861 #define TARGET_SECONDARY_RELOAD alpha_secondary_reload
9863 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9864 #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
9865 #undef TARGET_VECTOR_MODE_SUPPORTED_P
9866 #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
9868 #undef TARGET_BUILD_BUILTIN_VA_LIST
9869 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
9871 #undef TARGET_EXPAND_BUILTIN_VA_START
9872 #define TARGET_EXPAND_BUILTIN_VA_START alpha_va_start
9874 /* The Alpha architecture does not require sequential consistency. See
9875 http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
9876 for an example of how it can be violated in practice. */
9877 #undef TARGET_RELAXED_ORDERING
9878 #define TARGET_RELAXED_ORDERING true
9880 #undef TARGET_OPTION_OVERRIDE
9881 #define TARGET_OPTION_OVERRIDE alpha_option_override
9883 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9884 #undef TARGET_MANGLE_TYPE
9885 #define TARGET_MANGLE_TYPE alpha_mangle_type
9888 #undef TARGET_LEGITIMATE_ADDRESS_P
9889 #define TARGET_LEGITIMATE_ADDRESS_P alpha_legitimate_address_p
9891 #undef TARGET_CONDITIONAL_REGISTER_USAGE
9892 #define TARGET_CONDITIONAL_REGISTER_USAGE alpha_conditional_register_usage
9894 struct gcc_target targetm
= TARGET_INITIALIZER
;
9897 #include "gt-alpha.h"