1 /* Subroutines used for code generation on the Synopsys DesignWare ARC cpu.
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
4 Sources derived from work done by Sankhya Technologies (www.sankhya.com) on
5 behalf of Synopsys Inc.
7 Position Independent Code support added,Code cleaned up,
8 Comments and Support For ARC700 instructions added by
9 Saurabh Verma (saurabh.verma@codito.com)
10 Ramana Radhakrishnan(ramana.radhakrishnan@codito.com)
12 Fixing ABI inconsistencies, optimizations for ARC600 / ARC700 pipelines,
13 profiling support added by Joern Rennecke <joern.rennecke@embecosm.com>
15 This file is part of GCC.
17 GCC is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 3, or (at your option)
22 GCC is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
27 You should have received a copy of the GNU General Public License
28 along with GCC; see the file COPYING3. If not see
29 <http://www.gnu.org/licenses/>. */
33 #include "coretypes.h"
42 #include "stringpool.h"
48 #include "diagnostic.h"
49 #include "fold-const.h"
51 #include "stor-layout.h"
54 #include "insn-attr.h"
58 #include "langhooks.h"
59 #include "tm-constrs.h"
60 #include "reload.h" /* For operands_match_p */
62 #include "tree-pass.h"
69 /* Which cpu we're compiling for (ARC600, ARC601, ARC700). */
70 static char arc_cpu_name
[10] = "";
71 static const char *arc_cpu_string
= arc_cpu_name
;
73 /* ??? Loads can handle any constant, stores can only handle small ones. */
74 /* OTOH, LIMMs cost extra, so their usefulness is limited. */
75 #define RTX_OK_FOR_OFFSET_P(MODE, X) \
76 (GET_CODE (X) == CONST_INT \
77 && SMALL_INT_RANGE (INTVAL (X), (GET_MODE_SIZE (MODE) - 1) & -4, \
78 (INTVAL (X) & (GET_MODE_SIZE (MODE) - 1) & 3 \
80 : -(-GET_MODE_SIZE (MODE) | -4) >> 1)))
82 #define LEGITIMATE_SMALL_DATA_OFFSET_P(X) \
83 (GET_CODE (X) == CONST \
84 && GET_CODE (XEXP ((X), 0)) == PLUS \
85 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == SYMBOL_REF \
86 && SYMBOL_REF_SMALL_P (XEXP (XEXP ((X), 0), 0)) \
87 && GET_CODE (XEXP(XEXP ((X), 0), 1)) == CONST_INT \
88 && INTVAL (XEXP (XEXP ((X), 0), 1)) <= g_switch_value)
90 #define LEGITIMATE_SMALL_DATA_ADDRESS_P(X) \
91 (GET_CODE (X) == PLUS \
92 && REG_P (XEXP ((X), 0)) \
93 && REGNO (XEXP ((X), 0)) == SDATA_BASE_REGNUM \
94 && ((GET_CODE (XEXP ((X), 1)) == SYMBOL_REF \
95 && SYMBOL_REF_SMALL_P (XEXP ((X), 1))) \
96 || LEGITIMATE_SMALL_DATA_OFFSET_P (XEXP ((X), 1))))
98 /* Array of valid operand punctuation characters. */
99 char arc_punct_chars
[256];
101 /* State used by arc_ccfsm_advance to implement conditional execution. */
102 struct GTY (()) arc_ccfsm
107 rtx_insn
*target_insn
;
111 /* Status of the IRQ_CTRL_AUX register. */
112 typedef struct irq_ctrl_saved_t
114 /* Last register number used by IRQ_CTRL_SAVED aux_reg. */
115 short irq_save_last_reg
;
116 /* True if BLINK is automatically saved. */
118 /* True if LPCOUNT is automatically saved. */
119 bool irq_save_lpcount
;
121 static irq_ctrl_saved_t irq_ctrl_saved
;
123 #define ARC_AUTOBLINK_IRQ_P(FNTYPE) \
124 ((ARC_INTERRUPT_P (FNTYPE) \
125 && irq_ctrl_saved.irq_save_blink) \
126 || (ARC_FAST_INTERRUPT_P (FNTYPE) \
127 && rgf_banked_register_count > 8))
129 #define ARC_AUTOFP_IRQ_P(FNTYPE) \
130 ((ARC_INTERRUPT_P (FNTYPE) \
131 && (irq_ctrl_saved.irq_save_last_reg > 26)) \
132 || (ARC_FAST_INTERRUPT_P (FNTYPE) \
133 && rgf_banked_register_count > 8))
135 #define ARC_AUTO_IRQ_P(FNTYPE) \
136 (ARC_INTERRUPT_P (FNTYPE) && !ARC_FAST_INTERRUPT_P (FNTYPE) \
137 && (irq_ctrl_saved.irq_save_blink \
138 || (irq_ctrl_saved.irq_save_last_reg >= 0)))
140 /* Number of registers in second bank for FIRQ support. */
141 static int rgf_banked_register_count
;
143 #define arc_ccfsm_current cfun->machine->ccfsm_current
145 #define ARC_CCFSM_BRANCH_DELETED_P(STATE) \
146 ((STATE)->state == 1 || (STATE)->state == 2)
148 /* Indicate we're conditionalizing insns now. */
149 #define ARC_CCFSM_RECORD_BRANCH_DELETED(STATE) \
150 ((STATE)->state += 2)
152 #define ARC_CCFSM_COND_EXEC_P(STATE) \
153 ((STATE)->state == 3 || (STATE)->state == 4 || (STATE)->state == 5 \
154 || current_insn_predicate)
156 /* Check if INSN has a 16 bit opcode considering struct arc_ccfsm *STATE. */
157 #define CCFSM_ISCOMPACT(INSN,STATE) \
158 (ARC_CCFSM_COND_EXEC_P (STATE) \
159 ? (get_attr_iscompact (INSN) == ISCOMPACT_TRUE \
160 || get_attr_iscompact (INSN) == ISCOMPACT_TRUE_LIMM) \
161 : get_attr_iscompact (INSN) != ISCOMPACT_FALSE)
163 /* Likewise, but also consider that INSN might be in a delay slot of JUMP. */
164 #define CCFSM_DBR_ISCOMPACT(INSN,JUMP,STATE) \
165 ((ARC_CCFSM_COND_EXEC_P (STATE) \
167 && INSN_ANNULLED_BRANCH_P (JUMP) \
168 && (TARGET_AT_DBR_CONDEXEC || INSN_FROM_TARGET_P (INSN)))) \
169 ? (get_attr_iscompact (INSN) == ISCOMPACT_TRUE \
170 || get_attr_iscompact (INSN) == ISCOMPACT_TRUE_LIMM) \
171 : get_attr_iscompact (INSN) != ISCOMPACT_FALSE)
173 /* The maximum number of insns skipped which will be conditionalised if
175 /* When optimizing for speed:
176 Let p be the probability that the potentially skipped insns need to
177 be executed, pn the cost of a correctly predicted non-taken branch,
178 mt the cost of a mis/non-predicted taken branch,
179 mn mispredicted non-taken, pt correctly predicted taken ;
180 costs expressed in numbers of instructions like the ones considered
182 Unfortunately we don't have a measure of predictability - this
183 is linked to probability only in that in the no-eviction-scenario
184 there is a lower bound 1 - 2 * min (p, 1-p), and a somewhat larger
185 value that can be assumed *if* the distribution is perfectly random.
186 A predictability of 1 is perfectly plausible not matter what p is,
187 because the decision could be dependent on an invocation parameter
189 For large p, we want MAX_INSNS_SKIPPED == pn/(1-p) + mt - pn
190 For small p, we want MAX_INSNS_SKIPPED == pt
192 When optimizing for size:
193 We want to skip insn unless we could use 16 opcodes for the
194 non-conditionalized insn to balance the branch length or more.
195 Performance can be tie-breaker. */
196 /* If the potentially-skipped insns are likely to be executed, we'll
197 generally save one non-taken branch
199 this to be no less than the 1/p */
200 #define MAX_INSNS_SKIPPED 3
202 /* A nop is needed between a 4 byte insn that sets the condition codes and
203 a branch that uses them (the same isn't true for an 8 byte insn that sets
204 the condition codes). Set by arc_ccfsm_advance. Used by
205 arc_print_operand. */
207 static int get_arc_condition_code (rtx
);
209 static tree
arc_handle_interrupt_attribute (tree
*, tree
, tree
, int, bool *);
210 static tree
arc_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
212 /* Initialized arc_attribute_table to NULL since arc doesnot have any
213 machine specific supported attributes. */
214 const struct attribute_spec arc_attribute_table
[] =
216 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
217 affects_type_identity } */
218 { "interrupt", 1, 1, true, false, false, arc_handle_interrupt_attribute
, true },
219 /* Function calls made to this symbol must be done indirectly, because
220 it may lie outside of the 21/25 bit addressing range of a normal function
222 { "long_call", 0, 0, false, true, true, NULL
, false },
223 /* Whereas these functions are always known to reside within the 25 bit
224 addressing range of unconditionalized bl. */
225 { "medium_call", 0, 0, false, true, true, NULL
, false },
226 /* And these functions are always known to reside within the 21 bit
227 addressing range of blcc. */
228 { "short_call", 0, 0, false, true, true, NULL
, false },
229 /* Function which are not having the prologue and epilogue generated
231 { "naked", 0, 0, true, false, false, arc_handle_fndecl_attribute
, false },
232 { NULL
, 0, 0, false, false, false, NULL
, false }
234 static int arc_comp_type_attributes (const_tree
, const_tree
);
235 static void arc_file_start (void);
236 static void arc_internal_label (FILE *, const char *, unsigned long);
237 static void arc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
239 static int arc_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
240 static void arc_encode_section_info (tree decl
, rtx rtl
, int first
);
242 static void arc_init_builtins (void);
243 static rtx
arc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
245 static int branch_dest (rtx
);
247 static void arc_output_pic_addr_const (FILE *, rtx
, int);
248 static bool arc_function_ok_for_sibcall (tree
, tree
);
249 static rtx
arc_function_value (const_tree
, const_tree
, bool);
250 const char * output_shift (rtx
*);
251 static void arc_reorg (void);
252 static bool arc_in_small_data_p (const_tree
);
254 static void arc_init_reg_tables (void);
255 static bool arc_return_in_memory (const_tree
, const_tree
);
256 static bool arc_vector_mode_supported_p (machine_mode
);
258 static bool arc_can_use_doloop_p (const widest_int
&, const widest_int
&,
260 static const char *arc_invalid_within_doloop (const rtx_insn
*);
262 static void output_short_suffix (FILE *file
);
264 static bool arc_frame_pointer_required (void);
266 static bool arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT
,
268 enum by_pieces_operation op
,
271 /* Globally visible information about currently selected cpu. */
272 const arc_cpu_t
*arc_selected_cpu
;
275 legitimate_scaled_address_p (machine_mode mode
, rtx op
, bool strict
)
277 if (GET_CODE (op
) != PLUS
)
280 if (GET_CODE (XEXP (op
, 0)) != MULT
)
283 /* Check multiplication operands. */
284 if (!RTX_OK_FOR_INDEX_P (XEXP (XEXP (op
, 0), 0), strict
))
287 if (!CONST_INT_P (XEXP (XEXP (op
, 0), 1)))
290 switch (GET_MODE_SIZE (mode
))
293 if (INTVAL (XEXP (XEXP (op
, 0), 1)) != 2)
301 if (INTVAL (XEXP (XEXP (op
, 0), 1)) != 4)
307 /* Check the base. */
308 if (RTX_OK_FOR_BASE_P (XEXP (op
, 1), (strict
)))
313 if (CONST_INT_P (XEXP (op
, 1)))
317 if (CONSTANT_P (XEXP (op
, 1)))
319 /* Scalled addresses for sdata is done other places. */
320 if (GET_CODE (XEXP (op
, 1)) == SYMBOL_REF
321 && SYMBOL_REF_SMALL_P (XEXP (op
, 1)))
329 /* Check for constructions like REG + OFFS, where OFFS can be a
330 register, an immediate or an long immediate. */
333 legitimate_offset_address_p (machine_mode mode
, rtx x
, bool index
, bool strict
)
335 if (GET_CODE (x
) != PLUS
)
338 if (!RTX_OK_FOR_BASE_P (XEXP (x
, 0), (strict
)))
341 /* Check for: [Rx + small offset] or [Rx + Ry]. */
342 if (((index
&& RTX_OK_FOR_INDEX_P (XEXP (x
, 1), (strict
))
343 && GET_MODE_SIZE ((mode
)) <= 4)
344 || RTX_OK_FOR_OFFSET_P (mode
, XEXP (x
, 1))))
347 /* Check for [Rx + symbol]. */
349 && (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
350 /* Avoid this type of address for double or larger modes. */
351 && (GET_MODE_SIZE (mode
) <= 4)
352 /* Avoid small data which ends in something like GP +
354 && (!SYMBOL_REF_SMALL_P (XEXP (x
, 1))))
360 /* Implements target hook vector_mode_supported_p. */
363 arc_vector_mode_supported_p (machine_mode mode
)
368 return TARGET_PLUS_DMPY
;
371 return TARGET_PLUS_QMACW
;
374 return TARGET_SIMD_SET
;
381 /* Implements target hook TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
384 arc_preferred_simd_mode (scalar_mode mode
)
389 return TARGET_PLUS_QMACW
? V4HImode
: V2HImode
;
398 /* Implements target hook
399 TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES. */
402 arc_autovectorize_vector_sizes (void)
404 return TARGET_PLUS_QMACW
? (8 | 4) : 0;
407 /* TARGET_PRESERVE_RELOAD_P is still awaiting patch re-evaluation / review. */
408 static bool arc_preserve_reload_p (rtx in
) ATTRIBUTE_UNUSED
;
409 static rtx
arc_delegitimize_address (rtx
);
410 static bool arc_can_follow_jump (const rtx_insn
*follower
,
411 const rtx_insn
*followee
);
413 static rtx
frame_insn (rtx
);
414 static void arc_function_arg_advance (cumulative_args_t
, machine_mode
,
416 static rtx
arc_legitimize_address_0 (rtx
, rtx
, machine_mode mode
);
418 static void arc_finalize_pic (void);
420 /* initialize the GCC target structure. */
421 #undef TARGET_COMP_TYPE_ATTRIBUTES
422 #define TARGET_COMP_TYPE_ATTRIBUTES arc_comp_type_attributes
423 #undef TARGET_ASM_FILE_START
424 #define TARGET_ASM_FILE_START arc_file_start
425 #undef TARGET_ATTRIBUTE_TABLE
426 #define TARGET_ATTRIBUTE_TABLE arc_attribute_table
427 #undef TARGET_ASM_INTERNAL_LABEL
428 #define TARGET_ASM_INTERNAL_LABEL arc_internal_label
429 #undef TARGET_RTX_COSTS
430 #define TARGET_RTX_COSTS arc_rtx_costs
431 #undef TARGET_ADDRESS_COST
432 #define TARGET_ADDRESS_COST arc_address_cost
434 #undef TARGET_ENCODE_SECTION_INFO
435 #define TARGET_ENCODE_SECTION_INFO arc_encode_section_info
437 #undef TARGET_CANNOT_FORCE_CONST_MEM
438 #define TARGET_CANNOT_FORCE_CONST_MEM arc_cannot_force_const_mem
440 #undef TARGET_INIT_BUILTINS
441 #define TARGET_INIT_BUILTINS arc_init_builtins
443 #undef TARGET_EXPAND_BUILTIN
444 #define TARGET_EXPAND_BUILTIN arc_expand_builtin
446 #undef TARGET_BUILTIN_DECL
447 #define TARGET_BUILTIN_DECL arc_builtin_decl
449 #undef TARGET_ASM_OUTPUT_MI_THUNK
450 #define TARGET_ASM_OUTPUT_MI_THUNK arc_output_mi_thunk
452 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
453 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
455 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
456 #define TARGET_FUNCTION_OK_FOR_SIBCALL arc_function_ok_for_sibcall
458 #undef TARGET_MACHINE_DEPENDENT_REORG
459 #define TARGET_MACHINE_DEPENDENT_REORG arc_reorg
461 #undef TARGET_IN_SMALL_DATA_P
462 #define TARGET_IN_SMALL_DATA_P arc_in_small_data_p
464 #undef TARGET_PROMOTE_FUNCTION_MODE
465 #define TARGET_PROMOTE_FUNCTION_MODE \
466 default_promote_function_mode_always_promote
468 #undef TARGET_PROMOTE_PROTOTYPES
469 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
471 #undef TARGET_RETURN_IN_MEMORY
472 #define TARGET_RETURN_IN_MEMORY arc_return_in_memory
473 #undef TARGET_PASS_BY_REFERENCE
474 #define TARGET_PASS_BY_REFERENCE arc_pass_by_reference
476 #undef TARGET_SETUP_INCOMING_VARARGS
477 #define TARGET_SETUP_INCOMING_VARARGS arc_setup_incoming_varargs
479 #undef TARGET_ARG_PARTIAL_BYTES
480 #define TARGET_ARG_PARTIAL_BYTES arc_arg_partial_bytes
482 #undef TARGET_MUST_PASS_IN_STACK
483 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
485 #undef TARGET_FUNCTION_VALUE
486 #define TARGET_FUNCTION_VALUE arc_function_value
488 #undef TARGET_SCHED_ADJUST_PRIORITY
489 #define TARGET_SCHED_ADJUST_PRIORITY arc_sched_adjust_priority
491 #undef TARGET_VECTOR_MODE_SUPPORTED_P
492 #define TARGET_VECTOR_MODE_SUPPORTED_P arc_vector_mode_supported_p
494 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
495 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arc_preferred_simd_mode
497 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
498 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES arc_autovectorize_vector_sizes
500 #undef TARGET_CAN_USE_DOLOOP_P
501 #define TARGET_CAN_USE_DOLOOP_P arc_can_use_doloop_p
503 #undef TARGET_INVALID_WITHIN_DOLOOP
504 #define TARGET_INVALID_WITHIN_DOLOOP arc_invalid_within_doloop
506 #undef TARGET_PRESERVE_RELOAD_P
507 #define TARGET_PRESERVE_RELOAD_P arc_preserve_reload_p
509 #undef TARGET_CAN_FOLLOW_JUMP
510 #define TARGET_CAN_FOLLOW_JUMP arc_can_follow_jump
512 #undef TARGET_DELEGITIMIZE_ADDRESS
513 #define TARGET_DELEGITIMIZE_ADDRESS arc_delegitimize_address
515 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
516 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
517 arc_use_by_pieces_infrastructure_p
519 /* Usually, we will be able to scale anchor offsets.
520 When this fails, we want LEGITIMIZE_ADDRESS to kick in. */
521 #undef TARGET_MIN_ANCHOR_OFFSET
522 #define TARGET_MIN_ANCHOR_OFFSET (-1024)
523 #undef TARGET_MAX_ANCHOR_OFFSET
524 #define TARGET_MAX_ANCHOR_OFFSET (1020)
526 #undef TARGET_SECONDARY_RELOAD
527 #define TARGET_SECONDARY_RELOAD arc_secondary_reload
529 #define TARGET_OPTION_OVERRIDE arc_override_options
531 #define TARGET_CONDITIONAL_REGISTER_USAGE arc_conditional_register_usage
533 #define TARGET_TRAMPOLINE_INIT arc_initialize_trampoline
535 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arc_trampoline_adjust_address
537 #define TARGET_CAN_ELIMINATE arc_can_eliminate
539 #define TARGET_FRAME_POINTER_REQUIRED arc_frame_pointer_required
541 #define TARGET_FUNCTION_ARG arc_function_arg
543 #define TARGET_FUNCTION_ARG_ADVANCE arc_function_arg_advance
545 #define TARGET_LEGITIMATE_CONSTANT_P arc_legitimate_constant_p
547 #define TARGET_LEGITIMATE_ADDRESS_P arc_legitimate_address_p
549 #define TARGET_MODE_DEPENDENT_ADDRESS_P arc_mode_dependent_address_p
551 #define TARGET_LEGITIMIZE_ADDRESS arc_legitimize_address
553 #define TARGET_ADJUST_INSN_LENGTH arc_adjust_insn_length
555 #define TARGET_INSN_LENGTH_PARAMETERS arc_insn_length_parameters
557 #undef TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P
558 #define TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P \
559 arc_no_speculation_in_delay_slots_p
562 #define TARGET_LRA_P arc_lra_p
563 #define TARGET_REGISTER_PRIORITY arc_register_priority
564 /* Stores with scaled offsets have different displacement ranges. */
565 #define TARGET_DIFFERENT_ADDR_DISPLACEMENT_P hook_bool_void_true
566 #define TARGET_SPILL_CLASS arc_spill_class
568 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
569 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arc_allocate_stack_slots_for_args
571 #undef TARGET_WARN_FUNC_RETURN
572 #define TARGET_WARN_FUNC_RETURN arc_warn_func_return
574 #include "target-def.h"
576 #undef TARGET_ASM_ALIGNED_HI_OP
577 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
578 #undef TARGET_ASM_ALIGNED_SI_OP
579 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
582 #undef TARGET_HAVE_TLS
583 #define TARGET_HAVE_TLS HAVE_AS_TLS
586 #undef TARGET_DWARF_REGISTER_SPAN
587 #define TARGET_DWARF_REGISTER_SPAN arc_dwarf_register_span
589 /* Try to keep the (mov:DF _, reg) as early as possible so
590 that the d<add/sub/mul>h-lr insns appear together and can
591 use the peephole2 pattern. */
594 arc_sched_adjust_priority (rtx_insn
*insn
, int priority
)
596 rtx set
= single_set (insn
);
598 && GET_MODE (SET_SRC(set
)) == DFmode
599 && GET_CODE (SET_SRC(set
)) == REG
)
601 /* Incrementing priority by 20 (empirically derived). */
602 return priority
+ 20;
608 /* For ARC base register + offset addressing, the validity of the
609 address is mode-dependent for most of the offset range, as the
610 offset can be scaled by the access size.
611 We don't expose these as mode-dependent addresses in the
612 mode_dependent_address_p target hook, because that would disable
613 lots of optimizations, and most uses of these addresses are for 32
614 or 64 bit accesses anyways, which are fine.
615 However, that leaves some addresses for 8 / 16 bit values not
616 properly reloaded by the generic code, which is why we have to
617 schedule secondary reloads for these. */
620 arc_secondary_reload (bool in_p
,
624 secondary_reload_info
*sri
)
626 enum rtx_code code
= GET_CODE (x
);
628 if (cl
== DOUBLE_REGS
)
631 /* The loop counter register can be stored, but not loaded directly. */
632 if ((cl
== LPCOUNT_REG
|| cl
== WRITABLE_CORE_REGS
)
633 && in_p
&& MEM_P (x
))
636 /* If we have a subreg (reg), where reg is a pseudo (that will end in
637 a memory location), then we may need a scratch register to handle
638 the fp/sp+largeoffset address. */
646 int regno
= REGNO (x
);
647 if (regno
>= FIRST_PSEUDO_REGISTER
)
648 regno
= reg_renumber
[regno
];
653 /* It is a pseudo that ends in a stack location. */
654 if (reg_equiv_mem (REGNO (x
)))
656 /* Get the equivalent address and check the range of the
658 rtx mem
= reg_equiv_mem (REGNO (x
));
659 addr
= find_replacement (&XEXP (mem
, 0));
664 gcc_assert (MEM_P (x
));
666 addr
= simplify_rtx (addr
);
668 if (addr
&& GET_CODE (addr
) == PLUS
669 && CONST_INT_P (XEXP (addr
, 1))
670 && (!RTX_OK_FOR_OFFSET_P (mode
, XEXP (addr
, 1))))
676 in_p
? CODE_FOR_reload_qi_load
: CODE_FOR_reload_qi_store
;
680 in_p
? CODE_FOR_reload_hi_load
: CODE_FOR_reload_hi_store
;
690 /* Convert reloads using offsets that are too large to use indirect
694 arc_secondary_reload_conv (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
698 gcc_assert (GET_CODE (mem
) == MEM
);
699 addr
= XEXP (mem
, 0);
701 /* Large offset: use a move. FIXME: ld ops accepts limms as
702 offsets. Hence, the following move insn is not required. */
703 emit_move_insn (scratch
, addr
);
704 mem
= replace_equiv_address_nv (mem
, scratch
);
706 /* Now create the move. */
708 emit_insn (gen_rtx_SET (mem
, reg
));
710 emit_insn (gen_rtx_SET (reg
, mem
));
715 static unsigned arc_ifcvt (void);
719 const pass_data pass_data_arc_ifcvt
=
722 "arc_ifcvt", /* name */
723 OPTGROUP_NONE
, /* optinfo_flags */
724 TV_IFCVT2
, /* tv_id */
725 0, /* properties_required */
726 0, /* properties_provided */
727 0, /* properties_destroyed */
728 0, /* todo_flags_start */
729 TODO_df_finish
/* todo_flags_finish */
732 class pass_arc_ifcvt
: public rtl_opt_pass
735 pass_arc_ifcvt(gcc::context
*ctxt
)
736 : rtl_opt_pass(pass_data_arc_ifcvt
, ctxt
)
739 /* opt_pass methods: */
740 opt_pass
* clone () { return new pass_arc_ifcvt (m_ctxt
); }
741 virtual unsigned int execute (function
*) { return arc_ifcvt (); }
747 make_pass_arc_ifcvt (gcc::context
*ctxt
)
749 return new pass_arc_ifcvt (ctxt
);
752 static unsigned arc_predicate_delay_insns (void);
756 const pass_data pass_data_arc_predicate_delay_insns
=
759 "arc_predicate_delay_insns", /* name */
760 OPTGROUP_NONE
, /* optinfo_flags */
761 TV_IFCVT2
, /* tv_id */
762 0, /* properties_required */
763 0, /* properties_provided */
764 0, /* properties_destroyed */
765 0, /* todo_flags_start */
766 TODO_df_finish
/* todo_flags_finish */
769 class pass_arc_predicate_delay_insns
: public rtl_opt_pass
772 pass_arc_predicate_delay_insns(gcc::context
*ctxt
)
773 : rtl_opt_pass(pass_data_arc_predicate_delay_insns
, ctxt
)
776 /* opt_pass methods: */
777 virtual unsigned int execute (function
*)
779 return arc_predicate_delay_insns ();
786 make_pass_arc_predicate_delay_insns (gcc::context
*ctxt
)
788 return new pass_arc_predicate_delay_insns (ctxt
);
791 /* Called by OVERRIDE_OPTIONS to initialize various things. */
798 /* I have the multiplier, then use it*/
799 if (TARGET_MPYW
|| TARGET_MULTI
)
800 arc_multcost
= COSTS_N_INSNS (1);
802 /* Note: arc_multcost is only used in rtx_cost if speed is true. */
803 if (arc_multcost
< 0)
806 case TUNE_ARC700_4_2_STD
:
808 max throughput (1 multiply + 4 other insns) / 5 cycles. */
809 arc_multcost
= COSTS_N_INSNS (4);
810 if (TARGET_NOMPY_SET
)
811 arc_multcost
= COSTS_N_INSNS (30);
813 case TUNE_ARC700_4_2_XMAC
:
815 max throughput (1 multiply + 2 other insns) / 3 cycles. */
816 arc_multcost
= COSTS_N_INSNS (3);
817 if (TARGET_NOMPY_SET
)
818 arc_multcost
= COSTS_N_INSNS (30);
821 if (TARGET_MUL64_SET
)
823 arc_multcost
= COSTS_N_INSNS (4);
828 arc_multcost
= COSTS_N_INSNS (30);
832 /* MPY instructions valid only for ARC700 or ARCv2. */
833 if (TARGET_NOMPY_SET
&& TARGET_ARC600_FAMILY
)
834 error ("-mno-mpy supported only for ARC700 or ARCv2");
836 if (!TARGET_DPFP
&& TARGET_DPFP_DISABLE_LRSR
)
837 error ("-mno-dpfp-lrsr supported only with -mdpfp");
839 /* FPX-1. No fast and compact together. */
840 if ((TARGET_DPFP_FAST_SET
&& TARGET_DPFP_COMPACT_SET
)
841 || (TARGET_SPFP_FAST_SET
&& TARGET_SPFP_COMPACT_SET
))
842 error ("FPX fast and compact options cannot be specified together");
844 /* FPX-2. No fast-spfp for arc600 or arc601. */
845 if (TARGET_SPFP_FAST_SET
&& TARGET_ARC600_FAMILY
)
846 error ("-mspfp_fast not available on ARC600 or ARC601");
848 /* FPX-4. No FPX extensions mixed with FPU extensions. */
849 if ((TARGET_DPFP_FAST_SET
|| TARGET_DPFP_COMPACT_SET
|| TARGET_SPFP
)
850 && TARGET_HARD_FLOAT
)
851 error ("No FPX/FPU mixing allowed");
853 /* Warn for unimplemented PIC in pre-ARC700 cores, and disable flag_pic. */
854 if (flag_pic
&& TARGET_ARC600_FAMILY
)
857 "PIC is not supported for %s. Generating non-PIC code only..",
862 arc_init_reg_tables ();
864 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
865 memset (arc_punct_chars
, 0, sizeof (arc_punct_chars
));
866 arc_punct_chars
['#'] = 1;
867 arc_punct_chars
['*'] = 1;
868 arc_punct_chars
['?'] = 1;
869 arc_punct_chars
['!'] = 1;
870 arc_punct_chars
['^'] = 1;
871 arc_punct_chars
['&'] = 1;
872 arc_punct_chars
['+'] = 1;
873 arc_punct_chars
['_'] = 1;
875 if (optimize
> 1 && !TARGET_NO_COND_EXEC
)
877 /* There are two target-independent ifcvt passes, and arc_reorg may do
878 one or more arc_ifcvt calls. */
879 opt_pass
*pass_arc_ifcvt_4
= make_pass_arc_ifcvt (g
);
880 struct register_pass_info arc_ifcvt4_info
881 = { pass_arc_ifcvt_4
, "dbr", 1, PASS_POS_INSERT_AFTER
};
882 struct register_pass_info arc_ifcvt5_info
883 = { pass_arc_ifcvt_4
->clone (), "shorten", 1, PASS_POS_INSERT_BEFORE
};
885 register_pass (&arc_ifcvt4_info
);
886 register_pass (&arc_ifcvt5_info
);
889 if (flag_delayed_branch
)
891 opt_pass
*pass_arc_predicate_delay_insns
892 = make_pass_arc_predicate_delay_insns (g
);
893 struct register_pass_info arc_predicate_delay_info
894 = { pass_arc_predicate_delay_insns
, "dbr", 1, PASS_POS_INSERT_AFTER
};
896 register_pass (&arc_predicate_delay_info
);
900 /* Parse -mirq-ctrl-saved=RegisterRange, blink, lp_copunt. The
901 register range is specified as two registers separated by a dash.
902 It always starts with r0, and its upper limit is fp register.
903 blink and lp_count registers are optional. */
906 irq_range (const char *cstr
)
908 int i
, first
, last
, blink
, lpcount
, xreg
;
909 char *str
, *dash
, *comma
;
912 str
= (char *) alloca (i
+ 1);
913 memcpy (str
, cstr
, i
+ 1);
917 dash
= strchr (str
, '-');
920 warning (0, "value of -mirq-ctrl-saved must have form R0-REGx");
925 comma
= strchr (dash
+ 1, ',');
929 first
= decode_reg_name (str
);
932 warning (0, "first register must be R0");
936 /* At this moment we do not have the register names initialized
938 if (!strcmp (dash
+ 1, "ilink"))
941 last
= decode_reg_name (dash
+ 1);
945 warning (0, "unknown register name: %s", dash
+ 1);
951 warning (0, "last register name %s must be an odd register", dash
+ 1);
959 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
968 comma
= strchr (str
, ',');
972 xreg
= decode_reg_name (str
);
984 warning (0, "unknown register name: %s", str
);
989 irq_ctrl_saved
.irq_save_last_reg
= last
;
990 irq_ctrl_saved
.irq_save_blink
= (blink
== 31) || (last
== 31);
991 irq_ctrl_saved
.irq_save_lpcount
= (lpcount
== 60);
994 /* Parse -mrgf-banked-regs=NUM option string. Valid values for NUM are 4,
998 parse_mrgf_banked_regs_option (const char *arg
)
1004 val
= strtol (arg
, &end_ptr
, 10);
1005 if (errno
!= 0 || *arg
== '\0' || *end_ptr
!= '\0'
1006 || (val
!= 0 && val
!= 4 && val
!= 8 && val
!= 16 && val
!= 32))
1008 error ("invalid number in -mrgf-banked-regs=%s "
1009 "valid values are 0, 4, 8, 16, or 32", arg
);
1012 rgf_banked_register_count
= (int) val
;
1015 /* Check ARC options, generate derived target attributes. */
1018 arc_override_options (void)
1021 cl_deferred_option
*opt
;
1022 vec
<cl_deferred_option
> *vopt
1023 = (vec
<cl_deferred_option
> *) arc_deferred_options
;
1025 if (arc_cpu
== PROCESSOR_NONE
)
1026 arc_cpu
= TARGET_CPU_DEFAULT
;
1028 /* Set the default cpu options. */
1029 arc_selected_cpu
= &arc_cpu_types
[(int) arc_cpu
];
1031 /* Set the architectures. */
1032 switch (arc_selected_cpu
->arch_info
->arch_id
)
1035 arc_cpu_string
= "EM";
1038 arc_cpu_string
= "HS";
1041 if (arc_selected_cpu
->processor
== PROCESSOR_nps400
)
1042 arc_cpu_string
= "NPS400";
1044 arc_cpu_string
= "ARC700";
1047 arc_cpu_string
= "ARC600";
1053 irq_ctrl_saved
.irq_save_last_reg
= -1;
1054 irq_ctrl_saved
.irq_save_blink
= false;
1055 irq_ctrl_saved
.irq_save_lpcount
= false;
1057 rgf_banked_register_count
= 0;
1059 /* Handle the deferred options. */
1061 FOR_EACH_VEC_ELT (*vopt
, i
, opt
)
1063 switch (opt
->opt_index
)
1065 case OPT_mirq_ctrl_saved_
:
1067 irq_range (opt
->arg
);
1069 warning (0, "option -mirq-ctrl-saved valid only for ARC v2 processors");
1072 case OPT_mrgf_banked_regs_
:
1074 parse_mrgf_banked_regs_option (opt
->arg
);
1076 warning (0, "option -mrgf-banked-regs valid only for ARC v2 processors");
1084 /* Set cpu flags accordingly to architecture/selected cpu. The cpu
1085 specific flags are set in arc-common.c. The architecture forces
1086 the default hardware configurations in, regardless what command
1087 line options are saying. The CPU optional hw options can be
1088 turned on or off. */
1089 #define ARC_OPT(NAME, CODE, MASK, DOC) \
1091 if ((arc_selected_cpu->flags & CODE) \
1092 && ((target_flags_explicit & MASK) == 0)) \
1093 target_flags |= MASK; \
1094 if (arc_selected_cpu->arch_info->dflags & CODE) \
1095 target_flags |= MASK; \
1097 #define ARC_OPTX(NAME, CODE, VAR, VAL, DOC) \
1099 if ((arc_selected_cpu->flags & CODE) \
1100 && (VAR == DEFAULT_##VAR)) \
1102 if (arc_selected_cpu->arch_info->dflags & CODE) \
1106 #include "arc-options.def"
1111 /* Check options against architecture options. Throw an error if
1112 option is not allowed. */
1113 #define ARC_OPTX(NAME, CODE, VAR, VAL, DOC) \
1116 && (!(arc_selected_cpu->arch_info->flags & CODE))) \
1118 error ("%s is not available for %s architecture", \
1119 DOC, arc_selected_cpu->arch_info->name); \
1122 #define ARC_OPT(NAME, CODE, MASK, DOC) \
1124 if ((target_flags & MASK) \
1125 && (!(arc_selected_cpu->arch_info->flags & CODE))) \
1126 error ("%s is not available for %s architecture", \
1127 DOC, arc_selected_cpu->arch_info->name); \
1130 #include "arc-options.def"
1135 /* Set Tune option. */
1136 if (arc_tune
== TUNE_NONE
)
1137 arc_tune
= (enum attr_tune
) arc_selected_cpu
->tune
;
1139 if (arc_size_opt_level
== 3)
1142 /* Compact casesi is not a valid option for ARCv2 family. */
1145 if (TARGET_COMPACT_CASESI
)
1147 warning (0, "compact-casesi is not applicable to ARCv2");
1148 TARGET_COMPACT_CASESI
= 0;
1151 else if (optimize_size
== 1
1152 && !global_options_set
.x_TARGET_COMPACT_CASESI
)
1153 TARGET_COMPACT_CASESI
= 1;
1156 target_flags
|= MASK_NO_SDATA_SET
;
1158 if (flag_no_common
== 255)
1159 flag_no_common
= !TARGET_NO_SDATA_SET
;
1161 /* TARGET_COMPACT_CASESI needs the "q" register class. */
1162 if (TARGET_MIXED_CODE
)
1164 if (!TARGET_Q_CLASS
)
1165 TARGET_COMPACT_CASESI
= 0;
1166 if (TARGET_COMPACT_CASESI
)
1167 TARGET_CASE_VECTOR_PC_RELATIVE
= 1;
1169 /* Check for small data option */
1170 if (!global_options_set
.x_g_switch_value
&& !TARGET_NO_SDATA_SET
)
1171 g_switch_value
= TARGET_LL64
? 8 : 4;
1173 /* These need to be done at start up. It's convenient to do them here. */
1177 /* The condition codes of the ARC, and the inverse function. */
1178 /* For short branches, the "c" / "nc" names are not defined in the ARC
1179 Programmers manual, so we have to use "lo" / "hs"" instead. */
1180 static const char *arc_condition_codes
[] =
1182 "al", 0, "eq", "ne", "p", "n", "lo", "hs", "v", "nv",
1183 "gt", "le", "ge", "lt", "hi", "ls", "pnz", 0
1186 enum arc_cc_code_index
1188 ARC_CC_AL
, ARC_CC_EQ
= ARC_CC_AL
+2, ARC_CC_NE
, ARC_CC_P
, ARC_CC_N
,
1189 ARC_CC_C
, ARC_CC_NC
, ARC_CC_V
, ARC_CC_NV
,
1190 ARC_CC_GT
, ARC_CC_LE
, ARC_CC_GE
, ARC_CC_LT
, ARC_CC_HI
, ARC_CC_LS
, ARC_CC_PNZ
,
1191 ARC_CC_LO
= ARC_CC_C
, ARC_CC_HS
= ARC_CC_NC
1194 #define ARC_INVERSE_CONDITION_CODE(X) ((X) ^ 1)
1196 /* Returns the index of the ARC condition code string in
1197 `arc_condition_codes'. COMPARISON should be an rtx like
1198 `(eq (...) (...))'. */
1201 get_arc_condition_code (rtx comparison
)
1203 switch (GET_MODE (XEXP (comparison
, 0)))
1206 case E_SImode
: /* For BRcc. */
1207 switch (GET_CODE (comparison
))
1209 case EQ
: return ARC_CC_EQ
;
1210 case NE
: return ARC_CC_NE
;
1211 case GT
: return ARC_CC_GT
;
1212 case LE
: return ARC_CC_LE
;
1213 case GE
: return ARC_CC_GE
;
1214 case LT
: return ARC_CC_LT
;
1215 case GTU
: return ARC_CC_HI
;
1216 case LEU
: return ARC_CC_LS
;
1217 case LTU
: return ARC_CC_LO
;
1218 case GEU
: return ARC_CC_HS
;
1219 default : gcc_unreachable ();
1222 switch (GET_CODE (comparison
))
1224 case EQ
: return ARC_CC_EQ
;
1225 case NE
: return ARC_CC_NE
;
1226 case GE
: return ARC_CC_P
;
1227 case LT
: return ARC_CC_N
;
1228 case GT
: return ARC_CC_PNZ
;
1229 default : gcc_unreachable ();
1232 switch (GET_CODE (comparison
))
1234 case EQ
: return ARC_CC_EQ
;
1235 case NE
: return ARC_CC_NE
;
1236 default : gcc_unreachable ();
1239 switch (GET_CODE (comparison
))
1241 case LTU
: return ARC_CC_C
;
1242 case GEU
: return ARC_CC_NC
;
1243 default : gcc_unreachable ();
1245 case E_CC_FP_GTmode
:
1246 if (TARGET_ARGONAUT_SET
&& TARGET_SPFP
)
1247 switch (GET_CODE (comparison
))
1249 case GT
: return ARC_CC_N
;
1250 case UNLE
: return ARC_CC_P
;
1251 default : gcc_unreachable ();
1254 switch (GET_CODE (comparison
))
1256 case GT
: return ARC_CC_HI
;
1257 case UNLE
: return ARC_CC_LS
;
1258 default : gcc_unreachable ();
1260 case E_CC_FP_GEmode
:
1261 /* Same for FPX and non-FPX. */
1262 switch (GET_CODE (comparison
))
1264 case GE
: return ARC_CC_HS
;
1265 case UNLT
: return ARC_CC_LO
;
1266 default : gcc_unreachable ();
1268 case E_CC_FP_UNEQmode
:
1269 switch (GET_CODE (comparison
))
1271 case UNEQ
: return ARC_CC_EQ
;
1272 case LTGT
: return ARC_CC_NE
;
1273 default : gcc_unreachable ();
1275 case E_CC_FP_ORDmode
:
1276 switch (GET_CODE (comparison
))
1278 case UNORDERED
: return ARC_CC_C
;
1279 case ORDERED
: return ARC_CC_NC
;
1280 default : gcc_unreachable ();
1283 switch (GET_CODE (comparison
))
1285 case EQ
: return ARC_CC_EQ
;
1286 case NE
: return ARC_CC_NE
;
1287 case UNORDERED
: return ARC_CC_C
;
1288 case ORDERED
: return ARC_CC_NC
;
1289 case LTGT
: return ARC_CC_HI
;
1290 case UNEQ
: return ARC_CC_LS
;
1291 default : gcc_unreachable ();
1294 switch (GET_CODE (comparison
))
1296 case EQ
: return ARC_CC_EQ
;
1297 case NE
: return ARC_CC_NE
;
1298 case GT
: return ARC_CC_GT
;
1299 case GE
: return ARC_CC_GE
;
1300 case LT
: return ARC_CC_C
;
1301 case LE
: return ARC_CC_LS
;
1302 case UNORDERED
: return ARC_CC_V
;
1303 case ORDERED
: return ARC_CC_NV
;
1304 case UNGT
: return ARC_CC_HI
;
1305 case UNGE
: return ARC_CC_HS
;
1306 case UNLT
: return ARC_CC_LT
;
1307 case UNLE
: return ARC_CC_LE
;
1308 /* UNEQ and LTGT do not have representation. */
1309 case LTGT
: /* Fall through. */
1310 case UNEQ
: /* Fall through. */
1311 default : gcc_unreachable ();
1313 case E_CC_FPU_UNEQmode
:
1314 switch (GET_CODE (comparison
))
1316 case LTGT
: return ARC_CC_NE
;
1317 case UNEQ
: return ARC_CC_EQ
;
1318 default : gcc_unreachable ();
1320 default : gcc_unreachable ();
1326 /* Return true if COMPARISON has a short form that can accomodate OFFSET. */
1329 arc_short_comparison_p (rtx comparison
, int offset
)
1331 gcc_assert (ARC_CC_NC
== ARC_CC_HS
);
1332 gcc_assert (ARC_CC_C
== ARC_CC_LO
);
1333 switch (get_arc_condition_code (comparison
))
1335 case ARC_CC_EQ
: case ARC_CC_NE
:
1336 return offset
>= -512 && offset
<= 506;
1337 case ARC_CC_GT
: case ARC_CC_LE
: case ARC_CC_GE
: case ARC_CC_LT
:
1338 case ARC_CC_HI
: case ARC_CC_LS
: case ARC_CC_LO
: case ARC_CC_HS
:
1339 return offset
>= -64 && offset
<= 58;
1345 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1346 return the mode to be used for the comparison. */
1349 arc_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
1351 machine_mode mode
= GET_MODE (x
);
1354 /* For an operation that sets the condition codes as a side-effect, the
1355 C and V flags is not set as for cmp, so we can only use comparisons where
1356 this doesn't matter. (For LT and GE we can use "mi" and "pl"
1358 /* ??? We could use "pnz" for greater than zero, however, we could then
1359 get into trouble because the comparison could not be reversed. */
1360 if (GET_MODE_CLASS (mode
) == MODE_INT
1362 && (op
== EQ
|| op
== NE
1363 || ((op
== LT
|| op
== GE
) && GET_MODE_SIZE (GET_MODE (x
)) <= 4)))
1366 /* add.f for if (a+b) */
1368 && GET_CODE (y
) == NEG
1369 && (op
== EQ
|| op
== NE
))
1372 /* Check if this is a test suitable for bxor.f . */
1373 if (mode
== SImode
&& (op
== EQ
|| op
== NE
) && CONST_INT_P (y
)
1374 && ((INTVAL (y
) - 1) & INTVAL (y
)) == 0
1378 /* Check if this is a test suitable for add / bmsk.f . */
1379 if (mode
== SImode
&& (op
== EQ
|| op
== NE
) && CONST_INT_P (y
)
1380 && GET_CODE (x
) == AND
&& CONST_INT_P ((x1
= XEXP (x
, 1)))
1381 && ((INTVAL (x1
) + 1) & INTVAL (x1
)) == 0
1382 && (~INTVAL (x1
) | INTVAL (y
)) < 0
1383 && (~INTVAL (x1
) | INTVAL (y
)) > -0x800)
1386 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
1387 && GET_CODE (x
) == PLUS
1388 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
1391 if (TARGET_ARGONAUT_SET
1392 && ((mode
== SFmode
&& TARGET_SPFP
) || (mode
== DFmode
&& TARGET_DPFP
)))
1395 case EQ
: case NE
: case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
1397 case LT
: case UNGE
: case GT
: case UNLE
:
1398 return CC_FP_GTmode
;
1399 case LE
: case UNGT
: case GE
: case UNLT
:
1400 return CC_FP_GEmode
;
1401 default: gcc_unreachable ();
1403 else if (TARGET_HARD_FLOAT
1404 && ((mode
== SFmode
&& TARGET_FP_SP_BASE
)
1405 || (mode
== DFmode
&& TARGET_FP_DP_BASE
)))
1424 return CC_FPU_UNEQmode
;
1429 else if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& TARGET_OPTFPE
)
1433 case EQ
: case NE
: return CC_Zmode
;
1435 case GT
: case UNLE
: return CC_FP_GTmode
;
1437 case GE
: case UNLT
: return CC_FP_GEmode
;
1438 case UNEQ
: case LTGT
: return CC_FP_UNEQmode
;
1439 case ORDERED
: case UNORDERED
: return CC_FP_ORDmode
;
1440 default: gcc_unreachable ();
1446 /* Vectors to keep interesting information about registers where it can easily
1447 be got. We use to use the actual mode value as the bit number, but there
1448 is (or may be) more than 32 modes now. Instead we use two tables: one
1449 indexed by hard register number, and one indexed by mode. */
1451 /* The purpose of arc_mode_class is to shrink the range of modes so that
1452 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
1453 mapped into one arc_mode_class mode. */
1455 enum arc_mode_class
{
1457 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
1458 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
1462 /* Modes for condition codes. */
1463 #define C_MODES (1 << (int) C_MODE)
1465 /* Modes for single-word and smaller quantities. */
1466 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
1468 /* Modes for double-word and smaller quantities. */
1469 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
1471 /* Mode for 8-byte DF values only. */
1472 #define DF_MODES (1 << DF_MODE)
1474 /* Modes for quad-word and smaller quantities. */
1475 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
1477 /* Modes for 128-bit vectors. */
1478 #define V_MODES (1 << (int) V_MODE)
1480 /* Value is 1 if register/mode pair is acceptable on arc. */
1482 unsigned int arc_hard_regno_mode_ok
[] = {
1483 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
1484 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
1485 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, D_MODES
,
1486 D_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1488 /* ??? Leave these as S_MODES for now. */
1489 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1490 DF_MODES
, 0, DF_MODES
, 0, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1491 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1492 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, C_MODES
, S_MODES
,
1494 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1495 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1496 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1497 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1499 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1500 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1501 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1502 V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
, V_MODES
,
1504 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
1505 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
1508 unsigned int arc_mode_class
[NUM_MACHINE_MODES
];
1510 enum reg_class arc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
1513 arc_preferred_reload_class (rtx
, enum reg_class cl
)
1515 if ((cl
) == CHEAP_CORE_REGS
|| (cl
) == WRITABLE_CORE_REGS
)
1516 return GENERAL_REGS
;
1520 /* Initialize the arc_mode_class array. */
1523 arc_init_reg_tables (void)
1527 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
1529 machine_mode m
= (machine_mode
) i
;
1531 switch (GET_MODE_CLASS (m
))
1534 case MODE_PARTIAL_INT
:
1535 case MODE_COMPLEX_INT
:
1536 if (GET_MODE_SIZE (m
) <= 4)
1537 arc_mode_class
[i
] = 1 << (int) S_MODE
;
1538 else if (GET_MODE_SIZE (m
) == 8)
1539 arc_mode_class
[i
] = 1 << (int) D_MODE
;
1540 else if (GET_MODE_SIZE (m
) == 16)
1541 arc_mode_class
[i
] = 1 << (int) T_MODE
;
1542 else if (GET_MODE_SIZE (m
) == 32)
1543 arc_mode_class
[i
] = 1 << (int) O_MODE
;
1545 arc_mode_class
[i
] = 0;
1548 case MODE_COMPLEX_FLOAT
:
1549 if (GET_MODE_SIZE (m
) <= 4)
1550 arc_mode_class
[i
] = 1 << (int) SF_MODE
;
1551 else if (GET_MODE_SIZE (m
) == 8)
1552 arc_mode_class
[i
] = 1 << (int) DF_MODE
;
1553 else if (GET_MODE_SIZE (m
) == 16)
1554 arc_mode_class
[i
] = 1 << (int) TF_MODE
;
1555 else if (GET_MODE_SIZE (m
) == 32)
1556 arc_mode_class
[i
] = 1 << (int) OF_MODE
;
1558 arc_mode_class
[i
] = 0;
1560 case MODE_VECTOR_INT
:
1561 if (GET_MODE_SIZE (m
) == 4)
1562 arc_mode_class
[i
] = (1 << (int) S_MODE
);
1563 else if (GET_MODE_SIZE (m
) == 8)
1564 arc_mode_class
[i
] = (1 << (int) D_MODE
);
1566 arc_mode_class
[i
] = (1 << (int) V_MODE
);
1570 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
1571 we must explicitly check for them here. */
1572 if (i
== (int) CCmode
|| i
== (int) CC_ZNmode
|| i
== (int) CC_Zmode
1573 || i
== (int) CC_Cmode
1574 || i
== CC_FP_GTmode
|| i
== CC_FP_GEmode
|| i
== CC_FP_ORDmode
1575 || i
== CC_FPUmode
|| i
== CC_FPU_UNEQmode
)
1576 arc_mode_class
[i
] = 1 << (int) C_MODE
;
1578 arc_mode_class
[i
] = 0;
1584 /* Core registers 56..59 are used for multiply extension options.
1585 The dsp option uses r56 and r57, these are then named acc1 and acc2.
1586 acc1 is the highpart, and acc2 the lowpart, so which register gets which
1587 number depends on endianness.
1588 The mul64 multiplier options use r57 for mlo, r58 for mmid and r59 for mhi.
1589 Because mlo / mhi form a 64 bit value, we use different gcc internal
1590 register numbers to make them form a register pair as the gcc internals
1591 know it. mmid gets number 57, if still available, and mlo / mhi get
1592 number 58 and 59, depending on endianness. We use DBX_REGISTER_NUMBER
1593 to map this back. */
1594 char rname56
[5] = "r56";
1595 char rname57
[5] = "r57";
1596 char rname58
[5] = "r58";
1597 char rname59
[5] = "r59";
1598 char rname29
[7] = "ilink1";
1599 char rname30
[7] = "ilink2";
1602 arc_conditional_register_usage (void)
1606 int fix_start
= 60, fix_end
= 55;
1610 /* For ARCv2 the core register set is changed. */
1611 strcpy (rname29
, "ilink");
1612 strcpy (rname30
, "r30");
1613 call_used_regs
[30] = 1;
1616 arc_regno_reg_class
[30] = WRITABLE_CORE_REGS
;
1617 SET_HARD_REG_BIT (reg_class_contents
[WRITABLE_CORE_REGS
], 30);
1618 SET_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], 30);
1619 SET_HARD_REG_BIT (reg_class_contents
[GENERAL_REGS
], 30);
1620 SET_HARD_REG_BIT (reg_class_contents
[MPY_WRITABLE_CORE_REGS
], 30);
1623 if (TARGET_MUL64_SET
)
1628 /* We don't provide a name for mmed. In rtl / assembly resource lists,
1629 you are supposed to refer to it as mlo & mhi, e.g
1630 (zero_extract:SI (reg:DI 58) (const_int 32) (16)) .
1631 In an actual asm instruction, you are of course use mmed.
1632 The point of avoiding having a separate register for mmed is that
1633 this way, we don't have to carry clobbers of that reg around in every
1634 isntruction that modifies mlo and/or mhi. */
1635 strcpy (rname57
, "");
1636 strcpy (rname58
, TARGET_BIG_ENDIAN
? "mhi" : "mlo");
1637 strcpy (rname59
, TARGET_BIG_ENDIAN
? "mlo" : "mhi");
1640 /* The nature of arc_tp_regno is actually something more like a global
1641 register, however globalize_reg requires a declaration.
1642 We use EPILOGUE_USES to compensate so that sets from
1643 __builtin_set_frame_pointer are not deleted. */
1644 if (arc_tp_regno
!= -1)
1645 fixed_regs
[arc_tp_regno
] = call_used_regs
[arc_tp_regno
] = 1;
1647 if (TARGET_MULMAC_32BY16_SET
)
1650 fix_end
= fix_end
> 57 ? fix_end
: 57;
1651 strcpy (rname56
, TARGET_BIG_ENDIAN
? "acc1" : "acc2");
1652 strcpy (rname57
, TARGET_BIG_ENDIAN
? "acc2" : "acc1");
1654 for (regno
= fix_start
; regno
<= fix_end
; regno
++)
1656 if (!fixed_regs
[regno
])
1657 warning (0, "multiply option implies r%d is fixed", regno
);
1658 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
1664 reg_alloc_order
[0] = 0;
1665 reg_alloc_order
[1] = 1;
1666 reg_alloc_order
[2] = 2;
1667 reg_alloc_order
[3] = 3;
1668 reg_alloc_order
[4] = 12;
1669 reg_alloc_order
[5] = 13;
1670 reg_alloc_order
[6] = 14;
1671 reg_alloc_order
[7] = 15;
1672 reg_alloc_order
[8] = 4;
1673 reg_alloc_order
[9] = 5;
1674 reg_alloc_order
[10] = 6;
1675 reg_alloc_order
[11] = 7;
1676 reg_alloc_order
[12] = 8;
1677 reg_alloc_order
[13] = 9;
1678 reg_alloc_order
[14] = 10;
1679 reg_alloc_order
[15] = 11;
1683 reg_alloc_order
[2] = 12;
1684 reg_alloc_order
[3] = 13;
1685 reg_alloc_order
[4] = 14;
1686 reg_alloc_order
[5] = 15;
1687 reg_alloc_order
[6] = 1;
1688 reg_alloc_order
[7] = 0;
1689 reg_alloc_order
[8] = 4;
1690 reg_alloc_order
[9] = 5;
1691 reg_alloc_order
[10] = 6;
1692 reg_alloc_order
[11] = 7;
1693 reg_alloc_order
[12] = 8;
1694 reg_alloc_order
[13] = 9;
1695 reg_alloc_order
[14] = 10;
1696 reg_alloc_order
[15] = 11;
1699 if (TARGET_SIMD_SET
)
1702 for (i
= ARC_FIRST_SIMD_VR_REG
; i
<= ARC_LAST_SIMD_VR_REG
; i
++)
1703 reg_alloc_order
[i
] = i
;
1704 for (i
= ARC_FIRST_SIMD_DMA_CONFIG_REG
;
1705 i
<= ARC_LAST_SIMD_DMA_CONFIG_REG
; i
++)
1706 reg_alloc_order
[i
] = i
;
1708 /* For ARC600, lp_count may not be read in an instruction
1709 following immediately after another one setting it to a new value.
1710 There was some discussion on how to enforce scheduling constraints for
1711 processors with missing interlocks on the gcc mailing list:
1712 http://gcc.gnu.org/ml/gcc/2008-05/msg00021.html .
1713 However, we can't actually use this approach, because for ARC the
1714 delay slot scheduling pass is active, which runs after
1715 machine_dependent_reorg. */
1717 CLEAR_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], LP_COUNT
);
1718 else if (!TARGET_LP_WR_INTERLOCK
)
1719 fixed_regs
[LP_COUNT
] = 1;
1720 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1721 if (!call_used_regs
[regno
])
1722 CLEAR_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], regno
);
1723 for (regno
= 32; regno
< 60; regno
++)
1724 if (!fixed_regs
[regno
])
1725 SET_HARD_REG_BIT (reg_class_contents
[WRITABLE_CORE_REGS
], regno
);
1726 if (!TARGET_ARC600_FAMILY
)
1728 for (regno
= 32; regno
<= 60; regno
++)
1729 CLEAR_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], regno
);
1731 /* If they have used -ffixed-lp_count, make sure it takes
1733 if (fixed_regs
[LP_COUNT
])
1735 CLEAR_HARD_REG_BIT (reg_class_contents
[LPCOUNT_REG
], LP_COUNT
);
1736 CLEAR_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], LP_COUNT
);
1737 CLEAR_HARD_REG_BIT (reg_class_contents
[WRITABLE_CORE_REGS
], LP_COUNT
);
1739 /* Instead of taking out SF_MODE like below, forbid it outright. */
1740 arc_hard_regno_mode_ok
[60] = 0;
1743 arc_hard_regno_mode_ok
[60] = 1 << (int) S_MODE
;
1746 /* ARCHS has 64-bit data-path which makes use of the even-odd paired
1750 for (regno
= 1; regno
< 32; regno
+=2)
1752 arc_hard_regno_mode_ok
[regno
] = S_MODES
;
1756 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1760 if ((TARGET_Q_CLASS
|| TARGET_RRQ_CLASS
)
1761 && ((i
<= 3) || ((i
>= 12) && (i
<= 15))))
1762 arc_regno_reg_class
[i
] = ARCOMPACT16_REGS
;
1764 arc_regno_reg_class
[i
] = GENERAL_REGS
;
1767 arc_regno_reg_class
[i
]
1769 ? (TEST_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], i
)
1770 ? CHEAP_CORE_REGS
: ALL_CORE_REGS
)
1771 : (((!TARGET_ARC600_FAMILY
)
1772 && TEST_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], i
))
1773 ? CHEAP_CORE_REGS
: WRITABLE_CORE_REGS
));
1775 arc_regno_reg_class
[i
] = NO_REGS
;
1778 /* ARCOMPACT16_REGS is empty, if TARGET_Q_CLASS / TARGET_RRQ_CLASS
1779 has not been activated. */
1780 if (!TARGET_Q_CLASS
&& !TARGET_RRQ_CLASS
)
1781 CLEAR_HARD_REG_SET(reg_class_contents
[ARCOMPACT16_REGS
]);
1782 if (!TARGET_Q_CLASS
)
1783 CLEAR_HARD_REG_SET(reg_class_contents
[AC16_BASE_REGS
]);
1785 gcc_assert (FIRST_PSEUDO_REGISTER
>= 144);
1787 /* Handle Special Registers. */
1788 arc_regno_reg_class
[29] = LINK_REGS
; /* ilink1 register. */
1790 arc_regno_reg_class
[30] = LINK_REGS
; /* ilink2 register. */
1791 arc_regno_reg_class
[31] = LINK_REGS
; /* blink register. */
1792 arc_regno_reg_class
[60] = LPCOUNT_REG
;
1793 arc_regno_reg_class
[61] = NO_REGS
; /* CC_REG: must be NO_REGS. */
1794 arc_regno_reg_class
[62] = GENERAL_REGS
;
1798 for (i
= 40; i
< 44; ++i
)
1800 arc_regno_reg_class
[i
] = DOUBLE_REGS
;
1802 /* Unless they want us to do 'mov d1, 0x00000000' make sure
1803 no attempt is made to use such a register as a destination
1804 operand in *movdf_insn. */
1805 if (!TARGET_ARGONAUT_SET
)
1807 /* Make sure no 'c', 'w', 'W', or 'Rac' constraint is
1808 interpreted to mean they can use D1 or D2 in their insn. */
1809 CLEAR_HARD_REG_BIT(reg_class_contents
[CHEAP_CORE_REGS
], i
);
1810 CLEAR_HARD_REG_BIT(reg_class_contents
[ALL_CORE_REGS
], i
);
1811 CLEAR_HARD_REG_BIT(reg_class_contents
[WRITABLE_CORE_REGS
], i
);
1812 CLEAR_HARD_REG_BIT(reg_class_contents
[MPY_WRITABLE_CORE_REGS
], i
);
1818 /* Disable all DOUBLE_REGISTER settings,
1819 if not generating DPFP code. */
1820 arc_regno_reg_class
[40] = ALL_REGS
;
1821 arc_regno_reg_class
[41] = ALL_REGS
;
1822 arc_regno_reg_class
[42] = ALL_REGS
;
1823 arc_regno_reg_class
[43] = ALL_REGS
;
1830 arc_hard_regno_mode_ok
[40] = 0;
1831 arc_hard_regno_mode_ok
[42] = 0;
1833 CLEAR_HARD_REG_SET(reg_class_contents
[DOUBLE_REGS
]);
1836 if (TARGET_SIMD_SET
)
1838 gcc_assert (ARC_FIRST_SIMD_VR_REG
== 64);
1839 gcc_assert (ARC_LAST_SIMD_VR_REG
== 127);
1841 for (i
= ARC_FIRST_SIMD_VR_REG
; i
<= ARC_LAST_SIMD_VR_REG
; i
++)
1842 arc_regno_reg_class
[i
] = SIMD_VR_REGS
;
1844 gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_REG
== 128);
1845 gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_IN_REG
== 128);
1846 gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG
== 136);
1847 gcc_assert (ARC_LAST_SIMD_DMA_CONFIG_REG
== 143);
1849 for (i
= ARC_FIRST_SIMD_DMA_CONFIG_REG
;
1850 i
<= ARC_LAST_SIMD_DMA_CONFIG_REG
; i
++)
1851 arc_regno_reg_class
[i
] = SIMD_DMA_CONFIG_REGS
;
1855 arc_regno_reg_class
[PROGRAM_COUNTER_REGNO
] = GENERAL_REGS
;
1857 /*ARCV2 Accumulator. */
1859 && (TARGET_FP_DP_FUSED
|| TARGET_FP_SP_FUSED
))
1860 || TARGET_PLUS_DMPY
)
1862 arc_regno_reg_class
[ACCL_REGNO
] = WRITABLE_CORE_REGS
;
1863 arc_regno_reg_class
[ACCH_REGNO
] = WRITABLE_CORE_REGS
;
1864 SET_HARD_REG_BIT (reg_class_contents
[WRITABLE_CORE_REGS
], ACCL_REGNO
);
1865 SET_HARD_REG_BIT (reg_class_contents
[WRITABLE_CORE_REGS
], ACCH_REGNO
);
1866 SET_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], ACCL_REGNO
);
1867 SET_HARD_REG_BIT (reg_class_contents
[CHEAP_CORE_REGS
], ACCH_REGNO
);
1868 SET_HARD_REG_BIT (reg_class_contents
[GENERAL_REGS
], ACCL_REGNO
);
1869 SET_HARD_REG_BIT (reg_class_contents
[GENERAL_REGS
], ACCH_REGNO
);
1870 SET_HARD_REG_BIT (reg_class_contents
[MPY_WRITABLE_CORE_REGS
], ACCL_REGNO
);
1871 SET_HARD_REG_BIT (reg_class_contents
[MPY_WRITABLE_CORE_REGS
], ACCH_REGNO
);
1873 /* Allow the compiler to freely use them. */
1874 fixed_regs
[ACCL_REGNO
] = 0;
1875 fixed_regs
[ACCH_REGNO
] = 0;
1877 arc_hard_regno_mode_ok
[ACC_REG_FIRST
] = D_MODES
;
1881 /* Handle an "interrupt" attribute; arguments as in
1882 struct attribute_spec.handler. */
1885 arc_handle_interrupt_attribute (tree
*, tree name
, tree args
, int,
1890 tree value
= TREE_VALUE (args
);
1892 if (TREE_CODE (value
) != STRING_CST
)
1894 warning (OPT_Wattributes
,
1895 "argument of %qE attribute is not a string constant",
1897 *no_add_attrs
= true;
1900 && strcmp (TREE_STRING_POINTER (value
), "ilink1")
1901 && strcmp (TREE_STRING_POINTER (value
), "ilink2"))
1903 warning (OPT_Wattributes
,
1904 "argument of %qE attribute is not \"ilink1\" or \"ilink2\"",
1906 *no_add_attrs
= true;
1909 && strcmp (TREE_STRING_POINTER (value
), "ilink")
1910 && strcmp (TREE_STRING_POINTER (value
), "firq"))
1912 warning (OPT_Wattributes
,
1913 "argument of %qE attribute is not \"ilink\" or \"firq\"",
1915 *no_add_attrs
= true;
1922 arc_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
1923 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1925 if (TREE_CODE (*node
) != FUNCTION_DECL
)
1927 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
1929 *no_add_attrs
= true;
1935 /* Implement `TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS' */
1938 arc_allocate_stack_slots_for_args (void)
1940 /* Naked functions should not allocate stack slots for arguments. */
1941 unsigned int fn_type
= arc_compute_function_type (cfun
);
1943 return !ARC_NAKED_P(fn_type
);
1946 /* Implement `TARGET_WARN_FUNC_RETURN'. */
1949 arc_warn_func_return (tree decl
)
1951 struct function
*func
= DECL_STRUCT_FUNCTION (decl
);
1952 unsigned int fn_type
= arc_compute_function_type (func
);
1954 return !ARC_NAKED_P (fn_type
);
1957 /* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
1958 and two if they are nearly compatible (which causes a warning to be
1962 arc_comp_type_attributes (const_tree type1
,
1965 int l1
, l2
, m1
, m2
, s1
, s2
;
1967 /* Check for mismatch of non-default calling convention. */
1968 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
1971 /* Check for mismatched call attributes. */
1972 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
1973 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
1974 m1
= lookup_attribute ("medium_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
1975 m2
= lookup_attribute ("medium_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
1976 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
1977 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
1979 /* Only bother to check if an attribute is defined. */
1980 if (l1
| l2
| m1
| m2
| s1
| s2
)
1982 /* If one type has an attribute, the other must have the same attribute. */
1983 if ((l1
!= l2
) || (m1
!= m2
) || (s1
!= s2
))
1986 /* Disallow mixed attributes. */
1987 if (l1
+ m1
+ s1
> 1)
1995 /* Set the default attributes for TYPE. */
1998 arc_set_default_type_attributes (tree type ATTRIBUTE_UNUSED
)
2003 /* Misc. utilities. */
2005 /* X and Y are two things to compare using CODE. Emit the compare insn and
2006 return the rtx for the cc reg in the proper mode. */
2009 gen_compare_reg (rtx comparison
, machine_mode omode
)
2011 enum rtx_code code
= GET_CODE (comparison
);
2012 rtx x
= XEXP (comparison
, 0);
2013 rtx y
= XEXP (comparison
, 1);
2015 machine_mode mode
, cmode
;
2018 cmode
= GET_MODE (x
);
2019 if (cmode
== VOIDmode
)
2020 cmode
= GET_MODE (y
);
2021 gcc_assert (cmode
== SImode
|| cmode
== SFmode
|| cmode
== DFmode
);
2022 if (cmode
== SImode
)
2024 if (!register_operand (x
, SImode
))
2026 if (register_operand (y
, SImode
))
2031 code
= swap_condition (code
);
2034 x
= copy_to_mode_reg (SImode
, x
);
2036 if (GET_CODE (y
) == SYMBOL_REF
&& flag_pic
)
2037 y
= copy_to_mode_reg (SImode
, y
);
2041 x
= force_reg (cmode
, x
);
2042 y
= force_reg (cmode
, y
);
2044 mode
= SELECT_CC_MODE (code
, x
, y
);
2046 cc_reg
= gen_rtx_REG (mode
, CC_REG
);
2048 /* ??? FIXME (x-y)==0, as done by both cmpsfpx_raw and
2049 cmpdfpx_raw, is not a correct comparison for floats:
2050 http://www.cygnus-software.com/papers/comparingfloats/comparingfloats.htm
2052 if (TARGET_ARGONAUT_SET
2053 && ((cmode
== SFmode
&& TARGET_SPFP
) || (cmode
== DFmode
&& TARGET_DPFP
)))
2057 case NE
: case EQ
: case LT
: case UNGE
: case LE
: case UNGT
:
2058 case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
2060 case GT
: case UNLE
: case GE
: case UNLT
:
2061 code
= swap_condition (code
);
2069 if (cmode
== SFmode
)
2071 emit_insn (gen_cmpsfpx_raw (x
, y
));
2075 /* Accepts Dx regs directly by insns. */
2076 emit_insn (gen_cmpdfpx_raw (x
, y
));
2079 if (mode
!= CC_FPXmode
)
2080 emit_insn (gen_rtx_SET (cc_reg
,
2081 gen_rtx_COMPARE (mode
,
2082 gen_rtx_REG (CC_FPXmode
, 61),
2085 else if (TARGET_FPX_QUARK
&& (cmode
== SFmode
))
2089 case NE
: case EQ
: case GT
: case UNLE
: case GE
: case UNLT
:
2090 case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
2092 case LT
: case UNGE
: case LE
: case UNGT
:
2093 code
= swap_condition (code
);
2102 emit_insn (gen_cmp_quark (cc_reg
,
2103 gen_rtx_COMPARE (mode
, x
, y
)));
2105 else if (TARGET_HARD_FLOAT
2106 && ((cmode
== SFmode
&& TARGET_FP_SP_BASE
)
2107 || (cmode
== DFmode
&& TARGET_FP_DP_BASE
)))
2108 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2109 else if (GET_MODE_CLASS (cmode
) == MODE_FLOAT
&& TARGET_OPTFPE
)
2111 rtx op0
= gen_rtx_REG (cmode
, 0);
2112 rtx op1
= gen_rtx_REG (cmode
, GET_MODE_SIZE (cmode
) / UNITS_PER_WORD
);
2117 case NE
: case EQ
: case GT
: case UNLE
: case GE
: case UNLT
:
2118 case UNEQ
: case LTGT
: case ORDERED
: case UNORDERED
:
2120 case LT
: case UNGE
: case LE
: case UNGT
:
2121 code
= swap_condition (code
);
2127 if (currently_expanding_to_rtl
)
2135 emit_move_insn (op0
, x
);
2136 emit_move_insn (op1
, y
);
2140 gcc_assert (rtx_equal_p (op0
, x
));
2141 gcc_assert (rtx_equal_p (op1
, y
));
2148 emit_insn (gen_cmp_float (cc_reg
, gen_rtx_COMPARE (mode
, op0
, op1
)));
2151 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2152 return gen_rtx_fmt_ee (code
, omode
, cc_reg
, const0_rtx
);
2155 /* Return true if VALUE, a const_double, will fit in a limm (4 byte number).
2156 We assume the value can be either signed or unsigned. */
2159 arc_double_limm_p (rtx value
)
2161 HOST_WIDE_INT low
, high
;
2163 gcc_assert (GET_CODE (value
) == CONST_DOUBLE
);
2168 low
= CONST_DOUBLE_LOW (value
);
2169 high
= CONST_DOUBLE_HIGH (value
);
2171 if (low
& 0x80000000)
2173 return (((unsigned HOST_WIDE_INT
) low
<= 0xffffffff && high
== 0)
2174 || (((low
& - (unsigned HOST_WIDE_INT
) 0x80000000)
2175 == - (unsigned HOST_WIDE_INT
) 0x80000000)
2180 return (unsigned HOST_WIDE_INT
) low
<= 0x7fffffff && high
== 0;
2184 /* Do any needed setup for a variadic function. For the ARC, we must
2185 create a register parameter block, and then copy any anonymous arguments
2186 in registers to memory.
2188 CUM has not been updated for the last named argument which has type TYPE
2189 and mode MODE, and we rely on this fact. */
2192 arc_setup_incoming_varargs (cumulative_args_t args_so_far
,
2193 machine_mode mode
, tree type
,
2194 int *pretend_size
, int no_rtl
)
2197 CUMULATIVE_ARGS next_cum
;
2199 /* We must treat `__builtin_va_alist' as an anonymous arg. */
2201 next_cum
= *get_cumulative_args (args_so_far
);
2202 arc_function_arg_advance (pack_cumulative_args (&next_cum
),
2204 first_anon_arg
= next_cum
;
2206 if (FUNCTION_ARG_REGNO_P (first_anon_arg
))
2208 /* First anonymous (unnamed) argument is in a reg. */
2210 /* Note that first_reg_offset < MAX_ARC_PARM_REGS. */
2211 int first_reg_offset
= first_anon_arg
;
2216 = gen_rtx_MEM (BLKmode
, plus_constant (Pmode
, arg_pointer_rtx
,
2217 FIRST_PARM_OFFSET (0)));
2218 move_block_from_reg (first_reg_offset
, regblock
,
2219 MAX_ARC_PARM_REGS
- first_reg_offset
);
2223 = ((MAX_ARC_PARM_REGS
- first_reg_offset
) * UNITS_PER_WORD
);
2227 /* Cost functions. */
2229 /* Provide the costs of an addressing mode that contains ADDR.
2230 If ADDR is not a valid address, its cost is irrelevant. */
2233 arc_address_cost (rtx addr
, machine_mode
, addr_space_t
, bool speed
)
2235 switch (GET_CODE (addr
))
2238 return speed
|| satisfies_constraint_Rcq (addr
) ? 0 : 1;
2239 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
2240 case PRE_MODIFY
: case POST_MODIFY
:
2246 if (TARGET_NPS_CMEM
&& cmem_address (addr
, SImode
))
2248 /* Most likely needs a LIMM. */
2249 return COSTS_N_INSNS (1);
2253 register rtx plus0
= XEXP (addr
, 0);
2254 register rtx plus1
= XEXP (addr
, 1);
2256 if (GET_CODE (plus0
) != REG
2257 && (GET_CODE (plus0
) != MULT
2258 || !CONST_INT_P (XEXP (plus0
, 1))
2259 || (INTVAL (XEXP (plus0
, 1)) != 2
2260 && INTVAL (XEXP (plus0
, 1)) != 4)))
2263 switch (GET_CODE (plus1
))
2266 return (!RTX_OK_FOR_OFFSET_P (SImode
, plus1
)
2270 : (satisfies_constraint_Rcq (plus0
)
2271 && satisfies_constraint_O (plus1
))
2275 return (speed
< 1 ? 0
2276 : (satisfies_constraint_Rcq (plus0
)
2277 && satisfies_constraint_Rcq (plus1
))
2282 return COSTS_N_INSNS (1);
2295 /* Emit instruction X with the frame related bit set. */
2301 RTX_FRAME_RELATED_P (x
) = 1;
2305 /* Emit a frame insn to move SRC to DST. */
2308 frame_move (rtx dst
, rtx src
)
2310 rtx tmp
= gen_rtx_SET (dst
, src
);
2311 RTX_FRAME_RELATED_P (tmp
) = 1;
2312 return frame_insn (tmp
);
2315 /* Like frame_move, but add a REG_INC note for REG if ADDR contains an
2316 auto increment address, or is zero. */
2319 frame_move_inc (rtx dst
, rtx src
, rtx reg
, rtx addr
)
2321 rtx insn
= frame_move (dst
, src
);
2324 || GET_CODE (addr
) == PRE_DEC
|| GET_CODE (addr
) == POST_INC
2325 || GET_CODE (addr
) == PRE_MODIFY
|| GET_CODE (addr
) == POST_MODIFY
)
2326 add_reg_note (insn
, REG_INC
, reg
);
2330 /* Emit a frame insn which adjusts a frame address register REG by OFFSET. */
2333 frame_add (rtx reg
, HOST_WIDE_INT offset
)
2335 gcc_assert ((offset
& 0x3) == 0);
2338 return frame_move (reg
, plus_constant (Pmode
, reg
, offset
));
2341 /* Emit a frame insn which adjusts stack pointer by OFFSET. */
2344 frame_stack_add (HOST_WIDE_INT offset
)
2346 return frame_add (stack_pointer_rtx
, offset
);
2349 /* Traditionally, we push saved registers first in the prologue,
2350 then we allocate the rest of the frame - and reverse in the epilogue.
2351 This has still its merits for ease of debugging, or saving code size
2352 or even execution time if the stack frame is so large that some accesses
2353 can't be encoded anymore with offsets in the instruction code when using
2355 Also, it would be a good starting point if we got instructions to help
2356 with register save/restore.
2358 However, often stack frames are small, and the pushing / popping has
2360 - the stack modification prevents a lot of scheduling.
2361 - frame allocation / deallocation needs extra instructions.
2362 - unless we know that we compile ARC700 user code, we need to put
2363 a memory barrier after frame allocation / before deallocation to
2364 prevent interrupts clobbering our data in the frame.
2365 In particular, we don't have any such guarantees for library functions,
2366 which tend to, on the other hand, to have small frames.
2368 Thus, for small frames, we'd like to use a different scheme:
2369 - The frame is allocated in full with the first prologue instruction,
2370 and deallocated in full with the last epilogue instruction.
2371 Thus, the instructions in-betwen can be freely scheduled.
2372 - If the function has no outgoing arguments on the stack, we can allocate
2373 one register save slot at the top of the stack. This register can then
2374 be saved simultanously with frame allocation, and restored with
2376 This register can be picked depending on scheduling considerations,
2377 although same though should go into having some set of registers
2378 to be potentially lingering after a call, and others to be available
2379 immediately - i.e. in the absence of interprocedual optimization, we
2380 can use an ABI-like convention for register allocation to reduce
2381 stalls after function return. */
2382 /* Function prologue/epilogue handlers. */
2384 /* ARCompact stack frames look like:
2386 Before call After call
2387 high +-----------------------+ +-----------------------+
2388 mem | reg parm save area | | reg parm save area |
2389 | only created for | | only created for |
2390 | variable arg fns | | variable arg fns |
2391 AP +-----------------------+ +-----------------------+
2392 | return addr register | | return addr register |
2393 | (if required) | | (if required) |
2394 +-----------------------+ +-----------------------+
2396 | reg save area | | reg save area |
2398 +-----------------------+ +-----------------------+
2399 | frame pointer | | frame pointer |
2400 | (if required) | | (if required) |
2401 FP +-----------------------+ +-----------------------+
2403 | local/temp variables | | local/temp variables |
2405 +-----------------------+ +-----------------------+
2407 | arguments on stack | | arguments on stack |
2409 SP +-----------------------+ +-----------------------+
2410 | reg parm save area |
2411 | only created for |
2412 | variable arg fns |
2413 AP +-----------------------+
2414 | return addr register |
2416 +-----------------------+
2420 +-----------------------+
2423 FP +-----------------------+
2425 | local/temp variables |
2427 +-----------------------+
2429 | arguments on stack |
2431 mem SP +-----------------------+
2434 1) The "reg parm save area" does not exist for non variable argument fns.
2435 The "reg parm save area" can be eliminated completely if we created our
2436 own va-arc.h, but that has tradeoffs as well (so it's not done). */
2438 /* Structure to be filled in by arc_compute_frame_size with register
2439 save masks, and offsets for the current function. */
2440 struct GTY (()) arc_frame_info
2442 unsigned int total_size
; /* # bytes that the entire frame takes up. */
2443 unsigned int extra_size
; /* # bytes of extra stuff. */
2444 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
2445 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
2446 unsigned int reg_size
; /* # bytes needed to store regs. */
2447 unsigned int var_size
; /* # bytes that variables take up. */
2448 unsigned int reg_offset
; /* Offset from new sp to store regs. */
2449 unsigned int gmask
; /* Mask of saved gp registers. */
2450 int initialized
; /* Nonzero if frame size already calculated. */
2451 short millicode_start_reg
;
2452 short millicode_end_reg
;
2453 bool save_return_addr
;
2456 /* Defining data structures for per-function information. */
2458 typedef struct GTY (()) machine_function
2460 unsigned int fn_type
;
2461 struct arc_frame_info frame_info
;
2462 /* To keep track of unalignment caused by short insns. */
2464 int force_short_suffix
; /* Used when disgorging return delay slot insns. */
2465 const char *size_reason
;
2466 struct arc_ccfsm ccfsm_current
;
2467 /* Map from uid to ccfsm state during branch shortening. */
2468 rtx ccfsm_current_insn
;
2469 char arc_reorg_started
;
2470 char prescan_initialized
;
2473 /* Type of function DECL.
2475 The result is cached. To reset the cache at the end of a function,
2476 call with DECL = NULL_TREE. */
2479 arc_compute_function_type (struct function
*fun
)
2481 tree attr
, decl
= fun
->decl
;
2482 unsigned int fn_type
= fun
->machine
->fn_type
;
2484 if (fn_type
!= ARC_FUNCTION_UNKNOWN
)
2487 /* Check if it is a naked function. */
2488 if (lookup_attribute ("naked", DECL_ATTRIBUTES (decl
)) != NULL_TREE
)
2489 fn_type
|= ARC_FUNCTION_NAKED
;
2491 fn_type
|= ARC_FUNCTION_NORMAL
;
2493 /* Now see if this is an interrupt handler. */
2494 attr
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (decl
));
2495 if (attr
!= NULL_TREE
)
2497 tree value
, args
= TREE_VALUE (attr
);
2499 gcc_assert (list_length (args
) == 1);
2500 value
= TREE_VALUE (args
);
2501 gcc_assert (TREE_CODE (value
) == STRING_CST
);
2503 if (!strcmp (TREE_STRING_POINTER (value
), "ilink1")
2504 || !strcmp (TREE_STRING_POINTER (value
), "ilink"))
2505 fn_type
|= ARC_FUNCTION_ILINK1
;
2506 else if (!strcmp (TREE_STRING_POINTER (value
), "ilink2"))
2507 fn_type
|= ARC_FUNCTION_ILINK2
;
2508 else if (!strcmp (TREE_STRING_POINTER (value
), "firq"))
2509 fn_type
|= ARC_FUNCTION_FIRQ
;
2514 return fun
->machine
->fn_type
= fn_type
;
2517 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
2518 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
2520 /* Tell prologue and epilogue if register REGNO should be saved / restored.
2521 The return address and frame pointer are treated separately.
2522 Don't consider them here.
2523 Addition for pic: The gp register needs to be saved if the current
2524 function changes it to access gotoff variables.
2525 FIXME: This will not be needed if we used some arbitrary register
2530 arc_must_save_register (int regno
, struct function
*func
)
2532 unsigned int fn_type
= arc_compute_function_type (func
);
2533 bool irq_auto_save_p
= ((irq_ctrl_saved
.irq_save_last_reg
>= regno
)
2534 && ARC_AUTO_IRQ_P (fn_type
));
2535 bool firq_auto_save_p
= ARC_FAST_INTERRUPT_P (fn_type
);
2537 switch (rgf_banked_register_count
)
2540 firq_auto_save_p
&= (regno
< 4);
2543 firq_auto_save_p
&= ((regno
< 4) || ((regno
> 11) && (regno
< 16)));
2546 firq_auto_save_p
&= ((regno
< 4) || ((regno
> 9) && (regno
< 16))
2547 || ((regno
> 25) && (regno
< 29))
2548 || ((regno
> 29) && (regno
< 32)));
2551 firq_auto_save_p
&= (regno
!= 29) && (regno
< 32);
2554 firq_auto_save_p
= false;
2558 if ((regno
) != RETURN_ADDR_REGNUM
2559 && (regno
) != FRAME_POINTER_REGNUM
2560 && df_regs_ever_live_p (regno
)
2561 && (!call_used_regs
[regno
]
2562 || ARC_INTERRUPT_P (fn_type
))
2563 /* Do not emit code for auto saved regs. */
2565 && !firq_auto_save_p
)
2568 if (flag_pic
&& crtl
->uses_pic_offset_table
2569 && regno
== PIC_OFFSET_TABLE_REGNUM
)
2575 /* Return true if the return address must be saved in the current function,
2576 otherwise return false. */
2579 arc_must_save_return_addr (struct function
*func
)
2581 if (func
->machine
->frame_info
.save_return_addr
)
2587 /* Helper function to wrap FRAME_POINTER_NEEDED. We do this as
2588 FRAME_POINTER_NEEDED will not be true until the IRA (Integrated
2589 Register Allocator) pass, while we want to get the frame size
2590 correct earlier than the IRA pass. */
2592 arc_frame_pointer_needed (void)
2594 return (frame_pointer_needed
);
2598 /* Return non-zero if there are registers to be saved or loaded using
2599 millicode thunks. We can only use consecutive sequences starting
2600 with r13, and not going beyond r25.
2601 GMASK is a bitmask of registers to save. This function sets
2602 FRAME->millicod_start_reg .. FRAME->millicode_end_reg to the range
2603 of registers to be saved / restored with a millicode call. */
2606 arc_compute_millicode_save_restore_regs (unsigned int gmask
,
2607 struct arc_frame_info
*frame
)
2611 int start_reg
= 13, end_reg
= 25;
2613 for (regno
= start_reg
; regno
<= end_reg
&& (gmask
& (1L << regno
));)
2615 end_reg
= regno
- 1;
2616 /* There is no point in using millicode thunks if we don't save/restore
2617 at least three registers. For non-leaf functions we also have the
2619 if (regno
- start_reg
>= 3 - (crtl
->is_leaf
== 0))
2621 frame
->millicode_start_reg
= 13;
2622 frame
->millicode_end_reg
= regno
- 1;
2628 /* Return the bytes needed to compute the frame pointer from the current
2631 SIZE is the size needed for local variables. */
2634 arc_compute_frame_size (int size
) /* size = # of var. bytes allocated. */
2637 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
2638 unsigned int reg_size
, reg_offset
;
2640 struct arc_frame_info
*frame_info
= &cfun
->machine
->frame_info
;
2642 size
= ARC_STACK_ALIGN (size
);
2644 /* 1) Size of locals and temporaries */
2647 /* 2) Size of outgoing arguments */
2648 args_size
= crtl
->outgoing_args_size
;
2650 /* 3) Calculate space needed for saved registers.
2651 ??? We ignore the extension registers for now. */
2653 /* See if this is an interrupt handler. Call used registers must be saved
2659 for (regno
= 0; regno
<= 31; regno
++)
2661 if (arc_must_save_register (regno
, cfun
))
2663 reg_size
+= UNITS_PER_WORD
;
2664 gmask
|= 1L << regno
;
2668 /* 4) Space for back trace data structure.
2669 <return addr reg size> (if required) + <fp size> (if required). */
2670 frame_info
->save_return_addr
2671 = (!crtl
->is_leaf
|| df_regs_ever_live_p (RETURN_ADDR_REGNUM
));
2672 /* Saving blink reg in case of leaf function for millicode thunk calls. */
2673 if (optimize_size
&& !TARGET_NO_MILLICODE_THUNK_SET
)
2675 if (arc_compute_millicode_save_restore_regs (gmask
, frame_info
))
2676 frame_info
->save_return_addr
= true;
2680 if (arc_must_save_return_addr (cfun
))
2682 if (arc_frame_pointer_needed ())
2685 /* 5) Space for variable arguments passed in registers */
2686 pretend_size
= crtl
->args
.pretend_args_size
;
2688 /* Ensure everything before the locals is aligned appropriately. */
2690 unsigned int extra_plus_reg_size
;
2691 unsigned int extra_plus_reg_size_aligned
;
2693 extra_plus_reg_size
= extra_size
+ reg_size
;
2694 extra_plus_reg_size_aligned
= ARC_STACK_ALIGN(extra_plus_reg_size
);
2695 reg_size
= extra_plus_reg_size_aligned
- extra_size
;
2698 /* Compute total frame size. */
2699 total_size
= var_size
+ args_size
+ extra_size
+ pretend_size
+ reg_size
;
2701 total_size
= ARC_STACK_ALIGN (total_size
);
2703 /* Compute offset of register save area from stack pointer:
2704 Frame: pretend_size <blink> reg_size <fp> var_size args_size <--sp
2706 reg_offset
= (total_size
- (pretend_size
+ reg_size
+ extra_size
)
2707 + (arc_frame_pointer_needed () ? 4 : 0));
2709 /* Save computed information. */
2710 frame_info
->total_size
= total_size
;
2711 frame_info
->extra_size
= extra_size
;
2712 frame_info
->pretend_size
= pretend_size
;
2713 frame_info
->var_size
= var_size
;
2714 frame_info
->args_size
= args_size
;
2715 frame_info
->reg_size
= reg_size
;
2716 frame_info
->reg_offset
= reg_offset
;
2717 frame_info
->gmask
= gmask
;
2718 frame_info
->initialized
= reload_completed
;
2720 /* Ok, we're done. */
2724 /* Common code to save/restore registers. */
2725 /* BASE_REG is the base register to use for addressing and to adjust.
2726 GMASK is a bitmask of general purpose registers to save/restore.
2727 epilogue_p 0: prologue 1:epilogue 2:epilogue, sibling thunk
2728 If *FIRST_OFFSET is non-zero, add it first to BASE_REG - preferably
2729 using a pre-modify for the first memory access. *FIRST_OFFSET is then
2733 arc_save_restore (rtx base_reg
,
2734 unsigned int gmask
, int epilogue_p
, int *first_offset
)
2736 unsigned int offset
= 0;
2738 struct arc_frame_info
*frame
= &cfun
->machine
->frame_info
;
2739 rtx sibthunk_insn
= NULL_RTX
;
2743 /* Millicode thunks implementation:
2744 Generates calls to millicodes for registers starting from r13 to r25
2745 Present Limitations:
2746 - Only one range supported. The remaining regs will have the ordinary
2747 st and ld instructions for store and loads. Hence a gmask asking
2748 to store r13-14, r16-r25 will only generate calls to store and
2749 load r13 to r14 while store and load insns will be generated for
2750 r16 to r25 in the prologue and epilogue respectively.
2752 - Presently library only supports register ranges starting from r13.
2754 if (epilogue_p
== 2 || frame
->millicode_end_reg
> 14)
2756 int start_call
= frame
->millicode_start_reg
;
2757 int end_call
= frame
->millicode_end_reg
;
2758 int n_regs
= end_call
- start_call
+ 1;
2759 int i
= 0, r
, off
= 0;
2761 rtx ret_addr
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
2765 /* "reg_size" won't be more than 127 . */
2766 gcc_assert (epilogue_p
|| abs (*first_offset
) <= 127);
2767 frame_add (base_reg
, *first_offset
);
2770 insn
= gen_rtx_PARALLEL
2771 (VOIDmode
, rtvec_alloc ((epilogue_p
== 2) + n_regs
+ 1));
2772 if (epilogue_p
== 2)
2775 XVECEXP (insn
, 0, n_regs
) = gen_rtx_CLOBBER (VOIDmode
, ret_addr
);
2776 for (r
= start_call
; r
<= end_call
; r
++, off
+= UNITS_PER_WORD
, i
++)
2778 rtx reg
= gen_rtx_REG (SImode
, r
);
2780 = gen_frame_mem (SImode
, plus_constant (Pmode
, base_reg
, off
));
2783 XVECEXP (insn
, 0, i
) = gen_rtx_SET (reg
, mem
);
2785 XVECEXP (insn
, 0, i
) = gen_rtx_SET (mem
, reg
);
2786 gmask
= gmask
& ~(1L << r
);
2788 if (epilogue_p
== 2)
2789 sibthunk_insn
= insn
;
2792 insn
= frame_insn (insn
);
2794 for (r
= start_call
; r
<= end_call
; r
++)
2796 rtx reg
= gen_rtx_REG (SImode
, r
);
2797 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
2803 for (regno
= 0; regno
<= 31; regno
++)
2805 machine_mode mode
= SImode
;
2810 && ((gmask
& (1L << regno
)) != 0)
2811 && ((gmask
& (1L << (regno
+1))) != 0))
2816 else if ((gmask
& (1L << regno
)) != 0)
2824 rtx reg
= gen_rtx_REG (mode
, regno
);
2826 int cfa_adjust
= *first_offset
;
2830 gcc_assert (!offset
);
2831 addr
= plus_constant (Pmode
, base_reg
, *first_offset
);
2832 addr
= gen_rtx_PRE_MODIFY (Pmode
, base_reg
, addr
);
2837 gcc_assert (SMALL_INT (offset
));
2838 addr
= plus_constant (Pmode
, base_reg
, offset
);
2840 mem
= gen_frame_mem (mode
, addr
);
2844 frame_move_inc (reg
, mem
, base_reg
, addr
);
2845 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
2848 enum reg_note note
= REG_CFA_ADJUST_CFA
;
2849 add_reg_note (insn
, note
,
2850 gen_rtx_SET (stack_pointer_rtx
,
2851 plus_constant (Pmode
,
2857 frame_move_inc (mem
, reg
, base_reg
, addr
);
2858 offset
+= UNITS_PER_WORD
;
2861 offset
+= UNITS_PER_WORD
;
2869 int start_call
= frame
->millicode_start_reg
;
2870 int end_call
= frame
->millicode_end_reg
;
2873 rtx r12
= gen_rtx_REG (Pmode
, 12);
2875 frame_insn (gen_rtx_SET (r12
, GEN_INT (offset
)));
2876 XVECEXP (sibthunk_insn
, 0, 0) = ret_rtx
;
2877 XVECEXP (sibthunk_insn
, 0, 1)
2878 = gen_rtx_SET (stack_pointer_rtx
,
2879 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, r12
));
2880 sibthunk_insn
= emit_jump_insn (sibthunk_insn
);
2881 RTX_FRAME_RELATED_P (sibthunk_insn
) = 1;
2883 /* Would be nice if we could do this earlier, when the PARALLEL
2884 is populated, but these need to be attached after the
2886 for (r
= start_call
; r
<= end_call
; r
++)
2888 rtx reg
= gen_rtx_REG (SImode
, r
);
2889 add_reg_note (sibthunk_insn
, REG_CFA_RESTORE
, reg
);
2892 } /* arc_save_restore */
2894 /* Build dwarf information when the context is saved via AUX_IRQ_CTRL
2898 arc_dwarf_emit_irq_save_regs (void)
2900 rtx tmp
, par
, insn
, reg
;
2903 par
= gen_rtx_SEQUENCE (VOIDmode
,
2904 rtvec_alloc (irq_ctrl_saved
.irq_save_last_reg
+ 1
2905 + irq_ctrl_saved
.irq_save_blink
2906 + irq_ctrl_saved
.irq_save_lpcount
2909 /* Build the stack adjustment note for unwind info. */
2911 offset
= UNITS_PER_WORD
* (irq_ctrl_saved
.irq_save_last_reg
+ 1
2912 + irq_ctrl_saved
.irq_save_blink
2913 + irq_ctrl_saved
.irq_save_lpcount
);
2914 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, -1 * offset
);
2915 tmp
= gen_rtx_SET (stack_pointer_rtx
, tmp
);
2916 RTX_FRAME_RELATED_P (tmp
) = 1;
2917 XVECEXP (par
, 0, j
++) = tmp
;
2919 offset
-= UNITS_PER_WORD
;
2921 /* 1st goes LP_COUNT. */
2922 if (irq_ctrl_saved
.irq_save_lpcount
)
2924 reg
= gen_rtx_REG (SImode
, 60);
2925 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
2926 tmp
= gen_frame_mem (SImode
, tmp
);
2927 tmp
= gen_rtx_SET (tmp
, reg
);
2928 RTX_FRAME_RELATED_P (tmp
) = 1;
2929 XVECEXP (par
, 0, j
++) = tmp
;
2930 offset
-= UNITS_PER_WORD
;
2933 /* 2nd goes BLINK. */
2934 if (irq_ctrl_saved
.irq_save_blink
)
2936 reg
= gen_rtx_REG (SImode
, 31);
2937 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
2938 tmp
= gen_frame_mem (SImode
, tmp
);
2939 tmp
= gen_rtx_SET (tmp
, reg
);
2940 RTX_FRAME_RELATED_P (tmp
) = 1;
2941 XVECEXP (par
, 0, j
++) = tmp
;
2942 offset
-= UNITS_PER_WORD
;
2945 /* Build the parallel of the remaining registers recorded as saved
2947 for (i
= irq_ctrl_saved
.irq_save_last_reg
; i
>= 0; i
--)
2949 reg
= gen_rtx_REG (SImode
, i
);
2950 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
2951 tmp
= gen_frame_mem (SImode
, tmp
);
2952 tmp
= gen_rtx_SET (tmp
, reg
);
2953 RTX_FRAME_RELATED_P (tmp
) = 1;
2954 XVECEXP (par
, 0, j
++) = tmp
;
2955 offset
-= UNITS_PER_WORD
;
2958 /* Dummy insn used to anchor the dwarf info. */
2959 insn
= emit_insn (gen_stack_irq_dwarf());
2960 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, par
);
2961 RTX_FRAME_RELATED_P (insn
) = 1;
2964 /* Set up the stack and frame pointer (if desired) for the function. */
2967 arc_expand_prologue (void)
2969 int size
= get_frame_size ();
2970 unsigned int gmask
= cfun
->machine
->frame_info
.gmask
;
2971 /* unsigned int frame_pointer_offset;*/
2972 unsigned int frame_size_to_allocate
;
2973 /* (FIXME: The first store will use a PRE_MODIFY; this will usually be r13.
2974 Change the stack layout so that we rather store a high register with the
2975 PRE_MODIFY, thus enabling more short insn generation.) */
2976 int first_offset
= 0;
2977 unsigned int fn_type
= arc_compute_function_type (cfun
);
2979 /* Naked functions don't have prologue. */
2980 if (ARC_NAKED_P (fn_type
))
2983 size
= ARC_STACK_ALIGN (size
);
2985 /* Compute/get total frame size. */
2986 size
= (!cfun
->machine
->frame_info
.initialized
2987 ? arc_compute_frame_size (size
)
2988 : cfun
->machine
->frame_info
.total_size
);
2990 if (flag_stack_usage_info
)
2991 current_function_static_stack_size
= size
;
2993 /* Keep track of frame size to be allocated. */
2994 frame_size_to_allocate
= size
;
2996 /* These cases shouldn't happen. Catch them now. */
2997 gcc_assert (!(size
== 0 && gmask
));
2999 /* Allocate space for register arguments if this is a variadic function. */
3000 if (cfun
->machine
->frame_info
.pretend_size
!= 0)
3002 /* Ensure pretend_size is maximum of 8 * word_size. */
3003 gcc_assert (cfun
->machine
->frame_info
.pretend_size
<= 32);
3005 frame_stack_add (-(HOST_WIDE_INT
)cfun
->machine
->frame_info
.pretend_size
);
3006 frame_size_to_allocate
-= cfun
->machine
->frame_info
.pretend_size
;
3009 /* IRQ using automatic save mechanism will save the register before
3011 if (ARC_AUTO_IRQ_P (fn_type
)
3012 && !ARC_FAST_INTERRUPT_P (fn_type
))
3014 arc_dwarf_emit_irq_save_regs ();
3017 /* The home-grown ABI says link register is saved first. */
3018 if (arc_must_save_return_addr (cfun
)
3019 && !ARC_AUTOBLINK_IRQ_P (fn_type
))
3021 rtx ra
= gen_rtx_REG (SImode
, RETURN_ADDR_REGNUM
);
3022 rtx mem
= gen_frame_mem (Pmode
,
3023 gen_rtx_PRE_DEC (Pmode
,
3024 stack_pointer_rtx
));
3026 frame_move_inc (mem
, ra
, stack_pointer_rtx
, 0);
3027 frame_size_to_allocate
-= UNITS_PER_WORD
;
3030 /* Save any needed call-saved regs (and call-used if this is an
3031 interrupt handler) for ARCompact ISA. */
3032 if (cfun
->machine
->frame_info
.reg_size
)
3034 first_offset
= -cfun
->machine
->frame_info
.reg_size
;
3035 /* N.B. FRAME_POINTER_MASK and RETURN_ADDR_MASK are cleared in gmask. */
3036 arc_save_restore (stack_pointer_rtx
, gmask
, 0, &first_offset
);
3037 frame_size_to_allocate
-= cfun
->machine
->frame_info
.reg_size
;
3040 /* Save frame pointer if needed. First save the FP on stack, if not
3042 if (arc_frame_pointer_needed ()
3043 && !ARC_AUTOFP_IRQ_P (fn_type
))
3045 rtx addr
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
3046 GEN_INT (-UNITS_PER_WORD
+ first_offset
));
3047 rtx mem
= gen_frame_mem (Pmode
, gen_rtx_PRE_MODIFY (Pmode
,
3050 frame_move_inc (mem
, frame_pointer_rtx
, stack_pointer_rtx
, 0);
3051 frame_size_to_allocate
-= UNITS_PER_WORD
;
3055 /* Emit mov fp,sp. */
3056 if (arc_frame_pointer_needed ())
3058 frame_move (frame_pointer_rtx
, stack_pointer_rtx
);
3061 /* ??? We don't handle the case where the saved regs are more than 252
3062 bytes away from sp. This can be handled by decrementing sp once, saving
3063 the regs, and then decrementing it again. The epilogue doesn't have this
3064 problem as the `ld' insn takes reg+limm values (though it would be more
3065 efficient to avoid reg+limm). */
3067 frame_size_to_allocate
-= first_offset
;
3068 /* Allocate the stack frame. */
3069 if (frame_size_to_allocate
> 0)
3071 frame_stack_add ((HOST_WIDE_INT
) 0 - frame_size_to_allocate
);
3072 /* If the frame pointer is needed, emit a special barrier that
3073 will prevent the scheduler from moving stores to the frame
3074 before the stack adjustment. */
3075 if (arc_frame_pointer_needed ())
3076 emit_insn (gen_stack_tie (stack_pointer_rtx
,
3077 hard_frame_pointer_rtx
));
3080 /* Setup the gp register, if needed. */
3081 if (crtl
->uses_pic_offset_table
)
3082 arc_finalize_pic ();
3085 /* Do any necessary cleanup after a function to restore stack, frame,
3089 arc_expand_epilogue (int sibcall_p
)
3091 int size
= get_frame_size ();
3092 unsigned int fn_type
= arc_compute_function_type (cfun
);
3094 size
= ARC_STACK_ALIGN (size
);
3095 size
= (!cfun
->machine
->frame_info
.initialized
3096 ? arc_compute_frame_size (size
)
3097 : cfun
->machine
->frame_info
.total_size
);
3099 unsigned int pretend_size
= cfun
->machine
->frame_info
.pretend_size
;
3100 unsigned int frame_size
;
3101 unsigned int size_to_deallocate
;
3103 int can_trust_sp_p
= !cfun
->calls_alloca
;
3104 int first_offset
= 0;
3105 int millicode_p
= cfun
->machine
->frame_info
.millicode_end_reg
> 0;
3108 /* Naked functions don't have epilogue. */
3109 if (ARC_NAKED_P (fn_type
))
3112 size_to_deallocate
= size
;
3114 frame_size
= size
- (pretend_size
+
3115 cfun
->machine
->frame_info
.reg_size
+
3116 cfun
->machine
->frame_info
.extra_size
);
3118 /* ??? There are lots of optimizations that can be done here.
3119 EG: Use fp to restore regs if it's closer.
3120 Maybe in time we'll do them all. For now, always restore regs from
3121 sp, but don't restore sp if we don't have to. */
3123 if (!can_trust_sp_p
)
3124 gcc_assert (arc_frame_pointer_needed ());
3126 /* Restore stack pointer to the beginning of saved register area for
3130 if (arc_frame_pointer_needed ())
3131 frame_move (stack_pointer_rtx
, frame_pointer_rtx
);
3133 first_offset
= frame_size
;
3134 size_to_deallocate
-= frame_size
;
3136 else if (!can_trust_sp_p
)
3137 frame_stack_add (-frame_size
);
3140 /* Restore any saved registers. */
3141 if (arc_frame_pointer_needed ()
3142 && !ARC_AUTOFP_IRQ_P (fn_type
))
3144 rtx addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
3146 insn
= frame_move_inc (frame_pointer_rtx
, gen_frame_mem (Pmode
, addr
),
3147 stack_pointer_rtx
, 0);
3148 add_reg_note (insn
, REG_CFA_RESTORE
, frame_pointer_rtx
);
3149 add_reg_note (insn
, REG_CFA_DEF_CFA
,
3150 plus_constant (SImode
, stack_pointer_rtx
,
3152 size_to_deallocate
-= UNITS_PER_WORD
;
3155 /* Load blink after the calls to thunk calls in case of optimize size. */
3158 int sibthunk_p
= (!sibcall_p
3159 && fn_type
== ARC_FUNCTION_NORMAL
3160 && !cfun
->machine
->frame_info
.pretend_size
);
3162 gcc_assert (!(cfun
->machine
->frame_info
.gmask
3163 & (FRAME_POINTER_MASK
| RETURN_ADDR_MASK
)));
3164 arc_save_restore (stack_pointer_rtx
,
3165 cfun
->machine
->frame_info
.gmask
,
3166 1 + sibthunk_p
, &first_offset
);
3170 /* If we are to restore registers, and first_offset would require
3171 a limm to be encoded in a PRE_MODIFY, yet we can add it with a
3172 fast add to the stack pointer, do this now. */
3173 if ((!SMALL_INT (first_offset
)
3174 && cfun
->machine
->frame_info
.gmask
3175 && ((TARGET_ARC700
&& !optimize_size
)
3176 ? first_offset
<= 0x800
3177 : satisfies_constraint_C2a (GEN_INT (first_offset
))))
3178 /* Also do this if we have both gprs and return
3179 address to restore, and they both would need a LIMM. */
3180 || (arc_must_save_return_addr (cfun
)
3181 && !SMALL_INT ((cfun
->machine
->frame_info
.reg_size
+ first_offset
) >> 2)
3182 && cfun
->machine
->frame_info
.gmask
))
3184 frame_stack_add (first_offset
);
3187 if (arc_must_save_return_addr (cfun
)
3188 && !ARC_AUTOBLINK_IRQ_P (fn_type
))
3190 rtx ra
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3191 int ra_offs
= cfun
->machine
->frame_info
.reg_size
+ first_offset
;
3192 rtx addr
= plus_constant (Pmode
, stack_pointer_rtx
, ra_offs
);
3193 HOST_WIDE_INT cfa_adjust
= 0;
3195 /* If the load of blink would need a LIMM, but we can add
3196 the offset quickly to sp, do the latter. */
3197 if (!SMALL_INT (ra_offs
>> 2)
3198 && !cfun
->machine
->frame_info
.gmask
3199 && ((TARGET_ARC700
&& !optimize_size
)
3201 : satisfies_constraint_C2a (GEN_INT (ra_offs
))))
3203 size_to_deallocate
-= ra_offs
- first_offset
;
3205 frame_stack_add (ra_offs
);
3207 addr
= stack_pointer_rtx
;
3209 /* See if we can combine the load of the return address with the
3210 final stack adjustment.
3211 We need a separate load if there are still registers to
3212 restore. We also want a separate load if the combined insn
3213 would need a limm, but a separate load doesn't. */
3215 && !cfun
->machine
->frame_info
.gmask
3216 && (SMALL_INT (ra_offs
) || !SMALL_INT (ra_offs
>> 2)))
3218 addr
= gen_rtx_PRE_MODIFY (Pmode
, stack_pointer_rtx
, addr
);
3219 cfa_adjust
= ra_offs
;
3221 size_to_deallocate
-= cfun
->machine
->frame_info
.reg_size
;
3223 else if (!ra_offs
&& size_to_deallocate
== UNITS_PER_WORD
)
3225 addr
= gen_rtx_POST_INC (Pmode
, addr
);
3226 cfa_adjust
= GET_MODE_SIZE (Pmode
);
3227 size_to_deallocate
= 0;
3230 insn
= frame_move_inc (ra
, gen_frame_mem (Pmode
, addr
),
3231 stack_pointer_rtx
, addr
);
3234 enum reg_note note
= REG_CFA_ADJUST_CFA
;
3236 add_reg_note (insn
, note
,
3237 gen_rtx_SET (stack_pointer_rtx
,
3238 plus_constant (SImode
, stack_pointer_rtx
,
3241 add_reg_note (insn
, REG_CFA_RESTORE
, ra
);
3246 if (cfun
->machine
->frame_info
.reg_size
)
3247 arc_save_restore (stack_pointer_rtx
,
3248 /* The zeroing of these two bits is unnecessary, but leave this in for clarity. */
3249 cfun
->machine
->frame_info
.gmask
3250 & ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
), 1, &first_offset
);
3253 /* The rest of this function does the following:
3254 ARCompact : handle epilogue_delay, restore sp (phase-2), return
3257 /* Keep track of how much of the stack pointer we've restored.
3258 It makes the following a lot more readable. */
3259 size_to_deallocate
+= first_offset
;
3260 restored
= size
- size_to_deallocate
;
3262 if (size
> restored
)
3263 frame_stack_add (size
- restored
);
3265 /* Emit the return instruction. */
3266 if (sibcall_p
== FALSE
)
3267 emit_jump_insn (gen_simple_return ());
3270 /* Return the offset relative to the stack pointer where the return address
3271 is stored, or -1 if it is not stored. */
3274 arc_return_slot_offset ()
3276 struct arc_frame_info
*afi
= &cfun
->machine
->frame_info
;
3278 return (afi
->save_return_addr
3279 ? afi
->total_size
- afi
->pretend_size
- afi
->extra_size
: -1);
3284 /* Helper to generate unspec constant. */
3287 arc_unspec_offset (rtx loc
, int unspec
)
3289 return gen_rtx_CONST (Pmode
, gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, loc
),
3293 /* Emit special PIC prologues and epilogues. */
3294 /* If the function has any GOTOFF relocations, then the GOTBASE
3295 register has to be setup in the prologue
3296 The instruction needed at the function start for setting up the
3299 ----------------------------------------------------------
3300 The rtl to be emitted for this should be:
3303 (const (unspec (symref _DYNAMIC) 3)))
3304 ---------------------------------------------------------- */
3307 arc_finalize_pic (void)
3310 rtx baseptr_rtx
= gen_rtx_REG (Pmode
, PIC_OFFSET_TABLE_REGNUM
);
3312 if (crtl
->uses_pic_offset_table
== 0)
3315 gcc_assert (flag_pic
!= 0);
3317 pat
= gen_rtx_SYMBOL_REF (Pmode
, "_DYNAMIC");
3318 pat
= arc_unspec_offset (pat
, ARC_UNSPEC_GOT
);
3319 pat
= gen_rtx_SET (baseptr_rtx
, pat
);
3324 /* !TARGET_BARREL_SHIFTER support. */
3325 /* Emit a shift insn to set OP0 to OP1 shifted by OP2; CODE specifies what
3329 emit_shift (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
3331 rtx shift
= gen_rtx_fmt_ee (code
, SImode
, op1
, op2
);
3333 = ((shift4_operator (shift
, SImode
) ? gen_shift_si3
: gen_shift_si3_loop
)
3334 (op0
, op1
, op2
, shift
));
3338 /* Output the assembler code for doing a shift.
3339 We go to a bit of trouble to generate efficient code as the ARC601 only has
3340 single bit shifts. This is taken from the h8300 port. We only have one
3341 mode of shifting and can't access individual bytes like the h8300 can, so
3342 this is greatly simplified (at the expense of not generating hyper-
3345 This function is not used if the variable shift insns are present. */
3347 /* FIXME: This probably can be done using a define_split in arc.md.
3348 Alternately, generate rtx rather than output instructions. */
3351 output_shift (rtx
*operands
)
3353 /* static int loopend_lab;*/
3354 rtx shift
= operands
[3];
3355 machine_mode mode
= GET_MODE (shift
);
3356 enum rtx_code code
= GET_CODE (shift
);
3357 const char *shift_one
;
3359 gcc_assert (mode
== SImode
);
3363 case ASHIFT
: shift_one
= "add %0,%1,%1"; break;
3364 case ASHIFTRT
: shift_one
= "asr %0,%1"; break;
3365 case LSHIFTRT
: shift_one
= "lsr %0,%1"; break;
3366 default: gcc_unreachable ();
3369 if (GET_CODE (operands
[2]) != CONST_INT
)
3371 output_asm_insn ("and.f lp_count,%2, 0x1f", operands
);
3378 n
= INTVAL (operands
[2]);
3380 /* Only consider the lower 5 bits of the shift count. */
3383 /* First see if we can do them inline. */
3384 /* ??? We could get better scheduling & shorter code (using short insns)
3385 by using splitters. Alas, that'd be even more verbose. */
3386 if (code
== ASHIFT
&& n
<= 9 && n
> 2
3387 && dest_reg_operand (operands
[4], SImode
))
3389 output_asm_insn ("mov %4,0\n\tadd3 %0,%4,%1", operands
);
3390 for (n
-=3 ; n
>= 3; n
-= 3)
3391 output_asm_insn ("add3 %0,%4,%0", operands
);
3393 output_asm_insn ("add2 %0,%4,%0", operands
);
3395 output_asm_insn ("add %0,%0,%0", operands
);
3401 output_asm_insn (shift_one
, operands
);
3402 operands
[1] = operands
[0];
3405 /* See if we can use a rotate/and. */
3406 else if (n
== BITS_PER_WORD
- 1)
3411 output_asm_insn ("and %0,%1,1\n\tror %0,%0", operands
);
3414 /* The ARC doesn't have a rol insn. Use something else. */
3415 output_asm_insn ("add.f 0,%1,%1\n\tsbc %0,%0,%0", operands
);
3418 /* The ARC doesn't have a rol insn. Use something else. */
3419 output_asm_insn ("add.f 0,%1,%1\n\trlc %0,0", operands
);
3425 else if (n
== BITS_PER_WORD
- 2 && dest_reg_operand (operands
[4], SImode
))
3430 output_asm_insn ("and %0,%1,3\n\tror %0,%0\n\tror %0,%0", operands
);
3433 #if 1 /* Need some scheduling comparisons. */
3434 output_asm_insn ("add.f %4,%1,%1\n\tsbc %0,%0,%0\n\t"
3435 "add.f 0,%4,%4\n\trlc %0,%0", operands
);
3437 output_asm_insn ("add.f %4,%1,%1\n\tbxor %0,%4,31\n\t"
3438 "sbc.f %0,%0,%4\n\trlc %0,%0", operands
);
3443 output_asm_insn ("add.f %4,%1,%1\n\trlc %0,0\n\t"
3444 "add.f 0,%4,%4\n\trlc %0,%0", operands
);
3446 output_asm_insn ("add.f %0,%1,%1\n\trlc.f %0,0\n\t"
3447 "and %0,%0,1\n\trlc %0,%0", operands
);
3454 else if (n
== BITS_PER_WORD
- 3 && code
== ASHIFT
)
3455 output_asm_insn ("and %0,%1,7\n\tror %0,%0\n\tror %0,%0\n\tror %0,%0",
3460 operands
[2] = GEN_INT (n
);
3461 output_asm_insn ("mov.f lp_count, %2", operands
);
3465 output_asm_insn ("lpnz\t2f", operands
);
3466 output_asm_insn (shift_one
, operands
);
3467 output_asm_insn ("nop", operands
);
3468 fprintf (asm_out_file
, "2:\t%s end single insn loop\n",
3477 /* Nested function support. */
3479 /* Directly store VALUE into memory object BLOCK at OFFSET. */
3482 emit_store_direct (rtx block
, int offset
, int value
)
3484 emit_insn (gen_store_direct (adjust_address (block
, SImode
, offset
),
3486 gen_int_mode (value
, SImode
))));
3489 /* Emit RTL insns to initialize the variable parts of a trampoline.
3490 FNADDR is an RTX for the address of the function's pure code.
3491 CXT is an RTX for the static chain value for the function. */
3492 /* With potentially multiple shared objects loaded, and multiple stacks
3493 present for multiple thereds where trampolines might reside, a simple
3494 range check will likely not suffice for the profiler to tell if a callee
3495 is a trampoline. We a speedier check by making the trampoline start at
3496 an address that is not 4-byte aligned.
3497 A trampoline looks like this:
3501 ld_s r12,[pcl,12] 0xd403
3502 ld r11,[pcl,12] 0x170c 700b
3506 The fastest trampoline to execute for trampolines within +-8KB of CTX
3509 j [limm] 0x20200f80 limm
3510 and that would also be faster to write to the stack by computing the offset
3511 from CTX to TRAMP at compile time. However, it would really be better to
3512 get rid of the high cost of cache invalidation when generating trampolines,
3513 which requires that the code part of trampolines stays constant, and
3515 - making sure that no executable code but trampolines is on the stack,
3516 no icache entries linger for the area of the stack from when before the
3517 stack was allocated, and allocating trampolines in trampoline-only
3520 - allocate trampolines fram a special pool of pre-allocated trampolines. */
3523 arc_initialize_trampoline (rtx tramp
, tree fndecl
, rtx cxt
)
3525 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
3527 emit_store_direct (tramp
, 0, TARGET_BIG_ENDIAN
? 0x78e0d403 : 0xd40378e0);
3528 emit_store_direct (tramp
, 4, TARGET_BIG_ENDIAN
? 0x170c700b : 0x700b170c);
3529 emit_store_direct (tramp
, 8, TARGET_BIG_ENDIAN
? 0x7c0078e0 : 0x78e07c00);
3530 emit_move_insn (adjust_address (tramp
, SImode
, 12), fnaddr
);
3531 emit_move_insn (adjust_address (tramp
, SImode
, 16), cxt
);
3532 emit_insn (gen_flush_icache (adjust_address (tramp
, SImode
, 0)));
3535 /* Allow the profiler to easily distinguish trampolines from normal
3539 arc_trampoline_adjust_address (rtx addr
)
3541 return plus_constant (Pmode
, addr
, 2);
3544 /* This is set briefly to 1 when we output a ".as" address modifer, and then
3545 reset when we output the scaled address. */
3546 static int output_scaled
= 0;
3548 /* Print operand X (an rtx) in assembler syntax to file FILE.
3549 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3550 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3551 /* In final.c:output_asm_insn:
3554 'c' : constant address if CONSTANT_ADDRESS_P
3560 'p': bit Position of lsb
3561 's': size of bit field
3562 '#': condbranch delay slot suffix
3563 '*': jump delay slot suffix
3564 '?' : nonjump-insn suffix for conditional execution or short instruction
3565 '!' : jump / call suffix for conditional execution or short instruction
3566 '`': fold constant inside unary o-perator, re-recognize, and emit.
3571 'B': Branch comparison operand - suppress sda reference
3572 'H': Most significant word
3573 'L': Least significant word
3574 'A': ASCII decimal representation of floating point value
3575 'U': Load/store update or scaling indicator
3576 'V': cache bypass indicator for volatile
3581 'o': original symbol - no @ prepending. */
3584 arc_print_operand (FILE *file
, rtx x
, int code
)
3589 if (GET_CODE (x
) == CONST_INT
)
3590 fprintf (file
, "%d",exact_log2(INTVAL (x
) + 1) - 1 );
3592 output_operand_lossage ("invalid operand to %%Z code");
3597 if (GET_CODE (x
) == CONST_INT
)
3598 fprintf (file
, "%d",exact_log2(INTVAL (x
)) );
3600 output_operand_lossage ("invalid operand to %%z code");
3605 if (GET_CODE (x
) == CONST_INT
)
3606 fprintf (file
, "%d", INTVAL (x
) );
3608 output_operand_lossage ("invalid operands to %%c code");
3613 if (GET_CODE (x
) == CONST_INT
)
3614 fprintf (file
, "%d",exact_log2(~INTVAL (x
)) );
3616 output_operand_lossage ("invalid operand to %%M code");
3621 if (GET_CODE (x
) == CONST_INT
)
3622 fprintf (file
, "%d", exact_log2 (INTVAL (x
) & -INTVAL (x
)));
3624 output_operand_lossage ("invalid operand to %%p code");
3628 if (GET_CODE (x
) == CONST_INT
)
3630 HOST_WIDE_INT i
= INTVAL (x
);
3631 HOST_WIDE_INT s
= exact_log2 (i
& -i
);
3632 fprintf (file
, "%d", exact_log2 (((0xffffffffUL
& i
) >> s
) + 1));
3635 output_operand_lossage ("invalid operand to %%s code");
3639 /* Conditional branches depending on condition codes.
3640 Note that this is only for branches that were known to depend on
3641 condition codes before delay slot scheduling;
3642 out-of-range brcc / bbit expansions should use '*'.
3643 This distinction is important because of the different
3644 allowable delay slot insns and the output of the delay suffix
3645 for TARGET_AT_DBR_COND_EXEC. */
3647 /* Unconditional branches / branches not depending on condition codes.
3648 This could also be a CALL_INSN.
3649 Output the appropriate delay slot suffix. */
3650 if (final_sequence
&& final_sequence
->len () != 1)
3652 rtx_insn
*jump
= final_sequence
->insn (0);
3653 rtx_insn
*delay
= final_sequence
->insn (1);
3655 /* For TARGET_PAD_RETURN we might have grabbed the delay insn. */
3656 if (delay
->deleted ())
3658 if (JUMP_P (jump
) && INSN_ANNULLED_BRANCH_P (jump
))
3659 fputs (INSN_FROM_TARGET_P (delay
) ? ".d"
3660 : TARGET_AT_DBR_CONDEXEC
&& code
== '#' ? ".d"
3661 : get_attr_type (jump
) == TYPE_RETURN
&& code
== '#' ? ""
3668 case '?' : /* with leading "." */
3669 case '!' : /* without leading "." */
3670 /* This insn can be conditionally executed. See if the ccfsm machinery
3671 says it should be conditionalized.
3672 If it shouldn't, we'll check the compact attribute if this insn
3673 has a short variant, which may be used depending on code size and
3674 alignment considerations. */
3675 if (current_insn_predicate
)
3676 arc_ccfsm_current
.cc
3677 = get_arc_condition_code (current_insn_predicate
);
3678 if (ARC_CCFSM_COND_EXEC_P (&arc_ccfsm_current
))
3680 /* Is this insn in a delay slot sequence? */
3681 if (!final_sequence
|| XVECLEN (final_sequence
, 0) < 2
3682 || current_insn_predicate
3683 || CALL_P (final_sequence
->insn (0))
3684 || simplejump_p (final_sequence
->insn (0)))
3686 /* This insn isn't in a delay slot sequence, or conditionalized
3687 independently of its position in a delay slot. */
3688 fprintf (file
, "%s%s",
3689 code
== '?' ? "." : "",
3690 arc_condition_codes
[arc_ccfsm_current
.cc
]);
3691 /* If this is a jump, there are still short variants. However,
3692 only beq_s / bne_s have the same offset range as b_s,
3693 and the only short conditional returns are jeq_s and jne_s. */
3695 && (arc_ccfsm_current
.cc
== ARC_CC_EQ
3696 || arc_ccfsm_current
.cc
== ARC_CC_NE
3697 || 0 /* FIXME: check if branch in 7 bit range. */))
3698 output_short_suffix (file
);
3700 else if (code
== '!') /* Jump with delay slot. */
3701 fputs (arc_condition_codes
[arc_ccfsm_current
.cc
], file
);
3702 else /* An Instruction in a delay slot of a jump or call. */
3704 rtx jump
= XVECEXP (final_sequence
, 0, 0);
3705 rtx insn
= XVECEXP (final_sequence
, 0, 1);
3707 /* If the insn is annulled and is from the target path, we need
3708 to inverse the condition test. */
3709 if (JUMP_P (jump
) && INSN_ANNULLED_BRANCH_P (jump
))
3711 if (INSN_FROM_TARGET_P (insn
))
3712 fprintf (file
, "%s%s",
3713 code
== '?' ? "." : "",
3714 arc_condition_codes
[ARC_INVERSE_CONDITION_CODE (arc_ccfsm_current
.cc
)]);
3716 fprintf (file
, "%s%s",
3717 code
== '?' ? "." : "",
3718 arc_condition_codes
[arc_ccfsm_current
.cc
]);
3719 if (arc_ccfsm_current
.state
== 5)
3720 arc_ccfsm_current
.state
= 0;
3723 /* This insn is executed for either path, so don't
3724 conditionalize it at all. */
3725 output_short_suffix (file
);
3730 output_short_suffix (file
);
3733 /* FIXME: fold constant inside unary operator, re-recognize, and emit. */
3736 fputs (arc_condition_codes
[get_arc_condition_code (x
)], file
);
3739 fputs (arc_condition_codes
[ARC_INVERSE_CONDITION_CODE
3740 (get_arc_condition_code (x
))],
3744 /* Write second word of DImode or DFmode reference,
3745 register or memory. */
3746 if (GET_CODE (x
) == REG
)
3747 fputs (reg_names
[REGNO (x
)+1], file
);
3748 else if (GET_CODE (x
) == MEM
)
3752 /* Handle possible auto-increment. For PRE_INC / PRE_DEC /
3753 PRE_MODIFY, we will have handled the first word already;
3754 For POST_INC / POST_DEC / POST_MODIFY, the access to the
3755 first word will be done later. In either case, the access
3756 to the first word will do the modify, and we only have
3757 to add an offset of four here. */
3758 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
3759 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
3760 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
3761 || GET_CODE (XEXP (x
, 0)) == POST_INC
3762 || GET_CODE (XEXP (x
, 0)) == POST_DEC
3763 || GET_CODE (XEXP (x
, 0)) == POST_MODIFY
)
3764 output_address (VOIDmode
,
3765 plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 4));
3766 else if (output_scaled
)
3768 rtx addr
= XEXP (x
, 0);
3769 int size
= GET_MODE_SIZE (GET_MODE (x
));
3771 output_address (VOIDmode
,
3772 plus_constant (Pmode
, XEXP (addr
, 0),
3773 ((INTVAL (XEXP (addr
, 1)) + 4)
3774 >> (size
== 2 ? 1 : 2))));
3778 output_address (VOIDmode
,
3779 plus_constant (Pmode
, XEXP (x
, 0), 4));
3783 output_operand_lossage ("invalid operand to %%R code");
3786 /* FIXME: remove %S option. */
3788 case 'B' /* Branch or other LIMM ref - must not use sda references. */ :
3791 output_addr_const (file
, x
);
3797 if (GET_CODE (x
) == REG
)
3799 /* L = least significant word, H = most significant word. */
3800 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
3801 fputs (reg_names
[REGNO (x
)], file
);
3803 fputs (reg_names
[REGNO (x
)+1], file
);
3805 else if (GET_CODE (x
) == CONST_INT
3806 || GET_CODE (x
) == CONST_DOUBLE
)
3808 rtx first
, second
, word
;
3810 split_double (x
, &first
, &second
);
3812 if((WORDS_BIG_ENDIAN
) == 0)
3813 word
= (code
== 'L' ? first
: second
);
3815 word
= (code
== 'L' ? second
: first
);
3817 fprintf (file
, "0x%08" PRIx32
, ((uint32_t) INTVAL (word
)));
3820 output_operand_lossage ("invalid operand to %%H/%%L code");
3826 gcc_assert (GET_CODE (x
) == CONST_DOUBLE
3827 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
);
3829 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
3830 fprintf (file
, "%s", str
);
3834 /* Output a load/store with update indicator if appropriate. */
3835 if (GET_CODE (x
) == MEM
)
3837 rtx addr
= XEXP (x
, 0);
3838 switch (GET_CODE (addr
))
3840 case PRE_INC
: case PRE_DEC
: case PRE_MODIFY
:
3841 fputs (".a", file
); break;
3842 case POST_INC
: case POST_DEC
: case POST_MODIFY
:
3843 fputs (".ab", file
); break;
3845 /* Are we using a scaled index? */
3846 if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3847 fputs (".as", file
);
3848 /* Can we use a scaled offset? */
3849 else if (CONST_INT_P (XEXP (addr
, 1))
3850 && GET_MODE_SIZE (GET_MODE (x
)) > 1
3851 && (!(INTVAL (XEXP (addr
, 1))
3852 & (GET_MODE_SIZE (GET_MODE (x
)) - 1) & 3))
3853 /* Does it make a difference? */
3854 && !SMALL_INT_RANGE(INTVAL (XEXP (addr
, 1)),
3855 GET_MODE_SIZE (GET_MODE (x
)) - 2, 0))
3857 fputs (".as", file
);
3860 else if (LEGITIMATE_SMALL_DATA_ADDRESS_P (addr
)
3861 && GET_MODE_SIZE (GET_MODE (x
)) > 1)
3863 tree decl
= NULL_TREE
;
3865 if (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
)
3866 decl
= SYMBOL_REF_DECL (XEXP (addr
, 1));
3867 else if (GET_CODE (XEXP (XEXP (XEXP (addr
, 1), 0), 0))
3869 decl
= SYMBOL_REF_DECL (XEXP (XEXP (XEXP (addr
, 1), 0), 0));
3871 align
= DECL_ALIGN (decl
);
3872 align
= align
/ BITS_PER_UNIT
;
3873 if ((GET_MODE_SIZE (GET_MODE (x
)) == 2)
3874 && align
&& ((align
& 1) == 0))
3875 fputs (".as", file
);
3876 if ((GET_MODE_SIZE (GET_MODE (x
)) >= 4)
3877 && align
&& ((align
& 3) == 0))
3878 fputs (".as", file
);
3884 gcc_assert (CONSTANT_P (addr
)); break;
3888 output_operand_lossage ("invalid operand to %%U code");
3891 /* Output cache bypass indicator for a load/store insn. Volatile memory
3892 refs are defined to use the cache bypass mechanism. */
3893 if (GET_CODE (x
) == MEM
)
3895 if (MEM_VOLATILE_P (x
) && !TARGET_VOLATILE_CACHE_SET
)
3896 fputs (".di", file
);
3899 output_operand_lossage ("invalid operand to %%V code");
3904 /* Do nothing special. */
3907 fputs (reg_names
[REGNO (x
)]+1, file
);
3910 /* This punctuation character is needed because label references are
3911 printed in the output template using %l. This is a front end
3912 character, and when we want to emit a '@' before it, we have to use
3918 /* Output an operator. */
3919 switch (GET_CODE (x
))
3921 case PLUS
: fputs ("add", file
); return;
3922 case SS_PLUS
: fputs ("adds", file
); return;
3923 case AND
: fputs ("and", file
); return;
3924 case IOR
: fputs ("or", file
); return;
3925 case XOR
: fputs ("xor", file
); return;
3926 case MINUS
: fputs ("sub", file
); return;
3927 case SS_MINUS
: fputs ("subs", file
); return;
3928 case ASHIFT
: fputs ("asl", file
); return;
3929 case ASHIFTRT
: fputs ("asr", file
); return;
3930 case LSHIFTRT
: fputs ("lsr", file
); return;
3931 case ROTATERT
: fputs ("ror", file
); return;
3932 case MULT
: fputs ("mpy", file
); return;
3933 case ABS
: fputs ("abs", file
); return; /* Unconditional. */
3934 case NEG
: fputs ("neg", file
); return;
3935 case SS_NEG
: fputs ("negs", file
); return;
3936 case NOT
: fputs ("not", file
); return; /* Unconditional. */
3938 fputs ("ext", file
); /* bmsk allows predication. */
3940 case SIGN_EXTEND
: /* Unconditional. */
3941 fputs ("sex", file
);
3943 switch (GET_MODE (XEXP (x
, 0)))
3945 case E_QImode
: fputs ("b", file
); return;
3946 case E_HImode
: fputs ("w", file
); return;
3951 if (GET_MODE (x
) != HImode
)
3953 fputs ("sat16", file
);
3956 output_operand_lossage ("invalid operand to %%O code"); return;
3958 if (GET_CODE (x
) == SYMBOL_REF
)
3960 assemble_name (file
, XSTR (x
, 0));
3965 if (TARGET_ANNOTATE_ALIGN
&& cfun
->machine
->size_reason
)
3966 fprintf (file
, "; unalign: %d", cfun
->machine
->unalign
);
3982 output_operand_lossage ("invalid operand output code");
3985 switch (GET_CODE (x
))
3988 fputs (reg_names
[REGNO (x
)], file
);
3992 rtx addr
= XEXP (x
, 0);
3993 int size
= GET_MODE_SIZE (GET_MODE (x
));
3997 switch (GET_CODE (addr
))
3999 case PRE_INC
: case POST_INC
:
4000 output_address (VOIDmode
,
4001 plus_constant (Pmode
, XEXP (addr
, 0), size
)); break;
4002 case PRE_DEC
: case POST_DEC
:
4003 output_address (VOIDmode
,
4004 plus_constant (Pmode
, XEXP (addr
, 0), -size
));
4006 case PRE_MODIFY
: case POST_MODIFY
:
4007 output_address (VOIDmode
, XEXP (addr
, 1)); break;
4011 output_address (VOIDmode
,
4012 plus_constant (Pmode
, XEXP (addr
, 0),
4013 (INTVAL (XEXP (addr
, 1))
4014 >> (size
== 2 ? 1 : 2))));
4018 output_address (VOIDmode
, addr
);
4021 if (flag_pic
&& CONSTANT_ADDRESS_P (addr
))
4022 arc_output_pic_addr_const (file
, addr
, code
);
4024 output_address (VOIDmode
, addr
);
4031 /* We handle SFmode constants here as output_addr_const doesn't. */
4032 if (GET_MODE (x
) == SFmode
)
4036 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
4037 fprintf (file
, "0x%08lx", l
);
4041 /* Let output_addr_const deal with it. */
4044 || (GET_CODE (x
) == CONST
4045 && GET_CODE (XEXP (x
, 0)) == UNSPEC
4046 && (XINT (XEXP (x
, 0), 1) == UNSPEC_TLS_OFF
4047 || XINT (XEXP (x
, 0), 1) == UNSPEC_TLS_GD
))
4048 || (GET_CODE (x
) == CONST
4049 && GET_CODE (XEXP (x
, 0)) == PLUS
4050 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == UNSPEC
4051 && (XINT (XEXP (XEXP (x
, 0), 0), 1) == UNSPEC_TLS_OFF
4052 || XINT (XEXP (XEXP (x
, 0), 0), 1) == UNSPEC_TLS_GD
)))
4053 arc_output_pic_addr_const (file
, x
, code
);
4056 /* FIXME: Dirty way to handle @var@sda+const. Shd be handled
4057 with asm_output_symbol_ref */
4058 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4061 output_addr_const (file
, XEXP (x
, 0));
4062 if (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (XEXP (x
, 0)))
4063 fprintf (file
, "@sda");
4065 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
4066 || INTVAL (XEXP (x
, 1)) >= 0)
4067 fprintf (file
, "+");
4068 output_addr_const (file
, XEXP (x
, 1));
4071 output_addr_const (file
, x
);
4073 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (x
))
4074 fprintf (file
, "@sda");
4079 /* Print a memory address as an operand to reference that memory location. */
4082 arc_print_operand_address (FILE *file
, rtx addr
)
4084 register rtx base
, index
= 0;
4086 switch (GET_CODE (addr
))
4089 fputs (reg_names
[REGNO (addr
)], file
);
4092 output_addr_const (file
, addr
);
4093 if (SYMBOL_REF_SMALL_P (addr
))
4094 fprintf (file
, "@sda");
4097 if (GET_CODE (XEXP (addr
, 0)) == MULT
)
4098 index
= XEXP (XEXP (addr
, 0), 0), base
= XEXP (addr
, 1);
4099 else if (CONST_INT_P (XEXP (addr
, 0)))
4100 index
= XEXP (addr
, 0), base
= XEXP (addr
, 1);
4102 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
4104 gcc_assert (OBJECT_P (base
));
4105 arc_print_operand_address (file
, base
);
4106 if (CONSTANT_P (base
) && CONST_INT_P (index
))
4110 gcc_assert (OBJECT_P (index
));
4111 arc_print_operand_address (file
, index
);
4115 rtx c
= XEXP (addr
, 0);
4117 if ((GET_CODE (c
) == UNSPEC
4118 && (XINT (c
, 1) == UNSPEC_TLS_OFF
4119 || XINT (c
, 1) == UNSPEC_TLS_IE
))
4120 || (GET_CODE (c
) == PLUS
4121 && GET_CODE (XEXP (c
, 0)) == UNSPEC
4122 && (XINT (XEXP (c
, 0), 1) == UNSPEC_TLS_OFF
4123 || XINT (XEXP (c
, 0), 1) == ARC_UNSPEC_GOTOFFPC
)))
4125 arc_output_pic_addr_const (file
, c
, 0);
4128 gcc_assert (GET_CODE (c
) == PLUS
);
4129 gcc_assert (GET_CODE (XEXP (c
, 0)) == SYMBOL_REF
);
4130 gcc_assert (GET_CODE (XEXP (c
, 1)) == CONST_INT
);
4132 output_address (VOIDmode
, XEXP (addr
, 0));
4138 /* We shouldn't get here as we've lost the mode of the memory object
4139 (which says how much to inc/dec by. */
4144 arc_output_pic_addr_const (file
, addr
, 0);
4146 output_addr_const (file
, addr
);
4151 /* Conditional execution support.
4153 This is based on the ARM port but for now is much simpler.
4155 A finite state machine takes care of noticing whether or not instructions
4156 can be conditionally executed, and thus decrease execution time and code
4157 size by deleting branch instructions. The fsm is controlled by
4158 arc_ccfsm_advance (called by arc_final_prescan_insn), and controls the
4159 actions of PRINT_OPERAND. The patterns in the .md file for the branch
4160 insns also have a hand in this. */
4161 /* The way we leave dealing with non-anulled or annull-false delay slot
4162 insns to the consumer is awkward. */
4164 /* The state of the fsm controlling condition codes are:
4165 0: normal, do nothing special
4166 1: don't output this insn
4167 2: don't output this insn
4168 3: make insns conditional
4169 4: make insns conditional
4170 5: make insn conditional (only for outputting anulled delay slot insns)
4172 special value for cfun->machine->uid_ccfsm_state:
4173 6: return with but one insn before it since function start / call
4175 State transitions (state->state by whom, under what condition):
4176 0 -> 1 arc_ccfsm_advance, if insn is a conditional branch skipping over
4178 0 -> 2 arc_ccfsm_advance, if insn is a conditional branch followed
4179 by zero or more non-jump insns and an unconditional branch with
4180 the same target label as the condbranch.
4181 1 -> 3 branch patterns, after having not output the conditional branch
4182 2 -> 4 branch patterns, after having not output the conditional branch
4183 0 -> 5 branch patterns, for anulled delay slot insn.
4184 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL, if the `target' label is reached
4185 (the target label has CODE_LABEL_NUMBER equal to
4186 arc_ccfsm_target_label).
4187 4 -> 0 arc_ccfsm_advance, if `target' unconditional branch is reached
4188 3 -> 1 arc_ccfsm_advance, finding an 'else' jump skipping over some insns.
4189 5 -> 0 when outputting the delay slot insn
4191 If the jump clobbers the conditions then we use states 2 and 4.
4193 A similar thing can be done with conditional return insns.
4195 We also handle separating branches from sets of the condition code.
4196 This is done here because knowledge of the ccfsm state is required,
4197 we may not be outputting the branch. */
4199 /* arc_final_prescan_insn calls arc_ccfsm_advance to adjust arc_ccfsm_current,
4200 before letting final output INSN. */
4203 arc_ccfsm_advance (rtx_insn
*insn
, struct arc_ccfsm
*state
)
4205 /* BODY will hold the body of INSN. */
4208 /* This will be 1 if trying to repeat the trick (ie: do the `else' part of
4209 an if/then/else), and things need to be reversed. */
4212 /* If we start with a return insn, we only succeed if we find another one. */
4213 int seeking_return
= 0;
4215 /* START_INSN will hold the insn from where we start looking. This is the
4216 first insn after the following code_label if REVERSE is true. */
4217 rtx_insn
*start_insn
= insn
;
4219 /* Type of the jump_insn. Brcc insns don't affect ccfsm changes,
4220 since they don't rely on a cmp preceding the. */
4221 enum attr_type jump_insn_type
;
4223 /* Allow -mdebug-ccfsm to turn this off so we can see how well it does.
4224 We can't do this in macro FINAL_PRESCAN_INSN because its called from
4225 final_scan_insn which has `optimize' as a local. */
4226 if (optimize
< 2 || TARGET_NO_COND_EXEC
)
4229 /* Ignore notes and labels. */
4232 body
= PATTERN (insn
);
4233 /* If in state 4, check if the target branch is reached, in order to
4234 change back to state 0. */
4235 if (state
->state
== 4)
4237 if (insn
== state
->target_insn
)
4239 state
->target_insn
= NULL
;
4245 /* If in state 3, it is possible to repeat the trick, if this insn is an
4246 unconditional branch to a label, and immediately following this branch
4247 is the previous target label which is only used once, and the label this
4248 branch jumps to is not too far off. Or in other words "we've done the
4249 `then' part, see if we can do the `else' part." */
4250 if (state
->state
== 3)
4252 if (simplejump_p (insn
))
4254 start_insn
= next_nonnote_insn (start_insn
);
4255 if (GET_CODE (start_insn
) == BARRIER
)
4257 /* ??? Isn't this always a barrier? */
4258 start_insn
= next_nonnote_insn (start_insn
);
4260 if (GET_CODE (start_insn
) == CODE_LABEL
4261 && CODE_LABEL_NUMBER (start_insn
) == state
->target_label
4262 && LABEL_NUSES (start_insn
) == 1)
4267 else if (GET_CODE (body
) == SIMPLE_RETURN
)
4269 start_insn
= next_nonnote_insn (start_insn
);
4270 if (GET_CODE (start_insn
) == BARRIER
)
4271 start_insn
= next_nonnote_insn (start_insn
);
4272 if (GET_CODE (start_insn
) == CODE_LABEL
4273 && CODE_LABEL_NUMBER (start_insn
) == state
->target_label
4274 && LABEL_NUSES (start_insn
) == 1)
4286 if (GET_CODE (insn
) != JUMP_INSN
4287 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
4288 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
)
4291 /* We can't predicate BRCC or loop ends.
4292 Also, when generating PIC code, and considering a medium range call,
4293 we can't predicate the call. */
4294 jump_insn_type
= get_attr_type (insn
);
4295 if (jump_insn_type
== TYPE_BRCC
4296 || jump_insn_type
== TYPE_BRCC_NO_DELAY_SLOT
4297 || jump_insn_type
== TYPE_LOOP_END
4298 || (jump_insn_type
== TYPE_CALL
&& !get_attr_predicable (insn
)))
4301 /* This jump might be paralleled with a clobber of the condition codes,
4302 the jump should always come first. */
4303 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
4304 body
= XVECEXP (body
, 0, 0);
4307 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
4308 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
4310 int insns_skipped
= 0, fail
= FALSE
, succeed
= FALSE
;
4311 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
4312 int then_not_else
= TRUE
;
4313 /* Nonzero if next insn must be the target label. */
4314 int next_must_be_target_label_p
;
4315 rtx_insn
*this_insn
= start_insn
;
4318 /* Register the insn jumped to. */
4321 if (!seeking_return
)
4322 label
= XEXP (SET_SRC (body
), 0);
4324 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
4325 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
4326 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
4328 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
4329 then_not_else
= FALSE
;
4331 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == SIMPLE_RETURN
)
4333 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == SIMPLE_RETURN
)
4336 then_not_else
= FALSE
;
4341 /* If this is a non-annulled branch with a delay slot, there is
4342 no need to conditionalize the delay slot. */
4343 if ((GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) == SEQUENCE
)
4344 && state
->state
== 0 && !INSN_ANNULLED_BRANCH_P (insn
))
4346 this_insn
= NEXT_INSN (this_insn
);
4348 /* See how many insns this branch skips, and what kind of insns. If all
4349 insns are okay, and the label or unconditional branch to the same
4350 label is not too far away, succeed. */
4351 for (insns_skipped
= 0, next_must_be_target_label_p
= FALSE
;
4352 !fail
&& !succeed
&& insns_skipped
< MAX_INSNS_SKIPPED
;
4357 this_insn
= next_nonnote_insn (this_insn
);
4361 if (next_must_be_target_label_p
)
4363 if (GET_CODE (this_insn
) == BARRIER
)
4365 if (GET_CODE (this_insn
) == CODE_LABEL
4366 && this_insn
== label
)
4376 switch (GET_CODE (this_insn
))
4379 /* Succeed if it is the target label, otherwise fail since
4380 control falls in from somewhere else. */
4381 if (this_insn
== label
)
4391 /* Succeed if the following insn is the target label.
4393 If return insns are used then the last insn in a function
4394 will be a barrier. */
4395 next_must_be_target_label_p
= TRUE
;
4399 /* Can handle a call insn if there are no insns after it.
4400 IE: The next "insn" is the target label. We don't have to
4401 worry about delay slots as such insns are SEQUENCE's inside
4402 INSN's. ??? It is possible to handle such insns though. */
4403 if (get_attr_cond (this_insn
) == COND_CANUSE
)
4404 next_must_be_target_label_p
= TRUE
;
4410 scanbody
= PATTERN (this_insn
);
4412 /* If this is an unconditional branch to the same label, succeed.
4413 If it is to another label, do nothing. If it is conditional,
4415 /* ??? Probably, the test for the SET and the PC are
4418 if (GET_CODE (scanbody
) == SET
4419 && GET_CODE (SET_DEST (scanbody
)) == PC
)
4421 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
4422 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
4427 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
4429 else if (get_attr_cond (this_insn
) != COND_CANUSE
)
4432 else if (GET_CODE (scanbody
) == SIMPLE_RETURN
4438 else if (GET_CODE (scanbody
) == PARALLEL
)
4440 if (get_attr_cond (this_insn
) != COND_CANUSE
)
4446 scanbody
= PATTERN (this_insn
);
4448 /* We can only do this with insns that can use the condition
4449 codes (and don't set them). */
4450 if (GET_CODE (scanbody
) == SET
4451 || GET_CODE (scanbody
) == PARALLEL
)
4453 if (get_attr_cond (this_insn
) != COND_CANUSE
)
4456 /* We can't handle other insns like sequences. */
4468 if ((!seeking_return
) && (state
->state
== 1 || reverse
))
4469 state
->target_label
= CODE_LABEL_NUMBER (label
);
4470 else if (seeking_return
|| state
->state
== 2)
4472 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
4474 this_insn
= next_nonnote_insn (this_insn
);
4476 gcc_assert (!this_insn
||
4477 (GET_CODE (this_insn
) != BARRIER
4478 && GET_CODE (this_insn
) != CODE_LABEL
));
4482 /* Oh dear! we ran off the end, give up. */
4483 extract_insn_cached (insn
);
4485 state
->target_insn
= NULL
;
4488 state
->target_insn
= this_insn
;
4493 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
4497 state
->cond
= XEXP (SET_SRC (body
), 0);
4498 state
->cc
= get_arc_condition_code (XEXP (SET_SRC (body
), 0));
4501 if (reverse
|| then_not_else
)
4502 state
->cc
= ARC_INVERSE_CONDITION_CODE (state
->cc
);
4505 /* Restore recog_operand. Getting the attributes of other insns can
4506 destroy this array, but final.c assumes that it remains intact
4507 across this call; since the insn has been recognized already we
4508 call insn_extract direct. */
4509 extract_insn_cached (insn
);
4513 /* Record that we are currently outputting label NUM with prefix PREFIX.
4514 It it's the label we're looking for, reset the ccfsm machinery.
4516 Called from ASM_OUTPUT_INTERNAL_LABEL. */
4519 arc_ccfsm_at_label (const char *prefix
, int num
, struct arc_ccfsm
*state
)
4521 if (state
->state
== 3 && state
->target_label
== num
4522 && !strcmp (prefix
, "L"))
4525 state
->target_insn
= NULL
;
4529 /* We are considering a conditional branch with the condition COND.
4530 Check if we want to conditionalize a delay slot insn, and if so modify
4531 the ccfsm state accordingly.
4532 REVERSE says branch will branch when the condition is false. */
4534 arc_ccfsm_record_condition (rtx cond
, bool reverse
, rtx_insn
*jump
,
4535 struct arc_ccfsm
*state
)
4537 rtx_insn
*seq_insn
= NEXT_INSN (PREV_INSN (jump
));
4539 state
= &arc_ccfsm_current
;
4541 gcc_assert (state
->state
== 0);
4542 if (seq_insn
!= jump
)
4544 rtx insn
= XVECEXP (PATTERN (seq_insn
), 0, 1);
4546 if (!as_a
<rtx_insn
*> (insn
)->deleted ()
4547 && INSN_ANNULLED_BRANCH_P (jump
)
4548 && (TARGET_AT_DBR_CONDEXEC
|| INSN_FROM_TARGET_P (insn
)))
4551 state
->cc
= get_arc_condition_code (cond
);
4553 arc_ccfsm_current
.cc
4554 = ARC_INVERSE_CONDITION_CODE (state
->cc
);
4555 rtx pat
= PATTERN (insn
);
4556 if (GET_CODE (pat
) == COND_EXEC
)
4557 gcc_assert ((INSN_FROM_TARGET_P (insn
)
4558 ? ARC_INVERSE_CONDITION_CODE (state
->cc
) : state
->cc
)
4559 == get_arc_condition_code (XEXP (pat
, 0)));
4566 /* Update *STATE as we would when we emit INSN. */
4569 arc_ccfsm_post_advance (rtx_insn
*insn
, struct arc_ccfsm
*state
)
4571 enum attr_type type
;
4574 arc_ccfsm_at_label ("L", CODE_LABEL_NUMBER (insn
), state
);
4575 else if (JUMP_P (insn
)
4576 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
4577 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
4578 && ((type
= get_attr_type (insn
)) == TYPE_BRANCH
4579 || ((type
== TYPE_UNCOND_BRANCH
4580 || type
== TYPE_RETURN
)
4581 && ARC_CCFSM_BRANCH_DELETED_P (state
))))
4583 if (ARC_CCFSM_BRANCH_DELETED_P (state
))
4584 ARC_CCFSM_RECORD_BRANCH_DELETED (state
);
4587 rtx src
= SET_SRC (PATTERN (insn
));
4588 arc_ccfsm_record_condition (XEXP (src
, 0), XEXP (src
, 1) == pc_rtx
,
4592 else if (arc_ccfsm_current
.state
== 5)
4593 arc_ccfsm_current
.state
= 0;
4596 /* Return true if the current insn, which is a conditional branch, is to be
4600 arc_ccfsm_branch_deleted_p (void)
4602 return ARC_CCFSM_BRANCH_DELETED_P (&arc_ccfsm_current
);
4605 /* Record a branch isn't output because subsequent insns can be
4609 arc_ccfsm_record_branch_deleted (void)
4611 ARC_CCFSM_RECORD_BRANCH_DELETED (&arc_ccfsm_current
);
4614 /* During insn output, indicate if the current insn is predicated. */
4617 arc_ccfsm_cond_exec_p (void)
4619 return (cfun
->machine
->prescan_initialized
4620 && ARC_CCFSM_COND_EXEC_P (&arc_ccfsm_current
));
4623 /* Like next_active_insn, but return NULL if we find an ADDR_(DIFF_)VEC,
4624 and look inside SEQUENCEs. */
4627 arc_next_active_insn (rtx_insn
*insn
, struct arc_ccfsm
*statep
)
4634 arc_ccfsm_post_advance (insn
, statep
);
4635 insn
= NEXT_INSN (insn
);
4636 if (!insn
|| BARRIER_P (insn
))
4639 arc_ccfsm_advance (insn
, statep
);
4641 while (NOTE_P (insn
)
4642 || (cfun
->machine
->arc_reorg_started
4643 && LABEL_P (insn
) && !label_to_alignment (insn
))
4644 || (NONJUMP_INSN_P (insn
)
4645 && (GET_CODE (PATTERN (insn
)) == USE
4646 || GET_CODE (PATTERN (insn
)) == CLOBBER
)));
4647 if (!LABEL_P (insn
))
4649 gcc_assert (INSN_P (insn
));
4650 pat
= PATTERN (insn
);
4651 if (GET_CODE (pat
) == ADDR_VEC
|| GET_CODE (pat
) == ADDR_DIFF_VEC
)
4653 if (GET_CODE (pat
) == SEQUENCE
)
4654 return as_a
<rtx_insn
*> (XVECEXP (pat
, 0, 0));
4659 /* When deciding if an insn should be output short, we want to know something
4660 about the following insns:
4661 - if another insn follows which we know we can output as a short insn
4662 before an alignment-sensitive point, we can output this insn short:
4663 the decision about the eventual alignment can be postponed.
4664 - if a to-be-aligned label comes next, we should output this insn such
4665 as to get / preserve 4-byte alignment.
4666 - if a likely branch without delay slot insn, or a call with an immediately
4667 following short insn comes next, we should out output this insn such as to
4668 get / preserve 2 mod 4 unalignment.
4669 - do the same for a not completely unlikely branch with a short insn
4670 following before any other branch / label.
4671 - in order to decide if we are actually looking at a branch, we need to
4672 call arc_ccfsm_advance.
4673 - in order to decide if we are looking at a short insn, we should know
4674 if it is conditionalized. To a first order of approximation this is
4675 the case if the state from arc_ccfsm_advance from before this insn
4676 indicates the insn is conditionalized. However, a further refinement
4677 could be to not conditionalize an insn if the destination register(s)
4678 is/are dead in the non-executed case. */
4679 /* Return non-zero if INSN should be output as a short insn. UNALIGN is
4680 zero if the current insn is aligned to a 4-byte-boundary, two otherwise.
4681 If CHECK_ATTR is greater than 0, check the iscompact attribute first. */
4684 arc_verify_short (rtx_insn
*insn
, int, int check_attr
)
4686 enum attr_iscompact iscompact
;
4687 struct machine_function
*machine
;
4691 iscompact
= get_attr_iscompact (insn
);
4692 if (iscompact
== ISCOMPACT_FALSE
)
4695 machine
= cfun
->machine
;
4697 if (machine
->force_short_suffix
>= 0)
4698 return machine
->force_short_suffix
;
4700 return (get_attr_length (insn
) & 2) != 0;
4703 /* When outputting an instruction (alternative) that can potentially be short,
4704 output the short suffix if the insn is in fact short, and update
4705 cfun->machine->unalign accordingly. */
4708 output_short_suffix (FILE *file
)
4710 rtx_insn
*insn
= current_output_insn
;
4712 if (arc_verify_short (insn
, cfun
->machine
->unalign
, 1))
4714 fprintf (file
, "_s");
4715 cfun
->machine
->unalign
^= 2;
4717 /* Restore recog_operand. */
4718 extract_insn_cached (insn
);
4721 /* Implement FINAL_PRESCAN_INSN. */
4724 arc_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec ATTRIBUTE_UNUSED
,
4725 int noperands ATTRIBUTE_UNUSED
)
4727 if (TARGET_DUMPISIZE
)
4728 fprintf (asm_out_file
, "\n; at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
4730 /* Output a nop if necessary to prevent a hazard.
4731 Don't do this for delay slots: inserting a nop would
4732 alter semantics, and the only time we would find a hazard is for a
4733 call function result - and in that case, the hazard is spurious to
4735 if (PREV_INSN (insn
)
4736 && PREV_INSN (NEXT_INSN (insn
)) == insn
4737 && arc_hazard (prev_real_insn (insn
), insn
))
4739 current_output_insn
=
4740 emit_insn_before (gen_nop (), NEXT_INSN (PREV_INSN (insn
)));
4741 final_scan_insn (current_output_insn
, asm_out_file
, optimize
, 1, NULL
);
4742 current_output_insn
= insn
;
4744 /* Restore extraction data which might have been clobbered by arc_hazard. */
4745 extract_constrain_insn_cached (insn
);
4747 if (!cfun
->machine
->prescan_initialized
)
4749 /* Clear lingering state from branch shortening. */
4750 memset (&arc_ccfsm_current
, 0, sizeof arc_ccfsm_current
);
4751 cfun
->machine
->prescan_initialized
= 1;
4753 arc_ccfsm_advance (insn
, &arc_ccfsm_current
);
4755 cfun
->machine
->size_reason
= 0;
4758 /* Given FROM and TO register numbers, say whether this elimination is allowed.
4759 Frame pointer elimination is automatically handled.
4761 All eliminations are permissible. If we need a frame
4762 pointer, we must eliminate ARG_POINTER_REGNUM into
4763 FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
4766 arc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
4768 return ((to
== FRAME_POINTER_REGNUM
) || !arc_frame_pointer_needed ());
4771 /* Define the offset between two registers, one to be eliminated, and
4772 the other its replacement, at the start of a routine. */
4775 arc_initial_elimination_offset (int from
, int to
)
4777 if (! cfun
->machine
->frame_info
.initialized
)
4778 arc_compute_frame_size (get_frame_size ());
4780 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
4782 return (cfun
->machine
->frame_info
.extra_size
4783 + cfun
->machine
->frame_info
.reg_size
);
4786 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
4788 return (cfun
->machine
->frame_info
.total_size
4789 - cfun
->machine
->frame_info
.pretend_size
);
4792 if ((from
== FRAME_POINTER_REGNUM
) && (to
== STACK_POINTER_REGNUM
))
4794 return (cfun
->machine
->frame_info
.total_size
4795 - (cfun
->machine
->frame_info
.pretend_size
4796 + cfun
->machine
->frame_info
.extra_size
4797 + cfun
->machine
->frame_info
.reg_size
));
4804 arc_frame_pointer_required (void)
4806 return cfun
->calls_alloca
;
4810 /* Return the destination address of a branch. */
4813 branch_dest (rtx branch
)
4815 rtx pat
= PATTERN (branch
);
4816 rtx dest
= (GET_CODE (pat
) == PARALLEL
4817 ? SET_SRC (XVECEXP (pat
, 0, 0)) : SET_SRC (pat
));
4820 if (GET_CODE (dest
) == IF_THEN_ELSE
)
4821 dest
= XEXP (dest
, XEXP (dest
, 1) == pc_rtx
? 2 : 1);
4823 dest
= XEXP (dest
, 0);
4824 dest_uid
= INSN_UID (dest
);
4826 return INSN_ADDRESSES (dest_uid
);
4830 /* Implement TARGET_ENCODE_SECTION_INFO hook. */
4833 arc_encode_section_info (tree decl
, rtx rtl
, int first
)
4835 /* For sdata, SYMBOL_FLAG_LOCAL and SYMBOL_FLAG_FUNCTION.
4836 This clears machine specific flags, so has to come first. */
4837 default_encode_section_info (decl
, rtl
, first
);
4839 /* Check if it is a function, and whether it has the
4840 [long/medium/short]_call attribute specified. */
4841 if (TREE_CODE (decl
) == FUNCTION_DECL
)
4843 rtx symbol
= XEXP (rtl
, 0);
4844 int flags
= SYMBOL_REF_FLAGS (symbol
);
4846 tree attr
= (TREE_TYPE (decl
) != error_mark_node
4847 ? TYPE_ATTRIBUTES (TREE_TYPE (decl
)) : NULL_TREE
);
4848 tree long_call_attr
= lookup_attribute ("long_call", attr
);
4849 tree medium_call_attr
= lookup_attribute ("medium_call", attr
);
4850 tree short_call_attr
= lookup_attribute ("short_call", attr
);
4852 if (long_call_attr
!= NULL_TREE
)
4853 flags
|= SYMBOL_FLAG_LONG_CALL
;
4854 else if (medium_call_attr
!= NULL_TREE
)
4855 flags
|= SYMBOL_FLAG_MEDIUM_CALL
;
4856 else if (short_call_attr
!= NULL_TREE
)
4857 flags
|= SYMBOL_FLAG_SHORT_CALL
;
4859 SYMBOL_REF_FLAGS (symbol
) = flags
;
4861 else if (TREE_CODE (decl
) == VAR_DECL
)
4863 rtx symbol
= XEXP (rtl
, 0);
4865 tree attr
= (TREE_TYPE (decl
) != error_mark_node
4866 ? DECL_ATTRIBUTES (decl
) : NULL_TREE
);
4868 tree sec_attr
= lookup_attribute ("section", attr
);
4871 const char *sec_name
4872 = TREE_STRING_POINTER (TREE_VALUE (TREE_VALUE (sec_attr
)));
4873 if (strcmp (sec_name
, ".cmem") == 0
4874 || strcmp (sec_name
, ".cmem_shared") == 0
4875 || strcmp (sec_name
, ".cmem_private") == 0)
4876 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_CMEM
;
4881 /* This is how to output a definition of an internal numbered label where
4882 PREFIX is the class of label and NUM is the number within the class. */
4884 static void arc_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
4887 arc_ccfsm_at_label (prefix
, labelno
, &arc_ccfsm_current
);
4888 default_internal_label (stream
, prefix
, labelno
);
4891 /* Set the cpu type and print out other fancy things,
4892 at the top of the file. */
4894 static void arc_file_start (void)
4896 default_file_start ();
4897 fprintf (asm_out_file
, "\t.cpu %s\n", arc_cpu_string
);
4900 /* Cost functions. */
4902 /* Compute a (partial) cost for rtx X. Return true if the complete
4903 cost has been computed, and false if subexpressions should be
4904 scanned. In either case, *TOTAL contains the cost result. */
4907 arc_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
4908 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
4910 int code
= GET_CODE (x
);
4914 /* Small integers are as cheap as registers. */
4917 bool nolimm
= false; /* Can we do without long immediate? */
4918 bool fast
= false; /* Is the result available immediately? */
4919 bool condexec
= false; /* Does this allow conditiobnal execution? */
4920 bool compact
= false; /* Is a 16 bit opcode available? */
4921 /* CONDEXEC also implies that we can have an unconditional
4922 3-address operation. */
4924 nolimm
= compact
= condexec
= false;
4925 if (UNSIGNED_INT6 (INTVAL (x
)))
4926 nolimm
= condexec
= compact
= true;
4929 if (SMALL_INT (INTVAL (x
)))
4930 nolimm
= fast
= true;
4933 case AND
: /* bclr, bmsk, ext[bw] */
4934 if (satisfies_constraint_Ccp (x
) /* bclr */
4935 || satisfies_constraint_C1p (x
) /* bmsk */)
4936 nolimm
= fast
= condexec
= compact
= true;
4938 case IOR
: /* bset */
4939 if (satisfies_constraint_C0p (x
)) /* bset */
4940 nolimm
= fast
= condexec
= compact
= true;
4943 if (satisfies_constraint_C0p (x
)) /* bxor */
4944 nolimm
= fast
= condexec
= true;
4947 if (satisfies_constraint_Crr (x
)) /* ror b,u6 */
4953 /* FIXME: Add target options to attach a small cost if
4954 condexec / compact is not true. */
4963 /* 4 byte values can be fetched as immediate constants -
4964 let's give that the cost of an extra insn. */
4968 *total
= COSTS_N_INSNS (1);
4977 *total
= COSTS_N_INSNS (1);
4980 split_double (x
, &first
, &second
);
4981 *total
= COSTS_N_INSNS (!SMALL_INT (INTVAL (first
))
4982 + !SMALL_INT (INTVAL (second
)));
4986 /* Encourage synth_mult to find a synthetic multiply when reasonable.
4987 If we need more than 12 insns to do a multiply, then go out-of-line,
4988 since the call overhead will be < 10% of the cost of the multiply. */
4992 if (TARGET_BARREL_SHIFTER
)
4994 /* If we want to shift a constant, we need a LIMM. */
4995 /* ??? when the optimizers want to know if a constant should be
4996 hoisted, they ask for the cost of the constant. OUTER_CODE is
4997 insufficient context for shifts since we don't know which operand
4998 we are looking at. */
4999 if (CONSTANT_P (XEXP (x
, 0)))
5001 *total
+= (COSTS_N_INSNS (2)
5002 + rtx_cost (XEXP (x
, 1), mode
, (enum rtx_code
) code
,
5006 *total
= COSTS_N_INSNS (1);
5008 else if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5009 *total
= COSTS_N_INSNS (16);
5012 *total
= COSTS_N_INSNS (INTVAL (XEXP ((x
), 1)));
5013 /* ??? want_to_gcse_p can throw negative shift counts at us,
5014 and then panics when it gets a negative cost as result.
5015 Seen for gcc.c-torture/compile/20020710-1.c -Os . */
5024 *total
= COSTS_N_INSNS(30);
5026 *total
= COSTS_N_INSNS(1);
5030 if ((TARGET_DPFP
&& GET_MODE (x
) == DFmode
))
5031 *total
= COSTS_N_INSNS (1);
5033 *total
= arc_multcost
;
5034 /* We do not want synth_mult sequences when optimizing
5036 else if (TARGET_MUL64_SET
|| TARGET_ARC700_MPY
)
5037 *total
= COSTS_N_INSNS (1);
5039 *total
= COSTS_N_INSNS (2);
5042 if ((GET_CODE (XEXP (x
, 0)) == ASHIFT
5043 && _1_2_3_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
5044 || (GET_CODE (XEXP (x
, 0)) == MULT
5045 && _2_4_8_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
)))
5047 *total
+= (rtx_cost (XEXP (x
, 1), mode
, PLUS
, 0, speed
)
5048 + rtx_cost (XEXP (XEXP (x
, 0), 0), mode
, PLUS
, 1, speed
));
5053 if ((GET_CODE (XEXP (x
, 1)) == ASHIFT
5054 && _1_2_3_operand (XEXP (XEXP (x
, 1), 1), VOIDmode
))
5055 || (GET_CODE (XEXP (x
, 1)) == MULT
5056 && _2_4_8_operand (XEXP (XEXP (x
, 1), 1), VOIDmode
)))
5058 *total
+= (rtx_cost (XEXP (x
, 0), mode
, PLUS
, 0, speed
)
5059 + rtx_cost (XEXP (XEXP (x
, 1), 0), mode
, PLUS
, 1, speed
));
5065 rtx op0
= XEXP (x
, 0);
5066 rtx op1
= XEXP (x
, 1);
5068 if (GET_CODE (op0
) == ZERO_EXTRACT
&& op1
== const0_rtx
5069 && XEXP (op0
, 1) == const1_rtx
)
5071 /* btst / bbit0 / bbit1:
5072 Small integers and registers are free; everything else can
5073 be put in a register. */
5074 mode
= GET_MODE (XEXP (op0
, 0));
5075 *total
= (rtx_cost (XEXP (op0
, 0), mode
, SET
, 1, speed
)
5076 + rtx_cost (XEXP (op0
, 2), mode
, SET
, 1, speed
));
5079 if (GET_CODE (op0
) == AND
&& op1
== const0_rtx
5080 && satisfies_constraint_C1p (XEXP (op0
, 1)))
5083 *total
= rtx_cost (XEXP (op0
, 0), VOIDmode
, SET
, 1, speed
);
5087 if (GET_CODE (op1
) == NEG
)
5089 /* op0 might be constant, the inside of op1 is rather
5090 unlikely to be so. So swapping the operands might lower
5092 mode
= GET_MODE (op0
);
5093 *total
= (rtx_cost (op0
, mode
, PLUS
, 1, speed
)
5094 + rtx_cost (XEXP (op1
, 0), mode
, PLUS
, 0, speed
));
5099 if (outer_code
== IF_THEN_ELSE
5100 && GET_CODE (XEXP (x
, 0)) == ZERO_EXTRACT
5101 && XEXP (x
, 1) == const0_rtx
5102 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
5104 /* btst / bbit0 / bbit1:
5105 Small integers and registers are free; everything else can
5106 be put in a register. */
5107 rtx op0
= XEXP (x
, 0);
5109 mode
= GET_MODE (XEXP (op0
, 0));
5110 *total
= (rtx_cost (XEXP (op0
, 0), mode
, SET
, 1, speed
)
5111 + rtx_cost (XEXP (op0
, 2), mode
, SET
, 1, speed
));
5115 /* scc_insn expands into two insns. */
5116 case GTU
: case GEU
: case LEU
:
5118 *total
+= COSTS_N_INSNS (1);
5120 case LTU
: /* might use adc. */
5122 *total
+= COSTS_N_INSNS (1) - 1;
5129 /* Return true if ADDR is a valid pic address.
5130 A valid pic address on arc should look like
5131 const (unspec (SYMBOL_REF/LABEL) (ARC_UNSPEC_GOTOFF/ARC_UNSPEC_GOT)) */
5134 arc_legitimate_pic_addr_p (rtx addr
)
5136 if (GET_CODE (addr
) != CONST
)
5139 addr
= XEXP (addr
, 0);
5142 if (GET_CODE (addr
) == PLUS
)
5144 if (GET_CODE (XEXP (addr
, 1)) != CONST_INT
)
5146 addr
= XEXP (addr
, 0);
5149 if (GET_CODE (addr
) != UNSPEC
5150 || XVECLEN (addr
, 0) != 1)
5153 /* Must be one of @GOT, @GOTOFF, @GOTOFFPC, @tlsgd, tlsie. */
5154 if (XINT (addr
, 1) != ARC_UNSPEC_GOT
5155 && XINT (addr
, 1) != ARC_UNSPEC_GOTOFF
5156 && XINT (addr
, 1) != ARC_UNSPEC_GOTOFFPC
5157 && XINT (addr
, 1) != UNSPEC_TLS_GD
5158 && XINT (addr
, 1) != UNSPEC_TLS_IE
)
5161 if (GET_CODE (XVECEXP (addr
, 0, 0)) != SYMBOL_REF
5162 && GET_CODE (XVECEXP (addr
, 0, 0)) != LABEL_REF
)
5170 /* Return true if OP contains a symbol reference. */
5173 symbolic_reference_mentioned_p (rtx op
)
5175 register const char *fmt
;
5178 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
5181 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
5182 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
5188 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
5189 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
5193 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
5200 /* Return true if OP contains a SYMBOL_REF that is not wrapped in an unspec.
5201 If SKIP_LOCAL is true, skip symbols that bind locally.
5202 This is used further down in this file, and, without SKIP_LOCAL,
5203 in the addsi3 / subsi3 expanders when generating PIC code. */
5206 arc_raw_symbolic_reference_mentioned_p (rtx op
, bool skip_local
)
5208 register const char *fmt
;
5211 if (GET_CODE(op
) == UNSPEC
)
5214 if (GET_CODE (op
) == SYMBOL_REF
)
5216 if (SYMBOL_REF_TLS_MODEL (op
))
5220 tree decl
= SYMBOL_REF_DECL (op
);
5221 return !skip_local
|| !decl
|| !default_binds_local_p (decl
);
5224 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
5225 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
5231 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
5232 if (arc_raw_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
),
5237 else if (fmt
[i
] == 'e'
5238 && arc_raw_symbolic_reference_mentioned_p (XEXP (op
, i
),
5246 /* Get the thread pointer. */
5251 /* If arc_tp_regno has been set, we can use that hard register
5252 directly as a base register. */
5253 if (arc_tp_regno
!= -1)
5254 return gen_rtx_REG (Pmode
, arc_tp_regno
);
5256 /* Otherwise, call __read_tp. Copy the result to a pseudo to avoid
5257 conflicts with function arguments / results. */
5258 rtx reg
= gen_reg_rtx (Pmode
);
5259 emit_insn (gen_tls_load_tp_soft ());
5260 emit_move_insn (reg
, gen_rtx_REG (Pmode
, R0_REG
));
5264 /* Helper to be used by TLS Global dynamic model. */
5267 arc_emit_call_tls_get_addr (rtx sym
, int reloc
, rtx eqv
)
5269 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
5270 rtx call_fusage
= NULL_RTX
;
5274 rtx x
= arc_unspec_offset (sym
, reloc
);
5275 emit_move_insn (r0
, x
);
5276 use_reg (&call_fusage
, r0
);
5278 gcc_assert (reloc
== UNSPEC_TLS_GD
);
5279 rtx call_insn
= emit_call_insn (gen_tls_gd_get_addr (sym
));
5280 /* Should we set RTL_CONST_CALL_P? We read memory, but not in a
5281 way that the application should care. */
5282 RTL_PURE_CALL_P (call_insn
) = 1;
5283 add_function_usage_to (call_insn
, call_fusage
);
5285 rtx_insn
*insns
= get_insns ();
5288 rtx dest
= gen_reg_rtx (Pmode
);
5289 emit_libcall_block (insns
, dest
, r0
, eqv
);
5293 #define DTPOFF_ZERO_SYM ".tdata"
5295 /* Return a legitimized address for ADDR,
5296 which is a SYMBOL_REF with tls_model MODEL. */
5299 arc_legitimize_tls_address (rtx addr
, enum tls_model model
)
5301 if (!flag_pic
&& model
== TLS_MODEL_LOCAL_DYNAMIC
)
5302 model
= TLS_MODEL_LOCAL_EXEC
;
5306 case TLS_MODEL_LOCAL_DYNAMIC
:
5309 const char *base_name
;
5312 decl
= SYMBOL_REF_DECL (addr
);
5313 base_name
= DTPOFF_ZERO_SYM
;
5314 if (decl
&& bss_initializer_p (decl
))
5315 base_name
= ".tbss";
5317 base
= gen_rtx_SYMBOL_REF (Pmode
, base_name
);
5318 if (strcmp (base_name
, DTPOFF_ZERO_SYM
) == 0)
5322 v
= gen_rtvec (1, addr
);
5325 v
= gen_rtvec (2, addr
, base
);
5326 addr
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_TLS_OFF
);
5327 addr
= gen_rtx_CONST (Pmode
, addr
);
5328 base
= arc_legitimize_tls_address (base
, TLS_MODEL_GLOBAL_DYNAMIC
);
5329 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, base
), addr
);
5331 case TLS_MODEL_GLOBAL_DYNAMIC
:
5332 return arc_emit_call_tls_get_addr (addr
, UNSPEC_TLS_GD
, addr
);
5334 case TLS_MODEL_INITIAL_EXEC
:
5335 addr
= arc_unspec_offset (addr
, UNSPEC_TLS_IE
);
5336 addr
= copy_to_mode_reg (Pmode
, gen_const_mem (Pmode
, addr
));
5337 return gen_rtx_PLUS (Pmode
, arc_get_tp (), addr
);
5339 case TLS_MODEL_LOCAL_EXEC
:
5341 addr
= arc_unspec_offset (addr
, UNSPEC_TLS_OFF
);
5342 return gen_rtx_PLUS (Pmode
, arc_get_tp (), addr
);
5348 /* Legitimize a pic address reference in ORIG.
5349 The return value is the legitimated address.
5350 If OLDX is non-zero, it is the target to assign the address to first. */
5353 arc_legitimize_pic_address (rtx orig
, rtx oldx
)
5362 if (GET_CODE (addr
) == LABEL_REF
)
5364 else if (GET_CODE (addr
) == SYMBOL_REF
)
5366 enum tls_model model
= SYMBOL_REF_TLS_MODEL (addr
);
5368 return arc_legitimize_tls_address (addr
, model
);
5371 else if (CONSTANT_POOL_ADDRESS_P (addr
) || SYMBOL_REF_LOCAL_P (addr
))
5372 return arc_unspec_offset (addr
, ARC_UNSPEC_GOTOFFPC
);
5374 /* This symbol must be referenced via a load from the Global
5375 Offset Table (@GOTPC). */
5376 pat
= arc_unspec_offset (addr
, ARC_UNSPEC_GOT
);
5377 pat
= gen_const_mem (Pmode
, pat
);
5380 oldx
= gen_reg_rtx (Pmode
);
5382 emit_move_insn (oldx
, pat
);
5387 if (GET_CODE (addr
) == CONST
)
5389 addr
= XEXP (addr
, 0);
5390 if (GET_CODE (addr
) == UNSPEC
)
5392 /* Check that the unspec is one of the ones we generate? */
5395 /* fwprop is placing in the REG_EQUIV notes constant pic
5396 unspecs expressions. Then, loop may use these notes for
5397 optimizations resulting in complex patterns that are not
5398 supported by the current implementation. The following
5399 two if-cases are simplifying the complex patters to
5401 else if (GET_CODE (addr
) == MINUS
)
5403 rtx op0
= XEXP (addr
, 0);
5404 rtx op1
= XEXP (addr
, 1);
5406 gcc_assert (GET_CODE (op1
) == UNSPEC
);
5408 emit_move_insn (oldx
,
5409 gen_rtx_CONST (SImode
,
5410 arc_legitimize_pic_address (op1
,
5412 emit_insn (gen_rtx_SET (oldx
, gen_rtx_MINUS (SImode
, op0
, oldx
)));
5416 else if (GET_CODE (addr
) != PLUS
)
5418 rtx tmp
= XEXP (addr
, 0);
5419 enum rtx_code code
= GET_CODE (addr
);
5421 /* It only works for UNARY operations. */
5422 gcc_assert (UNARY_P (addr
));
5423 gcc_assert (GET_CODE (tmp
) == UNSPEC
);
5428 gen_rtx_CONST (SImode
,
5429 arc_legitimize_pic_address (tmp
,
5432 emit_insn (gen_rtx_SET (oldx
,
5433 gen_rtx_fmt_ee (code
, SImode
,
5434 oldx
, const0_rtx
)));
5440 gcc_assert (GET_CODE (addr
) == PLUS
);
5441 if (GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
5446 if (GET_CODE (addr
) == PLUS
)
5448 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
5450 base
= arc_legitimize_pic_address (op0
, oldx
);
5451 pat
= arc_legitimize_pic_address (op1
,
5452 base
== oldx
? NULL_RTX
: oldx
);
5454 if (base
== op0
&& pat
== op1
)
5457 if (GET_CODE (pat
) == CONST_INT
)
5458 pat
= plus_constant (Pmode
, base
, INTVAL (pat
));
5461 if (GET_CODE (pat
) == PLUS
&& CONSTANT_P (XEXP (pat
, 1)))
5463 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (pat
, 0));
5464 pat
= XEXP (pat
, 1);
5466 pat
= gen_rtx_PLUS (Pmode
, base
, pat
);
5474 /* Output address constant X to FILE, taking PIC into account. */
5477 arc_output_pic_addr_const (FILE * file
, rtx x
, int code
)
5482 switch (GET_CODE (x
))
5492 output_addr_const (file
, x
);
5494 /* Local functions do not get references through the PLT. */
5495 if (code
== 'P' && ! SYMBOL_REF_LOCAL_P (x
))
5496 fputs ("@plt", file
);
5500 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (x
, 0)));
5501 assemble_name (file
, buf
);
5505 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
5506 assemble_name (file
, buf
);
5510 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5514 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
5518 if (GET_MODE (x
) == VOIDmode
)
5520 /* We can use %d if the number is one word and positive. */
5521 if (CONST_DOUBLE_HIGH (x
))
5522 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
5523 CONST_DOUBLE_HIGH (x
), CONST_DOUBLE_LOW (x
));
5524 else if (CONST_DOUBLE_LOW (x
) < 0)
5525 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
5527 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
));
5530 /* We can't handle floating point constants;
5531 PRINT_OPERAND must handle them. */
5532 output_operand_lossage ("floating constant misused");
5536 /* FIXME: Not needed here. */
5537 /* Some assemblers need integer constants to appear last (eg masm). */
5538 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5540 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
5541 fprintf (file
, "+");
5542 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
5544 else if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5546 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
5547 if (INTVAL (XEXP (x
, 1)) >= 0)
5548 fprintf (file
, "+");
5549 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
5556 /* Avoid outputting things like x-x or x+5-x,
5557 since some assemblers can't handle that. */
5558 x
= simplify_subtraction (x
);
5559 if (GET_CODE (x
) != MINUS
)
5562 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
5563 fprintf (file
, "-");
5564 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5565 && INTVAL (XEXP (x
, 1)) < 0)
5567 fprintf (file
, "(");
5568 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
5569 fprintf (file
, ")");
5572 arc_output_pic_addr_const (file
, XEXP (x
, 1), code
);
5577 arc_output_pic_addr_const (file
, XEXP (x
, 0), code
);
5583 bool pcrel
; pcrel
= false;
5584 rtx base
; base
= NULL
;
5585 gcc_assert (XVECLEN (x
, 0) >= 1);
5586 switch (XINT (x
, 1))
5588 case ARC_UNSPEC_GOT
:
5589 suffix
= "@gotpc", pcrel
= true;
5591 case ARC_UNSPEC_GOTOFF
:
5594 case ARC_UNSPEC_GOTOFFPC
:
5595 suffix
= "@pcl", pcrel
= true;
5597 case ARC_UNSPEC_PLT
:
5601 suffix
= "@tlsgd", pcrel
= true;
5604 suffix
= "@tlsie", pcrel
= true;
5606 case UNSPEC_TLS_OFF
:
5607 if (XVECLEN (x
, 0) == 2)
5608 base
= XVECEXP (x
, 0, 1);
5609 if (SYMBOL_REF_TLS_MODEL (XVECEXP (x
, 0, 0)) == TLS_MODEL_LOCAL_EXEC
5610 || (!flag_pic
&& !base
))
5616 suffix
= "@invalid";
5617 output_operand_lossage ("invalid UNSPEC as operand: %d", XINT (x
,1));
5621 fputs ("pcl,", file
);
5622 arc_output_pic_addr_const (file
, XVECEXP (x
, 0, 0), code
);
5623 fputs (suffix
, file
);
5625 arc_output_pic_addr_const (file
, base
, code
);
5629 output_operand_lossage ("invalid expression as operand");
5633 #define SYMBOLIC_CONST(X) \
5634 (GET_CODE (X) == SYMBOL_REF \
5635 || GET_CODE (X) == LABEL_REF \
5636 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
5638 /* Emit insns to move operands[1] into operands[0]. */
5641 prepare_pic_move (rtx
*operands
, machine_mode
)
5643 if (GET_CODE (operands
[0]) == MEM
&& SYMBOLIC_CONST (operands
[1])
5645 operands
[1] = force_reg (Pmode
, operands
[1]);
5648 rtx temp
= (reload_in_progress
? operands
[0]
5649 : flag_pic
? gen_reg_rtx (Pmode
) : NULL_RTX
);
5650 operands
[1] = arc_legitimize_pic_address (operands
[1], temp
);
5655 /* The function returning the number of words, at the beginning of an
5656 argument, must be put in registers. The returned value must be
5657 zero for arguments that are passed entirely in registers or that
5658 are entirely pushed on the stack.
5660 On some machines, certain arguments must be passed partially in
5661 registers and partially in memory. On these machines, typically
5662 the first N words of arguments are passed in registers, and the
5663 rest on the stack. If a multi-word argument (a `double' or a
5664 structure) crosses that boundary, its first few words must be
5665 passed in registers and the rest must be pushed. This function
5666 tells the compiler when this occurs, and how many of the words
5667 should go in registers.
5669 `FUNCTION_ARG' for these arguments should return the first register
5670 to be used by the caller for this argument; likewise
5671 `FUNCTION_INCOMING_ARG', for the called function.
5673 The function is used to implement macro FUNCTION_ARG_PARTIAL_NREGS. */
5675 /* If REGNO is the least arg reg available then what is the total number of arg
5677 #define GPR_REST_ARG_REGS(REGNO) \
5678 ((REGNO) <= MAX_ARC_PARM_REGS ? MAX_ARC_PARM_REGS - (REGNO) : 0 )
5680 /* Since arc parm regs are contiguous. */
5681 #define ARC_NEXT_ARG_REG(REGNO) ( (REGNO) + 1 )
5683 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5686 arc_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
5687 tree type
, bool named ATTRIBUTE_UNUSED
)
5689 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5690 int bytes
= (mode
== BLKmode
5691 ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
));
5692 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5696 arg_num
= ROUND_ADVANCE_CUM (arg_num
, mode
, type
);
5697 ret
= GPR_REST_ARG_REGS (arg_num
);
5699 /* ICEd at function.c:2361, and ret is copied to data->partial */
5700 ret
= (ret
>= words
? 0 : ret
* UNITS_PER_WORD
);
5705 /* This function is used to control a function argument is passed in a
5706 register, and which register.
5708 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes
5709 (in a way defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE)
5710 all of the previous arguments so far passed in registers; MODE, the
5711 machine mode of the argument; TYPE, the data type of the argument
5712 as a tree node or 0 if that is not known (which happens for C
5713 support library functions); and NAMED, which is 1 for an ordinary
5714 argument and 0 for nameless arguments that correspond to `...' in
5715 the called function's prototype.
5717 The returned value should either be a `reg' RTX for the hard
5718 register in which to pass the argument, or zero to pass the
5719 argument on the stack.
5721 For machines like the Vax and 68000, where normally all arguments
5722 are pushed, zero suffices as a definition.
5724 The usual way to make the ANSI library `stdarg.h' work on a machine
5725 where some arguments are usually passed in registers, is to cause
5726 nameless arguments to be passed on the stack instead. This is done
5727 by making the function return 0 whenever NAMED is 0.
5729 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the
5730 definition of this function to determine if this argument is of a
5731 type that must be passed in the stack. If `REG_PARM_STACK_SPACE'
5732 is not defined and the function returns non-zero for such an
5733 argument, the compiler will abort. If `REG_PARM_STACK_SPACE' is
5734 defined, the argument will be computed in the stack and then loaded
5737 The function is used to implement macro FUNCTION_ARG. */
5738 /* On the ARC the first MAX_ARC_PARM_REGS args are normally in registers
5739 and the rest are pushed. */
5742 arc_function_arg (cumulative_args_t cum_v
,
5744 const_tree type ATTRIBUTE_UNUSED
,
5745 bool named ATTRIBUTE_UNUSED
)
5747 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5750 const char *debstr ATTRIBUTE_UNUSED
;
5752 arg_num
= ROUND_ADVANCE_CUM (arg_num
, mode
, type
);
5753 /* Return a marker for use in the call instruction. */
5754 if (mode
== VOIDmode
)
5759 else if (GPR_REST_ARG_REGS (arg_num
) > 0)
5761 ret
= gen_rtx_REG (mode
, arg_num
);
5762 debstr
= reg_names
[arg_num
];
5772 /* The function to update the summarizer variable *CUM to advance past
5773 an argument in the argument list. The values MODE, TYPE and NAMED
5774 describe that argument. Once this is done, the variable *CUM is
5775 suitable for analyzing the *following* argument with
5776 `FUNCTION_ARG', etc.
5778 This function need not do anything if the argument in question was
5779 passed on the stack. The compiler knows how to track the amount of
5780 stack space used for arguments without any special help.
5782 The function is used to implement macro FUNCTION_ARG_ADVANCE. */
5783 /* For the ARC: the cum set here is passed on to function_arg where we
5784 look at its value and say which reg to use. Strategy: advance the
5785 regnumber here till we run out of arg regs, then set *cum to last
5786 reg. In function_arg, since *cum > last arg reg we would return 0
5787 and thus the arg will end up on the stack. For straddling args of
5788 course function_arg_partial_nregs will come into play. */
5791 arc_function_arg_advance (cumulative_args_t cum_v
,
5794 bool named ATTRIBUTE_UNUSED
)
5796 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5797 int bytes
= (mode
== BLKmode
5798 ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
));
5799 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5803 *cum
= ROUND_ADVANCE_CUM (*cum
, mode
, type
);
5804 for (i
= 0; i
< words
; i
++)
5805 *cum
= ARC_NEXT_ARG_REG (*cum
);
5809 /* Define how to find the value returned by a function.
5810 VALTYPE is the data type of the value (as a tree).
5811 If the precise function being called is known, FN_DECL_OR_TYPE is its
5812 FUNCTION_DECL; otherwise, FN_DECL_OR_TYPE is its type. */
5815 arc_function_value (const_tree valtype
,
5816 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
5817 bool outgoing ATTRIBUTE_UNUSED
)
5819 machine_mode mode
= TYPE_MODE (valtype
);
5820 int unsignedp ATTRIBUTE_UNUSED
;
5822 unsignedp
= TYPE_UNSIGNED (valtype
);
5823 if (INTEGRAL_TYPE_P (valtype
) || TREE_CODE (valtype
) == OFFSET_TYPE
)
5824 PROMOTE_MODE (mode
, unsignedp
, valtype
);
5825 return gen_rtx_REG (mode
, 0);
5828 /* Returns the return address that is used by builtin_return_address. */
5831 arc_return_addr_rtx (int count
, ATTRIBUTE_UNUSED rtx frame
)
5836 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
5839 /* Determine if a given RTX is a valid constant. We already know this
5840 satisfies CONSTANT_P. */
5843 arc_legitimate_constant_p (machine_mode mode
, rtx x
)
5845 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
5848 if (!flag_pic
&& mode
!= Pmode
)
5851 switch (GET_CODE (x
))
5856 if (arc_legitimate_pic_addr_p (x
))
5859 return arc_legitimate_constant_p (mode
, XEXP (x
, 0));
5862 if (SYMBOL_REF_TLS_MODEL (x
))
5874 return arc_legitimate_constant_p (mode
, XEXP (x
, 0));
5879 bool t1
= arc_legitimate_constant_p (mode
, XEXP (x
, 0));
5880 bool t2
= arc_legitimate_constant_p (mode
, XEXP (x
, 1));
5889 return TARGET_PLUS_DMPY
;
5892 return TARGET_PLUS_QMACW
;
5898 switch (XINT (x
, 1))
5901 case UNSPEC_TLS_OFF
:
5905 /* Any other unspec ending here are pic related, hence the above
5906 constant pic address checking returned false. */
5912 fatal_insn ("unrecognized supposed constant", x
);
5919 arc_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
5921 if (RTX_OK_FOR_BASE_P (x
, strict
))
5923 if (legitimate_offset_address_p (mode
, x
, TARGET_INDEXED_LOADS
, strict
))
5925 if (legitimate_scaled_address_p (mode
, x
, strict
))
5927 if (LEGITIMATE_SMALL_DATA_ADDRESS_P (x
))
5929 if (GET_CODE (x
) == CONST_INT
&& LARGE_INT (INTVAL (x
)))
5932 /* When we compile for size avoid const (@sym + offset)
5934 if (!flag_pic
&& optimize_size
&& !reload_completed
5935 && (GET_CODE (x
) == CONST
)
5936 && (GET_CODE (XEXP (x
, 0)) == PLUS
)
5937 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)
5938 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) == 0
5939 && !SYMBOL_REF_FUNCTION_P (XEXP (XEXP (x
, 0), 0)))
5941 rtx addend
= XEXP (XEXP (x
, 0), 1);
5942 gcc_assert (CONST_INT_P (addend
));
5943 HOST_WIDE_INT offset
= INTVAL (addend
);
5945 /* Allow addresses having a large offset to pass. Anyhow they
5946 will end in a limm. */
5947 return !(offset
> -1024 && offset
< 1020);
5950 if ((GET_MODE_SIZE (mode
) != 16) && CONSTANT_P (x
))
5952 return arc_legitimate_constant_p (mode
, x
);
5954 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == PRE_INC
5955 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == POST_INC
)
5956 && RTX_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
5958 /* We're restricted here by the `st' insn. */
5959 if ((GET_CODE (x
) == PRE_MODIFY
|| GET_CODE (x
) == POST_MODIFY
)
5960 && GET_CODE (XEXP ((x
), 1)) == PLUS
5961 && rtx_equal_p (XEXP ((x
), 0), XEXP (XEXP (x
, 1), 0))
5962 && legitimate_offset_address_p (QImode
, XEXP (x
, 1),
5963 TARGET_AUTO_MODIFY_REG
, strict
))
5968 /* Return true iff ADDR (a legitimate address expression)
5969 has an effect that depends on the machine mode it is used for. */
5972 arc_mode_dependent_address_p (const_rtx addr
, addr_space_t
)
5974 /* SYMBOL_REF is not mode dependent: it is either a small data reference,
5975 which is valid for loads and stores, or a limm offset, which is valid for
5976 loads. Scaled indices are scaled by the access mode. */
5977 if (GET_CODE (addr
) == PLUS
5978 && GET_CODE (XEXP ((addr
), 0)) == MULT
)
5983 /* Determine if it's legal to put X into the constant pool. */
5986 arc_cannot_force_const_mem (machine_mode mode
, rtx x
)
5988 return !arc_legitimate_constant_p (mode
, x
);
5991 /* IDs for all the ARC builtins. */
5995 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \
5996 ARC_BUILTIN_ ## NAME,
5997 #include "builtins.def"
6003 struct GTY(()) arc_builtin_description
6005 enum insn_code icode
;
6010 static GTY(()) struct arc_builtin_description
6011 arc_bdesc
[ARC_BUILTIN_COUNT
] =
6013 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \
6014 { (enum insn_code) CODE_FOR_ ## ICODE, N_ARGS, NULL_TREE },
6015 #include "builtins.def"
6019 /* Transform UP into lowercase and write the result to LO.
6020 You must provide enough space for LO. Return LO. */
6023 arc_tolower (char *lo
, const char *up
)
6027 for (; *up
; up
++, lo
++)
6028 *lo
= TOLOWER (*up
);
6035 /* Implement `TARGET_BUILTIN_DECL'. */
6038 arc_builtin_decl (unsigned id
, bool initialize_p ATTRIBUTE_UNUSED
)
6040 if (id
< ARC_BUILTIN_COUNT
)
6041 return arc_bdesc
[id
].fndecl
;
6043 return error_mark_node
;
6047 arc_init_builtins (void)
6049 tree V4HI_type_node
;
6050 tree V2SI_type_node
;
6051 tree V2HI_type_node
;
6053 /* Vector types based on HS SIMD elements. */
6054 V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
6055 V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
6056 V2HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V2HImode
);
6058 tree pcvoid_type_node
6059 = build_pointer_type (build_qualified_type (void_type_node
,
6061 tree V8HI_type_node
= build_vector_type_for_mode (intHI_type_node
,
6064 tree void_ftype_void
6065 = build_function_type_list (void_type_node
, NULL_TREE
);
6067 = build_function_type_list (integer_type_node
, integer_type_node
,
6069 tree int_ftype_pcvoid_int
6070 = build_function_type_list (integer_type_node
, pcvoid_type_node
,
6071 integer_type_node
, NULL_TREE
);
6072 tree void_ftype_usint_usint
6073 = build_function_type_list (void_type_node
, long_unsigned_type_node
,
6074 long_unsigned_type_node
, NULL_TREE
);
6075 tree int_ftype_int_int
6076 = build_function_type_list (integer_type_node
, integer_type_node
,
6077 integer_type_node
, NULL_TREE
);
6078 tree usint_ftype_usint
6079 = build_function_type_list (long_unsigned_type_node
,
6080 long_unsigned_type_node
, NULL_TREE
);
6081 tree void_ftype_usint
6082 = build_function_type_list (void_type_node
, long_unsigned_type_node
,
6085 = build_function_type_list (integer_type_node
, void_type_node
,
6088 = build_function_type_list (void_type_node
, integer_type_node
,
6090 tree int_ftype_short
6091 = build_function_type_list (integer_type_node
, short_integer_type_node
,
6094 /* Old ARC SIMD types. */
6095 tree v8hi_ftype_v8hi_v8hi
6096 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6097 V8HI_type_node
, NULL_TREE
);
6098 tree v8hi_ftype_v8hi_int
6099 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6100 integer_type_node
, NULL_TREE
);
6101 tree v8hi_ftype_v8hi_int_int
6102 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6103 integer_type_node
, integer_type_node
,
6105 tree void_ftype_v8hi_int_int
6106 = build_function_type_list (void_type_node
, V8HI_type_node
,
6107 integer_type_node
, integer_type_node
,
6109 tree void_ftype_v8hi_int_int_int
6110 = build_function_type_list (void_type_node
, V8HI_type_node
,
6111 integer_type_node
, integer_type_node
,
6112 integer_type_node
, NULL_TREE
);
6113 tree v8hi_ftype_int_int
6114 = build_function_type_list (V8HI_type_node
, integer_type_node
,
6115 integer_type_node
, NULL_TREE
);
6116 tree void_ftype_int_int
6117 = build_function_type_list (void_type_node
, integer_type_node
,
6118 integer_type_node
, NULL_TREE
);
6119 tree v8hi_ftype_v8hi
6120 = build_function_type_list (V8HI_type_node
, V8HI_type_node
,
6122 /* ARCv2 SIMD types. */
6123 tree long_ftype_v4hi_v4hi
6124 = build_function_type_list (long_long_integer_type_node
,
6125 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
6126 tree int_ftype_v2hi_v2hi
6127 = build_function_type_list (integer_type_node
,
6128 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
6129 tree v2si_ftype_v2hi_v2hi
6130 = build_function_type_list (V2SI_type_node
,
6131 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
6132 tree v2hi_ftype_v2hi_v2hi
6133 = build_function_type_list (V2HI_type_node
,
6134 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
6135 tree v2si_ftype_v2si_v2si
6136 = build_function_type_list (V2SI_type_node
,
6137 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
6138 tree v4hi_ftype_v4hi_v4hi
6139 = build_function_type_list (V4HI_type_node
,
6140 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
6141 tree long_ftype_v2si_v2hi
6142 = build_function_type_list (long_long_integer_type_node
,
6143 V2SI_type_node
, V2HI_type_node
, NULL_TREE
);
6145 /* Add the builtins. */
6146 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \
6148 int id = ARC_BUILTIN_ ## NAME; \
6149 const char *Name = "__builtin_arc_" #NAME; \
6150 char *name = (char*) alloca (1 + strlen (Name)); \
6152 gcc_assert (id < ARC_BUILTIN_COUNT); \
6154 arc_bdesc[id].fndecl \
6155 = add_builtin_function (arc_tolower(name, Name), TYPE, id, \
6156 BUILT_IN_MD, NULL, NULL_TREE); \
6158 #include "builtins.def"
6162 /* Helper to expand __builtin_arc_aligned (void* val, int
6166 arc_expand_builtin_aligned (tree exp
)
6168 tree arg0
= CALL_EXPR_ARG (exp
, 0);
6169 tree arg1
= CALL_EXPR_ARG (exp
, 1);
6171 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6172 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6174 if (!CONST_INT_P (op1
))
6176 /* If we can't fold the alignment to a constant integer
6177 whilst optimizing, this is probably a user error. */
6179 warning (0, "__builtin_arc_aligned with non-constant alignment");
6183 HOST_WIDE_INT alignTest
= INTVAL (op1
);
6184 /* Check alignTest is positive, and a power of two. */
6185 if (alignTest
<= 0 || alignTest
!= (alignTest
& -alignTest
))
6187 error ("invalid alignment value for __builtin_arc_aligned");
6191 if (CONST_INT_P (op0
))
6193 HOST_WIDE_INT pnt
= INTVAL (op0
);
6195 if ((pnt
& (alignTest
- 1)) == 0)
6200 unsigned align
= get_pointer_alignment (arg0
);
6201 unsigned numBits
= alignTest
* BITS_PER_UNIT
;
6203 if (align
&& align
>= numBits
)
6205 /* Another attempt to ascertain alignment. Check the type
6206 we are pointing to. */
6207 if (POINTER_TYPE_P (TREE_TYPE (arg0
))
6208 && TYPE_ALIGN (TREE_TYPE (TREE_TYPE (arg0
))) >= numBits
)
6213 /* Default to false. */
6217 /* Helper arc_expand_builtin, generates a pattern for the given icode
6221 apply_GEN_FCN (enum insn_code icode
, rtx
*arg
)
6223 switch (insn_data
[icode
].n_generator_args
)
6226 return GEN_FCN (icode
) ();
6228 return GEN_FCN (icode
) (arg
[0]);
6230 return GEN_FCN (icode
) (arg
[0], arg
[1]);
6232 return GEN_FCN (icode
) (arg
[0], arg
[1], arg
[2]);
6234 return GEN_FCN (icode
) (arg
[0], arg
[1], arg
[2], arg
[3]);
6236 return GEN_FCN (icode
) (arg
[0], arg
[1], arg
[2], arg
[3], arg
[4]);
6242 /* Expand an expression EXP that calls a built-in function,
6243 with result going to TARGET if that's convenient
6244 (and in mode MODE if that's convenient).
6245 SUBTARGET may be used as the target for computing one of EXP's operands.
6246 IGNORE is nonzero if the value is to be ignored. */
6249 arc_expand_builtin (tree exp
,
6251 rtx subtarget ATTRIBUTE_UNUSED
,
6252 machine_mode mode ATTRIBUTE_UNUSED
,
6253 int ignore ATTRIBUTE_UNUSED
)
6255 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
6256 unsigned int id
= DECL_FUNCTION_CODE (fndecl
);
6257 const struct arc_builtin_description
*d
= &arc_bdesc
[id
];
6258 int i
, j
, n_args
= call_expr_nargs (exp
);
6261 enum insn_code icode
= d
->icode
;
6262 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6279 if (id
>= ARC_BUILTIN_COUNT
)
6280 internal_error ("bad builtin fcode");
6282 /* 1st part: Expand special builtins. */
6285 case ARC_BUILTIN_NOP
:
6286 emit_insn (gen_nopv ());
6289 case ARC_BUILTIN_RTIE
:
6290 case ARC_BUILTIN_SYNC
:
6291 case ARC_BUILTIN_BRK
:
6292 case ARC_BUILTIN_SWI
:
6293 case ARC_BUILTIN_UNIMP_S
:
6294 gcc_assert (icode
!= 0);
6295 emit_insn (GEN_FCN (icode
) (const1_rtx
));
6298 case ARC_BUILTIN_ALIGNED
:
6299 return arc_expand_builtin_aligned (exp
);
6301 case ARC_BUILTIN_CLRI
:
6302 target
= gen_reg_rtx (SImode
);
6303 emit_insn (gen_clri (target
, const1_rtx
));
6306 case ARC_BUILTIN_TRAP_S
:
6307 case ARC_BUILTIN_SLEEP
:
6308 arg0
= CALL_EXPR_ARG (exp
, 0);
6310 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6312 if (!CONST_INT_P (op0
) || !satisfies_constraint_L (op0
))
6314 error ("builtin operand should be an unsigned 6-bit value");
6317 gcc_assert (icode
!= 0);
6318 emit_insn (GEN_FCN (icode
) (op0
));
6321 case ARC_BUILTIN_VDORUN
:
6322 case ARC_BUILTIN_VDIRUN
:
6323 arg0
= CALL_EXPR_ARG (exp
, 0);
6324 arg1
= CALL_EXPR_ARG (exp
, 1);
6325 op0
= expand_expr (arg0
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6326 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6328 target
= gen_rtx_REG (SImode
, (id
== ARC_BUILTIN_VDIRUN
) ? 131 : 139);
6330 mode0
= insn_data
[icode
].operand
[1].mode
;
6331 mode1
= insn_data
[icode
].operand
[2].mode
;
6333 if (!insn_data
[icode
].operand
[1].predicate (op0
, mode0
))
6334 op0
= copy_to_mode_reg (mode0
, op0
);
6336 if (!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
6337 op1
= copy_to_mode_reg (mode1
, op1
);
6339 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
6346 case ARC_BUILTIN_VDIWR
:
6347 case ARC_BUILTIN_VDOWR
:
6348 arg0
= CALL_EXPR_ARG (exp
, 0);
6349 arg1
= CALL_EXPR_ARG (exp
, 1);
6350 op0
= expand_expr (arg0
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6351 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6353 if (!CONST_INT_P (op0
)
6354 || !(UNSIGNED_INT3 (INTVAL (op0
))))
6355 error ("operand 1 should be an unsigned 3-bit immediate");
6357 mode1
= insn_data
[icode
].operand
[1].mode
;
6359 if (icode
== CODE_FOR_vdiwr_insn
)
6360 target
= gen_rtx_REG (SImode
,
6361 ARC_FIRST_SIMD_DMA_CONFIG_IN_REG
+ INTVAL (op0
));
6362 else if (icode
== CODE_FOR_vdowr_insn
)
6363 target
= gen_rtx_REG (SImode
,
6364 ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG
+ INTVAL (op0
));
6368 if (!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
6369 op1
= copy_to_mode_reg (mode1
, op1
);
6371 pat
= GEN_FCN (icode
) (target
, op1
);
6378 case ARC_BUILTIN_VASRW
:
6379 case ARC_BUILTIN_VSR8
:
6380 case ARC_BUILTIN_VSR8AW
:
6381 arg0
= CALL_EXPR_ARG (exp
, 0);
6382 arg1
= CALL_EXPR_ARG (exp
, 1);
6383 op0
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
6384 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6385 op2
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
6387 target
= gen_reg_rtx (V8HImode
);
6388 mode0
= insn_data
[icode
].operand
[1].mode
;
6389 mode1
= insn_data
[icode
].operand
[2].mode
;
6391 if (!insn_data
[icode
].operand
[1].predicate (op0
, mode0
))
6392 op0
= copy_to_mode_reg (mode0
, op0
);
6394 if ((!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
6395 || !(UNSIGNED_INT3 (INTVAL (op1
))))
6396 error ("operand 2 should be an unsigned 3-bit value (I0-I7)");
6398 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
6405 case ARC_BUILTIN_VLD32WH
:
6406 case ARC_BUILTIN_VLD32WL
:
6407 case ARC_BUILTIN_VLD64
:
6408 case ARC_BUILTIN_VLD32
:
6411 arg0
= CALL_EXPR_ARG (exp
, 0); /* source vreg. */
6412 arg1
= CALL_EXPR_ARG (exp
, 1); /* [I]0-7. */
6413 arg2
= CALL_EXPR_ARG (exp
, 2); /* u8. */
6415 src_vreg
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
6416 op0
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6417 op1
= expand_expr (arg2
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6418 op2
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
6420 /* target <- src vreg. */
6421 emit_insn (gen_move_insn (target
, src_vreg
));
6423 /* target <- vec_concat: target, mem (Ib, u8). */
6424 mode0
= insn_data
[icode
].operand
[3].mode
;
6425 mode1
= insn_data
[icode
].operand
[1].mode
;
6427 if ((!insn_data
[icode
].operand
[3].predicate (op0
, mode0
))
6428 || !(UNSIGNED_INT3 (INTVAL (op0
))))
6429 error ("operand 1 should be an unsigned 3-bit value (I0-I7)");
6431 if ((!insn_data
[icode
].operand
[1].predicate (op1
, mode1
))
6432 || !(UNSIGNED_INT8 (INTVAL (op1
))))
6433 error ("operand 2 should be an unsigned 8-bit value");
6435 pat
= GEN_FCN (icode
) (target
, op1
, op2
, op0
);
6442 case ARC_BUILTIN_VLD64W
:
6443 case ARC_BUILTIN_VLD128
:
6444 arg0
= CALL_EXPR_ARG (exp
, 0); /* dest vreg. */
6445 arg1
= CALL_EXPR_ARG (exp
, 1); /* [I]0-7. */
6447 op0
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
6448 op1
= expand_expr (arg0
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6449 op2
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6451 /* target <- src vreg. */
6452 target
= gen_reg_rtx (V8HImode
);
6454 /* target <- vec_concat: target, mem (Ib, u8). */
6455 mode0
= insn_data
[icode
].operand
[1].mode
;
6456 mode1
= insn_data
[icode
].operand
[2].mode
;
6457 mode2
= insn_data
[icode
].operand
[3].mode
;
6459 if ((!insn_data
[icode
].operand
[2].predicate (op1
, mode1
))
6460 || !(UNSIGNED_INT3 (INTVAL (op1
))))
6461 error ("operand 1 should be an unsigned 3-bit value (I0-I7)");
6463 if ((!insn_data
[icode
].operand
[3].predicate (op2
, mode2
))
6464 || !(UNSIGNED_INT8 (INTVAL (op2
))))
6465 error ("operand 2 should be an unsigned 8-bit value");
6467 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
6475 case ARC_BUILTIN_VST128
:
6476 case ARC_BUILTIN_VST64
:
6477 arg0
= CALL_EXPR_ARG (exp
, 0); /* src vreg. */
6478 arg1
= CALL_EXPR_ARG (exp
, 1); /* [I]0-7. */
6479 arg2
= CALL_EXPR_ARG (exp
, 2); /* u8. */
6481 op0
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
6482 op1
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6483 op2
= expand_expr (arg2
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6484 op3
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
6486 mode0
= insn_data
[icode
].operand
[0].mode
;
6487 mode1
= insn_data
[icode
].operand
[1].mode
;
6488 mode2
= insn_data
[icode
].operand
[2].mode
;
6489 mode3
= insn_data
[icode
].operand
[3].mode
;
6491 if ((!insn_data
[icode
].operand
[1].predicate (op1
, mode1
))
6492 || !(UNSIGNED_INT3 (INTVAL (op1
))))
6493 error ("operand 2 should be an unsigned 3-bit value (I0-I7)");
6495 if ((!insn_data
[icode
].operand
[2].predicate (op2
, mode2
))
6496 || !(UNSIGNED_INT8 (INTVAL (op2
))))
6497 error ("operand 3 should be an unsigned 8-bit value");
6499 if (!insn_data
[icode
].operand
[3].predicate (op3
, mode3
))
6500 op3
= copy_to_mode_reg (mode3
, op3
);
6502 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
6509 case ARC_BUILTIN_VST16_N
:
6510 case ARC_BUILTIN_VST32_N
:
6511 arg0
= CALL_EXPR_ARG (exp
, 0); /* source vreg. */
6512 arg1
= CALL_EXPR_ARG (exp
, 1); /* u3. */
6513 arg2
= CALL_EXPR_ARG (exp
, 2); /* [I]0-7. */
6514 arg3
= CALL_EXPR_ARG (exp
, 3); /* u8. */
6516 op0
= expand_expr (arg3
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6517 op1
= gen_rtx_REG (V8HImode
, ARC_FIRST_SIMD_VR_REG
);
6518 op2
= expand_expr (arg2
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6519 op3
= expand_expr (arg0
, NULL_RTX
, V8HImode
, EXPAND_NORMAL
);
6520 op4
= expand_expr (arg1
, NULL_RTX
, SImode
, EXPAND_NORMAL
);
6522 mode0
= insn_data
[icode
].operand
[0].mode
;
6523 mode2
= insn_data
[icode
].operand
[2].mode
;
6524 mode3
= insn_data
[icode
].operand
[3].mode
;
6525 mode4
= insn_data
[icode
].operand
[4].mode
;
6527 /* Do some correctness checks for the operands. */
6528 if ((!insn_data
[icode
].operand
[0].predicate (op0
, mode0
))
6529 || !(UNSIGNED_INT8 (INTVAL (op0
))))
6530 error ("operand 4 should be an unsigned 8-bit value (0-255)");
6532 if ((!insn_data
[icode
].operand
[2].predicate (op2
, mode2
))
6533 || !(UNSIGNED_INT3 (INTVAL (op2
))))
6534 error ("operand 3 should be an unsigned 3-bit value (I0-I7)");
6536 if (!insn_data
[icode
].operand
[3].predicate (op3
, mode3
))
6537 op3
= copy_to_mode_reg (mode3
, op3
);
6539 if ((!insn_data
[icode
].operand
[4].predicate (op4
, mode4
))
6540 || !(UNSIGNED_INT3 (INTVAL (op4
))))
6541 error ("operand 2 should be an unsigned 3-bit value (subreg 0-7)");
6542 else if (icode
== CODE_FOR_vst32_n_insn
6543 && ((INTVAL (op4
) % 2) != 0))
6544 error ("operand 2 should be an even 3-bit value (subreg 0,2,4,6)");
6546 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
, op4
);
6557 /* 2nd part: Expand regular builtins. */
6559 internal_error ("bad builtin fcode");
6561 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6566 if (target
== NULL_RTX
6567 || GET_MODE (target
) != tmode
6568 || !insn_data
[icode
].operand
[0].predicate (target
, tmode
))
6570 target
= gen_reg_rtx (tmode
);
6575 gcc_assert (n_args
<= 4);
6576 for (i
= 0; i
< n_args
; i
++, j
++)
6578 tree arg
= CALL_EXPR_ARG (exp
, i
);
6579 machine_mode mode
= insn_data
[icode
].operand
[j
].mode
;
6580 rtx op
= expand_expr (arg
, NULL_RTX
, mode
, EXPAND_NORMAL
);
6581 machine_mode opmode
= GET_MODE (op
);
6582 char c
= insn_data
[icode
].operand
[j
].constraint
[0];
6584 /* SIMD extension requires exact immediate operand match. */
6585 if ((id
> ARC_BUILTIN_SIMD_BEGIN
)
6586 && (id
< ARC_BUILTIN_SIMD_END
)
6590 if (!CONST_INT_P (op
))
6591 error ("builtin requires an immediate for operand %d", j
);
6595 if (!satisfies_constraint_L (op
))
6596 error ("operand %d should be a 6 bit unsigned immediate", j
);
6599 if (!satisfies_constraint_P (op
))
6600 error ("operand %d should be a 8 bit unsigned immediate", j
);
6603 if (!satisfies_constraint_K (op
))
6604 error ("operand %d should be a 3 bit unsigned immediate", j
);
6607 error ("unknown builtin immediate operand type for operand %d",
6612 if (CONST_INT_P (op
))
6615 if ((opmode
== SImode
) && (mode
== HImode
))
6618 op
= gen_lowpart (HImode
, op
);
6621 /* In case the insn wants input operands in modes different from
6622 the result, abort. */
6623 gcc_assert (opmode
== mode
|| opmode
== VOIDmode
);
6625 if (!insn_data
[icode
].operand
[i
+ nonvoid
].predicate (op
, mode
))
6626 op
= copy_to_mode_reg (mode
, op
);
6631 pat
= apply_GEN_FCN (icode
, xop
);
6632 if (pat
== NULL_RTX
)
6643 /* Returns true if the operands[opno] is a valid compile-time constant to be
6644 used as register number in the code for builtins. Else it flags an error
6645 and returns false. */
6648 check_if_valid_regno_const (rtx
*operands
, int opno
)
6651 switch (GET_CODE (operands
[opno
]))
6658 error ("register number must be a compile-time constant. Try giving higher optimization levels");
6664 /* Check that after all the constant folding, whether the operand to
6665 __builtin_arc_sleep is an unsigned int of 6 bits. If not, flag an error. */
6668 check_if_valid_sleep_operand (rtx
*operands
, int opno
)
6670 switch (GET_CODE (operands
[opno
]))
6674 if( UNSIGNED_INT6 (INTVAL (operands
[opno
])))
6678 fatal_error (input_location
,
6679 "operand for sleep instruction must be an unsigned 6 bit compile-time constant");
6685 /* Return true if it is ok to make a tail-call to DECL. */
6688 arc_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
6689 tree exp ATTRIBUTE_UNUSED
)
6691 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
6692 if (ARC_INTERRUPT_P (arc_compute_function_type (cfun
)))
6695 /* Everything else is ok. */
6699 /* Output code to add DELTA to the first argument, and then jump
6700 to FUNCTION. Used for C++ multiple inheritance. */
6703 arc_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
6704 HOST_WIDE_INT delta
,
6705 HOST_WIDE_INT vcall_offset
,
6708 int mi_delta
= delta
;
6709 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
6712 = aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
) ? 1 : 0;
6716 mi_delta
= - mi_delta
;
6718 /* Add DELTA. When possible use a plain add, otherwise load it into
6719 a register first. */
6721 while (mi_delta
!= 0)
6723 if ((mi_delta
& (3 << shift
)) == 0)
6727 asm_fprintf (file
, "\t%s\t%s, %s, %d\n",
6728 mi_op
, reg_names
[this_regno
], reg_names
[this_regno
],
6729 mi_delta
& (0xff << shift
));
6730 mi_delta
&= ~(0xff << shift
);
6735 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
6736 if (vcall_offset
!= 0)
6738 /* ld r12,[this] --> temp = *this
6739 add r12,r12,vcall_offset --> temp = *(*this + vcall_offset)
6741 add this,this,r12 --> this+ = *(*this + vcall_offset) */
6742 asm_fprintf (file
, "\tld\t%s, [%s]\n",
6743 ARC_TEMP_SCRATCH_REG
, reg_names
[this_regno
]);
6744 asm_fprintf (file
, "\tadd\t%s, %s, " HOST_WIDE_INT_PRINT_DEC
"\n",
6745 ARC_TEMP_SCRATCH_REG
, ARC_TEMP_SCRATCH_REG
, vcall_offset
);
6746 asm_fprintf (file
, "\tld\t%s, [%s]\n",
6747 ARC_TEMP_SCRATCH_REG
, ARC_TEMP_SCRATCH_REG
);
6748 asm_fprintf (file
, "\tadd\t%s, %s, %s\n", reg_names
[this_regno
],
6749 reg_names
[this_regno
], ARC_TEMP_SCRATCH_REG
);
6752 fnaddr
= XEXP (DECL_RTL (function
), 0);
6754 if (arc_is_longcall_p (fnaddr
))
6758 asm_fprintf (file
, "\tld\t%s, [pcl, @",
6759 ARC_TEMP_SCRATCH_REG
);
6760 assemble_name (file
, XSTR (fnaddr
, 0));
6761 fputs ("@gotpc]\n", file
);
6762 asm_fprintf (file
, "\tj\t[%s]", ARC_TEMP_SCRATCH_REG
);
6766 fputs ("\tj\t@", file
);
6767 assemble_name (file
, XSTR (fnaddr
, 0));
6772 fputs ("\tb\t@", file
);
6773 assemble_name (file
, XSTR (fnaddr
, 0));
6775 fputs ("@plt\n", file
);
6780 /* Return true if a 32 bit "long_call" should be generated for
6781 this calling SYM_REF. We generate a long_call if the function:
6783 a. has an __attribute__((long call))
6784 or b. the -mlong-calls command line switch has been specified
6786 However we do not generate a long call if the function has an
6787 __attribute__ ((short_call)) or __attribute__ ((medium_call))
6789 This function will be called by C fragments contained in the machine
6790 description file. */
6793 arc_is_longcall_p (rtx sym_ref
)
6795 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
6798 return (SYMBOL_REF_LONG_CALL_P (sym_ref
)
6799 || (TARGET_LONG_CALLS_SET
6800 && !SYMBOL_REF_SHORT_CALL_P (sym_ref
)
6801 && !SYMBOL_REF_MEDIUM_CALL_P (sym_ref
)));
6805 /* Likewise for short calls. */
6808 arc_is_shortcall_p (rtx sym_ref
)
6810 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
6813 return (SYMBOL_REF_SHORT_CALL_P (sym_ref
)
6814 || (!TARGET_LONG_CALLS_SET
&& !TARGET_MEDIUM_CALLS
6815 && !SYMBOL_REF_LONG_CALL_P (sym_ref
)
6816 && !SYMBOL_REF_MEDIUM_CALL_P (sym_ref
)));
6820 /* Worker function for TARGET_RETURN_IN_MEMORY. */
6823 arc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
6825 if (AGGREGATE_TYPE_P (type
) || TREE_ADDRESSABLE (type
))
6829 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6830 return (size
== -1 || size
> (TARGET_V2
? 16 : 8));
6835 /* This was in rtlanal.c, and can go in there when we decide we want
6836 to submit the change for inclusion in the GCC tree. */
6837 /* Like note_stores, but allow the callback to have side effects on the rtl
6838 (like the note_stores of yore):
6839 Call FUN on each register or MEM that is stored into or clobbered by X.
6840 (X would be the pattern of an insn). DATA is an arbitrary pointer,
6841 ignored by note_stores, but passed to FUN.
6842 FUN may alter parts of the RTL.
6844 FUN receives three arguments:
6845 1. the REG, MEM, CC0 or PC being stored in or clobbered,
6846 2. the SET or CLOBBER rtx that does the store,
6847 3. the pointer DATA provided to note_stores.
6849 If the item being stored in or clobbered is a SUBREG of a hard register,
6850 the SUBREG will be passed. */
6852 /* For now. */ static
6854 walk_stores (rtx x
, void (*fun
) (rtx
, rtx
, void *), void *data
)
6858 if (GET_CODE (x
) == COND_EXEC
)
6859 x
= COND_EXEC_CODE (x
);
6861 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
6863 rtx dest
= SET_DEST (x
);
6865 while ((GET_CODE (dest
) == SUBREG
6866 && (!REG_P (SUBREG_REG (dest
))
6867 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
6868 || GET_CODE (dest
) == ZERO_EXTRACT
6869 || GET_CODE (dest
) == STRICT_LOW_PART
)
6870 dest
= XEXP (dest
, 0);
6872 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
6873 each of whose first operand is a register. */
6874 if (GET_CODE (dest
) == PARALLEL
)
6876 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
6877 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
6878 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
6881 (*fun
) (dest
, x
, data
);
6884 else if (GET_CODE (x
) == PARALLEL
)
6885 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
6886 walk_stores (XVECEXP (x
, 0, i
), fun
, data
);
6890 arc_pass_by_reference (cumulative_args_t ca_v ATTRIBUTE_UNUSED
,
6891 machine_mode mode ATTRIBUTE_UNUSED
,
6893 bool named ATTRIBUTE_UNUSED
)
6896 && (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
6897 || TREE_ADDRESSABLE (type
)));
6900 /* Implement TARGET_CAN_USE_DOLOOP_P. */
6903 arc_can_use_doloop_p (const widest_int
&iterations
, const widest_int
&,
6904 unsigned int loop_depth
, bool entered_at_top
)
6908 /* Setting up the loop with two sr instructions costs 6 cycles. */
6911 && wi::gtu_p (iterations
, 0)
6912 && wi::leu_p (iterations
, flag_pic
? 6 : 3))
6917 /* NULL if INSN insn is valid within a low-overhead loop.
6918 Otherwise return why doloop cannot be applied. */
6921 arc_invalid_within_doloop (const rtx_insn
*insn
)
6924 return "Function call in the loop.";
6928 /* Return true if a load instruction (CONSUMER) uses the same address as a
6929 store instruction (PRODUCER). This function is used to avoid st/ld
6930 address hazard in ARC700 cores. */
6932 arc_store_addr_hazard_p (rtx_insn
* producer
, rtx_insn
* consumer
)
6934 rtx in_set
, out_set
;
6935 rtx out_addr
, in_addr
;
6943 /* Peel the producer and the consumer for the address. */
6944 out_set
= single_set (producer
);
6947 out_addr
= SET_DEST (out_set
);
6950 if (GET_CODE (out_addr
) == ZERO_EXTEND
6951 || GET_CODE (out_addr
) == SIGN_EXTEND
)
6952 out_addr
= XEXP (out_addr
, 0);
6954 if (!MEM_P (out_addr
))
6957 in_set
= single_set (consumer
);
6960 in_addr
= SET_SRC (in_set
);
6963 if (GET_CODE (in_addr
) == ZERO_EXTEND
6964 || GET_CODE (in_addr
) == SIGN_EXTEND
)
6965 in_addr
= XEXP (in_addr
, 0);
6967 if (!MEM_P (in_addr
))
6969 /* Get rid of the MEM and check if the addresses are
6971 in_addr
= XEXP (in_addr
, 0);
6972 out_addr
= XEXP (out_addr
, 0);
6974 return exp_equiv_p (in_addr
, out_addr
, 0, true);
6980 /* The same functionality as arc_hazard. It is called in machine
6981 reorg before any other optimization. Hence, the NOP size is taken
6982 into account when doing branch shortening. */
6985 workaround_arc_anomaly (void)
6987 rtx_insn
*insn
, *succ0
;
6989 /* For any architecture: call arc_hazard here. */
6990 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6992 succ0
= next_real_insn (insn
);
6993 if (arc_hazard (insn
, succ0
))
6995 emit_insn_before (gen_nopv (), succ0
);
7003 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7005 succ0
= next_real_insn (insn
);
7006 if (arc_store_addr_hazard_p (insn
, succ0
))
7008 emit_insn_after (gen_nopv (), insn
);
7009 emit_insn_after (gen_nopv (), insn
);
7013 /* Avoid adding nops if the instruction between the ST and LD is
7015 succ1
= next_real_insn (succ0
);
7016 if (succ0
&& !JUMP_P (succ0
) && !CALL_P (succ0
)
7017 && arc_store_addr_hazard_p (insn
, succ1
))
7018 emit_insn_after (gen_nopv (), insn
);
7023 static int arc_reorg_in_progress
= 0;
7025 /* ARC's machince specific reorg function. */
7036 workaround_arc_anomaly ();
7038 cfun
->machine
->arc_reorg_started
= 1;
7039 arc_reorg_in_progress
= 1;
7041 /* Link up loop ends with their loop start. */
7043 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7044 if (GET_CODE (insn
) == JUMP_INSN
7045 && recog_memoized (insn
) == CODE_FOR_doloop_end_i
)
7048 = as_a
<rtx_insn
*> (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn
), 0, 0)), 1), 0));
7049 rtx num
= GEN_INT (CODE_LABEL_NUMBER (top_label
));
7050 rtx_insn
*lp
, *prev
= prev_nonnote_insn (top_label
);
7051 rtx_insn
*lp_simple
= NULL
;
7052 rtx_insn
*next
= NULL
;
7053 rtx op0
= XEXP (XVECEXP (PATTERN (insn
), 0, 1), 0);
7057 (lp
&& NONJUMP_INSN_P (lp
)
7058 && recog_memoized (lp
) != CODE_FOR_doloop_begin_i
);
7059 lp
= prev_nonnote_insn (lp
))
7061 if (!lp
|| !NONJUMP_INSN_P (lp
)
7062 || dead_or_set_regno_p (lp
, LP_COUNT
))
7064 HOST_WIDE_INT loop_end_id
7065 = INTVAL (XEXP (XVECEXP (PATTERN (insn
), 0, 4), 0));
7067 for (prev
= next
= insn
, lp
= NULL
; prev
|| next
;)
7071 if (NONJUMP_INSN_P (prev
)
7072 && recog_memoized (prev
) == CODE_FOR_doloop_begin_i
7073 && (INTVAL (XEXP (XVECEXP (PATTERN (prev
), 0, 5), 0))
7079 else if (LABEL_P (prev
))
7081 prev
= prev_nonnote_insn (prev
);
7085 if (NONJUMP_INSN_P (next
)
7086 && recog_memoized (next
) == CODE_FOR_doloop_begin_i
7087 && (INTVAL (XEXP (XVECEXP (PATTERN (next
), 0, 5), 0))
7093 next
= next_nonnote_insn (next
);
7100 if (lp
&& !dead_or_set_regno_p (lp
, LP_COUNT
))
7102 rtx begin_cnt
= XEXP (XVECEXP (PATTERN (lp
), 0 ,3), 0);
7103 if (INTVAL (XEXP (XVECEXP (PATTERN (lp
), 0, 4), 0)))
7104 /* The loop end insn has been duplicated. That can happen
7105 when there is a conditional block at the very end of
7108 /* If Register allocation failed to allocate to the right
7109 register, There is no point into teaching reload to
7110 fix this up with reloads, as that would cost more
7111 than using an ordinary core register with the
7112 doloop_fallback pattern. */
7113 if ((true_regnum (op0
) != LP_COUNT
|| !REG_P (begin_cnt
))
7114 /* Likewise, if the loop setup is evidently inside the loop,
7116 || (!lp_simple
&& lp
!= next
&& !seen_label
))
7121 /* It is common that the optimizers copy the loop count from
7122 another register, and doloop_begin_i is stuck with the
7123 source of the move. Making doloop_begin_i only accept "l"
7124 is nonsentical, as this then makes reload evict the pseudo
7125 used for the loop end. The underlying cause is that the
7126 optimizers don't understand that the register allocation for
7127 doloop_begin_i should be treated as part of the loop.
7128 Try to work around this problem by verifying the previous
7130 if (true_regnum (begin_cnt
) != LP_COUNT
)
7135 for (mov
= prev_nonnote_insn (lp
); mov
;
7136 mov
= prev_nonnote_insn (mov
))
7138 if (!NONJUMP_INSN_P (mov
))
7140 else if ((set
= single_set (mov
))
7141 && rtx_equal_p (SET_SRC (set
), begin_cnt
)
7142 && rtx_equal_p (SET_DEST (set
), op0
))
7147 XEXP (XVECEXP (PATTERN (lp
), 0 ,3), 0) = op0
;
7148 note
= find_regno_note (lp
, REG_DEAD
, REGNO (begin_cnt
));
7150 remove_note (lp
, note
);
7158 XEXP (XVECEXP (PATTERN (insn
), 0, 4), 0) = num
;
7159 XEXP (XVECEXP (PATTERN (lp
), 0, 4), 0) = num
;
7161 XEXP (XVECEXP (PATTERN (lp
), 0, 6), 0) = const2_rtx
;
7162 else if (!lp_simple
)
7163 XEXP (XVECEXP (PATTERN (lp
), 0, 6), 0) = const1_rtx
;
7164 else if (prev
!= lp
)
7167 add_insn_after (lp
, prev
, NULL
);
7171 XEXP (XVECEXP (PATTERN (lp
), 0, 7), 0)
7172 = gen_rtx_LABEL_REF (Pmode
, top_label
);
7173 add_reg_note (lp
, REG_LABEL_OPERAND
, top_label
);
7174 LABEL_NUSES (top_label
)++;
7176 /* We can avoid tedious loop start / end setting for empty loops
7177 be merely setting the loop count to its final value. */
7178 if (next_active_insn (top_label
) == insn
)
7181 = gen_rtx_SET (XEXP (XVECEXP (PATTERN (lp
), 0, 3), 0),
7184 rtx_insn
*lc_set_insn
= emit_insn_before (lc_set
, insn
);
7189 /* If the loop is non-empty with zero length, we can't make it
7190 a zero-overhead loop. That can happen for empty asms. */
7195 for (scan
= top_label
;
7196 (scan
&& scan
!= insn
7197 && (!NONJUMP_INSN_P (scan
) || !get_attr_length (scan
)));
7198 scan
= NEXT_INSN (scan
));
7208 /* Sometimes the loop optimizer makes a complete hash of the
7209 loop. If it were only that the loop is not entered at the
7210 top, we could fix this up by setting LP_START with SR .
7211 However, if we can't find the loop begin were it should be,
7212 chances are that it does not even dominate the loop, but is
7213 inside the loop instead. Using SR there would kill
7215 We use the doloop_fallback pattern here, which executes
7216 in two cycles on the ARC700 when predicted correctly. */
7220 rtx op3
= XEXP (XVECEXP (PATTERN (insn
), 0, 5), 0);
7222 emit_insn_before (gen_move_insn (op3
, op0
), insn
);
7224 = gen_doloop_fallback_m (op3
, JUMP_LABEL (insn
), op0
);
7227 XVEC (PATTERN (insn
), 0)
7228 = gen_rtvec (2, XVECEXP (PATTERN (insn
), 0, 0),
7229 XVECEXP (PATTERN (insn
), 0, 1));
7230 INSN_CODE (insn
) = -1;
7235 /* FIXME: should anticipate ccfsm action, generate special patterns for
7236 to-be-deleted branches that have no delay slot and have at least the
7237 length of the size increase forced on other insns that are conditionalized.
7238 This can also have an insn_list inside that enumerates insns which are
7239 not actually conditionalized because the destinations are dead in the
7241 Could also tag branches that we want to be unaligned if they get no delay
7242 slot, or even ones that we don't want to do delay slot sheduling for
7243 because we can unalign them.
7245 However, there are cases when conditional execution is only possible after
7246 delay slot scheduling:
7248 - If a delay slot is filled with a nocond/set insn from above, the previous
7249 basic block can become elegible for conditional execution.
7250 - If a delay slot is filled with a nocond insn from the fall-through path,
7251 the branch with that delay slot can become eligble for conditional
7252 execution (however, with the same sort of data flow analysis that dbr
7253 does, we could have figured out before that we don't need to
7254 conditionalize this insn.)
7255 - If a delay slot insn is filled with an insn from the target, the
7256 target label gets its uses decremented (even deleted if falling to zero),
7257 thus possibly creating more condexec opportunities there.
7258 Therefore, we should still be prepared to apply condexec optimization on
7259 non-prepared branches if the size increase of conditionalized insns is no
7260 more than the size saved from eliminating the branch. An invocation option
7261 could also be used to reserve a bit of extra size for condbranches so that
7262 this'll work more often (could also test in arc_reorg if the block is
7263 'close enough' to be eligible for condexec to make this likely, and
7264 estimate required size increase). */
7265 /* Generate BRcc insns, by combining cmp and Bcc insns wherever possible. */
7266 if (TARGET_NO_BRCC_SET
)
7271 init_insn_lengths();
7274 if (optimize
> 1 && !TARGET_NO_COND_EXEC
)
7277 unsigned int flags
= pass_data_arc_ifcvt
.todo_flags_finish
;
7278 df_finish_pass ((flags
& TODO_df_verify
) != 0);
7282 fprintf (dump_file
, ";; After if conversion:\n\n");
7283 print_rtl (dump_file
, get_insns ());
7287 /* Call shorten_branches to calculate the insn lengths. */
7288 shorten_branches (get_insns());
7289 cfun
->machine
->ccfsm_current_insn
= NULL_RTX
;
7291 if (!INSN_ADDRESSES_SET_P())
7292 fatal_error (input_location
, "Insn addresses not set after shorten_branches");
7294 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7297 enum attr_type insn_type
;
7299 /* If a non-jump insn (or a casesi jump table), continue. */
7300 if (GET_CODE (insn
) != JUMP_INSN
||
7301 GET_CODE (PATTERN (insn
)) == ADDR_VEC
7302 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
)
7305 /* If we already have a brcc, note if it is suitable for brcc_s.
7306 Be a bit generous with the brcc_s range so that we can take
7307 advantage of any code shortening from delay slot scheduling. */
7308 if (recog_memoized (insn
) == CODE_FOR_cbranchsi4_scratch
)
7310 rtx pat
= PATTERN (insn
);
7311 rtx op
= XEXP (SET_SRC (XVECEXP (pat
, 0, 0)), 0);
7312 rtx
*ccp
= &XEXP (XVECEXP (pat
, 0, 1), 0);
7314 offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
7315 if ((offset
>= -140 && offset
< 140)
7316 && rtx_equal_p (XEXP (op
, 1), const0_rtx
)
7317 && compact_register_operand (XEXP (op
, 0), VOIDmode
)
7318 && equality_comparison_operator (op
, VOIDmode
))
7319 PUT_MODE (*ccp
, CC_Zmode
);
7320 else if (GET_MODE (*ccp
) == CC_Zmode
)
7321 PUT_MODE (*ccp
, CC_ZNmode
);
7324 if ((insn_type
= get_attr_type (insn
)) == TYPE_BRCC
7325 || insn_type
== TYPE_BRCC_NO_DELAY_SLOT
)
7328 /* OK. so we have a jump insn. */
7329 /* We need to check that it is a bcc. */
7330 /* Bcc => set (pc) (if_then_else ) */
7331 pattern
= PATTERN (insn
);
7332 if (GET_CODE (pattern
) != SET
7333 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
7334 || ANY_RETURN_P (XEXP (SET_SRC (pattern
), 1)))
7337 /* Now check if the jump is beyond the s9 range. */
7338 if (CROSSING_JUMP_P (insn
))
7340 offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
7342 if(offset
> 253 || offset
< -254)
7345 pc_target
= SET_SRC (pattern
);
7347 /* Avoid FPU instructions. */
7348 if ((GET_MODE (XEXP (XEXP (pc_target
, 0), 0)) == CC_FPUmode
)
7349 || (GET_MODE (XEXP (XEXP (pc_target
, 0), 0)) == CC_FPU_UNEQmode
))
7352 /* Now go back and search for the set cc insn. */
7354 label
= XEXP (pc_target
, 1);
7358 rtx_insn
*scan
, *link_insn
= NULL
;
7360 for (scan
= PREV_INSN (insn
);
7361 scan
&& GET_CODE (scan
) != CODE_LABEL
;
7362 scan
= PREV_INSN (scan
))
7364 if (! INSN_P (scan
))
7366 pat
= PATTERN (scan
);
7367 if (GET_CODE (pat
) == SET
7368 && cc_register (SET_DEST (pat
), VOIDmode
))
7377 /* Check if this is a data dependency. */
7379 rtx op
, cc_clob_rtx
, op0
, op1
, brcc_insn
, note
;
7382 /* Ok this is the set cc. copy args here. */
7383 op
= XEXP (pc_target
, 0);
7385 op0
= cmp0
= XEXP (SET_SRC (pat
), 0);
7386 op1
= cmp1
= XEXP (SET_SRC (pat
), 1);
7387 if (GET_CODE (op0
) == ZERO_EXTRACT
7388 && XEXP (op0
, 1) == const1_rtx
7389 && (GET_CODE (op
) == EQ
7390 || GET_CODE (op
) == NE
))
7392 /* btst / b{eq,ne} -> bbit{0,1} */
7393 op0
= XEXP (cmp0
, 0);
7394 op1
= XEXP (cmp0
, 2);
7396 else if (!register_operand (op0
, VOIDmode
)
7397 || !general_operand (op1
, VOIDmode
))
7399 /* Be careful not to break what cmpsfpx_raw is
7400 trying to create for checking equality of
7401 single-precision floats. */
7402 else if (TARGET_SPFP
7403 && GET_MODE (op0
) == SFmode
7404 && GET_MODE (op1
) == SFmode
)
7407 /* None of the two cmp operands should be set between the
7408 cmp and the branch. */
7409 if (reg_set_between_p (op0
, link_insn
, insn
))
7412 if (reg_set_between_p (op1
, link_insn
, insn
))
7415 /* Since the MODE check does not work, check that this is
7416 CC reg's last set location before insn, and also no
7417 instruction between the cmp and branch uses the
7419 if ((reg_set_between_p (SET_DEST (pat
), link_insn
, insn
))
7420 || (reg_used_between_p (SET_DEST (pat
), link_insn
, insn
)))
7423 /* CC reg should be dead after insn. */
7424 if (!find_regno_note (insn
, REG_DEAD
, CC_REG
))
7427 op
= gen_rtx_fmt_ee (GET_CODE (op
),
7428 GET_MODE (op
), cmp0
, cmp1
);
7429 /* If we create a LIMM where there was none before,
7430 we only benefit if we can avoid a scheduling bubble
7431 for the ARC600. Otherwise, we'd only forgo chances
7432 at short insn generation, and risk out-of-range
7434 if (!brcc_nolimm_operator (op
, VOIDmode
)
7435 && !long_immediate_operand (op1
, VOIDmode
)
7437 || next_active_insn (link_insn
) != insn
))
7440 /* Emit bbit / brcc (or brcc_s if possible).
7441 CC_Zmode indicates that brcc_s is possible. */
7444 cc_clob_rtx
= gen_rtx_REG (CC_ZNmode
, CC_REG
);
7445 else if ((offset
>= -140 && offset
< 140)
7446 && rtx_equal_p (op1
, const0_rtx
)
7447 && compact_register_operand (op0
, VOIDmode
)
7448 && (GET_CODE (op
) == EQ
7449 || GET_CODE (op
) == NE
))
7450 cc_clob_rtx
= gen_rtx_REG (CC_Zmode
, CC_REG
);
7452 cc_clob_rtx
= gen_rtx_REG (CCmode
, CC_REG
);
7455 = gen_rtx_IF_THEN_ELSE (VOIDmode
, op
, label
, pc_rtx
);
7456 brcc_insn
= gen_rtx_SET (pc_rtx
, brcc_insn
);
7457 cc_clob_rtx
= gen_rtx_CLOBBER (VOIDmode
, cc_clob_rtx
);
7460 (VOIDmode
, gen_rtvec (2, brcc_insn
, cc_clob_rtx
));
7461 brcc_insn
= emit_jump_insn_before (brcc_insn
, insn
);
7463 JUMP_LABEL (brcc_insn
) = JUMP_LABEL (insn
);
7464 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
7467 XEXP (note
, 1) = REG_NOTES (brcc_insn
);
7468 REG_NOTES (brcc_insn
) = note
;
7470 note
= find_reg_note (link_insn
, REG_DEAD
, op0
);
7473 remove_note (link_insn
, note
);
7474 XEXP (note
, 1) = REG_NOTES (brcc_insn
);
7475 REG_NOTES (brcc_insn
) = note
;
7477 note
= find_reg_note (link_insn
, REG_DEAD
, op1
);
7480 XEXP (note
, 1) = REG_NOTES (brcc_insn
);
7481 REG_NOTES (brcc_insn
) = note
;
7486 /* Delete the bcc insn. */
7487 set_insn_deleted (insn
);
7489 /* Delete the cmp insn. */
7490 set_insn_deleted (link_insn
);
7495 /* Clear out insn_addresses. */
7496 INSN_ADDRESSES_FREE ();
7500 if (INSN_ADDRESSES_SET_P())
7501 fatal_error (input_location
, "insn addresses not freed");
7503 arc_reorg_in_progress
= 0;
7506 /* Check if the operands are valid for BRcc.d generation
7507 Valid Brcc.d patterns are
7511 For cc={GT, LE, GTU, LEU}, u6=63 can not be allowed,
7512 since they are encoded by the assembler as {GE, LT, HS, LS} 64, which
7513 does not have a delay slot
7515 Assumed precondition: Second operand is either a register or a u6 value. */
7518 valid_brcc_with_delay_p (rtx
*operands
)
7520 if (optimize_size
&& GET_MODE (operands
[4]) == CC_Zmode
)
7522 return brcc_nolimm_operator (operands
[0], VOIDmode
);
7525 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7526 access DECL using %gp_rel(...)($gp). */
7529 arc_in_small_data_p (const_tree decl
)
7533 /* Only variables are going into small data area. */
7534 if (TREE_CODE (decl
) != VAR_DECL
)
7537 if (TARGET_NO_SDATA_SET
)
7540 /* Disable sdata references to weak variables. */
7541 if (DECL_WEAK (decl
))
7544 /* Don't put constants into the small data section: we want them to
7545 be in ROM rather than RAM. */
7546 if (TREE_READONLY (decl
))
7549 /* To ensure -mvolatile-cache works ld.di does not have a
7550 gp-relative variant. */
7551 if (!TARGET_VOLATILE_CACHE_SET
7552 && TREE_THIS_VOLATILE (decl
))
7555 if (DECL_SECTION_NAME (decl
) != 0)
7557 const char *name
= DECL_SECTION_NAME (decl
);
7558 if (strcmp (name
, ".sdata") == 0
7559 || strcmp (name
, ".sbss") == 0)
7562 /* If it's not public, there's no need to put it in the small data
7564 else if (TREE_PUBLIC (decl
))
7566 size
= int_size_in_bytes (TREE_TYPE (decl
));
7567 return (size
> 0 && size
<= g_switch_value
);
7572 /* Return true if X is a small data address that can be rewritten
7576 arc_rewrite_small_data_p (const_rtx x
)
7578 if (GET_CODE (x
) == CONST
)
7581 if (GET_CODE (x
) == PLUS
)
7583 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7587 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (x
))
7589 gcc_assert (SYMBOL_REF_TLS_MODEL (x
) == 0);
7595 /* If possible, rewrite OP so that it refers to small data using
7596 explicit relocations. */
7599 arc_rewrite_small_data_1 (rtx op
)
7601 rtx rgp
= gen_rtx_REG (Pmode
, SDATA_BASE_REGNUM
);
7602 op
= copy_insn (op
);
7603 subrtx_ptr_iterator::array_type array
;
7604 FOR_EACH_SUBRTX_PTR (iter
, array
, &op
, ALL
)
7607 if (arc_rewrite_small_data_p (*loc
))
7609 *loc
= gen_rtx_PLUS (Pmode
, rgp
, *loc
);
7610 iter
.skip_subrtxes ();
7612 else if (GET_CODE (*loc
) == PLUS
7613 && rtx_equal_p (XEXP (*loc
, 0), rgp
))
7614 iter
.skip_subrtxes ();
7620 arc_rewrite_small_data (rtx op
)
7622 op
= arc_rewrite_small_data_1 (op
);
7624 /* Check if we fit small data constraints. */
7626 && !LEGITIMATE_SMALL_DATA_ADDRESS_P (XEXP (op
, 0)))
7628 rtx addr
= XEXP (op
, 0);
7629 rtx tmp
= gen_reg_rtx (Pmode
);
7630 emit_move_insn (tmp
, addr
);
7631 op
= replace_equiv_address_nv (op
, tmp
);
7636 /* Return true if OP refers to small data symbols directly, not through
7640 small_data_pattern (rtx op
, machine_mode
)
7642 if (GET_CODE (op
) == SEQUENCE
)
7645 rtx rgp
= gen_rtx_REG (Pmode
, SDATA_BASE_REGNUM
);
7646 subrtx_iterator::array_type array
;
7647 FOR_EACH_SUBRTX (iter
, array
, op
, ALL
)
7649 const_rtx x
= *iter
;
7650 if (GET_CODE (x
) == PLUS
7651 && rtx_equal_p (XEXP (x
, 0), rgp
))
7652 iter
.skip_subrtxes ();
7653 else if (arc_rewrite_small_data_p (x
))
7659 /* Return true if OP is an acceptable memory operand for ARCompact
7660 16-bit gp-relative load instructions.
7661 op shd look like : [r26, symref@sda]
7662 i.e. (mem (plus (reg 26) (symref with smalldata flag set))
7664 /* volatile cache option still to be handled. */
7667 compact_sda_memory_operand (rtx op
, machine_mode mode
, bool short_p
)
7671 tree decl
= NULL_TREE
;
7675 /* Eliminate non-memory operations. */
7676 if (GET_CODE (op
) != MEM
)
7679 if (mode
== VOIDmode
)
7680 mode
= GET_MODE (op
);
7682 size
= GET_MODE_SIZE (mode
);
7684 /* dword operations really put out 2 instructions, so eliminate them. */
7685 if (size
> UNITS_PER_WORD
)
7688 /* Decode the address now. */
7689 addr
= XEXP (op
, 0);
7691 if (!LEGITIMATE_SMALL_DATA_ADDRESS_P (addr
))
7694 if (!short_p
|| size
== 1)
7697 /* Now check for the alignment, the short loads using gp require the
7698 addresses to be aligned. */
7699 if (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
)
7700 decl
= SYMBOL_REF_DECL (XEXP (addr
, 1));
7701 else if (GET_CODE (XEXP (XEXP (XEXP (addr
, 1), 0), 0)) == SYMBOL_REF
)
7702 decl
= SYMBOL_REF_DECL (XEXP (XEXP (XEXP (addr
, 1), 0), 0));
7704 align
= DECL_ALIGN (decl
);
7705 align
= align
/ BITS_PER_UNIT
;
7717 if (align
&& ((align
& mask
) == 0))
7722 /* Implement ASM_OUTPUT_ALIGNED_DECL_LOCAL. */
7725 arc_asm_output_aligned_decl_local (FILE * stream
, tree decl
, const char * name
,
7726 unsigned HOST_WIDE_INT size
,
7727 unsigned HOST_WIDE_INT align
,
7728 unsigned HOST_WIDE_INT globalize_p
)
7730 int in_small_data
= arc_in_small_data_p (decl
);
7733 switch_to_section (get_named_section (NULL
, ".sbss", 0));
7734 /* named_section (0,".sbss",0); */
7736 switch_to_section (bss_section
);
7739 (*targetm
.asm_out
.globalize_label
) (stream
, name
);
7741 ASM_OUTPUT_ALIGN (stream
, floor_log2 ((align
) / BITS_PER_UNIT
));
7742 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
7743 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
7744 ASM_OUTPUT_LABEL (stream
, name
);
7747 ASM_OUTPUT_SKIP (stream
, size
);
7751 arc_preserve_reload_p (rtx in
)
7753 return (GET_CODE (in
) == PLUS
7754 && RTX_OK_FOR_BASE_P (XEXP (in
, 0), true)
7755 && CONST_INT_P (XEXP (in
, 1))
7756 && !((INTVAL (XEXP (in
, 1)) & 511)));
7760 arc_register_move_cost (machine_mode
,
7761 enum reg_class from_class
, enum reg_class to_class
)
7763 /* The ARC600 has no bypass for extension registers, hence a nop might be
7764 needed to be inserted after a write so that reads are safe. */
7767 if (to_class
== MPY_WRITABLE_CORE_REGS
)
7769 /* Instructions modifying LP_COUNT need 4 additional cycles before
7770 the register will actually contain the value. */
7771 else if (to_class
== LPCOUNT_REG
)
7773 else if (to_class
== WRITABLE_CORE_REGS
)
7777 /* The ARC700 stalls for 3 cycles when *reading* from lp_count. */
7779 && (from_class
== LPCOUNT_REG
|| from_class
== ALL_CORE_REGS
7780 || from_class
== WRITABLE_CORE_REGS
))
7783 /* Force an attempt to 'mov Dy,Dx' to spill. */
7784 if ((TARGET_ARC700
|| TARGET_EM
) && TARGET_DPFP
7785 && from_class
== DOUBLE_REGS
&& to_class
== DOUBLE_REGS
)
7791 /* Emit code for an addsi3 instruction with OPERANDS.
7792 COND_P indicates if this will use conditional execution.
7793 Return the length of the instruction.
7794 If OUTPUT_P is false, don't actually output the instruction, just return
7797 arc_output_addsi (rtx
*operands
, bool cond_p
, bool output_p
)
7801 int match
= operands_match_p (operands
[0], operands
[1]);
7802 int match2
= operands_match_p (operands
[0], operands
[2]);
7803 int intval
= (REG_P (operands
[2]) ? 1
7804 : CONST_INT_P (operands
[2]) ? INTVAL (operands
[2]) : 0xbadc057);
7805 int neg_intval
= -intval
;
7806 int short_0
= satisfies_constraint_Rcq (operands
[0]);
7807 int short_p
= (!cond_p
&& short_0
&& satisfies_constraint_Rcq (operands
[1]));
7810 #define REG_H_P(OP) (REG_P (OP) && ((TARGET_V2 && REGNO (OP) <= 31 \
7811 && REGNO (OP) != 30) \
7814 #define ADDSI_OUTPUT1(FORMAT) do {\
7816 output_asm_insn (FORMAT, operands);\
7819 #define ADDSI_OUTPUT(LIST) do {\
7822 ADDSI_OUTPUT1 (format);\
7826 /* First try to emit a 16 bit insn. */
7829 /* If we are actually about to output this insn, don't try a 16 bit
7830 variant if we already decided that we don't want that
7831 (I.e. we upsized this insn to align some following insn.)
7832 E.g. add_s r0,sp,70 is 16 bit, but add r0,sp,70 requires a LIMM -
7833 but add1 r0,sp,35 doesn't. */
7834 && (!output_p
|| (get_attr_length (current_output_insn
) & 2)))
7836 /* Generate add_s a,b,c; add_s b,b,u7; add_s c,b,u3; add_s b,b,h
7839 && ((REG_H_P (operands
[2])
7840 && (match
|| satisfies_constraint_Rcq (operands
[2])))
7841 || (CONST_INT_P (operands
[2])
7842 && ((unsigned) intval
<= (match
? 127 : 7)))))
7843 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;1");
7845 /* Generate add_s b,b,h patterns. */
7846 if (short_0
&& match2
&& REG_H_P (operands
[1]))
7847 ADDSI_OUTPUT1 ("add%? %0,%2,%1 ;2");
7849 /* Generate add_s b,sp,u7; add_s sp,sp,u7 patterns. */
7850 if ((short_0
|| REGNO (operands
[0]) == STACK_POINTER_REGNUM
)
7851 && REGNO (operands
[1]) == STACK_POINTER_REGNUM
&& !(intval
& ~124))
7852 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;3");
7854 if ((short_p
&& (unsigned) neg_intval
<= (match
? 31 : 7))
7855 || (REGNO (operands
[0]) == STACK_POINTER_REGNUM
7856 && match
&& !(neg_intval
& ~124)))
7857 ADDSI_OUTPUT1 ("sub%? %0,%1,%n2 ;4");
7859 /* Generate add_s h,h,s3 patterns. */
7860 if (REG_H_P (operands
[0]) && match
&& TARGET_V2
7861 && CONST_INT_P (operands
[2]) && ((intval
>= -1) && (intval
<= 6)))
7862 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;5");
7864 /* Generate add_s r0,b,u6; add_s r1,b,u6 patterns. */
7865 if (TARGET_CODE_DENSITY
&& REG_P (operands
[0]) && REG_P (operands
[1])
7866 && ((REGNO (operands
[0]) == 0) || (REGNO (operands
[0]) == 1))
7867 && satisfies_constraint_Rcq (operands
[1])
7868 && satisfies_constraint_L (operands
[2]))
7869 ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;6");
7872 /* Now try to emit a 32 bit insn without long immediate. */
7874 if (!match
&& match2
&& REG_P (operands
[1]))
7875 ADDSI_OUTPUT1 ("add%? %0,%2,%1");
7876 if (match
|| !cond_p
)
7878 int limit
= (match
&& !cond_p
) ? 0x7ff : 0x3f;
7879 int range_factor
= neg_intval
& intval
;
7882 if (intval
== (HOST_WIDE_INT
) (HOST_WIDE_INT_M1U
<< 31))
7883 ADDSI_OUTPUT1 ("bxor%? %0,%1,31");
7885 /* If we can use a straight add / sub instead of a {add,sub}[123] of
7886 same size, do, so - the insn latency is lower. */
7887 /* -0x800 is a 12-bit constant for add /add3 / sub / sub3, but
7889 if ((intval
>= 0 && intval
<= limit
)
7890 || (intval
== -0x800 && limit
== 0x7ff))
7891 ADDSI_OUTPUT1 ("add%? %0,%1,%2");
7892 else if ((intval
< 0 && neg_intval
<= limit
)
7893 || (intval
== 0x800 && limit
== 0x7ff))
7894 ADDSI_OUTPUT1 ("sub%? %0,%1,%n2");
7895 shift
= range_factor
>= 8 ? 3 : (range_factor
>> 1);
7896 gcc_assert (shift
== 0 || shift
== 1 || shift
== 2 || shift
== 3);
7897 gcc_assert ((((1 << shift
) - 1) & intval
) == 0);
7898 if (((intval
< 0 && intval
!= -0x4000)
7899 /* sub[123] is slower than add_s / sub, only use it if it
7900 avoids a long immediate. */
7901 && neg_intval
<= limit
<< shift
)
7902 || (intval
== 0x4000 && limit
== 0x7ff))
7903 ADDSI_OUTPUT ((format
, "sub%d%%? %%0,%%1,%d",
7904 shift
, neg_intval
>> shift
));
7905 else if ((intval
>= 0 && intval
<= limit
<< shift
)
7906 || (intval
== -0x4000 && limit
== 0x7ff))
7907 ADDSI_OUTPUT ((format
, "add%d%%? %%0,%%1,%d", shift
, intval
>> shift
));
7909 /* Try to emit a 16 bit opcode with long immediate. */
7911 if (short_p
&& match
)
7912 ADDSI_OUTPUT1 ("add%? %0,%1,%S2");
7914 /* We have to use a 32 bit opcode, and with a long immediate. */
7916 ADDSI_OUTPUT1 (intval
< 0 ? "sub%? %0,%1,%n2" : "add%? %0,%1,%S2");
7919 /* Emit code for an commutative_cond_exec instruction with OPERANDS.
7920 Return the length of the instruction.
7921 If OUTPUT_P is false, don't actually output the instruction, just return
7924 arc_output_commutative_cond_exec (rtx
*operands
, bool output_p
)
7926 enum rtx_code commutative_op
= GET_CODE (operands
[3]);
7927 const char *pat
= NULL
;
7929 /* Canonical rtl should not have a constant in the first operand position. */
7930 gcc_assert (!CONSTANT_P (operands
[1]));
7932 switch (commutative_op
)
7935 if (satisfies_constraint_C1p (operands
[2]))
7936 pat
= "bmsk%? %0,%1,%Z2";
7937 else if (satisfies_constraint_C2p (operands
[2]))
7939 operands
[2] = GEN_INT ((~INTVAL (operands
[2])));
7940 pat
= "bmskn%? %0,%1,%Z2";
7942 else if (satisfies_constraint_Ccp (operands
[2]))
7943 pat
= "bclr%? %0,%1,%M2";
7944 else if (satisfies_constraint_CnL (operands
[2]))
7945 pat
= "bic%? %0,%1,%n2-1";
7948 if (satisfies_constraint_C0p (operands
[2]))
7949 pat
= "bset%? %0,%1,%z2";
7952 if (satisfies_constraint_C0p (operands
[2]))
7953 pat
= "bxor%? %0,%1,%z2";
7956 return arc_output_addsi (operands
, true, output_p
);
7960 output_asm_insn (pat
? pat
: "%O3.%d5 %0,%1,%2", operands
);
7961 if (pat
|| REG_P (operands
[2]) || satisfies_constraint_L (operands
[2]))
7966 /* Helper function of arc_expand_movmem. ADDR points to a chunk of memory.
7967 Emit code and return an potentially modified address such that offsets
7968 up to SIZE are can be added to yield a legitimate address.
7969 if REUSE is set, ADDR is a register that may be modified. */
7972 force_offsettable (rtx addr
, HOST_WIDE_INT size
, bool reuse
)
7975 rtx offs
= const0_rtx
;
7977 if (GET_CODE (base
) == PLUS
)
7979 offs
= XEXP (base
, 1);
7980 base
= XEXP (base
, 0);
7983 || (REGNO (base
) != STACK_POINTER_REGNUM
7984 && REGNO_PTR_FRAME_P (REGNO (base
)))
7985 || !CONST_INT_P (offs
) || !SMALL_INT (INTVAL (offs
))
7986 || !SMALL_INT (INTVAL (offs
) + size
))
7989 emit_insn (gen_add2_insn (addr
, offs
));
7991 addr
= copy_to_mode_reg (Pmode
, addr
);
7996 /* Like move_by_pieces, but take account of load latency, and actual
7997 offset ranges. Return true on success. */
8000 arc_expand_movmem (rtx
*operands
)
8002 rtx dst
= operands
[0];
8003 rtx src
= operands
[1];
8004 rtx dst_addr
, src_addr
;
8006 int align
= INTVAL (operands
[3]);
8013 if (!CONST_INT_P (operands
[2]))
8015 size
= INTVAL (operands
[2]);
8016 /* move_by_pieces_ninsns is static, so we can't use it. */
8020 n_pieces
= (size
+ 4) / 8U + ((size
>> 1) & 1) + (size
& 1);
8022 n_pieces
= (size
+ 2) / 4U + (size
& 1);
8024 else if (align
== 2)
8025 n_pieces
= (size
+ 1) / 2U;
8028 if (n_pieces
>= (unsigned int) (optimize_size
? 3 : 15))
8030 /* Force 32 bit aligned and larger datum to use 64 bit transfers, if
8032 if (TARGET_LL64
&& (piece
>= 4) && (size
>= 8))
8036 dst_addr
= force_offsettable (XEXP (operands
[0], 0), size
, 0);
8037 src_addr
= force_offsettable (XEXP (operands
[1], 0), size
, 0);
8038 store
[0] = store
[1] = NULL_RTX
;
8039 tmpx
[0] = tmpx
[1] = NULL_RTX
;
8040 for (i
= 0; size
> 0; i
^= 1, size
-= piece
)
8045 while (piece
> size
)
8047 mode
= smallest_int_mode_for_size (piece
* BITS_PER_UNIT
);
8048 /* If we don't re-use temporaries, the scheduler gets carried away,
8049 and the register pressure gets unnecessarily high. */
8050 if (0 && tmpx
[i
] && GET_MODE (tmpx
[i
]) == mode
)
8053 tmpx
[i
] = tmp
= gen_reg_rtx (mode
);
8054 dst_addr
= force_offsettable (dst_addr
, piece
, 1);
8055 src_addr
= force_offsettable (src_addr
, piece
, 1);
8057 emit_insn (store
[i
]);
8058 emit_move_insn (tmp
, change_address (src
, mode
, src_addr
));
8059 store
[i
] = gen_move_insn (change_address (dst
, mode
, dst_addr
), tmp
);
8060 dst_addr
= plus_constant (Pmode
, dst_addr
, piece
);
8061 src_addr
= plus_constant (Pmode
, src_addr
, piece
);
8064 emit_insn (store
[i
]);
8066 emit_insn (store
[i
^1]);
8070 /* Prepare operands for move in MODE. Return true iff the move has
8074 prepare_move_operands (rtx
*operands
, machine_mode mode
)
8076 /* We used to do this only for MODE_INT Modes, but addresses to floating
8077 point variables may well be in the small data section. */
8078 if (!TARGET_NO_SDATA_SET
&& small_data_pattern (operands
[0], Pmode
))
8079 operands
[0] = arc_rewrite_small_data (operands
[0]);
8081 if (mode
== SImode
&& SYMBOLIC_CONST (operands
[1]))
8083 prepare_pic_move (operands
, SImode
);
8085 /* Disable any REG_EQUALs associated with the symref
8086 otherwise the optimization pass undoes the work done
8087 here and references the variable directly. */
8090 if (GET_CODE (operands
[0]) != MEM
8091 && !TARGET_NO_SDATA_SET
8092 && small_data_pattern (operands
[1], Pmode
))
8094 /* This is to take care of address calculations involving sdata
8096 operands
[1] = arc_rewrite_small_data (operands
[1]);
8098 emit_insn (gen_rtx_SET (operands
[0],operands
[1]));
8099 /* ??? This note is useless, since it only restates the set itself.
8100 We should rather use the original SYMBOL_REF. However, there is
8101 the problem that we are lying to the compiler about these
8102 SYMBOL_REFs to start with. symbol@sda should be encoded specially
8103 so that we can tell it apart from an actual symbol. */
8104 set_unique_reg_note (get_last_insn (), REG_EQUAL
, operands
[1]);
8106 /* Take care of the REG_EQUAL note that will be attached to mark the
8107 output reg equal to the initial symbol_ref after this code is
8109 emit_move_insn (operands
[0], operands
[0]);
8113 if (MEM_P (operands
[0])
8114 && !(reload_in_progress
|| reload_completed
))
8116 operands
[1] = force_reg (mode
, operands
[1]);
8117 if (!move_dest_operand (operands
[0], mode
))
8119 rtx addr
= copy_to_mode_reg (Pmode
, XEXP (operands
[0], 0));
8120 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
8121 except that we can't use that function because it is static. */
8122 rtx pat
= change_address (operands
[0], mode
, addr
);
8123 MEM_COPY_ATTRIBUTES (pat
, operands
[0]);
8126 if (!cse_not_expected
)
8128 rtx pat
= XEXP (operands
[0], 0);
8130 pat
= arc_legitimize_address_0 (pat
, pat
, mode
);
8133 pat
= change_address (operands
[0], mode
, pat
);
8134 MEM_COPY_ATTRIBUTES (pat
, operands
[0]);
8140 if (MEM_P (operands
[1]) && !cse_not_expected
)
8142 rtx pat
= XEXP (operands
[1], 0);
8144 pat
= arc_legitimize_address_0 (pat
, pat
, mode
);
8147 pat
= change_address (operands
[1], mode
, pat
);
8148 MEM_COPY_ATTRIBUTES (pat
, operands
[1]);
8156 /* Prepare OPERANDS for an extension using CODE to OMODE.
8157 Return true iff the move has been emitted. */
8160 prepare_extend_operands (rtx
*operands
, enum rtx_code code
,
8163 if (!TARGET_NO_SDATA_SET
&& small_data_pattern (operands
[1], Pmode
))
8165 /* This is to take care of address calculations involving sdata
8168 = gen_rtx_fmt_e (code
, omode
, arc_rewrite_small_data (operands
[1]));
8169 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
8170 set_unique_reg_note (get_last_insn (), REG_EQUAL
, operands
[1]);
8172 /* Take care of the REG_EQUAL note that will be attached to mark the
8173 output reg equal to the initial extension after this code is
8175 emit_move_insn (operands
[0], operands
[0]);
8181 /* Output a library call to a function called FNAME that has been arranged
8182 to be local to any dso. */
8185 arc_output_libcall (const char *fname
)
8187 unsigned len
= strlen (fname
);
8188 static char buf
[64];
8190 gcc_assert (len
< sizeof buf
- 35);
8191 if (TARGET_LONG_CALLS_SET
8192 || (TARGET_MEDIUM_CALLS
&& arc_ccfsm_cond_exec_p ()))
8195 sprintf (buf
, "add r12,pcl,@%s@pcl\n\tjl%%!%%* [r12]", fname
);
8197 sprintf (buf
, "jl%%! @%s", fname
);
8200 sprintf (buf
, "bl%%!%%* @%s", fname
);
8204 /* Return the SImode highpart of the DImode value IN. */
8207 disi_highpart (rtx in
)
8209 return simplify_gen_subreg (SImode
, in
, DImode
, TARGET_BIG_ENDIAN
? 0 : 4);
8212 /* Return length adjustment for INSN.
8214 A write to a core reg greater or equal to 32 must not be immediately
8215 followed by a use. Anticipate the length requirement to insert a nop
8216 between PRED and SUCC to prevent a hazard. */
8219 arc600_corereg_hazard (rtx_insn
*pred
, rtx_insn
*succ
)
8223 /* If SUCC is a doloop_end_i with a preceding label, we must output a nop
8224 in front of SUCC anyway, so there will be separation between PRED and
8226 if (recog_memoized (succ
) == CODE_FOR_doloop_end_i
8227 && LABEL_P (prev_nonnote_insn (succ
)))
8229 if (recog_memoized (succ
) == CODE_FOR_doloop_begin_i
)
8231 if (GET_CODE (PATTERN (pred
)) == SEQUENCE
)
8232 pred
= as_a
<rtx_sequence
*> (PATTERN (pred
))->insn (1);
8233 if (GET_CODE (PATTERN (succ
)) == SEQUENCE
)
8234 succ
= as_a
<rtx_sequence
*> (PATTERN (succ
))->insn (0);
8235 if (recog_memoized (pred
) == CODE_FOR_mulsi_600
8236 || recog_memoized (pred
) == CODE_FOR_umul_600
8237 || recog_memoized (pred
) == CODE_FOR_mac_600
8238 || recog_memoized (pred
) == CODE_FOR_mul64_600
8239 || recog_memoized (pred
) == CODE_FOR_mac64_600
8240 || recog_memoized (pred
) == CODE_FOR_umul64_600
8241 || recog_memoized (pred
) == CODE_FOR_umac64_600
)
8243 subrtx_iterator::array_type array
;
8244 FOR_EACH_SUBRTX (iter
, array
, PATTERN (pred
), NONCONST
)
8246 const_rtx x
= *iter
;
8247 switch (GET_CODE (x
))
8249 case SET
: case POST_INC
: case POST_DEC
: case PRE_INC
: case PRE_DEC
:
8252 /* This is also fine for PRE/POST_MODIFY, because they
8256 rtx dest
= XEXP (x
, 0);
8257 /* Check if this sets a an extension register. N.B. we use 61 for the
8258 condition codes, which is definitely not an extension register. */
8259 if (REG_P (dest
) && REGNO (dest
) >= 32 && REGNO (dest
) < 61
8260 /* Check if the same register is used by the PAT. */
8261 && (refers_to_regno_p
8263 REGNO (dest
) + (GET_MODE_SIZE (GET_MODE (dest
)) + 3) / 4U,
8264 PATTERN (succ
), 0)))
8270 /* Given a rtx, check if it is an assembly instruction or not. */
8273 arc_asm_insn_p (rtx x
)
8280 switch (GET_CODE (x
))
8287 return arc_asm_insn_p (SET_SRC (x
));
8291 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8292 j
+= arc_asm_insn_p (XVECEXP (x
, 0, i
));
8304 /* We might have a CALL to a non-returning function before a loop end.
8305 ??? Although the manual says that's OK (the target is outside the
8306 loop, and the loop counter unused there), the assembler barfs on
8307 this for ARC600, so we must insert a nop before such a call too.
8308 For ARC700, and ARCv2 is not allowed to have the last ZOL
8309 instruction a jump to a location where lp_count is modified. */
8312 arc_loop_hazard (rtx_insn
*pred
, rtx_insn
*succ
)
8314 rtx_insn
*jump
= NULL
;
8315 rtx label_rtx
= NULL_RTX
;
8316 rtx_insn
*label
= NULL
;
8317 basic_block succ_bb
;
8319 if (recog_memoized (succ
) != CODE_FOR_doloop_end_i
)
8322 /* Phase 1: ARC600 and ARCv2HS doesn't allow any control instruction
8323 (i.e., jump/call) as the last instruction of a ZOL. */
8324 if (TARGET_ARC600
|| TARGET_HS
)
8325 if (JUMP_P (pred
) || CALL_P (pred
)
8326 || arc_asm_insn_p (PATTERN (pred
))
8327 || GET_CODE (PATTERN (pred
)) == SEQUENCE
)
8330 /* Phase 2: Any architecture, it is not allowed to have the last ZOL
8331 instruction a jump to a location where lp_count is modified. */
8333 /* Phase 2a: Dig for the jump instruction. */
8336 else if (GET_CODE (PATTERN (pred
)) == SEQUENCE
8337 && JUMP_P (XVECEXP (PATTERN (pred
), 0, 0)))
8338 jump
= as_a
<rtx_insn
*> (XVECEXP (PATTERN (pred
), 0, 0));
8342 /* Phase 2b: Make sure is not a millicode jump. */
8343 if ((GET_CODE (PATTERN (jump
)) == PARALLEL
)
8344 && (XVECEXP (PATTERN (jump
), 0, 0) == ret_rtx
))
8347 label_rtx
= JUMP_LABEL (jump
);
8351 /* Phase 2c: Make sure is not a return. */
8352 if (ANY_RETURN_P (label_rtx
))
8355 /* Pahse 2d: Go to the target of the jump and check for aliveness of
8356 LP_COUNT register. */
8357 label
= safe_as_a
<rtx_insn
*> (label_rtx
);
8358 succ_bb
= BLOCK_FOR_INSN (label
);
8361 gcc_assert (NEXT_INSN (label
));
8362 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (label
)))
8363 succ_bb
= NOTE_BASIC_BLOCK (NEXT_INSN (label
));
8365 succ_bb
= BLOCK_FOR_INSN (NEXT_INSN (label
));
8368 if (succ_bb
&& REGNO_REG_SET_P (df_get_live_out (succ_bb
), LP_COUNT
))
8375 A write to a core reg greater or equal to 32 must not be immediately
8376 followed by a use. Anticipate the length requirement to insert a nop
8377 between PRED and SUCC to prevent a hazard. */
8380 arc_hazard (rtx_insn
*pred
, rtx_insn
*succ
)
8382 if (!pred
|| !INSN_P (pred
) || !succ
|| !INSN_P (succ
))
8385 if (arc_loop_hazard (pred
, succ
))
8389 return arc600_corereg_hazard (pred
, succ
);
8394 /* Return length adjustment for INSN. */
8397 arc_adjust_insn_length (rtx_insn
*insn
, int len
, bool)
8401 /* We already handle sequences by ignoring the delay sequence flag. */
8402 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
8405 /* It is impossible to jump to the very end of a Zero-Overhead Loop, as
8406 the ZOL mechanism only triggers when advancing to the end address,
8407 so if there's a label at the end of a ZOL, we need to insert a nop.
8408 The ARC600 ZOL also has extra restrictions on jumps at the end of a
8410 if (recog_memoized (insn
) == CODE_FOR_doloop_end_i
)
8412 rtx_insn
*prev
= prev_nonnote_insn (insn
);
8414 return ((LABEL_P (prev
)
8417 || CALL_P (prev
) /* Could be a noreturn call. */
8418 || (NONJUMP_INSN_P (prev
)
8419 && GET_CODE (PATTERN (prev
)) == SEQUENCE
))))
8423 /* Check for return with but one preceding insn since function
8425 if (TARGET_PAD_RETURN
8427 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
8428 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
8429 && get_attr_type (insn
) == TYPE_RETURN
)
8431 rtx_insn
*prev
= prev_active_insn (insn
);
8433 if (!prev
|| !(prev
= prev_active_insn (prev
))
8434 || ((NONJUMP_INSN_P (prev
)
8435 && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
8436 ? CALL_ATTR (as_a
<rtx_sequence
*> (PATTERN (prev
))->insn (0),
8438 : CALL_ATTR (prev
, NON_SIBCALL
)))
8443 rtx_insn
*succ
= next_real_insn (insn
);
8445 /* One the ARC600, a write to an extension register must be separated
8447 if (succ
&& INSN_P (succ
))
8448 len
+= arc600_corereg_hazard (insn
, succ
);
8451 /* Restore extracted operands - otherwise splitters like the addsi3_mixed one
8453 extract_constrain_insn_cached (insn
);
8458 /* Values for length_sensitive. */
8462 ARC_LS_25
, // 25 bit offset, B
8463 ARC_LS_21
, // 21 bit offset, Bcc
8464 ARC_LS_U13
,// 13 bit unsigned offset, LP
8465 ARC_LS_10
, // 10 bit offset, B_s, Beq_s, Bne_s
8466 ARC_LS_9
, // 9 bit offset, BRcc
8467 ARC_LS_8
, // 8 bit offset, BRcc_s
8468 ARC_LS_U7
, // 7 bit unsigned offset, LPcc
8469 ARC_LS_7
// 7 bit offset, Bcc_s
8472 /* While the infrastructure patch is waiting for review, duplicate the
8473 struct definitions, to allow this file to compile. */
8478 /* Cost as a branch / call target or call return address. */
8480 int fallthrough_cost
;
8483 /* 0 for not length sensitive, 1 for largest offset range,
8484 * 2 for next smaller etc. */
8485 unsigned length_sensitive
: 8;
8487 } insn_length_variant_t
;
8489 typedef struct insn_length_parameters_s
8494 int (*get_variants
) (rtx_insn
*, int, bool, bool, insn_length_variant_t
*);
8495 } insn_length_parameters_t
;
8498 arc_insn_length_parameters (insn_length_parameters_t
*ilp
) ATTRIBUTE_UNUSED
;
8502 arc_get_insn_variants (rtx_insn
*insn
, int len
, bool, bool target_p
,
8503 insn_length_variant_t
*ilv
)
8505 if (!NONDEBUG_INSN_P (insn
))
8507 enum attr_type type
;
8508 /* shorten_branches doesn't take optimize_size into account yet for the
8509 get_variants mechanism, so turn this off for now. */
8512 if (rtx_sequence
*pat
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
8514 /* The interaction of a short delay slot insn with a short branch is
8515 too weird for shorten_branches to piece together, so describe the
8518 if (TARGET_UPSIZE_DBR
8519 && get_attr_length (pat
->insn (1)) <= 2
8520 && (((type
= get_attr_type (inner
= pat
->insn (0)))
8521 == TYPE_UNCOND_BRANCH
)
8522 || type
== TYPE_BRANCH
)
8523 && get_attr_delay_slot_filled (inner
) == DELAY_SLOT_FILLED_YES
)
8526 = arc_get_insn_variants (inner
, get_attr_length (inner
), true,
8528 /* The short variant gets split into a higher-cost aligned
8529 and a lower cost unaligned variant. */
8530 gcc_assert (n_variants
);
8531 gcc_assert (ilv
[1].length_sensitive
== ARC_LS_7
8532 || ilv
[1].length_sensitive
== ARC_LS_10
);
8533 gcc_assert (ilv
[1].align_set
== 3);
8535 ilv
[0].align_set
= 1;
8536 ilv
[0].branch_cost
+= 1;
8537 ilv
[1].align_set
= 2;
8539 for (int i
= 0; i
< n_variants
; i
++)
8541 /* In case an instruction with aligned size is wanted, and
8542 the short variants are unavailable / too expensive, add
8543 versions of long branch + long delay slot. */
8544 for (int i
= 2, end
= n_variants
; i
< end
; i
++, n_variants
++)
8546 ilv
[n_variants
] = ilv
[i
];
8547 ilv
[n_variants
].length
+= 2;
8553 insn_length_variant_t
*first_ilv
= ilv
;
8554 type
= get_attr_type (insn
);
8556 = (get_attr_delay_slot_filled (insn
) == DELAY_SLOT_FILLED_YES
);
8557 int branch_align_cost
= delay_filled
? 0 : 1;
8558 int branch_unalign_cost
= delay_filled
? 0 : TARGET_UNALIGN_BRANCH
? 0 : 1;
8559 /* If the previous instruction is an sfunc call, this insn is always
8560 a target, even though the middle-end is unaware of this. */
8561 bool force_target
= false;
8562 rtx_insn
*prev
= prev_active_insn (insn
);
8563 if (prev
&& arc_next_active_insn (prev
, 0) == insn
8564 && ((NONJUMP_INSN_P (prev
) && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
8565 ? CALL_ATTR (as_a
<rtx_sequence
*> (PATTERN (prev
))->insn (0),
8567 : (CALL_ATTR (prev
, NON_SIBCALL
)
8568 && NEXT_INSN (PREV_INSN (prev
)) == prev
)))
8569 force_target
= true;
8574 /* Short BRCC only comes in no-delay-slot version, and without limm */
8579 ilv
->branch_cost
= 1;
8580 ilv
->enabled
= (len
== 2);
8581 ilv
->length_sensitive
= ARC_LS_8
;
8585 case TYPE_BRCC_NO_DELAY_SLOT
:
8586 /* doloop_fallback* patterns are TYPE_BRCC_NO_DELAY_SLOT for
8587 (delay slot) scheduling purposes, but they are longer. */
8588 if (GET_CODE (PATTERN (insn
)) == PARALLEL
8589 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 1)) == SET
)
8591 /* Standard BRCC: 4 bytes, or 8 bytes with limm. */
8592 ilv
->length
= ((type
== TYPE_BRCC
) ? 4 : 8);
8594 ilv
->branch_cost
= branch_align_cost
;
8595 ilv
->enabled
= (len
<= ilv
->length
);
8596 ilv
->length_sensitive
= ARC_LS_9
;
8597 if ((target_p
|| force_target
)
8598 || (!delay_filled
&& TARGET_UNALIGN_BRANCH
))
8604 ilv
->target_cost
= 1;
8605 ilv
->branch_cost
= branch_unalign_cost
;
8610 op
= XEXP (SET_SRC (XVECEXP (PATTERN (insn
), 0, 0)), 0);
8613 if (GET_CODE (op0
) == ZERO_EXTRACT
8614 && satisfies_constraint_L (XEXP (op0
, 2)))
8615 op0
= XEXP (op0
, 0);
8616 if (satisfies_constraint_Rcq (op0
))
8618 ilv
->length
= ((type
== TYPE_BRCC
) ? 6 : 10);
8620 ilv
->branch_cost
= 1 + branch_align_cost
;
8621 ilv
->fallthrough_cost
= 1;
8622 ilv
->enabled
= true;
8623 ilv
->length_sensitive
= ARC_LS_21
;
8624 if (!delay_filled
&& TARGET_UNALIGN_BRANCH
)
8630 ilv
->branch_cost
= 1 + branch_unalign_cost
;
8634 ilv
->length
= ((type
== TYPE_BRCC
) ? 8 : 12);
8636 ilv
->branch_cost
= 1 + branch_align_cost
;
8637 ilv
->fallthrough_cost
= 1;
8638 ilv
->enabled
= true;
8639 ilv
->length_sensitive
= ARC_LS_21
;
8640 if ((target_p
|| force_target
)
8641 || (!delay_filled
&& TARGET_UNALIGN_BRANCH
))
8647 ilv
->target_cost
= 1;
8648 ilv
->branch_cost
= 1 + branch_unalign_cost
;
8656 case TYPE_CALL_NO_DELAY_SLOT
:
8661 ilv
->length_sensitive
8662 = GET_CODE (PATTERN (insn
)) == COND_EXEC
? ARC_LS_21
: ARC_LS_25
;
8665 ilv
->fallthrough_cost
= branch_align_cost
;
8666 ilv
->enabled
= true;
8667 if ((target_p
|| force_target
)
8668 || (!delay_filled
&& TARGET_UNALIGN_BRANCH
))
8674 ilv
->target_cost
= 1;
8675 ilv
->fallthrough_cost
= branch_unalign_cost
;
8679 case TYPE_UNCOND_BRANCH
:
8680 /* Strictly speaking, this should be ARC_LS_10 for equality comparisons,
8681 but that makes no difference at the moment. */
8682 ilv
->length_sensitive
= ARC_LS_7
;
8683 ilv
[1].length_sensitive
= ARC_LS_25
;
8686 ilv
->length_sensitive
= ARC_LS_10
;
8687 ilv
[1].length_sensitive
= ARC_LS_21
;
8691 ilv
->branch_cost
= branch_align_cost
;
8692 ilv
->enabled
= (len
== ilv
->length
);
8696 ilv
->branch_cost
= branch_align_cost
;
8697 ilv
->enabled
= true;
8698 if ((target_p
|| force_target
)
8699 || (!delay_filled
&& TARGET_UNALIGN_BRANCH
))
8705 ilv
->target_cost
= 1;
8706 ilv
->branch_cost
= branch_unalign_cost
;
8713 /* For every short insn, there is generally also a long insn.
8714 trap_s is an exception. */
8715 if ((len
& 2) == 0 || recog_memoized (insn
) == CODE_FOR_trap_s
)
8722 ilv
->length
= len
+ 2;
8724 if (target_p
|| force_target
)
8730 ilv
->target_cost
= 1;
8734 /* If the previous instruction is an sfunc call, this insn is always
8735 a target, even though the middle-end is unaware of this.
8736 Therefore, if we have a call predecessor, transfer the target cost
8737 to the fallthrough and branch costs. */
8740 for (insn_length_variant_t
*p
= first_ilv
; p
< ilv
; p
++)
8742 p
->fallthrough_cost
+= p
->target_cost
;
8743 p
->branch_cost
+= p
->target_cost
;
8748 return ilv
- first_ilv
;
8752 arc_insn_length_parameters (insn_length_parameters_t
*ilp
)
8754 ilp
->align_unit_log
= 1;
8755 ilp
->align_base_log
= 1;
8756 ilp
->max_variants
= 7;
8757 ilp
->get_variants
= arc_get_insn_variants
;
8760 /* Return a copy of COND from *STATEP, inverted if that is indicated by the
8761 CC field of *STATEP. */
8764 arc_get_ccfsm_cond (struct arc_ccfsm
*statep
, bool reverse
)
8766 rtx cond
= statep
->cond
;
8767 int raw_cc
= get_arc_condition_code (cond
);
8769 raw_cc
= ARC_INVERSE_CONDITION_CODE (raw_cc
);
8771 if (statep
->cc
== raw_cc
)
8772 return copy_rtx (cond
);
8774 gcc_assert (ARC_INVERSE_CONDITION_CODE (raw_cc
) == statep
->cc
);
8776 machine_mode ccm
= GET_MODE (XEXP (cond
, 0));
8777 enum rtx_code code
= reverse_condition (GET_CODE (cond
));
8778 if (code
== UNKNOWN
|| ccm
== CC_FP_GTmode
|| ccm
== CC_FP_GEmode
)
8779 code
= reverse_condition_maybe_unordered (GET_CODE (cond
));
8781 return gen_rtx_fmt_ee (code
, GET_MODE (cond
),
8782 copy_rtx (XEXP (cond
, 0)), copy_rtx (XEXP (cond
, 1)));
8785 /* Return version of PAT conditionalized with COND, which is part of INSN.
8786 ANNULLED indicates if INSN is an annulled delay-slot insn.
8787 Register further changes if necessary. */
8789 conditionalize_nonjump (rtx pat
, rtx cond
, rtx insn
, bool annulled
)
8791 /* For commutative operators, we generally prefer to have
8792 the first source match the destination. */
8793 if (GET_CODE (pat
) == SET
)
8795 rtx src
= SET_SRC (pat
);
8797 if (COMMUTATIVE_P (src
))
8799 rtx src0
= XEXP (src
, 0);
8800 rtx src1
= XEXP (src
, 1);
8801 rtx dst
= SET_DEST (pat
);
8803 if (rtx_equal_p (src1
, dst
) && !rtx_equal_p (src0
, dst
)
8804 /* Leave add_n alone - the canonical form is to
8805 have the complex summand first. */
8807 pat
= gen_rtx_SET (dst
,
8808 gen_rtx_fmt_ee (GET_CODE (src
), GET_MODE (src
),
8813 /* dwarf2out.c:dwarf2out_frame_debug_expr doesn't know
8814 what to do with COND_EXEC. */
8815 if (RTX_FRAME_RELATED_P (insn
))
8817 /* If this is the delay slot insn of an anulled branch,
8818 dwarf2out.c:scan_trace understands the anulling semantics
8819 without the COND_EXEC. */
8820 gcc_assert (annulled
);
8821 rtx note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
, pat
,
8823 validate_change (insn
, ®_NOTES (insn
), note
, 1);
8825 pat
= gen_rtx_COND_EXEC (VOIDmode
, cond
, pat
);
8829 /* Use the ccfsm machinery to do if conversion. */
8834 struct arc_ccfsm
*statep
= &cfun
->machine
->ccfsm_current
;
8836 memset (statep
, 0, sizeof *statep
);
8837 for (rtx_insn
*insn
= get_insns (); insn
; insn
= next_insn (insn
))
8839 arc_ccfsm_advance (insn
, statep
);
8841 switch (statep
->state
)
8847 /* Deleted branch. */
8848 arc_ccfsm_post_advance (insn
, statep
);
8849 gcc_assert (!IN_RANGE (statep
->state
, 1, 2));
8850 rtx_insn
*seq
= NEXT_INSN (PREV_INSN (insn
));
8851 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
8853 rtx slot
= XVECEXP (PATTERN (seq
), 0, 1);
8854 rtx pat
= PATTERN (slot
);
8855 if (INSN_ANNULLED_BRANCH_P (insn
))
8858 = arc_get_ccfsm_cond (statep
, INSN_FROM_TARGET_P (slot
));
8859 pat
= gen_rtx_COND_EXEC (VOIDmode
, cond
, pat
);
8861 if (!validate_change (seq
, &PATTERN (seq
), pat
, 0))
8863 PUT_CODE (slot
, NOTE
);
8864 NOTE_KIND (slot
) = NOTE_INSN_DELETED
;
8868 set_insn_deleted (insn
);
8874 && statep
->target_label
== CODE_LABEL_NUMBER (insn
))
8876 arc_ccfsm_post_advance (insn
, statep
);
8877 if (--LABEL_NUSES (insn
) == 0)
8883 if (!NONDEBUG_INSN_P (insn
))
8886 /* Conditionalized insn. */
8888 rtx_insn
*prev
, *pprev
;
8889 rtx
*patp
, pat
, cond
;
8890 bool annulled
; annulled
= false;
8892 /* If this is a delay slot insn in a non-annulled branch,
8893 don't conditionalize it. N.B., this should be fine for
8894 conditional return too. However, don't do this for
8895 unconditional branches, as these would be encountered when
8896 processing an 'else' part. */
8897 prev
= PREV_INSN (insn
);
8898 pprev
= PREV_INSN (prev
);
8899 if (pprev
&& NEXT_INSN (NEXT_INSN (pprev
)) == NEXT_INSN (insn
)
8900 && JUMP_P (prev
) && get_attr_cond (prev
) == COND_USE
)
8902 if (!INSN_ANNULLED_BRANCH_P (prev
))
8907 patp
= &PATTERN (insn
);
8909 cond
= arc_get_ccfsm_cond (statep
, INSN_FROM_TARGET_P (insn
));
8910 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8912 /* ??? don't conditionalize if all side effects are dead
8913 in the not-execute case. */
8915 pat
= conditionalize_nonjump (pat
, cond
, insn
, annulled
);
8917 else if (simplejump_p (insn
))
8919 patp
= &SET_SRC (pat
);
8920 pat
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, *patp
, pc_rtx
);
8922 else if (JUMP_P (insn
) && ANY_RETURN_P (PATTERN (insn
)))
8924 pat
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, pat
, pc_rtx
);
8925 pat
= gen_rtx_SET (pc_rtx
, pat
);
8929 validate_change (insn
, patp
, pat
, 1);
8930 if (!apply_change_group ())
8934 rtx_insn
*next
= next_nonnote_insn (insn
);
8935 if (GET_CODE (next
) == BARRIER
)
8937 if (statep
->state
== 3)
8944 arc_ccfsm_post_advance (insn
, statep
);
8949 /* Find annulled delay insns and convert them to use the appropriate predicate.
8950 This allows branch shortening to size up these insns properly. */
8953 arc_predicate_delay_insns (void)
8955 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8957 rtx pat
, jump
, dlay
, src
, cond
, *patp
;
8960 if (!NONJUMP_INSN_P (insn
)
8961 || GET_CODE (pat
= PATTERN (insn
)) != SEQUENCE
)
8963 jump
= XVECEXP (pat
, 0, 0);
8964 dlay
= XVECEXP (pat
, 0, 1);
8965 if (!JUMP_P (jump
) || !INSN_ANNULLED_BRANCH_P (jump
))
8967 /* If the branch insn does the annulling, leave the delay insn alone. */
8968 if (!TARGET_AT_DBR_CONDEXEC
&& !INSN_FROM_TARGET_P (dlay
))
8970 /* ??? Could also leave DLAY un-conditionalized if its target is dead
8971 on the other path. */
8972 gcc_assert (GET_CODE (PATTERN (jump
)) == SET
);
8973 gcc_assert (SET_DEST (PATTERN (jump
)) == pc_rtx
);
8974 src
= SET_SRC (PATTERN (jump
));
8975 gcc_assert (GET_CODE (src
) == IF_THEN_ELSE
);
8976 cond
= XEXP (src
, 0);
8977 if (XEXP (src
, 2) == pc_rtx
)
8979 else if (XEXP (src
, 1) == pc_rtx
)
8983 if (reverse
!= !INSN_FROM_TARGET_P (dlay
))
8985 machine_mode ccm
= GET_MODE (XEXP (cond
, 0));
8986 enum rtx_code code
= reverse_condition (GET_CODE (cond
));
8987 if (code
== UNKNOWN
|| ccm
== CC_FP_GTmode
|| ccm
== CC_FP_GEmode
)
8988 code
= reverse_condition_maybe_unordered (GET_CODE (cond
));
8990 cond
= gen_rtx_fmt_ee (code
, GET_MODE (cond
),
8991 copy_rtx (XEXP (cond
, 0)),
8992 copy_rtx (XEXP (cond
, 1)));
8995 cond
= copy_rtx (cond
);
8996 patp
= &PATTERN (dlay
);
8998 pat
= conditionalize_nonjump (pat
, cond
, dlay
, true);
8999 validate_change (dlay
, patp
, pat
, 1);
9000 if (!apply_change_group ())
9006 /* For ARC600: If a write to a core reg >=32 appears in a delay slot
9007 (other than of a forward brcc), it creates a hazard when there is a read
9008 of the same register at the branch target. We can't know what is at the
9009 branch target of calls, and for branches, we don't really know before the
9010 end of delay slot scheduling, either. Not only can individual instruction
9011 be hoisted out into a delay slot, a basic block can also be emptied this
9012 way, and branch and/or fall through targets be redirected. Hence we don't
9013 want such writes in a delay slot. */
9015 /* Return nonzreo iff INSN writes to an extension core register. */
9018 arc_write_ext_corereg (rtx insn
)
9020 subrtx_iterator::array_type array
;
9021 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
9023 const_rtx x
= *iter
;
9024 switch (GET_CODE (x
))
9026 case SET
: case POST_INC
: case POST_DEC
: case PRE_INC
: case PRE_DEC
:
9029 /* This is also fine for PRE/POST_MODIFY, because they
9033 const_rtx dest
= XEXP (x
, 0);
9034 if (REG_P (dest
) && REGNO (dest
) >= 32 && REGNO (dest
) < 61)
9040 /* This is like the hook, but returns NULL when it can't / won't generate
9041 a legitimate address. */
9044 arc_legitimize_address_0 (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
9049 if (flag_pic
&& SYMBOLIC_CONST (x
))
9050 (x
) = arc_legitimize_pic_address (x
, 0);
9052 if (GET_CODE (addr
) == CONST
)
9053 addr
= XEXP (addr
, 0);
9054 if (GET_CODE (addr
) == PLUS
9055 && CONST_INT_P (XEXP (addr
, 1))
9056 && ((GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
9057 && !SYMBOL_REF_FUNCTION_P (XEXP (addr
, 0)))
9058 || (REG_P (XEXP (addr
, 0))
9059 && (INTVAL (XEXP (addr
, 1)) & 252))))
9061 HOST_WIDE_INT offs
, upper
;
9062 int size
= GET_MODE_SIZE (mode
);
9064 offs
= INTVAL (XEXP (addr
, 1));
9065 upper
= (offs
+ 256 * size
) & ~511 * size
;
9066 inner
= plus_constant (Pmode
, XEXP (addr
, 0), upper
);
9067 #if 0 /* ??? this produces worse code for EEMBC idctrn01 */
9068 if (GET_CODE (x
) == CONST
)
9069 inner
= gen_rtx_CONST (Pmode
, inner
);
9071 addr
= plus_constant (Pmode
, force_reg (Pmode
, inner
), offs
- upper
);
9074 else if (GET_CODE (addr
) == SYMBOL_REF
&& !SYMBOL_REF_FUNCTION_P (addr
))
9075 x
= force_reg (Pmode
, x
);
9076 if (memory_address_p ((machine_mode
) mode
, x
))
9082 arc_legitimize_address (rtx orig_x
, rtx oldx
, machine_mode mode
)
9084 if (GET_CODE (orig_x
) == SYMBOL_REF
)
9086 enum tls_model model
= SYMBOL_REF_TLS_MODEL (orig_x
);
9088 return arc_legitimize_tls_address (orig_x
, model
);
9091 rtx new_x
= arc_legitimize_address_0 (orig_x
, oldx
, mode
);
9099 arc_delegitimize_address_0 (rtx x
)
9103 if (GET_CODE (x
) == CONST
&& GET_CODE (u
= XEXP (x
, 0)) == UNSPEC
)
9105 if (XINT (u
, 1) == ARC_UNSPEC_GOT
9106 || XINT (u
, 1) == ARC_UNSPEC_GOTOFFPC
)
9107 return XVECEXP (u
, 0, 0);
9109 else if (GET_CODE (x
) == CONST
&& GET_CODE (p
= XEXP (x
, 0)) == PLUS
9110 && GET_CODE (u
= XEXP (p
, 0)) == UNSPEC
9111 && (XINT (u
, 1) == ARC_UNSPEC_GOT
9112 || XINT (u
, 1) == ARC_UNSPEC_GOTOFFPC
))
9113 return gen_rtx_CONST
9115 gen_rtx_PLUS (GET_MODE (p
), XVECEXP (u
, 0, 0), XEXP (p
, 1)));
9116 else if (GET_CODE (x
) == PLUS
9117 && ((REG_P (gp
= XEXP (x
, 0))
9118 && REGNO (gp
) == PIC_OFFSET_TABLE_REGNUM
)
9119 || (GET_CODE (gp
) == CONST
9120 && GET_CODE (u
= XEXP (gp
, 0)) == UNSPEC
9121 && XINT (u
, 1) == ARC_UNSPEC_GOT
9122 && GET_CODE (XVECEXP (u
, 0, 0)) == SYMBOL_REF
9123 && !strcmp (XSTR (XVECEXP (u
, 0, 0), 0), "_DYNAMIC")))
9124 && GET_CODE (XEXP (x
, 1)) == CONST
9125 && GET_CODE (u
= XEXP (XEXP (x
, 1), 0)) == UNSPEC
9126 && XINT (u
, 1) == ARC_UNSPEC_GOTOFF
)
9127 return XVECEXP (u
, 0, 0);
9128 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
9129 && ((REG_P (gp
= XEXP (XEXP (x
, 0), 1))
9130 && REGNO (gp
) == PIC_OFFSET_TABLE_REGNUM
)
9131 || (GET_CODE (gp
) == CONST
9132 && GET_CODE (u
= XEXP (gp
, 0)) == UNSPEC
9133 && XINT (u
, 1) == ARC_UNSPEC_GOT
9134 && GET_CODE (XVECEXP (u
, 0, 0)) == SYMBOL_REF
9135 && !strcmp (XSTR (XVECEXP (u
, 0, 0), 0), "_DYNAMIC")))
9136 && GET_CODE (XEXP (x
, 1)) == CONST
9137 && GET_CODE (u
= XEXP (XEXP (x
, 1), 0)) == UNSPEC
9138 && XINT (u
, 1) == ARC_UNSPEC_GOTOFF
)
9139 return gen_rtx_PLUS (GET_MODE (x
), XEXP (XEXP (x
, 0), 0),
9141 else if (GET_CODE (x
) == PLUS
9142 && (u
= arc_delegitimize_address_0 (XEXP (x
, 1))))
9143 return gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0), u
);
9148 arc_delegitimize_address (rtx x
)
9150 rtx orig_x
= x
= delegitimize_mem_from_attrs (x
);
9151 if (GET_CODE (x
) == MEM
)
9153 x
= arc_delegitimize_address_0 (x
);
9157 x
= replace_equiv_address_nv (orig_x
, x
);
9163 /* Return a REG rtx for acc1. N.B. the gcc-internal representation may
9164 differ from the hardware register number in order to allow the generic
9165 code to correctly split the concatenation of acc1 and acc2. */
9170 return gen_rtx_REG (SImode
, TARGET_BIG_ENDIAN
? 56: 57);
9173 /* Return a REG rtx for acc2. N.B. the gcc-internal representation may
9174 differ from the hardware register number in order to allow the generic
9175 code to correctly split the concatenation of acc1 and acc2. */
9180 return gen_rtx_REG (SImode
, TARGET_BIG_ENDIAN
? 57: 56);
9183 /* Return a REG rtx for mlo. N.B. the gcc-internal representation may
9184 differ from the hardware register number in order to allow the generic
9185 code to correctly split the concatenation of mhi and mlo. */
9190 return gen_rtx_REG (SImode
, TARGET_BIG_ENDIAN
? 59: 58);
9193 /* Return a REG rtx for mhi. N.B. the gcc-internal representation may
9194 differ from the hardware register number in order to allow the generic
9195 code to correctly split the concatenation of mhi and mlo. */
9200 return gen_rtx_REG (SImode
, TARGET_BIG_ENDIAN
? 58: 59);
9203 /* FIXME: a parameter should be added, and code added to final.c,
9204 to reproduce this functionality in shorten_branches. */
9206 /* Return nonzero iff BRANCH should be unaligned if possible by upsizing
9207 a previous instruction. */
9209 arc_unalign_branch_p (rtx branch
)
9213 if (!TARGET_UNALIGN_BRANCH
)
9215 /* Do not do this if we have a filled delay slot. */
9216 if (get_attr_delay_slot_filled (branch
) == DELAY_SLOT_FILLED_YES
9217 && !NEXT_INSN (branch
)->deleted ())
9219 note
= find_reg_note (branch
, REG_BR_PROB
, 0);
9221 || (arc_unalign_prob_threshold
&& !br_prob_note_reliable_p (note
))
9222 || INTVAL (XEXP (note
, 0)) < arc_unalign_prob_threshold
);
9226 /* When estimating sizes during arc_reorg, when optimizing for speed, there
9227 are three reasons why we need to consider branches to be length 6:
9228 - annull-false delay slot insns are implemented using conditional execution,
9229 thus preventing short insn formation where used.
9230 - for ARC600: annul-true delay slot insns are implemented where possible
9231 using conditional execution, preventing short insn formation where used.
9232 - for ARC700: likely or somewhat likely taken branches are made long and
9233 unaligned if possible to avoid branch penalty. */
9236 arc_branch_size_unknown_p (void)
9238 return !optimize_size
&& arc_reorg_in_progress
;
9241 /* We are about to output a return insn. Add padding if necessary to avoid
9242 a mispredict. A return could happen immediately after the function
9243 start, but after a call we know that there will be at least a blink
9247 arc_pad_return (void)
9249 rtx_insn
*insn
= current_output_insn
;
9250 rtx_insn
*prev
= prev_active_insn (insn
);
9255 fputs ("\tnop_s\n", asm_out_file
);
9256 cfun
->machine
->unalign
^= 2;
9259 /* If PREV is a sequence, we know it must be a branch / jump or a tailcall,
9260 because after a call, we'd have to restore blink first. */
9261 else if (GET_CODE (PATTERN (prev
)) == SEQUENCE
)
9265 want_long
= (get_attr_length (prev
) == 2);
9266 prev
= prev_active_insn (prev
);
9269 || ((NONJUMP_INSN_P (prev
) && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
9270 ? CALL_ATTR (as_a
<rtx_sequence
*> (PATTERN (prev
))->insn (0),
9272 : CALL_ATTR (prev
, NON_SIBCALL
)))
9275 cfun
->machine
->size_reason
9276 = "call/return and return/return must be 6 bytes apart to avoid mispredict";
9277 else if (TARGET_UNALIGN_BRANCH
&& cfun
->machine
->unalign
)
9279 cfun
->machine
->size_reason
9280 = "Long unaligned jump avoids non-delay slot penalty";
9283 /* Disgorge delay insn, if there is any, and it may be moved. */
9285 /* ??? Annulled would be OK if we can and do conditionalize
9286 the delay slot insn accordingly. */
9287 && !INSN_ANNULLED_BRANCH_P (insn
)
9288 && (get_attr_cond (insn
) != COND_USE
9289 || !reg_set_p (gen_rtx_REG (CCmode
, CC_REG
),
9290 XVECEXP (final_sequence
, 0, 1))))
9292 prev
= as_a
<rtx_insn
*> (XVECEXP (final_sequence
, 0, 1));
9293 gcc_assert (!prev_real_insn (insn
)
9294 || !arc_hazard (prev_real_insn (insn
), prev
));
9295 cfun
->machine
->force_short_suffix
= !want_long
;
9296 rtx save_pred
= current_insn_predicate
;
9297 final_scan_insn (prev
, asm_out_file
, optimize
, 1, NULL
);
9298 cfun
->machine
->force_short_suffix
= -1;
9299 prev
->set_deleted ();
9300 current_output_insn
= insn
;
9301 current_insn_predicate
= save_pred
;
9304 fputs ("\tnop\n", asm_out_file
);
9307 fputs ("\tnop_s\n", asm_out_file
);
9308 cfun
->machine
->unalign
^= 2;
9314 /* The usual; we set up our machine_function data. */
9316 static struct machine_function
*
9317 arc_init_machine_status (void)
9319 struct machine_function
*machine
;
9320 machine
= ggc_cleared_alloc
<machine_function
> ();
9321 machine
->fn_type
= ARC_FUNCTION_UNKNOWN
;
9322 machine
->force_short_suffix
= -1;
9327 /* Implements INIT_EXPANDERS. We just set up to call the above
9331 arc_init_expanders (void)
9333 init_machine_status
= arc_init_machine_status
;
9336 /* Check if OP is a proper parallel of a millicode call pattern. OFFSET
9337 indicates a number of elements to ignore - that allows to have a
9338 sibcall pattern that starts with (return). LOAD_P is zero for store
9339 multiple (for prologues), and one for load multiples (for epilogues),
9340 and two for load multiples where no final clobber of blink is required.
9341 We also skip the first load / store element since this is supposed to
9342 be checked in the instruction pattern. */
9345 arc_check_millicode (rtx op
, int offset
, int load_p
)
9347 int len
= XVECLEN (op
, 0) - offset
;
9352 if (len
< 2 || len
> 13)
9358 rtx elt
= XVECEXP (op
, 0, --len
);
9360 if (GET_CODE (elt
) != CLOBBER
9361 || !REG_P (XEXP (elt
, 0))
9362 || REGNO (XEXP (elt
, 0)) != RETURN_ADDR_REGNUM
9363 || len
< 3 || len
> 13)
9366 for (i
= 1; i
< len
; i
++)
9368 rtx elt
= XVECEXP (op
, 0, i
+ offset
);
9371 if (GET_CODE (elt
) != SET
)
9373 mem
= XEXP (elt
, load_p
);
9374 reg
= XEXP (elt
, 1-load_p
);
9375 if (!REG_P (reg
) || REGNO (reg
) != 13U+i
|| !MEM_P (mem
))
9377 addr
= XEXP (mem
, 0);
9378 if (GET_CODE (addr
) != PLUS
9379 || !rtx_equal_p (stack_pointer_rtx
, XEXP (addr
, 0))
9380 || !CONST_INT_P (XEXP (addr
, 1)) || INTVAL (XEXP (addr
, 1)) != i
*4)
9386 /* Accessor functions for cfun->machine->unalign. */
9389 arc_get_unalign (void)
9391 return cfun
->machine
->unalign
;
9395 arc_clear_unalign (void)
9398 cfun
->machine
->unalign
= 0;
9402 arc_toggle_unalign (void)
9404 cfun
->machine
->unalign
^= 2;
9407 /* Operands 0..2 are the operands of a addsi which uses a 12 bit
9408 constant in operand 2, but which would require a LIMM because of
9410 operands 3 and 4 are new SET_SRCs for operands 0. */
9413 split_addsi (rtx
*operands
)
9415 int val
= INTVAL (operands
[2]);
9417 /* Try for two short insns first. Lengths being equal, we prefer
9418 expansions with shorter register lifetimes. */
9419 if (val
> 127 && val
<= 255
9420 && satisfies_constraint_Rcq (operands
[0]))
9422 operands
[3] = operands
[2];
9423 operands
[4] = gen_rtx_PLUS (SImode
, operands
[0], operands
[1]);
9427 operands
[3] = operands
[1];
9428 operands
[4] = gen_rtx_PLUS (SImode
, operands
[0], operands
[2]);
9432 /* Operands 0..2 are the operands of a subsi which uses a 12 bit
9433 constant in operand 1, but which would require a LIMM because of
9435 operands 3 and 4 are new SET_SRCs for operands 0. */
9438 split_subsi (rtx
*operands
)
9440 int val
= INTVAL (operands
[1]);
9442 /* Try for two short insns first. Lengths being equal, we prefer
9443 expansions with shorter register lifetimes. */
9444 if (satisfies_constraint_Rcq (operands
[0])
9445 && satisfies_constraint_Rcq (operands
[2]))
9447 if (val
>= -31 && val
<= 127)
9449 operands
[3] = gen_rtx_NEG (SImode
, operands
[2]);
9450 operands
[4] = gen_rtx_PLUS (SImode
, operands
[0], operands
[1]);
9453 else if (val
>= 0 && val
< 255)
9455 operands
[3] = operands
[1];
9456 operands
[4] = gen_rtx_MINUS (SImode
, operands
[0], operands
[2]);
9460 /* If the destination is not an ARCompact16 register, we might
9461 still have a chance to make a short insn if the source is;
9462 we need to start with a reg-reg move for this. */
9463 operands
[3] = operands
[2];
9464 operands
[4] = gen_rtx_MINUS (SImode
, operands
[1], operands
[0]);
9467 /* Handle DOUBLE_REGS uses.
9468 Operand 0: destination register
9469 Operand 1: source register */
9472 arc_process_double_reg_moves (rtx
*operands
)
9474 rtx dest
= operands
[0];
9475 rtx src
= operands
[1];
9477 enum usesDxState
{ none
, srcDx
, destDx
, maxDx
};
9478 enum usesDxState state
= none
;
9480 if (refers_to_regno_p (40, 44, src
, 0))
9482 if (refers_to_regno_p (40, 44, dest
, 0))
9484 /* Via arc_register_move_cost, we should never see D,D moves. */
9485 gcc_assert (state
== none
);
9494 /* Without the LR insn, we need to split this into a
9495 sequence of insns which will use the DEXCLx and DADDHxy
9496 insns to be able to read the Dx register in question. */
9497 if (TARGET_DPFP_DISABLE_LRSR
)
9499 /* gen *movdf_insn_nolrsr */
9500 rtx set
= gen_rtx_SET (dest
, src
);
9501 rtx use1
= gen_rtx_USE (VOIDmode
, const1_rtx
);
9502 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, use1
)));
9506 /* When we have 'mov D, r' or 'mov D, D' then get the target
9507 register pair for use with LR insn. */
9508 rtx destHigh
= simplify_gen_subreg (SImode
, dest
, DFmode
,
9509 TARGET_BIG_ENDIAN
? 0 : 4);
9510 rtx destLow
= simplify_gen_subreg (SImode
, dest
, DFmode
,
9511 TARGET_BIG_ENDIAN
? 4 : 0);
9513 /* Produce the two LR insns to get the high and low parts. */
9514 emit_insn (gen_rtx_SET (destHigh
,
9515 gen_rtx_UNSPEC_VOLATILE (Pmode
,
9517 VUNSPEC_ARC_LR_HIGH
)));
9518 emit_insn (gen_rtx_SET (destLow
,
9519 gen_rtx_UNSPEC_VOLATILE (Pmode
,
9524 else if (state
== destDx
)
9526 /* When we have 'mov r, D' or 'mov D, D' and we have access to the
9527 LR insn get the target register pair. */
9528 rtx srcHigh
= simplify_gen_subreg (SImode
, src
, DFmode
,
9529 TARGET_BIG_ENDIAN
? 0 : 4);
9530 rtx srcLow
= simplify_gen_subreg (SImode
, src
, DFmode
,
9531 TARGET_BIG_ENDIAN
? 4 : 0);
9533 emit_insn (gen_dexcl_2op (dest
, srcHigh
, srcLow
));
9541 /* operands 0..1 are the operands of a 64 bit move instruction.
9542 split it into two moves with operands 2/3 and 4/5. */
9545 arc_split_move (rtx
*operands
)
9547 machine_mode mode
= GET_MODE (operands
[0]);
9554 if (arc_process_double_reg_moves (operands
))
9559 && ((memory_operand (operands
[0], mode
)
9560 && even_register_operand (operands
[1], mode
))
9561 || (memory_operand (operands
[1], mode
)
9562 && even_register_operand (operands
[0], mode
))))
9564 emit_move_insn (operands
[0], operands
[1]);
9568 if (TARGET_PLUS_QMACW
9569 && GET_CODE (operands
[1]) == CONST_VECTOR
)
9571 HOST_WIDE_INT intval0
, intval1
;
9572 if (GET_MODE (operands
[1]) == V2SImode
)
9574 intval0
= INTVAL (XVECEXP (operands
[1], 0, 0));
9575 intval1
= INTVAL (XVECEXP (operands
[1], 0, 1));
9579 intval1
= INTVAL (XVECEXP (operands
[1], 0, 3)) << 16;
9580 intval1
|= INTVAL (XVECEXP (operands
[1], 0, 2)) & 0xFFFF;
9581 intval0
= INTVAL (XVECEXP (operands
[1], 0, 1)) << 16;
9582 intval0
|= INTVAL (XVECEXP (operands
[1], 0, 0)) & 0xFFFF;
9584 xop
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]));
9585 xop
[3] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
9586 xop
[2] = GEN_INT (trunc_int_for_mode (intval0
, SImode
));
9587 xop
[1] = GEN_INT (trunc_int_for_mode (intval1
, SImode
));
9588 emit_move_insn (xop
[0], xop
[2]);
9589 emit_move_insn (xop
[3], xop
[1]);
9593 for (i
= 0; i
< 2; i
++)
9595 if (MEM_P (operands
[i
]) && auto_inc_p (XEXP (operands
[i
], 0)))
9597 rtx addr
= XEXP (operands
[i
], 0);
9601 gcc_assert (!reg_overlap_mentioned_p (operands
[0], addr
));
9602 switch (GET_CODE (addr
))
9604 case PRE_DEC
: o
= GEN_INT (-8); goto pre_modify
;
9605 case PRE_INC
: o
= GEN_INT (8); goto pre_modify
;
9606 case PRE_MODIFY
: o
= XEXP (XEXP (addr
, 1), 1);
9610 case POST_DEC
: o
= GEN_INT (-8); goto post_modify
;
9611 case POST_INC
: o
= GEN_INT (8); goto post_modify
;
9612 case POST_MODIFY
: o
= XEXP (XEXP (addr
, 1), 1);
9621 xop
[0+i
] = adjust_automodify_address_nv
9622 (operands
[i
], SImode
,
9623 gen_rtx_fmt_ee (code
, Pmode
, r
,
9624 gen_rtx_PLUS (Pmode
, r
, o
)),
9626 xop
[2+i
] = adjust_automodify_address_nv
9627 (operands
[i
], SImode
, plus_constant (Pmode
, r
, 4), 4);
9631 xop
[0+i
] = operand_subword (operands
[i
], 0, 0, mode
);
9632 xop
[2+i
] = operand_subword (operands
[i
], 1, 0, mode
);
9635 if (reg_overlap_mentioned_p (xop
[0], xop
[3]))
9638 gcc_assert (!reg_overlap_mentioned_p (xop
[2], xop
[1]));
9641 emit_move_insn (xop
[0 + swap
], xop
[1 + swap
]);
9642 emit_move_insn (xop
[2 - swap
], xop
[3 - swap
]);
9646 /* Select between the instruction output templates s_tmpl (for short INSNs)
9647 and l_tmpl (for long INSNs). */
9650 arc_short_long (rtx_insn
*insn
, const char *s_tmpl
, const char *l_tmpl
)
9652 int is_short
= arc_verify_short (insn
, cfun
->machine
->unalign
, -1);
9654 extract_constrain_insn_cached (insn
);
9655 return is_short
? s_tmpl
: l_tmpl
;
9658 /* Searches X for any reference to REGNO, returning the rtx of the
9659 reference found if any. Otherwise, returns NULL_RTX. */
9662 arc_regno_use_in (unsigned int regno
, rtx x
)
9668 if (REG_P (x
) && refers_to_regno_p (regno
, x
))
9671 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
9672 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
9676 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
9679 else if (fmt
[i
] == 'E')
9680 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9681 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
9688 /* Return the integer value of the "type" attribute for INSN, or -1 if
9689 INSN can't have attributes. */
9692 arc_attr_type (rtx_insn
*insn
)
9694 if (NONJUMP_INSN_P (insn
)
9695 ? (GET_CODE (PATTERN (insn
)) == USE
9696 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
9698 ? (GET_CODE (PATTERN (insn
)) == ADDR_VEC
9699 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
)
9702 return get_attr_type (insn
);
9705 /* Return true if insn sets the condition codes. */
9708 arc_sets_cc_p (rtx_insn
*insn
)
9710 if (NONJUMP_INSN_P (insn
))
9711 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
9712 insn
= seq
->insn (seq
->len () - 1);
9713 return arc_attr_type (insn
) == TYPE_COMPARE
;
9716 /* Return true if INSN is an instruction with a delay slot we may want
9720 arc_need_delay (rtx_insn
*insn
)
9724 if (!flag_delayed_branch
)
9726 /* The return at the end of a function needs a delay slot. */
9727 if (NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
9728 && (!(next
= next_active_insn (insn
))
9729 || ((!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) != SEQUENCE
)
9730 && arc_attr_type (next
) == TYPE_RETURN
))
9731 && (!TARGET_PAD_RETURN
9732 || (prev_active_insn (insn
)
9733 && prev_active_insn (prev_active_insn (insn
))
9734 && prev_active_insn (prev_active_insn (prev_active_insn (insn
))))))
9736 if (NONJUMP_INSN_P (insn
)
9737 ? (GET_CODE (PATTERN (insn
)) == USE
9738 || GET_CODE (PATTERN (insn
)) == CLOBBER
9739 || GET_CODE (PATTERN (insn
)) == SEQUENCE
)
9741 ? (GET_CODE (PATTERN (insn
)) == ADDR_VEC
9742 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
)
9745 return num_delay_slots (insn
) != 0;
9748 /* Return true if the scheduling pass(es) has/have already run,
9749 i.e. where possible, we should try to mitigate high latencies
9750 by different instruction selection. */
9753 arc_scheduling_not_expected (void)
9755 return cfun
->machine
->arc_reorg_started
;
9758 /* Oddly enough, sometimes we get a zero overhead loop that branch
9759 shortening doesn't think is a loop - observed with compile/pr24883.c
9760 -O3 -fomit-frame-pointer -funroll-loops. Make sure to include the
9761 alignment visible for branch shortening (we actually align the loop
9762 insn before it, but that is equivalent since the loop insn is 4 byte
9766 arc_label_align (rtx_insn
*label
)
9768 int loop_align
= LOOP_ALIGN (LABEL
);
9770 if (loop_align
> align_labels_log
)
9772 rtx_insn
*prev
= prev_nonnote_insn (label
);
9774 if (prev
&& NONJUMP_INSN_P (prev
)
9775 && GET_CODE (PATTERN (prev
)) == PARALLEL
9776 && recog_memoized (prev
) == CODE_FOR_doloop_begin_i
)
9779 /* Code has a minimum p2 alignment of 1, which we must restore after an
9781 if (align_labels_log
< 1)
9783 rtx_insn
*next
= next_nonnote_nondebug_insn (label
);
9784 if (INSN_P (next
) && recog_memoized (next
) >= 0)
9787 return align_labels_log
;
9790 /* Return true if LABEL is in executable code. */
9793 arc_text_label (rtx_insn
*label
)
9797 /* ??? We use deleted labels like they were still there, see
9798 gcc.c-torture/compile/20000326-2.c . */
9799 gcc_assert (GET_CODE (label
) == CODE_LABEL
9800 || (GET_CODE (label
) == NOTE
9801 && NOTE_KIND (label
) == NOTE_INSN_DELETED_LABEL
));
9802 next
= next_nonnote_insn (label
);
9804 return (!JUMP_TABLE_DATA_P (next
)
9805 || GET_CODE (PATTERN (next
)) != ADDR_VEC
);
9806 else if (!PREV_INSN (label
))
9807 /* ??? sometimes text labels get inserted very late, see
9808 gcc.dg/torture/stackalign/comp-goto-1.c */
9813 /* Without this, gcc.dg/tree-prof/bb-reorg.c fails to assemble
9814 when compiling with -O2 -freorder-blocks-and-partition -fprofile-use
9815 -D_PROFILE_USE; delay branch scheduling then follows a crossing jump
9816 to redirect two breqs. */
9819 arc_can_follow_jump (const rtx_insn
*follower
, const rtx_insn
*followee
)
9821 /* ??? get_attr_type is declared to take an rtx. */
9822 union { const rtx_insn
*c
; rtx_insn
*r
; } u
;
9825 if (CROSSING_JUMP_P (followee
))
9826 switch (get_attr_type (u
.r
))
9829 if (get_attr_length (u
.r
) != 2)
9832 case TYPE_BRCC_NO_DELAY_SLOT
:
9840 /* Return the register number of the register holding the return address
9841 for a function of type TYPE. */
9844 arc_return_address_register (unsigned int fn_type
)
9848 if (ARC_INTERRUPT_P (fn_type
))
9850 if (((fn_type
& ARC_FUNCTION_ILINK1
) | ARC_FUNCTION_FIRQ
) != 0)
9851 regno
= ILINK1_REGNUM
;
9852 else if ((fn_type
& ARC_FUNCTION_ILINK2
) != 0)
9853 regno
= ILINK2_REGNUM
;
9857 else if (ARC_NORMAL_P (fn_type
) || ARC_NAKED_P (fn_type
))
9858 regno
= RETURN_ADDR_REGNUM
;
9860 gcc_assert (regno
!= 0);
9864 /* Implement EPILOGUE_USES.
9865 Return true if REGNO should be added to the deemed uses of the epilogue.
9867 We have to make sure all the register restore instructions are
9868 known to be live in interrupt functions, plus the blink register if
9869 it is clobbered by the isr. */
9872 arc_epilogue_uses (int regno
)
9874 unsigned int fn_type
;
9876 if (regno
== arc_tp_regno
)
9879 fn_type
= arc_compute_function_type (cfun
);
9880 if (reload_completed
)
9882 if (ARC_INTERRUPT_P (cfun
->machine
->fn_type
))
9884 if (!fixed_regs
[regno
])
9886 return ((regno
== arc_return_address_register (fn_type
))
9887 || (regno
== RETURN_ADDR_REGNUM
));
9890 return regno
== RETURN_ADDR_REGNUM
;
9893 return regno
== arc_return_address_register (fn_type
);
9896 /* Helper for EH_USES macro. */
9899 arc_eh_uses (int regno
)
9901 if (regno
== arc_tp_regno
)
9906 #ifndef TARGET_NO_LRA
9907 #define TARGET_NO_LRA !TARGET_LRA
9913 return !TARGET_NO_LRA
;
9916 /* ??? Should we define TARGET_REGISTER_PRIORITY? We might perfer to use
9917 Rcq registers, because some insn are shorter with them. OTOH we already
9918 have separate alternatives for this purpose, and other insns don't
9919 mind, so maybe we should rather prefer the other registers?
9920 We need more data, and we can only get that if we allow people to
9923 arc_register_priority (int r
)
9925 switch (arc_lra_priority_tag
)
9927 case ARC_LRA_PRIORITY_NONE
:
9929 case ARC_LRA_PRIORITY_NONCOMPACT
:
9930 return ((((r
& 7) ^ 4) - 4) & 15) != r
;
9931 case ARC_LRA_PRIORITY_COMPACT
:
9932 return ((((r
& 7) ^ 4) - 4) & 15) == r
;
9939 arc_spill_class (reg_class_t
/* orig_class */, machine_mode
)
9941 return GENERAL_REGS
;
9945 arc_legitimize_reload_address (rtx
*p
, machine_mode mode
, int opnum
,
9949 enum reload_type type
= (enum reload_type
) itype
;
9951 if (GET_CODE (x
) == PLUS
9952 && CONST_INT_P (XEXP (x
, 1))
9953 && (RTX_OK_FOR_BASE_P (XEXP (x
, 0), true)
9954 || (REG_P (XEXP (x
, 0))
9955 && reg_equiv_constant (REGNO (XEXP (x
, 0))))))
9957 int scale
= GET_MODE_SIZE (mode
);
9959 rtx index_rtx
= XEXP (x
, 1);
9960 HOST_WIDE_INT offset
= INTVAL (index_rtx
), offset_base
;
9965 if ((scale
-1) & offset
)
9969 = ((offset
+ (256 << shift
))
9970 & ((HOST_WIDE_INT
)((unsigned HOST_WIDE_INT
) -512 << shift
)));
9971 /* Sometimes the normal form does not suit DImode. We
9972 could avoid that by using smaller ranges, but that
9973 would give less optimized code when SImode is
9975 if (GET_MODE_SIZE (mode
) + offset
- offset_base
<= (256 << shift
))
9980 regno
= REGNO (reg
);
9981 sum2
= sum
= plus_constant (Pmode
, reg
, offset_base
);
9983 if (reg_equiv_constant (regno
))
9985 sum2
= plus_constant (Pmode
, reg_equiv_constant (regno
),
9987 if (GET_CODE (sum2
) == PLUS
)
9988 sum2
= gen_rtx_CONST (Pmode
, sum2
);
9990 *p
= gen_rtx_PLUS (Pmode
, sum
, GEN_INT (offset
- offset_base
));
9991 push_reload (sum2
, NULL_RTX
, &XEXP (*p
, 0), NULL
,
9992 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
,
9997 /* We must re-recognize what we created before. */
9998 else if (GET_CODE (x
) == PLUS
9999 && GET_CODE (XEXP (x
, 0)) == PLUS
10000 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
10001 && REG_P (XEXP (XEXP (x
, 0), 0))
10002 && CONST_INT_P (XEXP (x
, 1)))
10004 /* Because this address is so complex, we know it must have
10005 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
10006 it is already unshared, and needs no further unsharing. */
10007 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
10008 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10014 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
10017 arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
10018 unsigned int align
,
10019 enum by_pieces_operation op
,
10022 /* Let the movmem expander handle small block moves. */
10023 if (op
== MOVE_BY_PIECES
)
10026 return default_use_by_pieces_infrastructure_p (size
, align
, op
, speed_p
);
10029 /* Emit a (pre) memory barrier around an atomic sequence according to
10033 arc_pre_atomic_barrier (enum memmodel model
)
10035 if (need_atomic_barrier_p (model
, true))
10036 emit_insn (gen_memory_barrier ());
10039 /* Emit a (post) memory barrier around an atomic sequence according to
10043 arc_post_atomic_barrier (enum memmodel model
)
10045 if (need_atomic_barrier_p (model
, false))
10046 emit_insn (gen_memory_barrier ());
10049 /* Expand a compare and swap pattern. */
10052 emit_unlikely_jump (rtx insn
)
10054 rtx_insn
*jump
= emit_jump_insn (insn
);
10055 add_reg_br_prob_note (jump
, profile_probability::very_unlikely ());
10058 /* Expand code to perform a 8 or 16-bit compare and swap by doing
10059 32-bit compare and swap on the word containing the byte or
10060 half-word. The difference between a weak and a strong CAS is that
10061 the weak version may simply fail. The strong version relies on two
10062 loops, one checks if the SCOND op is succsfully or not, the other
10063 checks if the 32 bit accessed location which contains the 8 or 16
10064 bit datum is not changed by other thread. The first loop is
10065 implemented by the atomic_compare_and_swapsi_1 pattern. The second
10066 loops is implemented by this routine. */
10069 arc_expand_compare_and_swap_qh (rtx bool_result
, rtx result
, rtx mem
,
10070 rtx oldval
, rtx newval
, rtx weak
,
10071 rtx mod_s
, rtx mod_f
)
10073 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
10074 rtx addr
= gen_reg_rtx (Pmode
);
10075 rtx off
= gen_reg_rtx (SImode
);
10076 rtx oldv
= gen_reg_rtx (SImode
);
10077 rtx newv
= gen_reg_rtx (SImode
);
10078 rtx oldvalue
= gen_reg_rtx (SImode
);
10079 rtx newvalue
= gen_reg_rtx (SImode
);
10080 rtx res
= gen_reg_rtx (SImode
);
10081 rtx resv
= gen_reg_rtx (SImode
);
10082 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
, x
;
10084 bool is_weak
= (weak
!= const0_rtx
);
10086 /* Truncate the address. */
10087 emit_insn (gen_rtx_SET (addr
,
10088 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
10090 /* Compute the datum offset. */
10091 emit_insn (gen_rtx_SET (off
,
10092 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
10093 if (TARGET_BIG_ENDIAN
)
10094 emit_insn (gen_rtx_SET (off
,
10095 gen_rtx_MINUS (SImode
,
10096 (GET_MODE (mem
) == QImode
) ?
10097 GEN_INT (3) : GEN_INT (2), off
)));
10099 /* Normal read from truncated address. */
10100 memsi
= gen_rtx_MEM (SImode
, addr
);
10101 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
10102 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
10104 val
= copy_to_reg (memsi
);
10106 /* Convert the offset in bits. */
10107 emit_insn (gen_rtx_SET (off
,
10108 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
10110 /* Get the proper mask. */
10111 if (GET_MODE (mem
) == QImode
)
10112 mask
= force_reg (SImode
, GEN_INT (0xff));
10114 mask
= force_reg (SImode
, GEN_INT (0xffff));
10116 emit_insn (gen_rtx_SET (mask
,
10117 gen_rtx_ASHIFT (SImode
, mask
, off
)));
10119 /* Prepare the old and new values. */
10120 emit_insn (gen_rtx_SET (val
,
10121 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10124 oldval
= gen_lowpart (SImode
, oldval
);
10125 emit_insn (gen_rtx_SET (oldv
,
10126 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
10128 newval
= gen_lowpart_common (SImode
, newval
);
10129 emit_insn (gen_rtx_SET (newv
,
10130 gen_rtx_ASHIFT (SImode
, newval
, off
)));
10132 emit_insn (gen_rtx_SET (oldv
,
10133 gen_rtx_AND (SImode
, oldv
, mask
)));
10135 emit_insn (gen_rtx_SET (newv
,
10136 gen_rtx_AND (SImode
, newv
, mask
)));
10140 end_label
= gen_label_rtx ();
10141 loop_label
= gen_label_rtx ();
10142 emit_label (loop_label
);
10145 /* Make the old and new values. */
10146 emit_insn (gen_rtx_SET (oldvalue
,
10147 gen_rtx_IOR (SImode
, oldv
, val
)));
10149 emit_insn (gen_rtx_SET (newvalue
,
10150 gen_rtx_IOR (SImode
, newv
, val
)));
10152 /* Try an 32bit atomic compare and swap. It clobbers the CC
10154 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
,
10155 weak
, mod_s
, mod_f
));
10157 /* Regardless of the weakness of the operation, a proper boolean
10158 result needs to be provided. */
10159 x
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10160 x
= gen_rtx_EQ (SImode
, x
, const0_rtx
);
10161 emit_insn (gen_rtx_SET (bool_result
, x
));
10165 /* Check the results: if the atomic op is successfully the goto
10167 x
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10168 x
= gen_rtx_EQ (VOIDmode
, x
, const0_rtx
);
10169 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10170 gen_rtx_LABEL_REF (Pmode
, end_label
), pc_rtx
);
10171 emit_jump_insn (gen_rtx_SET (pc_rtx
, x
));
10173 /* Wait for the right moment when the accessed 32-bit location
10175 emit_insn (gen_rtx_SET (resv
,
10176 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10178 mode
= SELECT_CC_MODE (NE
, resv
, val
);
10179 cc
= gen_rtx_REG (mode
, CC_REG
);
10180 emit_insn (gen_rtx_SET (cc
, gen_rtx_COMPARE (mode
, resv
, val
)));
10182 /* Set the new value of the 32 bit location, proper masked. */
10183 emit_insn (gen_rtx_SET (val
, resv
));
10185 /* Try again if location is unstable. Fall through if only
10186 scond op failed. */
10187 x
= gen_rtx_NE (VOIDmode
, cc
, const0_rtx
);
10188 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10189 gen_rtx_LABEL_REF (Pmode
, loop_label
), pc_rtx
);
10190 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10192 emit_label (end_label
);
10195 /* End: proper return the result for the given mode. */
10196 emit_insn (gen_rtx_SET (res
,
10197 gen_rtx_AND (SImode
, res
, mask
)));
10199 emit_insn (gen_rtx_SET (res
,
10200 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
10202 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
10205 /* Helper function used by "atomic_compare_and_swap" expand
10209 arc_expand_compare_and_swap (rtx operands
[])
10211 rtx bval
, rval
, mem
, oldval
, newval
, is_weak
, mod_s
, mod_f
, x
;
10214 bval
= operands
[0];
10215 rval
= operands
[1];
10217 oldval
= operands
[3];
10218 newval
= operands
[4];
10219 is_weak
= operands
[5];
10220 mod_s
= operands
[6];
10221 mod_f
= operands
[7];
10222 mode
= GET_MODE (mem
);
10224 if (reg_overlap_mentioned_p (rval
, oldval
))
10225 oldval
= copy_to_reg (oldval
);
10227 if (mode
== SImode
)
10229 emit_insn (gen_atomic_compare_and_swapsi_1 (rval
, mem
, oldval
, newval
,
10230 is_weak
, mod_s
, mod_f
));
10231 x
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10232 x
= gen_rtx_EQ (SImode
, x
, const0_rtx
);
10233 emit_insn (gen_rtx_SET (bval
, x
));
10237 arc_expand_compare_and_swap_qh (bval
, rval
, mem
, oldval
, newval
,
10238 is_weak
, mod_s
, mod_f
);
10242 /* Helper function used by the "atomic_compare_and_swapsi_1"
10246 arc_split_compare_and_swap (rtx operands
[])
10248 rtx rval
, mem
, oldval
, newval
;
10250 enum memmodel mod_s
, mod_f
;
10252 rtx label1
, label2
, x
, cond
;
10254 rval
= operands
[0];
10256 oldval
= operands
[2];
10257 newval
= operands
[3];
10258 is_weak
= (operands
[4] != const0_rtx
);
10259 mod_s
= (enum memmodel
) INTVAL (operands
[5]);
10260 mod_f
= (enum memmodel
) INTVAL (operands
[6]);
10261 mode
= GET_MODE (mem
);
10263 /* ARC atomic ops work only with 32-bit aligned memories. */
10264 gcc_assert (mode
== SImode
);
10266 arc_pre_atomic_barrier (mod_s
);
10271 label1
= gen_label_rtx ();
10272 emit_label (label1
);
10274 label2
= gen_label_rtx ();
10276 /* Load exclusive. */
10277 emit_insn (gen_arc_load_exclusivesi (rval
, mem
));
10279 /* Check if it is oldval. */
10280 mode
= SELECT_CC_MODE (NE
, rval
, oldval
);
10281 cond
= gen_rtx_REG (mode
, CC_REG
);
10282 emit_insn (gen_rtx_SET (cond
, gen_rtx_COMPARE (mode
, rval
, oldval
)));
10284 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
10285 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10286 gen_rtx_LABEL_REF (Pmode
, label2
), pc_rtx
);
10287 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10289 /* Exclusively store new item. Store clobbers CC reg. */
10290 emit_insn (gen_arc_store_exclusivesi (mem
, newval
));
10294 /* Check the result of the store. */
10295 cond
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10296 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
10297 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10298 gen_rtx_LABEL_REF (Pmode
, label1
), pc_rtx
);
10299 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10302 if (mod_f
!= MEMMODEL_RELAXED
)
10303 emit_label (label2
);
10305 arc_post_atomic_barrier (mod_s
);
10307 if (mod_f
== MEMMODEL_RELAXED
)
10308 emit_label (label2
);
10311 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
10312 to perform. MEM is the memory on which to operate. VAL is the second
10313 operand of the binary operator. BEFORE and AFTER are optional locations to
10314 return the value of MEM either before of after the operation. MODEL_RTX
10315 is a CONST_INT containing the memory model to use. */
10318 arc_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
10319 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
10321 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
10322 machine_mode mode
= GET_MODE (mem
);
10323 rtx label
, x
, cond
;
10324 rtx before
= orig_before
, after
= orig_after
;
10326 /* ARC atomic ops work only with 32-bit aligned memories. */
10327 gcc_assert (mode
== SImode
);
10329 arc_pre_atomic_barrier (model
);
10331 label
= gen_label_rtx ();
10332 emit_label (label
);
10333 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
10335 if (before
== NULL_RTX
)
10336 before
= gen_reg_rtx (mode
);
10338 if (after
== NULL_RTX
)
10339 after
= gen_reg_rtx (mode
);
10341 /* Load exclusive. */
10342 emit_insn (gen_arc_load_exclusivesi (before
, mem
));
10347 x
= gen_rtx_AND (mode
, before
, val
);
10348 emit_insn (gen_rtx_SET (after
, x
));
10349 x
= gen_rtx_NOT (mode
, after
);
10350 emit_insn (gen_rtx_SET (after
, x
));
10354 if (CONST_INT_P (val
))
10356 val
= GEN_INT (-INTVAL (val
));
10362 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
10363 emit_insn (gen_rtx_SET (after
, x
));
10367 /* Exclusively store new item. Store clobbers CC reg. */
10368 emit_insn (gen_arc_store_exclusivesi (mem
, after
));
10370 /* Check the result of the store. */
10371 cond
= gen_rtx_REG (CC_Zmode
, CC_REG
);
10372 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
10373 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
10375 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
10377 arc_post_atomic_barrier (model
);
10380 /* Implement TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P. */
10383 arc_no_speculation_in_delay_slots_p ()
10388 /* Return a parallel of registers to represent where to find the
10389 register pieces if required, otherwise NULL_RTX. */
10392 arc_dwarf_register_span (rtx rtl
)
10394 machine_mode mode
= GET_MODE (rtl
);
10398 if (GET_MODE_SIZE (mode
) != 8)
10401 p
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
10402 regno
= REGNO (rtl
);
10403 XVECEXP (p
, 0, 0) = gen_rtx_REG (SImode
, regno
);
10404 XVECEXP (p
, 0, 1) = gen_rtx_REG (SImode
, regno
+ 1);
10409 /* Return true if OP is an acceptable memory operand for ARCompact
10410 16-bit load instructions of MODE.
10412 AV2SHORT: TRUE if address needs to fit into the new ARCv2 short
10413 non scaled instructions.
10415 SCALED: TRUE if address can be scaled. */
10418 compact_memory_operand_p (rtx op
, machine_mode mode
,
10419 bool av2short
, bool scaled
)
10421 rtx addr
, plus0
, plus1
;
10424 /* Eliminate non-memory operations. */
10425 if (GET_CODE (op
) != MEM
)
10428 /* .di instructions have no 16-bit form. */
10429 if (MEM_VOLATILE_P (op
) && !TARGET_VOLATILE_CACHE_SET
)
10432 if (mode
== VOIDmode
)
10433 mode
= GET_MODE (op
);
10435 size
= GET_MODE_SIZE (mode
);
10437 /* dword operations really put out 2 instructions, so eliminate
10439 if (size
> UNITS_PER_WORD
)
10442 /* Decode the address now. */
10443 addr
= XEXP (op
, 0);
10444 switch (GET_CODE (addr
))
10447 return (REGNO (addr
) >= FIRST_PSEUDO_REGISTER
10448 || COMPACT_GP_REG_P (REGNO (addr
))
10449 || (SP_REG_P (REGNO (addr
)) && (size
!= 2)));
10451 plus0
= XEXP (addr
, 0);
10452 plus1
= XEXP (addr
, 1);
10454 if ((GET_CODE (plus0
) == REG
)
10455 && ((REGNO (plus0
) >= FIRST_PSEUDO_REGISTER
)
10456 || COMPACT_GP_REG_P (REGNO (plus0
)))
10457 && ((GET_CODE (plus1
) == REG
)
10458 && ((REGNO (plus1
) >= FIRST_PSEUDO_REGISTER
)
10459 || COMPACT_GP_REG_P (REGNO (plus1
)))))
10464 if ((GET_CODE (plus0
) == REG
)
10465 && ((REGNO (plus0
) >= FIRST_PSEUDO_REGISTER
)
10466 || (COMPACT_GP_REG_P (REGNO (plus0
)) && !av2short
)
10467 || (IN_RANGE (REGNO (plus0
), 0, 31) && av2short
))
10468 && (GET_CODE (plus1
) == CONST_INT
))
10470 bool valid
= false;
10472 off
= INTVAL (plus1
);
10474 /* Negative offset is not supported in 16-bit load/store insns. */
10478 /* Only u5 immediates allowed in code density instructions. */
10486 /* This is an ldh_s.x instruction, check the u6
10488 if (COMPACT_GP_REG_P (REGNO (plus0
)))
10492 /* Only u5 immediates allowed in 32bit access code
10493 density instructions. */
10494 if (REGNO (plus0
) <= 31)
10495 return ((off
< 32) && (off
% 4 == 0));
10502 if (COMPACT_GP_REG_P (REGNO (plus0
)))
10513 /* The 6-bit constant get shifted to fit the real
10514 5-bits field. Check also for the alignment. */
10515 return ((off
< 64) && (off
% 2 == 0));
10517 return ((off
< 128) && (off
% 4 == 0));
10524 if (REG_P (plus0
) && CONST_INT_P (plus1
)
10525 && ((REGNO (plus0
) >= FIRST_PSEUDO_REGISTER
)
10526 || SP_REG_P (REGNO (plus0
)))
10529 off
= INTVAL (plus1
);
10530 return ((size
!= 2) && (off
>= 0 && off
< 128) && (off
% 4 == 0));
10533 if ((GET_CODE (plus0
) == MULT
)
10534 && (GET_CODE (XEXP (plus0
, 0)) == REG
)
10535 && ((REGNO (XEXP (plus0
, 0)) >= FIRST_PSEUDO_REGISTER
)
10536 || COMPACT_GP_REG_P (REGNO (XEXP (plus0
, 0))))
10537 && (GET_CODE (plus1
) == REG
)
10538 && ((REGNO (plus1
) >= FIRST_PSEUDO_REGISTER
)
10539 || COMPACT_GP_REG_P (REGNO (plus1
))))
10543 /* TODO: 'gp' and 'pcl' are to supported as base address operand
10544 for 16-bit load instructions. */
10549 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
10550 anchors for small data: the GP register acts as an anchor in that
10551 case. We also don't want to use them for PC-relative accesses,
10552 where the PC acts as an anchor. Prohibit also TLS symbols to use
10556 arc_use_anchors_for_symbol_p (const_rtx symbol
)
10558 if (SYMBOL_REF_TLS_MODEL (symbol
))
10564 if (SYMBOL_REF_SMALL_P (symbol
))
10567 return default_use_anchors_for_symbol_p (symbol
);
10570 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
10571 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
10573 struct gcc_target targetm
= TARGET_INITIALIZER
;
10575 #include "gt-arc.h"