1 /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu.
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
31 #define SYMBOL_FLAG_SHORT_CALL (SYMBOL_FLAG_MACH_DEP << 0)
32 #define SYMBOL_FLAG_MEDIUM_CALL (SYMBOL_FLAG_MACH_DEP << 1)
33 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 2)
34 #define SYMBOL_FLAG_CMEM (SYMBOL_FLAG_MACH_DEP << 3)
36 #ifndef TARGET_CPU_DEFAULT
37 #define TARGET_CPU_DEFAULT PROCESSOR_arc700
40 /* Check if this symbol has a long_call attribute in its declaration */
41 #define SYMBOL_REF_LONG_CALL_P(X) \
42 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
44 /* Check if this symbol has a medium_call attribute in its declaration */
45 #define SYMBOL_REF_MEDIUM_CALL_P(X) \
46 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_MEDIUM_CALL) != 0)
48 /* Check if this symbol has a short_call attribute in its declaration */
49 #define SYMBOL_REF_SHORT_CALL_P(X) \
50 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SHORT_CALL) != 0)
52 /* Names to predefine in the preprocessor for this target machine. */
53 #define TARGET_CPU_CPP_BUILTINS() arc_cpu_cpp_builtins (pfile)
55 /* Macros enabled by specific command line option. FIXME: to be
58 %{msimd:-D__Xsimd} %{mno-mpy:-D__Xno_mpy} %{mswap:-D__Xswap} \
59 %{mmin-max:-D__Xmin_max} %{mEA:-D__Xea} \
60 %{mspfp*:-D__Xspfp} %{mdpfp*:-D__Xdpfp} \
61 %{mmac-d16:-D__Xxmac_d16} %{mmac-24:-D__Xxmac_24} \
62 %{mdsp-packa:-D__Xdsp_packa} %{mcrc:-D__Xcrc} %{mdvbf:-D__Xdvbf} \
63 %{mtelephony:-D__Xtelephony} %{mxy:-D__Xxy} %{mmul64: -D__Xmult32} \
64 %{mlock:-D__Xlock} %{mswape:-D__Xswape} %{mrtsc:-D__Xrtsc} \
65 %(subtarget_cpp_spec)"
68 #define CC1_SPEC "%{EB:%{EL:%emay not use both -EB and -EL}} \
69 %{EB:-mbig-endian} %{EL:-mlittle-endian} \
72 extern const char *arc_cpu_to_as (int argc
, const char **argv
);
74 #define EXTRA_SPEC_FUNCTIONS \
75 { "cpu_to_as", arc_cpu_to_as },
77 /* This macro defines names of additional specifications to put in the specs
78 that can be used in various specifications like CC1_SPEC. Its definition
79 is an initializer with a subgrouping for each command option.
81 Each subgrouping contains a string constant, that defines the
82 specification name, and a string constant that used by the GCC driver
85 Do not define this macro if it does not need to do anything. */
87 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
90 #ifndef SUBTARGET_EXTRA_SPECS
91 #define SUBTARGET_EXTRA_SPECS
94 #ifndef SUBTARGET_CPP_SPEC
95 #define SUBTARGET_CPP_SPEC ""
99 #define ASM_SPEC "%{mbig-endian|EB:-EB} %{EL} " \
100 "%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} %{mfpu=fpuda*:-mfpuda}"
102 #define OPTION_DEFAULT_SPECS \
103 {"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}}}}}" }
105 #ifndef DRIVER_ENDIAN_SELF_SPECS
106 #define DRIVER_ENDIAN_SELF_SPECS ""
109 #define DRIVER_SELF_SPECS DRIVER_ENDIAN_SELF_SPECS \
110 "%{mARC600|mA6: -mcpu=arc600 %<mARC600 %<mA6 %<mARC600}" \
111 "%{mARC601: -mcpu=arc601 %<mARC601}" \
112 "%{mARC700|mA7: -mcpu=arc700 %<mARC700 %<mA7}" \
115 /* Run-time compilation parameters selecting different hardware subsets. */
117 #define TARGET_MIXED_CODE (TARGET_MIXED_CODE_SET)
119 #define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET)
120 #define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET \
123 #define SUBTARGET_SWITCHES
125 /* Instruction set characteristics.
126 These are internal macros, set by the appropriate -m option. */
128 /* Non-zero means the cpu supports norm instruction. This flag is set by
129 default for A7, and only for pre A7 cores when -mnorm is given. */
130 #define TARGET_NORM (TARGET_ARC700 || TARGET_NORM_SET || TARGET_HS)
131 /* Indicate if an optimized floating point emulation library is available. */
132 #define TARGET_OPTFPE (TARGET_ARC700 || TARGET_FPX_QUARK)
134 /* Non-zero means the cpu supports swap instruction. This flag is set by
135 default for A7, and only for pre A7 cores when -mswap is given. */
136 #define TARGET_SWAP (TARGET_ARC700 || TARGET_SWAP_SET)
138 /* Provide some macros for size / scheduling features of the ARC700, so
139 that we can pick & choose features if we get a new cpu family member. */
141 /* Should we try to unalign likely taken branches without a delay slot. */
142 #define TARGET_UNALIGN_BRANCH (TARGET_ARC700 && !optimize_size)
144 /* Should we upsize short delayed branches with a short delay insn? */
145 #define TARGET_UPSIZE_DBR (TARGET_ARC700 && !optimize_size)
147 /* Should we add padding before a return insn to avoid mispredict? */
148 #define TARGET_PAD_RETURN (TARGET_ARC700 && !optimize_size)
150 /* For an anulled-true delay slot insn for a delayed branch, should we only
151 use conditional execution? */
152 #define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700 && !TARGET_V2)
154 #define TARGET_ARC600 ((arc_selected_cpu->arch_info->arch_id \
156 && (TARGET_BARREL_SHIFTER))
157 #define TARGET_ARC601 ((arc_selected_cpu->arch_info->arch_id \
159 && (!TARGET_BARREL_SHIFTER))
160 #define TARGET_ARC700 (arc_selected_cpu->arch_info->arch_id \
162 /* An NPS400 is a specialisation of ARC700, so it is correct for NPS400
163 TARGET_ARC700 is true, and TARGET_NPS400 is true. */
164 #define TARGET_NPS400 ((arc_selected_cpu->arch_info->arch_id \
166 && (arc_selected_cpu->processor \
167 == PROCESSOR_nps400))
168 #define TARGET_EM (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_em)
169 #define TARGET_HS (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_hs)
170 #define TARGET_V2 (TARGET_EM || TARGET_HS)
172 #ifndef UNALIGNED_ACCESS_DEFAULT
173 #define UNALIGNED_ACCESS_DEFAULT 0
176 #ifndef TARGET_NPS_BITOPS_DEFAULT
177 #define TARGET_NPS_BITOPS_DEFAULT 0
180 #ifndef TARGET_NPS_CMEM_DEFAULT
181 #define TARGET_NPS_CMEM_DEFAULT 0
184 /* Enable the RRQ instruction alternatives. */
186 #define TARGET_RRQ_CLASS TARGET_NPS_BITOPS
188 /* Target machine storage layout. */
190 /* We want zero_extract to mean the same
191 no matter what the byte endianness is. */
192 #define BITS_BIG_ENDIAN 0
194 /* Define this if most significant byte of a word is the lowest numbered. */
195 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
197 /* Define this if most significant word of a multiword number is the lowest
199 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
201 /* Width in bits of a "word", which is the contents of a machine register.
202 Note that this is not necessarily the width of data type `int';
203 if using 16-bit ints on a 68000, this would still be 32.
204 But on a machine with 16-bit registers, this would be 16. */
205 #define BITS_PER_WORD 32
207 /* Width of a word, in units (bytes). */
208 #define UNITS_PER_WORD 4
210 /* Define this macro if it is advisable to hold scalars in registers
211 in a wider mode than that declared by the program. In such cases,
212 the value is constrained to be within the bounds of the declared
213 type, but kept valid in the wider mode. The signedness of the
214 extension may differ from that of the type. */
215 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
216 if (GET_MODE_CLASS (MODE) == MODE_INT \
217 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
222 /* Width in bits of a pointer.
223 See also the macro `Pmode' defined below. */
224 #define POINTER_SIZE 32
226 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
227 #define PARM_BOUNDARY 32
229 /* Boundary (in *bits*) on which stack pointer should be aligned. */
230 /* TOCHECK: Changed from 64 to 32 */
231 #define STACK_BOUNDARY 32
233 /* ALIGN FRAMES on word boundaries. */
234 #define ARC_STACK_ALIGN(LOC) \
235 (((LOC) + STACK_BOUNDARY / BITS_PER_UNIT - 1) & -STACK_BOUNDARY/BITS_PER_UNIT)
237 /* Allocation boundary (in *bits*) for the code of a function. */
238 #define FUNCTION_BOUNDARY 32
240 /* Alignment of field after `int : 0' in a structure. */
241 #define EMPTY_FIELD_BOUNDARY 32
243 /* Every structure's size must be a multiple of this. */
244 #define STRUCTURE_SIZE_BOUNDARY 8
246 /* A bitfield declared as `int' forces `int' alignment for the struct. */
247 #define PCC_BITFIELD_TYPE_MATTERS 1
249 /* An expression for the alignment of a structure field FIELD if the
250 alignment computed in the usual way (including applying of
251 `BIGGEST_ALIGNMENT' and `BIGGEST_FIELD_ALIGNMENT' to the
252 alignment) is COMPUTED. It overrides alignment only if the field
253 alignment has not been set by the `__attribute__ ((aligned (N)))'
257 #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
258 (TYPE_MODE (strip_array_types (TYPE)) == DFmode \
259 ? MIN ((COMPUTED), 32) : (COMPUTED))
263 /* No data type wants to be aligned rounder than this. */
264 /* This is bigger than currently necessary for the ARC. If 8 byte floats are
265 ever added it's not clear whether they'll need such alignment or not. For
266 now we assume they will. We can always relax it if necessary but the
267 reverse isn't true. */
268 /* TOCHECK: Changed from 64 to 32 */
269 #define BIGGEST_ALIGNMENT 32
271 /* The best alignment to use in cases where we have a choice. */
272 #define FASTEST_ALIGNMENT 32
274 /* Make strings word-aligned so strcpy from constants will be faster. */
275 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
276 ((TREE_CODE (EXP) == STRING_CST \
277 && (ALIGN) < FASTEST_ALIGNMENT) \
278 ? FASTEST_ALIGNMENT : (ALIGN))
281 /* Make arrays of chars word-aligned for the same reasons. */
282 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
283 (TREE_CODE (TYPE) == ARRAY_TYPE \
284 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
285 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
287 #define DATA_ALIGNMENT(TYPE, ALIGN) \
288 (TREE_CODE (TYPE) == ARRAY_TYPE \
289 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
290 && arc_size_opt_level < 3 \
291 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
293 /* Set this nonzero if move instructions will actually fail to work
294 when given unaligned data. */
295 /* On the ARC the lower address bits are masked to 0 as necessary. The chip
296 won't croak when given an unaligned address, but the insn will still fail
297 to produce the correct result. */
298 #define STRICT_ALIGNMENT 1
300 /* Layout of source language data types. */
302 #define SHORT_TYPE_SIZE 16
303 #define INT_TYPE_SIZE 32
304 #define LONG_TYPE_SIZE 32
305 #define LONG_LONG_TYPE_SIZE 64
306 #define FLOAT_TYPE_SIZE 32
307 #define DOUBLE_TYPE_SIZE 64
308 #define LONG_DOUBLE_TYPE_SIZE 64
310 /* Define this as 1 if `char' should by default be signed; else as 0. */
311 #define DEFAULT_SIGNED_CHAR 0
314 #define SIZE_TYPE "unsigned int"
317 #define PTRDIFF_TYPE "int"
320 #define WCHAR_TYPE "int"
322 #undef WCHAR_TYPE_SIZE
323 #define WCHAR_TYPE_SIZE 32
325 #define PROGRAM_COUNTER_REGNO 63
327 /* Standard register usage. */
329 /* Number of actual hardware registers.
330 The hardware registers are assigned numbers for the compiler
331 from 0 to just below FIRST_PSEUDO_REGISTER.
332 All registers that the compiler knows about must be given numbers,
333 even those that are not normally considered general registers.
335 Registers 61, 62, and 63 are not really registers and we needn't treat
336 them as such. We still need a register for the condition code and
339 /* r63 is pc, r64-r127 = simd vregs, r128-r143 = simd dma config regs
340 r144, r145 = lp_start, lp_end
341 and therefore the pseudo registers start from r146. */
342 #define FIRST_PSEUDO_REGISTER 146
344 /* 1 for registers that have pervasive standard uses
345 and are not available for the register allocator.
347 0-28 - general purpose registers
348 29 - ilink1 (interrupt link register)
349 30 - ilink2 (interrupt link register)
350 31 - blink (branch link register)
351 32-59 - reserved for extensions
354 62 - argument pointer
357 FWIW, this is how the 61-63 encodings are used by the hardware:
359 62 - long immediate data indicator
360 63 - PCL (program counter aligned to 32 bit, read-only)
362 The general purpose registers are further broken down into:
364 0-7 - arguments/results
365 8-12 - call used (r11 - static chain pointer)
372 31 - return address register
374 By default, the extension registers are not available. */
375 /* Present implementations only have VR0-VR23 only. */
376 /* ??? FIXME: r27 and r31 should not be fixed registers. */
377 #define FIXED_REGISTERS \
378 { 0, 0, 0, 0, 0, 0, 0, 0, \
379 0, 0, 0, 0, 0, 0, 0, 0, \
380 0, 0, 0, 0, 0, 0, 0, 0, \
381 0, 0, 1, 1, 1, 1, 1, 1, \
383 1, 1, 1, 1, 1, 1, 1, 1, \
384 0, 0, 0, 0, 1, 1, 1, 1, \
385 1, 1, 1, 1, 1, 1, 1, 1, \
386 1, 1, 1, 1, 0, 1, 1, 1, \
388 0, 0, 0, 0, 0, 0, 0, 0, \
389 0, 0, 0, 0, 0, 0, 0, 0, \
390 0, 0, 0, 0, 0, 0, 0, 0, \
391 1, 1, 1, 1, 1, 1, 1, 1, \
393 1, 1, 1, 1, 1, 1, 1, 1, \
394 1, 1, 1, 1, 1, 1, 1, 1, \
395 1, 1, 1, 1, 1, 1, 1, 1, \
396 1, 1, 1, 1, 1, 1, 1, 1, \
398 0, 0, 0, 0, 0, 0, 0, 0, \
399 0, 0, 0, 0, 0, 0, 0, 0, \
402 /* 1 for registers not available across function calls.
403 These must include the FIXED_REGISTERS and also any
404 registers that can be used without being saved.
405 The latter must include the registers where values are returned
406 and the register where structure-value addresses are passed.
407 Aside from that, you can include as many other registers as you like. */
408 #define CALL_USED_REGISTERS \
410 1, 1, 1, 1, 1, 1, 1, 1, \
411 1, 1, 1, 1, 1, 0, 0, 0, \
412 0, 0, 0, 0, 0, 0, 0, 0, \
413 0, 0, 1, 1, 1, 1, 1, 1, \
415 1, 1, 1, 1, 1, 1, 1, 1, \
416 1, 1, 1, 1, 1, 1, 1, 1, \
417 1, 1, 1, 1, 1, 1, 1, 1, \
418 1, 1, 1, 1, 1, 1, 1, 1, \
420 0, 0, 0, 0, 0, 0, 0, 0, \
421 0, 0, 0, 0, 0, 0, 0, 0, \
422 0, 0, 0, 0, 0, 0, 0, 0, \
423 1, 1, 1, 1, 1, 1, 1, 1, \
425 1, 1, 1, 1, 1, 1, 1, 1, \
426 1, 1, 1, 1, 1, 1, 1, 1, \
427 1, 1, 1, 1, 1, 1, 1, 1, \
428 1, 1, 1, 1, 1, 1, 1, 1, \
430 0, 0, 0, 0, 0, 0, 0, 0, \
431 0, 0, 0, 0, 0, 0, 0, 0, \
434 /* If defined, an initializer for a vector of integers, containing the
435 numbers of hard registers in the order in which GCC should
436 prefer to use them (from most preferred to least). */
437 #define REG_ALLOC_ORDER \
438 { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \
439 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
440 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
441 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
442 27, 28, 29, 30, 31, 63}
444 /* Return number of consecutive hard regs needed starting at reg REGNO
445 to hold something of mode MODE.
446 This is ordinarily the length in words of a value of mode MODE
447 but can be less for certain modes in special long registers. */
448 #define HARD_REGNO_NREGS(REGNO, MODE) \
449 ((GET_MODE_SIZE (MODE) == 16 \
450 && REGNO >= ARC_FIRST_SIMD_VR_REG && REGNO <= ARC_LAST_SIMD_VR_REG) ? 1 \
451 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
453 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
454 extern unsigned int arc_hard_regno_mode_ok
[];
455 extern unsigned int arc_mode_class
[];
456 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
457 ((arc_hard_regno_mode_ok[REGNO] & arc_mode_class[MODE]) != 0)
459 /* A C expression that is nonzero if it is desirable to choose
460 register allocation so as to avoid move instructions between a
461 value of mode MODE1 and a value of mode MODE2.
463 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
464 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
465 MODE2)' must be zero. */
467 /* Tie QI/HI/SI modes together. */
468 #define MODES_TIEABLE_P(MODE1, MODE2) \
469 (GET_MODE_CLASS (MODE1) == MODE_INT \
470 && GET_MODE_CLASS (MODE2) == MODE_INT \
471 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
472 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
474 /* Internal macros to classify a register number as to whether it's a
475 general purpose register for compact insns (r0-r3,r12-r15), or
476 stack pointer (r28). */
478 #define COMPACT_GP_REG_P(REGNO) \
479 (((signed)(REGNO) >= 0 && (REGNO) <= 3) || ((REGNO) >= 12 && (REGNO) <= 15))
480 #define SP_REG_P(REGNO) ((REGNO) == 28)
484 /* Register classes and constants. */
486 /* Define the classes of registers for register constraints in the
487 machine description. Also define ranges of constants.
489 One of the classes must always be named ALL_REGS and include all hard regs.
490 If there is more than one class, another class must be named NO_REGS
491 and contain no registers.
493 The name GENERAL_REGS must be the name of a class (or an alias for
494 another name such as ALL_REGS). This is the class of registers
495 that is allowed by "g" or "r" in a register constraint.
496 Also, registers outside this class are allocated only when
497 instructions express preferences for them.
499 The classes must be numbered in nondecreasing order; that is,
500 a larger-numbered class must never be contained completely
501 in a smaller-numbered class.
503 For any two classes, it is very desirable that there be another
504 class that represents their union.
506 It is important that any condition codes have class NO_REGS.
507 See `register_operand'. */
516 LPCOUNT_REG
, /* 'l' */
518 DOUBLE_REGS
, /* D0, D1 */
519 SIMD_VR_REGS
, /* VR00-VR63 */
520 SIMD_DMA_CONFIG_REGS
, /* DI0-DI7,DO0-DO7 */
521 ARCOMPACT16_REGS
, /* 'q' */
522 AC16_BASE_REGS
, /* 'e' */
523 SIBCALL_REGS
, /* "Rsc" */
524 GENERAL_REGS
, /* 'r' */
525 MPY_WRITABLE_CORE_REGS
, /* 'W' */
526 WRITABLE_CORE_REGS
, /* 'w' */
527 CHEAP_CORE_REGS
, /* 'c' */
528 ALL_CORE_REGS
, /* 'Rac' */
529 R0R3_CD_REGS
, /* 'Rcd' */
530 R0R1_CD_REGS
, /* 'Rsd' */
531 AC16_H_REGS
, /* 'h' */
536 #define N_REG_CLASSES (int) LIM_REG_CLASSES
538 /* Give names of register classes as strings for dump file. */
539 #define REG_CLASS_NAMES \
550 "SIMD_DMA_CONFIG_REGS", \
551 "ARCOMPACT16_REGS", \
555 "MPY_WRITABLE_CORE_REGS", \
556 "WRITABLE_CORE_REGS", \
565 /* Define which registers fit in which classes.
566 This is an initializer for a vector of HARD_REG_SET
567 of length N_REG_CLASSES. */
569 #define REG_CLASS_CONTENTS \
571 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* No Registers */ \
572 {0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'x', r0 register , r0 */ \
573 {0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rgp', Global Pointer, r26 */ \
574 {0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'f', Frame Pointer, r27 */ \
575 {0x10000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'b', Stack Pointer, r28 */ \
576 {0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000}, /* 'l', LPCOUNT Register, r60 */ \
577 {0xe0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'k', LINK Registers, r29-r31 */ \
578 {0x00000000, 0x00000f00, 0x00000000, 0x00000000, 0x00000000}, /* 'D', D1, D2 Registers */ \
579 {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000}, /* 'V', VR00-VR63 Registers */ \
580 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff}, /* 'V', DI0-7,DO0-7 Registers */ \
581 {0x0000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'q', r0-r3, r12-r15 */ \
582 {0x1000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'e', r0-r3, r12-r15, sp */ \
583 {0x1c001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* "Rsc", r0-r12 */ \
584 {0x9fffffff, 0xc0000000, 0x00000000, 0x00000000, 0x00000000}, /* 'r', r0-r28, blink, ap and pcl */ \
585 {0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'W', r0-r31 */ \
586 /* Include ap / pcl in WRITABLE_CORE_REGS for sake of symmetry. As these \
587 registers are fixed, it does not affect the literal meaning of the \
588 constraints, but it makes it a superset of GENERAL_REGS, thus \
589 enabling some operations that would otherwise not be possible. */ \
590 {0xffffffff, 0xd0000000, 0x00000000, 0x00000000, 0x00000000}, /* 'w', r0-r31, r60 */ \
591 {0xffffffff, 0xdfffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'c', r0-r60, ap, pcl */ \
592 {0xffffffff, 0xdfffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'Rac', r0-r60, ap, pcl */ \
593 {0x0000000f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rcd', r0-r3 */ \
594 {0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsd', r0-r1 */ \
595 {0x9fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'h', r0-28, r30 */ \
596 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff} /* All Registers */ \
599 /* Local macros to mark the first and last regs of different classes. */
600 #define ARC_FIRST_SIMD_VR_REG 64
601 #define ARC_LAST_SIMD_VR_REG 127
603 #define ARC_FIRST_SIMD_DMA_CONFIG_REG 128
604 #define ARC_FIRST_SIMD_DMA_CONFIG_IN_REG 128
605 #define ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG 136
606 #define ARC_LAST_SIMD_DMA_CONFIG_REG 143
608 /* ARCv2 double-register accumulator. */
609 #define ACC_REG_FIRST 58
610 #define ACC_REG_LAST 59
611 #define ACCL_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST + 1 : ACC_REG_FIRST)
612 #define ACCH_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST : ACC_REG_FIRST + 1)
614 /* The same information, inverted:
615 Return the class number of the smallest class containing
616 reg number REGNO. This could be a conditional expression
617 or could index an array. */
619 extern enum reg_class arc_regno_reg_class
[];
621 #define REGNO_REG_CLASS(REGNO) (arc_regno_reg_class[REGNO])
623 /* The class value for valid index registers. An index register is
624 one used in an address where its value is either multiplied by
625 a scale factor or added to another register (as well as added to a
628 #define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS)
630 /* The class value for valid base registers. A base register is one used in
631 an address which is the register value plus a displacement. */
633 #define BASE_REG_CLASS (TARGET_MIXED_CODE ? AC16_BASE_REGS : GENERAL_REGS)
635 /* These assume that REGNO is a hard or pseudo reg number.
636 They give nonzero only if REGNO is a hard reg of the suitable class
637 or a pseudo reg currently allocated to a suitable hard reg.
638 Since they use reg_renumber, they are safe only once reg_renumber
639 has been allocated, which happens in local-alloc.c. */
640 #define REGNO_OK_FOR_BASE_P(REGNO) \
641 ((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63) \
642 || ((unsigned) reg_renumber[REGNO] < 29) \
643 || ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \
644 || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \
645 || ((REGNO) == 30 && fixed_regs[REGNO] == 0))
647 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
649 /* Given an rtx X being reloaded into a reg required to be
650 in class CLASS, return the class of reg to actually use.
651 In general this is just CLASS; but on some machines
652 in some cases it is preferable to use a more restrictive class. */
654 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
655 arc_preferred_reload_class((X), (CLASS))
657 extern enum reg_class
arc_preferred_reload_class (rtx
, enum reg_class
);
659 /* Return the maximum number of consecutive registers
660 needed to represent mode MODE in a register of class CLASS. */
662 #define CLASS_MAX_NREGS(CLASS, MODE) \
663 (( GET_MODE_SIZE (MODE) == 16 && CLASS == SIMD_VR_REGS) ? 1: \
664 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
666 #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200)
667 #define SMALL_INT_RANGE(X, OFFSET, SHIFT) \
668 ((unsigned) (((X) >> (SHIFT)) + 0x100) \
669 < 0x200 - ((unsigned) (OFFSET) >> (SHIFT)))
670 #define SIGNED_INT12(X) ((unsigned) ((X) + 0x800) < 0x1000)
671 #define SIGNED_INT16(X) ((unsigned) ((X) + 0x8000) < 0x10000)
672 #define LARGE_INT(X) \
674 ? (X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \
675 : (unsigned HOST_WIDE_INT) (X) <= (unsigned HOST_WIDE_INT) 0xffffffff)
676 #define UNSIGNED_INT3(X) ((unsigned) (X) < 0x8)
677 #define UNSIGNED_INT5(X) ((unsigned) (X) < 0x20)
678 #define UNSIGNED_INT6(X) ((unsigned) (X) < 0x40)
679 #define UNSIGNED_INT7(X) ((unsigned) (X) < 0x80)
680 #define UNSIGNED_INT8(X) ((unsigned) (X) < 0x100)
681 #define UNSIGNED_INT12(X) ((unsigned) (X) < 0x800)
682 #define UNSIGNED_INT16(X) ((unsigned) (X) < 0x10000)
683 #define IS_ONE(X) ((X) == 1)
684 #define IS_ZERO(X) ((X) == 0)
686 /* Stack layout and stack pointer usage. */
688 /* Define this macro if pushing a word onto the stack moves the stack
689 pointer to a smaller address. */
690 #define STACK_GROWS_DOWNWARD 1
692 /* Define this if the nominal address of the stack frame
693 is at the high-address end of the local variables;
694 that is, each additional local variable allocated
695 goes at a more negative offset in the frame. */
696 #define FRAME_GROWS_DOWNWARD 1
698 /* Offset within stack frame to start allocating local variables at.
699 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
700 first local allocated. Otherwise, it is the offset to the BEGINNING
701 of the first local allocated. */
702 #define STARTING_FRAME_OFFSET 0
704 /* Offset from the stack pointer register to the first location at which
705 outgoing arguments are placed. */
706 #define STACK_POINTER_OFFSET (0)
708 /* Offset of first parameter from the argument pointer register value. */
709 #define FIRST_PARM_OFFSET(FNDECL) (0)
711 /* A C expression whose value is RTL representing the address in a
712 stack frame where the pointer to the caller's frame is stored.
713 Assume that FRAMEADDR is an RTL expression for the address of the
716 If you don't define this macro, the default is to return the value
717 of FRAMEADDR--that is, the stack frame address is also the address
718 of the stack word that points to the previous frame. */
720 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
722 /* A C expression whose value is RTL representing the value of the
723 return address for the frame COUNT steps up from the current frame.
724 FRAMEADDR is the frame pointer of the COUNT frame, or the frame
725 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
727 /* The current return address is in r31. The return address of anything
728 farther back is at [%fp,4]. */
730 #define RETURN_ADDR_RTX(COUNT, FRAME) \
731 arc_return_addr_rtx(COUNT,FRAME)
733 /* Register to use for pushing function arguments. */
734 #define STACK_POINTER_REGNUM 28
736 /* Base register for access to local variables of the function. */
737 #define FRAME_POINTER_REGNUM 27
739 /* Base register for access to arguments of the function. This register
740 will be eliminated into either fp or sp. */
741 #define ARG_POINTER_REGNUM 62
743 #define RETURN_ADDR_REGNUM 31
745 /* TODO - check usage of STATIC_CHAIN_REGNUM with a testcase */
746 /* Register in which static-chain is passed to a function. This must
747 not be a register used by the prologue. */
748 #define STATIC_CHAIN_REGNUM 11
750 /* Function argument passing. */
752 /* If defined, the maximum amount of space required for outgoing
753 arguments will be computed and placed into the variable
754 `crtl->outgoing_args_size'. No space will be pushed
755 onto the stack for each call; instead, the function prologue should
756 increase the stack frame size by this amount. */
757 #define ACCUMULATE_OUTGOING_ARGS 1
759 /* Define a data type for recording info about an argument list
760 during the scan of that argument list. This data type should
761 hold all necessary information about the function itself
762 and about the args processed so far, enough to enable macros
763 such as FUNCTION_ARG to determine where the next arg should go. */
764 #define CUMULATIVE_ARGS int
766 /* Initialize a variable CUM of type CUMULATIVE_ARGS
767 for a call to a function whose data type is FNTYPE.
768 For a library call, FNTYPE is 0. */
769 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
772 /* The number of registers used for parameter passing. Local to this file. */
773 #define MAX_ARC_PARM_REGS 8
775 /* 1 if N is a possible register number for function argument passing. */
776 #define FUNCTION_ARG_REGNO_P(N) \
777 ((unsigned) (N) < MAX_ARC_PARM_REGS)
779 /* The ROUND_ADVANCE* macros are local to this file. */
780 /* Round SIZE up to a word boundary. */
781 #define ROUND_ADVANCE(SIZE) \
782 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
784 /* Round arg MODE/TYPE up to the next word boundary. */
785 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
787 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
788 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
790 #define ARC_FUNCTION_ARG_BOUNDARY(MODE,TYPE) PARM_BOUNDARY
791 /* Round CUM up to the necessary point for argument MODE/TYPE. */
792 /* N.B. Vectors have alignment exceeding BIGGEST_ALIGNMENT.
793 ARC_FUNCTION_ARG_BOUNDARY reduces this to no more than 32 bit. */
794 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \
795 ((((CUM) - 1) | (ARC_FUNCTION_ARG_BOUNDARY ((MODE), (TYPE)) - 1)/BITS_PER_WORD)\
798 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
799 a reg. This includes arguments that have to be passed by reference as the
800 pointer to them is passed in a reg if one is available (and that is what
802 When passing arguments NAMED is always 1. When receiving arguments NAMED
803 is 1 for each argument except the last in a stdarg/varargs function. In
804 a stdarg function we want to treat the last named arg as named. In a
805 varargs function we want to treat the last named arg (which is
806 `__builtin_va_alist') as unnamed.
807 This macro is only used in this file. */
808 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
809 ((CUM) < MAX_ARC_PARM_REGS)
812 /* Function results. */
814 /* Define how to find the value returned by a library function
815 assuming the value has mode MODE. */
816 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
818 /* 1 if N is a possible register number for a function value
819 as seen by the caller. */
820 /* ??? What about r1 in DI/DF values. */
821 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
823 /* Tell GCC to use RETURN_IN_MEMORY. */
824 #define DEFAULT_PCC_STRUCT_RETURN 0
826 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
827 the stack pointer does not matter. The value is tested only in
828 functions that have frame pointers.
829 No definition is equivalent to always zero. */
830 #define EXIT_IGNORE_STACK 0
832 #define EPILOGUE_USES(REGNO) arc_epilogue_uses ((REGNO))
834 #define EH_USES(REGNO) arc_eh_uses((REGNO))
836 /* Definitions for register eliminations.
838 This is an array of structures. Each structure initializes one pair
839 of eliminable registers. The "from" register number is given first,
840 followed by "to". Eliminations of the same "from" register are listed
841 in order of preference.
843 We have two registers that can be eliminated on the ARC. First, the
844 argument pointer register can always be eliminated in favor of the stack
845 pointer register or frame pointer register. Secondly, the frame pointer
846 register can often be eliminated in favor of the stack pointer register.
849 #define ELIMINABLE_REGS \
850 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
851 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
852 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
854 /* Define the offset between two registers, one to be eliminated, and the other
855 its replacement, at the start of a routine. */
856 extern int arc_initial_elimination_offset(int from
, int to
);
857 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
858 (OFFSET) = arc_initial_elimination_offset ((FROM), (TO))
860 /* Output assembler code to FILE to increment profiler label # LABELNO
861 for profiling a function entry. */
862 #define FUNCTION_PROFILER(FILE, LABELNO) \
865 fprintf (FILE, "\tbl\t__mcount@plt\n"); \
867 fprintf (FILE, "\tbl\t__mcount\n"); \
870 #define NO_PROFILE_COUNTERS 1
874 /* Length in units of the trampoline for entering a nested function. */
875 #define TRAMPOLINE_SIZE 20
877 /* Alignment required for a trampoline in bits . */
878 /* For actual data alignment we just need 32, no more than the stack;
879 however, to reduce cache coherency issues, we want to make sure that
880 trampoline instructions always appear the same in any given cache line. */
881 #define TRAMPOLINE_ALIGNMENT 256
885 /* Addressing modes, and classification of registers for them. */
887 /* Maximum number of registers that can appear in a valid memory address. */
888 /* The `ld' insn allows 2, but the `st' insn only allows 1. */
889 #define MAX_REGS_PER_ADDRESS 1
891 /* We have pre inc/dec (load/store with update). */
892 #define HAVE_PRE_INCREMENT 1
893 #define HAVE_PRE_DECREMENT 1
894 #define HAVE_POST_INCREMENT 1
895 #define HAVE_POST_DECREMENT 1
896 #define HAVE_PRE_MODIFY_DISP 1
897 #define HAVE_POST_MODIFY_DISP 1
898 #define HAVE_PRE_MODIFY_REG 1
899 #define HAVE_POST_MODIFY_REG 1
900 /* ??? should also do PRE_MODIFY_REG / POST_MODIFY_REG, but that requires
901 a special predicate for the memory operand of stores, like for the SH. */
903 /* Recognize any constant value that is a valid address. */
904 #define CONSTANT_ADDRESS_P(X) \
905 (flag_pic ? (arc_legitimate_pic_addr_p (X) || LABEL_P (X)): \
906 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
907 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST))
909 /* Is the argument a const_int rtx, containing an exact power of 2 */
910 #define IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X))
911 #define IS_POWEROF2_OR_0_P(X) (! ( (X) & ((X) - 1)))
913 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
914 and check its validity for a certain class.
915 We have two alternate definitions for each of them.
916 The *_NONSTRICT definition accepts all pseudo regs; the other rejects
917 them unless they have been allocated suitable hard regs.
919 Most source files want to accept pseudo regs in the hope that
920 they will get allocated to the class that the insn wants them to be in.
921 Source files for reload pass need to be strict.
922 After reload, it makes no difference, since pseudo regs have
923 been eliminated by then. */
925 /* Nonzero if X is a hard reg that can be used as an index
926 or if it is a pseudo reg. */
927 #define REG_OK_FOR_INDEX_P_NONSTRICT(X) \
928 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \
929 || REGNO_OK_FOR_BASE_P (REGNO (X)))
931 /* Nonzero if X is a hard reg that can be used as a base reg
932 or if it is a pseudo reg. */
933 #define REG_OK_FOR_BASE_P_NONSTRICT(X) \
934 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \
935 || REGNO_OK_FOR_BASE_P (REGNO (X)))
937 /* Nonzero if X is a hard reg that can be used as an index. */
938 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
939 /* Nonzero if X is a hard reg that can be used as a base reg. */
940 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
942 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
943 that is a valid memory address for an instruction.
944 The MODE argument is the machine mode for the MEM expression
945 that wants to use this address. */
946 /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm]
947 but the `st' insn only allows [reg],[reg+shimm],[limm].
948 The only thing we can do is only allow the most strict case `st' and hope
949 other parts optimize out the restrictions for `ld'. */
951 #define RTX_OK_FOR_BASE_P(X, STRICT) \
953 && ((STRICT) ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P_NONSTRICT (X)))
955 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
957 && ((STRICT) ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P_NONSTRICT (X)))
959 /* A C compound statement that attempts to replace X, which is an address
960 that needs reloading, with a valid memory address for an operand of
961 mode MODE. WIN is a C statement label elsewhere in the code.
963 We try to get a normal form
964 of the address. That will allow inheritance of the address reloads. */
966 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
968 if (arc_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
972 /* Reading lp_count for anything but the lp instruction is very slow on the
974 #define DONT_REALLOC(REGNO,MODE) \
975 (TARGET_ARC700 && (REGNO) == 60)
978 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
979 return the mode to be used for the comparison. */
980 /*extern machine_mode arc_select_cc_mode ();*/
981 #define SELECT_CC_MODE(OP, X, Y) \
982 arc_select_cc_mode (OP, X, Y)
984 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
985 floating point inequality comparison. */
986 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
990 /* Compute extra cost of moving data between one register class
992 #define REGISTER_MOVE_COST(MODE, CLASS, TO_CLASS) \
993 arc_register_move_cost ((MODE), (CLASS), (TO_CLASS))
995 /* Compute the cost of moving data between registers and memory. */
996 /* Memory is 3 times as expensive as registers.
997 ??? Is that the right way to look at it? */
998 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
999 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1001 /* The cost of a branch insn. */
1002 /* ??? What's the right value here? Branches are certainly more
1003 expensive than reg->reg moves. */
1004 #define BRANCH_COST(speed_p, predictable_p) 2
1006 /* Scc sets the destination to 1 and then conditionally zeroes it.
1007 Best case, ORed SCCs can be made into clear - condset - condset.
1008 But it could also end up as five insns. So say it costs four on
1010 These extra instructions - and the second comparison - will also be
1011 an extra cost if the first comparison would have been decisive.
1012 So get an average saving, with a probability of the first branch
1013 beging decisive of p0, we want:
1014 p0 * (branch_cost - 4) > (1 - p0) * 5
1015 ??? We don't get to see that probability to evaluate, so we can
1016 only wildly guess that it might be 50%.
1017 ??? The compiler also lacks the notion of branch predictability. */
1018 #define LOGICAL_OP_NON_SHORT_CIRCUIT \
1019 (BRANCH_COST (optimize_function_for_speed_p (cfun), \
1022 /* Nonzero if access to memory by bytes is slow and undesirable.
1023 For RISC chips, it means that access to memory by bytes is no
1024 better than access by words when possible, so grab a whole word
1025 and maybe make use of that. */
1026 #define SLOW_BYTE_ACCESS 0
1028 /* Define this macro if it is as good or better to call a constant
1029 function address than to call an address kept in a register. */
1030 /* On the ARC, calling through registers is slow. */
1031 #define NO_FUNCTION_CSE 1
1033 /* Section selection. */
1034 /* WARNING: These section names also appear in dwarfout.c. */
1036 #define TEXT_SECTION_ASM_OP "\t.section\t.text"
1037 #define DATA_SECTION_ASM_OP "\t.section\t.data"
1039 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1040 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata"
1041 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss"
1043 /* Expression whose value is a string, including spacing, containing the
1044 assembler operation to identify the following data as initialization/termination
1045 code. If not defined, GCC will assume such a section does not exist. */
1046 #define INIT_SECTION_ASM_OP "\t.section\t.init"
1047 #define FINI_SECTION_ASM_OP "\t.section\t.fini"
1049 /* Define this macro if jump tables (for tablejump insns) should be
1050 output in the text section, along with the assembler instructions.
1051 Otherwise, the readonly data section is used.
1052 This macro is irrelevant if there is no separate readonly data section. */
1053 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic || CASE_VECTOR_PC_RELATIVE)
1055 /* For DWARF. Marginally different than default so output is "prettier"
1056 (and consistent with above). */
1057 #define PUSHSECTION_FORMAT "\t%s %s\n"
1059 /* Tell crtstuff.c we're using ELF. */
1060 #define OBJECT_FORMAT_ELF
1064 /* The register number of the register used to address a table of static
1065 data addresses in memory. In some cases this register is defined by a
1066 processor's ``application binary interface'' (ABI). When this macro
1067 is defined, RTL is generated for this register once, as with the stack
1068 pointer and frame pointer registers. If this macro is not defined, it
1069 is up to the machine-dependent files to allocate such a register (if
1071 #define PIC_OFFSET_TABLE_REGNUM 26
1073 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1074 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1076 /* This register is call-saved on the ARC. */
1077 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1079 /* A C expression that is nonzero if X is a legitimate immediate
1080 operand on the target machine when generating position independent code.
1081 You can assume that X satisfies CONSTANT_P, so you need not
1082 check this. You can also assume `flag_pic' is true, so you need not
1083 check it either. You need not define this macro if all constants
1084 (including SYMBOL_REF) can be immediate operands when generating
1085 position independent code. */
1086 #define LEGITIMATE_PIC_OPERAND_P(X) \
1087 (!arc_raw_symbolic_reference_mentioned_p ((X), true))
1089 /* PIC and small data don't mix on ARC because they use the same register. */
1090 #define SDATA_BASE_REGNUM 26
1092 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1094 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1097 /* Control the assembler format that we output. */
1099 /* A C string constant describing how to begin a comment in the target
1100 assembler language. The compiler assumes that the comment will
1101 end at the end of the line. */
1102 /* Gas needs this to be "#" in order to recognize line directives. */
1103 #define ASM_COMMENT_START "#"
1105 /* Output to assembler file text saying following lines
1106 may contain character constants, extra white space, comments, etc. */
1108 #define ASM_APP_ON ""
1110 /* Output to assembler file text saying following lines
1111 no longer contain unusual constructs. */
1113 #define ASM_APP_OFF ""
1115 /* Globalizing directive for a label. */
1116 #define GLOBAL_ASM_OP "\t.global\t"
1118 /* This is how to output an assembler line defining a `char' constant. */
1119 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
1120 ( fprintf (FILE, "\t.byte\t"), \
1121 output_addr_const (FILE, (VALUE)), \
1122 fprintf (FILE, "\n"))
1124 /* This is how to output an assembler line defining a `short' constant. */
1125 #define ASM_OUTPUT_SHORT(FILE, VALUE) \
1126 ( fprintf (FILE, "\t.hword\t"), \
1127 output_addr_const (FILE, (VALUE)), \
1128 fprintf (FILE, "\n"))
1130 /* This is how to output an assembler line defining an `int' constant.
1131 We also handle symbol output here. Code addresses must be right shifted
1132 by 2 because that's how the jump instruction wants them. */
1133 #define ASM_OUTPUT_INT(FILE, VALUE) \
1135 fprintf (FILE, "\t.word\t"); \
1136 if (GET_CODE (VALUE) == LABEL_REF) \
1138 fprintf (FILE, "%%st(@"); \
1139 output_addr_const (FILE, (VALUE)); \
1140 fprintf (FILE, ")"); \
1143 output_addr_const (FILE, (VALUE)); \
1144 fprintf (FILE, "\n"); \
1147 /* This is how to output an assembler line defining a `float' constant. */
1148 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \
1152 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1153 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
1154 fprintf (FILE, "\t.word\t0x%lx %s %s\n", \
1155 t, ASM_COMMENT_START, str); \
1158 /* This is how to output an assembler line defining a `double' constant. */
1159 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
1163 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1164 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
1165 fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n", \
1166 t[0], ASM_COMMENT_START, str, t[1]); \
1169 /* This is how to output the definition of a user-level label named NAME,
1170 such as the label on a static function or variable NAME. */
1171 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1172 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1174 #define ASM_NAME_P(NAME) ( NAME[0]=='*')
1176 /* This is how to output a reference to a user-level label named NAME.
1177 `assemble_name' uses this. */
1178 /* We work around a dwarfout.c deficiency by watching for labels from it and
1179 not adding the '_' prefix. There is a comment in
1180 dwarfout.c that says it should be using ASM_OUTPUT_INTERNAL_LABEL. */
1181 #define ASM_OUTPUT_LABELREF(FILE, NAME1) \
1184 NAME = (*targetm.strip_name_encoding)(NAME1); \
1185 if ((NAME)[0] == '.' && (NAME)[1] == 'L') \
1186 fprintf (FILE, "%s", NAME); \
1189 if (!ASM_NAME_P (NAME1)) \
1190 fprintf (FILE, "%s", user_label_prefix); \
1191 fprintf (FILE, "%s", NAME); \
1195 /* This is how to output a reference to a symbol_ref / label_ref as
1196 (part of) an operand. To disambiguate from register names like
1197 a1 / a2 / status etc, symbols are preceded by '@'. */
1198 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
1199 ASM_OUTPUT_LABEL_REF ((FILE), XSTR ((SYM), 0))
1200 #define ASM_OUTPUT_LABEL_REF(FILE,STR) \
1203 fputc ('@', file); \
1204 assemble_name ((FILE), (STR)); \
1208 /* Store in OUTPUT a string (made with alloca) containing
1209 an assembler-name for a local static variable named NAME.
1210 LABELNO is an integer which is different for each call. */
1211 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1212 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1213 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1215 /* The following macro defines the format used to output the second
1216 operand of the .type assembler directive. Different svr4 assemblers
1217 expect various different forms for this operand. The one given here
1218 is just a default. You may need to override it in your machine-
1219 specific tm.h file (depending upon the particulars of your assembler). */
1221 #undef TYPE_OPERAND_FMT
1222 #define TYPE_OPERAND_FMT "@%s"
1224 /* A C string containing the appropriate assembler directive to
1225 specify the size of a symbol, without any arguments. On systems
1226 that use ELF, the default (in `config/elfos.h') is `"\t.size\t"';
1227 on other systems, the default is not to define this macro. */
1229 #define SIZE_ASM_OP "\t.size\t"
1231 /* Assembler pseudo-op to equate one value with another. */
1232 /* ??? This is needed because dwarfout.c provides a default definition too
1233 late for defaults.h (which contains the default definition of ASM_OTPUT_DEF
1238 #define SET_ASM_OP "\t.set\t"
1240 extern char rname29
[], rname30
[];
1241 extern char rname56
[], rname57
[], rname58
[], rname59
[];
1242 /* How to refer to registers in assembler output.
1243 This sequence is indexed by compiler's hard-register-number (see above). */
1244 #define REGISTER_NAMES \
1245 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1246 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1247 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
1248 "r24", "r25", "gp", "fp", "sp", rname29, rname30, "blink", \
1249 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
1250 "d1", "d1", "d2", "d2", "r44", "r45", "r46", "r47", \
1251 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
1252 rname56,rname57,rname58,rname59,"lp_count", "cc", "ap", "pcl", \
1253 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", \
1254 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", \
1255 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", \
1256 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31", \
1257 "vr32", "vr33", "vr34", "vr35", "vr36", "vr37", "vr38", "vr39", \
1258 "vr40", "vr41", "vr42", "vr43", "vr44", "vr45", "vr46", "vr47", \
1259 "vr48", "vr49", "vr50", "vr51", "vr52", "vr53", "vr54", "vr55", \
1260 "vr56", "vr57", "vr58", "vr59", "vr60", "vr61", "vr62", "vr63", \
1261 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \
1262 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \
1263 "lp_start", "lp_end" \
1266 #define ADDITIONAL_REGISTER_NAMES \
1273 /* Entry to the insn conditionalizer. */
1274 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1275 arc_final_prescan_insn (INSN, OPVEC, NOPERANDS)
1277 /* A C expression which evaluates to true if CODE is a valid
1278 punctuation character for use in the `PRINT_OPERAND' macro. */
1279 extern char arc_punct_chars
[];
1280 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1281 arc_punct_chars[(unsigned char) (CHAR)]
1283 /* Print operand X (an rtx) in assembler syntax to file FILE.
1284 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1285 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1286 #define PRINT_OPERAND(FILE, X, CODE) \
1287 arc_print_operand (FILE, X, CODE)
1289 /* A C compound statement to output to stdio stream STREAM the
1290 assembler syntax for an instruction operand that is a memory
1291 reference whose address is ADDR. ADDR is an RTL expression.
1293 On some machines, the syntax for a symbolic address depends on
1294 the section that the address refers to. On these machines,
1295 define the macro `ENCODE_SECTION_INFO' to store the information
1296 into the `symbol_ref', and then check for it here. */
1297 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1298 arc_print_operand_address (FILE, ADDR)
1300 /* This is how to output an element of a case-vector that is absolute. */
1301 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1304 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1305 fprintf (FILE, "\t.word "); \
1306 assemble_name (FILE, label); \
1307 fprintf(FILE, "\n"); \
1310 /* This is how to output an element of a case-vector that is relative. */
1311 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1314 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1315 switch (GET_MODE (BODY)) \
1317 case E_QImode: fprintf (FILE, "\t.byte "); break; \
1318 case E_HImode: fprintf (FILE, "\t.hword "); break; \
1319 case E_SImode: fprintf (FILE, "\t.word "); break; \
1320 default: gcc_unreachable (); \
1322 assemble_name (FILE, label); \
1323 fprintf (FILE, "-"); \
1324 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1325 assemble_name (FILE, label); \
1326 if (TARGET_COMPACT_CASESI) \
1327 fprintf (FILE, " + %d", 4 + arc_get_unalign ()); \
1328 fprintf(FILE, "\n"); \
1331 /* ADDR_DIFF_VECs are in the text section and thus can affect the
1332 current alignment. */
1333 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
1336 if (GET_CODE (PATTERN (JUMPTABLE)) == ADDR_DIFF_VEC \
1337 && ((GET_MODE_SIZE (GET_MODE (PATTERN (JUMPTABLE))) \
1338 * XVECLEN (PATTERN (JUMPTABLE), 1) + 1) \
1340 arc_toggle_unalign (); \
1344 #define JUMP_ALIGN(LABEL) (arc_size_opt_level < 2 ? 2 : 0)
1345 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
1346 (JUMP_ALIGN(LABEL) \
1347 ? JUMP_ALIGN(LABEL) \
1348 : GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \
1350 /* The desired alignment for the location counter at the beginning
1352 /* On the ARC, align loops to 4 byte boundaries unless doing all-out size
1354 #define LOOP_ALIGN JUMP_ALIGN
1356 #define LABEL_ALIGN(LABEL) (arc_label_align (LABEL))
1358 /* This is how to output an assembler line
1359 that says to advance the location counter
1360 to a multiple of 2**LOG bytes. */
1361 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1363 if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1365 arc_clear_unalign (); \
1368 /* ASM_OUTPUT_ALIGNED_DECL_LOCAL (STREAM, DECL, NAME, SIZE, ALIGNMENT)
1369 Define this macro when you need to see the variable's decl in order to
1370 chose what to output. */
1371 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
1372 arc_asm_output_aligned_decl_local (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
1374 /* Debugging information. */
1376 /* Generate DBX and DWARF debugging information. */
1377 #ifdef DBX_DEBUGGING_INFO
1378 #undef DBX_DEBUGGING_INFO
1380 #define DBX_DEBUGGING_INFO
1382 #ifdef DWARF2_DEBUGGING_INFO
1383 #undef DWARF2_DEBUGGING_INFO
1385 #define DWARF2_DEBUGGING_INFO
1387 /* Prefer STABS (for now). */
1388 #undef PREFERRED_DEBUGGING_TYPE
1389 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1391 /* How to renumber registers for dbx and gdb. */
1392 #define DBX_REGISTER_NUMBER(REGNO) \
1393 ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \
1394 ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \
1395 : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 59) \
1398 : ((REGNO) & 1) ^ TARGET_BIG_ENDIAN \
1400 : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \
1403 #define DWARF_FRAME_REGNUM(REG) (REG)
1405 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (31)
1407 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 31)
1411 #define EH_RETURN_DATA_REGNO(N) \
1412 ((N) < 4 ? (N) : INVALID_REGNUM)
1414 /* Turn off splitting of long stabs. */
1415 #define DBX_CONTIN_LENGTH 0
1417 /* Miscellaneous. */
1419 /* Specify the machine mode that this machine uses
1420 for the index in the tablejump instruction.
1421 If we have pc relative case vectors, we start the case vector shortening
1423 #define CASE_VECTOR_MODE \
1424 ((optimize && (CASE_VECTOR_PC_RELATIVE || flag_pic)) ? QImode : Pmode)
1426 /* Define as C expression which evaluates to nonzero if the tablejump
1427 instruction expects the table to contain offsets from the address of the
1429 Do not define this if the table should contain absolute addresses. */
1430 #define CASE_VECTOR_PC_RELATIVE TARGET_CASE_VECTOR_PC_RELATIVE
1432 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1433 CASE_VECTOR_SHORTEN_MODE_1 \
1434 (MIN_OFFSET, TARGET_COMPACT_CASESI ? MAX_OFFSET + 6 : MAX_OFFSET, BODY)
1436 #define CASE_VECTOR_SHORTEN_MODE_1(MIN_OFFSET, MAX_OFFSET, BODY) \
1437 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1438 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1439 : (MIN_OFFSET) >= -128 && (MAX_OFFSET) <= 127 \
1440 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1441 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 65535 \
1442 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, HImode) \
1443 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 \
1444 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, HImode) \
1447 #define ADDR_VEC_ALIGN(VEC_INSN) \
1448 (exact_log2 (GET_MODE_SIZE (GET_MODE (PATTERN (VEC_INSN)))))
1449 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
1450 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) \
1451 ASM_OUTPUT_ALIGN ((FILE), ADDR_VEC_ALIGN (TABLE));
1453 #define INSN_LENGTH_ALIGNMENT(INSN) \
1454 ((JUMP_TABLE_DATA_P (INSN) \
1455 && GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC \
1456 && GET_MODE (PATTERN (INSN)) == QImode) \
1457 ? 0 : length_unit_log)
1459 /* Define if operations between registers always perform the operation
1460 on the full register even if a narrower mode is specified. */
1461 #define WORD_REGISTER_OPERATIONS 1
1463 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1464 will either zero-extend or sign-extend. The value of this macro should
1465 be the code that says which one of the two operations is implicitly
1466 done, NIL if none. */
1467 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1470 /* Max number of bytes we can move from memory to memory
1471 in one reasonably fast instruction. */
1474 /* Undo the effects of the movmem pattern presence on STORE_BY_PIECES_P . */
1475 #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3)
1477 /* Define this to be nonzero if shift instructions ignore all but the
1480 #define SHIFT_COUNT_TRUNCATED 1
1482 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1483 is done just by pretending it is already truncated. */
1484 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1486 /* We assume that the store-condition-codes instructions store 0 for false
1487 and some other value for true. This is the value stored for true. */
1488 #define STORE_FLAG_VALUE 1
1490 /* Specify the machine mode that pointers have.
1491 After generation of rtl, the compiler makes no further distinction
1492 between pointers and any other objects of this machine mode. */
1493 /* ARCompact has full 32-bit pointers. */
1494 #define Pmode SImode
1496 /* A function address in a call instruction. */
1497 #define FUNCTION_MODE SImode
1499 /* Define the information needed to generate branch and scc insns. This is
1500 stored from the compare operation. Note that we can't use "rtx" here
1501 since it hasn't been defined! */
1502 extern struct rtx_def
*arc_compare_op0
, *arc_compare_op1
;
1504 /* ARC function types. */
1505 enum arc_function_type
{
1506 /* No function should have the unknown type. This value is used to
1507 indicate the that function type has not yet been computed. */
1508 ARC_FUNCTION_UNKNOWN
= 0,
1510 /* The normal function type indicates that the function has the
1511 standard prologue and epilogue. */
1512 ARC_FUNCTION_NORMAL
= 1 << 0,
1513 /* These are interrupt handlers. The name corresponds to the register
1514 name that contains the return address. */
1515 ARC_FUNCTION_ILINK1
= 1 << 1,
1516 ARC_FUNCTION_ILINK2
= 1 << 2,
1517 /* Fast interrupt is only available on ARCv2 processors. */
1518 ARC_FUNCTION_FIRQ
= 1 << 3,
1519 /* The naked function type indicates that the function does not have
1520 prologue or epilogue, and that no stack frame is available. */
1521 ARC_FUNCTION_NAKED
= 1 << 4
1524 /* Check if a function is an interrupt function. */
1525 #define ARC_INTERRUPT_P(TYPE) \
1526 (((TYPE) & (ARC_FUNCTION_ILINK1 | ARC_FUNCTION_ILINK2 \
1527 | ARC_FUNCTION_FIRQ)) != 0)
1529 /* Check if a function is a fast interrupt function. */
1530 #define ARC_FAST_INTERRUPT_P(TYPE) (((TYPE) & ARC_FUNCTION_FIRQ) != 0)
1532 /* Check if a function is normal, that is, has standard prologue and
1534 #define ARC_NORMAL_P(TYPE) (((TYPE) & ARC_FUNCTION_NORMAL) != 0)
1536 /* Check if a function is naked. */
1537 #define ARC_NAKED_P(TYPE) (((TYPE) & ARC_FUNCTION_NAKED) != 0)
1539 /* Called by crtstuff.c to make calls to function FUNCTION that are defined in
1540 SECTION_OP, and then to switch back to text section. */
1541 #undef CRT_CALL_STATIC_FUNCTION
1542 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1543 asm (SECTION_OP "\n\t" \
1544 "add r12,pcl,@" USER_LABEL_PREFIX #FUNC "@pcl\n\t" \
1546 TEXT_SECTION_ASM_OP);
1548 /* This macro expands to the name of the scratch register r12, used for
1549 temporary calculations according to the ABI. */
1550 #define ARC_TEMP_SCRATCH_REG "r12"
1552 /* The C++ compiler must use one bit to indicate whether the function
1553 that will be called through a pointer-to-member-function is
1554 virtual. Normally, we assume that the low-order bit of a function
1555 pointer must always be zero. Then, by ensuring that the
1556 vtable_index is odd, we can distinguish which variant of the union
1557 is in use. But, on some platforms function pointers can be odd,
1558 and so this doesn't work. In that case, we use the low-order bit
1559 of the `delta' field, and shift the remainder of the `delta' field
1560 to the left. We needed to do this for A4 because the address was always
1561 shifted and thus could be odd. */
1562 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
1563 (ptrmemfunc_vbit_in_pfn)
1565 #define INSN_SETS_ARE_DELAYED(X) \
1566 (GET_CODE (X) == INSN \
1567 && GET_CODE (PATTERN (X)) != SEQUENCE \
1568 && GET_CODE (PATTERN (X)) != USE \
1569 && GET_CODE (PATTERN (X)) != CLOBBER \
1570 && (get_attr_type (X) == TYPE_CALL || get_attr_type (X) == TYPE_SFUNC))
1572 #define INSN_REFERENCES_ARE_DELAYED(insn) \
1573 (INSN_SETS_ARE_DELAYED (insn))
1575 #define CALL_ATTR(X, NAME) \
1576 ((CALL_P (X) || NONJUMP_INSN_P (X)) \
1577 && GET_CODE (PATTERN (X)) != USE \
1578 && GET_CODE (PATTERN (X)) != CLOBBER \
1579 && get_attr_is_##NAME (X) == IS_##NAME##_YES) \
1581 #define REVERSE_CONDITION(CODE,MODE) \
1582 (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \
1583 || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \
1584 || (MODE) == CC_FPXmode || (MODE) == CC_FPU_UNEQmode \
1585 || (MODE) == CC_FPUmode) \
1586 ? reverse_condition_maybe_unordered ((CODE)) \
1587 : reverse_condition ((CODE)))
1589 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1591 = (GET_CODE (PATTERN (X)) == SEQUENCE \
1593 + arc_adjust_insn_length ( \
1594 as_a <rtx_sequence *> (PATTERN (X))->insn (0), \
1595 get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)), \
1597 - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)) \
1598 + arc_adjust_insn_length ( \
1599 as_a <rtx_sequence *> (PATTERN (X))->insn (1), \
1600 get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1)), \
1602 - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1))) \
1603 : arc_adjust_insn_length ((X), (LENGTH), false)))
1605 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C,STR) ((C) == '`')
1607 #define INIT_EXPANDERS arc_init_expanders ()
1611 ARC_LRA_PRIORITY_NONE
, ARC_LRA_PRIORITY_NONCOMPACT
, ARC_LRA_PRIORITY_COMPACT
1614 /* The define_cond_exec construct is rather crude, as we can't have
1615 different ones with different conditions apply to different sets
1616 of instructions. We can't use an attribute test inside the condition,
1617 because that would lead to infinite recursion as the attribute test
1618 needs to recognize the insn. So, instead we have a clause for
1619 the pattern condition of all sfunc patterns which is only relevant for
1620 the predicated varaint. */
1621 #define SFUNC_CHECK_PREDICABLE \
1622 (GET_CODE (PATTERN (insn)) != COND_EXEC || !flag_pic || !TARGET_MEDIUM_CALLS)
1624 /* MPYW feature macro. Only valid for ARCHS and ARCEM cores. */
1625 #define TARGET_MPYW ((arc_mpy_option > 0) && TARGET_V2)
1626 /* Full ARCv2 multiplication feature macro. */
1627 #define TARGET_MULTI ((arc_mpy_option > 1) && TARGET_V2)
1628 /* General MPY feature macro. */
1629 #define TARGET_MPY ((TARGET_ARC700 && (!TARGET_NOMPY_SET)) || TARGET_MULTI)
1630 /* ARC700 MPY feature macro. */
1631 #define TARGET_ARC700_MPY (TARGET_ARC700 && (!TARGET_NOMPY_SET))
1632 /* Any multiplication feature macro. */
1633 #define TARGET_ANY_MPY \
1634 (TARGET_MPY || TARGET_MUL64_SET || TARGET_MULMAC_32BY16_SET)
1635 /* PLUS_DMPY feature macro. */
1636 #define TARGET_PLUS_DMPY ((arc_mpy_option > 6) && TARGET_HS)
1637 /* PLUS_MACD feature macro. */
1638 #define TARGET_PLUS_MACD ((arc_mpy_option > 7) && TARGET_HS)
1639 /* PLUS_QMACW feature macro. */
1640 #define TARGET_PLUS_QMACW ((arc_mpy_option > 8) && TARGET_HS)
1642 /* ARC600 and ARC601 feature macro. */
1643 #define TARGET_ARC600_FAMILY (TARGET_ARC600 || TARGET_ARC601)
1644 /* ARC600, ARC601 and ARC700 feature macro. */
1645 #define TARGET_ARCOMPACT_FAMILY \
1646 (TARGET_ARC600 || TARGET_ARC601 || TARGET_ARC700)
1647 /* Loop count register can be read in very next instruction after has
1648 been written to by an ordinary instruction. */
1649 #define TARGET_LP_WR_INTERLOCK (!TARGET_ARC600_FAMILY)
1652 /* Any FPU support. */
1653 #define TARGET_HARD_FLOAT ((arc_fpu_build & (FPU_SP | FPU_DP)) != 0)
1654 /* Single precision floating point support. */
1655 #define TARGET_FP_SP_BASE ((arc_fpu_build & FPU_SP) != 0)
1656 /* Double precision floating point support. */
1657 #define TARGET_FP_DP_BASE ((arc_fpu_build & FPU_DP) != 0)
1658 /* Single precision floating point support with fused operation. */
1659 #define TARGET_FP_SP_FUSED ((arc_fpu_build & FPU_SF) != 0)
1660 /* Double precision floating point support with fused operation. */
1661 #define TARGET_FP_DP_FUSED ((arc_fpu_build & FPU_DF) != 0)
1662 /* Single precision floating point conversion instruction support. */
1663 #define TARGET_FP_SP_CONV ((arc_fpu_build & FPU_SC) != 0)
1664 /* Double precision floating point conversion instruction support. */
1665 #define TARGET_FP_DP_CONV ((arc_fpu_build & FPU_DC) != 0)
1666 /* Single precision floating point SQRT/DIV instruction support. */
1667 #define TARGET_FP_SP_SQRT ((arc_fpu_build & FPU_SD) != 0)
1668 /* Double precision floating point SQRT/DIV instruction support. */
1669 #define TARGET_FP_DP_SQRT ((arc_fpu_build & FPU_DD) != 0)
1670 /* Double precision floating point assist instruction support. */
1671 #define TARGET_FP_DP_AX ((arc_fpu_build & FPX_DP) != 0)
1672 /* Custom FP instructions used by QuarkSE EM cpu. */
1673 #define TARGET_FPX_QUARK (TARGET_EM && TARGET_SPFP \
1674 && (arc_fpu_build == FPX_QK))
1676 #endif /* GCC_ARC_H */