gcc/config/arc/arc.opt

   1 ; Options for the Synopsys DesignWare ARC port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2015 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/arc/arc-opts.h
  23
  24 mbig-endian
  25 Target Report RejectNegative Mask(BIG_ENDIAN)
  26 Compile code for big endian mode.
  27
  28 mlittle-endian
  29 Target Report RejectNegative InverseMask(BIG_ENDIAN)
  30 Compile code for little endian mode.  This is the default.
  31
  32 mno-cond-exec
  33 Target Report RejectNegative Mask(NO_COND_EXEC)
  34 Disable ARCompact specific pass to generate conditional execution instructions.
  35
  36 mA6
  37 Target Report
  38 Generate ARCompact 32-bit code for ARC600 processor.
  39
  40 mARC600
  41 Target Report
  42 Same as -mA6.
  43
  44 mARC601
  45 Target Report
  46 Generate ARCompact 32-bit code for ARC601 processor.
  47
  48 mA7
  49 Target Report
  50 Generate ARCompact 32-bit code for ARC700 processor.
  51
  52 mARC700
  53 Target Report
  54 Same as -mA7.
  55
  56 mmixed-code
  57 Target Report Mask(MIXED_CODE_SET)
  58 Tweak register allocation to help 16-bit instruction generation.
  59 ; originally this was:
  60 ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
  61 ; but we do that without -mmixed-code, too, it's just a different instruction
  62 ; count / size tradeoff.
  63
  64 ; We use an explict definition for the negative form because that is the
  65 ; actually interesting option, and we want that to have its own comment.
  66 mvolatile-cache
  67 Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
  68 Use ordinarily cached memory accesses for volatile references.
  69
  70 mno-volatile-cache
  71 Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
  72 Enable cache bypass for volatile references.
  73
  74 mbarrel-shifter
  75 Target Report Mask(BARREL_SHIFTER)
  76 Generate instructions supported by barrel shifter.
  77
  78 mnorm
  79 Target Report Mask(NORM_SET)
  80 Generate norm instruction.
  81
  82 mswap
  83 Target Report Mask(SWAP_SET)
  84 Generate swap instruction.
  85
  86 mmul64
  87 Target Report Mask(MUL64_SET)
  88 Generate mul64 and mulu64 instructions.
  89
  90 mno-mpy
  91 Target Report Mask(NOMPY_SET)
  92 Do not generate mpy instructions for ARC700.
  93
  94 mea
  95 Target Report Mask(EA_SET)
  96 Generate Extended arithmetic instructions.  Currently only divaw, adds, subs and sat16 are supported.
  97
  98 msoft-float
  99 Target Report Mask(0)
 100 Dummy flag. This is the default unless FPX switches are provided explicitly.
 101
 102 mlong-calls
 103 Target Report Mask(LONG_CALLS_SET)
 104 Generate call insns as register indirect calls.
 105
 106 mno-brcc
 107 Target Report Mask(NO_BRCC_SET)
 108 Do no generate BRcc instructions in arc_reorg.
 109
 110 msdata
 111 Target Report InverseMask(NO_SDATA_SET)
 112 Generate sdata references.  This is the default, unless you compile for PIC.
 113
 114 mno-millicode
 115 Target Report Mask(NO_MILLICODE_THUNK_SET)
 116 Do not generate millicode thunks (needed only with -Os).
 117
 118 mspfp
 119 Target Report Mask(SPFP_COMPACT_SET)
 120 FPX: Generate Single Precision FPX (compact) instructions.
 121
 122 mspfp-compact
 123 Target Report Mask(SPFP_COMPACT_SET) MaskExists
 124 FPX: Generate Single Precision FPX (compact) instructions.
 125
 126 mspfp-fast
 127 Target Report Mask(SPFP_FAST_SET)
 128 FPX: Generate Single Precision FPX (fast) instructions.
 129
 130 margonaut
 131 Target Report Mask(ARGONAUT_SET)
 132 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
 133
 134 mdpfp
 135 Target Report Mask(DPFP_COMPACT_SET)
 136 FPX: Generate Double Precision FPX (compact) instructions.
 137
 138 mdpfp-compact
 139 Target Report Mask(DPFP_COMPACT_SET) MaskExists
 140 FPX: Generate Double Precision FPX (compact) instructions.
 141
 142 mdpfp-fast
 143 Target Report Mask(DPFP_FAST_SET)
 144 FPX: Generate Double Precision FPX (fast) instructions.
 145
 146 mno-dpfp-lrsr
 147 Target Report Mask(DPFP_DISABLE_LRSR)
 148 Disable LR and SR instructions from using FPX extension aux registers.
 149
 150 msimd
 151 Target Report Mask(SIMD_SET)
 152 Enable generation of ARC SIMD instructions via target-specific builtins.
 153
 154 mcpu=
 155 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
 156 -mcpu=CPU       Compile code for ARC variant CPU.
 157
 158 Enum
 159 Name(processor_type) Type(enum processor_type)
 160
 161 EnumValue
 162 Enum(processor_type) String(ARC600) Value(PROCESSOR_ARC600)
 163
 164 EnumValue
 165 Enum(processor_type) String(ARC601) Value(PROCESSOR_ARC601)
 166
 167 EnumValue
 168 Enum(processor_type) String(ARC700) Value(PROCESSOR_ARC700)
 169
 170 msize-level=
 171 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
 172 size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
 173
 174 misize
 175 Target Report PchIgnore Var(TARGET_DUMPISIZE)
 176 Annotate assembler instructions with estimated addresses.
 177
 178 mmultcost=
 179 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
 180 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
 181
 182 mtune=ARC600
 183 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 184 Tune for ARC600 cpu.
 185
 186 mtune=ARC601
 187 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 188 Tune for ARC601 cpu.
 189
 190 mtune=ARC700
 191 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD)
 192 Tune for ARC700 R4.2 Cpu with standard multiplier block.
 193
 194 mtune=ARC700-xmac
 195 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 196 Tune for ARC700 R4.2 Cpu with XMAC block.
 197
 198 mtune=ARC725D
 199 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 200 Tune for ARC700 R4.2 Cpu with XMAC block.
 201
 202 mtune=ARC750D
 203 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 204 Tune for ARC700 R4.2 Cpu with XMAC block.
 205
 206 mindexed-loads
 207 Target Var(TARGET_INDEXED_LOADS)
 208 Enable the use of indexed loads.
 209
 210 mauto-modify-reg
 211 Target Var(TARGET_AUTO_MODIFY_REG)
 212 Enable the use of pre/post modify with register displacement.
 213
 214 mmul32x16
 215 Target Report Mask(MULMAC_32BY16_SET)
 216 Generate 32x16 multiply and mac instructions.
 217
 218 ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
 219 ; alas, basic-block.h is not included in options.c .
 220 munalign-prob-threshold=
 221 Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
 222 Set probability threshold for unaligning branches.
 223
 224 mmedium-calls
 225 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
 226 Don't use less than 25 bit addressing range for calls.
 227
 228 mannotate-align
 229 Target Var(TARGET_ANNOTATE_ALIGN)
 230 Explain what alignment considerations lead to the decision to make an insn short or long.
 231
 232 malign-call
 233 Target Var(TARGET_ALIGN_CALL)
 234 Do alignment optimizations for call instructions.
 235
 236 mRcq
 237 Target Var(TARGET_Rcq)
 238 Enable Rcq constraint handling - most short code generation depends on this.
 239
 240 mRcw
 241 Target Var(TARGET_Rcw)
 242 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
 243
 244 mearly-cbranchsi
 245 Target Var(TARGET_EARLY_CBRANCHSI)
 246 Enable pre-reload use of cbranchsi pattern.
 247
 248 mbbit-peephole
 249 Target Var(TARGET_BBIT_PEEPHOLE)
 250 Enable bbit peephole2.
 251
 252 mcase-vector-pcrel
 253 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
 254 Use pc-relative switch case tables - this enables case table shortening.
 255
 256 mcompact-casesi
 257 Target Var(TARGET_COMPACT_CASESI)
 258 Enable compact casesi pattern.
 259
 260 mq-class
 261 Target Var(TARGET_Q_CLASS)
 262 Enable 'q' instruction alternatives.
 263
 264 mexpand-adddi
 265 Target Var(TARGET_EXPAND_ADDDI)
 266 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
 267
 268
 269 ; Flags used by the assembler, but for which we define preprocessor
 270 ; macro symbols as well.
 271 mcrc
 272 Target Report
 273 Enable variable polynomial CRC extension.
 274
 275 mdsp-packa
 276 Target Report
 277 Enable DSP 3.1 Pack A extensions.
 278
 279 mdvbf
 280 Target Report
 281 Enable dual viterbi butterfly extension.
 282
 283 mmac-d16
 284 Target Report Undocumented
 285
 286 mmac-24
 287 Target Report Undocumented
 288
 289 mtelephony
 290 Target Report RejectNegative
 291 Enable Dual and Single Operand Instructions for Telephony.
 292
 293 mxy
 294 Target Report
 295 Enable XY Memory extension (DSP version 3).
 296
 297 ; ARC700 4.10 extension instructions
 298 mlock
 299 Target Report
 300 Enable Locked Load/Store Conditional extension.
 301
 302 mswape
 303 Target Report
 304 Enable swap byte ordering extension instruction.
 305
 306 mrtsc
 307 Target Report
 308 Enable 64-bit Time-Stamp Counter extension instruction.
 309
 310 mno-epilogue-cfi
 311 Target Report RejectNegative InverseMask(EPILOGUE_CFI)
 312 Disable generation of cfi for epilogues.
 313
 314 mepilogue-cfi
 315 Target RejectNegative Mask(EPILOGUE_CFI)
 316 Enable generation of cfi for epilogues.
 317
 318 EB
 319 Target
 320 Pass -EB option through to linker.
 321
 322 EL
 323 Target
 324 Pass -EL option through to linker.
 325
 326 marclinux
 327 target
 328 Pass -marclinux option through to linker.
 329
 330 marclinux_prof
 331 target
 332 Pass -marclinux_prof option through to linker.
 333
 334 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
 335 ;Target InverseMask(NO_LRA)
 336 ; lra still won't allow to configure libgcc; see PR rtl-optimization/55464.
 337 ; so don't enable by default.
 338 mlra
 339 Target Mask(LRA)
 340 Enable lra.
 341
 342 mlra-priority-none
 343 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
 344 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
 345
 346 mlra-priority-compact
 347 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
 348 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 349
 350 mlra-priority-noncompact
 351 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
 352 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
 353
 354 mucb-mcount
 355 Target Report Var(TARGET_UCB_MCOUNT)
 356 instrument with mcount calls as in the ucb code.
 357
 358 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
 359
 360 mEA
 361 Target
 362
 363 multcost=
 364 Target RejectNegative Joined
 365
 366 ; Unfortunately, listing the full option name gives us clashes
 367 ; with OPT_opt_name being claimed for both opt_name and opt-name,
 368 ; so we leave out the last character or more.
 369 mbarrel_shifte
 370 Target Joined
 371
 372 mspfp_
 373 Target Joined
 374
 375 mdpfp_
 376 Target Joined
 377
 378 mdsp_pack
 379 Target Joined
 380
 381 mmac_
 382 Target Joined
 383