1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 /* Forward definitions of types. */
53 typedef struct minipool_node Mnode
;
54 typedef struct minipool_fixup Mfix
;
56 /* In order to improve the layout of the prototypes below
57 some short type abbreviations are defined here. */
58 #define Hint HOST_WIDE_INT
59 #define Mmode enum machine_mode
60 #define Ulong unsigned long
61 #define Ccstar const char *
63 const struct attribute_spec arm_attribute_table
[];
65 /* Forward function declarations. */
66 static void arm_add_gc_roots
PARAMS ((void));
67 static int arm_gen_constant
PARAMS ((enum rtx_code
, Mmode
, Hint
, rtx
, rtx
, int, int));
68 static Ulong bit_count
PARAMS ((signed int));
69 static int const_ok_for_op
PARAMS ((Hint
, enum rtx_code
));
70 static int eliminate_lr2ip
PARAMS ((rtx
*));
71 static rtx emit_multi_reg_push
PARAMS ((int));
72 static rtx emit_sfm
PARAMS ((int, int));
74 static bool arm_assemble_integer
PARAMS ((rtx
, unsigned int, int));
76 static Ccstar fp_const_from_val
PARAMS ((REAL_VALUE_TYPE
*));
77 static arm_cc get_arm_condition_code
PARAMS ((rtx
));
78 static void init_fpa_table
PARAMS ((void));
79 static Hint int_log2
PARAMS ((Hint
));
80 static rtx is_jump_table
PARAMS ((rtx
));
81 static Ccstar output_multi_immediate
PARAMS ((rtx
*, Ccstar
, Ccstar
, int, Hint
));
82 static void print_multi_reg
PARAMS ((FILE *, Ccstar
, int, int));
83 static Mmode select_dominance_cc_mode
PARAMS ((rtx
, rtx
, Hint
));
84 static Ccstar shift_op
PARAMS ((rtx
, Hint
*));
85 static void arm_init_machine_status
PARAMS ((struct function
*));
86 static void arm_mark_machine_status
PARAMS ((struct function
*));
87 static void arm_free_machine_status
PARAMS ((struct function
*));
88 static int number_of_first_bit_set
PARAMS ((int));
89 static void replace_symbols_in_block
PARAMS ((tree
, rtx
, rtx
));
90 static void thumb_exit
PARAMS ((FILE *, int, rtx
));
91 static void thumb_pushpop
PARAMS ((FILE *, int, int));
92 static Ccstar thumb_condition_code
PARAMS ((rtx
, int));
93 static rtx is_jump_table
PARAMS ((rtx
));
94 static Hint get_jump_table_size
PARAMS ((rtx
));
95 static Mnode
* move_minipool_fix_forward_ref
PARAMS ((Mnode
*, Mnode
*, Hint
));
96 static Mnode
* add_minipool_forward_ref
PARAMS ((Mfix
*));
97 static Mnode
* move_minipool_fix_backward_ref
PARAMS ((Mnode
*, Mnode
*, Hint
));
98 static Mnode
* add_minipool_backward_ref
PARAMS ((Mfix
*));
99 static void assign_minipool_offsets
PARAMS ((Mfix
*));
100 static void arm_print_value
PARAMS ((FILE *, rtx
));
101 static void dump_minipool
PARAMS ((rtx
));
102 static int arm_barrier_cost
PARAMS ((rtx
));
103 static Mfix
* create_fix_barrier
PARAMS ((Mfix
*, Hint
));
104 static void push_minipool_barrier
PARAMS ((rtx
, Hint
));
105 static void push_minipool_fix
PARAMS ((rtx
, Hint
, rtx
*, Mmode
, rtx
));
106 static void note_invalid_constants
PARAMS ((rtx
, Hint
));
107 static int current_file_function_operand
PARAMS ((rtx
));
108 static Ulong arm_compute_save_reg0_reg12_mask
PARAMS ((void));
109 static Ulong arm_compute_save_reg_mask
PARAMS ((void));
110 static Ulong arm_isr_value
PARAMS ((tree
));
111 static Ulong arm_compute_func_type
PARAMS ((void));
112 static tree arm_handle_fndecl_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
113 static tree arm_handle_isr_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
114 static void arm_output_function_epilogue
PARAMS ((FILE *, Hint
));
115 static void arm_output_function_prologue
PARAMS ((FILE *, Hint
));
116 static void thumb_output_function_prologue
PARAMS ((FILE *, Hint
));
117 static int arm_comp_type_attributes
PARAMS ((tree
, tree
));
118 static void arm_set_default_type_attributes
PARAMS ((tree
));
119 static int arm_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
120 #ifdef OBJECT_FORMAT_ELF
121 static void arm_elf_asm_named_section
PARAMS ((const char *, unsigned int));
124 static void arm_encode_section_info
PARAMS ((tree
, int));
132 /* Initialize the GCC target structure. */
133 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
134 #undef TARGET_MERGE_DECL_ATTRIBUTES
135 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
138 #undef TARGET_ATTRIBUTE_TABLE
139 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
142 #undef TARGET_ASM_BYTE_OP
143 #define TARGET_ASM_BYTE_OP "\tDCB\t"
144 #undef TARGET_ASM_ALIGNED_HI_OP
145 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
146 #undef TARGET_ASM_ALIGNED_SI_OP
147 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
149 #undef TARGET_ASM_ALIGNED_SI_OP
150 #define TARGET_ASM_ALIGNED_SI_OP NULL
151 #undef TARGET_ASM_INTEGER
152 #define TARGET_ASM_INTEGER arm_assemble_integer
155 #undef TARGET_ASM_FUNCTION_PROLOGUE
156 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
158 #undef TARGET_ASM_FUNCTION_EPILOGUE
159 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
161 #undef TARGET_COMP_TYPE_ATTRIBUTES
162 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
164 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
165 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
167 #undef TARGET_INIT_BUILTINS
168 #define TARGET_INIT_BUILTINS arm_init_builtins
170 #undef TARGET_EXPAND_BUILTIN
171 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
173 #undef TARGET_SCHED_ADJUST_COST
174 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
176 #undef TARGET_ENCODE_SECTION_INFO
178 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
180 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
183 #undef TARGET_STRIP_NAME_ENCODING
184 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
186 struct gcc_target targetm
= TARGET_INITIALIZER
;
188 /* Obstack for minipool constant handling. */
189 static struct obstack minipool_obstack
;
190 static char * minipool_startobj
;
192 #define obstack_chunk_alloc xmalloc
193 #define obstack_chunk_free free
195 /* The maximum number of insns skipped which
196 will be conditionalised if possible. */
197 static int max_insns_skipped
= 5;
199 extern FILE * asm_out_file
;
201 /* True if we are currently building a constant table. */
202 int making_const_table
;
204 /* Define the information needed to generate branch insns. This is
205 stored from the compare operation. */
206 rtx arm_compare_op0
, arm_compare_op1
;
208 /* What type of floating point are we tuning for? */
209 enum floating_point_type arm_fpu
;
211 /* What type of floating point instructions are available? */
212 enum floating_point_type arm_fpu_arch
;
214 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
215 enum prog_mode_type arm_prgmode
;
217 /* Set by the -mfp=... option. */
218 const char * target_fp_name
= NULL
;
220 /* Used to parse -mstructure_size_boundary command line option. */
221 const char * structure_size_string
= NULL
;
222 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
224 /* Bit values used to identify processor capabilities. */
225 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
226 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
227 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
228 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
229 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
230 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
231 #define FL_THUMB (1 << 6) /* Thumb aware */
232 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
233 #define FL_STRONG (1 << 8) /* StrongARM */
234 #define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */
235 #define FL_XSCALE (1 << 10) /* XScale */
237 /* The bits in this mask specify which
238 instructions we are allowed to generate. */
239 static int insn_flags
= 0;
241 /* The bits in this mask specify which instruction scheduling options should
242 be used. Note - there is an overlap with the FL_FAST_MULT. For some
243 hardware we want to be able to generate the multiply instructions, but to
244 tune as if they were not present in the architecture. */
245 static int tune_flags
= 0;
247 /* The following are used in the arm.md file as equivalents to bits
248 in the above two flag variables. */
250 /* Nonzero if this is an "M" variant of the processor. */
251 int arm_fast_multiply
= 0;
253 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
256 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
259 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
262 /* Nonzero if this chip can benefit from load scheduling. */
263 int arm_ld_sched
= 0;
265 /* Nonzero if this chip is a StrongARM. */
266 int arm_is_strong
= 0;
268 /* Nonzero if this chip is an XScale. */
269 int arm_is_xscale
= 0;
271 /* Nonzero if this chip is an ARM6 or an ARM7. */
272 int arm_is_6_or_7
= 0;
274 /* Nonzero if generating Thumb instructions. */
277 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
278 must report the mode of the memory reference from PRINT_OPERAND to
279 PRINT_OPERAND_ADDRESS. */
280 enum machine_mode output_memory_reference_mode
;
282 /* The register number to be used for the PIC offset register. */
283 const char * arm_pic_register_string
= NULL
;
284 int arm_pic_register
= INVALID_REGNUM
;
286 /* Set to 1 when a return insn is output, this means that the epilogue
288 int return_used_this_function
;
290 /* Set to 1 after arm_reorg has started. Reset to start at the start of
291 the next function. */
292 static int after_arm_reorg
= 0;
294 /* The maximum number of insns to be used when loading a constant. */
295 static int arm_constant_limit
= 3;
297 /* For an explanation of these variables, see final_prescan_insn below. */
299 enum arm_cond_code arm_current_cc
;
301 int arm_target_label
;
303 /* The condition codes of the ARM, and the inverse function. */
304 static const char * const arm_condition_codes
[] =
306 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
307 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
310 #define streq(string1, string2) (strcmp (string1, string2) == 0)
312 /* Initialization code. */
316 const char *const name
;
317 const unsigned int flags
;
320 /* Not all of these give usefully different compilation alternatives,
321 but there is no simple way of generalizing them. */
322 static const struct processors all_cores
[] =
326 {"arm2", FL_CO_PROC
| FL_MODE26
},
327 {"arm250", FL_CO_PROC
| FL_MODE26
},
328 {"arm3", FL_CO_PROC
| FL_MODE26
},
329 {"arm6", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
330 {"arm60", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
331 {"arm600", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
332 {"arm610", FL_MODE26
| FL_MODE32
},
333 {"arm620", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
334 {"arm7", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
335 /* arm7m doesn't exist on its own, but only with D, (and I), but
336 those don't alter the code, so arm7m is sometimes used. */
337 {"arm7m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
338 {"arm7d", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
339 {"arm7dm", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
340 {"arm7di", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
341 {"arm7dmi", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
342 {"arm70", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
343 {"arm700", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
344 {"arm700i", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
345 {"arm710", FL_MODE26
| FL_MODE32
},
346 {"arm710t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
347 {"arm720", FL_MODE26
| FL_MODE32
},
348 {"arm720t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
349 {"arm740t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
350 {"arm710c", FL_MODE26
| FL_MODE32
},
351 {"arm7100", FL_MODE26
| FL_MODE32
},
352 {"arm7500", FL_MODE26
| FL_MODE32
},
353 /* Doesn't have an external co-proc, but does have embedded fpu. */
354 {"arm7500fe", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
355 {"arm7tdmi", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
356 {"arm8", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
357 {"arm810", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
358 {"arm9", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
359 {"arm920", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
360 {"arm920t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
361 {"arm940t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
362 {"arm9tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
363 {"arm9e", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
364 {"strongarm", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
365 {"strongarm110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
366 {"strongarm1100", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
367 {"strongarm1110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
368 {"arm10tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
369 {"arm1020t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
370 {"xscale", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
},
375 static const struct processors all_architectures
[] =
377 /* ARM Architectures */
379 { "armv2", FL_CO_PROC
| FL_MODE26
},
380 { "armv2a", FL_CO_PROC
| FL_MODE26
},
381 { "armv3", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
382 { "armv3m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
383 { "armv4", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
},
384 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
385 implementations that support it, so we will leave it out for now. */
386 { "armv4t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
387 { "armv5", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
388 { "armv5t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
389 { "armv5te", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
},
393 /* This is a magic stucture. The 'string' field is magically filled in
394 with a pointer to the value specified by the user on the command line
395 assuming that the user has specified such a value. */
397 struct arm_cpu_select arm_select
[] =
399 /* string name processors */
400 { NULL
, "-mcpu=", all_cores
},
401 { NULL
, "-march=", all_architectures
},
402 { NULL
, "-mtune=", all_cores
}
405 /* Return the number of bits set in value' */
410 unsigned long count
= 0;
414 value
&= ~(value
& -value
);
421 /* Fix up any incompatible options that the user has specified.
422 This has now turned into a maze. */
424 arm_override_options ()
428 /* Set up the flags based on the cpu/architecture selected by the user. */
429 for (i
= ARRAY_SIZE (arm_select
); i
--;)
431 struct arm_cpu_select
* ptr
= arm_select
+ i
;
433 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
435 const struct processors
* sel
;
437 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
438 if (streq (ptr
->string
, sel
->name
))
441 tune_flags
= sel
->flags
;
444 /* If we have been given an architecture and a processor
445 make sure that they are compatible. We only generate
446 a warning though, and we prefer the CPU over the
448 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
449 warning ("switch -mcpu=%s conflicts with -march= switch",
452 insn_flags
= sel
->flags
;
458 if (sel
->name
== NULL
)
459 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
463 /* If the user did not specify a processor, choose one for them. */
466 const struct processors
* sel
;
468 static const struct cpu_default
471 const char *const name
;
475 { TARGET_CPU_arm2
, "arm2" },
476 { TARGET_CPU_arm6
, "arm6" },
477 { TARGET_CPU_arm610
, "arm610" },
478 { TARGET_CPU_arm710
, "arm710" },
479 { TARGET_CPU_arm7m
, "arm7m" },
480 { TARGET_CPU_arm7500fe
, "arm7500fe" },
481 { TARGET_CPU_arm7tdmi
, "arm7tdmi" },
482 { TARGET_CPU_arm8
, "arm8" },
483 { TARGET_CPU_arm810
, "arm810" },
484 { TARGET_CPU_arm9
, "arm9" },
485 { TARGET_CPU_strongarm
, "strongarm" },
486 { TARGET_CPU_xscale
, "xscale" },
487 { TARGET_CPU_generic
, "arm" },
490 const struct cpu_default
* def
;
492 /* Find the default. */
493 for (def
= cpu_defaults
; def
->name
; def
++)
494 if (def
->cpu
== TARGET_CPU_DEFAULT
)
497 /* Make sure we found the default CPU. */
498 if (def
->name
== NULL
)
501 /* Find the default CPU's flags. */
502 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
503 if (streq (def
->name
, sel
->name
))
506 if (sel
->name
== NULL
)
509 insn_flags
= sel
->flags
;
511 /* Now check to see if the user has specified some command line
512 switch that require certain abilities from the cpu. */
515 if (TARGET_INTERWORK
|| TARGET_THUMB
)
517 sought
|= (FL_THUMB
| FL_MODE32
);
519 /* Force apcs-32 to be used for interworking. */
520 target_flags
|= ARM_FLAG_APCS_32
;
522 /* There are no ARM processors that support both APCS-26 and
523 interworking. Therefore we force FL_MODE26 to be removed
524 from insn_flags here (if it was set), so that the search
525 below will always be able to find a compatible processor. */
526 insn_flags
&= ~FL_MODE26
;
528 else if (!TARGET_APCS_32
)
531 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
533 /* Try to locate a CPU type that supports all of the abilities
534 of the default CPU, plus the extra abilities requested by
536 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
537 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
540 if (sel
->name
== NULL
)
542 unsigned int current_bit_count
= 0;
543 const struct processors
* best_fit
= NULL
;
545 /* Ideally we would like to issue an error message here
546 saying that it was not possible to find a CPU compatible
547 with the default CPU, but which also supports the command
548 line options specified by the programmer, and so they
549 ought to use the -mcpu=<name> command line option to
550 override the default CPU type.
552 Unfortunately this does not work with multilibing. We
553 need to be able to support multilibs for -mapcs-26 and for
554 -mthumb-interwork and there is no CPU that can support both
555 options. Instead if we cannot find a cpu that has both the
556 characteristics of the default cpu and the given command line
557 options we scan the array again looking for a best match. */
558 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
559 if ((sel
->flags
& sought
) == sought
)
563 count
= bit_count (sel
->flags
& insn_flags
);
565 if (count
>= current_bit_count
)
568 current_bit_count
= count
;
572 if (best_fit
== NULL
)
578 insn_flags
= sel
->flags
;
582 /* If tuning has not been specified, tune for whichever processor or
583 architecture has been selected. */
585 tune_flags
= insn_flags
;
587 /* Make sure that the processor choice does not conflict with any of the
588 other command line choices. */
589 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
591 /* If APCS-32 was not the default then it must have been set by the
592 user, so issue a warning message. If the user has specified
593 "-mapcs-32 -mcpu=arm2" then we loose here. */
594 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
595 warning ("target CPU does not support APCS-32" );
596 target_flags
&= ~ARM_FLAG_APCS_32
;
598 else if (!TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
600 warning ("target CPU does not support APCS-26" );
601 target_flags
|= ARM_FLAG_APCS_32
;
604 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
606 warning ("target CPU does not support interworking" );
607 target_flags
&= ~ARM_FLAG_INTERWORK
;
610 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
612 warning ("target CPU does not support THUMB instructions");
613 target_flags
&= ~ARM_FLAG_THUMB
;
616 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
618 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
619 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
622 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
623 from here where no function is being compiled currently. */
624 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
626 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
628 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
629 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
631 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
632 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
634 /* If interworking is enabled then APCS-32 must be selected as well. */
635 if (TARGET_INTERWORK
)
638 warning ("interworking forces APCS-32 to be used" );
639 target_flags
|= ARM_FLAG_APCS_32
;
642 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
644 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
645 target_flags
|= ARM_FLAG_APCS_FRAME
;
648 if (TARGET_POKE_FUNCTION_NAME
)
649 target_flags
|= ARM_FLAG_APCS_FRAME
;
651 if (TARGET_APCS_REENT
&& flag_pic
)
652 error ("-fpic and -mapcs-reent are incompatible");
654 if (TARGET_APCS_REENT
)
655 warning ("APCS reentrant code not supported. Ignored");
657 /* If this target is normally configured to use APCS frames, warn if they
658 are turned off and debugging is turned on. */
660 && write_symbols
!= NO_DEBUG
661 && !TARGET_APCS_FRAME
662 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
663 warning ("-g with -mno-apcs-frame may not give sensible debugging");
665 /* If stack checking is disabled, we can use r10 as the PIC register,
666 which keeps r9 available. */
668 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
670 if (TARGET_APCS_FLOAT
)
671 warning ("passing floating point arguments in fp regs not yet supported");
673 /* Initialise boolean versions of the flags, for use in the arm.md file. */
674 arm_fast_multiply
= (insn_flags
& FL_FAST_MULT
) != 0;
675 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
676 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
677 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
678 arm_is_xscale
= (insn_flags
& FL_XSCALE
) != 0;
680 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
681 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
682 thumb_code
= (TARGET_ARM
== 0);
683 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
684 && !(tune_flags
& FL_ARCH4
))) != 0;
686 /* Default value for floating point code... if no co-processor
687 bus, then schedule for emulated floating point. Otherwise,
688 assume the user has an FPA.
689 Note: this does not prevent use of floating point instructions,
690 -msoft-float does that. */
691 arm_fpu
= (tune_flags
& FL_CO_PROC
) ? FP_HARD
: FP_SOFT3
;
695 if (streq (target_fp_name
, "2"))
696 arm_fpu_arch
= FP_SOFT2
;
697 else if (streq (target_fp_name
, "3"))
698 arm_fpu_arch
= FP_SOFT3
;
700 error ("invalid floating point emulation option: -mfpe-%s",
704 arm_fpu_arch
= FP_DEFAULT
;
706 if (TARGET_FPE
&& arm_fpu
!= FP_HARD
)
709 /* For arm2/3 there is no need to do any scheduling if there is only
710 a floating point emulator, or we are doing software floating-point. */
711 if ((TARGET_SOFT_FLOAT
|| arm_fpu
!= FP_HARD
)
712 && (tune_flags
& FL_MODE32
) == 0)
713 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
715 arm_prgmode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
717 if (structure_size_string
!= NULL
)
719 int size
= strtol (structure_size_string
, NULL
, 0);
721 if (size
== 8 || size
== 32)
722 arm_structure_size_boundary
= size
;
724 warning ("structure size boundary can only be set to 8 or 32");
727 if (arm_pic_register_string
!= NULL
)
729 int pic_register
= decode_reg_name (arm_pic_register_string
);
732 warning ("-mpic-register= is useless without -fpic");
734 /* Prevent the user from choosing an obviously stupid PIC register. */
735 else if (pic_register
< 0 || call_used_regs
[pic_register
]
736 || pic_register
== HARD_FRAME_POINTER_REGNUM
737 || pic_register
== STACK_POINTER_REGNUM
738 || pic_register
>= PC_REGNUM
)
739 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
741 arm_pic_register
= pic_register
;
744 if (TARGET_THUMB
&& flag_schedule_insns
)
746 /* Don't warn since it's on by default in -O2. */
747 flag_schedule_insns
= 0;
750 /* If optimizing for space, don't synthesize constants.
751 For processors with load scheduling, it never costs more than 2 cycles
752 to load a constant, and the load scheduler may well reduce that to 1. */
753 if (optimize_size
|| (tune_flags
& FL_LDSCHED
))
754 arm_constant_limit
= 1;
757 arm_constant_limit
= 2;
759 /* If optimizing for size, bump the number of instructions that we
760 are prepared to conditionally execute (even on a StrongARM).
761 Otherwise for the StrongARM, which has early execution of branches,
762 a sequence that is worth skipping is shorter. */
764 max_insns_skipped
= 6;
765 else if (arm_is_strong
)
766 max_insns_skipped
= 3;
768 /* Register global variables with the garbage collector. */
775 ggc_add_rtx_root (&arm_compare_op0
, 1);
776 ggc_add_rtx_root (&arm_compare_op1
, 1);
777 ggc_add_rtx_root (&arm_target_insn
, 1); /* Not sure this is really a root. */
779 gcc_obstack_init(&minipool_obstack
);
780 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
783 /* A table of known ARM exception types.
784 For use with the interrupt function attribute. */
788 const char *const arg
;
789 const unsigned long return_value
;
793 static const isr_attribute_arg isr_attribute_args
[] =
795 { "IRQ", ARM_FT_ISR
},
796 { "irq", ARM_FT_ISR
},
797 { "FIQ", ARM_FT_FIQ
},
798 { "fiq", ARM_FT_FIQ
},
799 { "ABORT", ARM_FT_ISR
},
800 { "abort", ARM_FT_ISR
},
801 { "ABORT", ARM_FT_ISR
},
802 { "abort", ARM_FT_ISR
},
803 { "UNDEF", ARM_FT_EXCEPTION
},
804 { "undef", ARM_FT_EXCEPTION
},
805 { "SWI", ARM_FT_EXCEPTION
},
806 { "swi", ARM_FT_EXCEPTION
},
807 { NULL
, ARM_FT_NORMAL
}
810 /* Returns the (interrupt) function type of the current
811 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
814 arm_isr_value (argument
)
817 const isr_attribute_arg
* ptr
;
820 /* No argument - default to IRQ. */
821 if (argument
== NULL_TREE
)
824 /* Get the value of the argument. */
825 if (TREE_VALUE (argument
) == NULL_TREE
826 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
827 return ARM_FT_UNKNOWN
;
829 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
831 /* Check it against the list of known arguments. */
832 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
833 if (streq (arg
, ptr
->arg
))
834 return ptr
->return_value
;
836 /* An unrecognised interrupt type. */
837 return ARM_FT_UNKNOWN
;
840 /* Computes the type of the current function. */
843 arm_compute_func_type ()
845 unsigned long type
= ARM_FT_UNKNOWN
;
849 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
852 /* Decide if the current function is volatile. Such functions
853 never return, and many memory cycles can be saved by not storing
854 register values that will never be needed again. This optimization
855 was added to speed up context switching in a kernel application. */
857 && current_function_nothrow
858 && TREE_THIS_VOLATILE (current_function_decl
))
859 type
|= ARM_FT_VOLATILE
;
861 if (current_function_needs_context
)
862 type
|= ARM_FT_NESTED
;
864 attr
= DECL_ATTRIBUTES (current_function_decl
);
866 a
= lookup_attribute ("naked", attr
);
868 type
|= ARM_FT_NAKED
;
870 if (cfun
->machine
->eh_epilogue_sp_ofs
!= NULL_RTX
)
871 type
|= ARM_FT_EXCEPTION_HANDLER
;
874 a
= lookup_attribute ("isr", attr
);
876 a
= lookup_attribute ("interrupt", attr
);
879 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
881 type
|= arm_isr_value (TREE_VALUE (a
));
887 /* Returns the type of the current function. */
890 arm_current_func_type ()
892 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
893 cfun
->machine
->func_type
= arm_compute_func_type ();
895 return cfun
->machine
->func_type
;
898 /* Return 1 if it is possible to return using a single instruction. */
901 use_return_insn (iscond
)
905 unsigned int func_type
;
907 /* Never use a return instruction before reload has run. */
908 if (!reload_completed
)
911 func_type
= arm_current_func_type ();
913 /* Naked functions and volatile functions need special
915 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
918 /* As do variadic functions. */
919 if (current_function_pretend_args_size
920 || cfun
->machine
->uses_anonymous_args
921 /* Of if the function calls __builtin_eh_return () */
922 || ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
923 /* Or if there is no frame pointer and there is a stack adjustment. */
924 || ((get_frame_size () + current_function_outgoing_args_size
!= 0)
925 && !frame_pointer_needed
))
928 /* Can't be done if interworking with Thumb, and any registers have been
929 stacked. Similarly, on StrongARM, conditional returns are expensive
930 if they aren't taken and registers have been stacked. */
931 if (iscond
&& arm_is_strong
&& frame_pointer_needed
)
934 if ((iscond
&& arm_is_strong
)
937 for (regno
= 0; regno
<= LAST_ARM_REGNUM
; regno
++)
938 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
941 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
945 /* Can't be done if any of the FPU regs are pushed,
946 since this also requires an insn. */
947 if (TARGET_HARD_FLOAT
)
948 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
949 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
955 /* Return TRUE if int I is a valid immediate ARM constant. */
961 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
963 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
964 be all zero, or all one. */
965 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
966 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
967 != ((~(unsigned HOST_WIDE_INT
) 0)
968 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
971 /* Fast return for 0 and powers of 2 */
972 if ((i
& (i
- 1)) == 0)
977 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
980 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
981 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
983 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
988 /* Return true if I is a valid constant for the operation CODE. */
990 const_ok_for_op (i
, code
)
994 if (const_ok_for_arm (i
))
1000 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1002 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1008 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1015 /* Emit a sequence of insns to handle a large constant.
1016 CODE is the code of the operation required, it can be any of SET, PLUS,
1017 IOR, AND, XOR, MINUS;
1018 MODE is the mode in which the operation is being performed;
1019 VAL is the integer to operate on;
1020 SOURCE is the other operand (a register, or a null-pointer for SET);
1021 SUBTARGETS means it is safe to create scratch registers if that will
1022 either produce a simpler sequence, or we will want to cse the values.
1023 Return value is the number of insns emitted. */
1026 arm_split_constant (code
, mode
, val
, target
, source
, subtargets
)
1028 enum machine_mode mode
;
1034 if (subtargets
|| code
== SET
1035 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1036 && REGNO (target
) != REGNO (source
)))
1038 /* After arm_reorg has been called, we can't fix up expensive
1039 constants by pushing them into memory so we must synthesise
1040 them in-line, regardless of the cost. This is only likely to
1041 be more costly on chips that have load delay slots and we are
1042 compiling without running the scheduler (so no splitting
1043 occurred before the final instruction emission).
1045 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1047 if (!after_arm_reorg
1048 && (arm_gen_constant (code
, mode
, val
, target
, source
, 1, 0)
1049 > arm_constant_limit
+ (code
!= SET
)))
1053 /* Currently SET is the only monadic value for CODE, all
1054 the rest are diadic. */
1055 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1060 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1062 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1063 /* For MINUS, the value is subtracted from, since we never
1064 have subtraction of a constant. */
1066 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1067 gen_rtx_MINUS (mode
, temp
, source
)));
1069 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1070 gen_rtx (code
, mode
, source
, temp
)));
1076 return arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, 1);
1080 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1082 HOST_WIDE_INT temp1
;
1090 if (remainder
& (3 << (i
- 2)))
1095 temp1
= remainder
& ((0x0ff << end
)
1096 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1097 remainder
&= ~temp1
;
1102 } while (remainder
);
1106 /* As above, but extra parameter GENERATE which, if clear, suppresses
1110 arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, generate
)
1112 enum machine_mode mode
;
1121 int can_negate_initial
= 0;
1124 int num_bits_set
= 0;
1125 int set_sign_bit_copies
= 0;
1126 int clear_sign_bit_copies
= 0;
1127 int clear_zero_bit_copies
= 0;
1128 int set_zero_bit_copies
= 0;
1130 unsigned HOST_WIDE_INT temp1
, temp2
;
1131 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1133 /* Find out which operations are safe for a given CODE. Also do a quick
1134 check for degenerate cases; these can occur when DImode operations
1146 can_negate_initial
= 1;
1150 if (remainder
== 0xffffffff)
1153 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1154 GEN_INT (ARM_SIGN_EXTEND (val
))));
1159 if (reload_completed
&& rtx_equal_p (target
, source
))
1162 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1171 emit_insn (gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1174 if (remainder
== 0xffffffff)
1176 if (reload_completed
&& rtx_equal_p (target
, source
))
1179 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1188 if (reload_completed
&& rtx_equal_p (target
, source
))
1191 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1194 if (remainder
== 0xffffffff)
1197 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1198 gen_rtx_NOT (mode
, source
)));
1202 /* We don't know how to handle this yet below. */
1206 /* We treat MINUS as (val - source), since (source - val) is always
1207 passed as (source + (-val)). */
1211 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1212 gen_rtx_NEG (mode
, source
)));
1215 if (const_ok_for_arm (val
))
1218 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1219 gen_rtx_MINUS (mode
, GEN_INT (val
),
1231 /* If we can do it in one insn get out quickly. */
1232 if (const_ok_for_arm (val
)
1233 || (can_negate_initial
&& const_ok_for_arm (-val
))
1234 || (can_invert
&& const_ok_for_arm (~val
)))
1237 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1238 (source
? gen_rtx (code
, mode
, source
,
1244 /* Calculate a few attributes that may be useful for specific
1246 for (i
= 31; i
>= 0; i
--)
1248 if ((remainder
& (1 << i
)) == 0)
1249 clear_sign_bit_copies
++;
1254 for (i
= 31; i
>= 0; i
--)
1256 if ((remainder
& (1 << i
)) != 0)
1257 set_sign_bit_copies
++;
1262 for (i
= 0; i
<= 31; i
++)
1264 if ((remainder
& (1 << i
)) == 0)
1265 clear_zero_bit_copies
++;
1270 for (i
= 0; i
<= 31; i
++)
1272 if ((remainder
& (1 << i
)) != 0)
1273 set_zero_bit_copies
++;
1281 /* See if we can do this by sign_extending a constant that is known
1282 to be negative. This is a good, way of doing it, since the shift
1283 may well merge into a subsequent insn. */
1284 if (set_sign_bit_copies
> 1)
1286 if (const_ok_for_arm
1287 (temp1
= ARM_SIGN_EXTEND (remainder
1288 << (set_sign_bit_copies
- 1))))
1292 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1293 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1295 emit_insn (gen_ashrsi3 (target
, new_src
,
1296 GEN_INT (set_sign_bit_copies
- 1)));
1300 /* For an inverted constant, we will need to set the low bits,
1301 these will be shifted out of harm's way. */
1302 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1303 if (const_ok_for_arm (~temp1
))
1307 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1308 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1310 emit_insn (gen_ashrsi3 (target
, new_src
,
1311 GEN_INT (set_sign_bit_copies
- 1)));
1317 /* See if we can generate this by setting the bottom (or the top)
1318 16 bits, and then shifting these into the other half of the
1319 word. We only look for the simplest cases, to do more would cost
1320 too much. Be careful, however, not to generate this when the
1321 alternative would take fewer insns. */
1322 if (val
& 0xffff0000)
1324 temp1
= remainder
& 0xffff0000;
1325 temp2
= remainder
& 0x0000ffff;
1327 /* Overlaps outside this range are best done using other methods. */
1328 for (i
= 9; i
< 24; i
++)
1330 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1331 && !const_ok_for_arm (temp2
))
1333 rtx new_src
= (subtargets
1334 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1336 insns
= arm_gen_constant (code
, mode
, temp2
, new_src
,
1337 source
, subtargets
, generate
);
1340 emit_insn (gen_rtx_SET
1343 gen_rtx_ASHIFT (mode
, source
,
1350 /* Don't duplicate cases already considered. */
1351 for (i
= 17; i
< 24; i
++)
1353 if (((temp1
| (temp1
>> i
)) == remainder
)
1354 && !const_ok_for_arm (temp1
))
1356 rtx new_src
= (subtargets
1357 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1359 insns
= arm_gen_constant (code
, mode
, temp1
, new_src
,
1360 source
, subtargets
, generate
);
1364 (gen_rtx_SET (VOIDmode
, target
,
1367 gen_rtx_LSHIFTRT (mode
, source
,
1378 /* If we have IOR or XOR, and the constant can be loaded in a
1379 single instruction, and we can find a temporary to put it in,
1380 then this can be done in two instructions instead of 3-4. */
1382 /* TARGET can't be NULL if SUBTARGETS is 0 */
1383 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1385 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1389 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1391 emit_insn (gen_rtx_SET (VOIDmode
, sub
, GEN_INT (val
)));
1392 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1393 gen_rtx (code
, mode
, source
, sub
)));
1402 if (set_sign_bit_copies
> 8
1403 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1407 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1408 rtx shift
= GEN_INT (set_sign_bit_copies
);
1410 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1412 gen_rtx_ASHIFT (mode
,
1415 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1417 gen_rtx_LSHIFTRT (mode
, sub
,
1423 if (set_zero_bit_copies
> 8
1424 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1428 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1429 rtx shift
= GEN_INT (set_zero_bit_copies
);
1431 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1433 gen_rtx_LSHIFTRT (mode
,
1436 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1438 gen_rtx_ASHIFT (mode
, sub
,
1444 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1448 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1449 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1450 gen_rtx_NOT (mode
, source
)));
1453 sub
= gen_reg_rtx (mode
);
1454 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1455 gen_rtx_AND (mode
, source
,
1457 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1458 gen_rtx_NOT (mode
, sub
)));
1465 /* See if two shifts will do 2 or more insn's worth of work. */
1466 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1468 HOST_WIDE_INT shift_mask
= ((0xffffffff
1469 << (32 - clear_sign_bit_copies
))
1472 if ((remainder
| shift_mask
) != 0xffffffff)
1476 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1477 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1478 new_src
, source
, subtargets
, 1);
1483 rtx targ
= subtargets
? NULL_RTX
: target
;
1484 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1485 targ
, source
, subtargets
, 0);
1491 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1492 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1494 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1495 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1501 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1503 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1505 if ((remainder
| shift_mask
) != 0xffffffff)
1509 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1511 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1512 new_src
, source
, subtargets
, 1);
1517 rtx targ
= subtargets
? NULL_RTX
: target
;
1519 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1520 targ
, source
, subtargets
, 0);
1526 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1527 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1529 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1530 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1542 for (i
= 0; i
< 32; i
++)
1543 if (remainder
& (1 << i
))
1546 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1547 remainder
= (~remainder
) & 0xffffffff;
1548 else if (code
== PLUS
&& num_bits_set
> 16)
1549 remainder
= (-remainder
) & 0xffffffff;
1556 /* Now try and find a way of doing the job in either two or three
1558 We start by looking for the largest block of zeros that are aligned on
1559 a 2-bit boundary, we then fill up the temps, wrapping around to the
1560 top of the word when we drop off the bottom.
1561 In the worst case this code should produce no more than four insns. */
1564 int best_consecutive_zeros
= 0;
1566 for (i
= 0; i
< 32; i
+= 2)
1568 int consecutive_zeros
= 0;
1570 if (!(remainder
& (3 << i
)))
1572 while ((i
< 32) && !(remainder
& (3 << i
)))
1574 consecutive_zeros
+= 2;
1577 if (consecutive_zeros
> best_consecutive_zeros
)
1579 best_consecutive_zeros
= consecutive_zeros
;
1580 best_start
= i
- consecutive_zeros
;
1586 /* So long as it won't require any more insns to do so, it's
1587 desirable to emit a small constant (in bits 0...9) in the last
1588 insn. This way there is more chance that it can be combined with
1589 a later addressing insn to form a pre-indexed load or store
1590 operation. Consider:
1592 *((volatile int *)0xe0000100) = 1;
1593 *((volatile int *)0xe0000110) = 2;
1595 We want this to wind up as:
1599 str rB, [rA, #0x100]
1601 str rB, [rA, #0x110]
1603 rather than having to synthesize both large constants from scratch.
1605 Therefore, we calculate how many insns would be required to emit
1606 the constant starting from `best_start', and also starting from
1607 zero (ie with bit 31 first to be output). If `best_start' doesn't
1608 yield a shorter sequence, we may as well use zero. */
1610 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
1611 && (count_insns_for_constant (remainder
, 0) <=
1612 count_insns_for_constant (remainder
, best_start
)))
1615 /* Now start emitting the insns. */
1623 if (remainder
& (3 << (i
- 2)))
1628 temp1
= remainder
& ((0x0ff << end
)
1629 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1630 remainder
&= ~temp1
;
1634 rtx new_src
, temp1_rtx
;
1636 if (code
== SET
|| code
== MINUS
)
1638 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
1639 if (can_invert
&& code
!= MINUS
)
1644 if (remainder
&& subtargets
)
1645 new_src
= gen_reg_rtx (mode
);
1650 else if (can_negate
)
1654 temp1
= trunc_int_for_mode (temp1
, mode
);
1655 temp1_rtx
= GEN_INT (temp1
);
1659 else if (code
== MINUS
)
1660 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
1662 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
1664 emit_insn (gen_rtx_SET (VOIDmode
, new_src
, temp1_rtx
));
1673 else if (code
== MINUS
)
1687 /* Canonicalize a comparison so that we are more likely to recognize it.
1688 This can be done for a few constant compares, where we can make the
1689 immediate value easier to load. */
1692 arm_canonicalize_comparison (code
, op1
)
1696 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
1706 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
1707 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1709 *op1
= GEN_INT (i
+ 1);
1710 return code
== GT
? GE
: LT
;
1716 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
1717 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1719 *op1
= GEN_INT (i
- 1);
1720 return code
== GE
? GT
: LE
;
1726 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
1727 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1729 *op1
= GEN_INT (i
+ 1);
1730 return code
== GTU
? GEU
: LTU
;
1737 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1739 *op1
= GEN_INT (i
- 1);
1740 return code
== GEU
? GTU
: LEU
;
1751 /* Decide whether a type should be returned in memory (true)
1752 or in a register (false). This is called by the macro
1753 RETURN_IN_MEMORY. */
1756 arm_return_in_memory (type
)
1759 if (!AGGREGATE_TYPE_P (type
))
1760 /* All simple types are returned in registers. */
1763 /* For the arm-wince targets we choose to be compitable with Microsoft's
1764 ARM and Thumb compilers, which always return aggregates in memory. */
1766 /* All structures/unions bigger than one word are returned in memory.
1767 Also catch the case where int_size_in_bytes returns -1. In this case
1768 the aggregate is either huge or of varaible size, and in either case
1769 we will want to return it via memory and not in a register. */
1770 if (((unsigned int) int_size_in_bytes (type
)) > UNITS_PER_WORD
)
1773 if (TREE_CODE (type
) == RECORD_TYPE
)
1777 /* For a struct the APCS says that we only return in a register
1778 if the type is 'integer like' and every addressable element
1779 has an offset of zero. For practical purposes this means
1780 that the structure can have at most one non bit-field element
1781 and that this element must be the first one in the structure. */
1783 /* Find the first field, ignoring non FIELD_DECL things which will
1784 have been created by C++. */
1785 for (field
= TYPE_FIELDS (type
);
1786 field
&& TREE_CODE (field
) != FIELD_DECL
;
1787 field
= TREE_CHAIN (field
))
1791 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1793 /* Check that the first field is valid for returning in a register. */
1795 /* ... Floats are not allowed */
1796 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1799 /* ... Aggregates that are not themselves valid for returning in
1800 a register are not allowed. */
1801 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1804 /* Now check the remaining fields, if any. Only bitfields are allowed,
1805 since they are not addressable. */
1806 for (field
= TREE_CHAIN (field
);
1808 field
= TREE_CHAIN (field
))
1810 if (TREE_CODE (field
) != FIELD_DECL
)
1813 if (!DECL_BIT_FIELD_TYPE (field
))
1820 if (TREE_CODE (type
) == UNION_TYPE
)
1824 /* Unions can be returned in registers if every element is
1825 integral, or can be returned in an integer register. */
1826 for (field
= TYPE_FIELDS (type
);
1828 field
= TREE_CHAIN (field
))
1830 if (TREE_CODE (field
) != FIELD_DECL
)
1833 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1836 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1842 #endif /* not ARM_WINCE */
1844 /* Return all other types in memory. */
1848 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1849 for a call to a function whose data type is FNTYPE.
1850 For a library call, FNTYPE is NULL. */
1852 arm_init_cumulative_args (pcum
, fntype
, libname
, indirect
)
1853 CUMULATIVE_ARGS
* pcum
;
1855 rtx libname ATTRIBUTE_UNUSED
;
1856 int indirect ATTRIBUTE_UNUSED
;
1858 /* On the ARM, the offset starts at 0. */
1859 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
))) ? 1 : 0);
1861 pcum
->call_cookie
= CALL_NORMAL
;
1863 if (TARGET_LONG_CALLS
)
1864 pcum
->call_cookie
= CALL_LONG
;
1866 /* Check for long call/short call attributes. The attributes
1867 override any command line option. */
1870 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
1871 pcum
->call_cookie
= CALL_SHORT
;
1872 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
1873 pcum
->call_cookie
= CALL_LONG
;
1877 /* Determine where to put an argument to a function.
1878 Value is zero to push the argument on the stack,
1879 or a hard register in which to store the argument.
1881 MODE is the argument's machine mode.
1882 TYPE is the data type of the argument (as a tree).
1883 This is null for libcalls where that information may
1885 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1886 the preceding args and about the function being called.
1887 NAMED is nonzero if this argument is a named parameter
1888 (otherwise it is an extra parameter matching an ellipsis). */
1891 arm_function_arg (pcum
, mode
, type
, named
)
1892 CUMULATIVE_ARGS
* pcum
;
1893 enum machine_mode mode
;
1894 tree type ATTRIBUTE_UNUSED
;
1897 if (mode
== VOIDmode
)
1898 /* Compute operand 2 of the call insn. */
1899 return GEN_INT (pcum
->call_cookie
);
1901 if (!named
|| pcum
->nregs
>= NUM_ARG_REGS
)
1904 return gen_rtx_REG (mode
, pcum
->nregs
);
1907 /* Encode the current state of the #pragma [no_]long_calls. */
1910 OFF
, /* No #pramgma [no_]long_calls is in effect. */
1911 LONG
, /* #pragma long_calls is in effect. */
1912 SHORT
/* #pragma no_long_calls is in effect. */
1915 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
1918 arm_pr_long_calls (pfile
)
1919 cpp_reader
* pfile ATTRIBUTE_UNUSED
;
1921 arm_pragma_long_calls
= LONG
;
1925 arm_pr_no_long_calls (pfile
)
1926 cpp_reader
* pfile ATTRIBUTE_UNUSED
;
1928 arm_pragma_long_calls
= SHORT
;
1932 arm_pr_long_calls_off (pfile
)
1933 cpp_reader
* pfile ATTRIBUTE_UNUSED
;
1935 arm_pragma_long_calls
= OFF
;
1938 /* Table of machine attributes. */
1939 const struct attribute_spec arm_attribute_table
[] =
1941 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1942 /* Function calls made to this symbol must be done indirectly, because
1943 it may lie outside of the 26 bit addressing range of a normal function
1945 { "long_call", 0, 0, false, true, true, NULL
},
1946 /* Whereas these functions are always known to reside within the 26 bit
1947 addressing range. */
1948 { "short_call", 0, 0, false, true, true, NULL
},
1949 /* Interrupt Service Routines have special prologue and epilogue requirements. */
1950 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
1951 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
1952 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
1954 /* ARM/PE has three new attributes:
1956 dllexport - for exporting a function/variable that will live in a dll
1957 dllimport - for importing a function/variable from a dll
1959 Microsoft allows multiple declspecs in one __declspec, separating
1960 them with spaces. We do NOT support this. Instead, use __declspec
1963 { "dllimport", 0, 0, true, false, false, NULL
},
1964 { "dllexport", 0, 0, true, false, false, NULL
},
1965 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
1967 { NULL
, 0, 0, false, false, false, NULL
}
1970 /* Handle an attribute requiring a FUNCTION_DECL;
1971 arguments as in struct attribute_spec.handler. */
1974 arm_handle_fndecl_attribute (node
, name
, args
, flags
, no_add_attrs
)
1977 tree args ATTRIBUTE_UNUSED
;
1978 int flags ATTRIBUTE_UNUSED
;
1979 bool * no_add_attrs
;
1981 if (TREE_CODE (*node
) != FUNCTION_DECL
)
1983 warning ("`%s' attribute only applies to functions",
1984 IDENTIFIER_POINTER (name
));
1985 *no_add_attrs
= true;
1991 /* Handle an "interrupt" or "isr" attribute;
1992 arguments as in struct attribute_spec.handler. */
1995 arm_handle_isr_attribute (node
, name
, args
, flags
, no_add_attrs
)
2000 bool * no_add_attrs
;
2004 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2006 warning ("`%s' attribute only applies to functions",
2007 IDENTIFIER_POINTER (name
));
2008 *no_add_attrs
= true;
2010 /* FIXME: the argument if any is checked for type attributes;
2011 should it be checked for decl ones? */
2015 if (TREE_CODE (*node
) == FUNCTION_TYPE
2016 || TREE_CODE (*node
) == METHOD_TYPE
)
2018 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2020 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2021 *no_add_attrs
= true;
2024 else if (TREE_CODE (*node
) == POINTER_TYPE
2025 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2026 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2027 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2029 *node
= build_type_copy (*node
);
2030 TREE_TYPE (*node
) = build_type_attribute_variant
2032 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2033 *no_add_attrs
= true;
2037 /* Possibly pass this attribute on from the type to a decl. */
2038 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2039 | (int) ATTR_FLAG_FUNCTION_NEXT
2040 | (int) ATTR_FLAG_ARRAY_NEXT
))
2042 *no_add_attrs
= true;
2043 return tree_cons (name
, args
, NULL_TREE
);
2047 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2055 /* Return 0 if the attributes for two types are incompatible, 1 if they
2056 are compatible, and 2 if they are nearly compatible (which causes a
2057 warning to be generated). */
2060 arm_comp_type_attributes (type1
, type2
)
2066 /* Check for mismatch of non-default calling convention. */
2067 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2070 /* Check for mismatched call attributes. */
2071 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2072 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2073 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2074 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2076 /* Only bother to check if an attribute is defined. */
2077 if (l1
| l2
| s1
| s2
)
2079 /* If one type has an attribute, the other must have the same attribute. */
2080 if ((l1
!= l2
) || (s1
!= s2
))
2083 /* Disallow mixed attributes. */
2084 if ((l1
& s2
) || (l2
& s1
))
2088 /* Check for mismatched ISR attribute. */
2089 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2091 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2092 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2094 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2101 /* Encode long_call or short_call attribute by prefixing
2102 symbol name in DECL with a special character FLAG. */
2105 arm_encode_call_attribute (decl
, flag
)
2109 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2110 int len
= strlen (str
);
2113 /* Do not allow weak functions to be treated as short call. */
2114 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2117 newstr
= alloca (len
+ 2);
2119 strcpy (newstr
+ 1, str
);
2121 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2122 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2125 /* Assigns default attributes to newly defined type. This is used to
2126 set short_call/long_call attributes for function types of
2127 functions defined inside corresponding #pragma scopes. */
2130 arm_set_default_type_attributes (type
)
2133 /* Add __attribute__ ((long_call)) to all functions, when
2134 inside #pragma long_calls or __attribute__ ((short_call)),
2135 when inside #pragma no_long_calls. */
2136 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2138 tree type_attr_list
, attr_name
;
2139 type_attr_list
= TYPE_ATTRIBUTES (type
);
2141 if (arm_pragma_long_calls
== LONG
)
2142 attr_name
= get_identifier ("long_call");
2143 else if (arm_pragma_long_calls
== SHORT
)
2144 attr_name
= get_identifier ("short_call");
2148 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2149 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2153 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2154 defined within the current compilation unit. If this caanot be
2155 determined, then 0 is returned. */
2158 current_file_function_operand (sym_ref
)
2161 /* This is a bit of a fib. A function will have a short call flag
2162 applied to its name if it has the short call attribute, or it has
2163 already been defined within the current compilation unit. */
2164 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2167 /* The current function is always defined within the current compilation
2168 unit. if it s a weak definition however, then this may not be the real
2169 definition of the function, and so we have to say no. */
2170 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2171 && !DECL_WEAK (current_function_decl
))
2174 /* We cannot make the determination - default to returning 0. */
2178 /* Return non-zero if a 32 bit "long_call" should be generated for
2179 this call. We generate a long_call if the function:
2181 a. has an __attribute__((long call))
2182 or b. is within the scope of a #pragma long_calls
2183 or c. the -mlong-calls command line switch has been specified
2185 However we do not generate a long call if the function:
2187 d. has an __attribute__ ((short_call))
2188 or e. is inside the scope of a #pragma no_long_calls
2189 or f. has an __attribute__ ((section))
2190 or g. is defined within the current compilation unit.
2192 This function will be called by C fragments contained in the machine
2193 description file. CALL_REF and CALL_COOKIE correspond to the matched
2194 rtl operands. CALL_SYMBOL is used to distinguish between
2195 two different callers of the function. It is set to 1 in the
2196 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2197 and "call_value" patterns. This is because of the difference in the
2198 SYM_REFs passed by these patterns. */
2201 arm_is_longcall_p (sym_ref
, call_cookie
, call_symbol
)
2208 if (GET_CODE (sym_ref
) != MEM
)
2211 sym_ref
= XEXP (sym_ref
, 0);
2214 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2217 if (call_cookie
& CALL_SHORT
)
2220 if (TARGET_LONG_CALLS
&& flag_function_sections
)
2223 if (current_file_function_operand (sym_ref
))
2226 return (call_cookie
& CALL_LONG
)
2227 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2228 || TARGET_LONG_CALLS
;
2231 /* Return non-zero if it is ok to make a tail-call to DECL. */
2234 arm_function_ok_for_sibcall (decl
)
2237 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2239 /* Never tailcall something for which we have no decl, or if we
2240 are in Thumb mode. */
2241 if (decl
== NULL
|| TARGET_THUMB
)
2244 /* Get the calling method. */
2245 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2246 call_type
= CALL_SHORT
;
2247 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2248 call_type
= CALL_LONG
;
2250 /* Cannot tail-call to long calls, since these are out of range of
2251 a branch instruction. However, if not compiling PIC, we know
2252 we can reach the symbol if it is in this compilation unit. */
2253 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2256 /* If we are interworking and the function is not declared static
2257 then we can't tail-call it unless we know that it exists in this
2258 compilation unit (since it might be a Thumb routine). */
2259 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2262 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2263 if (IS_INTERRUPT (arm_current_func_type ()))
2266 /* Everything else is ok. */
2272 legitimate_pic_operand_p (x
)
2277 && (GET_CODE (x
) == SYMBOL_REF
2278 || (GET_CODE (x
) == CONST
2279 && GET_CODE (XEXP (x
, 0)) == PLUS
2280 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2287 legitimize_pic_address (orig
, mode
, reg
)
2289 enum machine_mode mode
;
2292 if (GET_CODE (orig
) == SYMBOL_REF
2293 || GET_CODE (orig
) == LABEL_REF
)
2295 #ifndef AOF_ASSEMBLER
2296 rtx pic_ref
, address
;
2306 reg
= gen_reg_rtx (Pmode
);
2311 #ifdef AOF_ASSEMBLER
2312 /* The AOF assembler can generate relocations for these directly, and
2313 understands that the PIC register has to be added into the offset. */
2314 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2317 address
= gen_reg_rtx (Pmode
);
2322 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2324 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2326 if ((GET_CODE (orig
) == LABEL_REF
2327 || (GET_CODE (orig
) == SYMBOL_REF
&&
2328 ENCODED_SHORT_CALL_ATTR_P (XSTR (orig
, 0))))
2330 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2333 pic_ref
= gen_rtx_MEM (Pmode
,
2334 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2336 RTX_UNCHANGING_P (pic_ref
) = 1;
2339 insn
= emit_move_insn (reg
, pic_ref
);
2341 current_function_uses_pic_offset_table
= 1;
2342 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2344 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2348 else if (GET_CODE (orig
) == CONST
)
2352 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2353 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2361 reg
= gen_reg_rtx (Pmode
);
2364 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2366 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2367 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2368 base
== reg
? 0 : reg
);
2373 if (GET_CODE (offset
) == CONST_INT
)
2375 /* The base register doesn't really matter, we only want to
2376 test the index for the appropriate mode. */
2377 ARM_GO_IF_LEGITIMATE_INDEX (mode
, 0, offset
, win
);
2379 if (!no_new_pseudos
)
2380 offset
= force_reg (Pmode
, offset
);
2385 if (GET_CODE (offset
) == CONST_INT
)
2386 return plus_constant (base
, INTVAL (offset
));
2389 if (GET_MODE_SIZE (mode
) > 4
2390 && (GET_MODE_CLASS (mode
) == MODE_INT
2391 || TARGET_SOFT_FLOAT
))
2393 emit_insn (gen_addsi3 (reg
, base
, offset
));
2397 return gen_rtx_PLUS (Pmode
, base
, offset
);
2403 /* Generate code to load the PIC register. PROLOGUE is true if
2404 called from arm_expand_prologue (in which case we want the
2405 generated insns at the start of the function); false if called
2406 by an exception receiver that needs the PIC register reloaded
2407 (in which case the insns are just dumped at the current location). */
2410 arm_finalize_pic (prologue
)
2411 int prologue ATTRIBUTE_UNUSED
;
2413 #ifndef AOF_ASSEMBLER
2414 rtx l1
, pic_tmp
, pic_tmp2
, seq
, pic_rtx
;
2415 rtx global_offset_table
;
2417 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
2424 l1
= gen_label_rtx ();
2426 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2427 /* On the ARM the PC register contains 'dot + 8' at the time of the
2428 addition, on the Thumb it is 'dot + 4'. */
2429 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
2431 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
2432 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
2434 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
2436 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
2440 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
2441 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
2445 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
2446 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
2449 seq
= gen_sequence ();
2452 emit_insn_after (seq
, get_insns ());
2456 /* Need to emit this whether or not we obey regdecls,
2457 since setjmp/longjmp can cause life info to screw up. */
2458 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2459 #endif /* AOF_ASSEMBLER */
2462 #define REG_OR_SUBREG_REG(X) \
2463 (GET_CODE (X) == REG \
2464 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2466 #define REG_OR_SUBREG_RTX(X) \
2467 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2469 #ifndef COSTS_N_INSNS
2470 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2474 arm_rtx_costs (x
, code
, outer
)
2477 enum rtx_code outer
;
2479 enum machine_mode mode
= GET_MODE (x
);
2480 enum rtx_code subcode
;
2496 return COSTS_N_INSNS (1);
2499 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2502 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
2509 return COSTS_N_INSNS (2) + cycles
;
2511 return COSTS_N_INSNS (1) + 16;
2514 return (COSTS_N_INSNS (1)
2515 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
2516 + GET_CODE (SET_DEST (x
)) == MEM
));
2521 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
2523 if (thumb_shiftable_const (INTVAL (x
)))
2524 return COSTS_N_INSNS (2);
2525 return COSTS_N_INSNS (3);
2527 else if (outer
== PLUS
2528 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
2530 else if (outer
== COMPARE
2531 && (unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
2533 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
2534 || outer
== LSHIFTRT
)
2536 return COSTS_N_INSNS (2);
2542 return COSTS_N_INSNS (3);
2561 /* XXX another guess. */
2562 /* Memory costs quite a lot for the first word, but subsequent words
2563 load at the equivalent of a single insn each. */
2564 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
2565 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
2570 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
2575 /* XXX still guessing. */
2576 switch (GET_MODE (XEXP (x
, 0)))
2579 return (1 + (mode
== DImode
? 4 : 0)
2580 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2583 return (4 + (mode
== DImode
? 4 : 0)
2584 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2587 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2601 fprintf (stderr
, "unexpected code for thumb in rtx_costs: %s\n",
2611 /* Memory costs quite a lot for the first word, but subsequent words
2612 load at the equivalent of a single insn each. */
2613 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
2614 + (GET_CODE (x
) == SYMBOL_REF
2615 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
2622 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
2629 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
2631 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
2632 + ((GET_CODE (XEXP (x
, 0)) == REG
2633 || (GET_CODE (XEXP (x
, 0)) == SUBREG
2634 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
2636 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
2637 || (GET_CODE (XEXP (x
, 0)) == SUBREG
2638 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
2640 + ((GET_CODE (XEXP (x
, 1)) == REG
2641 || (GET_CODE (XEXP (x
, 1)) == SUBREG
2642 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
2643 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
2648 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
2649 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2650 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
2651 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
2654 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2655 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2656 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
2657 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
2659 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2660 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
2661 && const_double_rtx_ok_for_fpu (XEXP (x
, 0))))
2664 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
2665 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
2666 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
2667 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
2668 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
2669 || subcode
== ROTATE
|| subcode
== ROTATERT
2671 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
2672 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
2673 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
2674 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
2675 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
2676 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
2677 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
2682 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2683 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
2684 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2685 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
2686 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
2690 case AND
: case XOR
: case IOR
:
2693 /* Normally the frame registers will be spilt into reg+const during
2694 reload, so it is a bad idea to combine them with other instructions,
2695 since then they might not be moved outside of loops. As a compromise
2696 we allow integration with ops that have a constant as their second
2698 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2699 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
2700 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2701 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
2702 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
2706 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
2707 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2708 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2709 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
2712 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
2713 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
2714 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2715 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2716 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
2719 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
2720 return (1 + extra_cost
2721 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
2722 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
2723 || subcode
== ROTATE
|| subcode
== ROTATERT
2725 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2726 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
2727 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
2728 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
2729 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
2730 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
2736 /* There is no point basing this on the tuning, since it is always the
2737 fast variant if it exists at all. */
2738 if (arm_fast_multiply
&& mode
== DImode
2739 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
2740 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2741 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
2744 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
2748 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2750 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
2751 & (unsigned HOST_WIDE_INT
) 0xffffffff);
2752 int add_cost
= const_ok_for_arm (i
) ? 4 : 8;
2755 /* Tune as appropriate. */
2756 int booth_unit_size
= ((tune_flags
& FL_FAST_MULT
) ? 8 : 2);
2758 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
2760 i
>>= booth_unit_size
;
2767 return (((tune_flags
& FL_FAST_MULT
) ? 8 : 30)
2768 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
2769 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4));
2772 if (arm_fast_multiply
&& mode
== SImode
2773 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
2774 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2775 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
2776 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
2777 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
2778 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
2783 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2784 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
2788 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
2790 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
2793 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
2801 return 4 + (mode
== DImode
? 4 : 0);
2804 if (GET_MODE (XEXP (x
, 0)) == QImode
)
2805 return (4 + (mode
== DImode
? 4 : 0)
2806 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2809 switch (GET_MODE (XEXP (x
, 0)))
2812 return (1 + (mode
== DImode
? 4 : 0)
2813 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2816 return (4 + (mode
== DImode
? 4 : 0)
2817 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2820 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2828 if (const_ok_for_arm (INTVAL (x
)))
2829 return outer
== SET
? 2 : -1;
2830 else if (outer
== AND
2831 && const_ok_for_arm (~INTVAL (x
)))
2833 else if ((outer
== COMPARE
2834 || outer
== PLUS
|| outer
== MINUS
)
2835 && const_ok_for_arm (-INTVAL (x
)))
2846 if (const_double_rtx_ok_for_fpu (x
))
2847 return outer
== SET
? 2 : -1;
2848 else if ((outer
== COMPARE
|| outer
== PLUS
)
2849 && neg_const_double_rtx_ok_for_fpu (x
))
2859 arm_adjust_cost (insn
, link
, dep
, cost
)
2867 /* Some true dependencies can have a higher cost depending
2868 on precisely how certain input operands are used. */
2870 && REG_NOTE_KIND (link
) == 0
2871 && recog_memoized (insn
) < 0
2872 && recog_memoized (dep
) < 0)
2874 int shift_opnum
= get_attr_shift (insn
);
2875 enum attr_type attr_type
= get_attr_type (dep
);
2877 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
2878 operand for INSN. If we have a shifted input operand and the
2879 instruction we depend on is another ALU instruction, then we may
2880 have to account for an additional stall. */
2881 if (shift_opnum
!= 0 && attr_type
== TYPE_NORMAL
)
2883 rtx shifted_operand
;
2886 /* Get the shifted operand. */
2887 extract_insn (insn
);
2888 shifted_operand
= recog_data
.operand
[shift_opnum
];
2890 /* Iterate over all the operands in DEP. If we write an operand
2891 that overlaps with SHIFTED_OPERAND, then we have increase the
2892 cost of this dependency. */
2894 preprocess_constraints ();
2895 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2897 /* We can ignore strict inputs. */
2898 if (recog_data
.operand_type
[opno
] == OP_IN
)
2901 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
2908 /* XXX This is not strictly true for the FPA. */
2909 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
2910 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
2913 /* Call insns don't incur a stall, even if they follow a load. */
2914 if (REG_NOTE_KIND (link
) == 0
2915 && GET_CODE (insn
) == CALL_INSN
)
2918 if ((i_pat
= single_set (insn
)) != NULL
2919 && GET_CODE (SET_SRC (i_pat
)) == MEM
2920 && (d_pat
= single_set (dep
)) != NULL
2921 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
2923 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
2924 /* This is a load after a store, there is no conflict if the load reads
2925 from a cached area. Assume that loads from the stack, and from the
2926 constant pool are cached, and that others will miss. This is a
2929 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
2930 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
2931 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
2932 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
2939 /* This code has been fixed for cross compilation. */
2941 static int fpa_consts_inited
= 0;
2943 static const char * const strings_fpa
[8] =
2946 "4", "5", "0.5", "10"
2949 static REAL_VALUE_TYPE values_fpa
[8];
2957 for (i
= 0; i
< 8; i
++)
2959 r
= REAL_VALUE_ATOF (strings_fpa
[i
], DFmode
);
2963 fpa_consts_inited
= 1;
2966 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2969 const_double_rtx_ok_for_fpu (x
)
2975 if (!fpa_consts_inited
)
2978 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2979 if (REAL_VALUE_MINUS_ZERO (r
))
2982 for (i
= 0; i
< 8; i
++)
2983 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
2989 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2992 neg_const_double_rtx_ok_for_fpu (x
)
2998 if (!fpa_consts_inited
)
3001 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3002 r
= REAL_VALUE_NEGATE (r
);
3003 if (REAL_VALUE_MINUS_ZERO (r
))
3006 for (i
= 0; i
< 8; i
++)
3007 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3013 /* Predicates for `match_operand' and `match_operator'. */
3015 /* s_register_operand is the same as register_operand, but it doesn't accept
3018 This function exists because at the time it was put in it led to better
3019 code. SUBREG(MEM) always needs a reload in the places where
3020 s_register_operand is used, and this seemed to lead to excessive
3024 s_register_operand (op
, mode
)
3026 enum machine_mode mode
;
3028 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3031 if (GET_CODE (op
) == SUBREG
)
3032 op
= SUBREG_REG (op
);
3034 /* We don't consider registers whose class is NO_REGS
3035 to be a register operand. */
3036 /* XXX might have to check for lo regs only for thumb ??? */
3037 return (GET_CODE (op
) == REG
3038 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3039 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3042 /* A hard register operand (even before reload. */
3045 arm_hard_register_operand (op
, mode
)
3047 enum machine_mode mode
;
3049 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3052 return (GET_CODE (op
) == REG
3053 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
3056 /* Only accept reg, subreg(reg), const_int. */
3059 reg_or_int_operand (op
, mode
)
3061 enum machine_mode mode
;
3063 if (GET_CODE (op
) == CONST_INT
)
3066 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3069 if (GET_CODE (op
) == SUBREG
)
3070 op
= SUBREG_REG (op
);
3072 /* We don't consider registers whose class is NO_REGS
3073 to be a register operand. */
3074 return (GET_CODE (op
) == REG
3075 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3076 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3079 /* Return 1 if OP is an item in memory, given that we are in reload. */
3082 arm_reload_memory_operand (op
, mode
)
3084 enum machine_mode mode ATTRIBUTE_UNUSED
;
3086 int regno
= true_regnum (op
);
3088 return (!CONSTANT_P (op
)
3090 || (GET_CODE (op
) == REG
3091 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
3094 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3095 memory access (architecture V4).
3096 MODE is QImode if called when computing constraints, or VOIDmode when
3097 emitting patterns. In this latter case we cannot use memory_operand()
3098 because it will fail on badly formed MEMs, which is precisly what we are
3102 bad_signed_byte_operand (op
, mode
)
3104 enum machine_mode mode ATTRIBUTE_UNUSED
;
3107 if ((mode
== QImode
&& !memory_operand (op
, mode
)) || GET_CODE (op
) != MEM
)
3110 if (GET_CODE (op
) != MEM
)
3115 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3116 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3117 && (!s_register_operand (XEXP (op
, 0), VOIDmode
)
3118 || (!s_register_operand (XEXP (op
, 1), VOIDmode
)
3119 && GET_CODE (XEXP (op
, 1)) != CONST_INT
)))
3122 /* Big constants are also bad. */
3123 if (GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
3124 && (INTVAL (XEXP (op
, 1)) > 0xff
3125 || -INTVAL (XEXP (op
, 1)) > 0xff))
3128 /* Everything else is good, or can will automatically be made so. */
3132 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3135 arm_rhs_operand (op
, mode
)
3137 enum machine_mode mode
;
3139 return (s_register_operand (op
, mode
)
3140 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
3143 /* Return TRUE for valid operands for the
3144 rhs of an ARM instruction, or a load. */
3147 arm_rhsm_operand (op
, mode
)
3149 enum machine_mode mode
;
3151 return (s_register_operand (op
, mode
)
3152 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
3153 || memory_operand (op
, mode
));
3156 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3157 constant that is valid when negated. */
3160 arm_add_operand (op
, mode
)
3162 enum machine_mode mode
;
3165 return thumb_cmp_operand (op
, mode
);
3167 return (s_register_operand (op
, mode
)
3168 || (GET_CODE (op
) == CONST_INT
3169 && (const_ok_for_arm (INTVAL (op
))
3170 || const_ok_for_arm (-INTVAL (op
)))));
3174 arm_not_operand (op
, mode
)
3176 enum machine_mode mode
;
3178 return (s_register_operand (op
, mode
)
3179 || (GET_CODE (op
) == CONST_INT
3180 && (const_ok_for_arm (INTVAL (op
))
3181 || const_ok_for_arm (~INTVAL (op
)))));
3184 /* Return TRUE if the operand is a memory reference which contains an
3185 offsettable address. */
3188 offsettable_memory_operand (op
, mode
)
3190 enum machine_mode mode
;
3192 if (mode
== VOIDmode
)
3193 mode
= GET_MODE (op
);
3195 return (mode
== GET_MODE (op
)
3196 && GET_CODE (op
) == MEM
3197 && offsettable_address_p (reload_completed
| reload_in_progress
,
3198 mode
, XEXP (op
, 0)));
3201 /* Return TRUE if the operand is a memory reference which is, or can be
3202 made word aligned by adjusting the offset. */
3205 alignable_memory_operand (op
, mode
)
3207 enum machine_mode mode
;
3211 if (mode
== VOIDmode
)
3212 mode
= GET_MODE (op
);
3214 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
3219 return ((GET_CODE (reg
= op
) == REG
3220 || (GET_CODE (op
) == SUBREG
3221 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
3222 || (GET_CODE (op
) == PLUS
3223 && GET_CODE (XEXP (op
, 1)) == CONST_INT
3224 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
3225 || (GET_CODE (XEXP (op
, 0)) == SUBREG
3226 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
3227 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
3230 /* Similar to s_register_operand, but does not allow hard integer
3234 f_register_operand (op
, mode
)
3236 enum machine_mode mode
;
3238 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3241 if (GET_CODE (op
) == SUBREG
)
3242 op
= SUBREG_REG (op
);
3244 /* We don't consider registers whose class is NO_REGS
3245 to be a register operand. */
3246 return (GET_CODE (op
) == REG
3247 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3248 || REGNO_REG_CLASS (REGNO (op
)) == FPU_REGS
));
3251 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
3254 fpu_rhs_operand (op
, mode
)
3256 enum machine_mode mode
;
3258 if (s_register_operand (op
, mode
))
3261 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3264 if (GET_CODE (op
) == CONST_DOUBLE
)
3265 return const_double_rtx_ok_for_fpu (op
);
3271 fpu_add_operand (op
, mode
)
3273 enum machine_mode mode
;
3275 if (s_register_operand (op
, mode
))
3278 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3281 if (GET_CODE (op
) == CONST_DOUBLE
)
3282 return (const_double_rtx_ok_for_fpu (op
)
3283 || neg_const_double_rtx_ok_for_fpu (op
));
3288 /* Return nonzero if OP is a constant power of two. */
3291 power_of_two_operand (op
, mode
)
3293 enum machine_mode mode ATTRIBUTE_UNUSED
;
3295 if (GET_CODE (op
) == CONST_INT
)
3297 HOST_WIDE_INT value
= INTVAL (op
);
3299 return value
!= 0 && (value
& (value
- 1)) == 0;
3305 /* Return TRUE for a valid operand of a DImode operation.
3306 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3307 Note that this disallows MEM(REG+REG), but allows
3308 MEM(PRE/POST_INC/DEC(REG)). */
3311 di_operand (op
, mode
)
3313 enum machine_mode mode
;
3315 if (s_register_operand (op
, mode
))
3318 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
3321 if (GET_CODE (op
) == SUBREG
)
3322 op
= SUBREG_REG (op
);
3324 switch (GET_CODE (op
))
3331 return memory_address_p (DImode
, XEXP (op
, 0));
3338 /* Like di_operand, but don't accept constants. */
3341 nonimmediate_di_operand (op
, mode
)
3343 enum machine_mode mode
;
3345 if (s_register_operand (op
, mode
))
3348 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
3351 if (GET_CODE (op
) == SUBREG
)
3352 op
= SUBREG_REG (op
);
3354 if (GET_CODE (op
) == MEM
)
3355 return memory_address_p (DImode
, XEXP (op
, 0));
3360 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
3361 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3362 Note that this disallows MEM(REG+REG), but allows
3363 MEM(PRE/POST_INC/DEC(REG)). */
3366 soft_df_operand (op
, mode
)
3368 enum machine_mode mode
;
3370 if (s_register_operand (op
, mode
))
3373 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3376 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
3379 if (GET_CODE (op
) == SUBREG
)
3380 op
= SUBREG_REG (op
);
3382 switch (GET_CODE (op
))
3388 return memory_address_p (DFmode
, XEXP (op
, 0));
3395 /* Like soft_df_operand, but don't accept constants. */
3398 nonimmediate_soft_df_operand (op
, mode
)
3400 enum machine_mode mode
;
3402 if (s_register_operand (op
, mode
))
3405 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3408 if (GET_CODE (op
) == SUBREG
)
3409 op
= SUBREG_REG (op
);
3411 if (GET_CODE (op
) == MEM
)
3412 return memory_address_p (DFmode
, XEXP (op
, 0));
3416 /* Return TRUE for valid index operands. */
3419 index_operand (op
, mode
)
3421 enum machine_mode mode
;
3423 return (s_register_operand (op
, mode
)
3424 || (immediate_operand (op
, mode
)
3425 && (GET_CODE (op
) != CONST_INT
3426 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
3429 /* Return TRUE for valid shifts by a constant. This also accepts any
3430 power of two on the (somewhat overly relaxed) assumption that the
3431 shift operator in this case was a mult. */
3434 const_shift_operand (op
, mode
)
3436 enum machine_mode mode
;
3438 return (power_of_two_operand (op
, mode
)
3439 || (immediate_operand (op
, mode
)
3440 && (GET_CODE (op
) != CONST_INT
3441 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
3444 /* Return TRUE for arithmetic operators which can be combined with a multiply
3448 shiftable_operator (x
, mode
)
3450 enum machine_mode mode
;
3454 if (GET_MODE (x
) != mode
)
3457 code
= GET_CODE (x
);
3459 return (code
== PLUS
|| code
== MINUS
3460 || code
== IOR
|| code
== XOR
|| code
== AND
);
3463 /* Return TRUE for binary logical operators. */
3466 logical_binary_operator (x
, mode
)
3468 enum machine_mode mode
;
3472 if (GET_MODE (x
) != mode
)
3475 code
= GET_CODE (x
);
3477 return (code
== IOR
|| code
== XOR
|| code
== AND
);
3480 /* Return TRUE for shift operators. */
3483 shift_operator (x
, mode
)
3485 enum machine_mode mode
;
3489 if (GET_MODE (x
) != mode
)
3492 code
= GET_CODE (x
);
3495 return power_of_two_operand (XEXP (x
, 1), mode
);
3497 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
3498 || code
== ROTATERT
);
3501 /* Return TRUE if x is EQ or NE. */
3504 equality_operator (x
, mode
)
3506 enum machine_mode mode ATTRIBUTE_UNUSED
;
3508 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
3511 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
3514 arm_comparison_operator (x
, mode
)
3516 enum machine_mode mode
;
3518 return (comparison_operator (x
, mode
)
3519 && GET_CODE (x
) != LTGT
3520 && GET_CODE (x
) != UNEQ
);
3523 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3526 minmax_operator (x
, mode
)
3528 enum machine_mode mode
;
3530 enum rtx_code code
= GET_CODE (x
);
3532 if (GET_MODE (x
) != mode
)
3535 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
3538 /* Return TRUE if this is the condition code register, if we aren't given
3539 a mode, accept any class CCmode register. */
3542 cc_register (x
, mode
)
3544 enum machine_mode mode
;
3546 if (mode
== VOIDmode
)
3548 mode
= GET_MODE (x
);
3550 if (GET_MODE_CLASS (mode
) != MODE_CC
)
3554 if ( GET_MODE (x
) == mode
3555 && GET_CODE (x
) == REG
3556 && REGNO (x
) == CC_REGNUM
)
3562 /* Return TRUE if this is the condition code register, if we aren't given
3563 a mode, accept any class CCmode register which indicates a dominance
3567 dominant_cc_register (x
, mode
)
3569 enum machine_mode mode
;
3571 if (mode
== VOIDmode
)
3573 mode
= GET_MODE (x
);
3575 if (GET_MODE_CLASS (mode
) != MODE_CC
)
3579 if ( mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
3580 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
3581 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
3582 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
3583 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
3586 return cc_register (x
, mode
);
3589 /* Return TRUE if X references a SYMBOL_REF. */
3592 symbol_mentioned_p (x
)
3598 if (GET_CODE (x
) == SYMBOL_REF
)
3601 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3603 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3609 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3610 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
3613 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
3620 /* Return TRUE if X references a LABEL_REF. */
3623 label_mentioned_p (x
)
3629 if (GET_CODE (x
) == LABEL_REF
)
3632 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3633 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3639 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3640 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
3643 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
3654 enum rtx_code code
= GET_CODE (x
);
3658 else if (code
== SMIN
)
3660 else if (code
== UMIN
)
3662 else if (code
== UMAX
)
3668 /* Return 1 if memory locations are adjacent. */
3671 adjacent_mem_locations (a
, b
)
3674 if ((GET_CODE (XEXP (a
, 0)) == REG
3675 || (GET_CODE (XEXP (a
, 0)) == PLUS
3676 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
3677 && (GET_CODE (XEXP (b
, 0)) == REG
3678 || (GET_CODE (XEXP (b
, 0)) == PLUS
3679 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
3681 int val0
= 0, val1
= 0;
3684 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
3686 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
3687 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
3690 reg0
= REGNO (XEXP (a
, 0));
3692 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
3694 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
3695 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
3698 reg1
= REGNO (XEXP (b
, 0));
3700 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
3705 /* Return 1 if OP is a load multiple operation. It is known to be
3706 parallel and the first section will be tested. */
3709 load_multiple_operation (op
, mode
)
3711 enum machine_mode mode ATTRIBUTE_UNUSED
;
3713 HOST_WIDE_INT count
= XVECLEN (op
, 0);
3716 HOST_WIDE_INT i
= 1, base
= 0;
3720 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
3723 /* Check to see if this might be a write-back. */
3724 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
3729 /* Now check it more carefully. */
3730 if (GET_CODE (SET_DEST (elt
)) != REG
3731 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
3732 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
3733 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
3734 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
3738 /* Perform a quick check so we don't blow up below. */
3740 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
3741 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
3742 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
3745 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
3746 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
3748 for (; i
< count
; i
++)
3750 elt
= XVECEXP (op
, 0, i
);
3752 if (GET_CODE (elt
) != SET
3753 || GET_CODE (SET_DEST (elt
)) != REG
3754 || GET_MODE (SET_DEST (elt
)) != SImode
3755 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
3756 || GET_CODE (SET_SRC (elt
)) != MEM
3757 || GET_MODE (SET_SRC (elt
)) != SImode
3758 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
3759 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
3760 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
3761 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
3768 /* Return 1 if OP is a store multiple operation. It is known to be
3769 parallel and the first section will be tested. */
3772 store_multiple_operation (op
, mode
)
3774 enum machine_mode mode ATTRIBUTE_UNUSED
;
3776 HOST_WIDE_INT count
= XVECLEN (op
, 0);
3779 HOST_WIDE_INT i
= 1, base
= 0;
3783 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
3786 /* Check to see if this might be a write-back. */
3787 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
3792 /* Now check it more carefully. */
3793 if (GET_CODE (SET_DEST (elt
)) != REG
3794 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
3795 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
3796 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
3797 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
3801 /* Perform a quick check so we don't blow up below. */
3803 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
3804 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
3805 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
3808 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
3809 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
3811 for (; i
< count
; i
++)
3813 elt
= XVECEXP (op
, 0, i
);
3815 if (GET_CODE (elt
) != SET
3816 || GET_CODE (SET_SRC (elt
)) != REG
3817 || GET_MODE (SET_SRC (elt
)) != SImode
3818 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
3819 || GET_CODE (SET_DEST (elt
)) != MEM
3820 || GET_MODE (SET_DEST (elt
)) != SImode
3821 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
3822 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
3823 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
3824 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
3832 load_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
3837 HOST_WIDE_INT
* load_offset
;
3839 int unsorted_regs
[4];
3840 HOST_WIDE_INT unsorted_offsets
[4];
3845 /* Can only handle 2, 3, or 4 insns at present,
3846 though could be easily extended if required. */
3847 if (nops
< 2 || nops
> 4)
3850 /* Loop over the operands and check that the memory references are
3851 suitable (ie immediate offsets from the same base register). At
3852 the same time, extract the target register, and the memory
3854 for (i
= 0; i
< nops
; i
++)
3859 /* Convert a subreg of a mem into the mem itself. */
3860 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
3861 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
3863 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
3866 /* Don't reorder volatile memory references; it doesn't seem worth
3867 looking for the case where the order is ok anyway. */
3868 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
3871 offset
= const0_rtx
;
3873 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
3874 || (GET_CODE (reg
) == SUBREG
3875 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
3876 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
3877 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
3879 || (GET_CODE (reg
) == SUBREG
3880 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
3881 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
3886 base_reg
= REGNO (reg
);
3887 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
3888 ? REGNO (operands
[i
])
3889 : REGNO (SUBREG_REG (operands
[i
])));
3894 if (base_reg
!= (int) REGNO (reg
))
3895 /* Not addressed from the same base register. */
3898 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
3899 ? REGNO (operands
[i
])
3900 : REGNO (SUBREG_REG (operands
[i
])));
3901 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
3905 /* If it isn't an integer register, or if it overwrites the
3906 base register but isn't the last insn in the list, then
3907 we can't do this. */
3908 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
3909 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
3912 unsorted_offsets
[i
] = INTVAL (offset
);
3915 /* Not a suitable memory address. */
3919 /* All the useful information has now been extracted from the
3920 operands into unsorted_regs and unsorted_offsets; additionally,
3921 order[0] has been set to the lowest numbered register in the
3922 list. Sort the registers into order, and check that the memory
3923 offsets are ascending and adjacent. */
3925 for (i
= 1; i
< nops
; i
++)
3929 order
[i
] = order
[i
- 1];
3930 for (j
= 0; j
< nops
; j
++)
3931 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
3932 && (order
[i
] == order
[i
- 1]
3933 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
3936 /* Have we found a suitable register? if not, one must be used more
3938 if (order
[i
] == order
[i
- 1])
3941 /* Is the memory address adjacent and ascending? */
3942 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
3950 for (i
= 0; i
< nops
; i
++)
3951 regs
[i
] = unsorted_regs
[order
[i
]];
3953 *load_offset
= unsorted_offsets
[order
[0]];
3956 if (unsorted_offsets
[order
[0]] == 0)
3957 return 1; /* ldmia */
3959 if (unsorted_offsets
[order
[0]] == 4)
3960 return 2; /* ldmib */
3962 if (unsorted_offsets
[order
[nops
- 1]] == 0)
3963 return 3; /* ldmda */
3965 if (unsorted_offsets
[order
[nops
- 1]] == -4)
3966 return 4; /* ldmdb */
3968 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3969 if the offset isn't small enough. The reason 2 ldrs are faster
3970 is because these ARMs are able to do more than one cache access
3971 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3972 whilst the ARM8 has a double bandwidth cache. This means that
3973 these cores can do both an instruction fetch and a data fetch in
3974 a single cycle, so the trick of calculating the address into a
3975 scratch register (one of the result regs) and then doing a load
3976 multiple actually becomes slower (and no smaller in code size).
3977 That is the transformation
3979 ldr rd1, [rbase + offset]
3980 ldr rd2, [rbase + offset + 4]
3984 add rd1, rbase, offset
3985 ldmia rd1, {rd1, rd2}
3987 produces worse code -- '3 cycles + any stalls on rd2' instead of
3988 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3989 access per cycle, the first sequence could never complete in less
3990 than 6 cycles, whereas the ldm sequence would only take 5 and
3991 would make better use of sequential accesses if not hitting the
3994 We cheat here and test 'arm_ld_sched' which we currently know to
3995 only be true for the ARM8, ARM9 and StrongARM. If this ever
3996 changes, then the test below needs to be reworked. */
3997 if (nops
== 2 && arm_ld_sched
)
4000 /* Can't do it without setting up the offset, only do this if it takes
4001 no more than one insn. */
4002 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
4003 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
4007 emit_ldm_seq (operands
, nops
)
4013 HOST_WIDE_INT offset
;
4017 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4020 strcpy (buf
, "ldm%?ia\t");
4024 strcpy (buf
, "ldm%?ib\t");
4028 strcpy (buf
, "ldm%?da\t");
4032 strcpy (buf
, "ldm%?db\t");
4037 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4038 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4041 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4042 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4044 output_asm_insn (buf
, operands
);
4046 strcpy (buf
, "ldm%?ia\t");
4053 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4054 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4056 for (i
= 1; i
< nops
; i
++)
4057 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4058 reg_names
[regs
[i
]]);
4060 strcat (buf
, "}\t%@ phole ldm");
4062 output_asm_insn (buf
, operands
);
4067 store_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
4072 HOST_WIDE_INT
* load_offset
;
4074 int unsorted_regs
[4];
4075 HOST_WIDE_INT unsorted_offsets
[4];
4080 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4081 extended if required. */
4082 if (nops
< 2 || nops
> 4)
4085 /* Loop over the operands and check that the memory references are
4086 suitable (ie immediate offsets from the same base register). At
4087 the same time, extract the target register, and the memory
4089 for (i
= 0; i
< nops
; i
++)
4094 /* Convert a subreg of a mem into the mem itself. */
4095 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4096 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
4098 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4101 /* Don't reorder volatile memory references; it doesn't seem worth
4102 looking for the case where the order is ok anyway. */
4103 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4106 offset
= const0_rtx
;
4108 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4109 || (GET_CODE (reg
) == SUBREG
4110 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4111 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4112 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4114 || (GET_CODE (reg
) == SUBREG
4115 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4116 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4121 base_reg
= REGNO (reg
);
4122 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4123 ? REGNO (operands
[i
])
4124 : REGNO (SUBREG_REG (operands
[i
])));
4129 if (base_reg
!= (int) REGNO (reg
))
4130 /* Not addressed from the same base register. */
4133 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
4134 ? REGNO (operands
[i
])
4135 : REGNO (SUBREG_REG (operands
[i
])));
4136 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
4140 /* If it isn't an integer register, then we can't do this. */
4141 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
4144 unsorted_offsets
[i
] = INTVAL (offset
);
4147 /* Not a suitable memory address. */
4151 /* All the useful information has now been extracted from the
4152 operands into unsorted_regs and unsorted_offsets; additionally,
4153 order[0] has been set to the lowest numbered register in the
4154 list. Sort the registers into order, and check that the memory
4155 offsets are ascending and adjacent. */
4157 for (i
= 1; i
< nops
; i
++)
4161 order
[i
] = order
[i
- 1];
4162 for (j
= 0; j
< nops
; j
++)
4163 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
4164 && (order
[i
] == order
[i
- 1]
4165 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
4168 /* Have we found a suitable register? if not, one must be used more
4170 if (order
[i
] == order
[i
- 1])
4173 /* Is the memory address adjacent and ascending? */
4174 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
4182 for (i
= 0; i
< nops
; i
++)
4183 regs
[i
] = unsorted_regs
[order
[i
]];
4185 *load_offset
= unsorted_offsets
[order
[0]];
4188 if (unsorted_offsets
[order
[0]] == 0)
4189 return 1; /* stmia */
4191 if (unsorted_offsets
[order
[0]] == 4)
4192 return 2; /* stmib */
4194 if (unsorted_offsets
[order
[nops
- 1]] == 0)
4195 return 3; /* stmda */
4197 if (unsorted_offsets
[order
[nops
- 1]] == -4)
4198 return 4; /* stmdb */
4204 emit_stm_seq (operands
, nops
)
4210 HOST_WIDE_INT offset
;
4214 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4217 strcpy (buf
, "stm%?ia\t");
4221 strcpy (buf
, "stm%?ib\t");
4225 strcpy (buf
, "stm%?da\t");
4229 strcpy (buf
, "stm%?db\t");
4236 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4237 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4239 for (i
= 1; i
< nops
; i
++)
4240 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4241 reg_names
[regs
[i
]]);
4243 strcat (buf
, "}\t%@ phole stm");
4245 output_asm_insn (buf
, operands
);
4250 multi_register_push (op
, mode
)
4252 enum machine_mode mode ATTRIBUTE_UNUSED
;
4254 if (GET_CODE (op
) != PARALLEL
4255 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4256 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
4257 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
4263 /* Routines for use in generating RTL. */
4266 arm_gen_load_multiple (base_regno
, count
, from
, up
, write_back
, unchanging_p
,
4267 in_struct_p
, scalar_p
)
4279 int sign
= up
? 1 : -1;
4282 /* XScale has load-store double instructions, but they have stricter
4283 alignment requirements than load-store multiple, so we can not
4286 For XScale ldm requires 2 + NREGS cycles to complete and blocks
4287 the pipeline until completion.
4295 An ldr instruction takes 1-3 cycles, but does not block the
4304 Best case ldr will always win. However, the more ldr instructions
4305 we issue, the less likely we are to be able to schedule them well.
4306 Using ldr instructions also increases code size.
4308 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
4309 for counts of 3 or 4 regs. */
4310 if (arm_is_xscale
&& count
<= 2 && ! optimize_size
)
4316 for (i
= 0; i
< count
; i
++)
4318 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
4319 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4320 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4321 MEM_SCALAR_P (mem
) = scalar_p
;
4322 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
4326 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
4328 seq
= gen_sequence ();
4334 result
= gen_rtx_PARALLEL (VOIDmode
,
4335 rtvec_alloc (count
+ (write_back
? 1 : 0)));
4338 XVECEXP (result
, 0, 0)
4339 = gen_rtx_SET (GET_MODE (from
), from
,
4340 plus_constant (from
, count
* 4 * sign
));
4345 for (j
= 0; i
< count
; i
++, j
++)
4347 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
4348 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4349 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4350 MEM_SCALAR_P (mem
) = scalar_p
;
4351 XVECEXP (result
, 0, i
)
4352 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
4359 arm_gen_store_multiple (base_regno
, count
, to
, up
, write_back
, unchanging_p
,
4360 in_struct_p
, scalar_p
)
4372 int sign
= up
? 1 : -1;
4375 /* See arm_gen_load_multiple for discussion of
4376 the pros/cons of ldm/stm usage for XScale. */
4377 if (arm_is_xscale
&& count
<= 2 && ! optimize_size
)
4383 for (i
= 0; i
< count
; i
++)
4385 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
4386 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4387 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4388 MEM_SCALAR_P (mem
) = scalar_p
;
4389 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
4393 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
4395 seq
= gen_sequence ();
4401 result
= gen_rtx_PARALLEL (VOIDmode
,
4402 rtvec_alloc (count
+ (write_back
? 1 : 0)));
4405 XVECEXP (result
, 0, 0)
4406 = gen_rtx_SET (GET_MODE (to
), to
,
4407 plus_constant (to
, count
* 4 * sign
));
4412 for (j
= 0; i
< count
; i
++, j
++)
4414 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
4415 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4416 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4417 MEM_SCALAR_P (mem
) = scalar_p
;
4419 XVECEXP (result
, 0, i
)
4420 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
4427 arm_gen_movstrqi (operands
)
4430 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
4433 rtx st_src
, st_dst
, fin_src
, fin_dst
;
4434 rtx part_bytes_reg
= NULL
;
4436 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
4437 int dst_scalar_p
, src_scalar_p
;
4439 if (GET_CODE (operands
[2]) != CONST_INT
4440 || GET_CODE (operands
[3]) != CONST_INT
4441 || INTVAL (operands
[2]) > 64
4442 || INTVAL (operands
[3]) & 3)
4445 st_dst
= XEXP (operands
[0], 0);
4446 st_src
= XEXP (operands
[1], 0);
4448 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
4449 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
4450 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
4451 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
4452 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
4453 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
4455 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
4456 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
4458 in_words_to_go
= NUM_INTS (INTVAL (operands
[2]));
4459 out_words_to_go
= INTVAL (operands
[2]) / 4;
4460 last_bytes
= INTVAL (operands
[2]) & 3;
4462 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
4463 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
4465 for (i
= 0; in_words_to_go
>= 2; i
+=4)
4467 if (in_words_to_go
> 4)
4468 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
4473 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
4474 FALSE
, src_unchanging_p
,
4475 src_in_struct_p
, src_scalar_p
));
4477 if (out_words_to_go
)
4479 if (out_words_to_go
> 4)
4480 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
4484 else if (out_words_to_go
!= 1)
4485 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
4494 mem
= gen_rtx_MEM (SImode
, dst
);
4495 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4496 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4497 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4498 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
4499 if (last_bytes
!= 0)
4500 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
4504 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
4505 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
4508 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
4509 if (out_words_to_go
)
4513 mem
= gen_rtx_MEM (SImode
, src
);
4514 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
4515 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
4516 MEM_SCALAR_P (mem
) = src_scalar_p
;
4517 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
4518 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
4520 mem
= gen_rtx_MEM (SImode
, dst
);
4521 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4522 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4523 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4524 emit_move_insn (mem
, sreg
);
4525 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
4528 if (in_words_to_go
) /* Sanity check */
4534 if (in_words_to_go
< 0)
4537 mem
= gen_rtx_MEM (SImode
, src
);
4538 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
4539 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
4540 MEM_SCALAR_P (mem
) = src_scalar_p
;
4541 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
4544 if (last_bytes
&& part_bytes_reg
== NULL
)
4547 if (BYTES_BIG_ENDIAN
&& last_bytes
)
4549 rtx tmp
= gen_reg_rtx (SImode
);
4551 /* The bytes we want are in the top end of the word. */
4552 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
4553 GEN_INT (8 * (4 - last_bytes
))));
4554 part_bytes_reg
= tmp
;
4558 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
4559 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4560 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4561 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4562 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
4566 tmp
= gen_reg_rtx (SImode
);
4567 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
4568 part_bytes_reg
= tmp
;
4577 mem
= gen_rtx_MEM (HImode
, dst
);
4578 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4579 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4580 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4581 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
4585 rtx tmp
= gen_reg_rtx (SImode
);
4587 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (2)));
4588 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
4589 part_bytes_reg
= tmp
;
4595 mem
= gen_rtx_MEM (QImode
, dst
);
4596 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4597 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4598 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4599 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
4606 /* Generate a memory reference for a half word, such that it will be loaded
4607 into the top 16 bits of the word. We can assume that the address is
4608 known to be alignable and of the form reg, or plus (reg, const). */
4611 arm_gen_rotated_half_load (memref
)
4614 HOST_WIDE_INT offset
= 0;
4615 rtx base
= XEXP (memref
, 0);
4617 if (GET_CODE (base
) == PLUS
)
4619 offset
= INTVAL (XEXP (base
, 1));
4620 base
= XEXP (base
, 0);
4623 /* If we aren't allowed to generate unaligned addresses, then fail. */
4624 if (TARGET_MMU_TRAPS
4625 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
4628 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
4630 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
4633 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
4636 /* Select a dominance comparison mode if possible. We support three forms.
4637 COND_OR == 0 => (X && Y)
4638 COND_OR == 1 => ((! X( || Y)
4639 COND_OR == 2 => (X || Y)
4640 If we are unable to support a dominance comparsison we return CC mode.
4641 This will then fail to match for the RTL expressions that generate this
4644 static enum machine_mode
4645 select_dominance_cc_mode (x
, y
, cond_or
)
4648 HOST_WIDE_INT cond_or
;
4650 enum rtx_code cond1
, cond2
;
4653 /* Currently we will probably get the wrong result if the individual
4654 comparisons are not simple. This also ensures that it is safe to
4655 reverse a comparison if necessary. */
4656 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
4658 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
4662 /* The if_then_else variant of this tests the second condition if the
4663 first passes, but is true if the first fails. Reverse the first
4664 condition to get a true "inclusive-or" expression. */
4666 cond1
= reverse_condition (cond1
);
4668 /* If the comparisons are not equal, and one doesn't dominate the other,
4669 then we can't do this. */
4671 && !comparison_dominates_p (cond1
, cond2
)
4672 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
4677 enum rtx_code temp
= cond1
;
4685 if (cond2
== EQ
|| !cond_or
)
4690 case LE
: return CC_DLEmode
;
4691 case LEU
: return CC_DLEUmode
;
4692 case GE
: return CC_DGEmode
;
4693 case GEU
: return CC_DGEUmode
;
4700 if (cond2
== LT
|| !cond_or
)
4709 if (cond2
== GT
|| !cond_or
)
4718 if (cond2
== LTU
|| !cond_or
)
4727 if (cond2
== GTU
|| !cond_or
)
4735 /* The remaining cases only occur when both comparisons are the
4760 arm_select_cc_mode (op
, x
, y
)
4765 /* All floating point compares return CCFP if it is an equality
4766 comparison, and CCFPE otherwise. */
4767 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
4794 /* A compare with a shifted operand. Because of canonicalization, the
4795 comparison will have to be swapped when we emit the assembler. */
4796 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
4797 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
4798 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
4799 || GET_CODE (x
) == ROTATERT
))
4802 /* This is a special case that is used by combine to allow a
4803 comparison of a shifted byte load to be split into a zero-extend
4804 followed by a comparison of the shifted integer (only valid for
4805 equalities and unsigned inequalities). */
4806 if (GET_MODE (x
) == SImode
4807 && GET_CODE (x
) == ASHIFT
4808 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
4809 && GET_CODE (XEXP (x
, 0)) == SUBREG
4810 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
4811 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
4812 && (op
== EQ
|| op
== NE
4813 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
4814 && GET_CODE (y
) == CONST_INT
)
4817 /* A construct for a conditional compare, if the false arm contains
4818 0, then both conditions must be true, otherwise either condition
4819 must be true. Not all conditions are possible, so CCmode is
4820 returned if it can't be done. */
4821 if (GET_CODE (x
) == IF_THEN_ELSE
4822 && (XEXP (x
, 2) == const0_rtx
4823 || XEXP (x
, 2) == const1_rtx
)
4824 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4825 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4826 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
4827 INTVAL (XEXP (x
, 2)));
4829 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
4830 if (GET_CODE (x
) == AND
4831 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4832 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4833 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1), 0);
4835 if (GET_CODE (x
) == IOR
4836 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4837 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4838 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1), 2);
4840 /* An operation that sets the condition codes as a side-effect, the
4841 V flag is not set correctly, so we can only use comparisons where
4842 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4844 if (GET_MODE (x
) == SImode
4846 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
4847 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
4848 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
4849 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
4850 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
4851 || GET_CODE (x
) == LSHIFTRT
4852 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
4853 || GET_CODE (x
) == ROTATERT
|| GET_CODE (x
) == ZERO_EXTRACT
))
4856 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
4859 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
4860 && GET_CODE (x
) == PLUS
4861 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
4867 /* X and Y are two things to compare using CODE. Emit the compare insn and
4868 return the rtx for register 0 in the proper mode. FP means this is a
4869 floating point compare: I don't think that it is needed on the arm. */
4872 arm_gen_compare_reg (code
, x
, y
)
4876 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
4877 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
4879 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
4880 gen_rtx_COMPARE (mode
, x
, y
)));
4886 arm_reload_in_hi (operands
)
4889 rtx ref
= operands
[1];
4891 HOST_WIDE_INT offset
= 0;
4893 if (GET_CODE (ref
) == SUBREG
)
4895 offset
= SUBREG_BYTE (ref
);
4896 ref
= SUBREG_REG (ref
);
4899 if (GET_CODE (ref
) == REG
)
4901 /* We have a pseudo which has been spilt onto the stack; there
4902 are two cases here: the first where there is a simple
4903 stack-slot replacement and a second where the stack-slot is
4904 out of range, or is used as a subreg. */
4905 if (reg_equiv_mem
[REGNO (ref
)])
4907 ref
= reg_equiv_mem
[REGNO (ref
)];
4908 base
= find_replacement (&XEXP (ref
, 0));
4911 /* The slot is out of range, or was dressed up in a SUBREG. */
4912 base
= reg_equiv_address
[REGNO (ref
)];
4915 base
= find_replacement (&XEXP (ref
, 0));
4917 /* Handle the case where the address is too complex to be offset by 1. */
4918 if (GET_CODE (base
) == MINUS
4919 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
4921 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
4923 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
4926 else if (GET_CODE (base
) == PLUS
)
4928 /* The addend must be CONST_INT, or we would have dealt with it above. */
4929 HOST_WIDE_INT hi
, lo
;
4931 offset
+= INTVAL (XEXP (base
, 1));
4932 base
= XEXP (base
, 0);
4934 /* Rework the address into a legal sequence of insns. */
4935 /* Valid range for lo is -4095 -> 4095 */
4938 : -((-offset
) & 0xfff));
4940 /* Corner case, if lo is the max offset then we would be out of range
4941 once we have added the additional 1 below, so bump the msb into the
4942 pre-loading insn(s). */
4946 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
4947 ^ (HOST_WIDE_INT
) 0x80000000)
4948 - (HOST_WIDE_INT
) 0x80000000);
4950 if (hi
+ lo
!= offset
)
4955 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
4957 /* Get the base address; addsi3 knows how to handle constants
4958 that require more than one insn. */
4959 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
4965 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
4966 emit_insn (gen_zero_extendqisi2 (scratch
,
4967 gen_rtx_MEM (QImode
,
4968 plus_constant (base
,
4970 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
4971 gen_rtx_MEM (QImode
,
4972 plus_constant (base
,
4974 if (!BYTES_BIG_ENDIAN
)
4975 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
4976 gen_rtx_IOR (SImode
,
4979 gen_rtx_SUBREG (SImode
, operands
[0], 0),
4983 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
4984 gen_rtx_IOR (SImode
,
4985 gen_rtx_ASHIFT (SImode
, scratch
,
4987 gen_rtx_SUBREG (SImode
, operands
[0],
4991 /* Handle storing a half-word to memory during reload by synthesising as two
4992 byte stores. Take care not to clobber the input values until after we
4993 have moved them somewhere safe. This code assumes that if the DImode
4994 scratch in operands[2] overlaps either the input value or output address
4995 in some way, then that value must die in this insn (we absolutely need
4996 two scratch registers for some corner cases). */
4999 arm_reload_out_hi (operands
)
5002 rtx ref
= operands
[0];
5003 rtx outval
= operands
[1];
5005 HOST_WIDE_INT offset
= 0;
5007 if (GET_CODE (ref
) == SUBREG
)
5009 offset
= SUBREG_BYTE (ref
);
5010 ref
= SUBREG_REG (ref
);
5013 if (GET_CODE (ref
) == REG
)
5015 /* We have a pseudo which has been spilt onto the stack; there
5016 are two cases here: the first where there is a simple
5017 stack-slot replacement and a second where the stack-slot is
5018 out of range, or is used as a subreg. */
5019 if (reg_equiv_mem
[REGNO (ref
)])
5021 ref
= reg_equiv_mem
[REGNO (ref
)];
5022 base
= find_replacement (&XEXP (ref
, 0));
5025 /* The slot is out of range, or was dressed up in a SUBREG. */
5026 base
= reg_equiv_address
[REGNO (ref
)];
5029 base
= find_replacement (&XEXP (ref
, 0));
5031 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5033 /* Handle the case where the address is too complex to be offset by 1. */
5034 if (GET_CODE (base
) == MINUS
5035 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
5037 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5039 /* Be careful not to destroy OUTVAL. */
5040 if (reg_overlap_mentioned_p (base_plus
, outval
))
5042 /* Updating base_plus might destroy outval, see if we can
5043 swap the scratch and base_plus. */
5044 if (!reg_overlap_mentioned_p (scratch
, outval
))
5047 scratch
= base_plus
;
5052 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5054 /* Be conservative and copy OUTVAL into the scratch now,
5055 this should only be necessary if outval is a subreg
5056 of something larger than a word. */
5057 /* XXX Might this clobber base? I can't see how it can,
5058 since scratch is known to overlap with OUTVAL, and
5059 must be wider than a word. */
5060 emit_insn (gen_movhi (scratch_hi
, outval
));
5061 outval
= scratch_hi
;
5065 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5068 else if (GET_CODE (base
) == PLUS
)
5070 /* The addend must be CONST_INT, or we would have dealt with it above. */
5071 HOST_WIDE_INT hi
, lo
;
5073 offset
+= INTVAL (XEXP (base
, 1));
5074 base
= XEXP (base
, 0);
5076 /* Rework the address into a legal sequence of insns. */
5077 /* Valid range for lo is -4095 -> 4095 */
5080 : -((-offset
) & 0xfff));
5082 /* Corner case, if lo is the max offset then we would be out of range
5083 once we have added the additional 1 below, so bump the msb into the
5084 pre-loading insn(s). */
5088 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5089 ^ (HOST_WIDE_INT
) 0x80000000)
5090 - (HOST_WIDE_INT
) 0x80000000);
5092 if (hi
+ lo
!= offset
)
5097 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5099 /* Be careful not to destroy OUTVAL. */
5100 if (reg_overlap_mentioned_p (base_plus
, outval
))
5102 /* Updating base_plus might destroy outval, see if we
5103 can swap the scratch and base_plus. */
5104 if (!reg_overlap_mentioned_p (scratch
, outval
))
5107 scratch
= base_plus
;
5112 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5114 /* Be conservative and copy outval into scratch now,
5115 this should only be necessary if outval is a
5116 subreg of something larger than a word. */
5117 /* XXX Might this clobber base? I can't see how it
5118 can, since scratch is known to overlap with
5120 emit_insn (gen_movhi (scratch_hi
, outval
));
5121 outval
= scratch_hi
;
5125 /* Get the base address; addsi3 knows how to handle constants
5126 that require more than one insn. */
5127 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5133 if (BYTES_BIG_ENDIAN
)
5135 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5136 plus_constant (base
, offset
+ 1)),
5137 gen_lowpart (QImode
, outval
)));
5138 emit_insn (gen_lshrsi3 (scratch
,
5139 gen_rtx_SUBREG (SImode
, outval
, 0),
5141 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5142 gen_lowpart (QImode
, scratch
)));
5146 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5147 gen_lowpart (QImode
, outval
)));
5148 emit_insn (gen_lshrsi3 (scratch
,
5149 gen_rtx_SUBREG (SImode
, outval
, 0),
5151 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5152 plus_constant (base
, offset
+ 1)),
5153 gen_lowpart (QImode
, scratch
)));
5157 /* Print a symbolic form of X to the debug file, F. */
5160 arm_print_value (f
, x
)
5164 switch (GET_CODE (x
))
5167 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
5171 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
5175 fprintf (f
, "\"%s\"", XSTR (x
, 0));
5179 fprintf (f
, "`%s'", XSTR (x
, 0));
5183 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
5187 arm_print_value (f
, XEXP (x
, 0));
5191 arm_print_value (f
, XEXP (x
, 0));
5193 arm_print_value (f
, XEXP (x
, 1));
5201 fprintf (f
, "????");
5206 /* Routines for manipulation of the constant pool. */
5208 /* Arm instructions cannot load a large constant directly into a
5209 register; they have to come from a pc relative load. The constant
5210 must therefore be placed in the addressable range of the pc
5211 relative load. Depending on the precise pc relative load
5212 instruction the range is somewhere between 256 bytes and 4k. This
5213 means that we often have to dump a constant inside a function, and
5214 generate code to branch around it.
5216 It is important to minimize this, since the branches will slow
5217 things down and make the code larger.
5219 Normally we can hide the table after an existing unconditional
5220 branch so that there is no interruption of the flow, but in the
5221 worst case the code looks like this:
5239 We fix this by performing a scan after scheduling, which notices
5240 which instructions need to have their operands fetched from the
5241 constant table and builds the table.
5243 The algorithm starts by building a table of all the constants that
5244 need fixing up and all the natural barriers in the function (places
5245 where a constant table can be dropped without breaking the flow).
5246 For each fixup we note how far the pc-relative replacement will be
5247 able to reach and the offset of the instruction into the function.
5249 Having built the table we then group the fixes together to form
5250 tables that are as large as possible (subject to addressing
5251 constraints) and emit each table of constants after the last
5252 barrier that is within range of all the instructions in the group.
5253 If a group does not contain a barrier, then we forcibly create one
5254 by inserting a jump instruction into the flow. Once the table has
5255 been inserted, the insns are then modified to reference the
5256 relevant entry in the pool.
5258 Possible enhancements to the algorithm (not implemented) are:
5260 1) For some processors and object formats, there may be benefit in
5261 aligning the pools to the start of cache lines; this alignment
5262 would need to be taken into account when calculating addressability
5265 /* These typedefs are located at the start of this file, so that
5266 they can be used in the prototypes there. This comment is to
5267 remind readers of that fact so that the following structures
5268 can be understood more easily.
5270 typedef struct minipool_node Mnode;
5271 typedef struct minipool_fixup Mfix; */
5273 struct minipool_node
5275 /* Doubly linked chain of entries. */
5278 /* The maximum offset into the code that this entry can be placed. While
5279 pushing fixes for forward references, all entries are sorted in order
5280 of increasing max_address. */
5281 HOST_WIDE_INT max_address
;
5282 /* Similarly for an entry inserted for a backwards ref. */
5283 HOST_WIDE_INT min_address
;
5284 /* The number of fixes referencing this entry. This can become zero
5285 if we "unpush" an entry. In this case we ignore the entry when we
5286 come to emit the code. */
5288 /* The offset from the start of the minipool. */
5289 HOST_WIDE_INT offset
;
5290 /* The value in table. */
5292 /* The mode of value. */
5293 enum machine_mode mode
;
5297 struct minipool_fixup
5301 HOST_WIDE_INT address
;
5303 enum machine_mode mode
;
5307 HOST_WIDE_INT forwards
;
5308 HOST_WIDE_INT backwards
;
5311 /* Fixes less than a word need padding out to a word boundary. */
5312 #define MINIPOOL_FIX_SIZE(mode) \
5313 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
5315 static Mnode
* minipool_vector_head
;
5316 static Mnode
* minipool_vector_tail
;
5317 static rtx minipool_vector_label
;
5319 /* The linked list of all minipool fixes required for this function. */
5320 Mfix
* minipool_fix_head
;
5321 Mfix
* minipool_fix_tail
;
5322 /* The fix entry for the current minipool, once it has been placed. */
5323 Mfix
* minipool_barrier
;
5325 /* Determines if INSN is the start of a jump table. Returns the end
5326 of the TABLE or NULL_RTX. */
5329 is_jump_table (insn
)
5334 if (GET_CODE (insn
) == JUMP_INSN
5335 && JUMP_LABEL (insn
) != NULL
5336 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
5337 == next_real_insn (insn
))
5339 && GET_CODE (table
) == JUMP_INSN
5340 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
5341 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
5347 #ifndef JUMP_TABLES_IN_TEXT_SECTION
5348 #define JUMP_TABLES_IN_TEXT_SECTION 0
5351 static HOST_WIDE_INT
5352 get_jump_table_size (insn
)
5355 /* ADDR_VECs only take room if read-only data does into the text
5357 if (JUMP_TABLES_IN_TEXT_SECTION
5358 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
5363 rtx body
= PATTERN (insn
);
5364 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
5366 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
5372 /* Move a minipool fix MP from its current location to before MAX_MP.
5373 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5374 contrains may need updating. */
5377 move_minipool_fix_forward_ref (mp
, max_mp
, max_address
)
5380 HOST_WIDE_INT max_address
;
5382 /* This should never be true and the code below assumes these are
5389 if (max_address
< mp
->max_address
)
5390 mp
->max_address
= max_address
;
5394 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
5395 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
5397 mp
->max_address
= max_address
;
5399 /* Unlink MP from its current position. Since max_mp is non-null,
5400 mp->prev must be non-null. */
5401 mp
->prev
->next
= mp
->next
;
5402 if (mp
->next
!= NULL
)
5403 mp
->next
->prev
= mp
->prev
;
5405 minipool_vector_tail
= mp
->prev
;
5407 /* Re-insert it before MAX_MP. */
5409 mp
->prev
= max_mp
->prev
;
5412 if (mp
->prev
!= NULL
)
5413 mp
->prev
->next
= mp
;
5415 minipool_vector_head
= mp
;
5418 /* Save the new entry. */
5421 /* Scan over the preceding entries and adjust their addresses as
5423 while (mp
->prev
!= NULL
5424 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
5426 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
5433 /* Add a constant to the minipool for a forward reference. Returns the
5434 node added or NULL if the constant will not fit in this pool. */
5437 add_minipool_forward_ref (fix
)
5440 /* If set, max_mp is the first pool_entry that has a lower
5441 constraint than the one we are trying to add. */
5442 Mnode
* max_mp
= NULL
;
5443 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
5446 /* If this fix's address is greater than the address of the first
5447 entry, then we can't put the fix in this pool. We subtract the
5448 size of the current fix to ensure that if the table is fully
5449 packed we still have enough room to insert this value by suffling
5450 the other fixes forwards. */
5451 if (minipool_vector_head
&&
5452 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
5455 /* Scan the pool to see if a constant with the same value has
5456 already been added. While we are doing this, also note the
5457 location where we must insert the constant if it doesn't already
5459 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5461 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
5462 && fix
->mode
== mp
->mode
5463 && (GET_CODE (fix
->value
) != CODE_LABEL
5464 || (CODE_LABEL_NUMBER (fix
->value
)
5465 == CODE_LABEL_NUMBER (mp
->value
)))
5466 && rtx_equal_p (fix
->value
, mp
->value
))
5468 /* More than one fix references this entry. */
5470 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
5473 /* Note the insertion point if necessary. */
5475 && mp
->max_address
> max_address
)
5479 /* The value is not currently in the minipool, so we need to create
5480 a new entry for it. If MAX_MP is NULL, the entry will be put on
5481 the end of the list since the placement is less constrained than
5482 any existing entry. Otherwise, we insert the new fix before
5483 MAX_MP and, if neceesary, adjust the constraints on the other
5485 mp
= xmalloc (sizeof (* mp
));
5486 mp
->fix_size
= fix
->fix_size
;
5487 mp
->mode
= fix
->mode
;
5488 mp
->value
= fix
->value
;
5490 /* Not yet required for a backwards ref. */
5491 mp
->min_address
= -65536;
5495 mp
->max_address
= max_address
;
5497 mp
->prev
= minipool_vector_tail
;
5499 if (mp
->prev
== NULL
)
5501 minipool_vector_head
= mp
;
5502 minipool_vector_label
= gen_label_rtx ();
5505 mp
->prev
->next
= mp
;
5507 minipool_vector_tail
= mp
;
5511 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
5512 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
5514 mp
->max_address
= max_address
;
5517 mp
->prev
= max_mp
->prev
;
5519 if (mp
->prev
!= NULL
)
5520 mp
->prev
->next
= mp
;
5522 minipool_vector_head
= mp
;
5525 /* Save the new entry. */
5528 /* Scan over the preceding entries and adjust their addresses as
5530 while (mp
->prev
!= NULL
5531 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
5533 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
5541 move_minipool_fix_backward_ref (mp
, min_mp
, min_address
)
5544 HOST_WIDE_INT min_address
;
5546 HOST_WIDE_INT offset
;
5548 /* This should never be true, and the code below assumes these are
5555 if (min_address
> mp
->min_address
)
5556 mp
->min_address
= min_address
;
5560 /* We will adjust this below if it is too loose. */
5561 mp
->min_address
= min_address
;
5563 /* Unlink MP from its current position. Since min_mp is non-null,
5564 mp->next must be non-null. */
5565 mp
->next
->prev
= mp
->prev
;
5566 if (mp
->prev
!= NULL
)
5567 mp
->prev
->next
= mp
->next
;
5569 minipool_vector_head
= mp
->next
;
5571 /* Reinsert it after MIN_MP. */
5573 mp
->next
= min_mp
->next
;
5575 if (mp
->next
!= NULL
)
5576 mp
->next
->prev
= mp
;
5578 minipool_vector_tail
= mp
;
5584 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5586 mp
->offset
= offset
;
5587 if (mp
->refcount
> 0)
5588 offset
+= mp
->fix_size
;
5590 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
5591 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
5597 /* Add a constant to the minipool for a backward reference. Returns the
5598 node added or NULL if the constant will not fit in this pool.
5600 Note that the code for insertion for a backwards reference can be
5601 somewhat confusing because the calculated offsets for each fix do
5602 not take into account the size of the pool (which is still under
5606 add_minipool_backward_ref (fix
)
5609 /* If set, min_mp is the last pool_entry that has a lower constraint
5610 than the one we are trying to add. */
5611 Mnode
* min_mp
= NULL
;
5612 /* This can be negative, since it is only a constraint. */
5613 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
5616 /* If we can't reach the current pool from this insn, or if we can't
5617 insert this entry at the end of the pool without pushing other
5618 fixes out of range, then we don't try. This ensures that we
5619 can't fail later on. */
5620 if (min_address
>= minipool_barrier
->address
5621 || (minipool_vector_tail
->min_address
+ fix
->fix_size
5622 >= minipool_barrier
->address
))
5625 /* Scan the pool to see if a constant with the same value has
5626 already been added. While we are doing this, also note the
5627 location where we must insert the constant if it doesn't already
5629 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
5631 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
5632 && fix
->mode
== mp
->mode
5633 && (GET_CODE (fix
->value
) != CODE_LABEL
5634 || (CODE_LABEL_NUMBER (fix
->value
)
5635 == CODE_LABEL_NUMBER (mp
->value
)))
5636 && rtx_equal_p (fix
->value
, mp
->value
)
5637 /* Check that there is enough slack to move this entry to the
5638 end of the table (this is conservative). */
5640 > (minipool_barrier
->address
5641 + minipool_vector_tail
->offset
5642 + minipool_vector_tail
->fix_size
)))
5645 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
5649 mp
->min_address
+= fix
->fix_size
;
5652 /* Note the insertion point if necessary. */
5653 if (mp
->min_address
< min_address
)
5655 else if (mp
->max_address
5656 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
5658 /* Inserting before this entry would push the fix beyond
5659 its maximum address (which can happen if we have
5660 re-located a forwards fix); force the new fix to come
5663 min_address
= mp
->min_address
+ fix
->fix_size
;
5668 /* We need to create a new entry. */
5669 mp
= xmalloc (sizeof (* mp
));
5670 mp
->fix_size
= fix
->fix_size
;
5671 mp
->mode
= fix
->mode
;
5672 mp
->value
= fix
->value
;
5674 mp
->max_address
= minipool_barrier
->address
+ 65536;
5676 mp
->min_address
= min_address
;
5681 mp
->next
= minipool_vector_head
;
5683 if (mp
->next
== NULL
)
5685 minipool_vector_tail
= mp
;
5686 minipool_vector_label
= gen_label_rtx ();
5689 mp
->next
->prev
= mp
;
5691 minipool_vector_head
= mp
;
5695 mp
->next
= min_mp
->next
;
5699 if (mp
->next
!= NULL
)
5700 mp
->next
->prev
= mp
;
5702 minipool_vector_tail
= mp
;
5705 /* Save the new entry. */
5713 /* Scan over the following entries and adjust their offsets. */
5714 while (mp
->next
!= NULL
)
5716 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
5717 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
5720 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
5722 mp
->next
->offset
= mp
->offset
;
5731 assign_minipool_offsets (barrier
)
5734 HOST_WIDE_INT offset
= 0;
5737 minipool_barrier
= barrier
;
5739 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5741 mp
->offset
= offset
;
5743 if (mp
->refcount
> 0)
5744 offset
+= mp
->fix_size
;
5748 /* Output the literal table */
5750 dump_minipool (scan
)
5757 fprintf (rtl_dump_file
,
5758 ";; Emitting minipool after insn %u; address %ld\n",
5759 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
);
5761 scan
= emit_label_after (gen_label_rtx (), scan
);
5762 scan
= emit_insn_after (gen_align_4 (), scan
);
5763 scan
= emit_label_after (minipool_vector_label
, scan
);
5765 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
5767 if (mp
->refcount
> 0)
5771 fprintf (rtl_dump_file
,
5772 ";; Offset %u, min %ld, max %ld ",
5773 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
5774 (unsigned long) mp
->max_address
);
5775 arm_print_value (rtl_dump_file
, mp
->value
);
5776 fputc ('\n', rtl_dump_file
);
5779 switch (mp
->fix_size
)
5781 #ifdef HAVE_consttable_1
5783 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
5787 #ifdef HAVE_consttable_2
5789 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
5793 #ifdef HAVE_consttable_4
5795 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
5799 #ifdef HAVE_consttable_8
5801 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
5815 minipool_vector_head
= minipool_vector_tail
= NULL
;
5816 scan
= emit_insn_after (gen_consttable_end (), scan
);
5817 scan
= emit_barrier_after (scan
);
5820 /* Return the cost of forcibly inserting a barrier after INSN. */
5823 arm_barrier_cost (insn
)
5826 /* Basing the location of the pool on the loop depth is preferable,
5827 but at the moment, the basic block information seems to be
5828 corrupt by this stage of the compilation. */
5830 rtx next
= next_nonnote_insn (insn
);
5832 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
5835 switch (GET_CODE (insn
))
5838 /* It will always be better to place the table before the label, rather
5847 return base_cost
- 10;
5850 return base_cost
+ 10;
5854 /* Find the best place in the insn stream in the range
5855 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5856 Create the barrier by inserting a jump and add a new fix entry for
5860 create_fix_barrier (fix
, max_address
)
5862 HOST_WIDE_INT max_address
;
5864 HOST_WIDE_INT count
= 0;
5866 rtx from
= fix
->insn
;
5867 rtx selected
= from
;
5869 HOST_WIDE_INT selected_address
;
5871 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
5872 rtx label
= gen_label_rtx ();
5874 selected_cost
= arm_barrier_cost (from
);
5875 selected_address
= fix
->address
;
5877 while (from
&& count
< max_count
)
5882 /* This code shouldn't have been called if there was a natural barrier
5884 if (GET_CODE (from
) == BARRIER
)
5887 /* Count the length of this insn. */
5888 count
+= get_attr_length (from
);
5890 /* If there is a jump table, add its length. */
5891 tmp
= is_jump_table (from
);
5894 count
+= get_jump_table_size (tmp
);
5896 /* Jump tables aren't in a basic block, so base the cost on
5897 the dispatch insn. If we select this location, we will
5898 still put the pool after the table. */
5899 new_cost
= arm_barrier_cost (from
);
5901 if (count
< max_count
&& new_cost
<= selected_cost
)
5904 selected_cost
= new_cost
;
5905 selected_address
= fix
->address
+ count
;
5908 /* Continue after the dispatch table. */
5909 from
= NEXT_INSN (tmp
);
5913 new_cost
= arm_barrier_cost (from
);
5915 if (count
< max_count
&& new_cost
<= selected_cost
)
5918 selected_cost
= new_cost
;
5919 selected_address
= fix
->address
+ count
;
5922 from
= NEXT_INSN (from
);
5925 /* Create a new JUMP_INSN that branches around a barrier. */
5926 from
= emit_jump_insn_after (gen_jump (label
), selected
);
5927 JUMP_LABEL (from
) = label
;
5928 barrier
= emit_barrier_after (from
);
5929 emit_label_after (label
, barrier
);
5931 /* Create a minipool barrier entry for the new barrier. */
5932 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
5933 new_fix
->insn
= barrier
;
5934 new_fix
->address
= selected_address
;
5935 new_fix
->next
= fix
->next
;
5936 fix
->next
= new_fix
;
5941 /* Record that there is a natural barrier in the insn stream at
5944 push_minipool_barrier (insn
, address
)
5946 HOST_WIDE_INT address
;
5948 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
5951 fix
->address
= address
;
5954 if (minipool_fix_head
!= NULL
)
5955 minipool_fix_tail
->next
= fix
;
5957 minipool_fix_head
= fix
;
5959 minipool_fix_tail
= fix
;
5962 /* Record INSN, which will need fixing up to load a value from the
5963 minipool. ADDRESS is the offset of the insn since the start of the
5964 function; LOC is a pointer to the part of the insn which requires
5965 fixing; VALUE is the constant that must be loaded, which is of type
5968 push_minipool_fix (insn
, address
, loc
, mode
, value
)
5970 HOST_WIDE_INT address
;
5972 enum machine_mode mode
;
5975 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
5977 #ifdef AOF_ASSEMBLER
5978 /* PIC symbol refereneces need to be converted into offsets into the
5980 /* XXX This shouldn't be done here. */
5981 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
5982 value
= aof_pic_entry (value
);
5983 #endif /* AOF_ASSEMBLER */
5986 fix
->address
= address
;
5989 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
5991 fix
->forwards
= get_attr_pool_range (insn
);
5992 fix
->backwards
= get_attr_neg_pool_range (insn
);
5993 fix
->minipool
= NULL
;
5995 /* If an insn doesn't have a range defined for it, then it isn't
5996 expecting to be reworked by this code. Better to abort now than
5997 to generate duff assembly code. */
5998 if (fix
->forwards
== 0 && fix
->backwards
== 0)
6003 fprintf (rtl_dump_file
,
6004 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6005 GET_MODE_NAME (mode
),
6006 INSN_UID (insn
), (unsigned long) address
,
6007 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
6008 arm_print_value (rtl_dump_file
, fix
->value
);
6009 fprintf (rtl_dump_file
, "\n");
6012 /* Add it to the chain of fixes. */
6015 if (minipool_fix_head
!= NULL
)
6016 minipool_fix_tail
->next
= fix
;
6018 minipool_fix_head
= fix
;
6020 minipool_fix_tail
= fix
;
6023 /* Scan INSN and note any of its operands that need fixing. */
6026 note_invalid_constants (insn
, address
)
6028 HOST_WIDE_INT address
;
6032 extract_insn (insn
);
6034 if (!constrain_operands (1))
6035 fatal_insn_not_found (insn
);
6037 /* Fill in recog_op_alt with information about the constraints of this
6039 preprocess_constraints ();
6041 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
6043 /* Things we need to fix can only occur in inputs. */
6044 if (recog_data
.operand_type
[opno
] != OP_IN
)
6047 /* If this alternative is a memory reference, then any mention
6048 of constants in this alternative is really to fool reload
6049 into allowing us to accept one there. We need to fix them up
6050 now so that we output the right code. */
6051 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
6053 rtx op
= recog_data
.operand
[opno
];
6055 if (CONSTANT_P (op
))
6056 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6057 recog_data
.operand_mode
[opno
], op
);
6059 /* RWE: Now we look correctly at the operands for the insn,
6060 this shouldn't be needed any more. */
6061 #ifndef AOF_ASSEMBLER
6062 /* XXX Is this still needed? */
6063 else if (GET_CODE (op
) == UNSPEC
&& XINT (op
, 1) == UNSPEC_PIC_SYM
)
6064 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6065 recog_data
.operand_mode
[opno
],
6066 XVECEXP (op
, 0, 0));
6069 else if (GET_CODE (op
) == MEM
6070 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
6071 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
6072 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6073 recog_data
.operand_mode
[opno
],
6074 get_pool_constant (XEXP (op
, 0)));
6084 HOST_WIDE_INT address
= 0;
6087 minipool_fix_head
= minipool_fix_tail
= NULL
;
6089 /* The first insn must always be a note, or the code below won't
6090 scan it properly. */
6091 if (GET_CODE (first
) != NOTE
)
6094 /* Scan all the insns and record the operands that will need fixing. */
6095 for (insn
= next_nonnote_insn (first
); insn
; insn
= next_nonnote_insn (insn
))
6097 if (GET_CODE (insn
) == BARRIER
)
6098 push_minipool_barrier (insn
, address
);
6099 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
6100 || GET_CODE (insn
) == JUMP_INSN
)
6104 note_invalid_constants (insn
, address
);
6105 address
+= get_attr_length (insn
);
6107 /* If the insn is a vector jump, add the size of the table
6108 and skip the table. */
6109 if ((table
= is_jump_table (insn
)) != NULL
)
6111 address
+= get_jump_table_size (table
);
6117 fix
= minipool_fix_head
;
6119 /* Now scan the fixups and perform the required changes. */
6124 Mfix
* last_added_fix
;
6125 Mfix
* last_barrier
= NULL
;
6128 /* Skip any further barriers before the next fix. */
6129 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
6132 /* No more fixes. */
6136 last_added_fix
= NULL
;
6138 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
6140 if (GET_CODE (ftmp
->insn
) == BARRIER
)
6142 if (ftmp
->address
>= minipool_vector_head
->max_address
)
6145 last_barrier
= ftmp
;
6147 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
6150 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
6153 /* If we found a barrier, drop back to that; any fixes that we
6154 could have reached but come after the barrier will now go in
6155 the next mini-pool. */
6156 if (last_barrier
!= NULL
)
6158 /* Reduce the refcount for those fixes that won't go into this
6160 for (fdel
= last_barrier
->next
;
6161 fdel
&& fdel
!= ftmp
;
6164 fdel
->minipool
->refcount
--;
6165 fdel
->minipool
= NULL
;
6168 ftmp
= last_barrier
;
6172 /* ftmp is first fix that we can't fit into this pool and
6173 there no natural barriers that we could use. Insert a
6174 new barrier in the code somewhere between the previous
6175 fix and this one, and arrange to jump around it. */
6176 HOST_WIDE_INT max_address
;
6178 /* The last item on the list of fixes must be a barrier, so
6179 we can never run off the end of the list of fixes without
6180 last_barrier being set. */
6184 max_address
= minipool_vector_head
->max_address
;
6185 /* Check that there isn't another fix that is in range that
6186 we couldn't fit into this pool because the pool was
6187 already too large: we need to put the pool before such an
6189 if (ftmp
->address
< max_address
)
6190 max_address
= ftmp
->address
;
6192 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
6195 assign_minipool_offsets (last_barrier
);
6199 if (GET_CODE (ftmp
->insn
) != BARRIER
6200 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
6207 /* Scan over the fixes we have identified for this pool, fixing them
6208 up and adding the constants to the pool itself. */
6209 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
6210 this_fix
= this_fix
->next
)
6211 if (GET_CODE (this_fix
->insn
) != BARRIER
)
6214 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
6215 minipool_vector_label
),
6216 this_fix
->minipool
->offset
);
6217 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
6220 dump_minipool (last_barrier
->insn
);
6224 /* From now on we must synthesize any constants that we can't handle
6225 directly. This can happen if the RTL gets split during final
6226 instruction generation. */
6227 after_arm_reorg
= 1;
6229 /* Free the minipool memory. */
6230 obstack_free (&minipool_obstack
, minipool_startobj
);
6233 /* Routines to output assembly language. */
6235 /* If the rtx is the correct value then return the string of the number.
6236 In this way we can ensure that valid double constants are generated even
6237 when cross compiling. */
6240 fp_immediate_constant (x
)
6246 if (!fpa_consts_inited
)
6249 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
6250 for (i
= 0; i
< 8; i
++)
6251 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
6252 return strings_fpa
[i
];
6257 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
6260 fp_const_from_val (r
)
6261 REAL_VALUE_TYPE
* r
;
6265 if (!fpa_consts_inited
)
6268 for (i
= 0; i
< 8; i
++)
6269 if (REAL_VALUES_EQUAL (*r
, values_fpa
[i
]))
6270 return strings_fpa
[i
];
6275 /* Output the operands of a LDM/STM instruction to STREAM.
6276 MASK is the ARM register set mask of which only bits 0-15 are important.
6277 REG is the base register, either the frame pointer or the stack pointer,
6278 INSTR is the possibly suffixed load or store instruction. */
6281 print_multi_reg (stream
, instr
, reg
, mask
)
6288 int not_first
= FALSE
;
6290 fputc ('\t', stream
);
6291 asm_fprintf (stream
, instr
, reg
);
6292 fputs (", {", stream
);
6294 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
6295 if (mask
& (1 << i
))
6298 fprintf (stream
, ", ");
6300 asm_fprintf (stream
, "%r", i
);
6304 fprintf (stream
, "}%s\n", TARGET_APCS_32
? "" : "^");
6307 /* Output a 'call' insn. */
6310 output_call (operands
)
6313 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
6315 if (REGNO (operands
[0]) == LR_REGNUM
)
6317 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
6318 output_asm_insn ("mov%?\t%0, %|lr", operands
);
6321 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6323 if (TARGET_INTERWORK
)
6324 output_asm_insn ("bx%?\t%0", operands
);
6326 output_asm_insn ("mov%?\t%|pc, %0", operands
);
6335 int something_changed
= 0;
6337 int code
= GET_CODE (x0
);
6344 if (REGNO (x0
) == LR_REGNUM
)
6346 *x
= gen_rtx_REG (SImode
, IP_REGNUM
);
6351 /* Scan through the sub-elements and change any references there. */
6352 fmt
= GET_RTX_FORMAT (code
);
6354 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6356 something_changed
|= eliminate_lr2ip (&XEXP (x0
, i
));
6357 else if (fmt
[i
] == 'E')
6358 for (j
= 0; j
< XVECLEN (x0
, i
); j
++)
6359 something_changed
|= eliminate_lr2ip (&XVECEXP (x0
, i
, j
));
6361 return something_changed
;
6365 /* Output a 'call' insn that is a reference in memory. */
6368 output_call_mem (operands
)
6371 operands
[0] = copy_rtx (operands
[0]); /* Be ultra careful. */
6372 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
6373 if (eliminate_lr2ip (&operands
[0]))
6374 output_asm_insn ("mov%?\t%|ip, %|lr", operands
);
6376 if (TARGET_INTERWORK
)
6378 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
6379 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6380 output_asm_insn ("bx%?\t%|ip", operands
);
6384 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6385 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
6392 /* Output a move from arm registers to an fpu registers.
6393 OPERANDS[0] is an fpu register.
6394 OPERANDS[1] is the first registers of an arm register pair. */
6397 output_mov_long_double_fpu_from_arm (operands
)
6400 int arm_reg0
= REGNO (operands
[1]);
6403 if (arm_reg0
== IP_REGNUM
)
6406 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6407 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6408 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
6410 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
6411 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
6416 /* Output a move from an fpu register to arm registers.
6417 OPERANDS[0] is the first registers of an arm register pair.
6418 OPERANDS[1] is an fpu register. */
6421 output_mov_long_double_arm_from_fpu (operands
)
6424 int arm_reg0
= REGNO (operands
[0]);
6427 if (arm_reg0
== IP_REGNUM
)
6430 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6431 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6432 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
6434 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
6435 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
6439 /* Output a move from arm registers to arm registers of a long double
6440 OPERANDS[0] is the destination.
6441 OPERANDS[1] is the source. */
6444 output_mov_long_double_arm_from_arm (operands
)
6447 /* We have to be careful here because the two might overlap. */
6448 int dest_start
= REGNO (operands
[0]);
6449 int src_start
= REGNO (operands
[1]);
6453 if (dest_start
< src_start
)
6455 for (i
= 0; i
< 3; i
++)
6457 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
6458 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
6459 output_asm_insn ("mov%?\t%0, %1", ops
);
6464 for (i
= 2; i
>= 0; i
--)
6466 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
6467 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
6468 output_asm_insn ("mov%?\t%0, %1", ops
);
6476 /* Output a move from arm registers to an fpu registers.
6477 OPERANDS[0] is an fpu register.
6478 OPERANDS[1] is the first registers of an arm register pair. */
6481 output_mov_double_fpu_from_arm (operands
)
6484 int arm_reg0
= REGNO (operands
[1]);
6487 if (arm_reg0
== IP_REGNUM
)
6490 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6491 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6492 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
6493 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
6497 /* Output a move from an fpu register to arm registers.
6498 OPERANDS[0] is the first registers of an arm register pair.
6499 OPERANDS[1] is an fpu register. */
6502 output_mov_double_arm_from_fpu (operands
)
6505 int arm_reg0
= REGNO (operands
[0]);
6508 if (arm_reg0
== IP_REGNUM
)
6511 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6512 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6513 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
6514 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
6518 /* Output a move between double words.
6519 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
6520 or MEM<-REG and all MEMs must be offsettable addresses. */
6523 output_move_double (operands
)
6526 enum rtx_code code0
= GET_CODE (operands
[0]);
6527 enum rtx_code code1
= GET_CODE (operands
[1]);
6532 int reg0
= REGNO (operands
[0]);
6534 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
6538 int reg1
= REGNO (operands
[1]);
6539 if (reg1
== IP_REGNUM
)
6542 /* Ensure the second source is not overwritten. */
6543 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
6544 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
6546 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
6548 else if (code1
== CONST_DOUBLE
)
6550 if (GET_MODE (operands
[1]) == DFmode
)
6555 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
6556 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
6557 otherops
[1] = GEN_INT (l
[1]);
6558 operands
[1] = GEN_INT (l
[0]);
6560 else if (GET_MODE (operands
[1]) != VOIDmode
)
6562 else if (WORDS_BIG_ENDIAN
)
6564 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
6565 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
6569 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
6570 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
6573 output_mov_immediate (operands
);
6574 output_mov_immediate (otherops
);
6576 else if (code1
== CONST_INT
)
6578 #if HOST_BITS_PER_WIDE_INT > 32
6579 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
6580 what the upper word is. */
6581 if (WORDS_BIG_ENDIAN
)
6583 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
6584 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
6588 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
6589 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
6592 /* Sign extend the intval into the high-order word. */
6593 if (WORDS_BIG_ENDIAN
)
6595 otherops
[1] = operands
[1];
6596 operands
[1] = (INTVAL (operands
[1]) < 0
6597 ? constm1_rtx
: const0_rtx
);
6600 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
6602 output_mov_immediate (otherops
);
6603 output_mov_immediate (operands
);
6605 else if (code1
== MEM
)
6607 switch (GET_CODE (XEXP (operands
[1], 0)))
6610 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
6614 abort (); /* Should never happen now. */
6618 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
6622 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
6626 abort (); /* Should never happen now. */
6631 output_asm_insn ("adr%?\t%0, %1", operands
);
6632 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
6636 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
6637 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
6639 otherops
[0] = operands
[0];
6640 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
6641 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
6643 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
6645 if (GET_CODE (otherops
[2]) == CONST_INT
)
6647 switch (INTVAL (otherops
[2]))
6650 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
6653 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
6656 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
6660 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
6661 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
6663 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
6666 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
6669 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
6671 return "ldm%?ia\t%0, %M0";
6675 otherops
[1] = adjust_address (operands
[1], VOIDmode
, 4);
6676 /* Take care of overlapping base/data reg. */
6677 if (reg_mentioned_p (operands
[0], operands
[1]))
6679 output_asm_insn ("ldr%?\t%0, %1", otherops
);
6680 output_asm_insn ("ldr%?\t%0, %1", operands
);
6684 output_asm_insn ("ldr%?\t%0, %1", operands
);
6685 output_asm_insn ("ldr%?\t%0, %1", otherops
);
6691 abort (); /* Constraints should prevent this. */
6693 else if (code0
== MEM
&& code1
== REG
)
6695 if (REGNO (operands
[1]) == IP_REGNUM
)
6698 switch (GET_CODE (XEXP (operands
[0], 0)))
6701 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
6705 abort (); /* Should never happen now. */
6709 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
6713 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
6717 abort (); /* Should never happen now. */
6721 if (GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == CONST_INT
)
6723 switch (INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
6726 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
6730 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
6734 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
6741 otherops
[0] = adjust_address (operands
[0], VOIDmode
, 4);
6742 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
6743 output_asm_insn ("str%?\t%1, %0", operands
);
6744 output_asm_insn ("str%?\t%1, %0", otherops
);
6748 /* Constraints should prevent this. */
6755 /* Output an arbitrary MOV reg, #n.
6756 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6759 output_mov_immediate (operands
)
6762 HOST_WIDE_INT n
= INTVAL (operands
[1]);
6764 /* Try to use one MOV. */
6765 if (const_ok_for_arm (n
))
6766 output_asm_insn ("mov%?\t%0, %1", operands
);
6768 /* Try to use one MVN. */
6769 else if (const_ok_for_arm (~n
))
6771 operands
[1] = GEN_INT (~n
);
6772 output_asm_insn ("mvn%?\t%0, %1", operands
);
6779 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6780 for (i
= 0; i
< 32; i
++)
6784 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
6785 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n
);
6787 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
6793 /* Output an ADD r, s, #n where n may be too big for one instruction.
6794 If adding zero to one register, output nothing. */
6797 output_add_immediate (operands
)
6800 HOST_WIDE_INT n
= INTVAL (operands
[2]);
6802 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
6805 output_multi_immediate (operands
,
6806 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
6809 output_multi_immediate (operands
,
6810 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
6817 /* Output a multiple immediate operation.
6818 OPERANDS is the vector of operands referred to in the output patterns.
6819 INSTR1 is the output pattern to use for the first constant.
6820 INSTR2 is the output pattern to use for subsequent constants.
6821 IMMED_OP is the index of the constant slot in OPERANDS.
6822 N is the constant value. */
6825 output_multi_immediate (operands
, instr1
, instr2
, immed_op
, n
)
6827 const char * instr1
;
6828 const char * instr2
;
6832 #if HOST_BITS_PER_WIDE_INT > 32
6838 /* Quick and easy output. */
6839 operands
[immed_op
] = const0_rtx
;
6840 output_asm_insn (instr1
, operands
);
6845 const char * instr
= instr1
;
6847 /* Note that n is never zero here (which would give no output). */
6848 for (i
= 0; i
< 32; i
+= 2)
6852 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
6853 output_asm_insn (instr
, operands
);
6863 /* Return the appropriate ARM instruction for the operation code.
6864 The returned result should not be overwritten. OP is the rtx of the
6865 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6869 arithmetic_instr (op
, shift_first_arg
)
6871 int shift_first_arg
;
6873 switch (GET_CODE (op
))
6879 return shift_first_arg
? "rsb" : "sub";
6895 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6896 for the operation code. The returned result should not be overwritten.
6897 OP is the rtx code of the shift.
6898 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6902 shift_op (op
, amountp
)
6904 HOST_WIDE_INT
*amountp
;
6907 enum rtx_code code
= GET_CODE (op
);
6909 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
6911 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6912 *amountp
= INTVAL (XEXP (op
, 1));
6935 /* We never have to worry about the amount being other than a
6936 power of 2, since this case can never be reloaded from a reg. */
6938 *amountp
= int_log2 (*amountp
);
6949 /* This is not 100% correct, but follows from the desire to merge
6950 multiplication by a power of 2 with the recognizer for a
6951 shift. >=32 is not a valid shift for "asl", so we must try and
6952 output a shift that produces the correct arithmetical result.
6953 Using lsr #32 is identical except for the fact that the carry bit
6954 is not set correctly if we set the flags; but we never use the
6955 carry bit from such an operation, so we can ignore that. */
6956 if (code
== ROTATERT
)
6957 /* Rotate is just modulo 32. */
6959 else if (*amountp
!= (*amountp
& 31))
6966 /* Shifts of 0 are no-ops. */
6974 /* Obtain the shift from the POWER of two. */
6976 static HOST_WIDE_INT
6978 HOST_WIDE_INT power
;
6980 HOST_WIDE_INT shift
= 0;
6982 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
6992 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
6993 /bin/as is horribly restrictive. */
6994 #define MAX_ASCII_LEN 51
6997 output_ascii_pseudo_op (stream
, p
, len
)
6999 const unsigned char * p
;
7005 fputs ("\t.ascii\t\"", stream
);
7007 for (i
= 0; i
< len
; i
++)
7011 if (len_so_far
>= MAX_ASCII_LEN
)
7013 fputs ("\"\n\t.ascii\t\"", stream
);
7020 fputs ("\\t", stream
);
7025 fputs ("\\f", stream
);
7030 fputs ("\\b", stream
);
7035 fputs ("\\r", stream
);
7039 case TARGET_NEWLINE
:
7040 fputs ("\\n", stream
);
7042 if ((c
>= ' ' && c
<= '~')
7044 /* This is a good place for a line break. */
7045 len_so_far
= MAX_ASCII_LEN
;
7052 putc ('\\', stream
);
7057 if (c
>= ' ' && c
<= '~')
7064 fprintf (stream
, "\\%03o", c
);
7071 fputs ("\"\n", stream
);
7074 /* Compute the register sabe mask for registers 0 through 12
7075 inclusive. This code is used by both arm_compute_save_reg_mask
7076 and arm_compute_initial_elimination_offset. */
7078 static unsigned long
7079 arm_compute_save_reg0_reg12_mask ()
7081 unsigned long func_type
= arm_current_func_type ();
7082 unsigned int save_reg_mask
= 0;
7085 if (IS_INTERRUPT (func_type
))
7087 unsigned int max_reg
;
7088 /* Interrupt functions must not corrupt any registers,
7089 even call clobbered ones. If this is a leaf function
7090 we can just examine the registers used by the RTL, but
7091 otherwise we have to assume that whatever function is
7092 called might clobber anything, and so we have to save
7093 all the call-clobbered registers as well. */
7094 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
7095 /* FIQ handlers have registers r8 - r12 banked, so
7096 we only need to check r0 - r7, Normal ISRs only
7097 bank r14 and r15, so we must check up to r12.
7098 r13 is the stack pointer which is always preserved,
7099 so we do not need to consider it here. */
7104 for (reg
= 0; reg
<= max_reg
; reg
++)
7105 if (regs_ever_live
[reg
]
7106 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
7107 save_reg_mask
|= (1 << reg
);
7111 /* In the normal case we only need to save those registers
7112 which are call saved and which are used by this function. */
7113 for (reg
= 0; reg
<= 10; reg
++)
7114 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
7115 save_reg_mask
|= (1 << reg
);
7117 /* Handle the frame pointer as a special case. */
7118 if (! TARGET_APCS_FRAME
7119 && ! frame_pointer_needed
7120 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
7121 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
7122 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
7124 /* If we aren't loading the PIC register,
7125 don't stack it even though it may be live. */
7127 && ! TARGET_SINGLE_PIC_BASE
7128 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
7129 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
7132 return save_reg_mask
;
7135 /* Compute a bit mask of which registers need to be
7136 saved on the stack for the current function. */
7138 static unsigned long
7139 arm_compute_save_reg_mask ()
7141 unsigned int save_reg_mask
= 0;
7142 unsigned long func_type
= arm_current_func_type ();
7144 if (IS_NAKED (func_type
))
7145 /* This should never really happen. */
7148 /* If we are creating a stack frame, then we must save the frame pointer,
7149 IP (which will hold the old stack pointer), LR and the PC. */
7150 if (frame_pointer_needed
)
7152 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
7157 /* Volatile functions do not return, so there
7158 is no need to save any other registers. */
7159 if (IS_VOLATILE (func_type
))
7160 return save_reg_mask
;
7162 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
7164 /* Decide if we need to save the link register.
7165 Interrupt routines have their own banked link register,
7166 so they never need to save it.
7167 Otherwise if we do not use the link register we do not need to save
7168 it. If we are pushing other registers onto the stack however, we
7169 can save an instruction in the epilogue by pushing the link register
7170 now and then popping it back into the PC. This incurs extra memory
7171 accesses though, so we only do it when optimising for size, and only
7172 if we know that we will not need a fancy return sequence. */
7173 if (regs_ever_live
[LR_REGNUM
]
7176 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
))
7177 save_reg_mask
|= 1 << LR_REGNUM
;
7179 if (cfun
->machine
->lr_save_eliminated
)
7180 save_reg_mask
&= ~ (1 << LR_REGNUM
);
7182 return save_reg_mask
;
7185 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
7186 everything bar the final return instruction. */
7189 output_return_instruction (operand
, really_return
, reverse
)
7194 char conditional
[10];
7197 unsigned long live_regs_mask
;
7198 unsigned long func_type
;
7200 func_type
= arm_current_func_type ();
7202 if (IS_NAKED (func_type
))
7205 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
7207 /* If this function was declared non-returning, and we have found a tail
7208 call, then we have to trust that the called function won't return. */
7213 /* Otherwise, trap an attempted return by aborting. */
7215 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
7217 assemble_external_libcall (ops
[1]);
7218 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
7224 if (current_function_calls_alloca
&& !really_return
)
7227 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
7229 return_used_this_function
= 1;
7231 live_regs_mask
= arm_compute_save_reg_mask ();
7235 const char * return_reg
;
7237 /* If we do not have any special requirements for function exit
7238 (eg interworking, or ISR) then we can load the return address
7239 directly into the PC. Otherwise we must load it into LR. */
7241 && ! TARGET_INTERWORK
)
7242 return_reg
= reg_names
[PC_REGNUM
];
7244 return_reg
= reg_names
[LR_REGNUM
];
7246 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
7247 /* There are two possible reasons for the IP register being saved.
7248 Either a stack frame was created, in which case IP contains the
7249 old stack pointer, or an ISR routine corrupted it. If this in an
7250 ISR routine then just restore IP, otherwise restore IP into SP. */
7251 if (! IS_INTERRUPT (func_type
))
7253 live_regs_mask
&= ~ (1 << IP_REGNUM
);
7254 live_regs_mask
|= (1 << SP_REGNUM
);
7257 /* On some ARM architectures it is faster to use LDR rather than
7258 LDM to load a single register. On other architectures, the
7259 cost is the same. In 26 bit mode, or for exception handlers,
7260 we have to use LDM to load the PC so that the CPSR is also
7262 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
7264 if (live_regs_mask
== (unsigned int)(1 << reg
))
7267 if (reg
<= LAST_ARM_REGNUM
7268 && (reg
!= LR_REGNUM
7270 || (TARGET_APCS_32
&& ! IS_INTERRUPT (func_type
))))
7272 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
7273 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
7280 /* Generate the load multiple instruction to restore the registers. */
7281 if (frame_pointer_needed
)
7282 sprintf (instr
, "ldm%sea\t%%|fp, {", conditional
);
7284 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
7286 p
= instr
+ strlen (instr
);
7288 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
7289 if (live_regs_mask
& (1 << reg
))
7291 int l
= strlen (reg_names
[reg
]);
7297 memcpy (p
, ", ", 2);
7301 memcpy (p
, "%|", 2);
7302 memcpy (p
+ 2, reg_names
[reg
], l
);
7306 if (live_regs_mask
& (1 << LR_REGNUM
))
7308 int l
= strlen (return_reg
);
7312 memcpy (p
, ", ", 2);
7316 memcpy (p
, "%|", 2);
7317 memcpy (p
+ 2, return_reg
, l
);
7318 strcpy (p
+ 2 + l
, ((TARGET_APCS_32
7319 && !IS_INTERRUPT (func_type
))
7327 output_asm_insn (instr
, & operand
);
7329 /* See if we need to generate an extra instruction to
7330 perform the actual function return. */
7332 && func_type
!= ARM_FT_INTERWORKED
7333 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
7335 /* The return has already been handled
7336 by loading the LR into the PC. */
7343 switch ((int) ARM_FUNC_TYPE (func_type
))
7347 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
7350 case ARM_FT_INTERWORKED
:
7351 sprintf (instr
, "bx%s\t%%|lr", conditional
);
7354 case ARM_FT_EXCEPTION
:
7355 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
7359 /* ARMv5 implementations always provide BX, so interworking
7360 is the default unless APCS-26 is in use. */
7361 if ((insn_flags
& FL_ARCH5
) != 0 && TARGET_APCS_32
)
7362 sprintf (instr
, "bx%s\t%%|lr", conditional
);
7364 sprintf (instr
, "mov%s%s\t%%|pc, %%|lr",
7365 conditional
, TARGET_APCS_32
? "" : "s");
7369 output_asm_insn (instr
, & operand
);
7375 /* Write the function name into the code section, directly preceding
7376 the function prologue.
7378 Code will be output similar to this:
7380 .ascii "arm_poke_function_name", 0
7383 .word 0xff000000 + (t1 - t0)
7384 arm_poke_function_name
7386 stmfd sp!, {fp, ip, lr, pc}
7389 When performing a stack backtrace, code can inspect the value
7390 of 'pc' stored at 'fp' + 0. If the trace function then looks
7391 at location pc - 12 and the top 8 bits are set, then we know
7392 that there is a function name embedded immediately preceding this
7393 location and has length ((pc[-3]) & 0xff000000).
7395 We assume that pc is declared as a pointer to an unsigned long.
7397 It is of no benefit to output the function name if we are assembling
7398 a leaf function. These function types will not contain a stack
7399 backtrace structure, therefore it is not possible to determine the
7403 arm_poke_function_name (stream
, name
)
7407 unsigned long alignlength
;
7408 unsigned long length
;
7411 length
= strlen (name
) + 1;
7412 alignlength
= ROUND_UP (length
);
7414 ASM_OUTPUT_ASCII (stream
, name
, length
);
7415 ASM_OUTPUT_ALIGN (stream
, 2);
7416 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
7417 assemble_aligned_integer (UNITS_PER_WORD
, x
);
7420 /* Place some comments into the assembler stream
7421 describing the current function. */
7424 arm_output_function_prologue (f
, frame_size
)
7426 HOST_WIDE_INT frame_size
;
7428 unsigned long func_type
;
7432 thumb_output_function_prologue (f
, frame_size
);
7437 if (arm_ccfsm_state
|| arm_target_insn
)
7440 func_type
= arm_current_func_type ();
7442 switch ((int) ARM_FUNC_TYPE (func_type
))
7447 case ARM_FT_INTERWORKED
:
7448 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
7450 case ARM_FT_EXCEPTION_HANDLER
:
7451 asm_fprintf (f
, "\t%@ C++ Exception Handler.\n");
7454 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
7457 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
7459 case ARM_FT_EXCEPTION
:
7460 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
7464 if (IS_NAKED (func_type
))
7465 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
7467 if (IS_VOLATILE (func_type
))
7468 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
7470 if (IS_NESTED (func_type
))
7471 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
7473 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %d\n",
7474 current_function_args_size
,
7475 current_function_pretend_args_size
, frame_size
);
7477 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
7478 frame_pointer_needed
,
7479 cfun
->machine
->uses_anonymous_args
);
7481 if (cfun
->machine
->lr_save_eliminated
)
7482 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
7484 #ifdef AOF_ASSEMBLER
7486 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
7489 return_used_this_function
= 0;
7493 arm_output_epilogue (really_return
)
7497 unsigned long saved_regs_mask
;
7498 unsigned long func_type
;
7499 /* Floats_offset is the offset from the "virtual" frame. In an APCS
7500 frame that is $fp + 4 for a non-variadic function. */
7501 int floats_offset
= 0;
7503 int frame_size
= get_frame_size ();
7504 FILE * f
= asm_out_file
;
7505 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
7507 /* If we have already generated the return instruction
7508 then it is futile to generate anything else. */
7509 if (use_return_insn (FALSE
) && return_used_this_function
)
7512 func_type
= arm_current_func_type ();
7514 if (IS_NAKED (func_type
))
7515 /* Naked functions don't have epilogues. */
7518 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
7522 /* A volatile function should never return. Call abort. */
7523 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
7524 assemble_external_libcall (op
);
7525 output_asm_insn ("bl\t%a0", &op
);
7530 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
7532 /* If we are throwing an exception, then we really must
7533 be doing a return, so we can't tail-call. */
7536 saved_regs_mask
= arm_compute_save_reg_mask ();
7538 /* XXX We should adjust floats_offset for any anonymous args, and then
7539 re-adjust vfp_offset below to compensate. */
7541 /* Compute how far away the floats will be. */
7542 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
7543 if (saved_regs_mask
& (1 << reg
))
7546 if (frame_pointer_needed
)
7550 if (arm_fpu_arch
== FP_SOFT2
)
7552 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
7553 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7555 floats_offset
+= 12;
7556 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
7557 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
7562 int start_reg
= LAST_ARM_FP_REGNUM
;
7564 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
7566 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7568 floats_offset
+= 12;
7570 /* We can't unstack more than four registers at once. */
7571 if (start_reg
- reg
== 3)
7573 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
7574 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
7575 start_reg
= reg
- 1;
7580 if (reg
!= start_reg
)
7581 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
7582 reg
+ 1, start_reg
- reg
,
7583 FP_REGNUM
, floats_offset
- vfp_offset
);
7584 start_reg
= reg
- 1;
7588 /* Just in case the last register checked also needs unstacking. */
7589 if (reg
!= start_reg
)
7590 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
7591 reg
+ 1, start_reg
- reg
,
7592 FP_REGNUM
, floats_offset
- vfp_offset
);
7595 /* saved_regs_mask should contain the IP, which at the time of stack
7596 frame generation actually contains the old stack pointer. So a
7597 quick way to unwind the stack is just pop the IP register directly
7598 into the stack pointer. */
7599 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
7601 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
7602 saved_regs_mask
|= (1 << SP_REGNUM
);
7604 /* There are two registers left in saved_regs_mask - LR and PC. We
7605 only need to restore the LR register (the return address), but to
7606 save time we can load it directly into the PC, unless we need a
7607 special function exit sequence, or we are not really returning. */
7608 if (really_return
&& ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
7609 /* Delete the LR from the register mask, so that the LR on
7610 the stack is loaded into the PC in the register mask. */
7611 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
7613 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
7615 print_multi_reg (f
, "ldmea\t%r", FP_REGNUM
, saved_regs_mask
);
7617 if (IS_INTERRUPT (func_type
))
7618 /* Interrupt handlers will have pushed the
7619 IP onto the stack, so restore it now. */
7620 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, 1 << IP_REGNUM
);
7624 /* Restore stack pointer if necessary. */
7625 if (frame_size
+ current_function_outgoing_args_size
!= 0)
7627 operands
[0] = operands
[1] = stack_pointer_rtx
;
7628 operands
[2] = GEN_INT (frame_size
7629 + current_function_outgoing_args_size
);
7630 output_add_immediate (operands
);
7633 if (arm_fpu_arch
== FP_SOFT2
)
7635 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
7636 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7637 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
7642 int start_reg
= FIRST_ARM_FP_REGNUM
;
7644 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
7646 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7648 if (reg
- start_reg
== 3)
7650 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
7651 start_reg
, SP_REGNUM
);
7652 start_reg
= reg
+ 1;
7657 if (reg
!= start_reg
)
7658 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
7659 start_reg
, reg
- start_reg
,
7662 start_reg
= reg
+ 1;
7666 /* Just in case the last register checked also needs unstacking. */
7667 if (reg
!= start_reg
)
7668 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
7669 start_reg
, reg
- start_reg
, SP_REGNUM
);
7672 /* If we can, restore the LR into the PC. */
7673 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
7675 && current_function_pretend_args_size
== 0
7676 && saved_regs_mask
& (1 << LR_REGNUM
))
7678 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
7679 saved_regs_mask
|= (1 << PC_REGNUM
);
7682 /* Load the registers off the stack. If we only have one register
7683 to load use the LDR instruction - it is faster. */
7684 if (saved_regs_mask
== (1 << LR_REGNUM
))
7686 /* The exception handler ignores the LR, so we do
7687 not really need to load it off the stack. */
7689 asm_fprintf (f
, "\tadd\t%r, %r, #4\n", SP_REGNUM
, SP_REGNUM
);
7691 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
7693 else if (saved_regs_mask
)
7694 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
7696 if (current_function_pretend_args_size
)
7698 /* Unwind the pre-pushed regs. */
7699 operands
[0] = operands
[1] = stack_pointer_rtx
;
7700 operands
[2] = GEN_INT (current_function_pretend_args_size
);
7701 output_add_immediate (operands
);
7706 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
)
7707 /* Adjust the stack to remove the exception handler stuff. */
7708 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
7713 || (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
7714 && current_function_pretend_args_size
== 0
7715 && saved_regs_mask
& (1 << PC_REGNUM
)))
7718 /* Generate the return instruction. */
7719 switch ((int) ARM_FUNC_TYPE (func_type
))
7721 case ARM_FT_EXCEPTION_HANDLER
:
7722 /* Even in 26-bit mode we do a mov (rather than a movs)
7723 because we don't have the PSR bits set in the address. */
7724 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, EXCEPTION_LR_REGNUM
);
7729 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
7732 case ARM_FT_EXCEPTION
:
7733 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7736 case ARM_FT_INTERWORKED
:
7737 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
7741 if (frame_pointer_needed
)
7742 /* If we used the frame pointer then the return adddress
7743 will have been loaded off the stack directly into the
7744 PC, so there is no need to issue a MOV instruction
7747 else if (current_function_pretend_args_size
== 0
7748 && (saved_regs_mask
& (1 << LR_REGNUM
)))
7749 /* Similarly we may have been able to load LR into the PC
7750 even if we did not create a stack frame. */
7752 else if (TARGET_APCS_32
)
7753 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7755 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7763 arm_output_function_epilogue (file
, frame_size
)
7764 FILE *file ATTRIBUTE_UNUSED
;
7765 HOST_WIDE_INT frame_size
;
7769 /* ??? Probably not safe to set this here, since it assumes that a
7770 function will be emitted as assembly immediately after we generate
7771 RTL for it. This does not happen for inline functions. */
7772 return_used_this_function
= 0;
7776 if (use_return_insn (FALSE
)
7777 && return_used_this_function
7778 && (frame_size
+ current_function_outgoing_args_size
) != 0
7779 && !frame_pointer_needed
)
7782 /* Reset the ARM-specific per-function variables. */
7783 after_arm_reorg
= 0;
7787 /* Generate and emit an insn that we will recognize as a push_multi.
7788 Unfortunately, since this insn does not reflect very well the actual
7789 semantics of the operation, we need to annotate the insn for the benefit
7790 of DWARF2 frame unwind information. */
7793 emit_multi_reg_push (mask
)
7801 int dwarf_par_index
;
7804 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7805 if (mask
& (1 << i
))
7808 if (num_regs
== 0 || num_regs
> 16)
7811 /* We don't record the PC in the dwarf frame information. */
7812 num_dwarf_regs
= num_regs
;
7813 if (mask
& (1 << PC_REGNUM
))
7816 /* For the body of the insn we are going to generate an UNSPEC in
7817 parallel with several USEs. This allows the insn to be recognised
7818 by the push_multi pattern in the arm.md file. The insn looks
7819 something like this:
7822 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
7823 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
7824 (use (reg:SI 11 fp))
7825 (use (reg:SI 12 ip))
7826 (use (reg:SI 14 lr))
7827 (use (reg:SI 15 pc))
7830 For the frame note however, we try to be more explicit and actually
7831 show each register being stored into the stack frame, plus a (single)
7832 decrement of the stack pointer. We do it this way in order to be
7833 friendly to the stack unwinding code, which only wants to see a single
7834 stack decrement per instruction. The RTL we generate for the note looks
7835 something like this:
7838 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
7839 (set (mem:SI (reg:SI sp)) (reg:SI r4))
7840 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
7841 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
7842 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
7845 This sequence is used both by the code to support stack unwinding for
7846 exceptions handlers and the code to generate dwarf2 frame debugging. */
7848 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
7849 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
7850 dwarf_par_index
= 1;
7852 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7854 if (mask
& (1 << i
))
7856 reg
= gen_rtx_REG (SImode
, i
);
7859 = gen_rtx_SET (VOIDmode
,
7860 gen_rtx_MEM (BLKmode
,
7861 gen_rtx_PRE_DEC (BLKmode
,
7862 stack_pointer_rtx
)),
7863 gen_rtx_UNSPEC (BLKmode
,
7869 tmp
= gen_rtx_SET (VOIDmode
,
7870 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
7872 RTX_FRAME_RELATED_P (tmp
) = 1;
7873 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
7881 for (j
= 1, i
++; j
< num_regs
; i
++)
7883 if (mask
& (1 << i
))
7885 reg
= gen_rtx_REG (SImode
, i
);
7887 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
7891 tmp
= gen_rtx_SET (VOIDmode
,
7892 gen_rtx_MEM (SImode
,
7893 plus_constant (stack_pointer_rtx
,
7896 RTX_FRAME_RELATED_P (tmp
) = 1;
7897 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
7904 par
= emit_insn (par
);
7906 tmp
= gen_rtx_SET (SImode
,
7908 gen_rtx_PLUS (SImode
,
7910 GEN_INT (-4 * num_regs
)));
7911 RTX_FRAME_RELATED_P (tmp
) = 1;
7912 XVECEXP (dwarf
, 0, 0) = tmp
;
7914 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
7920 emit_sfm (base_reg
, count
)
7929 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
7930 dwarf
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
7931 RTX_FRAME_RELATED_P (dwarf
) = 1;
7933 reg
= gen_rtx_REG (XFmode
, base_reg
++);
7936 = gen_rtx_SET (VOIDmode
,
7937 gen_rtx_MEM (BLKmode
,
7938 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
7939 gen_rtx_UNSPEC (BLKmode
,
7943 = gen_rtx_SET (VOIDmode
,
7944 gen_rtx_MEM (XFmode
,
7945 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
7947 RTX_FRAME_RELATED_P (tmp
) = 1;
7948 XVECEXP (dwarf
, 0, count
- 1) = tmp
;
7950 for (i
= 1; i
< count
; i
++)
7952 reg
= gen_rtx_REG (XFmode
, base_reg
++);
7953 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
7955 tmp
= gen_rtx_SET (VOIDmode
,
7956 gen_rtx_MEM (XFmode
,
7957 gen_rtx_PRE_DEC (BLKmode
,
7958 stack_pointer_rtx
)),
7960 RTX_FRAME_RELATED_P (tmp
) = 1;
7961 XVECEXP (dwarf
, 0, count
- i
- 1) = tmp
;
7964 par
= emit_insn (par
);
7965 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
7970 /* Compute the distance from register FROM to register TO.
7971 These can be the arg pointer (26), the soft frame pointer (25),
7972 the stack pointer (13) or the hard frame pointer (11).
7973 Typical stack layout looks like this:
7975 old stack pointer -> | |
7978 | | saved arguments for
7979 | | vararg functions
7982 hard FP & arg pointer -> | | \
7990 soft frame pointer -> | | /
8000 current stack pointer -> | | /
8003 For a given funciton some or all of these stack compomnents
8004 may not be needed, giving rise to the possibility of
8005 eliminating some of the registers.
8007 The values returned by this function must reflect the behaviour
8008 of arm_expand_prologue() and arm_compute_save_reg_mask().
8010 The sign of the number returned reflects the direction of stack
8011 growth, so the values are positive for all eliminations except
8012 from the soft frame pointer to the hard frame pointer. */
8015 arm_compute_initial_elimination_offset (from
, to
)
8019 unsigned int local_vars
= (get_frame_size () + 3) & ~3;
8020 unsigned int outgoing_args
= current_function_outgoing_args_size
;
8021 unsigned int stack_frame
;
8022 unsigned int call_saved_registers
;
8023 unsigned long func_type
;
8025 func_type
= arm_current_func_type ();
8027 /* Volatile functions never return, so there is
8028 no need to save call saved registers. */
8029 call_saved_registers
= 0;
8030 if (! IS_VOLATILE (func_type
))
8032 unsigned int reg_mask
;
8035 /* Make sure that we compute which registers will be saved
8036 on the stack using the same algorithm that is used by
8037 arm_compute_save_reg_mask(). */
8038 reg_mask
= arm_compute_save_reg0_reg12_mask ();
8040 /* Now count the number of bits set in save_reg_mask.
8041 For each set bit we need 4 bytes of stack space. */
8044 call_saved_registers
+= 4;
8045 reg_mask
= reg_mask
& ~ (reg_mask
& - reg_mask
);
8048 if (regs_ever_live
[LR_REGNUM
]
8049 /* If a stack frame is going to be created, the LR will
8050 be saved as part of that, so we do not need to allow
8052 && ! frame_pointer_needed
)
8053 call_saved_registers
+= 4;
8055 /* If the hard floating point registers are going to be
8056 used then they must be saved on the stack as well.
8057 Each register occupies 12 bytes of stack space. */
8058 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8059 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8060 call_saved_registers
+= 12;
8063 /* The stack frame contains 4 registers - the old frame pointer,
8064 the old stack pointer, the return address and PC of the start
8066 stack_frame
= frame_pointer_needed
? 16 : 0;
8068 /* OK, now we have enough information to compute the distances.
8069 There must be an entry in these switch tables for each pair
8070 of registers in ELIMINABLE_REGS, even if some of the entries
8071 seem to be redundant or useless. */
8074 case ARG_POINTER_REGNUM
:
8077 case THUMB_HARD_FRAME_POINTER_REGNUM
:
8080 case FRAME_POINTER_REGNUM
:
8081 /* This is the reverse of the soft frame pointer
8082 to hard frame pointer elimination below. */
8083 if (call_saved_registers
== 0 && stack_frame
== 0)
8085 return (call_saved_registers
+ stack_frame
- 4);
8087 case ARM_HARD_FRAME_POINTER_REGNUM
:
8088 /* If there is no stack frame then the hard
8089 frame pointer and the arg pointer coincide. */
8090 if (stack_frame
== 0 && call_saved_registers
!= 0)
8092 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
8093 return (frame_pointer_needed
8094 && current_function_needs_context
8095 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
8097 case STACK_POINTER_REGNUM
:
8098 /* If nothing has been pushed on the stack at all
8099 then this will return -4. This *is* correct! */
8100 return call_saved_registers
+ stack_frame
+ local_vars
+ outgoing_args
- 4;
8107 case FRAME_POINTER_REGNUM
:
8110 case THUMB_HARD_FRAME_POINTER_REGNUM
:
8113 case ARM_HARD_FRAME_POINTER_REGNUM
:
8114 /* The hard frame pointer points to the top entry in the
8115 stack frame. The soft frame pointer to the bottom entry
8116 in the stack frame. If there is no stack frame at all,
8117 then they are identical. */
8118 if (call_saved_registers
== 0 && stack_frame
== 0)
8120 return - (call_saved_registers
+ stack_frame
- 4);
8122 case STACK_POINTER_REGNUM
:
8123 return local_vars
+ outgoing_args
;
8131 /* You cannot eliminate from the stack pointer.
8132 In theory you could eliminate from the hard frame
8133 pointer to the stack pointer, but this will never
8134 happen, since if a stack frame is not needed the
8135 hard frame pointer will never be used. */
8140 /* Generate the prologue instructions for entry into an ARM function. */
8143 arm_expand_prologue ()
8149 unsigned long live_regs_mask
;
8150 unsigned long func_type
;
8152 int saved_pretend_args
= 0;
8153 unsigned int args_to_push
;
8155 func_type
= arm_current_func_type ();
8157 /* Naked functions don't have prologues. */
8158 if (IS_NAKED (func_type
))
8161 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
8162 args_to_push
= current_function_pretend_args_size
;
8164 /* Compute which register we will have to save onto the stack. */
8165 live_regs_mask
= arm_compute_save_reg_mask ();
8167 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
8169 if (frame_pointer_needed
)
8171 if (IS_INTERRUPT (func_type
))
8173 /* Interrupt functions must not corrupt any registers.
8174 Creating a frame pointer however, corrupts the IP
8175 register, so we must push it first. */
8176 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
8178 /* Do not set RTX_FRAME_RELATED_P on this insn.
8179 The dwarf stack unwinding code only wants to see one
8180 stack decrement per function, and this is not it. If
8181 this instruction is labeled as being part of the frame
8182 creation sequence then dwarf2out_frame_debug_expr will
8183 abort when it encounters the assignment of IP to FP
8184 later on, since the use of SP here establishes SP as
8185 the CFA register and not IP.
8187 Anyway this instruction is not really part of the stack
8188 frame creation although it is part of the prologue. */
8190 else if (IS_NESTED (func_type
))
8192 /* The Static chain register is the same as the IP register
8193 used as a scratch register during stack frame creation.
8194 To get around this need to find somewhere to store IP
8195 whilst the frame is being created. We try the following
8198 1. The last argument register.
8199 2. A slot on the stack above the frame. (This only
8200 works if the function is not a varargs function).
8201 3. Register r3, after pushing the argument registers
8204 Note - we only need to tell the dwarf2 backend about the SP
8205 adjustment in the second variant; the static chain register
8206 doesn't need to be unwound, as it doesn't contain a value
8207 inherited from the caller. */
8209 if (regs_ever_live
[3] == 0)
8211 insn
= gen_rtx_REG (SImode
, 3);
8212 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
8213 insn
= emit_insn (insn
);
8215 else if (args_to_push
== 0)
8218 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
8219 insn
= gen_rtx_MEM (SImode
, insn
);
8220 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
8221 insn
= emit_insn (insn
);
8225 /* Just tell the dwarf backend that we adjusted SP. */
8226 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8227 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8228 GEN_INT (-fp_offset
)));
8229 RTX_FRAME_RELATED_P (insn
) = 1;
8230 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8231 dwarf
, REG_NOTES (insn
));
8235 /* Store the args on the stack. */
8236 if (cfun
->machine
->uses_anonymous_args
)
8237 insn
= emit_multi_reg_push
8238 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
8241 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8242 GEN_INT (- args_to_push
)));
8244 RTX_FRAME_RELATED_P (insn
) = 1;
8246 saved_pretend_args
= 1;
8247 fp_offset
= args_to_push
;
8250 /* Now reuse r3 to preserve IP. */
8251 insn
= gen_rtx_REG (SImode
, 3);
8252 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
8253 (void) emit_insn (insn
);
8259 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
8260 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
8263 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
8265 insn
= emit_insn (insn
);
8266 RTX_FRAME_RELATED_P (insn
) = 1;
8271 /* Push the argument registers, or reserve space for them. */
8272 if (cfun
->machine
->uses_anonymous_args
)
8273 insn
= emit_multi_reg_push
8274 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
8277 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8278 GEN_INT (- args_to_push
)));
8279 RTX_FRAME_RELATED_P (insn
) = 1;
8282 /* If this is an interrupt service routine, and the link register is
8283 going to be pushed, subtracting four now will mean that the
8284 function return can be done with a single instruction. */
8285 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
8286 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
8288 emit_insn (gen_rtx_SET (SImode
,
8289 gen_rtx_REG (SImode
, LR_REGNUM
),
8290 gen_rtx_PLUS (SImode
,
8291 gen_rtx_REG (SImode
, LR_REGNUM
),
8297 insn
= emit_multi_reg_push (live_regs_mask
);
8298 RTX_FRAME_RELATED_P (insn
) = 1;
8301 if (! IS_VOLATILE (func_type
))
8303 /* Save any floating point call-saved registers used by this function. */
8304 if (arm_fpu_arch
== FP_SOFT2
)
8306 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8307 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8309 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
8310 insn
= gen_rtx_MEM (XFmode
, insn
);
8311 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
8312 gen_rtx_REG (XFmode
, reg
)));
8313 RTX_FRAME_RELATED_P (insn
) = 1;
8318 int start_reg
= LAST_ARM_FP_REGNUM
;
8320 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8322 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8324 if (start_reg
- reg
== 3)
8326 insn
= emit_sfm (reg
, 4);
8327 RTX_FRAME_RELATED_P (insn
) = 1;
8328 start_reg
= reg
- 1;
8333 if (start_reg
!= reg
)
8335 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
8336 RTX_FRAME_RELATED_P (insn
) = 1;
8338 start_reg
= reg
- 1;
8342 if (start_reg
!= reg
)
8344 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
8345 RTX_FRAME_RELATED_P (insn
) = 1;
8350 if (frame_pointer_needed
)
8352 /* Create the new frame pointer. */
8353 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
8354 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
8355 RTX_FRAME_RELATED_P (insn
) = 1;
8357 if (IS_NESTED (func_type
))
8359 /* Recover the static chain register. */
8360 if (regs_ever_live
[3] == 0
8361 || saved_pretend_args
)
8362 insn
= gen_rtx_REG (SImode
, 3);
8363 else /* if (current_function_pretend_args_size == 0) */
8365 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
, GEN_INT (4));
8366 insn
= gen_rtx_MEM (SImode
, insn
);
8369 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
8370 /* Add a USE to stop propagate_one_insn() from barfing. */
8371 emit_insn (gen_prologue_use (ip_rtx
));
8375 amount
= GEN_INT (-(get_frame_size ()
8376 + current_function_outgoing_args_size
));
8378 if (amount
!= const0_rtx
)
8380 /* This add can produce multiple insns for a large constant, so we
8381 need to get tricky. */
8382 rtx last
= get_last_insn ();
8383 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8387 last
= last
? NEXT_INSN (last
) : get_insns ();
8388 RTX_FRAME_RELATED_P (last
) = 1;
8390 while (last
!= insn
);
8392 /* If the frame pointer is needed, emit a special barrier that
8393 will prevent the scheduler from moving stores to the frame
8394 before the stack adjustment. */
8395 if (frame_pointer_needed
)
8397 rtx unspec
= gen_rtx_UNSPEC (SImode
,
8398 gen_rtvec (2, stack_pointer_rtx
,
8399 hard_frame_pointer_rtx
),
8402 insn
= emit_insn (gen_rtx_CLOBBER (VOIDmode
,
8403 gen_rtx_MEM (BLKmode
, unspec
)));
8407 /* If we are profiling, make sure no instructions are scheduled before
8408 the call to mcount. Similarly if the user has requested no
8409 scheduling in the prolog. */
8410 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
8411 emit_insn (gen_blockage ());
8413 /* If the link register is being kept alive, with the return address in it,
8414 then make sure that it does not get reused by the ce2 pass. */
8415 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
8417 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
8418 cfun
->machine
->lr_save_eliminated
= 1;
8422 /* If CODE is 'd', then the X is a condition operand and the instruction
8423 should only be executed if the condition is true.
8424 if CODE is 'D', then the X is a condition operand and the instruction
8425 should only be executed if the condition is false: however, if the mode
8426 of the comparison is CCFPEmode, then always execute the instruction -- we
8427 do this because in these circumstances !GE does not necessarily imply LT;
8428 in these cases the instruction pattern will take care to make sure that
8429 an instruction containing %d will follow, thereby undoing the effects of
8430 doing this instruction unconditionally.
8431 If CODE is 'N' then X is a floating point operand that must be negated
8433 If CODE is 'B' then output a bitwise inverted value of X (a const int).
8434 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
8437 arm_print_operand (stream
, x
, code
)
8445 fputs (ASM_COMMENT_START
, stream
);
8449 fputs (user_label_prefix
, stream
);
8453 fputs (REGISTER_PREFIX
, stream
);
8457 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
8459 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
8462 fputs (arm_condition_codes
[arm_current_cc
], stream
);
8464 else if (current_insn_predicate
)
8466 enum arm_cond_code code
;
8471 code
= get_arm_condition_code (current_insn_predicate
);
8472 fputs (arm_condition_codes
[code
], stream
);
8479 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8480 r
= REAL_VALUE_NEGATE (r
);
8481 fprintf (stream
, "%s", fp_const_from_val (&r
));
8486 if (GET_CODE (x
) == CONST_INT
)
8489 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
8490 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
8495 output_addr_const (stream
, x
);
8500 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
8504 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
8510 const char * shift
= shift_op (x
, &val
);
8514 fprintf (stream
, ", %s ", shift_op (x
, &val
));
8516 arm_print_operand (stream
, XEXP (x
, 1), 0);
8519 fputc ('#', stream
);
8520 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
8526 /* An explanation of the 'Q', 'R' and 'H' register operands:
8528 In a pair of registers containing a DI or DF value the 'Q'
8529 operand returns the register number of the register containing
8530 the least signficant part of the value. The 'R' operand returns
8531 the register number of the register containing the most
8532 significant part of the value.
8534 The 'H' operand returns the higher of the two register numbers.
8535 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
8536 same as the 'Q' operand, since the most signficant part of the
8537 value is held in the lower number register. The reverse is true
8538 on systems where WORDS_BIG_ENDIAN is false.
8540 The purpose of these operands is to distinguish between cases
8541 where the endian-ness of the values is important (for example
8542 when they are added together), and cases where the endian-ness
8543 is irrelevant, but the order of register operations is important.
8544 For example when loading a value from memory into a register
8545 pair, the endian-ness does not matter. Provided that the value
8546 from the lower memory address is put into the lower numbered
8547 register, and the value from the higher address is put into the
8548 higher numbered register, the load will work regardless of whether
8549 the value being loaded is big-wordian or little-wordian. The
8550 order of the two register loads can matter however, if the address
8551 of the memory location is actually held in one of the registers
8552 being overwritten by the load. */
8554 if (REGNO (x
) > LAST_ARM_REGNUM
)
8556 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
8560 if (REGNO (x
) > LAST_ARM_REGNUM
)
8562 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
8566 if (REGNO (x
) > LAST_ARM_REGNUM
)
8568 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
8572 asm_fprintf (stream
, "%r",
8573 GET_CODE (XEXP (x
, 0)) == REG
8574 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
8578 asm_fprintf (stream
, "{%r-%r}",
8580 REGNO (x
) + NUM_REGS (GET_MODE (x
)) - 1);
8584 /* CONST_TRUE_RTX means always -- that's the default. */
8585 if (x
== const_true_rtx
)
8589 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
8592 fputs (thumb_condition_code (x
, 0), stream
);
8596 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
8598 if (x
== const_true_rtx
)
8602 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
8603 (get_arm_condition_code (x
))],
8606 fputs (thumb_condition_code (x
, 1), stream
);
8613 if (GET_CODE (x
) == REG
)
8614 asm_fprintf (stream
, "%r", REGNO (x
));
8615 else if (GET_CODE (x
) == MEM
)
8617 output_memory_reference_mode
= GET_MODE (x
);
8618 output_address (XEXP (x
, 0));
8620 else if (GET_CODE (x
) == CONST_DOUBLE
)
8621 fprintf (stream
, "#%s", fp_immediate_constant (x
));
8622 else if (GET_CODE (x
) == NEG
)
8623 abort (); /* This should never happen now. */
8626 fputc ('#', stream
);
8627 output_addr_const (stream
, x
);
8632 #ifndef AOF_ASSEMBLER
8633 /* Target hook for assembling integer objects. The ARM version needs to
8634 handle word-sized values specially. */
8637 arm_assemble_integer (x
, size
, aligned_p
)
8642 if (size
== UNITS_PER_WORD
&& aligned_p
)
8644 fputs ("\t.word\t", asm_out_file
);
8645 output_addr_const (asm_out_file
, x
);
8647 /* Mark symbols as position independent. We only do this in the
8648 .text segment, not in the .data segment. */
8649 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
8650 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
8652 if (GET_CODE (x
) == SYMBOL_REF
8653 && (CONSTANT_POOL_ADDRESS_P (x
)
8654 || ENCODED_SHORT_CALL_ATTR_P (XSTR (x
, 0))))
8655 fputs ("(GOTOFF)", asm_out_file
);
8656 else if (GET_CODE (x
) == LABEL_REF
)
8657 fputs ("(GOTOFF)", asm_out_file
);
8659 fputs ("(GOT)", asm_out_file
);
8661 fputc ('\n', asm_out_file
);
8665 return default_assemble_integer (x
, size
, aligned_p
);
8669 /* A finite state machine takes care of noticing whether or not instructions
8670 can be conditionally executed, and thus decrease execution time and code
8671 size by deleting branch instructions. The fsm is controlled by
8672 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
8674 /* The state of the fsm controlling condition codes are:
8675 0: normal, do nothing special
8676 1: make ASM_OUTPUT_OPCODE not output this instruction
8677 2: make ASM_OUTPUT_OPCODE not output this instruction
8678 3: make instructions conditional
8679 4: make instructions conditional
8681 State transitions (state->state by whom under condition):
8682 0 -> 1 final_prescan_insn if the `target' is a label
8683 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
8684 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
8685 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
8686 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
8687 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
8688 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
8689 (the target insn is arm_target_insn).
8691 If the jump clobbers the conditions then we use states 2 and 4.
8693 A similar thing can be done with conditional return insns.
8695 XXX In case the `target' is an unconditional branch, this conditionalising
8696 of the instructions always reduces code size, but not always execution
8697 time. But then, I want to reduce the code size to somewhere near what
8698 /bin/cc produces. */
8700 /* Returns the index of the ARM condition code string in
8701 `arm_condition_codes'. COMPARISON should be an rtx like
8702 `(eq (...) (...))'. */
8704 static enum arm_cond_code
8705 get_arm_condition_code (comparison
)
8708 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
8710 enum rtx_code comp_code
= GET_CODE (comparison
);
8712 if (GET_MODE_CLASS (mode
) != MODE_CC
)
8713 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
8714 XEXP (comparison
, 1));
8718 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
8719 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
8720 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
8721 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
8722 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
8723 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
8724 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
8725 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
8726 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
8727 case CC_DLTUmode
: code
= ARM_CC
;
8730 if (comp_code
!= EQ
&& comp_code
!= NE
)
8733 if (comp_code
== EQ
)
8734 return ARM_INVERSE_CONDITION_CODE (code
);
8740 case NE
: return ARM_NE
;
8741 case EQ
: return ARM_EQ
;
8742 case GE
: return ARM_PL
;
8743 case LT
: return ARM_MI
;
8750 case NE
: return ARM_NE
;
8751 case EQ
: return ARM_EQ
;
8757 /* These encodings assume that AC=1 in the FPA system control
8758 byte. This allows us to handle all cases except UNEQ and
8762 case GE
: return ARM_GE
;
8763 case GT
: return ARM_GT
;
8764 case LE
: return ARM_LS
;
8765 case LT
: return ARM_MI
;
8766 case NE
: return ARM_NE
;
8767 case EQ
: return ARM_EQ
;
8768 case ORDERED
: return ARM_VC
;
8769 case UNORDERED
: return ARM_VS
;
8770 case UNLT
: return ARM_LT
;
8771 case UNLE
: return ARM_LE
;
8772 case UNGT
: return ARM_HI
;
8773 case UNGE
: return ARM_PL
;
8774 /* UNEQ and LTGT do not have a representation. */
8775 case UNEQ
: /* Fall through. */
8776 case LTGT
: /* Fall through. */
8783 case NE
: return ARM_NE
;
8784 case EQ
: return ARM_EQ
;
8785 case GE
: return ARM_LE
;
8786 case GT
: return ARM_LT
;
8787 case LE
: return ARM_GE
;
8788 case LT
: return ARM_GT
;
8789 case GEU
: return ARM_LS
;
8790 case GTU
: return ARM_CC
;
8791 case LEU
: return ARM_CS
;
8792 case LTU
: return ARM_HI
;
8799 case LTU
: return ARM_CS
;
8800 case GEU
: return ARM_CC
;
8807 case NE
: return ARM_NE
;
8808 case EQ
: return ARM_EQ
;
8809 case GE
: return ARM_GE
;
8810 case GT
: return ARM_GT
;
8811 case LE
: return ARM_LE
;
8812 case LT
: return ARM_LT
;
8813 case GEU
: return ARM_CS
;
8814 case GTU
: return ARM_HI
;
8815 case LEU
: return ARM_LS
;
8816 case LTU
: return ARM_CC
;
8828 arm_final_prescan_insn (insn
)
8831 /* BODY will hold the body of INSN. */
8832 rtx body
= PATTERN (insn
);
8834 /* This will be 1 if trying to repeat the trick, and things need to be
8835 reversed if it appears to fail. */
8838 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
8839 taken are clobbered, even if the rtl suggests otherwise. It also
8840 means that we have to grub around within the jump expression to find
8841 out what the conditions are when the jump isn't taken. */
8842 int jump_clobbers
= 0;
8844 /* If we start with a return insn, we only succeed if we find another one. */
8845 int seeking_return
= 0;
8847 /* START_INSN will hold the insn from where we start looking. This is the
8848 first insn after the following code_label if REVERSE is true. */
8849 rtx start_insn
= insn
;
8851 /* If in state 4, check if the target branch is reached, in order to
8852 change back to state 0. */
8853 if (arm_ccfsm_state
== 4)
8855 if (insn
== arm_target_insn
)
8857 arm_target_insn
= NULL
;
8858 arm_ccfsm_state
= 0;
8863 /* If in state 3, it is possible to repeat the trick, if this insn is an
8864 unconditional branch to a label, and immediately following this branch
8865 is the previous target label which is only used once, and the label this
8866 branch jumps to is not too far off. */
8867 if (arm_ccfsm_state
== 3)
8869 if (simplejump_p (insn
))
8871 start_insn
= next_nonnote_insn (start_insn
);
8872 if (GET_CODE (start_insn
) == BARRIER
)
8874 /* XXX Isn't this always a barrier? */
8875 start_insn
= next_nonnote_insn (start_insn
);
8877 if (GET_CODE (start_insn
) == CODE_LABEL
8878 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
8879 && LABEL_NUSES (start_insn
) == 1)
8884 else if (GET_CODE (body
) == RETURN
)
8886 start_insn
= next_nonnote_insn (start_insn
);
8887 if (GET_CODE (start_insn
) == BARRIER
)
8888 start_insn
= next_nonnote_insn (start_insn
);
8889 if (GET_CODE (start_insn
) == CODE_LABEL
8890 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
8891 && LABEL_NUSES (start_insn
) == 1)
8903 if (arm_ccfsm_state
!= 0 && !reverse
)
8905 if (GET_CODE (insn
) != JUMP_INSN
)
8908 /* This jump might be paralleled with a clobber of the condition codes
8909 the jump should always come first */
8910 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
8911 body
= XVECEXP (body
, 0, 0);
8914 /* If this is a conditional return then we don't want to know */
8915 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
8916 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
8917 && (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
8918 || GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
))
8923 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
8924 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
8927 int fail
= FALSE
, succeed
= FALSE
;
8928 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
8929 int then_not_else
= TRUE
;
8930 rtx this_insn
= start_insn
, label
= 0;
8932 /* If the jump cannot be done with one instruction, we cannot
8933 conditionally execute the instruction in the inverse case. */
8934 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
8940 /* Register the insn jumped to. */
8943 if (!seeking_return
)
8944 label
= XEXP (SET_SRC (body
), 0);
8946 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
8947 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
8948 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
8950 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
8951 then_not_else
= FALSE
;
8953 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
8955 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
8958 then_not_else
= FALSE
;
8963 /* See how many insns this branch skips, and what kind of insns. If all
8964 insns are okay, and the label or unconditional branch to the same
8965 label is not too far away, succeed. */
8966 for (insns_skipped
= 0;
8967 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
8971 this_insn
= next_nonnote_insn (this_insn
);
8975 switch (GET_CODE (this_insn
))
8978 /* Succeed if it is the target label, otherwise fail since
8979 control falls in from somewhere else. */
8980 if (this_insn
== label
)
8984 arm_ccfsm_state
= 2;
8985 this_insn
= next_nonnote_insn (this_insn
);
8988 arm_ccfsm_state
= 1;
8996 /* Succeed if the following insn is the target label.
8998 If return insns are used then the last insn in a function
8999 will be a barrier. */
9000 this_insn
= next_nonnote_insn (this_insn
);
9001 if (this_insn
&& this_insn
== label
)
9005 arm_ccfsm_state
= 2;
9006 this_insn
= next_nonnote_insn (this_insn
);
9009 arm_ccfsm_state
= 1;
9017 /* If using 32-bit addresses the cc is not preserved over
9021 /* Succeed if the following insn is the target label,
9022 or if the following two insns are a barrier and
9023 the target label. */
9024 this_insn
= next_nonnote_insn (this_insn
);
9025 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
9026 this_insn
= next_nonnote_insn (this_insn
);
9028 if (this_insn
&& this_insn
== label
9029 && insns_skipped
< max_insns_skipped
)
9033 arm_ccfsm_state
= 2;
9034 this_insn
= next_nonnote_insn (this_insn
);
9037 arm_ccfsm_state
= 1;
9046 /* If this is an unconditional branch to the same label, succeed.
9047 If it is to another label, do nothing. If it is conditional,
9049 /* XXX Probably, the tests for SET and the PC are unnecessary. */
9051 scanbody
= PATTERN (this_insn
);
9052 if (GET_CODE (scanbody
) == SET
9053 && GET_CODE (SET_DEST (scanbody
)) == PC
)
9055 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
9056 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
9058 arm_ccfsm_state
= 2;
9061 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
9064 /* Fail if a conditional return is undesirable (eg on a
9065 StrongARM), but still allow this if optimizing for size. */
9066 else if (GET_CODE (scanbody
) == RETURN
9067 && !use_return_insn (TRUE
)
9070 else if (GET_CODE (scanbody
) == RETURN
9073 arm_ccfsm_state
= 2;
9076 else if (GET_CODE (scanbody
) == PARALLEL
)
9078 switch (get_attr_conds (this_insn
))
9088 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
9093 /* Instructions using or affecting the condition codes make it
9095 scanbody
= PATTERN (this_insn
);
9096 if (!(GET_CODE (scanbody
) == SET
9097 || GET_CODE (scanbody
) == PARALLEL
)
9098 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
9108 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
9109 arm_target_label
= CODE_LABEL_NUMBER (label
);
9110 else if (seeking_return
|| arm_ccfsm_state
== 2)
9112 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
9114 this_insn
= next_nonnote_insn (this_insn
);
9115 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
9116 || GET_CODE (this_insn
) == CODE_LABEL
))
9121 /* Oh, dear! we ran off the end.. give up */
9122 recog (PATTERN (insn
), insn
, NULL
);
9123 arm_ccfsm_state
= 0;
9124 arm_target_insn
= NULL
;
9127 arm_target_insn
= this_insn
;
9136 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
9138 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
9139 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
9140 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
9141 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
9145 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
9148 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
9152 if (reverse
|| then_not_else
)
9153 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
9156 /* Restore recog_data (getting the attributes of other insns can
9157 destroy this array, but final.c assumes that it remains intact
9158 across this call; since the insn has been recognized already we
9159 call recog direct). */
9160 recog (PATTERN (insn
), insn
, NULL
);
9164 /* Returns true if REGNO is a valid register
9165 for holding a quantity of tyoe MODE. */
9168 arm_hard_regno_mode_ok (regno
, mode
)
9170 enum machine_mode mode
;
9172 if (GET_MODE_CLASS (mode
) == MODE_CC
)
9173 return regno
== CC_REGNUM
;
9176 /* For the Thumb we only allow values bigger than SImode in
9177 registers 0 - 6, so that there is always a second low
9178 register available to hold the upper part of the value.
9179 We probably we ought to ensure that the register is the
9180 start of an even numbered register pair. */
9181 return (NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
9183 if (regno
<= LAST_ARM_REGNUM
)
9184 /* We allow any value to be stored in the general regisetrs. */
9187 if ( regno
== FRAME_POINTER_REGNUM
9188 || regno
== ARG_POINTER_REGNUM
)
9189 /* We only allow integers in the fake hard registers. */
9190 return GET_MODE_CLASS (mode
) == MODE_INT
;
9192 /* The only registers left are the FPU registers
9193 which we only allow to hold FP values. */
9194 return GET_MODE_CLASS (mode
) == MODE_FLOAT
9195 && regno
>= FIRST_ARM_FP_REGNUM
9196 && regno
<= LAST_ARM_FP_REGNUM
;
9200 arm_regno_class (regno
)
9205 if (regno
== STACK_POINTER_REGNUM
)
9207 if (regno
== CC_REGNUM
)
9214 if ( regno
<= LAST_ARM_REGNUM
9215 || regno
== FRAME_POINTER_REGNUM
9216 || regno
== ARG_POINTER_REGNUM
)
9217 return GENERAL_REGS
;
9219 if (regno
== CC_REGNUM
)
9225 /* Handle a special case when computing the offset
9226 of an argument from the frame pointer. */
9229 arm_debugger_arg_offset (value
, addr
)
9235 /* We are only interested if dbxout_parms() failed to compute the offset. */
9239 /* We can only cope with the case where the address is held in a register. */
9240 if (GET_CODE (addr
) != REG
)
9243 /* If we are using the frame pointer to point at the argument, then
9244 an offset of 0 is correct. */
9245 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
9248 /* If we are using the stack pointer to point at the
9249 argument, then an offset of 0 is correct. */
9250 if ((TARGET_THUMB
|| !frame_pointer_needed
)
9251 && REGNO (addr
) == SP_REGNUM
)
9254 /* Oh dear. The argument is pointed to by a register rather
9255 than being held in a register, or being stored at a known
9256 offset from the frame pointer. Since GDB only understands
9257 those two kinds of argument we must translate the address
9258 held in the register into an offset from the frame pointer.
9259 We do this by searching through the insns for the function
9260 looking to see where this register gets its value. If the
9261 register is initialised from the frame pointer plus an offset
9262 then we are in luck and we can continue, otherwise we give up.
9264 This code is exercised by producing debugging information
9265 for a function with arguments like this:
9267 double func (double a, double b, int c, double d) {return d;}
9269 Without this code the stab for parameter 'd' will be set to
9270 an offset of 0 from the frame pointer, rather than 8. */
9272 /* The if() statement says:
9274 If the insn is a normal instruction
9275 and if the insn is setting the value in a register
9276 and if the register being set is the register holding the address of the argument
9277 and if the address is computing by an addition
9278 that involves adding to a register
9279 which is the frame pointer
9284 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9286 if ( GET_CODE (insn
) == INSN
9287 && GET_CODE (PATTERN (insn
)) == SET
9288 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
9289 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
9290 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
9291 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
9292 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
9295 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
9304 warning ("unable to compute real location of stacked parameter");
9305 value
= 8; /* XXX magic hack */
9311 #define def_builtin(NAME, TYPE, CODE) \
9312 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL)
9315 arm_init_builtins ()
9317 tree endlink
= void_list_node
;
9318 tree int_endlink
= tree_cons (NULL_TREE
, integer_type_node
, endlink
);
9319 tree pchar_type_node
= build_pointer_type (char_type_node
);
9321 tree int_ftype_int
, void_ftype_pchar
;
9323 /* void func (void *) */
9325 = build_function_type (void_type_node
,
9326 tree_cons (NULL_TREE
, pchar_type_node
, endlink
));
9328 /* int func (int) */
9330 = build_function_type (integer_type_node
, int_endlink
);
9332 /* Initialize arm V5 builtins. */
9334 def_builtin ("__builtin_clz", int_ftype_int
, ARM_BUILTIN_CLZ
);
9337 /* Expand an expression EXP that calls a built-in function,
9338 with result going to TARGET if that's convenient
9339 (and in mode MODE if that's convenient).
9340 SUBTARGET may be used as the target for computing one of EXP's operands.
9341 IGNORE is nonzero if the value is to be ignored. */
9344 arm_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
9347 rtx subtarget ATTRIBUTE_UNUSED
;
9348 enum machine_mode mode ATTRIBUTE_UNUSED
;
9349 int ignore ATTRIBUTE_UNUSED
;
9351 enum insn_code icode
;
9352 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
9353 tree arglist
= TREE_OPERAND (exp
, 1);
9356 enum machine_mode tmode
, mode0
;
9357 int fcode
= DECL_FUNCTION_CODE (fndecl
);
9364 case ARM_BUILTIN_CLZ
:
9365 icode
= CODE_FOR_clz
;
9366 arg0
= TREE_VALUE (arglist
);
9367 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
9368 tmode
= insn_data
[icode
].operand
[0].mode
;
9369 mode0
= insn_data
[icode
].operand
[1].mode
;
9371 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9372 op0
= copy_to_mode_reg (mode0
, op0
);
9374 || GET_MODE (target
) != tmode
9375 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9376 target
= gen_reg_rtx (tmode
);
9377 pat
= GEN_FCN (icode
) (target
, op0
);
9384 /* @@@ Should really do something sensible here. */
9388 /* Recursively search through all of the blocks in a function
9389 checking to see if any of the variables created in that
9390 function match the RTX called 'orig'. If they do then
9391 replace them with the RTX called 'new'. */
9394 replace_symbols_in_block (block
, orig
, new)
9399 for (; block
; block
= BLOCK_CHAIN (block
))
9403 if (!TREE_USED (block
))
9406 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
9408 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
9409 || DECL_IGNORED_P (sym
)
9410 || TREE_CODE (sym
) != VAR_DECL
9411 || DECL_EXTERNAL (sym
)
9412 || !rtx_equal_p (DECL_RTL (sym
), orig
)
9416 SET_DECL_RTL (sym
, new);
9419 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
9423 /* Return the number (counting from 0) of
9424 the least significant set bit in MASK. */
9430 number_of_first_bit_set (mask
)
9436 (mask
& (1 << bit
)) == 0;
9443 /* Generate code to return from a thumb function.
9444 If 'reg_containing_return_addr' is -1, then the return address is
9445 actually on the stack, at the stack pointer. */
9447 thumb_exit (f
, reg_containing_return_addr
, eh_ofs
)
9449 int reg_containing_return_addr
;
9452 unsigned regs_available_for_popping
;
9453 unsigned regs_to_pop
;
9459 int restore_a4
= FALSE
;
9461 /* Compute the registers we need to pop. */
9465 /* There is an assumption here, that if eh_ofs is not NULL, the
9466 normal return address will have been pushed. */
9467 if (reg_containing_return_addr
== -1 || eh_ofs
)
9469 /* When we are generating a return for __builtin_eh_return,
9470 reg_containing_return_addr must specify the return regno. */
9471 if (eh_ofs
&& reg_containing_return_addr
== -1)
9474 regs_to_pop
|= 1 << LR_REGNUM
;
9478 if (TARGET_BACKTRACE
)
9480 /* Restore the (ARM) frame pointer and stack pointer. */
9481 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
9485 /* If there is nothing to pop then just emit the BX instruction and
9487 if (pops_needed
== 0)
9490 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9492 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9495 /* Otherwise if we are not supporting interworking and we have not created
9496 a backtrace structure and the function was not entered in ARM mode then
9497 just pop the return address straight into the PC. */
9498 else if (!TARGET_INTERWORK
9499 && !TARGET_BACKTRACE
9500 && !is_called_in_ARM_mode (current_function_decl
))
9504 asm_fprintf (f
, "\tadd\t%r, #4\n", SP_REGNUM
);
9505 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9506 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9509 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
9514 /* Find out how many of the (return) argument registers we can corrupt. */
9515 regs_available_for_popping
= 0;
9517 /* If returning via __builtin_eh_return, the bottom three registers
9518 all contain information needed for the return. */
9524 /* If we can deduce the registers used from the function's
9525 return value. This is more reliable that examining
9526 regs_ever_live[] because that will be set if the register is
9527 ever used in the function, not just if the register is used
9528 to hold a return value. */
9530 if (current_function_return_rtx
!= 0)
9531 mode
= GET_MODE (current_function_return_rtx
);
9534 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
9536 size
= GET_MODE_SIZE (mode
);
9540 /* In a void function we can use any argument register.
9541 In a function that returns a structure on the stack
9542 we can use the second and third argument registers. */
9543 if (mode
== VOIDmode
)
9544 regs_available_for_popping
=
9545 (1 << ARG_REGISTER (1))
9546 | (1 << ARG_REGISTER (2))
9547 | (1 << ARG_REGISTER (3));
9549 regs_available_for_popping
=
9550 (1 << ARG_REGISTER (2))
9551 | (1 << ARG_REGISTER (3));
9554 regs_available_for_popping
=
9555 (1 << ARG_REGISTER (2))
9556 | (1 << ARG_REGISTER (3));
9558 regs_available_for_popping
=
9559 (1 << ARG_REGISTER (3));
9562 /* Match registers to be popped with registers into which we pop them. */
9563 for (available
= regs_available_for_popping
,
9564 required
= regs_to_pop
;
9565 required
!= 0 && available
!= 0;
9566 available
&= ~(available
& - available
),
9567 required
&= ~(required
& - required
))
9570 /* If we have any popping registers left over, remove them. */
9572 regs_available_for_popping
&= ~available
;
9574 /* Otherwise if we need another popping register we can use
9575 the fourth argument register. */
9576 else if (pops_needed
)
9578 /* If we have not found any free argument registers and
9579 reg a4 contains the return address, we must move it. */
9580 if (regs_available_for_popping
== 0
9581 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
9583 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
9584 reg_containing_return_addr
= LR_REGNUM
;
9588 /* Register a4 is being used to hold part of the return value,
9589 but we have dire need of a free, low register. */
9592 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
9595 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
9597 /* The fourth argument register is available. */
9598 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
9604 /* Pop as many registers as we can. */
9605 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9607 /* Process the registers we popped. */
9608 if (reg_containing_return_addr
== -1)
9610 /* The return address was popped into the lowest numbered register. */
9611 regs_to_pop
&= ~(1 << LR_REGNUM
);
9613 reg_containing_return_addr
=
9614 number_of_first_bit_set (regs_available_for_popping
);
9616 /* Remove this register for the mask of available registers, so that
9617 the return address will not be corrupted by futher pops. */
9618 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
9621 /* If we popped other registers then handle them here. */
9622 if (regs_available_for_popping
)
9626 /* Work out which register currently contains the frame pointer. */
9627 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
9629 /* Move it into the correct place. */
9630 asm_fprintf (f
, "\tmov\t%r, %r\n",
9631 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
9633 /* (Temporarily) remove it from the mask of popped registers. */
9634 regs_available_for_popping
&= ~(1 << frame_pointer
);
9635 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
9637 if (regs_available_for_popping
)
9641 /* We popped the stack pointer as well,
9642 find the register that contains it. */
9643 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
9645 /* Move it into the stack register. */
9646 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
9648 /* At this point we have popped all necessary registers, so
9649 do not worry about restoring regs_available_for_popping
9650 to its correct value:
9652 assert (pops_needed == 0)
9653 assert (regs_available_for_popping == (1 << frame_pointer))
9654 assert (regs_to_pop == (1 << STACK_POINTER)) */
9658 /* Since we have just move the popped value into the frame
9659 pointer, the popping register is available for reuse, and
9660 we know that we still have the stack pointer left to pop. */
9661 regs_available_for_popping
|= (1 << frame_pointer
);
9665 /* If we still have registers left on the stack, but we no longer have
9666 any registers into which we can pop them, then we must move the return
9667 address into the link register and make available the register that
9669 if (regs_available_for_popping
== 0 && pops_needed
> 0)
9671 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
9673 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
9674 reg_containing_return_addr
);
9676 reg_containing_return_addr
= LR_REGNUM
;
9679 /* If we have registers left on the stack then pop some more.
9680 We know that at most we will want to pop FP and SP. */
9681 if (pops_needed
> 0)
9686 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9688 /* We have popped either FP or SP.
9689 Move whichever one it is into the correct register. */
9690 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
9691 move_to
= number_of_first_bit_set (regs_to_pop
);
9693 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
9695 regs_to_pop
&= ~(1 << move_to
);
9700 /* If we still have not popped everything then we must have only
9701 had one register available to us and we are now popping the SP. */
9702 if (pops_needed
> 0)
9706 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9708 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
9710 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
9712 assert (regs_to_pop == (1 << STACK_POINTER))
9713 assert (pops_needed == 1)
9717 /* If necessary restore the a4 register. */
9720 if (reg_containing_return_addr
!= LR_REGNUM
)
9722 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
9723 reg_containing_return_addr
= LR_REGNUM
;
9726 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
9730 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9732 /* Return to caller. */
9733 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9736 /* Emit code to push or pop registers to or from the stack. */
9739 thumb_pushpop (f
, mask
, push
)
9745 int lo_mask
= mask
& 0xFF;
9747 if (lo_mask
== 0 && !push
&& (mask
& (1 << 15)))
9749 /* Special case. Do not generate a POP PC statement here, do it in
9751 thumb_exit (f
, -1, NULL_RTX
);
9755 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
9757 /* Look at the low registers first. */
9758 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
9762 asm_fprintf (f
, "%r", regno
);
9764 if ((lo_mask
& ~1) != 0)
9769 if (push
&& (mask
& (1 << LR_REGNUM
)))
9771 /* Catch pushing the LR. */
9775 asm_fprintf (f
, "%r", LR_REGNUM
);
9777 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
9779 /* Catch popping the PC. */
9780 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
)
9782 /* The PC is never poped directly, instead
9783 it is popped into r3 and then BX is used. */
9786 thumb_exit (f
, -1, NULL_RTX
);
9795 asm_fprintf (f
, "%r", PC_REGNUM
);
9803 thumb_final_prescan_insn (insn
)
9806 if (flag_print_asm_name
)
9807 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
9808 INSN_ADDRESSES (INSN_UID (insn
)));
9812 thumb_shiftable_const (val
)
9813 unsigned HOST_WIDE_INT val
;
9815 unsigned HOST_WIDE_INT mask
= 0xff;
9818 if (val
== 0) /* XXX */
9821 for (i
= 0; i
< 25; i
++)
9822 if ((val
& (mask
<< i
)) == val
)
9828 /* Returns non-zero if the current function contains,
9829 or might contain a far jump. */
9832 thumb_far_jump_used_p (int in_prologue
)
9836 /* This test is only important for leaf functions. */
9837 /* assert (!leaf_function_p ()); */
9839 /* If we have already decided that far jumps may be used,
9840 do not bother checking again, and always return true even if
9841 it turns out that they are not being used. Once we have made
9842 the decision that far jumps are present (and that hence the link
9843 register will be pushed onto the stack) we cannot go back on it. */
9844 if (cfun
->machine
->far_jump_used
)
9847 /* If this function is not being called from the prologue/epilogue
9848 generation code then it must be being called from the
9849 INITIAL_ELIMINATION_OFFSET macro. */
9852 /* In this case we know that we are being asked about the elimination
9853 of the arg pointer register. If that register is not being used,
9854 then there are no arguments on the stack, and we do not have to
9855 worry that a far jump might force the prologue to push the link
9856 register, changing the stack offsets. In this case we can just
9857 return false, since the presence of far jumps in the function will
9858 not affect stack offsets.
9860 If the arg pointer is live (or if it was live, but has now been
9861 eliminated and so set to dead) then we do have to test to see if
9862 the function might contain a far jump. This test can lead to some
9863 false negatives, since before reload is completed, then length of
9864 branch instructions is not known, so gcc defaults to returning their
9865 longest length, which in turn sets the far jump attribute to true.
9867 A false negative will not result in bad code being generated, but it
9868 will result in a needless push and pop of the link register. We
9869 hope that this does not occur too often. */
9870 if (regs_ever_live
[ARG_POINTER_REGNUM
])
9871 cfun
->machine
->arg_pointer_live
= 1;
9872 else if (!cfun
->machine
->arg_pointer_live
)
9876 /* Check to see if the function contains a branch
9877 insn with the far jump attribute set. */
9878 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9880 if (GET_CODE (insn
) == JUMP_INSN
9881 /* Ignore tablejump patterns. */
9882 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
9883 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
9884 && get_attr_far_jump (insn
) == FAR_JUMP_YES
9887 /* Record the fact that we have decied that
9888 the function does use far jumps. */
9889 cfun
->machine
->far_jump_used
= 1;
9897 /* Return non-zero if FUNC must be entered in ARM mode. */
9900 is_called_in_ARM_mode (func
)
9903 if (TREE_CODE (func
) != FUNCTION_DECL
)
9906 /* Ignore the problem about functions whoes address is taken. */
9907 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
9911 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
9917 /* The bits which aren't usefully expanded as rtl. */
9920 thumb_unexpanded_epilogue ()
9923 int live_regs_mask
= 0;
9924 int high_regs_pushed
= 0;
9925 int leaf_function
= leaf_function_p ();
9927 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
9929 if (return_used_this_function
)
9932 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
9933 if (regs_ever_live
[regno
] && !call_used_regs
[regno
]
9934 && !(TARGET_SINGLE_PIC_BASE
&& (regno
== arm_pic_register
)))
9935 live_regs_mask
|= 1 << regno
;
9937 for (regno
= 8; regno
< 13; regno
++)
9939 if (regs_ever_live
[regno
] && !call_used_regs
[regno
]
9940 && !(TARGET_SINGLE_PIC_BASE
&& (regno
== arm_pic_register
)))
9944 /* The prolog may have pushed some high registers to use as
9945 work registers. eg the testuite file:
9946 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
9947 compiles to produce:
9948 push {r4, r5, r6, r7, lr}
9952 as part of the prolog. We have to undo that pushing here. */
9954 if (high_regs_pushed
)
9956 int mask
= live_regs_mask
;
9962 /* If we can deduce the registers used from the function's return value.
9963 This is more reliable that examining regs_ever_live[] because that
9964 will be set if the register is ever used in the function, not just if
9965 the register is used to hold a return value. */
9967 if (current_function_return_rtx
!= 0)
9968 mode
= GET_MODE (current_function_return_rtx
);
9971 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
9973 size
= GET_MODE_SIZE (mode
);
9975 /* Unless we are returning a type of size > 12 register r3 is
9981 /* Oh dear! We have no low registers into which we can pop
9984 ("no low registers available for popping high registers");
9986 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
9987 if (regs_ever_live
[next_hi_reg
] && !call_used_regs
[next_hi_reg
]
9988 && !(TARGET_SINGLE_PIC_BASE
&& (next_hi_reg
== arm_pic_register
)))
9991 while (high_regs_pushed
)
9993 /* Find lo register(s) into which the high register(s) can
9995 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
9997 if (mask
& (1 << regno
))
9999 if (high_regs_pushed
== 0)
10003 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
10005 /* Pop the values into the low register(s). */
10006 thumb_pushpop (asm_out_file
, mask
, 0);
10008 /* Move the value(s) into the high registers. */
10009 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10011 if (mask
& (1 << regno
))
10013 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
10016 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
10017 if (regs_ever_live
[next_hi_reg
]
10018 && !call_used_regs
[next_hi_reg
]
10019 && !(TARGET_SINGLE_PIC_BASE
10020 && (next_hi_reg
== arm_pic_register
)))
10027 had_to_push_lr
= (live_regs_mask
|| !leaf_function
10028 || thumb_far_jump_used_p (1));
10030 if (TARGET_BACKTRACE
10031 && ((live_regs_mask
& 0xFF) == 0)
10032 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
10034 /* The stack backtrace structure creation code had to
10035 push R7 in order to get a work register, so we pop
10037 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
10040 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
10043 && !is_called_in_ARM_mode (current_function_decl
)
10045 live_regs_mask
|= 1 << PC_REGNUM
;
10047 /* Either no argument registers were pushed or a backtrace
10048 structure was created which includes an adjusted stack
10049 pointer, so just pop everything. */
10050 if (live_regs_mask
)
10051 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
10054 thumb_exit (asm_out_file
, 2, eh_ofs
);
10055 /* We have either just popped the return address into the
10056 PC or it is was kept in LR for the entire function or
10057 it is still on the stack because we do not want to
10058 return by doing a pop {pc}. */
10059 else if ((live_regs_mask
& (1 << PC_REGNUM
)) == 0)
10060 thumb_exit (asm_out_file
,
10062 && is_called_in_ARM_mode (current_function_decl
)) ?
10063 -1 : LR_REGNUM
, NULL_RTX
);
10067 /* Pop everything but the return address. */
10068 live_regs_mask
&= ~(1 << PC_REGNUM
);
10070 if (live_regs_mask
)
10071 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
10073 if (had_to_push_lr
)
10074 /* Get the return address into a temporary register. */
10075 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0);
10077 /* Remove the argument registers that were pushed onto the stack. */
10078 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
10079 SP_REGNUM
, SP_REGNUM
,
10080 current_function_pretend_args_size
);
10083 thumb_exit (asm_out_file
, 2, eh_ofs
);
10085 thumb_exit (asm_out_file
,
10086 had_to_push_lr
? LAST_ARG_REGNUM
: LR_REGNUM
, NULL_RTX
);
10092 /* Functions to save and restore machine-specific function data. */
10095 arm_mark_machine_status (p
)
10096 struct function
* p
;
10098 machine_function
*machine
= p
->machine
;
10101 ggc_mark_rtx (machine
->eh_epilogue_sp_ofs
);
10105 arm_init_machine_status (p
)
10106 struct function
* p
;
10109 (machine_function
*) xcalloc (1, sizeof (machine_function
));
10111 #if ARM_FT_UNKNOWWN != 0
10112 ((machine_function
*) p
->machine
)->func_type
= ARM_FT_UNKNOWN
;
10117 arm_free_machine_status (p
)
10118 struct function
* p
;
10127 /* Return an RTX indicating where the return address to the
10128 calling function can be found. */
10131 arm_return_addr (count
, frame
)
10133 rtx frame ATTRIBUTE_UNUSED
;
10138 if (TARGET_APCS_32
)
10139 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
10142 rtx lr
= gen_rtx_AND (Pmode
, gen_rtx_REG (Pmode
, LR_REGNUM
),
10143 GEN_INT (RETURN_ADDR_MASK26
));
10144 return get_func_hard_reg_initial_val (cfun
, lr
);
10148 /* Do anything needed before RTL is emitted for each function. */
10151 arm_init_expanders ()
10153 /* Arrange to initialize and mark the machine per-function status. */
10154 init_machine_status
= arm_init_machine_status
;
10155 mark_machine_status
= arm_mark_machine_status
;
10156 free_machine_status
= arm_free_machine_status
;
10159 /* Generate the rest of a function's prologue. */
10162 thumb_expand_prologue ()
10164 HOST_WIDE_INT amount
= (get_frame_size ()
10165 + current_function_outgoing_args_size
);
10166 unsigned long func_type
;
10168 func_type
= arm_current_func_type ();
10170 /* Naked functions don't have prologues. */
10171 if (IS_NAKED (func_type
))
10174 if (IS_INTERRUPT (func_type
))
10176 error ("interrupt Service Routines cannot be coded in Thumb mode");
10180 if (frame_pointer_needed
)
10181 emit_insn (gen_movsi (hard_frame_pointer_rtx
, stack_pointer_rtx
));
10185 amount
= ROUND_UP (amount
);
10188 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10189 GEN_INT (- amount
)));
10195 /* The stack decrement is too big for an immediate value in a single
10196 insn. In theory we could issue multiple subtracts, but after
10197 three of them it becomes more space efficient to place the full
10198 value in the constant pool and load into a register. (Also the
10199 ARM debugger really likes to see only one stack decrement per
10200 function). So instead we look for a scratch register into which
10201 we can load the decrement, and then we subtract this from the
10202 stack pointer. Unfortunately on the thumb the only available
10203 scratch registers are the argument registers, and we cannot use
10204 these as they may hold arguments to the function. Instead we
10205 attempt to locate a call preserved register which is used by this
10206 function. If we can find one, then we know that it will have
10207 been pushed at the start of the prologue and so we can corrupt
10209 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
10210 if (regs_ever_live
[regno
]
10211 && !call_used_regs
[regno
] /* Paranoia */
10212 && !(TARGET_SINGLE_PIC_BASE
&& (regno
== arm_pic_register
))
10213 && !(frame_pointer_needed
10214 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
10217 if (regno
> LAST_LO_REGNUM
) /* Very unlikely */
10219 rtx spare
= gen_rtx (REG
, SImode
, IP_REGNUM
);
10221 /* Choose an arbitary, non-argument low register. */
10222 reg
= gen_rtx (REG
, SImode
, LAST_LO_REGNUM
);
10224 /* Save it by copying it into a high, scratch register. */
10225 emit_insn (gen_movsi (spare
, reg
));
10226 /* Add a USE to stop propagate_one_insn() from barfing. */
10227 emit_insn (gen_prologue_use (spare
));
10229 /* Decrement the stack. */
10230 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
10231 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10234 /* Restore the low register's original value. */
10235 emit_insn (gen_movsi (reg
, spare
));
10237 /* Emit a USE of the restored scratch register, so that flow
10238 analysis will not consider the restore redundant. The
10239 register won't be used again in this function and isn't
10240 restored by the epilogue. */
10241 emit_insn (gen_prologue_use (reg
));
10245 reg
= gen_rtx (REG
, SImode
, regno
);
10247 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
10248 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10254 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
10255 emit_insn (gen_blockage ());
10259 thumb_expand_epilogue ()
10261 HOST_WIDE_INT amount
= (get_frame_size ()
10262 + current_function_outgoing_args_size
);
10264 /* Naked functions don't have prologues. */
10265 if (IS_NAKED (arm_current_func_type ()))
10268 if (frame_pointer_needed
)
10269 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
10272 amount
= ROUND_UP (amount
);
10275 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10276 GEN_INT (amount
)));
10279 /* r3 is always free in the epilogue. */
10280 rtx reg
= gen_rtx (REG
, SImode
, LAST_ARG_REGNUM
);
10282 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
10283 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
10287 /* Emit a USE (stack_pointer_rtx), so that
10288 the stack adjustment will not be deleted. */
10289 emit_insn (gen_prologue_use (stack_pointer_rtx
));
10291 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
10292 emit_insn (gen_blockage ());
10296 thumb_output_function_prologue (f
, size
)
10298 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
10300 int live_regs_mask
= 0;
10301 int high_regs_pushed
= 0;
10304 if (IS_NAKED (arm_current_func_type ()))
10307 if (is_called_in_ARM_mode (current_function_decl
))
10311 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
10313 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
10315 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10317 /* Generate code sequence to switch us into Thumb mode. */
10318 /* The .code 32 directive has already been emitted by
10319 ASM_DECLARE_FUNCTION_NAME. */
10320 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
10321 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
10323 /* Generate a label, so that the debugger will notice the
10324 change in instruction sets. This label is also used by
10325 the assembler to bypass the ARM code when this function
10326 is called from a Thumb encoded function elsewhere in the
10327 same file. Hence the definition of STUB_NAME here must
10328 agree with the definition in gas/config/tc-arm.c */
10330 #define STUB_NAME ".real_start_of"
10332 asm_fprintf (f
, "\t.code\t16\n");
10334 if (arm_dllexport_name_p (name
))
10335 name
= arm_strip_name_encoding (name
);
10337 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
10338 asm_fprintf (f
, "\t.thumb_func\n");
10339 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
10342 if (current_function_pretend_args_size
)
10344 if (cfun
->machine
->uses_anonymous_args
)
10348 asm_fprintf (f
, "\tpush\t{");
10350 num_pushes
= NUM_INTS (current_function_pretend_args_size
);
10352 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
10353 regno
<= LAST_ARG_REGNUM
;
10355 asm_fprintf (f
, "%r%s", regno
,
10356 regno
== LAST_ARG_REGNUM
? "" : ", ");
10358 asm_fprintf (f
, "}\n");
10361 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
10362 SP_REGNUM
, SP_REGNUM
,
10363 current_function_pretend_args_size
);
10366 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10367 if (regs_ever_live
[regno
] && !call_used_regs
[regno
]
10368 && !(TARGET_SINGLE_PIC_BASE
&& (regno
== arm_pic_register
)))
10369 live_regs_mask
|= 1 << regno
;
10371 if (live_regs_mask
|| !leaf_function_p () || thumb_far_jump_used_p (1))
10372 live_regs_mask
|= 1 << LR_REGNUM
;
10374 if (TARGET_BACKTRACE
)
10377 int work_register
= 0;
10380 /* We have been asked to create a stack backtrace structure.
10381 The code looks like this:
10385 0 sub SP, #16 Reserve space for 4 registers.
10386 2 push {R7} Get a work register.
10387 4 add R7, SP, #20 Get the stack pointer before the push.
10388 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
10389 8 mov R7, PC Get hold of the start of this code plus 12.
10390 10 str R7, [SP, #16] Store it.
10391 12 mov R7, FP Get hold of the current frame pointer.
10392 14 str R7, [SP, #4] Store it.
10393 16 mov R7, LR Get hold of the current return address.
10394 18 str R7, [SP, #12] Store it.
10395 20 add R7, SP, #16 Point at the start of the backtrace structure.
10396 22 mov FP, R7 Put this value into the frame pointer. */
10398 if ((live_regs_mask
& 0xFF) == 0)
10400 /* See if the a4 register is free. */
10402 if (regs_ever_live
[LAST_ARG_REGNUM
] == 0)
10403 work_register
= LAST_ARG_REGNUM
;
10404 else /* We must push a register of our own */
10405 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
10408 if (work_register
== 0)
10410 /* Select a register from the list that will be pushed to
10411 use as our work register. */
10412 for (work_register
= (LAST_LO_REGNUM
+ 1); work_register
--;)
10413 if ((1 << work_register
) & live_regs_mask
)
10418 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
10419 SP_REGNUM
, SP_REGNUM
);
10421 if (live_regs_mask
)
10422 thumb_pushpop (f
, live_regs_mask
, 1);
10424 for (offset
= 0, wr
= 1 << 15; wr
!= 0; wr
>>= 1)
10425 if (wr
& live_regs_mask
)
10428 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
10429 offset
+ 16 + current_function_pretend_args_size
);
10431 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10434 /* Make sure that the instruction fetching the PC is in the right place
10435 to calculate "start of backtrace creation code + 12". */
10436 if (live_regs_mask
)
10438 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
10439 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10441 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
10442 ARM_HARD_FRAME_POINTER_REGNUM
);
10443 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10448 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
10449 ARM_HARD_FRAME_POINTER_REGNUM
);
10450 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10452 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
10453 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10457 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
10458 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10460 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
10462 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
10463 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
10465 else if (live_regs_mask
)
10466 thumb_pushpop (f
, live_regs_mask
, 1);
10468 for (regno
= 8; regno
< 13; regno
++)
10470 if (regs_ever_live
[regno
] && !call_used_regs
[regno
]
10471 && !(TARGET_SINGLE_PIC_BASE
&& (regno
== arm_pic_register
)))
10472 high_regs_pushed
++;
10475 if (high_regs_pushed
)
10477 int pushable_regs
= 0;
10478 int mask
= live_regs_mask
& 0xff;
10481 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
10483 if (regs_ever_live
[next_hi_reg
] && !call_used_regs
[next_hi_reg
]
10484 && !(TARGET_SINGLE_PIC_BASE
10485 && (next_hi_reg
== arm_pic_register
)))
10489 pushable_regs
= mask
;
10491 if (pushable_regs
== 0)
10493 /* Desperation time -- this probably will never happen. */
10494 if (regs_ever_live
[LAST_ARG_REGNUM
]
10495 || !call_used_regs
[LAST_ARG_REGNUM
])
10496 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, LAST_ARG_REGNUM
);
10497 mask
= 1 << LAST_ARG_REGNUM
;
10500 while (high_regs_pushed
> 0)
10502 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
10504 if (mask
& (1 << regno
))
10506 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
10508 high_regs_pushed
--;
10510 if (high_regs_pushed
)
10511 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
10514 if (regs_ever_live
[next_hi_reg
]
10515 && !call_used_regs
[next_hi_reg
]
10516 && !(TARGET_SINGLE_PIC_BASE
10517 && (next_hi_reg
== arm_pic_register
)))
10522 mask
&= ~((1 << regno
) - 1);
10528 thumb_pushpop (f
, mask
, 1);
10531 if (pushable_regs
== 0
10532 && (regs_ever_live
[LAST_ARG_REGNUM
]
10533 || !call_used_regs
[LAST_ARG_REGNUM
]))
10534 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
10538 /* Handle the case of a double word load into a low register from
10539 a computed memory address. The computed address may involve a
10540 register which is overwritten by the load. */
10543 thumb_load_double_from_address (operands
)
10552 if (GET_CODE (operands
[0]) != REG
)
10555 if (GET_CODE (operands
[1]) != MEM
)
10558 /* Get the memory address. */
10559 addr
= XEXP (operands
[1], 0);
10561 /* Work out how the memory address is computed. */
10562 switch (GET_CODE (addr
))
10565 operands
[2] = gen_rtx (MEM
, SImode
,
10566 plus_constant (XEXP (operands
[1], 0), 4));
10568 if (REGNO (operands
[0]) == REGNO (addr
))
10570 output_asm_insn ("ldr\t%H0, %2", operands
);
10571 output_asm_insn ("ldr\t%0, %1", operands
);
10575 output_asm_insn ("ldr\t%0, %1", operands
);
10576 output_asm_insn ("ldr\t%H0, %2", operands
);
10581 /* Compute <address> + 4 for the high order load. */
10582 operands
[2] = gen_rtx (MEM
, SImode
,
10583 plus_constant (XEXP (operands
[1], 0), 4));
10585 output_asm_insn ("ldr\t%0, %1", operands
);
10586 output_asm_insn ("ldr\t%H0, %2", operands
);
10590 arg1
= XEXP (addr
, 0);
10591 arg2
= XEXP (addr
, 1);
10593 if (CONSTANT_P (arg1
))
10594 base
= arg2
, offset
= arg1
;
10596 base
= arg1
, offset
= arg2
;
10598 if (GET_CODE (base
) != REG
)
10601 /* Catch the case of <address> = <reg> + <reg> */
10602 if (GET_CODE (offset
) == REG
)
10604 int reg_offset
= REGNO (offset
);
10605 int reg_base
= REGNO (base
);
10606 int reg_dest
= REGNO (operands
[0]);
10608 /* Add the base and offset registers together into the
10609 higher destination register. */
10610 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
10611 reg_dest
+ 1, reg_base
, reg_offset
);
10613 /* Load the lower destination register from the address in
10614 the higher destination register. */
10615 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
10616 reg_dest
, reg_dest
+ 1);
10618 /* Load the higher destination register from its own address
10620 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
10621 reg_dest
+ 1, reg_dest
+ 1);
10625 /* Compute <address> + 4 for the high order load. */
10626 operands
[2] = gen_rtx (MEM
, SImode
,
10627 plus_constant (XEXP (operands
[1], 0), 4));
10629 /* If the computed address is held in the low order register
10630 then load the high order register first, otherwise always
10631 load the low order register first. */
10632 if (REGNO (operands
[0]) == REGNO (base
))
10634 output_asm_insn ("ldr\t%H0, %2", operands
);
10635 output_asm_insn ("ldr\t%0, %1", operands
);
10639 output_asm_insn ("ldr\t%0, %1", operands
);
10640 output_asm_insn ("ldr\t%H0, %2", operands
);
10646 /* With no registers to worry about we can just load the value
10648 operands
[2] = gen_rtx (MEM
, SImode
,
10649 plus_constant (XEXP (operands
[1], 0), 4));
10651 output_asm_insn ("ldr\t%H0, %2", operands
);
10652 output_asm_insn ("ldr\t%0, %1", operands
);
10665 thumb_output_move_mem_multiple (n
, operands
)
10674 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10677 operands
[4] = operands
[5];
10680 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
10681 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
10685 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10688 operands
[4] = operands
[5];
10691 if (REGNO (operands
[5]) > REGNO (operands
[6]))
10694 operands
[5] = operands
[6];
10697 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10700 operands
[4] = operands
[5];
10704 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
10705 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
10715 /* Routines for generating rtl. */
10718 thumb_expand_movstrqi (operands
)
10721 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
10722 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
10723 HOST_WIDE_INT len
= INTVAL (operands
[2]);
10724 HOST_WIDE_INT offset
= 0;
10728 emit_insn (gen_movmem12b (out
, in
, out
, in
));
10734 emit_insn (gen_movmem8b (out
, in
, out
, in
));
10740 rtx reg
= gen_reg_rtx (SImode
);
10741 emit_insn (gen_movsi (reg
, gen_rtx (MEM
, SImode
, in
)));
10742 emit_insn (gen_movsi (gen_rtx (MEM
, SImode
, out
), reg
));
10749 rtx reg
= gen_reg_rtx (HImode
);
10750 emit_insn (gen_movhi (reg
, gen_rtx (MEM
, HImode
,
10751 plus_constant (in
, offset
))));
10752 emit_insn (gen_movhi (gen_rtx (MEM
, HImode
, plus_constant (out
, offset
)),
10760 rtx reg
= gen_reg_rtx (QImode
);
10761 emit_insn (gen_movqi (reg
, gen_rtx (MEM
, QImode
,
10762 plus_constant (in
, offset
))));
10763 emit_insn (gen_movqi (gen_rtx (MEM
, QImode
, plus_constant (out
, offset
)),
10769 thumb_cmp_operand (op
, mode
)
10771 enum machine_mode mode
;
10773 return ((GET_CODE (op
) == CONST_INT
10774 && (unsigned HOST_WIDE_INT
) (INTVAL (op
)) < 256)
10775 || register_operand (op
, mode
));
10778 static const char *
10779 thumb_condition_code (x
, invert
)
10783 static const char * const conds
[] =
10785 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
10786 "hi", "ls", "ge", "lt", "gt", "le"
10790 switch (GET_CODE (x
))
10792 case EQ
: val
= 0; break;
10793 case NE
: val
= 1; break;
10794 case GEU
: val
= 2; break;
10795 case LTU
: val
= 3; break;
10796 case GTU
: val
= 8; break;
10797 case LEU
: val
= 9; break;
10798 case GE
: val
= 10; break;
10799 case LT
: val
= 11; break;
10800 case GT
: val
= 12; break;
10801 case LE
: val
= 13; break;
10806 return conds
[val
^ invert
];
10809 /* Handle storing a half-word to memory during reload. */
10812 thumb_reload_out_hi (operands
)
10815 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
10818 /* Handle storing a half-word to memory during reload. */
10821 thumb_reload_in_hi (operands
)
10822 rtx
* operands ATTRIBUTE_UNUSED
;
10827 /* Return the length of a function name prefix
10828 that starts with the character 'c'. */
10831 arm_get_strip_length (char c
)
10835 ARM_NAME_ENCODING_LENGTHS
10840 /* Return a pointer to a function's name with any
10841 and all prefix encodings stripped from it. */
10844 arm_strip_name_encoding (const char * name
)
10848 while ((skip
= arm_get_strip_length (* name
)))
10854 #ifdef AOF_ASSEMBLER
10855 /* Special functions only needed when producing AOF syntax assembler. */
10857 rtx aof_pic_label
= NULL_RTX
;
10860 struct pic_chain
* next
;
10861 const char * symname
;
10864 static struct pic_chain
* aof_pic_chain
= NULL
;
10870 struct pic_chain
** chainp
;
10873 if (aof_pic_label
== NULL_RTX
)
10875 /* We mark this here and not in arm_add_gc_roots() to avoid
10876 polluting even more code with ifdefs, and because it never
10877 contains anything useful until we assign to it here. */
10878 ggc_add_rtx_root (&aof_pic_label
, 1);
10879 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
10882 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
10883 offset
+= 4, chainp
= &(*chainp
)->next
)
10884 if ((*chainp
)->symname
== XSTR (x
, 0))
10885 return plus_constant (aof_pic_label
, offset
);
10887 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
10888 (*chainp
)->next
= NULL
;
10889 (*chainp
)->symname
= XSTR (x
, 0);
10890 return plus_constant (aof_pic_label
, offset
);
10894 aof_dump_pic_table (f
)
10897 struct pic_chain
* chain
;
10899 if (aof_pic_chain
== NULL
)
10902 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
10903 PIC_OFFSET_TABLE_REGNUM
,
10904 PIC_OFFSET_TABLE_REGNUM
);
10905 fputs ("|x$adcons|\n", f
);
10907 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
10909 fputs ("\tDCD\t", f
);
10910 assemble_name (f
, chain
->symname
);
10915 int arm_text_section_count
= 1;
10918 aof_text_section ()
10920 static char buf
[100];
10921 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
10922 arm_text_section_count
++);
10924 strcat (buf
, ", PIC, REENTRANT");
10928 static int arm_data_section_count
= 1;
10931 aof_data_section ()
10933 static char buf
[100];
10934 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
10938 /* The AOF assembler is religiously strict about declarations of
10939 imported and exported symbols, so that it is impossible to declare
10940 a function as imported near the beginning of the file, and then to
10941 export it later on. It is, however, possible to delay the decision
10942 until all the functions in the file have been compiled. To get
10943 around this, we maintain a list of the imports and exports, and
10944 delete from it any that are subsequently defined. At the end of
10945 compilation we spit the remainder of the list out before the END
10950 struct import
* next
;
10954 static struct import
* imports_list
= NULL
;
10957 aof_add_import (name
)
10960 struct import
* new;
10962 for (new = imports_list
; new; new = new->next
)
10963 if (new->name
== name
)
10966 new = (struct import
*) xmalloc (sizeof (struct import
));
10967 new->next
= imports_list
;
10968 imports_list
= new;
10973 aof_delete_import (name
)
10976 struct import
** old
;
10978 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
10980 if ((*old
)->name
== name
)
10982 *old
= (*old
)->next
;
10988 int arm_main_function
= 0;
10991 aof_dump_imports (f
)
10994 /* The AOF assembler needs this to cause the startup code to be extracted
10995 from the library. Brining in __main causes the whole thing to work
10997 if (arm_main_function
)
11000 fputs ("\tIMPORT __main\n", f
);
11001 fputs ("\tDCD __main\n", f
);
11004 /* Now dump the remaining imports. */
11005 while (imports_list
)
11007 fprintf (f
, "\tIMPORT\t");
11008 assemble_name (f
, imports_list
->name
);
11010 imports_list
= imports_list
->next
;
11013 #endif /* AOF_ASSEMBLER */
11015 #ifdef OBJECT_FORMAT_ELF
11016 /* Switch to an arbitrary section NAME with attributes as specified
11017 by FLAGS. ALIGN specifies any known alignment requirements for
11018 the section; 0 if the default should be used.
11020 Differs from the default elf version only in the prefix character
11021 used before the section type. */
11024 arm_elf_asm_named_section (name
, flags
)
11026 unsigned int flags
;
11028 char flagchars
[8], *f
= flagchars
;
11031 if (!(flags
& SECTION_DEBUG
))
11033 if (flags
& SECTION_WRITE
)
11035 if (flags
& SECTION_CODE
)
11037 if (flags
& SECTION_SMALL
)
11039 if (flags
& SECTION_MERGE
)
11041 if (flags
& SECTION_STRINGS
)
11045 if (flags
& SECTION_BSS
)
11050 if (flags
& SECTION_ENTSIZE
)
11051 fprintf (asm_out_file
, "\t.section\t%s,\"%s\",%%%s,%d\n",
11052 name
, flagchars
, type
, flags
& SECTION_ENTSIZE
);
11054 fprintf (asm_out_file
, "\t.section\t%s,\"%s\",%%%s\n",
11055 name
, flagchars
, type
);
11060 /* Symbols in the text segment can be accessed without indirecting via the
11061 constant pool; it may take an extra binary operation, but this is still
11062 faster than indirecting via memory. Don't do this when not optimizing,
11063 since we won't be calculating al of the offsets necessary to do this
11067 arm_encode_section_info (decl
, first
)
11071 /* This doesn't work with AOF syntax, since the string table may be in
11072 a different AREA. */
11073 #ifndef AOF_ASSEMBLER
11074 if (optimize
> 0 && TREE_CONSTANT (decl
)
11075 && (!flag_writable_strings
|| TREE_CODE (decl
) != STRING_CST
))
11077 rtx rtl
= (TREE_CODE_CLASS (TREE_CODE (decl
)) != 'd'
11078 ? TREE_CST_RTL (decl
) : DECL_RTL (decl
));
11079 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
11083 /* If we are referencing a function that is weak then encode a long call
11084 flag in the function name, otherwise if the function is static or
11085 or known to be defined in this file then encode a short call flag. */
11086 if (first
&& TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd')
11088 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
11089 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
11090 else if (! TREE_PUBLIC (decl
))
11091 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
11094 #endif /* !ARM_PE */