1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991-2020 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 3, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 Under Section 7 of GPL version 3, you are granted additional
21 permissions described in the GCC Runtime Library Exception, version
22 3.1, as published by the Free Software Foundation.
24 You should have received a copy of the GNU General Public License and
25 a copy of the GCC Runtime Library Exception along with this program;
26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
27 <http://www.gnu.org/licenses/>. */
32 /* We can't use machine_mode inside a generator file because it
33 hasn't been created yet; we shouldn't be using any code that
34 needs the real definition though, so this ought to be safe. */
38 #include "insn-modes.h"
39 #define MACHMODE machine_mode
42 #include "config/vxworks-dummy.h"
44 /* The architecture define. */
45 extern char arm_arch_name
[];
47 /* Target CPU builtins. */
48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile)
50 /* Target CPU versions for D. */
51 #define TARGET_D_CPU_VERSIONS arm_d_target_versions
53 #include "config/arm/arm-opts.h"
55 /* The processor for which instructions should be scheduled. */
56 extern enum processor_type arm_tune
;
58 typedef enum arm_cond_code
60 ARM_EQ
= 0, ARM_NE
, ARM_CS
, ARM_CC
, ARM_MI
, ARM_PL
, ARM_VS
, ARM_VC
,
61 ARM_HI
, ARM_LS
, ARM_GE
, ARM_LT
, ARM_GT
, ARM_LE
, ARM_AL
, ARM_NV
65 extern arm_cc arm_current_cc
;
67 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
69 /* The maximum number of instructions that is beneficial to
70 conditionally execute. */
71 #undef MAX_CONDITIONAL_EXECUTE
72 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute ()
74 extern int arm_target_label
;
75 extern int arm_ccfsm_state
;
76 extern GTY(()) rtx arm_target_insn
;
77 /* Callback to output language specific object attributes. */
78 extern void (*arm_lang_output_object_attributes_hook
)(void);
80 /* This type is the user-visible __fp16. We need it in a few places in
81 the backend. Defined in arm-builtins.c. */
82 extern tree arm_fp16_type_node
;
86 #define CPP_SPEC "%(subtarget_cpp_spec) \
87 %{mfloat-abi=soft:%{mfloat-abi=hard: \
88 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \
89 %{mbig-endian:%{mlittle-endian: \
90 %e-mbig-endian and -mlittle-endian may not be used together}}"
96 /* This macro defines names of additional specifications to put in the specs
97 that can be used in various specifications like CC1_SPEC. Its definition
98 is an initializer with a subgrouping for each command option.
100 Each subgrouping contains a string constant, that defines the
101 specification name, and a string constant that used by the GCC driver
104 Do not define this macro if it does not need to do anything. */
105 #define EXTRA_SPECS \
106 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
107 { "asm_cpu_spec", ASM_CPU_SPEC }, \
108 SUBTARGET_EXTRA_SPECS
110 #ifndef SUBTARGET_EXTRA_SPECS
111 #define SUBTARGET_EXTRA_SPECS
114 #ifndef SUBTARGET_CPP_SPEC
115 #define SUBTARGET_CPP_SPEC ""
118 /* Tree Target Specification. */
119 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags))
120 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2)
121 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2)
122 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags))
124 /* Run-time Target Specification. */
125 /* Use hardware floating point instructions. -mgeneral-regs-only prevents
126 the use of floating point instructions and registers but does not prevent
127 emission of floating point pcs attributes. */
128 #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT \
129 && bitmap_bit_p (arm_active_target.isa, \
133 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \
134 && !TARGET_GENERAL_REGS_ONLY)
136 #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT_SUB)
137 /* User has permitted use of FP instructions, if they exist for this
139 #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
140 /* Use hardware floating point calling convention. */
141 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
142 #define TARGET_IWMMXT (arm_arch_iwmmxt)
143 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
144 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \
145 && !TARGET_GENERAL_REGS_ONLY)
146 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \
147 && !TARGET_GENERAL_REGS_ONLY)
148 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
149 #define TARGET_ARM (! TARGET_THUMB)
150 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
151 #define TARGET_BACKTRACE (crtl->is_leaf \
152 ? TARGET_TPCS_LEAF_FRAME \
154 #define TARGET_AAPCS_BASED \
155 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
157 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
158 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
159 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2)
161 /* Only 16-bit thumb code. */
162 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
163 /* Arm or Thumb-2 32-bit code. */
164 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
165 /* 32-bit Thumb-2 code. */
166 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
168 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
170 #define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \
173 #define TARGET_CRC32 (arm_arch_crc)
175 /* The following two macros concern the ability to execute coprocessor
176 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
177 only ever tested when we know we are generating for VFP hardware; we need
178 to be more careful with TARGET_NEON as noted below. */
180 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
181 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32))
183 /* FPU supports VFPv3 instructions. */
184 #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3))
186 /* FPU supports FPv5 instructions. */
187 #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5))
189 /* FPU only supports VFP single-precision instructions. */
190 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE)
192 /* FPU supports VFP double-precision instructions. */
193 #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl))
195 /* FPU supports half-precision floating-point with NEON element load/store. */
196 #define TARGET_NEON_FP16 \
197 (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \
198 && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv))
200 /* FPU supports VFP half-precision floating-point conversions. */
201 #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv))
203 /* FPU supports converting between HFmode and DFmode in a single hardware
205 #define TARGET_FP16_TO_DOUBLE \
206 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE)
208 /* FPU supports fused-multiply-add operations. */
209 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4))
211 /* FPU supports Crypto extensions. */
212 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto))
214 /* FPU supports Neon instructions. The setting of this macro gets
215 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
216 and TARGET_HARD_FLOAT to ensure that NEON instructions are
218 #define TARGET_NEON \
219 (TARGET_32BIT && TARGET_HARD_FLOAT \
220 && bitmap_bit_p (arm_active_target.isa, isa_bit_neon))
222 /* FPU supports ARMv8.1 Adv.SIMD extensions. */
223 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1)
225 /* Supports the Dot Product AdvSIMD extensions. */
226 #define TARGET_DOTPROD (TARGET_NEON && TARGET_VFP5 \
227 && bitmap_bit_p (arm_active_target.isa, \
231 /* Supports the Armv8.3-a Complex number AdvSIMD extensions. */
232 #define TARGET_COMPLEX (TARGET_NEON && arm_arch8_3)
234 /* FPU supports the floating point FP16 instructions for ARMv8.2-A
236 #define TARGET_VFP_FP16INST \
237 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst)
239 /* Target supports the floating point FP16 instructions from ARMv8.2-A
241 #define TARGET_FP16FML (TARGET_NEON \
242 && bitmap_bit_p (arm_active_target.isa, \
246 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */
247 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA)
249 /* Q-bit is present. */
250 #define TARGET_ARM_QBIT \
251 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7))
252 /* Saturation operation, e.g. SSAT. */
253 #define TARGET_ARM_SAT \
254 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7))
255 /* "DSP" multiply instructions, eg. SMULxy. */
256 #define TARGET_DSP_MULTIPLY \
257 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em))
258 /* Integer SIMD instructions, and extend-accumulate instructions. */
259 #define TARGET_INT_SIMD \
260 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
262 /* Should MOVW/MOVT be used in preference to a constant pool. */
263 #define TARGET_USE_MOVT \
265 && (arm_disable_literal_pool \
266 || (!optimize_size && !current_tune->prefer_constant_pool)))
268 /* Nonzero if this chip provides the DMB instruction. */
269 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7)
271 /* Nonzero if this chip implements a memory barrier via CP15. */
272 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
275 /* Nonzero if this chip implements a memory barrier instruction. */
276 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
278 /* Nonzero if this chip supports ldrex and strex */
279 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \
281 || (arm_arch8 && !arm_arch_notm))
283 /* Nonzero if this chip supports LPAE. */
284 #define TARGET_HAVE_LPAE (arm_arch_lpae)
286 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
287 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \
289 || (arm_arch8 && !arm_arch_notm))
291 /* Nonzero if this chip supports ldrexd and strexd. */
292 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \
293 || arm_arch7) && arm_arch_notm)
295 /* Nonzero if this chip supports load-acquire and store-release. */
296 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8)
298 /* Nonzero if this chip supports LDAEXD and STLEXD. */
299 #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \
303 /* Nonzero if this chip provides the MOVW and MOVT instructions. */
304 #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8)
306 /* Nonzero if this chip provides the CBZ and CBNZ instructions. */
307 #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8)
309 /* Nonzero if integer division instructions supported. */
310 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
311 || (TARGET_THUMB && arm_arch_thumb_hwdiv))
313 /* Nonzero if disallow volatile memory access in IT block. */
314 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce)
316 /* Should constant I be slplit for OP. */
317 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \
319 && can_create_pseudo_p () \
320 && !const_ok_for_op (i, op))
322 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
323 then TARGET_AAPCS_BASED must be true -- but the converse does not
324 hold. TARGET_BPABI implies the use of the BPABI runtime library,
325 etc., in addition to just the AAPCS calling conventions. */
327 #define TARGET_BPABI false
330 /* Transform lane numbers on big endian targets. This is used to allow for the
331 endianness difference between NEON architectural lane numbers and those
333 #define NEON_ENDIAN_LANE_N(mode, n) \
334 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
336 /* Support for a compile-time default CPU, et cetera. The rules are:
337 --with-arch is ignored if -march or -mcpu are specified.
338 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
340 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
342 --with-float is ignored if -mfloat-abi is specified.
343 --with-fpu is ignored if -mfpu is specified.
344 --with-abi is ignored if -mabi is specified.
345 --with-tls is ignored if -mtls-dialect is specified. */
346 #define OPTION_DEFAULT_SPECS \
347 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
348 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
349 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
350 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \
351 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
352 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
353 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \
354 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
356 extern const struct arm_fpu_desc
359 enum isa_feature isa_bits
[isa_num_bits
];
362 /* Which floating point hardware to schedule for. */
363 extern int arm_fpu_attr
;
365 #ifndef TARGET_DEFAULT_FLOAT_ABI
366 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
369 #ifndef ARM_DEFAULT_ABI
370 #define ARM_DEFAULT_ABI ARM_ABI_APCS
373 /* AAPCS based ABIs use short enums by default. */
374 #ifndef ARM_DEFAULT_SHORT_ENUMS
375 #define ARM_DEFAULT_SHORT_ENUMS \
376 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX)
379 /* Map each of the micro-architecture variants to their corresponding
380 major architecture revision. */
382 enum base_architecture
406 BASE_ARCH_8M_BASE
= 8,
407 BASE_ARCH_8M_MAIN
= 8,
411 /* The major revision number of the ARM Architecture implemented by the target. */
412 extern enum base_architecture arm_base_arch
;
414 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
415 extern int arm_arch4
;
417 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
418 extern int arm_arch4t
;
420 /* Nonzero if this chip supports the ARM Architecture 5T extensions. */
421 extern int arm_arch5t
;
423 /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */
424 extern int arm_arch5te
;
426 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
427 extern int arm_arch6
;
429 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
430 extern int arm_arch6k
;
432 /* Nonzero if instructions present in ARMv6-M can be used. */
433 extern int arm_arch6m
;
435 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
436 extern int arm_arch7
;
438 /* Nonzero if instructions not present in the 'M' profile can be used. */
439 extern int arm_arch_notm
;
441 /* Nonzero if instructions present in ARMv7E-M can be used. */
442 extern int arm_arch7em
;
444 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */
445 extern int arm_arch8
;
447 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */
448 extern int arm_arch8_1
;
450 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */
451 extern int arm_arch8_2
;
453 /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */
454 extern int arm_arch8_3
;
456 /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */
457 extern int arm_arch8_4
;
459 /* Nonzero if this chip supports the FP16 instructions extension of ARM
461 extern int arm_fp16_inst
;
463 /* Nonzero if this chip can benefit from load scheduling. */
464 extern int arm_ld_sched
;
466 /* Nonzero if this chip is a StrongARM. */
467 extern int arm_tune_strongarm
;
469 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
470 extern int arm_arch_iwmmxt
;
472 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */
473 extern int arm_arch_iwmmxt2
;
475 /* Nonzero if this chip is an XScale. */
476 extern int arm_arch_xscale
;
478 /* Nonzero if tuning for XScale. */
479 extern int arm_tune_xscale
;
481 /* Nonzero if tuning for stores via the write buffer. */
482 extern int arm_tune_wbuf
;
484 /* Nonzero if tuning for Cortex-A9. */
485 extern int arm_tune_cortex_a9
;
487 /* Nonzero if we should define __THUMB_INTERWORK__ in the
489 XXX This is a bit of a hack, it's intended to help work around
490 problems in GLD which doesn't understand that armv5t code is
491 interworking clean. */
492 extern int arm_cpp_interwork
;
494 /* Nonzero if chip supports Thumb 1. */
495 extern int arm_arch_thumb1
;
497 /* Nonzero if chip supports Thumb 2. */
498 extern int arm_arch_thumb2
;
500 /* Nonzero if chip supports integer division instruction in ARM mode. */
501 extern int arm_arch_arm_hwdiv
;
503 /* Nonzero if chip supports integer division instruction in Thumb mode. */
504 extern int arm_arch_thumb_hwdiv
;
506 /* Nonzero if chip disallows volatile memory access in IT block. */
507 extern int arm_arch_no_volatile_ce
;
509 /* Nonzero if we shouldn't use literal pools. */
510 #ifndef USED_FOR_TARGET
511 extern bool arm_disable_literal_pool
;
514 /* Nonzero if chip supports the ARMv8 CRC instructions. */
515 extern int arm_arch_crc
;
517 /* Nonzero if chip supports the ARMv8-M Security Extensions. */
518 extern int arm_arch_cmse
;
520 #ifndef TARGET_DEFAULT
521 #define TARGET_DEFAULT (MASK_APCS_FRAME)
524 /* Nonzero if PIC code requires explicit qualifiers to generate
525 PLT and GOT relocs rather than the assembler doing so implicitly.
526 Subtargets can override these if required. */
527 #ifndef NEED_GOT_RELOC
528 #define NEED_GOT_RELOC 0
530 #ifndef NEED_PLT_RELOC
531 #define NEED_PLT_RELOC 0
534 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE
535 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1
538 /* Nonzero if we need to refer to the GOT with a PC-relative
539 offset. In other words, generate
541 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
545 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
547 The default is true, which matches NetBSD. Subtargets can
548 override this if required. */
553 /* Target machine storage Layout. */
556 /* Define this macro if it is advisable to hold scalars in registers
557 in a wider mode than that declared by the program. In such cases,
558 the value is constrained to be within the bounds of the declared
559 type, but kept valid in the wider mode. The signedness of the
560 extension may differ from that of the type. */
562 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
563 if (GET_MODE_CLASS (MODE) == MODE_INT \
564 && GET_MODE_SIZE (MODE) < 4) \
569 /* Define this if most significant bit is lowest numbered
570 in instructions that operate on numbered bit-fields. */
571 #define BITS_BIG_ENDIAN 0
573 /* Define this if most significant byte of a word is the lowest numbered.
574 Most ARM processors are run in little endian mode, so that is the default.
575 If you want to have it run-time selectable, change the definition in a
576 cover file to be TARGET_BIG_ENDIAN. */
577 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
579 /* Define this if most significant word of a multiword number is the lowest
581 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
583 #define UNITS_PER_WORD 4
585 /* True if natural alignment is used for doubleword types. */
586 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
588 #define DOUBLEWORD_ALIGNMENT 64
590 #define PARM_BOUNDARY 32
592 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
594 #define PREFERRED_STACK_BOUNDARY \
595 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
597 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32)
598 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags))
600 /* The lowest bit is used to indicate Thumb-mode functions, so the
601 vbit must go into the delta field of pointers to member
603 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
605 #define EMPTY_FIELD_BOUNDARY 32
607 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
609 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT
611 /* XXX Blah -- this macro is used directly by libobjc. Since it
612 supports no vector modes, cut out the complexity and fall back
613 on BIGGEST_FIELD_ALIGNMENT. */
614 #ifdef IN_TARGET_LIBS
615 #define BIGGEST_FIELD_ALIGNMENT 64
618 /* Align definitions of arrays, unions and structures so that
619 initializations and copies can be made more efficient. This is not
620 ABI-changing, so it only affects places where we can see the
621 definition. Increasing the alignment tends to introduce padding,
622 so don't do this when optimizing for size/conserving stack space. */
623 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
624 (((COND) && ((ALIGN) < BITS_PER_WORD) \
625 && (TREE_CODE (EXP) == ARRAY_TYPE \
626 || TREE_CODE (EXP) == UNION_TYPE \
627 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
629 /* Align global data. */
630 #define DATA_ALIGNMENT(EXP, ALIGN) \
631 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
633 /* Similarly, make sure that objects on the stack are sensibly aligned. */
634 #define LOCAL_ALIGNMENT(EXP, ALIGN) \
635 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
637 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
638 value set in previous versions of this toolchain was 8, which produces more
639 compact structures. The command line option -mstructure_size_boundary=<n>
640 can be used to change this value. For compatibility with the ARM SDK
641 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
642 0020D) page 2-20 says "Structures are aligned on word boundaries".
643 The AAPCS specifies a value of 8. */
644 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
646 /* This is the value used to initialize arm_structure_size_boundary. If a
647 particular arm target wants to change the default value it should change
648 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
649 for an example of this. */
650 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
651 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
654 /* Nonzero if move instructions will actually fail to work
655 when given unaligned data. */
656 #define STRICT_ALIGNMENT 1
658 /* wchar_t is unsigned under the AAPCS. */
660 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
662 #define WCHAR_TYPE_SIZE BITS_PER_WORD
665 /* Sized for fixed-point types. */
667 #define SHORT_FRACT_TYPE_SIZE 8
668 #define FRACT_TYPE_SIZE 16
669 #define LONG_FRACT_TYPE_SIZE 32
670 #define LONG_LONG_FRACT_TYPE_SIZE 64
672 #define SHORT_ACCUM_TYPE_SIZE 16
673 #define ACCUM_TYPE_SIZE 32
674 #define LONG_ACCUM_TYPE_SIZE 64
675 #define LONG_LONG_ACCUM_TYPE_SIZE 64
677 #define MAX_FIXED_MODE_SIZE 64
680 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
684 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
687 /* AAPCS requires that structure alignment is affected by bitfields. */
688 #ifndef PCC_BITFIELD_TYPE_MATTERS
689 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
692 /* The maximum size of the sync library functions supported. */
693 #ifndef MAX_SYNC_LIBFUNC_SIZE
694 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD)
698 /* Standard register usage. */
700 /* Register allocation in ARM Procedure Call Standard
701 (S - saved over call, F - Frame-related).
703 r0 * argument word/integer result
706 r4-r8 S register variable
707 r9 S (rfp) register variable (real frame pointer)
709 r10 F S (sl) stack limit (used by -mapcs-stack-check)
710 r11 F S (fp) argument pointer
711 r12 (ip) temp workspace
712 r13 F S (sp) lower end of current stack frame
713 r14 (lr) link address/workspace
714 r15 F (pc) program counter
716 cc This is NOT a real register, but is used internally
717 to represent things that use or set the condition
719 sfp This isn't either. It is used during rtl generation
720 since the offset between the frame pointer and the
721 auto's isn't known until after register allocation.
722 afp Nor this, we only need this because of non-local
723 goto. Without it fp appears to be used and the
724 elimination code won't get rid of sfp. It tracks
725 fp exactly at all times.
726 apsrq Nor this, it is used to track operations on the Q bit
727 of APSR by ACLE saturating intrinsics.
728 apsrge Nor this, it is used to track operations on the GE bits
729 of APSR by ACLE SIMD32 intrinsics
731 *: See TARGET_CONDITIONAL_REGISTER_USAGE */
733 /* s0-s15 VFP scratch (aka d0-d7).
734 s16-s31 S VFP variable (aka d8-d15).
735 vfpcc Not a real register. Represents the VFP condition
738 /* The stack backtrace structure is as follows:
739 fp points to here: | save code pointer | [fp]
740 | return link value | [fp, #-4]
741 | return sp value | [fp, #-8]
742 | return fp value | [fp, #-12]
743 [| saved r10 value |]
754 r0-r3 are not normally saved in a C function. */
756 /* 1 for registers that have pervasive standard uses
757 and are not available for the register allocator. */
758 #define FIXED_REGISTERS \
780 /* 1 for registers not available across function calls.
781 These must include the FIXED_REGISTERS and also any
782 registers that can be used without being saved.
783 The latter must include the registers where values are returned
784 and the register where structure-value addresses are passed.
785 Aside from that, you can include as many other registers as you like.
786 The CC is not preserved over function calls on the ARM 6, so it is
787 easier to assume this for all. SFP is preserved, since FP is. */
788 #define CALL_USED_REGISTERS \
810 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
811 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
814 /* These are a couple of extensions to the formats accepted
816 %@ prints out ASM_COMMENT_START
817 %r prints out REGISTER_PREFIX reg_names[arg] */
818 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
820 fputs (ASM_COMMENT_START, FILE); \
824 fputs (REGISTER_PREFIX, FILE); \
825 fputs (reg_names [va_arg (ARGS, int)], FILE); \
828 /* Round X up to the nearest word. */
829 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
831 /* Convert fron bytes to ints. */
832 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
834 /* The number of (integer) registers required to hold a quantity of type MODE.
835 Also used for VFP registers. */
836 #define ARM_NUM_REGS(MODE) \
837 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
839 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
840 #define ARM_NUM_REGS2(MODE, TYPE) \
841 ARM_NUM_INTS ((MODE) == BLKmode ? \
842 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
844 /* The number of (integer) argument register available. */
845 #define NUM_ARG_REGS 4
847 /* And similarly for the VFP. */
848 #define NUM_VFP_ARG_REGS 16
850 /* Return the register number of the N'th (integer) argument. */
851 #define ARG_REGISTER(N) (N - 1)
853 /* Specify the registers used for certain standard purposes.
854 The values of these macros are register numbers. */
856 /* The number of the last argument register. */
857 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
859 /* The numbers of the Thumb register ranges. */
860 #define FIRST_LO_REGNUM 0
861 #define LAST_LO_REGNUM 7
862 #define FIRST_HI_REGNUM 8
863 #define LAST_HI_REGNUM 11
865 /* Overridden by config/arm/bpabi.h. */
866 #ifndef ARM_UNWIND_INFO
867 #define ARM_UNWIND_INFO 0
870 /* Use r0 and r1 to pass exception handling information. */
871 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
873 /* The register that holds the return address in exception handlers. */
874 #define ARM_EH_STACKADJ_REGNUM 2
875 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
877 #ifndef ARM_TARGET2_DWARF_FORMAT
878 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel
881 /* ttype entries (the only interesting data references used)
882 use TARGET2 relocations. */
883 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
884 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \
887 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
888 as an invisible last argument (possible since varargs don't exist in
889 Pascal), so the following is not true. */
890 #define STATIC_CHAIN_REGNUM 12
892 /* r9 is the FDPIC register (base register for GOT and FUNCDESC accesses). */
893 #define FDPIC_REGNUM 9
895 /* Define this to be where the real frame pointer is if it is not possible to
896 work out the offset between the frame pointer and the automatic variables
897 until after register allocation has taken place. FRAME_POINTER_REGNUM
898 should point to a special register that we will make sure is eliminated.
900 For the Thumb we have another problem. The TPCS defines the frame pointer
901 as r11, and GCC believes that it is always possible to use the frame pointer
902 as base register for addressing purposes. (See comments in
903 find_reloads_address()). But - the Thumb does not allow high registers,
904 including r11, to be used as base address registers. Hence our problem.
906 The solution used here, and in the old thumb port is to use r7 instead of
907 r11 as the hard frame pointer and to have special code to generate
908 backtrace structures on the stack (if required to do so via a command line
909 option) using r11. This is the only 'user visible' use of r11 as a frame
911 #define ARM_HARD_FRAME_POINTER_REGNUM 11
912 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
914 #define HARD_FRAME_POINTER_REGNUM \
916 ? ARM_HARD_FRAME_POINTER_REGNUM \
917 : THUMB_HARD_FRAME_POINTER_REGNUM)
919 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
920 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
922 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
924 /* Register to use for pushing function arguments. */
925 #define STACK_POINTER_REGNUM SP_REGNUM
927 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1)
928 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
930 /* Need to sync with WCGR in iwmmxt.md. */
931 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
932 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3)
934 #define IS_IWMMXT_REGNUM(REGNUM) \
935 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
936 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
937 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
939 /* Base register for access to local variables of the function. */
940 #define FRAME_POINTER_REGNUM 102
942 /* Base register for access to arguments of the function. */
943 #define ARG_POINTER_REGNUM 103
945 #define FIRST_VFP_REGNUM 16
946 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15)
947 #define LAST_VFP_REGNUM \
948 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
950 #define IS_VFP_REGNUM(REGNUM) \
951 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
953 /* VFP registers are split into two types: those defined by VFP versions < 3
954 have D registers overlaid on consecutive pairs of S registers. VFP version 3
955 defines 16 new D registers (d16-d31) which, for simplicity and correctness
956 in various parts of the backend, we implement as "fake" single-precision
957 registers (which would be S32-S63, but cannot be used in that way). The
958 following macros define these ranges of registers. */
959 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31)
960 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1)
961 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31)
963 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
964 ((REGNUM) <= LAST_LO_VFP_REGNUM)
966 /* DFmode values are only valid in even register pairs. */
967 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
968 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
970 /* Neon Quad values must start at a multiple of four registers. */
971 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
972 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
974 /* Neon structures of vectors must be in even register pairs and there
975 must be enough registers available. Because of various patterns
976 requiring quad registers, we require them to start at a multiple of
978 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
979 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
980 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
982 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
983 + 1 APSRQ + 1 APSRGE. */
984 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
985 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
986 #define FIRST_PSEUDO_REGISTER 106
988 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
990 /* Value should be nonzero if functions must have frame pointers.
991 Zero means the frame pointer need not be set up (and parms may be accessed
992 via the stack pointer) in functions that seem suitable.
993 If we have to have a frame pointer we might as well make use of it.
994 APCS says that the frame pointer does not need to be pushed in leaf
995 functions, or simple tail call functions. */
997 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
998 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1001 #define VALID_IWMMXT_REG_MODE(MODE) \
1002 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1004 /* Modes valid for Neon D registers. */
1005 #define VALID_NEON_DREG_MODE(MODE) \
1006 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1007 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode)
1009 /* Modes valid for Neon Q registers. */
1010 #define VALID_NEON_QREG_MODE(MODE) \
1011 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1012 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode)
1014 /* Structure modes valid for Neon registers. */
1015 #define VALID_NEON_STRUCT_MODE(MODE) \
1016 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1017 || (MODE) == CImode || (MODE) == XImode)
1019 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1020 extern int arm_regs_in_sequence
[];
1022 /* The order in which register should be allocated. It is good to use ip
1023 since no saving is required (though calls clobber it) and it never contains
1024 function parameters. It is quite good to use lr since other calls may
1025 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1026 least likely to contain a function parameter; in addition results are
1028 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1029 then D8-D15. The reason for doing this is to attempt to reduce register
1030 pressure when both single- and double-precision registers are used in a
1033 #define VREG(X) (FIRST_VFP_REGNUM + (X))
1034 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X))
1035 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X))
1037 #define REG_ALLOC_ORDER \
1039 /* General registers. */ \
1040 3, 2, 1, 0, 12, 14, 4, 5, \
1041 6, 7, 8, 9, 10, 11, \
1042 /* High VFP registers. */ \
1043 VREG(32), VREG(33), VREG(34), VREG(35), \
1044 VREG(36), VREG(37), VREG(38), VREG(39), \
1045 VREG(40), VREG(41), VREG(42), VREG(43), \
1046 VREG(44), VREG(45), VREG(46), VREG(47), \
1047 VREG(48), VREG(49), VREG(50), VREG(51), \
1048 VREG(52), VREG(53), VREG(54), VREG(55), \
1049 VREG(56), VREG(57), VREG(58), VREG(59), \
1050 VREG(60), VREG(61), VREG(62), VREG(63), \
1051 /* VFP argument registers. */ \
1052 VREG(15), VREG(14), VREG(13), VREG(12), \
1053 VREG(11), VREG(10), VREG(9), VREG(8), \
1054 VREG(7), VREG(6), VREG(5), VREG(4), \
1055 VREG(3), VREG(2), VREG(1), VREG(0), \
1056 /* VFP call-saved registers. */ \
1057 VREG(16), VREG(17), VREG(18), VREG(19), \
1058 VREG(20), VREG(21), VREG(22), VREG(23), \
1059 VREG(24), VREG(25), VREG(26), VREG(27), \
1060 VREG(28), VREG(29), VREG(30), VREG(31), \
1061 /* IWMMX registers. */ \
1062 WREG(0), WREG(1), WREG(2), WREG(3), \
1063 WREG(4), WREG(5), WREG(6), WREG(7), \
1064 WREG(8), WREG(9), WREG(10), WREG(11), \
1065 WREG(12), WREG(13), WREG(14), WREG(15), \
1066 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \
1067 /* Registers not for general use. */ \
1068 CC_REGNUM, VFPCC_REGNUM, \
1069 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
1070 SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, APSRGE_REGNUM \
1073 /* Use different register alloc ordering for Thumb. */
1074 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1076 /* Tell IRA to use the order we define when optimizing for size. */
1077 #define HONOR_REG_ALLOC_ORDER optimize_function_for_size_p (cfun)
1079 /* Interrupt functions can only use registers that have already been
1080 saved by the prologue, even if they would normally be
1082 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1083 (! IS_INTERRUPT (cfun->machine->func_type) || \
1084 df_regs_ever_live_p (DST))
1086 /* Register and constant classes. */
1088 /* Register classes. */
1113 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1115 /* Give names of register classes as strings for dump file. */
1116 #define REG_CLASS_NAMES \
1123 "CALLER_SAVE_REGS", \
1139 /* Define which registers fit in which classes.
1140 This is an initializer for a vector of HARD_REG_SET
1141 of length N_REG_CLASSES. */
1142 #define REG_CLASS_CONTENTS \
1144 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1145 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1146 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1147 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1148 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1149 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
1150 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1151 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1152 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1153 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \
1154 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \
1155 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \
1156 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \
1157 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \
1158 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \
1159 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \
1160 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
1161 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
1162 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \
1165 /* Any of the VFP register classes. */
1166 #define IS_VFP_CLASS(X) \
1167 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1168 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1170 /* The same information, inverted:
1171 Return the class number of the smallest class containing
1172 reg number REGNO. This could be a conditional expression
1173 or could index an array. */
1174 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1176 /* The class value for index registers, and the one for base regs. */
1177 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1178 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1180 /* For the Thumb the high registers cannot be used as base registers
1181 when addressing quantities in QI or HI mode; if we don't know the
1182 mode, then we must be conservative. */
1183 #define MODE_BASE_REG_CLASS(MODE) \
1184 (TARGET_32BIT ? CORE_REGS \
1185 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \
1188 /* For Thumb we cannot support SP+reg addressing, so we return LO_REGS
1189 instead of BASE_REGS. */
1190 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1192 /* When this hook returns true for MODE, the compiler allows
1193 registers explicitly used in the rtl to be used as spill registers
1194 but prevents the compiler from extending the lifetime of these
1196 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1197 arm_small_register_classes_for_mode_p
1199 /* Must leave BASE_REGS reloads alone */
1200 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1201 (lra_in_progress ? NO_REGS \
1202 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1203 ? ((true_regnum (X) == -1 ? LO_REGS \
1204 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \
1208 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1209 (lra_in_progress ? NO_REGS \
1210 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1211 ? ((true_regnum (X) == -1 ? LO_REGS \
1212 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \
1216 /* Return the register class of a scratch register needed to copy IN into
1217 or out of a register in CLASS in MODE. If it can be done directly,
1218 NO_REGS is returned. */
1219 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1220 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1221 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
1222 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1223 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1224 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1226 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1227 ? GENERAL_REGS : NO_REGS) \
1228 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1230 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1231 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1232 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1233 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
1234 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1235 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1236 coproc_secondary_reload_class (MODE, X, TRUE) : \
1238 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1239 && CONSTANT_P (X)) \
1241 (((MODE) == HImode && ! arm_arch4 \
1243 || ((REG_P (X) || GET_CODE (X) == SUBREG) \
1244 && true_regnum (X) == -1))) \
1245 ? GENERAL_REGS : NO_REGS) \
1246 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1248 /* Return the maximum number of consecutive registers
1249 needed to represent mode MODE in a register of class CLASS.
1250 ARM regs are UNITS_PER_WORD bits.
1251 FIXME: Is this true for iWMMX? */
1252 #define CLASS_MAX_NREGS(CLASS, MODE) \
1253 (ARM_NUM_REGS (MODE))
1255 /* If defined, gives a class of registers that cannot be used as the
1256 operand of a SUBREG that changes the mode of the object illegally. */
1258 /* Stack layout; function entry, exit and calling. */
1260 /* Define this if pushing a word on the stack
1261 makes the stack pointer a smaller address. */
1262 #define STACK_GROWS_DOWNWARD 1
1264 /* Define this to nonzero if the nominal address of the stack frame
1265 is at the high-address end of the local variables;
1266 that is, each additional local variable allocated
1267 goes at a more negative offset in the frame. */
1268 #define FRAME_GROWS_DOWNWARD 1
1270 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1271 When present, it is one word in size, and sits at the top of the frame,
1272 between the soft frame pointer and either r7 or r11.
1274 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1275 and only then if some outgoing arguments are passed on the stack. It would
1276 be tempting to also check whether the stack arguments are passed by indirect
1277 calls, but there seems to be no reason in principle why a post-reload pass
1278 couldn't convert a direct call into an indirect one. */
1279 #define CALLER_INTERWORKING_SLOT_SIZE \
1280 (TARGET_CALLER_INTERWORKING \
1281 && maybe_ne (crtl->outgoing_args_size, 0) \
1282 ? UNITS_PER_WORD : 0)
1284 /* If we generate an insn to push BYTES bytes,
1285 this says how many the stack pointer really advances by. */
1286 /* The push insns do not do this rounding implicitly.
1287 So don't define this. */
1288 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1290 /* Define this if the maximum size of all the outgoing args is to be
1291 accumulated and pushed during the prologue. The amount can be
1292 found in the variable crtl->outgoing_args_size. */
1293 #define ACCUMULATE_OUTGOING_ARGS 1
1295 /* Offset of first parameter from the argument pointer register value. */
1296 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1298 /* Amount of memory needed for an untyped call to save all possible return
1300 #define APPLY_RESULT_SIZE arm_apply_result_size()
1302 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1303 values must be in memory. On the ARM, they need only do so if larger
1304 than a word, or if they contain elements offset from zero in the struct. */
1305 #define DEFAULT_PCC_STRUCT_RETURN 0
1307 /* These bits describe the different types of function supported
1308 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1309 normal function and an interworked function, for example. Knowing the
1310 type of a function is important for determining its prologue and
1312 Note value 7 is currently unassigned. Also note that the interrupt
1313 function types all have bit 2 set, so that they can be tested for easily.
1314 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1315 machine_function structure is initialized (to zero) func_type will
1316 default to unknown. This will force the first use of arm_current_func_type
1317 to call arm_compute_func_type. */
1318 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1319 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1320 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1321 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1322 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1323 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1325 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1327 /* In addition functions can have several type modifiers,
1328 outlined by these bit masks: */
1329 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1330 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1331 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1332 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1333 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1334 #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */
1336 /* Some macros to test these flags. */
1337 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1338 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1339 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1340 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1341 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1342 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1343 #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY)
1346 /* Structure used to hold the function stack frame layout. Offsets are
1347 relative to the stack pointer on function entry. Positive offsets are
1348 in the direction of stack growth.
1349 Only soft_frame is used in thumb mode. */
1351 typedef struct GTY(()) arm_stack_offsets
1353 int saved_args
; /* ARG_POINTER_REGNUM. */
1354 int frame
; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1356 int soft_frame
; /* FRAME_POINTER_REGNUM. */
1357 int locals_base
; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1358 int outgoing_args
; /* STACK_POINTER_REGNUM. */
1359 unsigned int saved_regs_mask
;
1363 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET)
1364 /* A C structure for machine-specific, per-function data.
1365 This is added to the cfun structure. */
1366 typedef struct GTY(()) machine_function
1368 /* Additional stack adjustment in __builtin_eh_throw. */
1369 rtx eh_epilogue_sp_ofs
;
1370 /* Records if LR has to be saved for far jumps. */
1372 /* Records if ARG_POINTER was ever live. */
1373 int arg_pointer_live
;
1374 /* Records if the save of LR has been eliminated. */
1375 int lr_save_eliminated
;
1376 /* The size of the stack frame. Only valid after reload. */
1377 arm_stack_offsets stack_offsets
;
1378 /* Records the type of the current function. */
1379 unsigned long func_type
;
1380 /* Record if the function has a variable argument list. */
1381 int uses_anonymous_args
;
1382 /* Records if sibcalls are blocked because an argument
1383 register is needed to preserve stack alignment. */
1384 int sibcall_blocked
;
1385 /* The PIC register for this function. This might be a pseudo. */
1387 /* Labels for per-function Thumb call-via stubs. One per potential calling
1388 register. We can never call via LR or PC. We can call via SP if a
1389 trampoline happens to be on the top of the stack. */
1391 /* Set to 1 when a return insn is output, this means that the epilogue
1393 int return_used_this_function
;
1394 /* When outputting Thumb-1 code, record the last insn that provides
1395 information about condition codes, and the comparison operands. */
1399 /* Also record the CC mode that is supported. */
1400 machine_mode thumb1_cc_mode
;
1401 /* Set to 1 after arm_reorg has started. */
1402 int after_arm_reorg
;
1403 /* The number of bytes used to store the static chain register on the
1404 stack, above the stack frame. */
1405 int static_chain_stack_bytes
;
1410 #define ARM_Q_BIT_READ (arm_q_bit_access ())
1411 #define ARM_GE_BITS_READ (arm_ge_bits_access ())
1413 /* As in the machine_function, a global set of call-via labels, for code
1414 that is in text_section. */
1415 extern GTY(()) rtx thumb_call_via_label
[14];
1417 /* The number of potential ways of assigning to a co-processor. */
1418 #define ARM_NUM_COPROC_SLOTS 1
1420 /* Enumeration of procedure calling standard variants. We don't really
1421 support all of these yet. */
1424 ARM_PCS_AAPCS
, /* Base standard AAPCS. */
1425 ARM_PCS_AAPCS_VFP
, /* Use VFP registers for floating point values. */
1426 ARM_PCS_AAPCS_IWMMXT
, /* Use iWMMXT registers for vectors. */
1427 /* This must be the last AAPCS variant. */
1428 ARM_PCS_AAPCS_LOCAL
, /* Private call within this compilation unit. */
1429 ARM_PCS_ATPCS
, /* ATPCS. */
1430 ARM_PCS_APCS
, /* APCS (legacy Linux etc). */
1434 /* Default procedure calling standard of current compilation unit. */
1435 extern enum arm_pcs arm_pcs_default
;
1437 #if !defined (USED_FOR_TARGET)
1438 /* A C type for declaring a variable that is used as the first argument of
1439 `FUNCTION_ARG' and other related values. */
1442 /* This is the number of registers of arguments scanned so far. */
1444 /* This is the number of iWMMXt register arguments scanned so far. */
1448 /* Which procedure call variant to use for this call. */
1449 enum arm_pcs pcs_variant
;
1451 /* AAPCS related state tracking. */
1452 int aapcs_arg_processed
; /* No need to lay out this argument again. */
1453 int aapcs_cprc_slot
; /* Index of co-processor rules to handle
1454 this argument, or -1 if using core
1457 int aapcs_next_ncrn
;
1458 rtx aapcs_reg
; /* Register assigned to this argument. */
1459 int aapcs_partial
; /* How many bytes are passed in regs (if
1460 split between core regs and stack.
1462 int aapcs_cprc_failed
[ARM_NUM_COPROC_SLOTS
];
1463 int can_split
; /* Argument can be split between core regs
1465 /* Private data for tracking VFP register allocation */
1466 unsigned aapcs_vfp_regs_free
;
1467 unsigned aapcs_vfp_reg_alloc
;
1468 int aapcs_vfp_rcount
;
1469 MACHMODE aapcs_vfp_rmode
;
1473 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1474 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
1476 /* For AAPCS, padding should never be below the argument. For other ABIs,
1477 * mimic the default. */
1478 #define PAD_VARARGS_DOWN \
1479 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1481 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1482 for a call to a function whose data type is FNTYPE.
1483 For a library call, FNTYPE is 0.
1484 On the ARM, the offset starts at 0. */
1485 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1486 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1488 /* 1 if N is a possible register number for function argument passing.
1489 On the ARM, r0-r3 are used to pass args. */
1490 #define FUNCTION_ARG_REGNO_P(REGNO) \
1491 (IN_RANGE ((REGNO), 0, 3) \
1492 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \
1493 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1494 || (TARGET_IWMMXT_ABI \
1495 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1498 /* If your target environment doesn't prefix user functions with an
1499 underscore, you may wish to re-define this to prevent any conflicts. */
1500 #ifndef ARM_MCOUNT_NAME
1501 #define ARM_MCOUNT_NAME "*mcount"
1504 /* Call the function profiler with a given profile label. The Acorn
1505 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1506 On the ARM the full profile code will look like:
1515 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1516 will output the .text section.
1518 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1519 ``prof'' doesn't seem to mind about this!
1521 Note - this version of the code is designed to work in both ARM and
1523 #ifndef ARM_FUNCTION_PROFILER
1524 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1529 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1530 IP_REGNUM, LR_REGNUM); \
1531 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1532 fputc ('\n', STREAM); \
1533 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1534 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1535 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1539 #ifdef THUMB_FUNCTION_PROFILER
1540 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1542 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1544 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1546 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1547 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1550 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1551 the stack pointer does not matter. The value is tested only in
1552 functions that have frame pointers.
1553 No definition is equivalent to always zero.
1555 On the ARM, the function epilogue recovers the stack pointer from the
1557 #define EXIT_IGNORE_STACK 1
1559 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM)
1561 /* Determine if the epilogue should be output as RTL.
1562 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1563 #define USE_RETURN_INSN(ISCOND) \
1564 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1566 /* Definitions for register eliminations.
1568 This is an array of structures. Each structure initializes one pair
1569 of eliminable registers. The "from" register number is given first,
1570 followed by "to". Eliminations of the same "from" register are listed
1571 in order of preference.
1573 We have two registers that can be eliminated on the ARM. First, the
1574 arg pointer register can often be eliminated in favor of the stack
1575 pointer register. Secondly, the pseudo frame pointer register can always
1576 be eliminated; it is replaced with either the stack or the real frame
1577 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1578 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1580 #define ELIMINABLE_REGS \
1581 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1582 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1583 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1584 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1585 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1586 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1587 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1589 /* Define the offset between two registers, one to be eliminated, and the
1590 other its replacement, at the start of a routine. */
1591 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1593 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1595 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1597 /* Special case handling of the location of arguments passed on the stack. */
1598 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1600 /* Initialize data used by insn expanders. This is called from insn_emit,
1601 once for every function before code is generated. */
1602 #define INIT_EXPANDERS arm_init_expanders ()
1604 /* Length in units of the trampoline for entering a nested function. */
1605 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : (TARGET_32BIT ? 16 : 20))
1607 /* Alignment required for a trampoline in bits. */
1608 #define TRAMPOLINE_ALIGNMENT 32
1610 /* Addressing modes, and classification of registers for them. */
1611 #define HAVE_POST_INCREMENT 1
1612 #define HAVE_PRE_INCREMENT TARGET_32BIT
1613 #define HAVE_POST_DECREMENT TARGET_32BIT
1614 #define HAVE_PRE_DECREMENT TARGET_32BIT
1615 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1616 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1617 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1618 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1620 enum arm_auto_incmodes
1628 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \
1629 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code))
1630 #define USE_LOAD_POST_INCREMENT(mode) \
1631 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC)
1632 #define USE_LOAD_PRE_INCREMENT(mode) \
1633 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC)
1634 #define USE_LOAD_POST_DECREMENT(mode) \
1635 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC)
1636 #define USE_LOAD_PRE_DECREMENT(mode) \
1637 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC)
1639 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode)
1640 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode)
1641 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
1642 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1644 /* Macros to check register numbers against specific register classes. */
1646 /* These assume that REGNO is a hard or pseudo reg number.
1647 They give nonzero only if REGNO is a hard reg of the suitable class
1648 or a pseudo reg currently allocated to a suitable hard reg. */
1649 #define TEST_REGNO(R, TEST, VALUE) \
1651 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE)))
1653 /* Don't allow the pc to be used. */
1654 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1655 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1656 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1657 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1659 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1660 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1661 || (GET_MODE_SIZE (MODE) >= 4 \
1662 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1664 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1666 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1667 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1669 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1670 For Thumb, we cannot use SP + reg, so reject SP. */
1671 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1672 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1674 /* For ARM code, we don't care about the mode, but for Thumb, the index
1675 must be suitable for use in a QImode load. */
1676 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1677 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1678 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1680 /* Maximum number of registers that can appear in a valid memory address.
1681 Shifts in addresses can't be by a register. */
1682 #define MAX_REGS_PER_ADDRESS 2
1684 /* Recognize any constant value that is a valid address. */
1685 /* XXX We can address any constant, eventually... */
1686 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1687 #define CONSTANT_ADDRESS_P(X) \
1688 (GET_CODE (X) == SYMBOL_REF \
1689 && (CONSTANT_POOL_ADDRESS_P (X) \
1690 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1692 /* True if SYMBOL + OFFSET constants must refer to something within
1693 SYMBOL's section. */
1694 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1696 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1697 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1698 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1701 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1702 #define SUBTARGET_NAME_ENCODING_LENGTHS
1705 /* This is a C fragment for the inside of a switch statement.
1706 Each case label should return the number of characters to
1707 be stripped from the start of a function's name, if that
1708 name starts with the indicated character. */
1709 #define ARM_NAME_ENCODING_LENGTHS \
1710 case '*': return 1; \
1711 SUBTARGET_NAME_ENCODING_LENGTHS
1713 /* This is how to output a reference to a user-level label named NAME.
1714 `assemble_name' uses this. */
1715 #undef ASM_OUTPUT_LABELREF
1716 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1717 arm_asm_output_labelref (FILE, NAME)
1719 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1720 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1721 if (TARGET_THUMB2) \
1722 thumb2_asm_output_opcode (STREAM);
1724 /* The EABI specifies that constructors should go in .init_array.
1725 Other targets use .ctors for compatibility. */
1726 #ifndef ARM_EABI_CTORS_SECTION_OP
1727 #define ARM_EABI_CTORS_SECTION_OP \
1728 "\t.section\t.init_array,\"aw\",%init_array"
1730 #ifndef ARM_EABI_DTORS_SECTION_OP
1731 #define ARM_EABI_DTORS_SECTION_OP \
1732 "\t.section\t.fini_array,\"aw\",%fini_array"
1734 #define ARM_CTORS_SECTION_OP \
1735 "\t.section\t.ctors,\"aw\",%progbits"
1736 #define ARM_DTORS_SECTION_OP \
1737 "\t.section\t.dtors,\"aw\",%progbits"
1739 /* Define CTORS_SECTION_ASM_OP. */
1740 #undef CTORS_SECTION_ASM_OP
1741 #undef DTORS_SECTION_ASM_OP
1743 # define CTORS_SECTION_ASM_OP \
1744 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1745 # define DTORS_SECTION_ASM_OP \
1746 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1747 #else /* !defined (IN_LIBGCC2) */
1748 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1749 so we cannot use the definition above. */
1750 # ifdef __ARM_EABI__
1751 /* The .ctors section is not part of the EABI, so we do not define
1752 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1753 from trying to use it. We do define it when doing normal
1754 compilation, as .init_array can be used instead of .ctors. */
1755 /* There is no need to emit begin or end markers when using
1756 init_array; the dynamic linker will compute the size of the
1757 array itself based on special symbols created by the static
1758 linker. However, we do need to arrange to set up
1759 exception-handling here. */
1760 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1761 # define CTOR_LIST_END /* empty */
1762 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1763 # define DTOR_LIST_END /* empty */
1764 # else /* !defined (__ARM_EABI__) */
1765 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1766 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1767 # endif /* !defined (__ARM_EABI__) */
1768 #endif /* !defined (IN_LIBCC2) */
1770 /* True if the operating system can merge entities with vague linkage
1771 (e.g., symbols in COMDAT group) during dynamic linking. */
1772 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1773 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1776 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1778 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1779 and check its validity for a certain class.
1780 We have two alternate definitions for each of them.
1781 The usual definition accepts all pseudo regs; the other rejects
1782 them unless they have been allocated suitable hard regs.
1783 The symbol REG_OK_STRICT causes the latter definition to be used.
1784 Thumb-2 has the same restrictions as arm. */
1785 #ifndef REG_OK_STRICT
1787 #define ARM_REG_OK_FOR_BASE_P(X) \
1788 (REGNO (X) <= LAST_ARM_REGNUM \
1789 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1790 || REGNO (X) == FRAME_POINTER_REGNUM \
1791 || REGNO (X) == ARG_POINTER_REGNUM)
1793 #define ARM_REG_OK_FOR_INDEX_P(X) \
1794 ((REGNO (X) <= LAST_ARM_REGNUM \
1795 && REGNO (X) != STACK_POINTER_REGNUM) \
1796 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1797 || REGNO (X) == FRAME_POINTER_REGNUM \
1798 || REGNO (X) == ARG_POINTER_REGNUM)
1800 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1801 (REGNO (X) <= LAST_LO_REGNUM \
1802 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1803 || (GET_MODE_SIZE (MODE) >= 4 \
1804 && (REGNO (X) == STACK_POINTER_REGNUM \
1805 || (X) == hard_frame_pointer_rtx \
1806 || (X) == arg_pointer_rtx)))
1808 #define REG_STRICT_P 0
1810 #else /* REG_OK_STRICT */
1812 #define ARM_REG_OK_FOR_BASE_P(X) \
1813 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1815 #define ARM_REG_OK_FOR_INDEX_P(X) \
1816 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
1818 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1819 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1821 #define REG_STRICT_P 1
1823 #endif /* REG_OK_STRICT */
1825 /* Now define some helpers in terms of the above. */
1827 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1829 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1830 : ARM_REG_OK_FOR_BASE_P (X))
1832 /* For 16-bit Thumb, a valid index register is anything that can be used in
1833 a byte load instruction. */
1834 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
1835 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
1837 /* Nonzero if X is a hard reg that can be used as an index
1838 or if it is a pseudo reg. On the Thumb, the stack pointer
1840 #define REG_OK_FOR_INDEX_P(X) \
1842 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
1843 : ARM_REG_OK_FOR_INDEX_P (X))
1845 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1846 For Thumb, we cannot use SP + reg, so reject SP. */
1847 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1848 REG_OK_FOR_INDEX_P (X)
1850 #define ARM_BASE_REGISTER_RTX_P(X) \
1851 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X))
1853 #define ARM_INDEX_REGISTER_RTX_P(X) \
1854 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X))
1856 /* Specify the machine mode that this machine uses
1857 for the index in the tablejump instruction. */
1858 #define CASE_VECTOR_MODE Pmode
1860 #define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \
1862 && (optimize_size || flag_pic))) \
1863 && (!target_pure_code))
1866 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
1868 ? (min >= 0 && max < 512 \
1869 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
1870 : min >= -256 && max < 256 \
1871 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
1872 : min >= 0 && max < 8192 \
1873 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
1874 : min >= -4096 && max < 4096 \
1875 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
1877 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
1878 : (max >= 0x200) ? HImode \
1881 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1882 unsigned is probably best, but may break some code. */
1883 #ifndef DEFAULT_SIGNED_CHAR
1884 #define DEFAULT_SIGNED_CHAR 0
1887 /* Max number of bytes we can move from memory to memory
1888 in one reasonably fast instruction. */
1892 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
1894 /* Define if operations between registers always perform the operation
1895 on the full register even if a narrower mode is specified. */
1896 #define WORD_REGISTER_OPERATIONS 1
1898 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1899 will either zero-extend or sign-extend. The value of this macro should
1900 be the code that says which one of the two operations is implicitly
1901 done, UNKNOWN if none. */
1902 #define LOAD_EXTEND_OP(MODE) \
1903 (TARGET_THUMB ? ZERO_EXTEND : \
1904 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1905 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
1907 /* Nonzero if access to memory by bytes is slow and undesirable. */
1908 #define SLOW_BYTE_ACCESS 0
1910 /* Immediate shift counts are truncated by the output routines (or was it
1911 the assembler?). Shift counts in a register are truncated by ARM. Note
1912 that the native compiler puts too large (> 32) immediate shift counts
1913 into a register and shifts by the register, letting the ARM decide what
1914 to do instead of doing that itself. */
1915 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1916 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1917 On the arm, Y in a register is used modulo 256 for the shift. Only for
1918 rotates is modulo 32 used. */
1919 /* #define SHIFT_COUNT_TRUNCATED 1 */
1921 /* Calling from registers is a massive pain. */
1922 #define NO_FUNCTION_CSE 1
1924 /* The machine modes of pointers and functions */
1925 #define Pmode SImode
1926 #define FUNCTION_MODE Pmode
1928 #define ARM_FRAME_RTX(X) \
1929 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1930 || (X) == arg_pointer_rtx)
1932 /* Try to generate sequences that don't involve branches, we can then use
1933 conditional instructions. */
1934 #define BRANCH_COST(speed_p, predictable_p) \
1935 ((arm_branch_cost != -1) ? arm_branch_cost : \
1936 (current_tune->branch_cost (speed_p, predictable_p)))
1938 /* False if short circuit operation is preferred. */
1939 #define LOGICAL_OP_NON_SHORT_CIRCUIT \
1941 ? (TARGET_THUMB ? false : true) \
1942 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \
1943 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm))
1946 /* Position Independent Code. */
1947 /* We decide which register to use based on the compilation options and
1948 the assembler in use; this is more general than the APCS restriction of
1949 using sb (r9) all the time. */
1950 extern unsigned arm_pic_register
;
1952 /* The register number of the register used to address a table of static
1953 data addresses in memory. */
1954 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1956 /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT
1957 entries would need to handle saving and restoring it). */
1958 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC
1960 /* We can't directly access anything that contains a symbol,
1961 nor can we indirect via the constant pool. One exception is
1962 UNSPEC_TLS, which is always PIC. */
1963 #define LEGITIMATE_PIC_OPERAND_P(X) \
1964 (!(symbol_mentioned_p (X) \
1965 || label_mentioned_p (X) \
1966 || (GET_CODE (X) == SYMBOL_REF \
1967 && CONSTANT_POOL_ADDRESS_P (X) \
1968 && (symbol_mentioned_p (get_pool_constant (X)) \
1969 || label_mentioned_p (get_pool_constant (X))))) \
1970 || tls_mentioned_p (X))
1972 /* We may want to save the PIC register if it is a dedicated one. */
1973 #define PIC_REGISTER_MAY_NEED_SAVING \
1975 && !TARGET_SINGLE_PIC_BASE \
1977 && arm_pic_register != INVALID_REGNUM)
1979 /* We need to know when we are making a constant pool; this determines
1980 whether data needs to be in the GOT or can be referenced via a GOT
1982 extern int making_const_table
;
1984 /* Handle pragmas for compatibility with Intel's compilers. */
1985 /* Also abuse this to register additional C specific EABI attributes. */
1986 #define REGISTER_TARGET_PRAGMAS() do { \
1987 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
1988 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
1989 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
1990 arm_lang_object_attributes_init(); \
1991 arm_register_target_pragmas(); \
1994 /* Condition code information. */
1995 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1996 return the mode to be used for the comparison. */
1998 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2000 #define REVERSIBLE_CC_MODE(MODE) 1
2002 #define REVERSE_CONDITION(CODE,MODE) \
2003 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2004 ? reverse_condition_maybe_unordered (code) \
2005 : reverse_condition (code))
2007 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2008 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
2009 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2010 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
2012 #define CC_STATUS_INIT \
2013 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2016 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \
2017 "\t.syntax divided\n")
2020 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \
2021 "\t.thumb\n\t.syntax unified\n")
2023 /* Output a push or a pop instruction (only used when profiling).
2024 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2025 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2026 that r7 isn't used by the function profiler, so we can use it as a
2027 scratch reg. WARNING: This isn't safe in the general case! It may be
2028 sensitive to future changes in final.c:profile_function. */
2029 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2033 && (REGNO) == STATIC_CHAIN_REGNUM) \
2035 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2036 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2037 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2040 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2044 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2045 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2049 && (REGNO) == STATIC_CHAIN_REGNUM) \
2051 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2052 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2053 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2056 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2059 #define ADDR_VEC_ALIGN(JUMPTABLE) \
2060 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0)
2062 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the
2063 default alignment from elfos.h. */
2064 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
2065 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */
2067 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
2068 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \
2071 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2072 arm_declare_function_name ((STREAM), (NAME), (DECL));
2074 /* For aliases of functions we use .thumb_set instead. */
2075 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2078 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2079 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2081 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2083 fprintf (FILE, "\t.thumb_set "); \
2084 assemble_name (FILE, LABEL1); \
2085 fprintf (FILE, ","); \
2086 assemble_name (FILE, LABEL2); \
2087 fprintf (FILE, "\n"); \
2090 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2094 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2095 /* To support -falign-* switches we need to use .p2align so
2096 that alignment directives in code sections will be padded
2097 with no-op instructions, rather than zeroes. */
2098 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2101 if ((MAX_SKIP) == 0) \
2102 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2104 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2105 (int) (LOG), (int) (MAX_SKIP)); \
2109 /* Add two bytes to the length of conditionally executed Thumb-2
2110 instructions for the IT instruction. */
2111 #define ADJUST_INSN_LENGTH(insn, length) \
2112 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2115 /* Only perform branch elimination (by making instructions conditional) if
2116 we're optimizing. For Thumb-2 check if any IT instructions need
2118 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2119 if (TARGET_ARM && optimize) \
2120 arm_final_prescan_insn (INSN); \
2121 else if (TARGET_THUMB2) \
2122 thumb2_final_prescan_insn (INSN); \
2123 else if (TARGET_THUMB1) \
2124 thumb1_final_prescan_insn (INSN)
2126 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2127 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2128 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2129 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2130 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2131 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2134 /* A C expression whose value is RTL representing the value of the return
2135 address for the frame COUNT steps up from the current frame. */
2137 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2138 arm_return_addr (COUNT, FRAME)
2140 /* Mask of the bits in the PC that contain the real return address
2141 when running in 26-bit mode. */
2142 #define RETURN_ADDR_MASK26 (0x03fffffc)
2144 /* Pick up the return address upon entry to a procedure. Used for
2145 dwarf2 unwind information. This also enables the table driven
2147 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2148 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2150 /* Used to mask out junk bits from the return address, such as
2151 processor state, interrupt status, condition codes and the like. */
2152 #define MASK_RETURN_ADDR \
2153 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2154 in 26 bit mode, the condition codes must be masked out of the \
2155 return address. This does not apply to ARM6 and later processors \
2156 when running in 32 bit mode. */ \
2157 ((arm_arch4 || TARGET_THUMB) \
2158 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2159 : arm_gen_return_addr_mask ())
2162 /* Do not emit .note.GNU-stack by default. */
2163 #ifndef NEED_INDICATE_EXEC_STACK
2164 #define NEED_INDICATE_EXEC_STACK 0
2167 #define TARGET_ARM_ARCH \
2170 /* The highest Thumb instruction set version supported by the chip. */
2171 #define TARGET_ARM_ARCH_ISA_THUMB \
2172 (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0))
2174 /* Expands to an upper-case char of the target's architectural
2176 #define TARGET_ARM_ARCH_PROFILE \
2177 (arm_active_target.profile)
2179 /* Bit-field indicating what size LDREX/STREX loads/stores are available.
2180 Bit 0 for bytes, up to bit 3 for double-words. */
2181 #define TARGET_ARM_FEATURE_LDREX \
2182 ((TARGET_HAVE_LDREX ? 4 : 0) \
2183 | (TARGET_HAVE_LDREXBH ? 3 : 0) \
2184 | (TARGET_HAVE_LDREXD ? 8 : 0))
2186 /* Set as a bit mask indicating the available widths of hardware floating
2187 point types. Where bit 1 indicates 16-bit support, bit 2 indicates
2188 32-bit support, bit 3 indicates 64-bit support. */
2189 #define TARGET_ARM_FP \
2190 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \
2191 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \
2195 /* Set as a bit mask indicating the available widths of floating point
2196 types for hardware NEON floating point. This is the same as
2197 TARGET_ARM_FP without the 64-bit bit set. */
2198 #define TARGET_NEON_FP \
2199 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \
2202 /* Name of the automatic fpu-selection option. */
2203 #define FPUTYPE_AUTO "auto"
2205 /* The maximum number of parallel loads or stores we support in an ldm/stm
2207 #define MAX_LDM_STM_OPS 4
2209 extern const char *arm_rewrite_mcpu (int argc
, const char **argv
);
2210 extern const char *arm_rewrite_march (int argc
, const char **argv
);
2211 extern const char *arm_asm_auto_mfpu (int argc
, const char **argv
);
2212 #define ASM_CPU_SPEC_FUNCTIONS \
2213 { "rewrite_mcpu", arm_rewrite_mcpu }, \
2214 { "rewrite_march", arm_rewrite_march }, \
2215 { "asm_auto_mfpu", arm_asm_auto_mfpu },
2217 #define ASM_CPU_SPEC \
2218 " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \
2219 " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \
2220 " march=*:-march=%:rewrite_march(%{march=*:%*});" \
2221 " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \
2224 extern const char *arm_target_thumb_only (int argc
, const char **argv
);
2225 #define TARGET_MODE_SPEC_FUNCTIONS \
2226 { "target_mode_check", arm_target_thumb_only },
2228 /* -mcpu=native handling only makes sense with compiler running on
2230 #if defined(__arm__)
2231 extern const char *host_detect_local_cpu (int argc
, const char **argv
);
2232 #define HAVE_LOCAL_CPU_DETECT
2233 # define MCPU_MTUNE_NATIVE_FUNCTIONS \
2234 { "local_cpu_detect", host_detect_local_cpu },
2235 # define MCPU_MTUNE_NATIVE_SPECS \
2236 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \
2237 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \
2238 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
2240 # define MCPU_MTUNE_NATIVE_FUNCTIONS
2241 # define MCPU_MTUNE_NATIVE_SPECS ""
2244 const char *arm_canon_arch_option (int argc
, const char **argv
);
2246 #define CANON_ARCH_SPEC_FUNCTION \
2247 { "canon_arch", arm_canon_arch_option },
2249 const char *arm_be8_option (int argc
, const char **argv
);
2250 #define BE8_SPEC_FUNCTION \
2251 { "be8_linkopt", arm_be8_option },
2253 # define EXTRA_SPEC_FUNCTIONS \
2254 MCPU_MTUNE_NATIVE_FUNCTIONS \
2255 ASM_CPU_SPEC_FUNCTIONS \
2256 CANON_ARCH_SPEC_FUNCTION \
2257 TARGET_MODE_SPEC_FUNCTIONS \
2260 /* Automatically add -mthumb for Thumb-only targets if mode isn't specified
2261 via the configuration option --with-mode or via the command line. The
2262 function target_mode_check is called to do the check with either:
2263 - an array of -march values if any is given;
2264 - an array of -mcpu values if any is given;
2265 - an empty array. */
2266 #define TARGET_MODE_SPECS \
2267 " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}"
2269 /* Generate a canonical string to represent the architecture selected. */
2270 #define ARCH_CANONICAL_SPECS \
2271 " -march=%:canon_arch(%{mcpu=*: cpu %*} " \
2272 " %{march=*: arch %*} " \
2273 " %{mfpu=*: fpu %*} " \
2274 " %{mfloat-abi=*: abi %*}" \
2277 /* Complete set of specs for the driver. Commas separate the
2278 individual rules so that any option suppression (%<opt...)is
2279 completed before starting subsequent rules. */
2280 #define DRIVER_SELF_SPECS \
2281 MCPU_MTUNE_NATIVE_SPECS, \
2282 TARGET_MODE_SPECS, \
2283 ARCH_CANONICAL_SPECS
2285 #define TARGET_SUPPORTS_WIDE_INT 1
2287 /* For switching between functions with different target attributes. */
2288 #define SWITCHABLE_TARGET 1
2290 /* Define SECTION_ARM_PURECODE as the ARM specific section attribute
2291 representation for SHF_ARM_PURECODE in GCC. */
2292 #define SECTION_ARM_PURECODE SECTION_MACH_DEP
2294 #endif /* ! GCC_ARM_H */