1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 3, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING3. If not see
23 <http://www.gnu.org/licenses/>. */
28 #include "config/vxworks-dummy.h"
30 /* The architecture define. */
31 extern char arm_arch_name
[];
33 /* Target CPU builtins. */
34 #define TARGET_CPU_CPP_BUILTINS() \
37 /* Define __arm__ even when in thumb mode, for \
38 consistency with armcc. */ \
39 builtin_define ("__arm__"); \
40 builtin_define ("__APCS_32__"); \
42 builtin_define ("__thumb__"); \
44 builtin_define ("__thumb2__"); \
48 builtin_define ("__ARMEB__"); \
50 builtin_define ("__THUMBEB__"); \
51 if (TARGET_LITTLE_WORDS) \
52 builtin_define ("__ARMWEL__"); \
56 builtin_define ("__ARMEL__"); \
58 builtin_define ("__THUMBEL__"); \
61 if (TARGET_SOFT_FLOAT) \
62 builtin_define ("__SOFTFP__"); \
65 builtin_define ("__VFP_FP__"); \
68 builtin_define ("__ARM_NEON__"); \
70 /* Add a define for interworking. \
71 Needed when building libgcc.a. */ \
72 if (arm_cpp_interwork) \
73 builtin_define ("__THUMB_INTERWORK__"); \
75 builtin_assert ("cpu=arm"); \
76 builtin_assert ("machine=arm"); \
78 builtin_define (arm_arch_name); \
79 if (arm_arch_cirrus) \
80 builtin_define ("__MAVERICK__"); \
81 if (arm_arch_xscale) \
82 builtin_define ("__XSCALE__"); \
83 if (arm_arch_iwmmxt) \
84 builtin_define ("__IWMMXT__"); \
85 if (TARGET_AAPCS_BASED) \
86 builtin_define ("__ARM_EABI__"); \
89 /* The various ARM cores. */
92 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
94 #include "arm-cores.def"
96 /* Used to indicate that no processor has been specified. */
102 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
104 #include "arm-cores.def"
109 /* The processor for which instructions should be scheduled. */
110 extern enum processor_type arm_tune
;
112 typedef enum arm_cond_code
114 ARM_EQ
= 0, ARM_NE
, ARM_CS
, ARM_CC
, ARM_MI
, ARM_PL
, ARM_VS
, ARM_VC
,
115 ARM_HI
, ARM_LS
, ARM_GE
, ARM_LT
, ARM_GT
, ARM_LE
, ARM_AL
, ARM_NV
119 extern arm_cc arm_current_cc
;
121 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
123 extern int arm_target_label
;
124 extern int arm_ccfsm_state
;
125 extern GTY(()) rtx arm_target_insn
;
126 /* Define the information needed to generate branch insns. This is
127 stored from the compare operation. */
128 extern GTY(()) rtx arm_compare_op0
;
129 extern GTY(()) rtx arm_compare_op1
;
130 /* The label of the current constant pool. */
131 extern rtx pool_vector_label
;
132 /* Set to 1 when a return insn is output, this means that the epilogue
134 extern int return_used_this_function
;
135 /* Used to produce AOF syntax assembler. */
136 extern GTY(()) rtx aof_pic_label
;
138 /* Just in case configure has failed to define anything. */
139 #ifndef TARGET_CPU_DEFAULT
140 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
145 #define CPP_SPEC "%(subtarget_cpp_spec) \
146 %{msoft-float:%{mhard-float: \
147 %e-msoft-float and -mhard_float may not be used together}} \
148 %{mbig-endian:%{mlittle-endian: \
149 %e-mbig-endian and -mlittle-endian may not be used together}}"
155 /* This macro defines names of additional specifications to put in the specs
156 that can be used in various specifications like CC1_SPEC. Its definition
157 is an initializer with a subgrouping for each command option.
159 Each subgrouping contains a string constant, that defines the
160 specification name, and a string constant that used by the GCC driver
163 Do not define this macro if it does not need to do anything. */
164 #define EXTRA_SPECS \
165 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
166 SUBTARGET_EXTRA_SPECS
168 #ifndef SUBTARGET_EXTRA_SPECS
169 #define SUBTARGET_EXTRA_SPECS
172 #ifndef SUBTARGET_CPP_SPEC
173 #define SUBTARGET_CPP_SPEC ""
176 /* Run-time Target Specification. */
177 #ifndef TARGET_VERSION
178 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
181 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
182 /* Use hardware floating point instructions. */
183 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
184 /* Use hardware floating point calling convention. */
185 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
186 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
187 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
188 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
189 #define TARGET_IWMMXT (arm_arch_iwmmxt)
190 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
191 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
192 #define TARGET_ARM (! TARGET_THUMB)
193 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
194 #define TARGET_BACKTRACE (leaf_function_p () \
195 ? TARGET_TPCS_LEAF_FRAME \
197 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
198 #define TARGET_AAPCS_BASED \
199 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
201 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
202 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
204 /* Only 16-bit thumb code. */
205 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
206 /* Arm or Thumb-2 32-bit code. */
207 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
208 /* 32-bit Thumb-2 code. */
209 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
211 /* The following two macros concern the ability to execute coprocessor
212 instructions for VFPv3 or NEON. TARGET_VFP3 is currently only ever
213 tested when we know we are generating for VFP hardware; we need to
214 be more careful with TARGET_NEON as noted below. */
216 /* FPU is VFPv3 (with twice the number of D registers). Setting the FPU to
217 Neon automatically enables VFPv3 too. */
218 #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \
219 && (arm_fpu_arch == FPUTYPE_VFP3 \
220 || arm_fpu_arch == FPUTYPE_NEON))
221 /* FPU supports Neon instructions. The setting of this macro gets
222 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
223 and TARGET_HARD_FLOAT to ensure that NEON instructions are
225 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
226 && arm_fp_model == ARM_FP_MODEL_VFP \
227 && arm_fpu_arch == FPUTYPE_NEON)
229 /* "DSP" multiply instructions, eg. SMULxy. */
230 #define TARGET_DSP_MULTIPLY \
231 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
232 /* Integer SIMD instructions, and extend-accumulate instructions. */
233 #define TARGET_INT_SIMD \
234 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
236 /* We could use unified syntax for arm mode, but for now we just use it
238 #define TARGET_UNIFIED_ASM TARGET_THUMB2
241 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
242 then TARGET_AAPCS_BASED must be true -- but the converse does not
243 hold. TARGET_BPABI implies the use of the BPABI runtime library,
244 etc., in addition to just the AAPCS calling conventions. */
246 #define TARGET_BPABI false
249 /* Support for a compile-time default CPU, et cetera. The rules are:
250 --with-arch is ignored if -march or -mcpu are specified.
251 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
253 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
255 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
257 --with-fpu is ignored if -mfpu is specified.
258 --with-abi is ignored is -mabi is specified. */
259 #define OPTION_DEFAULT_SPECS \
260 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
261 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
262 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
264 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
265 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
266 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
267 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
269 /* Which floating point model to use. */
272 ARM_FP_MODEL_UNKNOWN
,
273 /* FPA model (Hardware or software). */
275 /* Cirrus Maverick floating point model. */
276 ARM_FP_MODEL_MAVERICK
,
277 /* VFP floating point model. */
281 extern enum arm_fp_model arm_fp_model
;
283 /* Which floating point hardware is available. Also update
284 fp_model_for_fpu in arm.c when adding entries to this list. */
287 /* No FP hardware. */
289 /* Full FPA support. */
291 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
293 /* Emulated FPA hardware, Issue 3 emulator. */
295 /* Cirrus Maverick floating point co-processor. */
305 /* Recast the floating point class to be the floating point attribute. */
306 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
308 /* What type of floating point to tune for */
309 extern enum fputype arm_fpu_tune
;
311 /* What type of floating point instructions are available */
312 extern enum fputype arm_fpu_arch
;
317 ARM_FLOAT_ABI_SOFTFP
,
321 extern enum float_abi_type arm_float_abi
;
323 #ifndef TARGET_DEFAULT_FLOAT_ABI
324 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
327 /* Which ABI to use. */
337 extern enum arm_abi_type arm_abi
;
339 #ifndef ARM_DEFAULT_ABI
340 #define ARM_DEFAULT_ABI ARM_ABI_APCS
343 /* Which thread pointer access sequence to use. */
350 extern enum arm_tp_type target_thread_pointer
;
352 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
353 extern int arm_arch3m
;
355 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
356 extern int arm_arch4
;
358 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
359 extern int arm_arch4t
;
361 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
362 extern int arm_arch5
;
364 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
365 extern int arm_arch5e
;
367 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
368 extern int arm_arch6
;
370 /* Nonzero if instructions not present in the 'M' profile can be used. */
371 extern int arm_arch_notm
;
373 /* Nonzero if this chip can benefit from load scheduling. */
374 extern int arm_ld_sched
;
376 /* Nonzero if generating thumb code. */
377 extern int thumb_code
;
379 /* Nonzero if this chip is a StrongARM. */
380 extern int arm_tune_strongarm
;
382 /* Nonzero if this chip is a Cirrus variant. */
383 extern int arm_arch_cirrus
;
385 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
386 extern int arm_arch_iwmmxt
;
388 /* Nonzero if this chip is an XScale. */
389 extern int arm_arch_xscale
;
391 /* Nonzero if tuning for XScale. */
392 extern int arm_tune_xscale
;
394 /* Nonzero if tuning for stores via the write buffer. */
395 extern int arm_tune_wbuf
;
397 /* Nonzero if we should define __THUMB_INTERWORK__ in the
399 XXX This is a bit of a hack, it's intended to help work around
400 problems in GLD which doesn't understand that armv5t code is
401 interworking clean. */
402 extern int arm_cpp_interwork
;
404 /* Nonzero if chip supports Thumb 2. */
405 extern int arm_arch_thumb2
;
407 /* Nonzero if chip supports integer division instruction. */
408 extern int arm_arch_hwdiv
;
410 #ifndef TARGET_DEFAULT
411 #define TARGET_DEFAULT (MASK_APCS_FRAME)
414 /* The frame pointer register used in gcc has nothing to do with debugging;
415 that is controlled by the APCS-FRAME option. */
416 #define CAN_DEBUG_WITHOUT_FP
418 #define OVERRIDE_OPTIONS arm_override_options ()
420 /* Nonzero if PIC code requires explicit qualifiers to generate
421 PLT and GOT relocs rather than the assembler doing so implicitly.
422 Subtargets can override these if required. */
423 #ifndef NEED_GOT_RELOC
424 #define NEED_GOT_RELOC 0
426 #ifndef NEED_PLT_RELOC
427 #define NEED_PLT_RELOC 0
430 /* Nonzero if we need to refer to the GOT with a PC-relative
431 offset. In other words, generate
433 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
437 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
439 The default is true, which matches NetBSD. Subtargets can
440 override this if required. */
445 /* Target machine storage Layout. */
448 /* Define this macro if it is advisable to hold scalars in registers
449 in a wider mode than that declared by the program. In such cases,
450 the value is constrained to be within the bounds of the declared
451 type, but kept valid in the wider mode. The signedness of the
452 extension may differ from that of the type. */
454 /* It is far faster to zero extend chars than to sign extend them */
456 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
457 if (GET_MODE_CLASS (MODE) == MODE_INT \
458 && GET_MODE_SIZE (MODE) < 4) \
460 if (MODE == QImode) \
462 else if (MODE == HImode) \
467 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
468 if ((GET_MODE_CLASS (MODE) == MODE_INT \
469 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
470 && GET_MODE_SIZE (MODE) < 4) \
473 /* Define this if most significant bit is lowest numbered
474 in instructions that operate on numbered bit-fields. */
475 #define BITS_BIG_ENDIAN 0
477 /* Define this if most significant byte of a word is the lowest numbered.
478 Most ARM processors are run in little endian mode, so that is the default.
479 If you want to have it run-time selectable, change the definition in a
480 cover file to be TARGET_BIG_ENDIAN. */
481 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
483 /* Define this if most significant word of a multiword number is the lowest
485 This is always false, even when in big-endian mode. */
486 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
488 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
489 on processor pre-defineds when compiling libgcc2.c. */
490 #if defined(__ARMEB__) && !defined(__ARMWEL__)
491 #define LIBGCC2_WORDS_BIG_ENDIAN 1
493 #define LIBGCC2_WORDS_BIG_ENDIAN 0
496 /* Define this if most significant word of doubles is the lowest numbered.
497 The rules are different based on whether or not we use FPA-format,
498 VFP-format or some other floating point co-processor's format doubles. */
499 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
501 #define UNITS_PER_WORD 4
503 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
504 registers when autovectorizing for Neon, at least until multiple vector
505 widths are supported properly by the middle-end. */
506 #define UNITS_PER_SIMD_WORD \
507 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
509 /* True if natural alignment is used for doubleword types. */
510 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
512 #define DOUBLEWORD_ALIGNMENT 64
514 #define PARM_BOUNDARY 32
516 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
518 #define PREFERRED_STACK_BOUNDARY \
519 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
521 #define FUNCTION_BOUNDARY 32
523 /* The lowest bit is used to indicate Thumb-mode functions, so the
524 vbit must go into the delta field of pointers to member
526 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
528 #define EMPTY_FIELD_BOUNDARY 32
530 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
532 /* XXX Blah -- this macro is used directly by libobjc. Since it
533 supports no vector modes, cut out the complexity and fall back
534 on BIGGEST_FIELD_ALIGNMENT. */
535 #ifdef IN_TARGET_LIBS
536 #define BIGGEST_FIELD_ALIGNMENT 64
539 /* Make strings word-aligned so strcpy from constants will be faster. */
540 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
542 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
543 ((TREE_CODE (EXP) == STRING_CST \
545 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
546 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
548 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
549 value set in previous versions of this toolchain was 8, which produces more
550 compact structures. The command line option -mstructure_size_boundary=<n>
551 can be used to change this value. For compatibility with the ARM SDK
552 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
553 0020D) page 2-20 says "Structures are aligned on word boundaries".
554 The AAPCS specifies a value of 8. */
555 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
556 extern int arm_structure_size_boundary
;
558 /* This is the value used to initialize arm_structure_size_boundary. If a
559 particular arm target wants to change the default value it should change
560 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
561 for an example of this. */
562 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
563 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
566 /* Nonzero if move instructions will actually fail to work
567 when given unaligned data. */
568 #define STRICT_ALIGNMENT 1
570 /* wchar_t is unsigned under the AAPCS. */
572 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
574 #define WCHAR_TYPE_SIZE BITS_PER_WORD
578 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
582 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
585 /* AAPCS requires that structure alignment is affected by bitfields. */
586 #ifndef PCC_BITFIELD_TYPE_MATTERS
587 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
591 /* Standard register usage. */
593 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
594 (S - saved over call).
596 r0 * argument word/integer result
599 r4-r8 S register variable
600 r9 S (rfp) register variable (real frame pointer)
602 r10 F S (sl) stack limit (used by -mapcs-stack-check)
603 r11 F S (fp) argument pointer
604 r12 (ip) temp workspace
605 r13 F S (sp) lower end of current stack frame
606 r14 (lr) link address/workspace
607 r15 F (pc) program counter
609 f0 floating point result
610 f1-f3 floating point scratch
612 f4-f7 S floating point variable
614 cc This is NOT a real register, but is used internally
615 to represent things that use or set the condition
617 sfp This isn't either. It is used during rtl generation
618 since the offset between the frame pointer and the
619 auto's isn't known until after register allocation.
620 afp Nor this, we only need this because of non-local
621 goto. Without it fp appears to be used and the
622 elimination code won't get rid of sfp. It tracks
623 fp exactly at all times.
625 *: See CONDITIONAL_REGISTER_USAGE */
628 mvf0 Cirrus floating point result
629 mvf1-mvf3 Cirrus floating point scratch
630 mvf4-mvf15 S Cirrus floating point variable. */
632 /* s0-s15 VFP scratch (aka d0-d7).
633 s16-s31 S VFP variable (aka d8-d15).
634 vfpcc Not a real register. Represents the VFP condition
637 /* The stack backtrace structure is as follows:
638 fp points to here: | save code pointer | [fp]
639 | return link value | [fp, #-4]
640 | return sp value | [fp, #-8]
641 | return fp value | [fp, #-12]
642 [| saved r10 value |]
653 [| saved f7 value |] three words
654 [| saved f6 value |] three words
655 [| saved f5 value |] three words
656 [| saved f4 value |] three words
657 r0-r3 are not normally saved in a C function. */
659 /* 1 for registers that have pervasive standard uses
660 and are not available for the register allocator. */
661 #define FIXED_REGISTERS \
683 /* 1 for registers not available across function calls.
684 These must include the FIXED_REGISTERS and also any
685 registers that can be used without being saved.
686 The latter must include the registers where values are returned
687 and the register where structure-value addresses are passed.
688 Aside from that, you can include as many other registers as you like.
689 The CC is not preserved over function calls on the ARM 6, so it is
690 easier to assume this for all. SFP is preserved, since FP is. */
691 #define CALL_USED_REGISTERS \
713 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
714 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
717 #define CONDITIONAL_REGISTER_USAGE \
721 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
723 for (regno = FIRST_FPA_REGNUM; \
724 regno <= LAST_FPA_REGNUM; ++regno) \
725 fixed_regs[regno] = call_used_regs[regno] = 1; \
728 if (TARGET_THUMB && optimize_size) \
730 /* When optimizing for size, it's better not to use \
731 the HI regs, because of the overhead of stacking \
733 /* ??? Is this still true for thumb2? */ \
734 for (regno = FIRST_HI_REGNUM; \
735 regno <= LAST_HI_REGNUM; ++regno) \
736 fixed_regs[regno] = call_used_regs[regno] = 1; \
739 /* The link register can be clobbered by any branch insn, \
740 but we have no way to track that at present, so mark \
741 it as unavailable. */ \
743 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
745 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
747 if (TARGET_MAVERICK) \
749 for (regno = FIRST_FPA_REGNUM; \
750 regno <= LAST_FPA_REGNUM; ++ regno) \
751 fixed_regs[regno] = call_used_regs[regno] = 1; \
752 for (regno = FIRST_CIRRUS_FP_REGNUM; \
753 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
755 fixed_regs[regno] = 0; \
756 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
761 /* VFPv3 registers are disabled when earlier VFP \
762 versions are selected due to the definition of \
763 LAST_VFP_REGNUM. */ \
764 for (regno = FIRST_VFP_REGNUM; \
765 regno <= LAST_VFP_REGNUM; ++ regno) \
767 fixed_regs[regno] = 0; \
768 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
769 || regno >= FIRST_VFP_REGNUM + 32; \
774 if (TARGET_REALLY_IWMMXT) \
776 regno = FIRST_IWMMXT_GR_REGNUM; \
777 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
778 and wCG1 as call-preserved registers. The 2002/11/21 \
779 revision changed this so that all wCG registers are \
780 scratch registers. */ \
781 for (regno = FIRST_IWMMXT_GR_REGNUM; \
782 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
783 fixed_regs[regno] = 0; \
784 /* The XScale ABI has wR0 - wR9 as scratch registers, \
785 the rest as call-preserved registers. */ \
786 for (regno = FIRST_IWMMXT_REGNUM; \
787 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
789 fixed_regs[regno] = 0; \
790 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
794 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
796 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
797 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
799 else if (TARGET_APCS_STACK) \
801 fixed_regs[10] = 1; \
802 call_used_regs[10] = 1; \
804 /* -mcaller-super-interworking reserves r11 for calls to \
805 _interwork_r11_call_via_rN(). Making the register global \
806 is an easy way of ensuring that it remains valid for all \
808 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
809 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
811 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
812 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
813 if (TARGET_CALLER_INTERWORKING) \
814 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
816 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
819 /* These are a couple of extensions to the formats accepted
821 %@ prints out ASM_COMMENT_START
822 %r prints out REGISTER_PREFIX reg_names[arg] */
823 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
825 fputs (ASM_COMMENT_START, FILE); \
829 fputs (REGISTER_PREFIX, FILE); \
830 fputs (reg_names [va_arg (ARGS, int)], FILE); \
833 /* Round X up to the nearest word. */
834 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
836 /* Convert fron bytes to ints. */
837 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
839 /* The number of (integer) registers required to hold a quantity of type MODE.
840 Also used for VFP registers. */
841 #define ARM_NUM_REGS(MODE) \
842 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
844 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
845 #define ARM_NUM_REGS2(MODE, TYPE) \
846 ARM_NUM_INTS ((MODE) == BLKmode ? \
847 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
849 /* The number of (integer) argument register available. */
850 #define NUM_ARG_REGS 4
852 /* Return the register number of the N'th (integer) argument. */
853 #define ARG_REGISTER(N) (N - 1)
855 /* Specify the registers used for certain standard purposes.
856 The values of these macros are register numbers. */
858 /* The number of the last argument register. */
859 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
861 /* The numbers of the Thumb register ranges. */
862 #define FIRST_LO_REGNUM 0
863 #define LAST_LO_REGNUM 7
864 #define FIRST_HI_REGNUM 8
865 #define LAST_HI_REGNUM 11
867 #ifndef TARGET_UNWIND_INFO
868 /* We use sjlj exceptions for backwards compatibility. */
869 #define MUST_USE_SJLJ_EXCEPTIONS 1
872 /* We can generate DWARF2 Unwind info, even though we don't use it. */
873 #define DWARF2_UNWIND_INFO 1
875 /* Use r0 and r1 to pass exception handling information. */
876 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
878 /* The register that holds the return address in exception handlers. */
879 #define ARM_EH_STACKADJ_REGNUM 2
880 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
882 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
883 as an invisible last argument (possible since varargs don't exist in
884 Pascal), so the following is not true. */
885 #define STATIC_CHAIN_REGNUM 12
887 /* Define this to be where the real frame pointer is if it is not possible to
888 work out the offset between the frame pointer and the automatic variables
889 until after register allocation has taken place. FRAME_POINTER_REGNUM
890 should point to a special register that we will make sure is eliminated.
892 For the Thumb we have another problem. The TPCS defines the frame pointer
893 as r11, and GCC believes that it is always possible to use the frame pointer
894 as base register for addressing purposes. (See comments in
895 find_reloads_address()). But - the Thumb does not allow high registers,
896 including r11, to be used as base address registers. Hence our problem.
898 The solution used here, and in the old thumb port is to use r7 instead of
899 r11 as the hard frame pointer and to have special code to generate
900 backtrace structures on the stack (if required to do so via a command line
901 option) using r11. This is the only 'user visible' use of r11 as a frame
903 #define ARM_HARD_FRAME_POINTER_REGNUM 11
904 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
906 #define HARD_FRAME_POINTER_REGNUM \
908 ? ARM_HARD_FRAME_POINTER_REGNUM \
909 : THUMB_HARD_FRAME_POINTER_REGNUM)
911 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
913 /* Register to use for pushing function arguments. */
914 #define STACK_POINTER_REGNUM SP_REGNUM
916 /* ARM floating pointer registers. */
917 #define FIRST_FPA_REGNUM 16
918 #define LAST_FPA_REGNUM 23
919 #define IS_FPA_REGNUM(REGNUM) \
920 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
922 #define FIRST_IWMMXT_GR_REGNUM 43
923 #define LAST_IWMMXT_GR_REGNUM 46
924 #define FIRST_IWMMXT_REGNUM 47
925 #define LAST_IWMMXT_REGNUM 62
926 #define IS_IWMMXT_REGNUM(REGNUM) \
927 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
928 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
929 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
931 /* Base register for access to local variables of the function. */
932 #define FRAME_POINTER_REGNUM 25
934 /* Base register for access to arguments of the function. */
935 #define ARG_POINTER_REGNUM 26
937 #define FIRST_CIRRUS_FP_REGNUM 27
938 #define LAST_CIRRUS_FP_REGNUM 42
939 #define IS_CIRRUS_REGNUM(REGNUM) \
940 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
942 #define FIRST_VFP_REGNUM 63
943 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
944 #define LAST_VFP_REGNUM \
945 (TARGET_VFP3 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
947 #define IS_VFP_REGNUM(REGNUM) \
948 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
950 /* VFP registers are split into two types: those defined by VFP versions < 3
951 have D registers overlaid on consecutive pairs of S registers. VFP version 3
952 defines 16 new D registers (d16-d31) which, for simplicity and correctness
953 in various parts of the backend, we implement as "fake" single-precision
954 registers (which would be S32-S63, but cannot be used in that way). The
955 following macros define these ranges of registers. */
956 #define LAST_LO_VFP_REGNUM 94
957 #define FIRST_HI_VFP_REGNUM 95
958 #define LAST_HI_VFP_REGNUM 126
960 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
961 ((REGNUM) <= LAST_LO_VFP_REGNUM)
963 /* DFmode values are only valid in even register pairs. */
964 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
965 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
967 /* Neon Quad values must start at a multiple of four registers. */
968 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
969 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
971 /* Neon structures of vectors must be in even register pairs and there
972 must be enough registers available. Because of various patterns
973 requiring quad registers, we require them to start at a multiple of
975 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
976 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
977 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
979 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
980 /* + 16 Cirrus registers take us up to 43. */
981 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
982 /* VFP (VFP3) adds 32 (64) + 1 more. */
983 #define FIRST_PSEUDO_REGISTER 128
985 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
987 /* Value should be nonzero if functions must have frame pointers.
988 Zero means the frame pointer need not be set up (and parms may be accessed
989 via the stack pointer) in functions that seem suitable.
990 If we have to have a frame pointer we might as well make use of it.
991 APCS says that the frame pointer does not need to be pushed in leaf
992 functions, or simple tail call functions. */
994 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
995 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
998 #define FRAME_POINTER_REQUIRED \
999 (current_function_has_nonlocal_label \
1000 || SUBTARGET_FRAME_POINTER_REQUIRED \
1001 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1003 /* Return number of consecutive hard regs needed starting at reg REGNO
1004 to hold something of mode MODE.
1005 This is ordinarily the length in words of a value of mode MODE
1006 but can be less for certain modes in special long registers.
1008 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1010 #define HARD_REGNO_NREGS(REGNO, MODE) \
1012 && REGNO >= FIRST_FPA_REGNUM \
1013 && REGNO != FRAME_POINTER_REGNUM \
1014 && REGNO != ARG_POINTER_REGNUM) \
1015 && !IS_VFP_REGNUM (REGNO) \
1016 ? 1 : ARM_NUM_REGS (MODE))
1018 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1019 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1020 arm_hard_regno_mode_ok ((REGNO), (MODE))
1022 /* Value is 1 if it is a good idea to tie two pseudo registers
1023 when one has mode MODE1 and one has mode MODE2.
1024 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1025 for any hard reg, then this must be 0 for correct output. */
1026 #define MODES_TIEABLE_P(MODE1, MODE2) \
1027 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1029 #define VALID_IWMMXT_REG_MODE(MODE) \
1030 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1032 /* Modes valid for Neon D registers. */
1033 #define VALID_NEON_DREG_MODE(MODE) \
1034 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1035 || (MODE) == V2SFmode || (MODE) == DImode)
1037 /* Modes valid for Neon Q registers. */
1038 #define VALID_NEON_QREG_MODE(MODE) \
1039 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1040 || (MODE) == V4SFmode || (MODE) == V2DImode)
1042 /* Structure modes valid for Neon registers. */
1043 #define VALID_NEON_STRUCT_MODE(MODE) \
1044 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1045 || (MODE) == CImode || (MODE) == XImode)
1047 /* The order in which register should be allocated. It is good to use ip
1048 since no saving is required (though calls clobber it) and it never contains
1049 function parameters. It is quite good to use lr since other calls may
1050 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1051 least likely to contain a function parameter; in addition results are
1053 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1054 then D8-D15. The reason for doing this is to attempt to reduce register
1055 pressure when both single- and double-precision registers are used in a
1058 #define REG_ALLOC_ORDER \
1060 3, 2, 1, 0, 12, 14, 4, 5, \
1061 6, 7, 8, 10, 9, 11, 13, 15, \
1062 16, 17, 18, 19, 20, 21, 22, 23, \
1063 27, 28, 29, 30, 31, 32, 33, 34, \
1064 35, 36, 37, 38, 39, 40, 41, 42, \
1065 43, 44, 45, 46, 47, 48, 49, 50, \
1066 51, 52, 53, 54, 55, 56, 57, 58, \
1069 95, 96, 97, 98, 99, 100, 101, 102, \
1070 103, 104, 105, 106, 107, 108, 109, 110, \
1071 111, 112, 113, 114, 115, 116, 117, 118, \
1072 119, 120, 121, 122, 123, 124, 125, 126, \
1073 78, 77, 76, 75, 74, 73, 72, 71, \
1074 70, 69, 68, 67, 66, 65, 64, 63, \
1075 79, 80, 81, 82, 83, 84, 85, 86, \
1076 87, 88, 89, 90, 91, 92, 93, 94, \
1080 /* Interrupt functions can only use registers that have already been
1081 saved by the prologue, even if they would normally be
1083 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1084 (! IS_INTERRUPT (cfun->machine->func_type) || \
1085 df_regs_ever_live_p (DST))
1087 /* Register and constant classes. */
1089 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1090 Now that the Thumb is involved it has become more complicated. */
1113 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1115 /* Give names of register classes as strings for dump file. */
1116 #define REG_CLASS_NAMES \
1137 /* Define which registers fit in which classes.
1138 This is an initializer for a vector of HARD_REG_SET
1139 of length N_REG_CLASSES. */
1140 #define REG_CLASS_CONTENTS \
1142 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1143 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1144 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1145 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1146 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1147 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1148 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1149 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1150 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1151 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1152 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1153 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1154 { 0x0000FF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1155 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1156 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1157 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1158 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1161 /* Any of the VFP register classes. */
1162 #define IS_VFP_CLASS(X) \
1163 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1164 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1166 /* The same information, inverted:
1167 Return the class number of the smallest class containing
1168 reg number REGNO. This could be a conditional expression
1169 or could index an array. */
1170 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1172 /* FPA registers can't do subreg as all values are reformatted to internal
1173 precision. VFP registers may only be accessed in the mode they
1175 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1176 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1177 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1178 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1181 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1182 using r0-r4 for function arguments, r7 for the stack frame and don't
1183 have enough left over to do doubleword arithmetic. */
1184 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1185 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1186 || (CLASS) == CC_REG)
1188 /* The class value for index registers, and the one for base regs. */
1189 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1190 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1192 /* For the Thumb the high registers cannot be used as base registers
1193 when addressing quantities in QI or HI mode; if we don't know the
1194 mode, then we must be conservative. */
1195 #define MODE_BASE_REG_CLASS(MODE) \
1196 (TARGET_32BIT ? GENERAL_REGS : \
1197 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1199 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1200 instead of BASE_REGS. */
1201 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1203 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1204 registers explicitly used in the rtl to be used as spill registers
1205 but prevents the compiler from extending the lifetime of these
1207 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1209 /* Given an rtx X being reloaded into a reg required to be
1210 in class CLASS, return the class of reg to actually use.
1211 In general this is just CLASS, but for the Thumb core registers and
1212 immediate constants we prefer a LO_REGS class or a subset. */
1213 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1214 (TARGET_ARM ? (CLASS) : \
1215 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1216 || (CLASS) == NO_REGS ? LO_REGS : (CLASS)))
1218 /* Must leave BASE_REGS reloads alone */
1219 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1220 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1221 ? ((true_regnum (X) == -1 ? LO_REGS \
1222 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1226 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1227 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1228 ? ((true_regnum (X) == -1 ? LO_REGS \
1229 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1233 /* Return the register class of a scratch register needed to copy IN into
1234 or out of a register in CLASS in MODE. If it can be done directly,
1235 NO_REGS is returned. */
1236 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1237 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1238 ((TARGET_VFP && TARGET_HARD_FLOAT \
1239 && IS_VFP_CLASS (CLASS)) \
1240 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1241 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1242 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1244 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1245 ? GENERAL_REGS : NO_REGS) \
1246 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1248 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1249 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1250 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1251 ((TARGET_VFP && TARGET_HARD_FLOAT \
1252 && IS_VFP_CLASS (CLASS)) \
1253 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1254 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1255 coproc_secondary_reload_class (MODE, X, TRUE) : \
1256 /* Cannot load constants into Cirrus registers. */ \
1257 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1258 && (CLASS) == CIRRUS_REGS \
1259 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1262 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1263 && CONSTANT_P (X)) \
1265 (((MODE) == HImode && ! arm_arch4 \
1266 && (GET_CODE (X) == MEM \
1267 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1268 && true_regnum (X) == -1))) \
1269 ? GENERAL_REGS : NO_REGS) \
1270 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1272 /* Try a machine-dependent way of reloading an illegitimate address
1273 operand. If we find one, push the reload and jump to WIN. This
1274 macro is used in only one place: `find_reloads_address' in reload.c.
1276 For the ARM, we wish to handle large displacements off a base
1277 register by splitting the addend across a MOV and the mem insn.
1278 This can cut the number of reloads needed. */
1279 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1282 if (GET_CODE (X) == PLUS \
1283 && GET_CODE (XEXP (X, 0)) == REG \
1284 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1285 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1286 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1288 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1289 HOST_WIDE_INT low, high; \
1291 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1292 low = ((val & 0xf) ^ 0x8) - 0x8; \
1293 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1294 /* Need to be careful, -256 is not a valid offset. */ \
1295 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1296 else if (MODE == SImode \
1297 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1298 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1299 /* Need to be careful, -4096 is not a valid offset. */ \
1300 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1301 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1302 /* Need to be careful, -256 is not a valid offset. */ \
1303 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1304 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1305 && TARGET_HARD_FLOAT && TARGET_FPA) \
1306 /* Need to be careful, -1024 is not a valid offset. */ \
1307 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1311 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1312 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1313 - (unsigned HOST_WIDE_INT) 0x80000000); \
1314 /* Check for overflow or zero */ \
1315 if (low == 0 || high == 0 || (high + low != val)) \
1318 /* Reload the high part into a base reg; leave the low part \
1320 X = gen_rtx_PLUS (GET_MODE (X), \
1321 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1324 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1325 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1326 VOIDmode, 0, 0, OPNUM, TYPE); \
1332 /* XXX If an HImode FP+large_offset address is converted to an HImode
1333 SP+large_offset address, then reload won't know how to fix it. It sees
1334 only that SP isn't valid for HImode, and so reloads the SP into an index
1335 register, but the resulting address is still invalid because the offset
1336 is too big. We fix it here instead by reloading the entire address. */
1337 /* We could probably achieve better results by defining PROMOTE_MODE to help
1338 cope with the variances between the Thumb's signed and unsigned byte and
1339 halfword load instructions. */
1340 /* ??? This should be safe for thumb2, but we may be able to do better. */
1341 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1343 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1351 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1353 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1355 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1357 /* Return the maximum number of consecutive registers
1358 needed to represent mode MODE in a register of class CLASS.
1359 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1360 #define CLASS_MAX_NREGS(CLASS, MODE) \
1361 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1363 /* If defined, gives a class of registers that cannot be used as the
1364 operand of a SUBREG that changes the mode of the object illegally. */
1366 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1367 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1369 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1370 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1371 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \
1372 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \
1373 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1374 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1375 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1376 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1377 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1380 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1382 /* Stack layout; function entry, exit and calling. */
1384 /* Define this if pushing a word on the stack
1385 makes the stack pointer a smaller address. */
1386 #define STACK_GROWS_DOWNWARD 1
1388 /* Define this to nonzero if the nominal address of the stack frame
1389 is at the high-address end of the local variables;
1390 that is, each additional local variable allocated
1391 goes at a more negative offset in the frame. */
1392 #define FRAME_GROWS_DOWNWARD 1
1394 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1395 When present, it is one word in size, and sits at the top of the frame,
1396 between the soft frame pointer and either r7 or r11.
1398 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1399 and only then if some outgoing arguments are passed on the stack. It would
1400 be tempting to also check whether the stack arguments are passed by indirect
1401 calls, but there seems to be no reason in principle why a post-reload pass
1402 couldn't convert a direct call into an indirect one. */
1403 #define CALLER_INTERWORKING_SLOT_SIZE \
1404 (TARGET_CALLER_INTERWORKING \
1405 && current_function_outgoing_args_size != 0 \
1406 ? UNITS_PER_WORD : 0)
1408 /* Offset within stack frame to start allocating local variables at.
1409 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1410 first local allocated. Otherwise, it is the offset to the BEGINNING
1411 of the first local allocated. */
1412 #define STARTING_FRAME_OFFSET 0
1414 /* If we generate an insn to push BYTES bytes,
1415 this says how many the stack pointer really advances by. */
1416 /* The push insns do not do this rounding implicitly.
1417 So don't define this. */
1418 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1420 /* Define this if the maximum size of all the outgoing args is to be
1421 accumulated and pushed during the prologue. The amount can be
1422 found in the variable current_function_outgoing_args_size. */
1423 #define ACCUMULATE_OUTGOING_ARGS 1
1425 /* Offset of first parameter from the argument pointer register value. */
1426 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1428 /* Value is the number of byte of arguments automatically
1429 popped when returning from a subroutine call.
1430 FUNDECL is the declaration node of the function (as a tree),
1431 FUNTYPE is the data type of the function (as a tree),
1432 or for a library call it is an identifier node for the subroutine name.
1433 SIZE is the number of bytes of arguments passed on the stack.
1435 On the ARM, the caller does not pop any of its arguments that were passed
1437 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1439 /* Define how to find the value returned by a library function
1440 assuming the value has mode MODE. */
1441 #define LIBCALL_VALUE(MODE) \
1442 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1443 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1444 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1445 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1446 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1447 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1448 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1449 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1450 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1452 /* Define how to find the value returned by a function.
1453 VALTYPE is the data type of the value (as a tree).
1454 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1455 otherwise, FUNC is 0. */
1456 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1457 arm_function_value (VALTYPE, FUNC);
1459 /* 1 if N is a possible register number for a function value.
1460 On the ARM, only r0 and f0 can return results. */
1461 /* On a Cirrus chip, mvf0 can return results. */
1462 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1463 ((REGNO) == ARG_REGISTER (1) \
1464 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1465 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1466 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1467 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1468 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1470 /* Amount of memory needed for an untyped call to save all possible return
1472 #define APPLY_RESULT_SIZE arm_apply_result_size()
1474 /* How large values are returned */
1475 /* A C expression which can inhibit the returning of certain function values
1476 in registers, based on the type of value. */
1477 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1479 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1480 values must be in memory. On the ARM, they need only do so if larger
1481 than a word, or if they contain elements offset from zero in the struct. */
1482 #define DEFAULT_PCC_STRUCT_RETURN 0
1484 /* These bits describe the different types of function supported
1485 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1486 normal function and an interworked function, for example. Knowing the
1487 type of a function is important for determining its prologue and
1489 Note value 7 is currently unassigned. Also note that the interrupt
1490 function types all have bit 2 set, so that they can be tested for easily.
1491 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1492 machine_function structure is initialized (to zero) func_type will
1493 default to unknown. This will force the first use of arm_current_func_type
1494 to call arm_compute_func_type. */
1495 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1496 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1497 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1498 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1499 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1500 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1502 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1504 /* In addition functions can have several type modifiers,
1505 outlined by these bit masks: */
1506 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1507 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1508 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1509 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1510 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1512 /* Some macros to test these flags. */
1513 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1514 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1515 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1516 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1517 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1518 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1521 /* Structure used to hold the function stack frame layout. Offsets are
1522 relative to the stack pointer on function entry. Positive offsets are
1523 in the direction of stack growth.
1524 Only soft_frame is used in thumb mode. */
1526 typedef struct arm_stack_offsets
GTY(())
1528 int saved_args
; /* ARG_POINTER_REGNUM. */
1529 int frame
; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1531 int soft_frame
; /* FRAME_POINTER_REGNUM. */
1532 int locals_base
; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1533 int outgoing_args
; /* STACK_POINTER_REGNUM. */
1537 /* A C structure for machine-specific, per-function data.
1538 This is added to the cfun structure. */
1539 typedef struct machine_function
GTY(())
1541 /* Additional stack adjustment in __builtin_eh_throw. */
1542 rtx eh_epilogue_sp_ofs
;
1543 /* Records if LR has to be saved for far jumps. */
1545 /* Records if ARG_POINTER was ever live. */
1546 int arg_pointer_live
;
1547 /* Records if the save of LR has been eliminated. */
1548 int lr_save_eliminated
;
1549 /* The size of the stack frame. Only valid after reload. */
1550 arm_stack_offsets stack_offsets
;
1551 /* Records the type of the current function. */
1552 unsigned long func_type
;
1553 /* Record if the function has a variable argument list. */
1554 int uses_anonymous_args
;
1555 /* Records if sibcalls are blocked because an argument
1556 register is needed to preserve stack alignment. */
1557 int sibcall_blocked
;
1558 /* The PIC register for this function. This might be a pseudo. */
1560 /* Labels for per-function Thumb call-via stubs. One per potential calling
1561 register. We can never call via LR or PC. We can call via SP if a
1562 trampoline happens to be on the top of the stack. */
1567 /* As in the machine_function, a global set of call-via labels, for code
1568 that is in text_section. */
1569 extern GTY(()) rtx thumb_call_via_label
[14];
1571 /* A C type for declaring a variable that is used as the first argument of
1572 `FUNCTION_ARG' and other related values. For some target machines, the
1573 type `int' suffices and can hold the number of bytes of argument so far. */
1576 /* This is the number of registers of arguments scanned so far. */
1578 /* This is the number of iWMMXt register arguments scanned so far. */
1585 /* Define where to put the arguments to a function.
1586 Value is zero to push the argument on the stack,
1587 or a hard register in which to store the argument.
1589 MODE is the argument's machine mode.
1590 TYPE is the data type of the argument (as a tree).
1591 This is null for libcalls where that information may
1593 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1594 the preceding args and about the function being called.
1595 NAMED is nonzero if this argument is a named parameter
1596 (otherwise it is an extra parameter matching an ellipsis).
1598 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1599 other arguments are passed on the stack. If (NAMED == 0) (which happens
1600 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1601 defined), say it is passed in the stack (function_prologue will
1602 indeed make it pass in the stack if necessary). */
1603 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1604 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1606 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1607 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1609 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1610 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1612 /* For AAPCS, padding should never be below the argument. For other ABIs,
1613 * mimic the default. */
1614 #define PAD_VARARGS_DOWN \
1615 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1617 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1618 for a call to a function whose data type is FNTYPE.
1619 For a library call, FNTYPE is 0.
1620 On the ARM, the offset starts at 0. */
1621 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1622 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1624 /* Update the data in CUM to advance over an argument
1625 of mode MODE and data type TYPE.
1626 (TYPE is null for libcalls where that information may not be available.) */
1627 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1629 if (arm_vector_mode_supported_p (MODE) \
1630 && (CUM).named_count > (CUM).nargs \
1631 && TARGET_IWMMXT_ABI) \
1632 (CUM).iwmmxt_nregs += 1; \
1634 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1636 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1637 argument with the specified mode and type. If it is not defined,
1638 `PARM_BOUNDARY' is used for all arguments. */
1639 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1640 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1641 ? DOUBLEWORD_ALIGNMENT \
1644 /* 1 if N is a possible register number for function argument passing.
1645 On the ARM, r0-r3 are used to pass args. */
1646 #define FUNCTION_ARG_REGNO_P(REGNO) \
1647 (IN_RANGE ((REGNO), 0, 3) \
1648 || (TARGET_IWMMXT_ABI \
1649 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1652 /* If your target environment doesn't prefix user functions with an
1653 underscore, you may wish to re-define this to prevent any conflicts.
1654 e.g. AOF may prefix mcount with an underscore. */
1655 #ifndef ARM_MCOUNT_NAME
1656 #define ARM_MCOUNT_NAME "*mcount"
1659 /* Call the function profiler with a given profile label. The Acorn
1660 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1661 On the ARM the full profile code will look like:
1670 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1671 will output the .text section.
1673 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1674 ``prof'' doesn't seem to mind about this!
1676 Note - this version of the code is designed to work in both ARM and
1678 #ifndef ARM_FUNCTION_PROFILER
1679 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1684 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1685 IP_REGNUM, LR_REGNUM); \
1686 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1687 fputc ('\n', STREAM); \
1688 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1689 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1690 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1694 #ifdef THUMB_FUNCTION_PROFILER
1695 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1697 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1699 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1701 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1702 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1705 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1706 the stack pointer does not matter. The value is tested only in
1707 functions that have frame pointers.
1708 No definition is equivalent to always zero.
1710 On the ARM, the function epilogue recovers the stack pointer from the
1712 #define EXIT_IGNORE_STACK 1
1714 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1716 /* Determine if the epilogue should be output as RTL.
1717 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1718 /* This is disabled for Thumb-2 because it will confuse the
1719 conditional insn counter. */
1720 #define USE_RETURN_INSN(ISCOND) \
1721 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1723 /* Definitions for register eliminations.
1725 This is an array of structures. Each structure initializes one pair
1726 of eliminable registers. The "from" register number is given first,
1727 followed by "to". Eliminations of the same "from" register are listed
1728 in order of preference.
1730 We have two registers that can be eliminated on the ARM. First, the
1731 arg pointer register can often be eliminated in favor of the stack
1732 pointer register. Secondly, the pseudo frame pointer register can always
1733 be eliminated; it is replaced with either the stack or the real frame
1734 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1735 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1737 #define ELIMINABLE_REGS \
1738 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1739 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1740 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1741 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1742 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1743 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1744 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1746 /* Given FROM and TO register numbers, say whether this elimination is
1747 allowed. Frame pointer elimination is automatically handled.
1749 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1750 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1751 pointer, we must eliminate FRAME_POINTER_REGNUM into
1752 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1753 ARG_POINTER_REGNUM. */
1754 #define CAN_ELIMINATE(FROM, TO) \
1755 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1756 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1757 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1758 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1761 /* Define the offset between two registers, one to be eliminated, and the
1762 other its replacement, at the start of a routine. */
1763 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1765 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1767 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1769 /* Special case handling of the location of arguments passed on the stack. */
1770 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1772 /* Initialize data used by insn expanders. This is called from insn_emit,
1773 once for every function before code is generated. */
1774 #define INIT_EXPANDERS arm_init_expanders ()
1776 /* Output assembler code for a block containing the constant parts
1777 of a trampoline, leaving space for the variable parts.
1779 On the ARM, (if r8 is the static chain regnum, and remembering that
1780 referencing pc adds an offset of 8) the trampoline looks like:
1783 .word static chain value
1784 .word function's address
1785 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1786 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1788 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1789 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1790 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1791 PC_REGNUM, PC_REGNUM); \
1792 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1793 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1796 /* The Thumb-2 trampoline is similar to the arm implementation.
1797 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1798 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1800 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1801 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1802 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1803 PC_REGNUM, PC_REGNUM); \
1804 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1805 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1808 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1810 ASM_OUTPUT_ALIGN(FILE, 2); \
1811 fprintf (FILE, "\t.code\t16\n"); \
1812 fprintf (FILE, ".Ltrampoline_start:\n"); \
1813 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1814 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1816 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1817 STATIC_CHAIN_REGNUM); \
1818 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1820 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1822 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1824 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1825 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1828 #define TRAMPOLINE_TEMPLATE(FILE) \
1830 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1831 else if (TARGET_THUMB2) \
1832 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1834 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1836 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1838 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1841 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1842 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1845 /* Length in units of the trampoline for entering a nested function. */
1846 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1848 /* Alignment required for a trampoline in bits. */
1849 #define TRAMPOLINE_ALIGNMENT 32
1852 /* Emit RTL insns to initialize the variable parts of a trampoline.
1853 FNADDR is an RTX for the address of the function's pure code.
1854 CXT is an RTX for the static chain value for the function. */
1855 #ifndef INITIALIZE_TRAMPOLINE
1856 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1858 emit_move_insn (gen_rtx_MEM (SImode, \
1859 plus_constant (TRAMP, \
1860 TARGET_32BIT ? 8 : 12)), \
1862 emit_move_insn (gen_rtx_MEM (SImode, \
1863 plus_constant (TRAMP, \
1864 TARGET_32BIT ? 12 : 16)), \
1866 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1867 0, VOIDmode, 2, TRAMP, Pmode, \
1868 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1873 /* Addressing modes, and classification of registers for them. */
1874 #define HAVE_POST_INCREMENT 1
1875 #define HAVE_PRE_INCREMENT TARGET_32BIT
1876 #define HAVE_POST_DECREMENT TARGET_32BIT
1877 #define HAVE_PRE_DECREMENT TARGET_32BIT
1878 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1879 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1880 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1881 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1883 /* Macros to check register numbers against specific register classes. */
1885 /* These assume that REGNO is a hard or pseudo reg number.
1886 They give nonzero only if REGNO is a hard reg of the suitable class
1887 or a pseudo reg currently allocated to a suitable hard reg.
1888 Since they use reg_renumber, they are safe only once reg_renumber
1889 has been allocated, which happens in local-alloc.c. */
1890 #define TEST_REGNO(R, TEST, VALUE) \
1891 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1893 /* Don't allow the pc to be used. */
1894 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1895 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1896 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1897 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1899 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1900 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1901 || (GET_MODE_SIZE (MODE) >= 4 \
1902 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1904 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1906 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1907 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1909 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1910 For Thumb, we can not use SP + reg, so reject SP. */
1911 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1912 REGNO_OK_FOR_INDEX_P (X)
1914 /* For ARM code, we don't care about the mode, but for Thumb, the index
1915 must be suitable for use in a QImode load. */
1916 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1917 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1919 /* Maximum number of registers that can appear in a valid memory address.
1920 Shifts in addresses can't be by a register. */
1921 #define MAX_REGS_PER_ADDRESS 2
1923 /* Recognize any constant value that is a valid address. */
1924 /* XXX We can address any constant, eventually... */
1926 #ifdef AOF_ASSEMBLER
1928 #define CONSTANT_ADDRESS_P(X) \
1929 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1933 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1934 #define CONSTANT_ADDRESS_P(X) \
1935 (GET_CODE (X) == SYMBOL_REF \
1936 && (CONSTANT_POOL_ADDRESS_P (X) \
1937 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1939 #endif /* AOF_ASSEMBLER */
1941 /* True if SYMBOL + OFFSET constants must refer to something within
1942 SYMBOL's section. */
1943 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1945 /* Nonzero if the constant value X is a legitimate general operand.
1946 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1948 On the ARM, allow any integer (invalid ones are removed later by insn
1949 patterns), nice doubles and symbol_refs which refer to the function's
1952 When generating pic allow anything. */
1953 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1955 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1956 ( GET_CODE (X) == CONST_INT \
1957 || GET_CODE (X) == CONST_DOUBLE \
1958 || CONSTANT_ADDRESS_P (X) \
1961 #define LEGITIMATE_CONSTANT_P(X) \
1962 (!arm_cannot_force_const_mem (X) \
1963 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1964 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1966 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1967 #define SUBTARGET_NAME_ENCODING_LENGTHS
1970 /* This is a C fragment for the inside of a switch statement.
1971 Each case label should return the number of characters to
1972 be stripped from the start of a function's name, if that
1973 name starts with the indicated character. */
1974 #define ARM_NAME_ENCODING_LENGTHS \
1975 case '*': return 1; \
1976 SUBTARGET_NAME_ENCODING_LENGTHS
1978 /* This is how to output a reference to a user-level label named NAME.
1979 `assemble_name' uses this. */
1980 #undef ASM_OUTPUT_LABELREF
1981 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1982 arm_asm_output_labelref (FILE, NAME)
1984 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1985 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1986 if (TARGET_THUMB2) \
1987 thumb2_asm_output_opcode (STREAM);
1989 /* The EABI specifies that constructors should go in .init_array.
1990 Other targets use .ctors for compatibility. */
1991 #ifndef ARM_EABI_CTORS_SECTION_OP
1992 #define ARM_EABI_CTORS_SECTION_OP \
1993 "\t.section\t.init_array,\"aw\",%init_array"
1995 #ifndef ARM_EABI_DTORS_SECTION_OP
1996 #define ARM_EABI_DTORS_SECTION_OP \
1997 "\t.section\t.fini_array,\"aw\",%fini_array"
1999 #define ARM_CTORS_SECTION_OP \
2000 "\t.section\t.ctors,\"aw\",%progbits"
2001 #define ARM_DTORS_SECTION_OP \
2002 "\t.section\t.dtors,\"aw\",%progbits"
2004 /* Define CTORS_SECTION_ASM_OP. */
2005 #undef CTORS_SECTION_ASM_OP
2006 #undef DTORS_SECTION_ASM_OP
2008 # define CTORS_SECTION_ASM_OP \
2009 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2010 # define DTORS_SECTION_ASM_OP \
2011 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2012 #else /* !defined (IN_LIBGCC2) */
2013 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2014 so we cannot use the definition above. */
2015 # ifdef __ARM_EABI__
2016 /* The .ctors section is not part of the EABI, so we do not define
2017 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2018 from trying to use it. We do define it when doing normal
2019 compilation, as .init_array can be used instead of .ctors. */
2020 /* There is no need to emit begin or end markers when using
2021 init_array; the dynamic linker will compute the size of the
2022 array itself based on special symbols created by the static
2023 linker. However, we do need to arrange to set up
2024 exception-handling here. */
2025 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2026 # define CTOR_LIST_END /* empty */
2027 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2028 # define DTOR_LIST_END /* empty */
2029 # else /* !defined (__ARM_EABI__) */
2030 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2031 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2032 # endif /* !defined (__ARM_EABI__) */
2033 #endif /* !defined (IN_LIBCC2) */
2035 /* True if the operating system can merge entities with vague linkage
2036 (e.g., symbols in COMDAT group) during dynamic linking. */
2037 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2038 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2041 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2043 #ifdef TARGET_UNWIND_INFO
2044 #define ARM_EABI_UNWIND_TABLES \
2045 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2047 #define ARM_EABI_UNWIND_TABLES 0
2050 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2051 and check its validity for a certain class.
2052 We have two alternate definitions for each of them.
2053 The usual definition accepts all pseudo regs; the other rejects
2054 them unless they have been allocated suitable hard regs.
2055 The symbol REG_OK_STRICT causes the latter definition to be used.
2056 Thumb-2 has the same restrictions as arm. */
2057 #ifndef REG_OK_STRICT
2059 #define ARM_REG_OK_FOR_BASE_P(X) \
2060 (REGNO (X) <= LAST_ARM_REGNUM \
2061 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2062 || REGNO (X) == FRAME_POINTER_REGNUM \
2063 || REGNO (X) == ARG_POINTER_REGNUM)
2065 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2066 (REGNO (X) <= LAST_LO_REGNUM \
2067 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2068 || (GET_MODE_SIZE (MODE) >= 4 \
2069 && (REGNO (X) == STACK_POINTER_REGNUM \
2070 || (X) == hard_frame_pointer_rtx \
2071 || (X) == arg_pointer_rtx)))
2073 #define REG_STRICT_P 0
2075 #else /* REG_OK_STRICT */
2077 #define ARM_REG_OK_FOR_BASE_P(X) \
2078 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2080 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2081 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2083 #define REG_STRICT_P 1
2085 #endif /* REG_OK_STRICT */
2087 /* Now define some helpers in terms of the above. */
2089 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2091 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2092 : ARM_REG_OK_FOR_BASE_P (X))
2094 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2096 /* For 16-bit Thumb, a valid index register is anything that can be used in
2097 a byte load instruction. */
2098 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2099 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2101 /* Nonzero if X is a hard reg that can be used as an index
2102 or if it is a pseudo reg. On the Thumb, the stack pointer
2104 #define REG_OK_FOR_INDEX_P(X) \
2106 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2107 : ARM_REG_OK_FOR_INDEX_P (X))
2109 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2110 For Thumb, we can not use SP + reg, so reject SP. */
2111 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2112 REG_OK_FOR_INDEX_P (X)
2114 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2115 that is a valid memory address for an instruction.
2116 The MODE argument is the machine mode for the MEM expression
2117 that wants to use this address. */
2119 #define ARM_BASE_REGISTER_RTX_P(X) \
2120 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2122 #define ARM_INDEX_REGISTER_RTX_P(X) \
2123 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2125 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2127 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2131 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2133 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2137 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2139 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2143 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2145 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2146 else if (TARGET_THUMB2) \
2147 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2148 else /* if (TARGET_THUMB1) */ \
2149 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2152 /* Try machine-dependent ways of modifying an illegitimate address
2153 to be legitimate. If we find one, return the new, valid address. */
2154 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2156 X = arm_legitimize_address (X, OLDX, MODE); \
2159 /* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2160 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2164 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2166 X = thumb_legitimize_address (X, OLDX, MODE); \
2169 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2172 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2173 else if (TARGET_THUMB2) \
2174 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2176 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2178 if (memory_address_p (MODE, X)) \
2182 /* Go to LABEL if ADDR (a legitimate address expression)
2183 has an effect that depends on the machine mode it is used for. */
2184 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2186 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2187 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2191 /* Nothing helpful to do for the Thumb */
2192 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2194 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2197 /* Specify the machine mode that this machine uses
2198 for the index in the tablejump instruction. */
2199 #define CASE_VECTOR_MODE Pmode
2201 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2203 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2204 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2205 : (max >= 0x200) ? HImode \
2208 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2209 unsigned is probably best, but may break some code. */
2210 #ifndef DEFAULT_SIGNED_CHAR
2211 #define DEFAULT_SIGNED_CHAR 0
2214 /* Max number of bytes we can move from memory to memory
2215 in one reasonably fast instruction. */
2219 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2221 /* Define if operations between registers always perform the operation
2222 on the full register even if a narrower mode is specified. */
2223 #define WORD_REGISTER_OPERATIONS
2225 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2226 will either zero-extend or sign-extend. The value of this macro should
2227 be the code that says which one of the two operations is implicitly
2228 done, UNKNOWN if none. */
2229 #define LOAD_EXTEND_OP(MODE) \
2230 (TARGET_THUMB ? ZERO_EXTEND : \
2231 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2232 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2234 /* Nonzero if access to memory by bytes is slow and undesirable. */
2235 #define SLOW_BYTE_ACCESS 0
2237 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2239 /* Immediate shift counts are truncated by the output routines (or was it
2240 the assembler?). Shift counts in a register are truncated by ARM. Note
2241 that the native compiler puts too large (> 32) immediate shift counts
2242 into a register and shifts by the register, letting the ARM decide what
2243 to do instead of doing that itself. */
2244 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2245 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2246 On the arm, Y in a register is used modulo 256 for the shift. Only for
2247 rotates is modulo 32 used. */
2248 /* #define SHIFT_COUNT_TRUNCATED 1 */
2250 /* All integers have the same format so truncation is easy. */
2251 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2253 /* Calling from registers is a massive pain. */
2254 #define NO_FUNCTION_CSE 1
2256 /* The machine modes of pointers and functions */
2257 #define Pmode SImode
2258 #define FUNCTION_MODE Pmode
2260 #define ARM_FRAME_RTX(X) \
2261 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2262 || (X) == arg_pointer_rtx)
2264 /* Moves to and from memory are quite expensive */
2265 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2266 (TARGET_32BIT ? 10 : \
2267 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2268 * (CLASS == LO_REGS ? 1 : 2)))
2270 /* Try to generate sequences that don't involve branches, we can then use
2271 conditional instructions */
2272 #define BRANCH_COST \
2273 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2275 /* Position Independent Code. */
2276 /* We decide which register to use based on the compilation options and
2277 the assembler in use; this is more general than the APCS restriction of
2278 using sb (r9) all the time. */
2279 extern unsigned arm_pic_register
;
2281 /* The register number of the register used to address a table of static
2282 data addresses in memory. */
2283 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2285 /* We can't directly access anything that contains a symbol,
2286 nor can we indirect via the constant pool. One exception is
2287 UNSPEC_TLS, which is always PIC. */
2288 #define LEGITIMATE_PIC_OPERAND_P(X) \
2289 (!(symbol_mentioned_p (X) \
2290 || label_mentioned_p (X) \
2291 || (GET_CODE (X) == SYMBOL_REF \
2292 && CONSTANT_POOL_ADDRESS_P (X) \
2293 && (symbol_mentioned_p (get_pool_constant (X)) \
2294 || label_mentioned_p (get_pool_constant (X))))) \
2295 || tls_mentioned_p (X))
2297 /* We need to know when we are making a constant pool; this determines
2298 whether data needs to be in the GOT or can be referenced via a GOT
2300 extern int making_const_table
;
2302 /* Handle pragmas for compatibility with Intel's compilers. */
2303 #define REGISTER_TARGET_PRAGMAS() do { \
2304 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2305 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2306 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2309 /* Condition code information. */
2310 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2311 return the mode to be used for the comparison. */
2313 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2315 #define REVERSIBLE_CC_MODE(MODE) 1
2317 #define REVERSE_CONDITION(CODE,MODE) \
2318 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2319 ? reverse_condition_maybe_unordered (code) \
2320 : reverse_condition (code))
2322 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2325 if (GET_CODE (OP1) == CONST_INT \
2326 && ! (const_ok_for_arm (INTVAL (OP1)) \
2327 || (const_ok_for_arm (- INTVAL (OP1))))) \
2329 rtx const_op = OP1; \
2330 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2337 /* The arm5 clz instruction returns 32. */
2338 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2341 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2342 TARGET_THUMB2 ? "\t.thumb\n" : "")
2344 /* Output a push or a pop instruction (only used when profiling). */
2345 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2349 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2350 STACK_POINTER_REGNUM, REGNO); \
2352 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2356 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2360 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2361 STACK_POINTER_REGNUM, REGNO); \
2363 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2366 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2367 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2369 /* This is how to output a label which precedes a jumptable. Since
2370 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2371 #undef ASM_OUTPUT_CASE_LABEL
2372 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2375 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2376 ASM_OUTPUT_ALIGN (FILE, 2); \
2377 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2381 /* Make sure subsequent insns are aligned after a TBB. */
2382 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2385 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2386 ASM_OUTPUT_ALIGN (FILE, 1); \
2390 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2395 if (is_called_in_ARM_mode (DECL) \
2396 || (TARGET_THUMB1 && current_function_is_thunk)) \
2397 fprintf (STREAM, "\t.code 32\n") ; \
2398 else if (TARGET_THUMB1) \
2399 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2401 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2403 if (TARGET_POKE_FUNCTION_NAME) \
2404 arm_poke_function_name (STREAM, (const char *) NAME); \
2408 /* For aliases of functions we use .thumb_set instead. */
2409 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2412 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2413 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2415 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2417 fprintf (FILE, "\t.thumb_set "); \
2418 assemble_name (FILE, LABEL1); \
2419 fprintf (FILE, ","); \
2420 assemble_name (FILE, LABEL2); \
2421 fprintf (FILE, "\n"); \
2424 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2428 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2429 /* To support -falign-* switches we need to use .p2align so
2430 that alignment directives in code sections will be padded
2431 with no-op instructions, rather than zeroes. */
2432 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2435 if ((MAX_SKIP) == 0) \
2436 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2438 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2439 (int) (LOG), (int) (MAX_SKIP)); \
2443 /* Add two bytes to the length of conditionally executed Thumb-2
2444 instructions for the IT instruction. */
2445 #define ADJUST_INSN_LENGTH(insn, length) \
2446 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2449 /* Only perform branch elimination (by making instructions conditional) if
2450 we're optimizing. For Thumb-2 check if any IT instructions need
2452 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2453 if (TARGET_ARM && optimize) \
2454 arm_final_prescan_insn (INSN); \
2455 else if (TARGET_THUMB2) \
2456 thumb2_final_prescan_insn (INSN); \
2457 else if (TARGET_THUMB1) \
2458 thumb1_final_prescan_insn (INSN)
2460 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2461 (CODE == '@' || CODE == '|' || CODE == '.' \
2462 || CODE == '(' || CODE == ')' || CODE == '#' \
2463 || (TARGET_32BIT && (CODE == '?')) \
2464 || (TARGET_THUMB2 && (CODE == '!')) \
2465 || (TARGET_THUMB && (CODE == '_')))
2467 /* Output an operand of an instruction. */
2468 #define PRINT_OPERAND(STREAM, X, CODE) \
2469 arm_print_operand (STREAM, X, CODE)
2471 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2472 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2473 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2474 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2475 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2476 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2479 /* Output the address of an operand. */
2480 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2482 int is_minus = GET_CODE (X) == MINUS; \
2484 if (GET_CODE (X) == REG) \
2485 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2486 else if (GET_CODE (X) == PLUS || is_minus) \
2488 rtx base = XEXP (X, 0); \
2489 rtx index = XEXP (X, 1); \
2490 HOST_WIDE_INT offset = 0; \
2491 if (GET_CODE (base) != REG) \
2493 /* Ensure that BASE is a register. */ \
2494 /* (one of them must be). */ \
2499 switch (GET_CODE (index)) \
2502 offset = INTVAL (index); \
2505 asm_fprintf (STREAM, "[%r, #%wd]", \
2506 REGNO (base), offset); \
2510 asm_fprintf (STREAM, "[%r, %s%r]", \
2511 REGNO (base), is_minus ? "-" : "", \
2521 asm_fprintf (STREAM, "[%r, %s%r", \
2522 REGNO (base), is_minus ? "-" : "", \
2523 REGNO (XEXP (index, 0))); \
2524 arm_print_operand (STREAM, index, 'S'); \
2525 fputs ("]", STREAM); \
2530 gcc_unreachable (); \
2533 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2534 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2536 extern enum machine_mode output_memory_reference_mode; \
2538 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2540 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2541 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2542 REGNO (XEXP (X, 0)), \
2543 GET_CODE (X) == PRE_DEC ? "-" : "", \
2544 GET_MODE_SIZE (output_memory_reference_mode)); \
2546 asm_fprintf (STREAM, "[%r], #%s%d", \
2547 REGNO (XEXP (X, 0)), \
2548 GET_CODE (X) == POST_DEC ? "-" : "", \
2549 GET_MODE_SIZE (output_memory_reference_mode)); \
2551 else if (GET_CODE (X) == PRE_MODIFY) \
2553 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2554 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2555 asm_fprintf (STREAM, "#%wd]!", \
2556 INTVAL (XEXP (XEXP (X, 1), 1))); \
2558 asm_fprintf (STREAM, "%r]!", \
2559 REGNO (XEXP (XEXP (X, 1), 1))); \
2561 else if (GET_CODE (X) == POST_MODIFY) \
2563 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2564 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2565 asm_fprintf (STREAM, "#%wd", \
2566 INTVAL (XEXP (XEXP (X, 1), 1))); \
2568 asm_fprintf (STREAM, "%r", \
2569 REGNO (XEXP (XEXP (X, 1), 1))); \
2571 else output_addr_const (STREAM, X); \
2574 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2576 if (GET_CODE (X) == REG) \
2577 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2578 else if (GET_CODE (X) == POST_INC) \
2579 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2580 else if (GET_CODE (X) == PLUS) \
2582 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2583 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2584 asm_fprintf (STREAM, "[%r, #%wd]", \
2585 REGNO (XEXP (X, 0)), \
2586 INTVAL (XEXP (X, 1))); \
2588 asm_fprintf (STREAM, "[%r, %r]", \
2589 REGNO (XEXP (X, 0)), \
2590 REGNO (XEXP (X, 1))); \
2593 output_addr_const (STREAM, X); \
2596 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2598 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2600 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2602 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2603 if (arm_output_addr_const_extra (file, x) == FALSE) \
2606 /* A C expression whose value is RTL representing the value of the return
2607 address for the frame COUNT steps up from the current frame. */
2609 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2610 arm_return_addr (COUNT, FRAME)
2612 /* Mask of the bits in the PC that contain the real return address
2613 when running in 26-bit mode. */
2614 #define RETURN_ADDR_MASK26 (0x03fffffc)
2616 /* Pick up the return address upon entry to a procedure. Used for
2617 dwarf2 unwind information. This also enables the table driven
2619 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2620 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2622 /* Used to mask out junk bits from the return address, such as
2623 processor state, interrupt status, condition codes and the like. */
2624 #define MASK_RETURN_ADDR \
2625 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2626 in 26 bit mode, the condition codes must be masked out of the \
2627 return address. This does not apply to ARM6 and later processors \
2628 when running in 32 bit mode. */ \
2629 ((arm_arch4 || TARGET_THUMB) \
2630 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2631 : arm_gen_return_addr_mask ())
2634 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2635 symbolic names defined here (which would require too much duplication).
2644 ARM_BUILTIN_WAVG2BR
,
2645 ARM_BUILTIN_WAVG2HR
,
2672 ARM_BUILTIN_TMOVMSKB
,
2673 ARM_BUILTIN_TMOVMSKH
,
2674 ARM_BUILTIN_TMOVMSKW
,
2683 ARM_BUILTIN_WPACKHSS
,
2684 ARM_BUILTIN_WPACKWSS
,
2685 ARM_BUILTIN_WPACKDSS
,
2686 ARM_BUILTIN_WPACKHUS
,
2687 ARM_BUILTIN_WPACKWUS
,
2688 ARM_BUILTIN_WPACKDUS
,
2693 ARM_BUILTIN_WADDSSB
,
2694 ARM_BUILTIN_WADDSSH
,
2695 ARM_BUILTIN_WADDSSW
,
2696 ARM_BUILTIN_WADDUSB
,
2697 ARM_BUILTIN_WADDUSH
,
2698 ARM_BUILTIN_WADDUSW
,
2702 ARM_BUILTIN_WSUBSSB
,
2703 ARM_BUILTIN_WSUBSSH
,
2704 ARM_BUILTIN_WSUBSSW
,
2705 ARM_BUILTIN_WSUBUSB
,
2706 ARM_BUILTIN_WSUBUSH
,
2707 ARM_BUILTIN_WSUBUSW
,
2714 ARM_BUILTIN_WCMPEQB
,
2715 ARM_BUILTIN_WCMPEQH
,
2716 ARM_BUILTIN_WCMPEQW
,
2717 ARM_BUILTIN_WCMPGTUB
,
2718 ARM_BUILTIN_WCMPGTUH
,
2719 ARM_BUILTIN_WCMPGTUW
,
2720 ARM_BUILTIN_WCMPGTSB
,
2721 ARM_BUILTIN_WCMPGTSH
,
2722 ARM_BUILTIN_WCMPGTSW
,
2724 ARM_BUILTIN_TEXTRMSB
,
2725 ARM_BUILTIN_TEXTRMSH
,
2726 ARM_BUILTIN_TEXTRMSW
,
2727 ARM_BUILTIN_TEXTRMUB
,
2728 ARM_BUILTIN_TEXTRMUH
,
2729 ARM_BUILTIN_TEXTRMUW
,
2779 ARM_BUILTIN_WUNPCKIHB
,
2780 ARM_BUILTIN_WUNPCKIHH
,
2781 ARM_BUILTIN_WUNPCKIHW
,
2782 ARM_BUILTIN_WUNPCKILB
,
2783 ARM_BUILTIN_WUNPCKILH
,
2784 ARM_BUILTIN_WUNPCKILW
,
2786 ARM_BUILTIN_WUNPCKEHSB
,
2787 ARM_BUILTIN_WUNPCKEHSH
,
2788 ARM_BUILTIN_WUNPCKEHSW
,
2789 ARM_BUILTIN_WUNPCKEHUB
,
2790 ARM_BUILTIN_WUNPCKEHUH
,
2791 ARM_BUILTIN_WUNPCKEHUW
,
2792 ARM_BUILTIN_WUNPCKELSB
,
2793 ARM_BUILTIN_WUNPCKELSH
,
2794 ARM_BUILTIN_WUNPCKELSW
,
2795 ARM_BUILTIN_WUNPCKELUB
,
2796 ARM_BUILTIN_WUNPCKELUH
,
2797 ARM_BUILTIN_WUNPCKELUW
,
2799 ARM_BUILTIN_THREAD_POINTER
,
2801 ARM_BUILTIN_NEON_BASE
,
2803 ARM_BUILTIN_MAX
= ARM_BUILTIN_NEON_BASE
/* FIXME: Wrong! */
2806 /* Do not emit .note.GNU-stack by default. */
2807 #ifndef NEED_INDICATE_EXEC_STACK
2808 #define NEED_INDICATE_EXEC_STACK 0
2811 #endif /* ! GCC_ARM_H */