1 /* The Blackfin code generation auxiliary output file.
2 Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4 Contributed by Analog Devices.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-codes.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
41 #include "target-def.h"
43 #include "diagnostic-core.h"
48 #include "langhooks.h"
49 #include "bfin-protos.h"
51 #include "tm-constrs.h"
53 #include "basic-block.h"
54 #include "cfglayout.h"
57 #include "sel-sched.h"
58 #include "hw-doloop.h"
61 /* A C structure for machine-specific, per-function data.
62 This is added to the cfun structure. */
63 struct GTY(()) machine_function
65 /* Set if we are notified by the doloop pass that a hardware loop
67 int has_hardware_loops
;
69 /* Set if we create a memcpy pattern that uses loop registers. */
70 int has_loopreg_clobber
;
73 /* RTX for condition code flag register and RETS register */
74 extern GTY(()) rtx bfin_cc_rtx
;
75 extern GTY(()) rtx bfin_rets_rtx
;
76 rtx bfin_cc_rtx
, bfin_rets_rtx
;
78 int max_arg_registers
= 0;
80 /* Arrays used when emitting register names. */
81 const char *short_reg_names
[] = SHORT_REGISTER_NAMES
;
82 const char *high_reg_names
[] = HIGH_REGISTER_NAMES
;
83 const char *dregs_pair_names
[] = DREGS_PAIR_NAMES
;
84 const char *byte_reg_names
[] = BYTE_REGISTER_NAMES
;
86 static int arg_regs
[] = FUNCTION_ARG_REGISTERS
;
87 static int ret_regs
[] = FUNCTION_RETURN_REGISTERS
;
89 int splitting_for_sched
, splitting_loops
;
92 bfin_globalize_label (FILE *stream
, const char *name
)
94 fputs (".global ", stream
);
95 assemble_name (stream
, name
);
101 output_file_start (void)
103 FILE *file
= asm_out_file
;
106 fprintf (file
, ".file \"%s\";\n", input_filename
);
108 for (i
= 0; arg_regs
[i
] >= 0; i
++)
110 max_arg_registers
= i
; /* how many arg reg used */
113 /* Examine machine-dependent attributes of function type FUNTYPE and return its
114 type. See the definition of E_FUNKIND. */
117 funkind (const_tree funtype
)
119 tree attrs
= TYPE_ATTRIBUTES (funtype
);
120 if (lookup_attribute ("interrupt_handler", attrs
))
121 return INTERRUPT_HANDLER
;
122 else if (lookup_attribute ("exception_handler", attrs
))
123 return EXCPT_HANDLER
;
124 else if (lookup_attribute ("nmi_handler", attrs
))
130 /* Legitimize PIC addresses. If the address is already position-independent,
131 we return ORIG. Newly generated position-independent addresses go into a
132 reg. This is REG if nonzero, otherwise we allocate register(s) as
133 necessary. PICREG is the register holding the pointer to the PIC offset
137 legitimize_pic_address (rtx orig
, rtx reg
, rtx picreg
)
142 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
147 if (TARGET_ID_SHARED_LIBRARY
)
148 unspec
= UNSPEC_MOVE_PIC
;
149 else if (GET_CODE (addr
) == SYMBOL_REF
150 && SYMBOL_REF_FUNCTION_P (addr
))
151 unspec
= UNSPEC_FUNCDESC_GOT17M4
;
153 unspec
= UNSPEC_MOVE_FDPIC
;
157 gcc_assert (can_create_pseudo_p ());
158 reg
= gen_reg_rtx (Pmode
);
161 tmp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), unspec
);
162 new_rtx
= gen_const_mem (Pmode
, gen_rtx_PLUS (Pmode
, picreg
, tmp
));
164 emit_move_insn (reg
, new_rtx
);
165 if (picreg
== pic_offset_table_rtx
)
166 crtl
->uses_pic_offset_table
= 1;
170 else if (GET_CODE (addr
) == CONST
|| GET_CODE (addr
) == PLUS
)
174 if (GET_CODE (addr
) == CONST
)
176 addr
= XEXP (addr
, 0);
177 gcc_assert (GET_CODE (addr
) == PLUS
);
180 if (XEXP (addr
, 0) == picreg
)
185 gcc_assert (can_create_pseudo_p ());
186 reg
= gen_reg_rtx (Pmode
);
189 base
= legitimize_pic_address (XEXP (addr
, 0), reg
, picreg
);
190 addr
= legitimize_pic_address (XEXP (addr
, 1),
191 base
== reg
? NULL_RTX
: reg
,
194 if (GET_CODE (addr
) == CONST_INT
)
196 gcc_assert (! reload_in_progress
&& ! reload_completed
);
197 addr
= force_reg (Pmode
, addr
);
200 if (GET_CODE (addr
) == PLUS
&& CONSTANT_P (XEXP (addr
, 1)))
202 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (addr
, 0));
203 addr
= XEXP (addr
, 1);
206 return gen_rtx_PLUS (Pmode
, base
, addr
);
212 /* Stack frame layout. */
214 /* For a given REGNO, determine whether it must be saved in the function
215 prologue. IS_INTHANDLER specifies whether we're generating a normal
216 prologue or an interrupt/exception one. */
218 must_save_p (bool is_inthandler
, unsigned regno
)
220 if (D_REGNO_P (regno
))
222 bool is_eh_return_reg
= false;
223 if (crtl
->calls_eh_return
)
228 unsigned test
= EH_RETURN_DATA_REGNO (j
);
229 if (test
== INVALID_REGNUM
)
232 is_eh_return_reg
= true;
236 return (is_eh_return_reg
237 || (df_regs_ever_live_p (regno
)
238 && !fixed_regs
[regno
]
239 && (is_inthandler
|| !call_used_regs
[regno
])));
241 else if (P_REGNO_P (regno
))
243 return ((df_regs_ever_live_p (regno
)
244 && !fixed_regs
[regno
]
245 && (is_inthandler
|| !call_used_regs
[regno
]))
247 && (ENABLE_WA_05000283
|| ENABLE_WA_05000315
)
250 && regno
== PIC_OFFSET_TABLE_REGNUM
251 && (crtl
->uses_pic_offset_table
252 || (TARGET_ID_SHARED_LIBRARY
&& !current_function_is_leaf
))));
255 return ((is_inthandler
|| !call_used_regs
[regno
])
256 && (df_regs_ever_live_p (regno
)
257 || (!leaf_function_p () && call_used_regs
[regno
])));
261 /* Compute the number of DREGS to save with a push_multiple operation.
262 This could include registers that aren't modified in the function,
263 since push_multiple only takes a range of registers.
264 If IS_INTHANDLER, then everything that is live must be saved, even
265 if normally call-clobbered.
266 If CONSECUTIVE, return the number of registers we can save in one
267 instruction with a push/pop multiple instruction. */
270 n_dregs_to_save (bool is_inthandler
, bool consecutive
)
275 for (i
= REG_R7
+ 1; i
-- != REG_R0
;)
277 if (must_save_p (is_inthandler
, i
))
279 else if (consecutive
)
285 /* Like n_dregs_to_save, but compute number of PREGS to save. */
288 n_pregs_to_save (bool is_inthandler
, bool consecutive
)
293 for (i
= REG_P5
+ 1; i
-- != REG_P0
;)
294 if (must_save_p (is_inthandler
, i
))
296 else if (consecutive
)
301 /* Determine if we are going to save the frame pointer in the prologue. */
304 must_save_fp_p (void)
306 return df_regs_ever_live_p (REG_FP
);
309 /* Determine if we are going to save the RETS register. */
311 must_save_rets_p (void)
313 return df_regs_ever_live_p (REG_RETS
);
317 stack_frame_needed_p (void)
319 /* EH return puts a new return address into the frame using an
320 address relative to the frame pointer. */
321 if (crtl
->calls_eh_return
)
323 return frame_pointer_needed
;
326 /* Emit code to save registers in the prologue. SAVEALL is nonzero if we
327 must save all registers; this is used for interrupt handlers.
328 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
329 this for an interrupt (or exception) handler. */
332 expand_prologue_reg_save (rtx spreg
, int saveall
, bool is_inthandler
)
334 rtx predec1
= gen_rtx_PRE_DEC (SImode
, spreg
);
335 rtx predec
= gen_rtx_MEM (SImode
, predec1
);
336 int ndregs
= saveall
? 8 : n_dregs_to_save (is_inthandler
, false);
337 int npregs
= saveall
? 6 : n_pregs_to_save (is_inthandler
, false);
338 int ndregs_consec
= saveall
? 8 : n_dregs_to_save (is_inthandler
, true);
339 int npregs_consec
= saveall
? 6 : n_pregs_to_save (is_inthandler
, true);
341 int total_consec
= ndregs_consec
+ npregs_consec
;
344 if (saveall
|| is_inthandler
)
346 rtx insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, REG_ASTAT
));
348 RTX_FRAME_RELATED_P (insn
) = 1;
349 for (dregno
= REG_LT0
; dregno
<= REG_LB1
; dregno
++)
350 if (! current_function_is_leaf
351 || cfun
->machine
->has_hardware_loops
352 || cfun
->machine
->has_loopreg_clobber
353 || (ENABLE_WA_05000257
354 && (dregno
== REG_LC0
|| dregno
== REG_LC1
)))
356 insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, dregno
));
357 RTX_FRAME_RELATED_P (insn
) = 1;
361 if (total_consec
!= 0)
364 rtx val
= GEN_INT (-total_consec
* 4);
365 rtx pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_consec
+ 2));
367 XVECEXP (pat
, 0, 0) = gen_rtx_UNSPEC (VOIDmode
, gen_rtvec (1, val
),
368 UNSPEC_PUSH_MULTIPLE
);
369 XVECEXP (pat
, 0, total_consec
+ 1) = gen_rtx_SET (VOIDmode
, spreg
,
373 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, total_consec
+ 1)) = 1;
374 d_to_save
= ndregs_consec
;
375 dregno
= REG_R7
+ 1 - ndregs_consec
;
376 pregno
= REG_P5
+ 1 - npregs_consec
;
377 for (i
= 0; i
< total_consec
; i
++)
379 rtx memref
= gen_rtx_MEM (word_mode
,
380 gen_rtx_PLUS (Pmode
, spreg
,
381 GEN_INT (- i
* 4 - 4)));
385 subpat
= gen_rtx_SET (VOIDmode
, memref
, gen_rtx_REG (word_mode
,
391 subpat
= gen_rtx_SET (VOIDmode
, memref
, gen_rtx_REG (word_mode
,
394 XVECEXP (pat
, 0, i
+ 1) = subpat
;
395 RTX_FRAME_RELATED_P (subpat
) = 1;
397 insn
= emit_insn (pat
);
398 RTX_FRAME_RELATED_P (insn
) = 1;
401 for (dregno
= REG_R0
; ndregs
!= ndregs_consec
; dregno
++)
403 if (must_save_p (is_inthandler
, dregno
))
405 rtx insn
= emit_move_insn (predec
, gen_rtx_REG (word_mode
, dregno
));
406 RTX_FRAME_RELATED_P (insn
) = 1;
410 for (pregno
= REG_P0
; npregs
!= npregs_consec
; pregno
++)
412 if (must_save_p (is_inthandler
, pregno
))
414 rtx insn
= emit_move_insn (predec
, gen_rtx_REG (word_mode
, pregno
));
415 RTX_FRAME_RELATED_P (insn
) = 1;
419 for (i
= REG_P7
+ 1; i
< REG_CC
; i
++)
422 && (df_regs_ever_live_p (i
)
423 || (!leaf_function_p () && call_used_regs
[i
]))))
426 if (i
== REG_A0
|| i
== REG_A1
)
427 insn
= emit_move_insn (gen_rtx_MEM (PDImode
, predec1
),
428 gen_rtx_REG (PDImode
, i
));
430 insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, i
));
431 RTX_FRAME_RELATED_P (insn
) = 1;
435 /* Emit code to restore registers in the epilogue. SAVEALL is nonzero if we
436 must save all registers; this is used for interrupt handlers.
437 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
438 this for an interrupt (or exception) handler. */
441 expand_epilogue_reg_restore (rtx spreg
, bool saveall
, bool is_inthandler
)
443 rtx postinc1
= gen_rtx_POST_INC (SImode
, spreg
);
444 rtx postinc
= gen_rtx_MEM (SImode
, postinc1
);
446 int ndregs
= saveall
? 8 : n_dregs_to_save (is_inthandler
, false);
447 int npregs
= saveall
? 6 : n_pregs_to_save (is_inthandler
, false);
448 int ndregs_consec
= saveall
? 8 : n_dregs_to_save (is_inthandler
, true);
449 int npregs_consec
= saveall
? 6 : n_pregs_to_save (is_inthandler
, true);
450 int total_consec
= ndregs_consec
+ npregs_consec
;
454 /* A slightly crude technique to stop flow from trying to delete "dead"
456 MEM_VOLATILE_P (postinc
) = 1;
458 for (i
= REG_CC
- 1; i
> REG_P7
; i
--)
461 && (df_regs_ever_live_p (i
)
462 || (!leaf_function_p () && call_used_regs
[i
]))))
464 if (i
== REG_A0
|| i
== REG_A1
)
466 rtx mem
= gen_rtx_MEM (PDImode
, postinc1
);
467 MEM_VOLATILE_P (mem
) = 1;
468 emit_move_insn (gen_rtx_REG (PDImode
, i
), mem
);
471 emit_move_insn (gen_rtx_REG (SImode
, i
), postinc
);
474 regno
= REG_P5
- npregs_consec
;
475 for (; npregs
!= npregs_consec
; regno
--)
477 if (must_save_p (is_inthandler
, regno
))
479 emit_move_insn (gen_rtx_REG (word_mode
, regno
), postinc
);
483 regno
= REG_R7
- ndregs_consec
;
484 for (; ndregs
!= ndregs_consec
; regno
--)
486 if (must_save_p (is_inthandler
, regno
))
488 emit_move_insn (gen_rtx_REG (word_mode
, regno
), postinc
);
493 if (total_consec
!= 0)
495 rtx pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_consec
+ 1));
497 = gen_rtx_SET (VOIDmode
, spreg
,
498 gen_rtx_PLUS (Pmode
, spreg
,
499 GEN_INT (total_consec
* 4)));
501 if (npregs_consec
> 0)
506 for (i
= 0; i
< total_consec
; i
++)
509 ? gen_rtx_PLUS (Pmode
, spreg
, GEN_INT (i
* 4))
511 rtx memref
= gen_rtx_MEM (word_mode
, addr
);
514 XVECEXP (pat
, 0, i
+ 1)
515 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (word_mode
, regno
), memref
);
517 if (npregs_consec
> 0)
519 if (--npregs_consec
== 0)
524 insn
= emit_insn (pat
);
525 RTX_FRAME_RELATED_P (insn
) = 1;
527 if (saveall
|| is_inthandler
)
529 for (regno
= REG_LB1
; regno
>= REG_LT0
; regno
--)
530 if (! current_function_is_leaf
531 || cfun
->machine
->has_hardware_loops
532 || cfun
->machine
->has_loopreg_clobber
533 || (ENABLE_WA_05000257
&& (regno
== REG_LC0
|| regno
== REG_LC1
)))
534 emit_move_insn (gen_rtx_REG (SImode
, regno
), postinc
);
536 emit_move_insn (gen_rtx_REG (SImode
, REG_ASTAT
), postinc
);
540 /* Perform any needed actions needed for a function that is receiving a
541 variable number of arguments.
545 MODE and TYPE are the mode and type of the current parameter.
547 PRETEND_SIZE is a variable that should be set to the amount of stack
548 that must be pushed by the prolog to pretend that our caller pushed
551 Normally, this macro will push all remaining incoming registers on the
552 stack and set PRETEND_SIZE to the length of the registers pushed.
555 - VDSP C compiler manual (our ABI) says that a variable args function
556 should save the R0, R1 and R2 registers in the stack.
557 - The caller will always leave space on the stack for the
558 arguments that are passed in registers, so we dont have
559 to leave any extra space.
560 - now, the vastart pointer can access all arguments from the stack. */
563 setup_incoming_varargs (cumulative_args_t cum
,
564 enum machine_mode mode ATTRIBUTE_UNUSED
,
565 tree type ATTRIBUTE_UNUSED
, int *pretend_size
,
574 /* The move for named arguments will be generated automatically by the
575 compiler. We need to generate the move rtx for the unnamed arguments
576 if they are in the first 3 words. We assume at least 1 named argument
577 exists, so we never generate [ARGP] = R0 here. */
579 for (i
= get_cumulative_args (cum
)->words
+ 1; i
< max_arg_registers
; i
++)
581 mem
= gen_rtx_MEM (Pmode
,
582 plus_constant (Pmode
, arg_pointer_rtx
,
583 (i
* UNITS_PER_WORD
)));
584 emit_move_insn (mem
, gen_rtx_REG (Pmode
, i
));
590 /* Value should be nonzero if functions must have frame pointers.
591 Zero means the frame pointer need not be set up (and parms may
592 be accessed via the stack pointer) in functions that seem suitable. */
595 bfin_frame_pointer_required (void)
597 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
599 if (fkind
!= SUBROUTINE
)
602 /* We turn on -fomit-frame-pointer if -momit-leaf-frame-pointer is used,
603 so we have to override it for non-leaf functions. */
604 if (TARGET_OMIT_LEAF_FRAME_POINTER
&& ! current_function_is_leaf
)
610 /* Return the number of registers pushed during the prologue. */
613 n_regs_saved_by_prologue (void)
615 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
616 bool is_inthandler
= fkind
!= SUBROUTINE
;
617 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
618 bool all
= (lookup_attribute ("saveall", attrs
) != NULL_TREE
619 || (is_inthandler
&& !current_function_is_leaf
));
620 int ndregs
= all
? 8 : n_dregs_to_save (is_inthandler
, false);
621 int npregs
= all
? 6 : n_pregs_to_save (is_inthandler
, false);
622 int n
= ndregs
+ npregs
;
625 if (all
|| stack_frame_needed_p ())
629 if (must_save_fp_p ())
631 if (must_save_rets_p ())
635 if (fkind
!= SUBROUTINE
|| all
)
637 /* Increment once for ASTAT. */
639 if (! current_function_is_leaf
640 || cfun
->machine
->has_hardware_loops
641 || cfun
->machine
->has_loopreg_clobber
)
647 if (fkind
!= SUBROUTINE
)
650 if (lookup_attribute ("nesting", attrs
))
654 for (i
= REG_P7
+ 1; i
< REG_CC
; i
++)
656 || (fkind
!= SUBROUTINE
657 && (df_regs_ever_live_p (i
)
658 || (!leaf_function_p () && call_used_regs
[i
]))))
659 n
+= i
== REG_A0
|| i
== REG_A1
? 2 : 1;
664 /* Given FROM and TO register numbers, say whether this elimination is
665 allowed. Frame pointer elimination is automatically handled.
667 All other eliminations are valid. */
670 bfin_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
672 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
675 /* Return the offset between two registers, one to be eliminated, and the other
676 its replacement, at the start of a routine. */
679 bfin_initial_elimination_offset (int from
, int to
)
681 HOST_WIDE_INT offset
= 0;
683 if (from
== ARG_POINTER_REGNUM
)
684 offset
= n_regs_saved_by_prologue () * 4;
686 if (to
== STACK_POINTER_REGNUM
)
688 if (crtl
->outgoing_args_size
>= FIXED_STACK_AREA
)
689 offset
+= crtl
->outgoing_args_size
;
690 else if (crtl
->outgoing_args_size
)
691 offset
+= FIXED_STACK_AREA
;
693 offset
+= get_frame_size ();
699 /* Emit code to load a constant CONSTANT into register REG; setting
700 RTX_FRAME_RELATED_P on all insns we generate if RELATED is true.
701 Make sure that the insns we generate need not be split. */
704 frame_related_constant_load (rtx reg
, HOST_WIDE_INT constant
, bool related
)
707 rtx cst
= GEN_INT (constant
);
709 if (constant
>= -32768 && constant
< 65536)
710 insn
= emit_move_insn (reg
, cst
);
713 /* We don't call split_load_immediate here, since dwarf2out.c can get
714 confused about some of the more clever sequences it can generate. */
715 insn
= emit_insn (gen_movsi_high (reg
, cst
));
717 RTX_FRAME_RELATED_P (insn
) = 1;
718 insn
= emit_insn (gen_movsi_low (reg
, reg
, cst
));
721 RTX_FRAME_RELATED_P (insn
) = 1;
724 /* Generate efficient code to add a value to a P register.
725 Set RTX_FRAME_RELATED_P on the generated insns if FRAME is nonzero.
726 EPILOGUE_P is zero if this function is called for prologue,
727 otherwise it's nonzero. And it's less than zero if this is for
731 add_to_reg (rtx reg
, HOST_WIDE_INT value
, int frame
, int epilogue_p
)
736 /* Choose whether to use a sequence using a temporary register, or
737 a sequence with multiple adds. We can add a signed 7-bit value
738 in one instruction. */
739 if (value
> 120 || value
< -120)
747 /* For prologue or normal epilogue, P1 can be safely used
748 as the temporary register. For sibcall epilogue, we try to find
749 a call used P register, which will be restored in epilogue.
750 If we cannot find such a P register, we have to use one I register
754 tmpreg
= gen_rtx_REG (SImode
, REG_P1
);
758 for (i
= REG_P0
; i
<= REG_P5
; i
++)
759 if ((df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
761 && i
== PIC_OFFSET_TABLE_REGNUM
762 && (crtl
->uses_pic_offset_table
763 || (TARGET_ID_SHARED_LIBRARY
764 && ! current_function_is_leaf
))))
767 tmpreg
= gen_rtx_REG (SImode
, i
);
770 tmpreg
= gen_rtx_REG (SImode
, REG_P1
);
771 tmpreg2
= gen_rtx_REG (SImode
, REG_I0
);
772 emit_move_insn (tmpreg2
, tmpreg
);
777 frame_related_constant_load (tmpreg
, value
, TRUE
);
779 insn
= emit_move_insn (tmpreg
, GEN_INT (value
));
781 insn
= emit_insn (gen_addsi3 (reg
, reg
, tmpreg
));
783 RTX_FRAME_RELATED_P (insn
) = 1;
785 if (tmpreg2
!= NULL_RTX
)
786 emit_move_insn (tmpreg
, tmpreg2
);
797 /* We could use -62, but that would leave the stack unaligned, so
801 insn
= emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
803 RTX_FRAME_RELATED_P (insn
) = 1;
809 /* Generate a LINK insn for a frame sized FRAME_SIZE. If this constant
810 is too large, generate a sequence of insns that has the same effect.
811 SPREG contains (reg:SI REG_SP). */
814 emit_link_insn (rtx spreg
, HOST_WIDE_INT frame_size
)
816 HOST_WIDE_INT link_size
= frame_size
;
820 if (link_size
> 262140)
823 /* Use a LINK insn with as big a constant as possible, then subtract
824 any remaining size from the SP. */
825 insn
= emit_insn (gen_link (GEN_INT (-8 - link_size
)));
826 RTX_FRAME_RELATED_P (insn
) = 1;
828 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
830 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
831 gcc_assert (GET_CODE (set
) == SET
);
832 RTX_FRAME_RELATED_P (set
) = 1;
835 frame_size
-= link_size
;
839 /* Must use a call-clobbered PREG that isn't the static chain. */
840 rtx tmpreg
= gen_rtx_REG (Pmode
, REG_P1
);
842 frame_related_constant_load (tmpreg
, -frame_size
, TRUE
);
843 insn
= emit_insn (gen_addsi3 (spreg
, spreg
, tmpreg
));
844 RTX_FRAME_RELATED_P (insn
) = 1;
848 /* Return the number of bytes we must reserve for outgoing arguments
849 in the current function's stack frame. */
854 if (crtl
->outgoing_args_size
)
856 if (crtl
->outgoing_args_size
>= FIXED_STACK_AREA
)
857 return crtl
->outgoing_args_size
;
859 return FIXED_STACK_AREA
;
864 /* Save RETS and FP, and allocate a stack frame. ALL is true if the
865 function must save all its registers (true only for certain interrupt
869 do_link (rtx spreg
, HOST_WIDE_INT frame_size
, bool all
)
871 frame_size
+= arg_area_size ();
874 || stack_frame_needed_p ()
875 || (must_save_rets_p () && must_save_fp_p ()))
876 emit_link_insn (spreg
, frame_size
);
879 if (must_save_rets_p ())
881 rtx pat
= gen_movsi (gen_rtx_MEM (Pmode
,
882 gen_rtx_PRE_DEC (Pmode
, spreg
)),
884 rtx insn
= emit_insn (pat
);
885 RTX_FRAME_RELATED_P (insn
) = 1;
887 if (must_save_fp_p ())
889 rtx pat
= gen_movsi (gen_rtx_MEM (Pmode
,
890 gen_rtx_PRE_DEC (Pmode
, spreg
)),
891 gen_rtx_REG (Pmode
, REG_FP
));
892 rtx insn
= emit_insn (pat
);
893 RTX_FRAME_RELATED_P (insn
) = 1;
895 add_to_reg (spreg
, -frame_size
, 1, 0);
899 /* Like do_link, but used for epilogues to deallocate the stack frame.
900 EPILOGUE_P is zero if this function is called for prologue,
901 otherwise it's nonzero. And it's less than zero if this is for
905 do_unlink (rtx spreg
, HOST_WIDE_INT frame_size
, bool all
, int epilogue_p
)
907 frame_size
+= arg_area_size ();
909 if (stack_frame_needed_p ())
910 emit_insn (gen_unlink ());
913 rtx postinc
= gen_rtx_MEM (Pmode
, gen_rtx_POST_INC (Pmode
, spreg
));
915 add_to_reg (spreg
, frame_size
, 0, epilogue_p
);
916 if (all
|| must_save_fp_p ())
918 rtx fpreg
= gen_rtx_REG (Pmode
, REG_FP
);
919 emit_move_insn (fpreg
, postinc
);
922 if (all
|| must_save_rets_p ())
924 emit_move_insn (bfin_rets_rtx
, postinc
);
925 emit_use (bfin_rets_rtx
);
930 /* Generate a prologue suitable for a function of kind FKIND. This is
931 called for interrupt and exception handler prologues.
932 SPREG contains (reg:SI REG_SP). */
935 expand_interrupt_handler_prologue (rtx spreg
, e_funkind fkind
, bool all
)
937 HOST_WIDE_INT frame_size
= get_frame_size ();
938 rtx predec1
= gen_rtx_PRE_DEC (SImode
, spreg
);
939 rtx predec
= gen_rtx_MEM (SImode
, predec1
);
941 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
942 tree kspisusp
= lookup_attribute ("kspisusp", attrs
);
946 insn
= emit_move_insn (spreg
, gen_rtx_REG (Pmode
, REG_USP
));
947 RTX_FRAME_RELATED_P (insn
) = 1;
950 /* We need space on the stack in case we need to save the argument
952 if (fkind
== EXCPT_HANDLER
)
954 insn
= emit_insn (gen_addsi3 (spreg
, spreg
, GEN_INT (-12)));
955 RTX_FRAME_RELATED_P (insn
) = 1;
958 /* If we're calling other functions, they won't save their call-clobbered
959 registers, so we must save everything here. */
960 if (!current_function_is_leaf
)
962 expand_prologue_reg_save (spreg
, all
, true);
964 if (ENABLE_WA_05000283
|| ENABLE_WA_05000315
)
966 rtx chipid
= GEN_INT (trunc_int_for_mode (0xFFC00014, SImode
));
967 rtx p5reg
= gen_rtx_REG (Pmode
, REG_P5
);
968 emit_insn (gen_movbi (bfin_cc_rtx
, const1_rtx
));
969 emit_insn (gen_movsi_high (p5reg
, chipid
));
970 emit_insn (gen_movsi_low (p5reg
, p5reg
, chipid
));
971 emit_insn (gen_dummy_load (p5reg
, bfin_cc_rtx
));
974 if (lookup_attribute ("nesting", attrs
))
976 rtx srcreg
= gen_rtx_REG (Pmode
, ret_regs
[fkind
]);
977 insn
= emit_move_insn (predec
, srcreg
);
978 RTX_FRAME_RELATED_P (insn
) = 1;
981 do_link (spreg
, frame_size
, all
);
983 if (fkind
== EXCPT_HANDLER
)
985 rtx r0reg
= gen_rtx_REG (SImode
, REG_R0
);
986 rtx r1reg
= gen_rtx_REG (SImode
, REG_R1
);
987 rtx r2reg
= gen_rtx_REG (SImode
, REG_R2
);
989 emit_move_insn (r0reg
, gen_rtx_REG (SImode
, REG_SEQSTAT
));
990 emit_insn (gen_ashrsi3 (r0reg
, r0reg
, GEN_INT (26)));
991 emit_insn (gen_ashlsi3 (r0reg
, r0reg
, GEN_INT (26)));
992 emit_move_insn (r1reg
, spreg
);
993 emit_move_insn (r2reg
, gen_rtx_REG (Pmode
, REG_FP
));
994 emit_insn (gen_addsi3 (r2reg
, r2reg
, GEN_INT (8)));
998 /* Generate an epilogue suitable for a function of kind FKIND. This is
999 called for interrupt and exception handler epilogues.
1000 SPREG contains (reg:SI REG_SP). */
1003 expand_interrupt_handler_epilogue (rtx spreg
, e_funkind fkind
, bool all
)
1005 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1006 rtx postinc1
= gen_rtx_POST_INC (SImode
, spreg
);
1007 rtx postinc
= gen_rtx_MEM (SImode
, postinc1
);
1009 /* A slightly crude technique to stop flow from trying to delete "dead"
1011 MEM_VOLATILE_P (postinc
) = 1;
1013 do_unlink (spreg
, get_frame_size (), all
, 1);
1015 if (lookup_attribute ("nesting", attrs
))
1017 rtx srcreg
= gen_rtx_REG (Pmode
, ret_regs
[fkind
]);
1018 emit_move_insn (srcreg
, postinc
);
1021 /* If we're calling other functions, they won't save their call-clobbered
1022 registers, so we must save (and restore) everything here. */
1023 if (!current_function_is_leaf
)
1026 expand_epilogue_reg_restore (spreg
, all
, true);
1028 /* Deallocate any space we left on the stack in case we needed to save the
1029 argument registers. */
1030 if (fkind
== EXCPT_HANDLER
)
1031 emit_insn (gen_addsi3 (spreg
, spreg
, GEN_INT (12)));
1033 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
, ret_regs
[fkind
])));
1036 /* Used while emitting the prologue to generate code to load the correct value
1037 into the PIC register, which is passed in DEST. */
1040 bfin_load_pic_reg (rtx dest
)
1042 struct cgraph_local_info
*i
= NULL
;
1045 i
= cgraph_local_info (current_function_decl
);
1047 /* Functions local to the translation unit don't need to reload the
1048 pic reg, since the caller always passes a usable one. */
1050 return pic_offset_table_rtx
;
1052 if (global_options_set
.x_bfin_library_id
)
1053 addr
= plus_constant (Pmode
, pic_offset_table_rtx
,
1054 -4 - bfin_library_id
* 4);
1056 addr
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
1057 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1058 UNSPEC_LIBRARY_OFFSET
));
1059 emit_insn (gen_movsi (dest
, gen_rtx_MEM (Pmode
, addr
)));
1063 /* Generate RTL for the prologue of the current function. */
1066 bfin_expand_prologue (void)
1068 HOST_WIDE_INT frame_size
= get_frame_size ();
1069 rtx spreg
= gen_rtx_REG (Pmode
, REG_SP
);
1070 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1071 rtx pic_reg_loaded
= NULL_RTX
;
1072 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1073 bool all
= lookup_attribute ("saveall", attrs
) != NULL_TREE
;
1075 if (fkind
!= SUBROUTINE
)
1077 expand_interrupt_handler_prologue (spreg
, fkind
, all
);
1081 if (crtl
->limit_stack
1082 || (TARGET_STACK_CHECK_L1
1083 && !DECL_NO_LIMIT_STACK (current_function_decl
)))
1085 HOST_WIDE_INT offset
1086 = bfin_initial_elimination_offset (ARG_POINTER_REGNUM
,
1087 STACK_POINTER_REGNUM
);
1088 rtx lim
= crtl
->limit_stack
? stack_limit_rtx
: NULL_RTX
;
1089 rtx tmp
= gen_rtx_REG (Pmode
, REG_R3
);
1090 rtx p2reg
= gen_rtx_REG (Pmode
, REG_P2
);
1092 emit_move_insn (tmp
, p2reg
);
1095 emit_move_insn (p2reg
, gen_int_mode (0xFFB00000, SImode
));
1096 emit_move_insn (p2reg
, gen_rtx_MEM (Pmode
, p2reg
));
1099 if (GET_CODE (lim
) == SYMBOL_REF
)
1101 if (TARGET_ID_SHARED_LIBRARY
)
1103 rtx p1reg
= gen_rtx_REG (Pmode
, REG_P1
);
1105 pic_reg_loaded
= bfin_load_pic_reg (p2reg
);
1106 val
= legitimize_pic_address (stack_limit_rtx
, p1reg
,
1108 emit_move_insn (p1reg
, val
);
1109 frame_related_constant_load (p2reg
, offset
, FALSE
);
1110 emit_insn (gen_addsi3 (p2reg
, p2reg
, p1reg
));
1115 rtx limit
= plus_constant (Pmode
, lim
, offset
);
1116 emit_move_insn (p2reg
, limit
);
1123 emit_move_insn (p2reg
, lim
);
1124 add_to_reg (p2reg
, offset
, 0, 0);
1127 emit_insn (gen_compare_lt (bfin_cc_rtx
, spreg
, lim
));
1128 emit_insn (gen_trapifcc ());
1129 emit_move_insn (p2reg
, tmp
);
1131 expand_prologue_reg_save (spreg
, all
, false);
1133 do_link (spreg
, frame_size
, all
);
1135 if (TARGET_ID_SHARED_LIBRARY
1137 && (crtl
->uses_pic_offset_table
1138 || !current_function_is_leaf
))
1139 bfin_load_pic_reg (pic_offset_table_rtx
);
1142 /* Generate RTL for the epilogue of the current function. NEED_RETURN is zero
1143 if this is for a sibcall. EH_RETURN is nonzero if we're expanding an
1144 eh_return pattern. SIBCALL_P is true if this is a sibcall epilogue,
1148 bfin_expand_epilogue (int need_return
, int eh_return
, bool sibcall_p
)
1150 rtx spreg
= gen_rtx_REG (Pmode
, REG_SP
);
1151 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1152 int e
= sibcall_p
? -1 : 1;
1153 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1154 bool all
= lookup_attribute ("saveall", attrs
) != NULL_TREE
;
1156 if (fkind
!= SUBROUTINE
)
1158 expand_interrupt_handler_epilogue (spreg
, fkind
, all
);
1162 do_unlink (spreg
, get_frame_size (), all
, e
);
1164 expand_epilogue_reg_restore (spreg
, all
, false);
1166 /* Omit the return insn if this is for a sibcall. */
1171 emit_insn (gen_addsi3 (spreg
, spreg
, gen_rtx_REG (Pmode
, REG_P2
)));
1173 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
, REG_RETS
)));
1176 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
1179 bfin_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
1180 unsigned int new_reg
)
1182 /* Interrupt functions can only use registers that have already been
1183 saved by the prologue, even if they would normally be
1186 if (funkind (TREE_TYPE (current_function_decl
)) != SUBROUTINE
1187 && !df_regs_ever_live_p (new_reg
))
1193 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
1195 bfin_extra_live_on_entry (bitmap regs
)
1198 bitmap_set_bit (regs
, FDPIC_REGNO
);
1201 /* Return the value of the return address for the frame COUNT steps up
1202 from the current frame, after the prologue.
1203 We punt for everything but the current frame by returning const0_rtx. */
1206 bfin_return_addr_rtx (int count
)
1211 return get_hard_reg_initial_val (Pmode
, REG_RETS
);
1215 bfin_delegitimize_address (rtx orig_x
)
1219 if (GET_CODE (x
) != MEM
)
1223 if (GET_CODE (x
) == PLUS
1224 && GET_CODE (XEXP (x
, 1)) == UNSPEC
1225 && XINT (XEXP (x
, 1), 1) == UNSPEC_MOVE_PIC
1226 && GET_CODE (XEXP (x
, 0)) == REG
1227 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
1228 return XVECEXP (XEXP (x
, 1), 0, 0);
1233 /* This predicate is used to compute the length of a load/store insn.
1234 OP is a MEM rtx, we return nonzero if its addressing mode requires a
1235 32-bit instruction. */
1238 effective_address_32bit_p (rtx op
, enum machine_mode mode
)
1240 HOST_WIDE_INT offset
;
1242 mode
= GET_MODE (op
);
1245 if (GET_CODE (op
) != PLUS
)
1247 gcc_assert (REG_P (op
) || GET_CODE (op
) == POST_INC
1248 || GET_CODE (op
) == PRE_DEC
|| GET_CODE (op
) == POST_DEC
);
1252 if (GET_CODE (XEXP (op
, 1)) == UNSPEC
)
1255 offset
= INTVAL (XEXP (op
, 1));
1257 /* All byte loads use a 16-bit offset. */
1258 if (GET_MODE_SIZE (mode
) == 1)
1261 if (GET_MODE_SIZE (mode
) == 4)
1263 /* Frame pointer relative loads can use a negative offset, all others
1264 are restricted to a small positive one. */
1265 if (XEXP (op
, 0) == frame_pointer_rtx
)
1266 return offset
< -128 || offset
> 60;
1267 return offset
< 0 || offset
> 60;
1270 /* Must be HImode now. */
1271 return offset
< 0 || offset
> 30;
1274 /* Returns true if X is a memory reference using an I register. */
1276 bfin_dsp_memref_p (rtx x
)
1281 if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_INC
1282 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == PRE_DEC
)
1287 /* Return cost of the memory address ADDR.
1288 All addressing modes are equally cheap on the Blackfin. */
1291 bfin_address_cost (rtx addr ATTRIBUTE_UNUSED
, bool speed ATTRIBUTE_UNUSED
)
1296 /* Subroutine of print_operand; used to print a memory reference X to FILE. */
1299 print_address_operand (FILE *file
, rtx x
)
1301 switch (GET_CODE (x
))
1304 output_address (XEXP (x
, 0));
1305 fprintf (file
, "+");
1306 output_address (XEXP (x
, 1));
1310 fprintf (file
, "--");
1311 output_address (XEXP (x
, 0));
1314 output_address (XEXP (x
, 0));
1315 fprintf (file
, "++");
1318 output_address (XEXP (x
, 0));
1319 fprintf (file
, "--");
1323 gcc_assert (GET_CODE (x
) != MEM
);
1324 print_operand (file
, x
, 0);
1329 /* Adding intp DImode support by Tony
1335 print_operand (FILE *file
, rtx x
, char code
)
1337 enum machine_mode mode
;
1341 if (GET_MODE (current_output_insn
) == SImode
)
1342 fprintf (file
, " ||");
1344 fprintf (file
, ";");
1348 mode
= GET_MODE (x
);
1353 switch (GET_CODE (x
))
1356 fprintf (file
, "e");
1359 fprintf (file
, "ne");
1362 fprintf (file
, "g");
1365 fprintf (file
, "l");
1368 fprintf (file
, "ge");
1371 fprintf (file
, "le");
1374 fprintf (file
, "g");
1377 fprintf (file
, "l");
1380 fprintf (file
, "ge");
1383 fprintf (file
, "le");
1386 output_operand_lossage ("invalid %%j value");
1390 case 'J': /* reverse logic */
1391 switch (GET_CODE(x
))
1394 fprintf (file
, "ne");
1397 fprintf (file
, "e");
1400 fprintf (file
, "le");
1403 fprintf (file
, "ge");
1406 fprintf (file
, "l");
1409 fprintf (file
, "g");
1412 fprintf (file
, "le");
1415 fprintf (file
, "ge");
1418 fprintf (file
, "l");
1421 fprintf (file
, "g");
1424 output_operand_lossage ("invalid %%J value");
1429 switch (GET_CODE (x
))
1435 fprintf (file
, "%s", short_reg_names
[REGNO (x
)]);
1437 output_operand_lossage ("invalid operand for code '%c'", code
);
1439 else if (code
== 'd')
1442 fprintf (file
, "%s", high_reg_names
[REGNO (x
)]);
1444 output_operand_lossage ("invalid operand for code '%c'", code
);
1446 else if (code
== 'w')
1448 if (REGNO (x
) == REG_A0
|| REGNO (x
) == REG_A1
)
1449 fprintf (file
, "%s.w", reg_names
[REGNO (x
)]);
1451 output_operand_lossage ("invalid operand for code '%c'", code
);
1453 else if (code
== 'x')
1455 if (REGNO (x
) == REG_A0
|| REGNO (x
) == REG_A1
)
1456 fprintf (file
, "%s.x", reg_names
[REGNO (x
)]);
1458 output_operand_lossage ("invalid operand for code '%c'", code
);
1460 else if (code
== 'v')
1462 if (REGNO (x
) == REG_A0
)
1463 fprintf (file
, "AV0");
1464 else if (REGNO (x
) == REG_A1
)
1465 fprintf (file
, "AV1");
1467 output_operand_lossage ("invalid operand for code '%c'", code
);
1469 else if (code
== 'D')
1471 if (D_REGNO_P (REGNO (x
)))
1472 fprintf (file
, "%s", dregs_pair_names
[REGNO (x
)]);
1474 output_operand_lossage ("invalid operand for code '%c'", code
);
1476 else if (code
== 'H')
1478 if ((mode
== DImode
|| mode
== DFmode
) && REG_P (x
))
1479 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
1481 output_operand_lossage ("invalid operand for code '%c'", code
);
1483 else if (code
== 'T')
1485 if (D_REGNO_P (REGNO (x
)))
1486 fprintf (file
, "%s", byte_reg_names
[REGNO (x
)]);
1488 output_operand_lossage ("invalid operand for code '%c'", code
);
1491 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1497 print_address_operand (file
, x
);
1509 fputs ("(FU)", file
);
1512 fputs ("(T)", file
);
1515 fputs ("(TFU)", file
);
1518 fputs ("(W32)", file
);
1521 fputs ("(IS)", file
);
1524 fputs ("(IU)", file
);
1527 fputs ("(IH)", file
);
1530 fputs ("(M)", file
);
1533 fputs ("(IS,M)", file
);
1536 fputs ("(ISS2)", file
);
1539 fputs ("(S2RND)", file
);
1546 else if (code
== 'b')
1548 if (INTVAL (x
) == 0)
1550 else if (INTVAL (x
) == 1)
1556 /* Moves to half registers with d or h modifiers always use unsigned
1558 else if (code
== 'd')
1559 x
= GEN_INT ((INTVAL (x
) >> 16) & 0xffff);
1560 else if (code
== 'h')
1561 x
= GEN_INT (INTVAL (x
) & 0xffff);
1562 else if (code
== 'N')
1563 x
= GEN_INT (-INTVAL (x
));
1564 else if (code
== 'X')
1565 x
= GEN_INT (exact_log2 (0xffffffff & INTVAL (x
)));
1566 else if (code
== 'Y')
1567 x
= GEN_INT (exact_log2 (0xffffffff & ~INTVAL (x
)));
1568 else if (code
== 'Z')
1569 /* Used for LINK insns. */
1570 x
= GEN_INT (-8 - INTVAL (x
));
1575 output_addr_const (file
, x
);
1579 output_operand_lossage ("invalid const_double operand");
1583 switch (XINT (x
, 1))
1585 case UNSPEC_MOVE_PIC
:
1586 output_addr_const (file
, XVECEXP (x
, 0, 0));
1587 fprintf (file
, "@GOT");
1590 case UNSPEC_MOVE_FDPIC
:
1591 output_addr_const (file
, XVECEXP (x
, 0, 0));
1592 fprintf (file
, "@GOT17M4");
1595 case UNSPEC_FUNCDESC_GOT17M4
:
1596 output_addr_const (file
, XVECEXP (x
, 0, 0));
1597 fprintf (file
, "@FUNCDESC_GOT17M4");
1600 case UNSPEC_LIBRARY_OFFSET
:
1601 fprintf (file
, "_current_shared_library_p5_offset_");
1610 output_addr_const (file
, x
);
1615 /* Argument support functions. */
1617 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1618 for a call to a function whose data type is FNTYPE.
1619 For a library call, FNTYPE is 0.
1620 VDSP C Compiler manual, our ABI says that
1621 first 3 words of arguments will use R0, R1 and R2.
1625 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
1626 rtx libname ATTRIBUTE_UNUSED
)
1628 static CUMULATIVE_ARGS zero_cum
;
1632 /* Set up the number of registers to use for passing arguments. */
1634 cum
->nregs
= max_arg_registers
;
1635 cum
->arg_regs
= arg_regs
;
1637 cum
->call_cookie
= CALL_NORMAL
;
1638 /* Check for a longcall attribute. */
1639 if (fntype
&& lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
)))
1640 cum
->call_cookie
|= CALL_SHORT
;
1641 else if (fntype
&& lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
)))
1642 cum
->call_cookie
|= CALL_LONG
;
1647 /* Update the data in CUM to advance over an argument
1648 of mode MODE and data type TYPE.
1649 (TYPE is null for libcalls where that information may not be available.) */
1652 bfin_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1653 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1655 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1656 int count
, bytes
, words
;
1658 bytes
= (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1659 words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1661 cum
->words
+= words
;
1662 cum
->nregs
-= words
;
1664 if (cum
->nregs
<= 0)
1667 cum
->arg_regs
= NULL
;
1671 for (count
= 1; count
<= words
; count
++)
1678 /* Define where to put the arguments to a function.
1679 Value is zero to push the argument on the stack,
1680 or a hard register in which to store the argument.
1682 MODE is the argument's machine mode.
1683 TYPE is the data type of the argument (as a tree).
1684 This is null for libcalls where that information may
1686 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1687 the preceding args and about the function being called.
1688 NAMED is nonzero if this argument is a named parameter
1689 (otherwise it is an extra parameter matching an ellipsis). */
1692 bfin_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
1693 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1695 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1697 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1699 if (mode
== VOIDmode
)
1700 /* Compute operand 2 of the call insn. */
1701 return GEN_INT (cum
->call_cookie
);
1707 return gen_rtx_REG (mode
, *(cum
->arg_regs
));
1712 /* For an arg passed partly in registers and partly in memory,
1713 this is the number of bytes passed in registers.
1714 For args passed entirely in registers or entirely in memory, zero.
1716 Refer VDSP C Compiler manual, our ABI.
1717 First 3 words are in registers. So, if an argument is larger
1718 than the registers available, it will span the register and
1722 bfin_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
1723 tree type ATTRIBUTE_UNUSED
,
1724 bool named ATTRIBUTE_UNUSED
)
1727 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1728 int bytes_left
= get_cumulative_args (cum
)->nregs
* UNITS_PER_WORD
;
1733 if (bytes_left
== 0)
1735 if (bytes
> bytes_left
)
1740 /* Variable sized types are passed by reference. */
1743 bfin_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1744 enum machine_mode mode ATTRIBUTE_UNUSED
,
1745 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1747 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
1750 /* Decide whether a type should be returned in memory (true)
1751 or in a register (false). This is called by the macro
1752 TARGET_RETURN_IN_MEMORY. */
1755 bfin_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1757 int size
= int_size_in_bytes (type
);
1758 return size
> 2 * UNITS_PER_WORD
|| size
== -1;
1761 /* Register in which address to store a structure value
1762 is passed to a function. */
1764 bfin_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
1765 int incoming ATTRIBUTE_UNUSED
)
1767 return gen_rtx_REG (Pmode
, REG_P0
);
1770 /* Return true when register may be used to pass function parameters. */
1773 function_arg_regno_p (int n
)
1776 for (i
= 0; arg_regs
[i
] != -1; i
++)
1777 if (n
== arg_regs
[i
])
1782 /* Returns 1 if OP contains a symbol reference */
1785 symbolic_reference_mentioned_p (rtx op
)
1787 register const char *fmt
;
1790 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1793 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
1794 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
1800 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
1801 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
1805 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
1812 /* Decide whether we can make a sibling call to a function. DECL is the
1813 declaration of the function being targeted by the call and EXP is the
1814 CALL_EXPR representing the call. */
1817 bfin_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
1818 tree exp ATTRIBUTE_UNUSED
)
1820 struct cgraph_local_info
*this_func
, *called_func
;
1821 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1822 if (fkind
!= SUBROUTINE
)
1824 if (!TARGET_ID_SHARED_LIBRARY
|| TARGET_SEP_DATA
)
1827 /* When compiling for ID shared libraries, can't sibcall a local function
1828 from a non-local function, because the local function thinks it does
1829 not need to reload P5 in the prologue, but the sibcall wil pop P5 in the
1830 sibcall epilogue, and we end up with the wrong value in P5. */
1833 /* Not enough information. */
1836 this_func
= cgraph_local_info (current_function_decl
);
1837 called_func
= cgraph_local_info (decl
);
1840 return !called_func
->local
|| this_func
->local
;
1843 /* Write a template for a trampoline to F. */
1846 bfin_asm_trampoline_template (FILE *f
)
1850 fprintf (f
, "\t.dd\t0x00000000\n"); /* 0 */
1851 fprintf (f
, "\t.dd\t0x00000000\n"); /* 0 */
1852 fprintf (f
, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */
1853 fprintf (f
, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */
1854 fprintf (f
, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */
1855 fprintf (f
, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */
1856 fprintf (f
, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */
1857 fprintf (f
, "\t.dw\t0x9149\n"); /* p1 = [p1] */
1858 fprintf (f
, "\t.dw\t0x0051\n"); /* jump (p1)*/
1862 fprintf (f
, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */
1863 fprintf (f
, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */
1864 fprintf (f
, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */
1865 fprintf (f
, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */
1866 fprintf (f
, "\t.dw\t0x0051\n"); /* jump (p1)*/
1870 /* Emit RTL insns to initialize the variable parts of a trampoline at
1871 M_TRAMP. FNDECL is the target function. CHAIN_VALUE is an RTX for
1872 the static chain value for the function. */
1875 bfin_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
1877 rtx t1
= copy_to_reg (XEXP (DECL_RTL (fndecl
), 0));
1878 rtx t2
= copy_to_reg (chain_value
);
1882 emit_block_move (m_tramp
, assemble_trampoline_template (),
1883 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
1887 rtx a
= force_reg (Pmode
, plus_constant (Pmode
, XEXP (m_tramp
, 0), 8));
1888 mem
= adjust_address (m_tramp
, Pmode
, 0);
1889 emit_move_insn (mem
, a
);
1893 mem
= adjust_address (m_tramp
, HImode
, i
+ 2);
1894 emit_move_insn (mem
, gen_lowpart (HImode
, t1
));
1895 emit_insn (gen_ashrsi3 (t1
, t1
, GEN_INT (16)));
1896 mem
= adjust_address (m_tramp
, HImode
, i
+ 6);
1897 emit_move_insn (mem
, gen_lowpart (HImode
, t1
));
1899 mem
= adjust_address (m_tramp
, HImode
, i
+ 10);
1900 emit_move_insn (mem
, gen_lowpart (HImode
, t2
));
1901 emit_insn (gen_ashrsi3 (t2
, t2
, GEN_INT (16)));
1902 mem
= adjust_address (m_tramp
, HImode
, i
+ 14);
1903 emit_move_insn (mem
, gen_lowpart (HImode
, t2
));
1906 /* Emit insns to move operands[1] into operands[0]. */
1909 emit_pic_move (rtx
*operands
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1911 rtx temp
= reload_in_progress
? operands
[0] : gen_reg_rtx (Pmode
);
1913 gcc_assert (!TARGET_FDPIC
|| !(reload_in_progress
|| reload_completed
));
1914 if (GET_CODE (operands
[0]) == MEM
&& SYMBOLIC_CONST (operands
[1]))
1915 operands
[1] = force_reg (SImode
, operands
[1]);
1917 operands
[1] = legitimize_pic_address (operands
[1], temp
,
1918 TARGET_FDPIC
? OUR_FDPIC_REG
1919 : pic_offset_table_rtx
);
1922 /* Expand a move operation in mode MODE. The operands are in OPERANDS.
1923 Returns true if no further code must be generated, false if the caller
1924 should generate an insn to move OPERANDS[1] to OPERANDS[0]. */
1927 expand_move (rtx
*operands
, enum machine_mode mode
)
1929 rtx op
= operands
[1];
1930 if ((TARGET_ID_SHARED_LIBRARY
|| TARGET_FDPIC
)
1931 && SYMBOLIC_CONST (op
))
1932 emit_pic_move (operands
, mode
);
1933 else if (mode
== SImode
&& GET_CODE (op
) == CONST
1934 && GET_CODE (XEXP (op
, 0)) == PLUS
1935 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
1936 && !targetm
.legitimate_constant_p (mode
, op
))
1938 rtx dest
= operands
[0];
1940 gcc_assert (!reload_in_progress
&& !reload_completed
);
1942 op0
= force_reg (mode
, XEXP (op
, 0));
1944 if (!insn_data
[CODE_FOR_addsi3
].operand
[2].predicate (op1
, mode
))
1945 op1
= force_reg (mode
, op1
);
1946 if (GET_CODE (dest
) == MEM
)
1947 dest
= gen_reg_rtx (mode
);
1948 emit_insn (gen_addsi3 (dest
, op0
, op1
));
1949 if (dest
== operands
[0])
1953 /* Don't generate memory->memory or constant->memory moves, go through a
1955 else if ((reload_in_progress
| reload_completed
) == 0
1956 && GET_CODE (operands
[0]) == MEM
1957 && GET_CODE (operands
[1]) != REG
)
1958 operands
[1] = force_reg (mode
, operands
[1]);
1962 /* Split one or more DImode RTL references into pairs of SImode
1963 references. The RTL can be REG, offsettable MEM, integer constant, or
1964 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
1965 split and "num" is its length. lo_half and hi_half are output arrays
1966 that parallel "operands". */
1969 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
1973 rtx op
= operands
[num
];
1975 /* simplify_subreg refuse to split volatile memory addresses,
1976 but we still have to handle it. */
1977 if (GET_CODE (op
) == MEM
)
1979 lo_half
[num
] = adjust_address (op
, SImode
, 0);
1980 hi_half
[num
] = adjust_address (op
, SImode
, 4);
1984 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
1985 GET_MODE (op
) == VOIDmode
1986 ? DImode
: GET_MODE (op
), 0);
1987 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
1988 GET_MODE (op
) == VOIDmode
1989 ? DImode
: GET_MODE (op
), 4);
1995 bfin_longcall_p (rtx op
, int call_cookie
)
1997 gcc_assert (GET_CODE (op
) == SYMBOL_REF
);
1998 if (SYMBOL_REF_WEAK (op
))
2000 if (call_cookie
& CALL_SHORT
)
2002 if (call_cookie
& CALL_LONG
)
2004 if (TARGET_LONG_CALLS
)
2009 /* Expand a call instruction. FNADDR is the call target, RETVAL the return value.
2010 COOKIE is a CONST_INT holding the call_cookie prepared init_cumulative_args.
2011 SIBCALL is nonzero if this is a sibling call. */
2014 bfin_expand_call (rtx retval
, rtx fnaddr
, rtx callarg1
, rtx cookie
, int sibcall
)
2016 rtx use
= NULL
, call
;
2017 rtx callee
= XEXP (fnaddr
, 0);
2020 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REGNO
);
2021 rtx retsreg
= gen_rtx_REG (Pmode
, REG_RETS
);
2024 /* In an untyped call, we can get NULL for operand 2. */
2025 if (cookie
== NULL_RTX
)
2026 cookie
= const0_rtx
;
2028 /* Static functions and indirect calls don't need the pic register. */
2029 if (!TARGET_FDPIC
&& flag_pic
2030 && GET_CODE (callee
) == SYMBOL_REF
2031 && !SYMBOL_REF_LOCAL_P (callee
))
2032 use_reg (&use
, pic_offset_table_rtx
);
2036 int caller_in_sram
, callee_in_sram
;
2038 /* 0 is not in sram, 1 is in L1 sram, 2 is in L2 sram. */
2039 caller_in_sram
= callee_in_sram
= 0;
2041 if (lookup_attribute ("l1_text",
2042 DECL_ATTRIBUTES (cfun
->decl
)) != NULL_TREE
)
2044 else if (lookup_attribute ("l2",
2045 DECL_ATTRIBUTES (cfun
->decl
)) != NULL_TREE
)
2048 if (GET_CODE (callee
) == SYMBOL_REF
2049 && SYMBOL_REF_DECL (callee
) && DECL_P (SYMBOL_REF_DECL (callee
)))
2051 if (lookup_attribute
2053 DECL_ATTRIBUTES (SYMBOL_REF_DECL (callee
))) != NULL_TREE
)
2055 else if (lookup_attribute
2057 DECL_ATTRIBUTES (SYMBOL_REF_DECL (callee
))) != NULL_TREE
)
2061 if (GET_CODE (callee
) != SYMBOL_REF
2062 || bfin_longcall_p (callee
, INTVAL (cookie
))
2063 || (GET_CODE (callee
) == SYMBOL_REF
2064 && !SYMBOL_REF_LOCAL_P (callee
)
2065 && TARGET_INLINE_PLT
)
2066 || caller_in_sram
!= callee_in_sram
2067 || (caller_in_sram
&& callee_in_sram
2068 && (GET_CODE (callee
) != SYMBOL_REF
2069 || !SYMBOL_REF_LOCAL_P (callee
))))
2072 if (! address_operand (addr
, Pmode
))
2073 addr
= force_reg (Pmode
, addr
);
2075 fnaddr
= gen_reg_rtx (SImode
);
2076 emit_insn (gen_load_funcdescsi (fnaddr
, addr
));
2077 fnaddr
= gen_rtx_MEM (Pmode
, fnaddr
);
2079 picreg
= gen_reg_rtx (SImode
);
2080 emit_insn (gen_load_funcdescsi (picreg
,
2081 plus_constant (Pmode
, addr
, 4)));
2086 else if ((!register_no_elim_operand (callee
, Pmode
)
2087 && GET_CODE (callee
) != SYMBOL_REF
)
2088 || (GET_CODE (callee
) == SYMBOL_REF
2089 && ((TARGET_ID_SHARED_LIBRARY
&& !TARGET_LEAF_ID_SHARED_LIBRARY
)
2090 || bfin_longcall_p (callee
, INTVAL (cookie
)))))
2092 callee
= copy_to_mode_reg (Pmode
, callee
);
2093 fnaddr
= gen_rtx_MEM (Pmode
, callee
);
2095 call
= gen_rtx_CALL (VOIDmode
, fnaddr
, callarg1
);
2098 call
= gen_rtx_SET (VOIDmode
, retval
, call
);
2100 pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nelts
));
2102 XVECEXP (pat
, 0, n
++) = call
;
2104 XVECEXP (pat
, 0, n
++) = gen_rtx_USE (VOIDmode
, picreg
);
2105 XVECEXP (pat
, 0, n
++) = gen_rtx_USE (VOIDmode
, cookie
);
2107 XVECEXP (pat
, 0, n
++) = ret_rtx
;
2109 XVECEXP (pat
, 0, n
++) = gen_rtx_CLOBBER (VOIDmode
, retsreg
);
2110 call
= emit_call_insn (pat
);
2112 CALL_INSN_FUNCTION_USAGE (call
) = use
;
2115 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
2118 hard_regno_mode_ok (int regno
, enum machine_mode mode
)
2120 /* Allow only dregs to store value of mode HI or QI */
2121 enum reg_class rclass
= REGNO_REG_CLASS (regno
);
2126 if (mode
== V2HImode
)
2127 return D_REGNO_P (regno
);
2128 if (rclass
== CCREGS
)
2129 return mode
== BImode
;
2130 if (mode
== PDImode
|| mode
== V2PDImode
)
2131 return regno
== REG_A0
|| regno
== REG_A1
;
2133 /* Allow all normal 32-bit regs, except REG_M3, in case regclass ever comes
2134 up with a bad register class (such as ALL_REGS) for DImode. */
2136 return regno
< REG_M3
;
2139 && TEST_HARD_REG_BIT (reg_class_contents
[PROLOGUE_REGS
], regno
))
2142 return TEST_HARD_REG_BIT (reg_class_contents
[MOST_REGS
], regno
);
2145 /* Implements target hook vector_mode_supported_p. */
2148 bfin_vector_mode_supported_p (enum machine_mode mode
)
2150 return mode
== V2HImode
;
2153 /* Worker function for TARGET_REGISTER_MOVE_COST. */
2156 bfin_register_move_cost (enum machine_mode mode
,
2157 reg_class_t class1
, reg_class_t class2
)
2159 /* These need secondary reloads, so they're more expensive. */
2160 if ((class1
== CCREGS
&& !reg_class_subset_p (class2
, DREGS
))
2161 || (class2
== CCREGS
&& !reg_class_subset_p (class1
, DREGS
)))
2164 /* If optimizing for size, always prefer reg-reg over reg-memory moves. */
2168 if (GET_MODE_CLASS (mode
) == MODE_INT
)
2170 /* Discourage trying to use the accumulators. */
2171 if (TEST_HARD_REG_BIT (reg_class_contents
[class1
], REG_A0
)
2172 || TEST_HARD_REG_BIT (reg_class_contents
[class1
], REG_A1
)
2173 || TEST_HARD_REG_BIT (reg_class_contents
[class2
], REG_A0
)
2174 || TEST_HARD_REG_BIT (reg_class_contents
[class2
], REG_A1
))
2180 /* Worker function for TARGET_MEMORY_MOVE_COST.
2182 ??? In theory L1 memory has single-cycle latency. We should add a switch
2183 that tells the compiler whether we expect to use only L1 memory for the
2184 program; it'll make the costs more accurate. */
2187 bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2189 bool in ATTRIBUTE_UNUSED
)
2191 /* Make memory accesses slightly more expensive than any register-register
2192 move. Also, penalize non-DP registers, since they need secondary
2193 reloads to load and store. */
2194 if (! reg_class_subset_p (rclass
, DPREGS
))
2200 /* Inform reload about cases where moving X with a mode MODE to a register in
2201 RCLASS requires an extra scratch register. Return the class needed for the
2202 scratch register. */
2205 bfin_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
2206 enum machine_mode mode
, secondary_reload_info
*sri
)
2208 /* If we have HImode or QImode, we can only use DREGS as secondary registers;
2209 in most other cases we can also use PREGS. */
2210 enum reg_class default_class
= GET_MODE_SIZE (mode
) >= 4 ? DPREGS
: DREGS
;
2211 enum reg_class x_class
= NO_REGS
;
2212 enum rtx_code code
= GET_CODE (x
);
2213 enum reg_class rclass
= (enum reg_class
) rclass_i
;
2216 x
= SUBREG_REG (x
), code
= GET_CODE (x
);
2219 int regno
= REGNO (x
);
2220 if (regno
>= FIRST_PSEUDO_REGISTER
)
2221 regno
= reg_renumber
[regno
];
2226 x_class
= REGNO_REG_CLASS (regno
);
2229 /* We can be asked to reload (plus (FP) (large_constant)) into a DREG.
2230 This happens as a side effect of register elimination, and we need
2231 a scratch register to do it. */
2232 if (fp_plus_const_operand (x
, mode
))
2234 rtx op2
= XEXP (x
, 1);
2235 int large_constant_p
= ! satisfies_constraint_Ks7 (op2
);
2237 if (rclass
== PREGS
|| rclass
== PREGS_CLOBBERED
)
2239 /* If destination is a DREG, we can do this without a scratch register
2240 if the constant is valid for an add instruction. */
2241 if ((rclass
== DREGS
|| rclass
== DPREGS
)
2242 && ! large_constant_p
)
2244 /* Reloading to anything other than a DREG? Use a PREG scratch
2246 sri
->icode
= CODE_FOR_reload_insi
;
2250 /* Data can usually be moved freely between registers of most classes.
2251 AREGS are an exception; they can only move to or from another register
2252 in AREGS or one in DREGS. They can also be assigned the constant 0. */
2253 if (x_class
== AREGS
|| x_class
== EVEN_AREGS
|| x_class
== ODD_AREGS
)
2254 return (rclass
== DREGS
|| rclass
== AREGS
|| rclass
== EVEN_AREGS
2255 || rclass
== ODD_AREGS
2258 if (rclass
== AREGS
|| rclass
== EVEN_AREGS
|| rclass
== ODD_AREGS
)
2262 sri
->icode
= in_p
? CODE_FOR_reload_inpdi
: CODE_FOR_reload_outpdi
;
2266 if (x
!= const0_rtx
&& x_class
!= DREGS
)
2274 /* CCREGS can only be moved from/to DREGS. */
2275 if (rclass
== CCREGS
&& x_class
!= DREGS
)
2277 if (x_class
== CCREGS
&& rclass
!= DREGS
)
2280 /* All registers other than AREGS can load arbitrary constants. The only
2281 case that remains is MEM. */
2283 if (! reg_class_subset_p (rclass
, default_class
))
2284 return default_class
;
2289 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
2292 bfin_class_likely_spilled_p (reg_class_t rclass
)
2296 case PREGS_CLOBBERED
:
2312 static struct machine_function
*
2313 bfin_init_machine_status (void)
2315 return ggc_alloc_cleared_machine_function ();
2318 /* Implement the TARGET_OPTION_OVERRIDE hook. */
2321 bfin_option_override (void)
2323 /* If processor type is not specified, enable all workarounds. */
2324 if (bfin_cpu_type
== BFIN_CPU_UNKNOWN
)
2328 for (i
= 0; bfin_cpus
[i
].name
!= NULL
; i
++)
2329 bfin_workarounds
|= bfin_cpus
[i
].workarounds
;
2331 bfin_si_revision
= 0xffff;
2334 if (bfin_csync_anomaly
== 1)
2335 bfin_workarounds
|= WA_SPECULATIVE_SYNCS
;
2336 else if (bfin_csync_anomaly
== 0)
2337 bfin_workarounds
&= ~WA_SPECULATIVE_SYNCS
;
2339 if (bfin_specld_anomaly
== 1)
2340 bfin_workarounds
|= WA_SPECULATIVE_LOADS
;
2341 else if (bfin_specld_anomaly
== 0)
2342 bfin_workarounds
&= ~WA_SPECULATIVE_LOADS
;
2344 if (TARGET_OMIT_LEAF_FRAME_POINTER
)
2345 flag_omit_frame_pointer
= 1;
2347 #ifdef SUBTARGET_FDPIC_NOT_SUPPORTED
2349 error ("-mfdpic is not supported, please use a bfin-linux-uclibc target");
2352 /* Library identification */
2353 if (global_options_set
.x_bfin_library_id
&& ! TARGET_ID_SHARED_LIBRARY
)
2354 error ("-mshared-library-id= specified without -mid-shared-library");
2356 if (stack_limit_rtx
&& TARGET_FDPIC
)
2358 warning (0, "-fstack-limit- options are ignored with -mfdpic; use -mstack-check-l1");
2359 stack_limit_rtx
= NULL_RTX
;
2362 if (stack_limit_rtx
&& TARGET_STACK_CHECK_L1
)
2363 error ("can%'t use multiple stack checking methods together");
2365 if (TARGET_ID_SHARED_LIBRARY
&& TARGET_FDPIC
)
2366 error ("ID shared libraries and FD-PIC mode can%'t be used together");
2368 /* Don't allow the user to specify -mid-shared-library and -msep-data
2369 together, as it makes little sense from a user's point of view... */
2370 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
2371 error ("cannot specify both -msep-data and -mid-shared-library");
2372 /* ... internally, however, it's nearly the same. */
2373 if (TARGET_SEP_DATA
)
2374 target_flags
|= MASK_ID_SHARED_LIBRARY
| MASK_LEAF_ID_SHARED_LIBRARY
;
2376 if (TARGET_ID_SHARED_LIBRARY
&& flag_pic
== 0)
2379 /* There is no single unaligned SI op for PIC code. Sometimes we
2380 need to use ".4byte" and sometimes we need to use ".picptr".
2381 See bfin_assemble_integer for details. */
2383 targetm
.asm_out
.unaligned_op
.si
= 0;
2385 /* Silently turn off flag_pic if not doing FDPIC or ID shared libraries,
2386 since we don't support it and it'll just break. */
2387 if (flag_pic
&& !TARGET_FDPIC
&& !TARGET_ID_SHARED_LIBRARY
)
2390 if (TARGET_MULTICORE
&& bfin_cpu_type
!= BFIN_CPU_BF561
)
2391 error ("-mmulticore can only be used with BF561");
2393 if (TARGET_COREA
&& !TARGET_MULTICORE
)
2394 error ("-mcorea should be used with -mmulticore");
2396 if (TARGET_COREB
&& !TARGET_MULTICORE
)
2397 error ("-mcoreb should be used with -mmulticore");
2399 if (TARGET_COREA
&& TARGET_COREB
)
2400 error ("-mcorea and -mcoreb can%'t be used together");
2402 flag_schedule_insns
= 0;
2404 init_machine_status
= bfin_init_machine_status
;
2407 /* Return the destination address of BRANCH.
2408 We need to use this instead of get_attr_length, because the
2409 cbranch_with_nops pattern conservatively sets its length to 6, and
2410 we still prefer to use shorter sequences. */
2413 branch_dest (rtx branch
)
2417 rtx pat
= PATTERN (branch
);
2418 if (GET_CODE (pat
) == PARALLEL
)
2419 pat
= XVECEXP (pat
, 0, 0);
2420 dest
= SET_SRC (pat
);
2421 if (GET_CODE (dest
) == IF_THEN_ELSE
)
2422 dest
= XEXP (dest
, 1);
2423 dest
= XEXP (dest
, 0);
2424 dest_uid
= INSN_UID (dest
);
2425 return INSN_ADDRESSES (dest_uid
);
2428 /* Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates
2429 it's a branch that's predicted taken. */
2432 cbranch_predicted_taken_p (rtx insn
)
2434 rtx x
= find_reg_note (insn
, REG_BR_PROB
, 0);
2438 int pred_val
= INTVAL (XEXP (x
, 0));
2440 return pred_val
>= REG_BR_PROB_BASE
/ 2;
2446 /* Templates for use by asm_conditional_branch. */
2448 static const char *ccbranch_templates
[][3] = {
2449 { "if !cc jump %3;", "if cc jump 4 (bp); jump.s %3;", "if cc jump 6 (bp); jump.l %3;" },
2450 { "if cc jump %3;", "if !cc jump 4 (bp); jump.s %3;", "if !cc jump 6 (bp); jump.l %3;" },
2451 { "if !cc jump %3 (bp);", "if cc jump 4; jump.s %3;", "if cc jump 6; jump.l %3;" },
2452 { "if cc jump %3 (bp);", "if !cc jump 4; jump.s %3;", "if !cc jump 6; jump.l %3;" },
2455 /* Output INSN, which is a conditional branch instruction with operands
2458 We deal with the various forms of conditional branches that can be generated
2459 by bfin_reorg to prevent the hardware from doing speculative loads, by
2460 - emitting a sufficient number of nops, if N_NOPS is nonzero, or
2461 - always emitting the branch as predicted taken, if PREDICT_TAKEN is true.
2462 Either of these is only necessary if the branch is short, otherwise the
2463 template we use ends in an unconditional jump which flushes the pipeline
2467 asm_conditional_branch (rtx insn
, rtx
*operands
, int n_nops
, int predict_taken
)
2469 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
2470 /* Note : offset for instructions like if cc jmp; jump.[sl] offset
2471 is to be taken from start of if cc rather than jump.
2472 Range for jump.s is (-4094, 4096) instead of (-4096, 4094)
2474 int len
= (offset
>= -1024 && offset
<= 1022 ? 0
2475 : offset
>= -4094 && offset
<= 4096 ? 1
2477 int bp
= predict_taken
&& len
== 0 ? 1 : cbranch_predicted_taken_p (insn
);
2478 int idx
= (bp
<< 1) | (GET_CODE (operands
[0]) == EQ
? BRF
: BRT
);
2479 output_asm_insn (ccbranch_templates
[idx
][len
], operands
);
2480 gcc_assert (n_nops
== 0 || !bp
);
2482 while (n_nops
-- > 0)
2483 output_asm_insn ("nop;", NULL
);
2486 /* Emit rtl for a comparison operation CMP in mode MODE. Operands have been
2487 stored in bfin_compare_op0 and bfin_compare_op1 already. */
2490 bfin_gen_compare (rtx cmp
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2492 enum rtx_code code1
, code2
;
2493 rtx op0
= XEXP (cmp
, 0), op1
= XEXP (cmp
, 1);
2494 rtx tem
= bfin_cc_rtx
;
2495 enum rtx_code code
= GET_CODE (cmp
);
2497 /* If we have a BImode input, then we already have a compare result, and
2498 do not need to emit another comparison. */
2499 if (GET_MODE (op0
) == BImode
)
2501 gcc_assert ((code
== NE
|| code
== EQ
) && op1
== const0_rtx
);
2502 tem
= op0
, code2
= code
;
2507 /* bfin has these conditions */
2517 code1
= reverse_condition (code
);
2521 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
2522 gen_rtx_fmt_ee (code1
, BImode
, op0
, op1
)));
2525 return gen_rtx_fmt_ee (code2
, BImode
, tem
, CONST0_RTX (BImode
));
2528 /* Return nonzero iff C has exactly one bit set if it is interpreted
2529 as a 32-bit constant. */
2532 log2constp (unsigned HOST_WIDE_INT c
)
2535 return c
!= 0 && (c
& (c
-1)) == 0;
2538 /* Returns the number of consecutive least significant zeros in the binary
2539 representation of *V.
2540 We modify *V to contain the original value arithmetically shifted right by
2541 the number of zeroes. */
2544 shiftr_zero (HOST_WIDE_INT
*v
)
2546 unsigned HOST_WIDE_INT tmp
= *v
;
2547 unsigned HOST_WIDE_INT sgn
;
2553 sgn
= tmp
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1));
2554 while ((tmp
& 0x1) == 0 && n
<= 32)
2556 tmp
= (tmp
>> 1) | sgn
;
2563 /* After reload, split the load of an immediate constant. OPERANDS are the
2564 operands of the movsi_insn pattern which we are splitting. We return
2565 nonzero if we emitted a sequence to load the constant, zero if we emitted
2566 nothing because we want to use the splitter's default sequence. */
2569 split_load_immediate (rtx operands
[])
2571 HOST_WIDE_INT val
= INTVAL (operands
[1]);
2573 HOST_WIDE_INT shifted
= val
;
2574 HOST_WIDE_INT shifted_compl
= ~val
;
2575 int num_zero
= shiftr_zero (&shifted
);
2576 int num_compl_zero
= shiftr_zero (&shifted_compl
);
2577 unsigned int regno
= REGNO (operands
[0]);
2579 /* This case takes care of single-bit set/clear constants, which we could
2580 also implement with BITSET/BITCLR. */
2582 && shifted
>= -32768 && shifted
< 65536
2583 && (D_REGNO_P (regno
)
2584 || (regno
>= REG_P0
&& regno
<= REG_P7
&& num_zero
<= 2)))
2586 emit_insn (gen_movsi (operands
[0], GEN_INT (shifted
)));
2587 emit_insn (gen_ashlsi3 (operands
[0], operands
[0], GEN_INT (num_zero
)));
2592 tmp
|= -(tmp
& 0x8000);
2594 /* If high word has one bit set or clear, try to use a bit operation. */
2595 if (D_REGNO_P (regno
))
2597 if (log2constp (val
& 0xFFFF0000))
2599 emit_insn (gen_movsi (operands
[0], GEN_INT (val
& 0xFFFF)));
2600 emit_insn (gen_iorsi3 (operands
[0], operands
[0], GEN_INT (val
& 0xFFFF0000)));
2603 else if (log2constp (val
| 0xFFFF) && (val
& 0x8000) != 0)
2605 emit_insn (gen_movsi (operands
[0], GEN_INT (tmp
)));
2606 emit_insn (gen_andsi3 (operands
[0], operands
[0], GEN_INT (val
| 0xFFFF)));
2610 if (D_REGNO_P (regno
))
2612 if (tmp
>= -64 && tmp
<= 63)
2614 emit_insn (gen_movsi (operands
[0], GEN_INT (tmp
)));
2615 emit_insn (gen_movstricthi_high (operands
[0], GEN_INT (val
& -65536)));
2619 if ((val
& 0xFFFF0000) == 0)
2621 emit_insn (gen_movsi (operands
[0], const0_rtx
));
2622 emit_insn (gen_movsi_low (operands
[0], operands
[0], operands
[1]));
2626 if ((val
& 0xFFFF0000) == 0xFFFF0000)
2628 emit_insn (gen_movsi (operands
[0], constm1_rtx
));
2629 emit_insn (gen_movsi_low (operands
[0], operands
[0], operands
[1]));
2634 /* Need DREGs for the remaining case. */
2639 && num_compl_zero
&& shifted_compl
>= -64 && shifted_compl
<= 63)
2641 /* If optimizing for size, generate a sequence that has more instructions
2643 emit_insn (gen_movsi (operands
[0], GEN_INT (shifted_compl
)));
2644 emit_insn (gen_ashlsi3 (operands
[0], operands
[0],
2645 GEN_INT (num_compl_zero
)));
2646 emit_insn (gen_one_cmplsi2 (operands
[0], operands
[0]));
2652 /* Return true if the legitimate memory address for a memory operand of mode
2653 MODE. Return false if not. */
2656 bfin_valid_add (enum machine_mode mode
, HOST_WIDE_INT value
)
2658 unsigned HOST_WIDE_INT v
= value
> 0 ? value
: -value
;
2659 int sz
= GET_MODE_SIZE (mode
);
2660 int shift
= sz
== 1 ? 0 : sz
== 2 ? 1 : 2;
2661 /* The usual offsettable_memref machinery doesn't work so well for this
2662 port, so we deal with the problem here. */
2663 if (value
> 0 && sz
== 8)
2665 return (v
& ~(0x7fff << shift
)) == 0;
2669 bfin_valid_reg_p (unsigned int regno
, int strict
, enum machine_mode mode
,
2670 enum rtx_code outer_code
)
2673 return REGNO_OK_FOR_BASE_STRICT_P (regno
, mode
, outer_code
, SCRATCH
);
2675 return REGNO_OK_FOR_BASE_NONSTRICT_P (regno
, mode
, outer_code
, SCRATCH
);
2678 /* Recognize an RTL expression that is a valid memory address for an
2679 instruction. The MODE argument is the machine mode for the MEM expression
2680 that wants to use this address.
2682 Blackfin addressing modes are as follows:
2688 W [ Preg + uimm16m2 ]
2697 bfin_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
2699 switch (GET_CODE (x
)) {
2701 if (bfin_valid_reg_p (REGNO (x
), strict
, mode
, MEM
))
2705 if (REG_P (XEXP (x
, 0))
2706 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, PLUS
)
2707 && ((GET_CODE (XEXP (x
, 1)) == UNSPEC
&& mode
== SImode
)
2708 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2709 && bfin_valid_add (mode
, INTVAL (XEXP (x
, 1))))))
2714 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode
)
2715 && REG_P (XEXP (x
, 0))
2716 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, POST_INC
))
2719 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode
)
2720 && XEXP (x
, 0) == stack_pointer_rtx
2721 && REG_P (XEXP (x
, 0))
2722 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, PRE_DEC
))
2731 /* Decide whether we can force certain constants to memory. If we
2732 decide we can't, the caller should be able to cope with it in
2736 bfin_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
,
2737 rtx x ATTRIBUTE_UNUSED
)
2739 /* We have only one class of non-legitimate constants, and our movsi
2740 expander knows how to handle them. Dropping these constants into the
2741 data section would only shift the problem - we'd still get relocs
2742 outside the object, in the data section rather than the text section. */
2746 /* Ensure that for any constant of the form symbol + offset, the offset
2747 remains within the object. Any other constants are ok.
2748 This ensures that flat binaries never have to deal with relocations
2749 crossing section boundaries. */
2752 bfin_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2755 HOST_WIDE_INT offset
;
2757 if (GET_CODE (x
) != CONST
)
2761 gcc_assert (GET_CODE (x
) == PLUS
);
2765 if (GET_CODE (sym
) != SYMBOL_REF
2766 || GET_CODE (x
) != CONST_INT
)
2768 offset
= INTVAL (x
);
2770 if (SYMBOL_REF_DECL (sym
) == 0)
2773 || offset
>= int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (sym
))))
2780 bfin_rtx_costs (rtx x
, int code_i
, int outer_code_i
, int opno
, int *total
,
2783 enum rtx_code code
= (enum rtx_code
) code_i
;
2784 enum rtx_code outer_code
= (enum rtx_code
) outer_code_i
;
2785 int cost2
= COSTS_N_INSNS (1);
2791 if (outer_code
== SET
|| outer_code
== PLUS
)
2792 *total
= satisfies_constraint_Ks7 (x
) ? 0 : cost2
;
2793 else if (outer_code
== AND
)
2794 *total
= log2constp (~INTVAL (x
)) ? 0 : cost2
;
2795 else if (outer_code
== LE
|| outer_code
== LT
|| outer_code
== EQ
)
2796 *total
= (INTVAL (x
) >= -4 && INTVAL (x
) <= 3) ? 0 : cost2
;
2797 else if (outer_code
== LEU
|| outer_code
== LTU
)
2798 *total
= (INTVAL (x
) >= 0 && INTVAL (x
) <= 7) ? 0 : cost2
;
2799 else if (outer_code
== MULT
)
2800 *total
= (INTVAL (x
) == 2 || INTVAL (x
) == 4) ? 0 : cost2
;
2801 else if (outer_code
== ASHIFT
&& (INTVAL (x
) == 1 || INTVAL (x
) == 2))
2803 else if (outer_code
== ASHIFT
|| outer_code
== ASHIFTRT
2804 || outer_code
== LSHIFTRT
)
2805 *total
= (INTVAL (x
) >= 0 && INTVAL (x
) <= 31) ? 0 : cost2
;
2806 else if (outer_code
== IOR
|| outer_code
== XOR
)
2807 *total
= (INTVAL (x
) & (INTVAL (x
) - 1)) == 0 ? 0 : cost2
;
2816 *total
= COSTS_N_INSNS (2);
2822 if (GET_MODE (x
) == SImode
)
2824 if (GET_CODE (op0
) == MULT
2825 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
2827 HOST_WIDE_INT val
= INTVAL (XEXP (op0
, 1));
2828 if (val
== 2 || val
== 4)
2831 *total
+= rtx_cost (XEXP (op0
, 0), outer_code
, opno
, speed
);
2832 *total
+= rtx_cost (op1
, outer_code
, opno
, speed
);
2837 if (GET_CODE (op0
) != REG
2838 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2839 *total
+= set_src_cost (op0
, speed
);
2840 #if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer
2841 towards creating too many induction variables. */
2842 if (!reg_or_7bit_operand (op1
, SImode
))
2843 *total
+= set_src_cost (op1
, speed
);
2846 else if (GET_MODE (x
) == DImode
)
2849 if (GET_CODE (op1
) != CONST_INT
2850 || !satisfies_constraint_Ks7 (op1
))
2851 *total
+= rtx_cost (op1
, PLUS
, 1, speed
);
2852 if (GET_CODE (op0
) != REG
2853 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2854 *total
+= rtx_cost (op0
, PLUS
, 0, speed
);
2859 if (GET_MODE (x
) == DImode
)
2868 if (GET_MODE (x
) == DImode
)
2875 if (GET_CODE (op0
) != REG
2876 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2877 *total
+= rtx_cost (op0
, code
, 0, speed
);
2887 /* Handle special cases of IOR: rotates, ALIGN insns, movstricthi_high. */
2890 if ((GET_CODE (op0
) == LSHIFTRT
&& GET_CODE (op1
) == ASHIFT
)
2891 || (GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == ZERO_EXTEND
)
2892 || (GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
2893 || (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == CONST_INT
))
2900 if (GET_CODE (op0
) != REG
2901 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2902 *total
+= rtx_cost (op0
, code
, 0, speed
);
2904 if (GET_MODE (x
) == DImode
)
2910 if (GET_MODE (x
) != SImode
)
2915 if (! rhs_andsi3_operand (XEXP (x
, 1), SImode
))
2916 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
2920 if (! regorlog2_operand (XEXP (x
, 1), SImode
))
2921 *total
+= rtx_cost (XEXP (x
, 1), code
, 1, speed
);
2928 if (outer_code
== SET
2929 && XEXP (x
, 1) == const1_rtx
2930 && GET_CODE (XEXP (x
, 2)) == CONST_INT
)
2946 if (GET_CODE (op0
) == GET_CODE (op1
)
2947 && (GET_CODE (op0
) == ZERO_EXTEND
2948 || GET_CODE (op0
) == SIGN_EXTEND
))
2950 *total
= COSTS_N_INSNS (1);
2951 op0
= XEXP (op0
, 0);
2952 op1
= XEXP (op1
, 0);
2955 *total
= COSTS_N_INSNS (1);
2957 *total
= COSTS_N_INSNS (3);
2959 if (GET_CODE (op0
) != REG
2960 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2961 *total
+= rtx_cost (op0
, MULT
, 0, speed
);
2962 if (GET_CODE (op1
) != REG
2963 && (GET_CODE (op1
) != SUBREG
|| GET_CODE (SUBREG_REG (op1
)) != REG
))
2964 *total
+= rtx_cost (op1
, MULT
, 1, speed
);
2970 *total
= COSTS_N_INSNS (32);
2975 if (outer_code
== SET
)
2984 /* Used for communication between {push,pop}_multiple_operation (which
2985 we use not only as a predicate) and the corresponding output functions. */
2986 static int first_preg_to_save
, first_dreg_to_save
;
2987 static int n_regs_to_save
;
2990 push_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2992 int lastdreg
= 8, lastpreg
= 6;
2995 first_preg_to_save
= lastpreg
;
2996 first_dreg_to_save
= lastdreg
;
2997 for (i
= 1, group
= 0; i
< XVECLEN (op
, 0) - 1; i
++)
2999 rtx t
= XVECEXP (op
, 0, i
);
3003 if (GET_CODE (t
) != SET
)
3007 dest
= SET_DEST (t
);
3008 if (GET_CODE (dest
) != MEM
|| ! REG_P (src
))
3010 dest
= XEXP (dest
, 0);
3011 if (GET_CODE (dest
) != PLUS
3012 || ! REG_P (XEXP (dest
, 0))
3013 || REGNO (XEXP (dest
, 0)) != REG_SP
3014 || GET_CODE (XEXP (dest
, 1)) != CONST_INT
3015 || INTVAL (XEXP (dest
, 1)) != -i
* 4)
3018 regno
= REGNO (src
);
3021 if (D_REGNO_P (regno
))
3024 first_dreg_to_save
= lastdreg
= regno
- REG_R0
;
3026 else if (regno
>= REG_P0
&& regno
<= REG_P7
)
3029 first_preg_to_save
= lastpreg
= regno
- REG_P0
;
3039 if (regno
>= REG_P0
&& regno
<= REG_P7
)
3042 first_preg_to_save
= lastpreg
= regno
- REG_P0
;
3044 else if (regno
!= REG_R0
+ lastdreg
+ 1)
3049 else if (group
== 2)
3051 if (regno
!= REG_P0
+ lastpreg
+ 1)
3056 n_regs_to_save
= 8 - first_dreg_to_save
+ 6 - first_preg_to_save
;
3061 pop_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3063 int lastdreg
= 8, lastpreg
= 6;
3066 for (i
= 1, group
= 0; i
< XVECLEN (op
, 0); i
++)
3068 rtx t
= XVECEXP (op
, 0, i
);
3072 if (GET_CODE (t
) != SET
)
3076 dest
= SET_DEST (t
);
3077 if (GET_CODE (src
) != MEM
|| ! REG_P (dest
))
3079 src
= XEXP (src
, 0);
3083 if (! REG_P (src
) || REGNO (src
) != REG_SP
)
3086 else if (GET_CODE (src
) != PLUS
3087 || ! REG_P (XEXP (src
, 0))
3088 || REGNO (XEXP (src
, 0)) != REG_SP
3089 || GET_CODE (XEXP (src
, 1)) != CONST_INT
3090 || INTVAL (XEXP (src
, 1)) != (i
- 1) * 4)
3093 regno
= REGNO (dest
);
3096 if (regno
== REG_R7
)
3101 else if (regno
!= REG_P0
+ lastpreg
- 1)
3106 else if (group
== 1)
3108 if (regno
!= REG_R0
+ lastdreg
- 1)
3114 first_dreg_to_save
= lastdreg
;
3115 first_preg_to_save
= lastpreg
;
3116 n_regs_to_save
= 8 - first_dreg_to_save
+ 6 - first_preg_to_save
;
3120 /* Emit assembly code for one multi-register push described by INSN, with
3121 operands in OPERANDS. */
3124 output_push_multiple (rtx insn
, rtx
*operands
)
3129 /* Validate the insn again, and compute first_[dp]reg_to_save. */
3130 ok
= push_multiple_operation (PATTERN (insn
), VOIDmode
);
3133 if (first_dreg_to_save
== 8)
3134 sprintf (buf
, "[--sp] = ( p5:%d );\n", first_preg_to_save
);
3135 else if (first_preg_to_save
== 6)
3136 sprintf (buf
, "[--sp] = ( r7:%d );\n", first_dreg_to_save
);
3138 sprintf (buf
, "[--sp] = ( r7:%d, p5:%d );\n",
3139 first_dreg_to_save
, first_preg_to_save
);
3141 output_asm_insn (buf
, operands
);
3144 /* Emit assembly code for one multi-register pop described by INSN, with
3145 operands in OPERANDS. */
3148 output_pop_multiple (rtx insn
, rtx
*operands
)
3153 /* Validate the insn again, and compute first_[dp]reg_to_save. */
3154 ok
= pop_multiple_operation (PATTERN (insn
), VOIDmode
);
3157 if (first_dreg_to_save
== 8)
3158 sprintf (buf
, "( p5:%d ) = [sp++];\n", first_preg_to_save
);
3159 else if (first_preg_to_save
== 6)
3160 sprintf (buf
, "( r7:%d ) = [sp++];\n", first_dreg_to_save
);
3162 sprintf (buf
, "( r7:%d, p5:%d ) = [sp++];\n",
3163 first_dreg_to_save
, first_preg_to_save
);
3165 output_asm_insn (buf
, operands
);
3168 /* Adjust DST and SRC by OFFSET bytes, and generate one move in mode MODE. */
3171 single_move_for_movmem (rtx dst
, rtx src
, enum machine_mode mode
, HOST_WIDE_INT offset
)
3173 rtx scratch
= gen_reg_rtx (mode
);
3176 srcmem
= adjust_address_nv (src
, mode
, offset
);
3177 dstmem
= adjust_address_nv (dst
, mode
, offset
);
3178 emit_move_insn (scratch
, srcmem
);
3179 emit_move_insn (dstmem
, scratch
);
3182 /* Expand a string move operation of COUNT_EXP bytes from SRC to DST, with
3183 alignment ALIGN_EXP. Return true if successful, false if we should fall
3184 back on a different method. */
3187 bfin_expand_movmem (rtx dst
, rtx src
, rtx count_exp
, rtx align_exp
)
3189 rtx srcreg
, destreg
, countreg
;
3190 HOST_WIDE_INT align
= 0;
3191 unsigned HOST_WIDE_INT count
= 0;
3193 if (GET_CODE (align_exp
) == CONST_INT
)
3194 align
= INTVAL (align_exp
);
3195 if (GET_CODE (count_exp
) == CONST_INT
)
3197 count
= INTVAL (count_exp
);
3199 if (!TARGET_INLINE_ALL_STRINGOPS
&& count
> 64)
3204 /* If optimizing for size, only do single copies inline. */
3207 if (count
== 2 && align
< 2)
3209 if (count
== 4 && align
< 4)
3211 if (count
!= 1 && count
!= 2 && count
!= 4)
3214 if (align
< 2 && count
!= 1)
3217 destreg
= copy_to_mode_reg (Pmode
, XEXP (dst
, 0));
3218 if (destreg
!= XEXP (dst
, 0))
3219 dst
= replace_equiv_address_nv (dst
, destreg
);
3220 srcreg
= copy_to_mode_reg (Pmode
, XEXP (src
, 0));
3221 if (srcreg
!= XEXP (src
, 0))
3222 src
= replace_equiv_address_nv (src
, srcreg
);
3224 if (count
!= 0 && align
>= 2)
3226 unsigned HOST_WIDE_INT offset
= 0;
3230 if ((count
& ~3) == 4)
3232 single_move_for_movmem (dst
, src
, SImode
, offset
);
3235 else if (count
& ~3)
3237 HOST_WIDE_INT new_count
= ((count
>> 2) & 0x3fffffff) - 1;
3238 countreg
= copy_to_mode_reg (Pmode
, GEN_INT (new_count
));
3240 emit_insn (gen_rep_movsi (destreg
, srcreg
, countreg
, destreg
, srcreg
));
3241 cfun
->machine
->has_loopreg_clobber
= true;
3245 single_move_for_movmem (dst
, src
, HImode
, offset
);
3251 if ((count
& ~1) == 2)
3253 single_move_for_movmem (dst
, src
, HImode
, offset
);
3256 else if (count
& ~1)
3258 HOST_WIDE_INT new_count
= ((count
>> 1) & 0x7fffffff) - 1;
3259 countreg
= copy_to_mode_reg (Pmode
, GEN_INT (new_count
));
3261 emit_insn (gen_rep_movhi (destreg
, srcreg
, countreg
, destreg
, srcreg
));
3262 cfun
->machine
->has_loopreg_clobber
= true;
3267 single_move_for_movmem (dst
, src
, QImode
, offset
);
3274 /* Compute the alignment for a local variable.
3275 TYPE is the data type, and ALIGN is the alignment that
3276 the object would ordinarily have. The value of this macro is used
3277 instead of that alignment to align the object. */
3280 bfin_local_alignment (tree type
, unsigned align
)
3282 /* Increasing alignment for (relatively) big types allows the builtin
3283 memcpy can use 32 bit loads/stores. */
3284 if (TYPE_SIZE (type
)
3285 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
3286 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) > 8
3287 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 32)
3292 /* Implement TARGET_SCHED_ISSUE_RATE. */
3295 bfin_issue_rate (void)
3301 bfin_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3303 enum attr_type dep_insn_type
;
3304 int dep_insn_code_number
;
3306 /* Anti and output dependencies have zero cost. */
3307 if (REG_NOTE_KIND (link
) != 0)
3310 dep_insn_code_number
= recog_memoized (dep_insn
);
3312 /* If we can't recognize the insns, we can't really do anything. */
3313 if (dep_insn_code_number
< 0 || recog_memoized (insn
) < 0)
3316 dep_insn_type
= get_attr_type (dep_insn
);
3318 if (dep_insn_type
== TYPE_MOVE
|| dep_insn_type
== TYPE_MCLD
)
3320 rtx pat
= PATTERN (dep_insn
);
3323 if (GET_CODE (pat
) == PARALLEL
)
3324 pat
= XVECEXP (pat
, 0, 0);
3325 dest
= SET_DEST (pat
);
3326 src
= SET_SRC (pat
);
3327 if (! ADDRESS_REGNO_P (REGNO (dest
))
3328 || ! (MEM_P (src
) || D_REGNO_P (REGNO (src
))))
3330 return cost
+ (dep_insn_type
== TYPE_MOVE
? 4 : 3);
3336 /* This function acts like NEXT_INSN, but is aware of three-insn bundles and
3337 skips all subsequent parallel instructions if INSN is the start of such
3340 find_next_insn_start (rtx insn
)
3342 if (GET_MODE (insn
) == SImode
)
3344 while (GET_MODE (insn
) != QImode
)
3345 insn
= NEXT_INSN (insn
);
3347 return NEXT_INSN (insn
);
3350 /* This function acts like PREV_INSN, but is aware of three-insn bundles and
3351 skips all subsequent parallel instructions if INSN is the start of such
3354 find_prev_insn_start (rtx insn
)
3356 insn
= PREV_INSN (insn
);
3357 gcc_assert (GET_MODE (insn
) != SImode
);
3358 if (GET_MODE (insn
) == QImode
)
3360 while (GET_MODE (PREV_INSN (insn
)) == SImode
)
3361 insn
= PREV_INSN (insn
);
3366 /* Increment the counter for the number of loop instructions in the
3367 current function. */
3370 bfin_hardware_loop (void)
3372 cfun
->machine
->has_hardware_loops
++;
3375 /* Maximum loop nesting depth. */
3376 #define MAX_LOOP_DEPTH 2
3378 /* Maximum size of a loop. */
3379 #define MAX_LOOP_LENGTH 2042
3381 /* Maximum distance of the LSETUP instruction from the loop start. */
3382 #define MAX_LSETUP_DISTANCE 30
3384 /* Estimate the length of INSN conservatively. */
3387 length_for_loop (rtx insn
)
3390 if (JUMP_P (insn
) && any_condjump_p (insn
) && !optimize_size
)
3392 if (ENABLE_WA_SPECULATIVE_SYNCS
)
3394 else if (ENABLE_WA_SPECULATIVE_LOADS
)
3397 else if (LABEL_P (insn
))
3399 if (ENABLE_WA_SPECULATIVE_SYNCS
)
3403 if (NONDEBUG_INSN_P (insn
))
3404 length
+= get_attr_length (insn
);
3409 /* Optimize LOOP. */
3412 hwloop_optimize (hwloop_info loop
)
3415 rtx insn
, last_insn
;
3416 rtx loop_init
, start_label
, end_label
;
3417 rtx iter_reg
, scratchreg
, scratch_init
, scratch_init_insn
;
3418 rtx lc_reg
, lt_reg
, lb_reg
;
3421 bool clobber0
, clobber1
;
3423 if (loop
->depth
> MAX_LOOP_DEPTH
)
3426 fprintf (dump_file
, ";; loop %d too deep\n", loop
->loop_no
);
3430 /* Get the loop iteration register. */
3431 iter_reg
= loop
->iter_reg
;
3433 gcc_assert (REG_P (iter_reg
));
3435 scratchreg
= NULL_RTX
;
3436 scratch_init
= iter_reg
;
3437 scratch_init_insn
= NULL_RTX
;
3438 if (!PREG_P (iter_reg
) && loop
->incoming_src
)
3440 basic_block bb_in
= loop
->incoming_src
;
3442 for (i
= REG_P0
; i
<= REG_P5
; i
++)
3443 if ((df_regs_ever_live_p (i
)
3444 || (funkind (TREE_TYPE (current_function_decl
)) == SUBROUTINE
3445 && call_used_regs
[i
]))
3446 && !REGNO_REG_SET_P (df_get_live_out (bb_in
), i
))
3448 scratchreg
= gen_rtx_REG (SImode
, i
);
3451 for (insn
= BB_END (bb_in
); insn
!= BB_HEAD (bb_in
);
3452 insn
= PREV_INSN (insn
))
3455 if (NOTE_P (insn
) || BARRIER_P (insn
))
3457 set
= single_set (insn
);
3458 if (set
&& rtx_equal_p (SET_DEST (set
), iter_reg
))
3460 if (CONSTANT_P (SET_SRC (set
)))
3462 scratch_init
= SET_SRC (set
);
3463 scratch_init_insn
= insn
;
3467 else if (reg_mentioned_p (iter_reg
, PATTERN (insn
)))
3472 if (loop
->incoming_src
)
3474 /* Make sure the predecessor is before the loop start label, as required by
3475 the LSETUP instruction. */
3477 insn
= BB_END (loop
->incoming_src
);
3478 /* If we have to insert the LSETUP before a jump, count that jump in the
3480 if (VEC_length (edge
, loop
->incoming
) > 1
3481 || !(VEC_last (edge
, loop
->incoming
)->flags
& EDGE_FALLTHRU
))
3483 gcc_assert (JUMP_P (insn
));
3484 insn
= PREV_INSN (insn
);
3487 for (; insn
&& insn
!= loop
->start_label
; insn
= NEXT_INSN (insn
))
3488 length
+= length_for_loop (insn
);
3493 fprintf (dump_file
, ";; loop %d lsetup not before loop_start\n",
3498 /* Account for the pop of a scratch register where necessary. */
3499 if (!PREG_P (iter_reg
) && scratchreg
== NULL_RTX
3500 && ENABLE_WA_LOAD_LCREGS
)
3503 if (length
> MAX_LSETUP_DISTANCE
)
3506 fprintf (dump_file
, ";; loop %d lsetup too far away\n", loop
->loop_no
);
3511 /* Check if start_label appears before loop_end and calculate the
3512 offset between them. We calculate the length of instructions
3515 for (insn
= loop
->start_label
;
3516 insn
&& insn
!= loop
->loop_end
;
3517 insn
= NEXT_INSN (insn
))
3518 length
+= length_for_loop (insn
);
3523 fprintf (dump_file
, ";; loop %d start_label not before loop_end\n",
3528 loop
->length
= length
;
3529 if (loop
->length
> MAX_LOOP_LENGTH
)
3532 fprintf (dump_file
, ";; loop %d too long\n", loop
->loop_no
);
3536 /* Scan all the blocks to make sure they don't use iter_reg. */
3537 if (loop
->iter_reg_used
|| loop
->iter_reg_used_outside
)
3540 fprintf (dump_file
, ";; loop %d uses iterator\n", loop
->loop_no
);
3544 clobber0
= (TEST_HARD_REG_BIT (loop
->regs_set_in_loop
, REG_LC0
)
3545 || TEST_HARD_REG_BIT (loop
->regs_set_in_loop
, REG_LB0
)
3546 || TEST_HARD_REG_BIT (loop
->regs_set_in_loop
, REG_LT0
));
3547 clobber1
= (TEST_HARD_REG_BIT (loop
->regs_set_in_loop
, REG_LC1
)
3548 || TEST_HARD_REG_BIT (loop
->regs_set_in_loop
, REG_LB1
)
3549 || TEST_HARD_REG_BIT (loop
->regs_set_in_loop
, REG_LT1
));
3550 if (clobber0
&& clobber1
)
3553 fprintf (dump_file
, ";; loop %d no loop reg available\n",
3558 /* There should be an instruction before the loop_end instruction
3559 in the same basic block. And the instruction must not be
3561 - CONDITIONAL BRANCH
3565 - Returns (RTS, RTN, etc.) */
3568 last_insn
= find_prev_insn_start (loop
->loop_end
);
3572 for (; last_insn
!= BB_HEAD (bb
);
3573 last_insn
= find_prev_insn_start (last_insn
))
3574 if (NONDEBUG_INSN_P (last_insn
))
3577 if (last_insn
!= BB_HEAD (bb
))
3580 if (single_pred_p (bb
)
3581 && single_pred_edge (bb
)->flags
& EDGE_FALLTHRU
3582 && single_pred (bb
) != ENTRY_BLOCK_PTR
)
3584 bb
= single_pred (bb
);
3585 last_insn
= BB_END (bb
);
3590 last_insn
= NULL_RTX
;
3598 fprintf (dump_file
, ";; loop %d has no last instruction\n",
3603 if (JUMP_P (last_insn
) && !any_condjump_p (last_insn
))
3606 fprintf (dump_file
, ";; loop %d has bad last instruction\n",
3610 /* In all other cases, try to replace a bad last insn with a nop. */
3611 else if (JUMP_P (last_insn
)
3612 || CALL_P (last_insn
)
3613 || get_attr_type (last_insn
) == TYPE_SYNC
3614 || get_attr_type (last_insn
) == TYPE_CALL
3615 || get_attr_seq_insns (last_insn
) == SEQ_INSNS_MULTI
3616 || recog_memoized (last_insn
) == CODE_FOR_return_internal
3617 || GET_CODE (PATTERN (last_insn
)) == ASM_INPUT
3618 || asm_noperands (PATTERN (last_insn
)) >= 0)
3620 if (loop
->length
+ 2 > MAX_LOOP_LENGTH
)
3623 fprintf (dump_file
, ";; loop %d too long\n", loop
->loop_no
);
3627 fprintf (dump_file
, ";; loop %d has bad last insn; replace with nop\n",
3630 last_insn
= emit_insn_after (gen_forced_nop (), last_insn
);
3633 loop
->last_insn
= last_insn
;
3635 /* The loop is good for replacement. */
3636 start_label
= loop
->start_label
;
3637 end_label
= gen_label_rtx ();
3638 iter_reg
= loop
->iter_reg
;
3640 if (loop
->depth
== 1 && !clobber1
)
3642 lc_reg
= gen_rtx_REG (SImode
, REG_LC1
);
3643 lb_reg
= gen_rtx_REG (SImode
, REG_LB1
);
3644 lt_reg
= gen_rtx_REG (SImode
, REG_LT1
);
3645 SET_HARD_REG_BIT (loop
->regs_set_in_loop
, REG_LC1
);
3649 lc_reg
= gen_rtx_REG (SImode
, REG_LC0
);
3650 lb_reg
= gen_rtx_REG (SImode
, REG_LB0
);
3651 lt_reg
= gen_rtx_REG (SImode
, REG_LT0
);
3652 SET_HARD_REG_BIT (loop
->regs_set_in_loop
, REG_LC0
);
3655 loop
->end_label
= end_label
;
3657 /* Create a sequence containing the loop setup. */
3660 /* LSETUP only accepts P registers. If we have one, we can use it,
3661 otherwise there are several ways of working around the problem.
3662 If we're not affected by anomaly 312, we can load the LC register
3663 from any iteration register, and use LSETUP without initialization.
3664 If we've found a P scratch register that's not live here, we can
3665 instead copy the iter_reg into that and use an initializing LSETUP.
3666 If all else fails, push and pop P0 and use it as a scratch. */
3667 if (P_REGNO_P (REGNO (iter_reg
)))
3669 loop_init
= gen_lsetup_with_autoinit (lt_reg
, start_label
,
3672 seq_end
= emit_insn (loop_init
);
3674 else if (!ENABLE_WA_LOAD_LCREGS
&& DPREG_P (iter_reg
))
3676 emit_insn (gen_movsi (lc_reg
, iter_reg
));
3677 loop_init
= gen_lsetup_without_autoinit (lt_reg
, start_label
,
3680 seq_end
= emit_insn (loop_init
);
3682 else if (scratchreg
!= NULL_RTX
)
3684 emit_insn (gen_movsi (scratchreg
, scratch_init
));
3685 loop_init
= gen_lsetup_with_autoinit (lt_reg
, start_label
,
3687 lc_reg
, scratchreg
);
3688 seq_end
= emit_insn (loop_init
);
3689 if (scratch_init_insn
!= NULL_RTX
)
3690 delete_insn (scratch_init_insn
);
3694 rtx p0reg
= gen_rtx_REG (SImode
, REG_P0
);
3695 rtx push
= gen_frame_mem (SImode
,
3696 gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
));
3697 rtx pop
= gen_frame_mem (SImode
,
3698 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3699 emit_insn (gen_movsi (push
, p0reg
));
3700 emit_insn (gen_movsi (p0reg
, scratch_init
));
3701 loop_init
= gen_lsetup_with_autoinit (lt_reg
, start_label
,
3704 emit_insn (loop_init
);
3705 seq_end
= emit_insn (gen_movsi (p0reg
, pop
));
3706 if (scratch_init_insn
!= NULL_RTX
)
3707 delete_insn (scratch_init_insn
);
3712 fprintf (dump_file
, ";; replacing loop %d initializer with\n",
3714 print_rtl_single (dump_file
, loop_init
);
3715 fprintf (dump_file
, ";; replacing loop %d terminator with\n",
3717 print_rtl_single (dump_file
, loop
->loop_end
);
3720 /* If the loop isn't entered at the top, also create a jump to the entry
3722 if (!loop
->incoming_src
&& loop
->head
!= loop
->incoming_dest
)
3724 rtx label
= BB_HEAD (loop
->incoming_dest
);
3725 /* If we're jumping to the final basic block in the loop, and there's
3726 only one cheap instruction before the end (typically an increment of
3727 an induction variable), we can just emit a copy here instead of a
3729 if (loop
->incoming_dest
== loop
->tail
3730 && next_real_insn (label
) == last_insn
3731 && asm_noperands (last_insn
) < 0
3732 && GET_CODE (PATTERN (last_insn
)) == SET
)
3734 seq_end
= emit_insn (copy_rtx (PATTERN (last_insn
)));
3738 emit_jump_insn (gen_jump (label
));
3739 seq_end
= emit_barrier ();
3746 if (loop
->incoming_src
)
3748 rtx prev
= BB_END (loop
->incoming_src
);
3749 if (VEC_length (edge
, loop
->incoming
) > 1
3750 || !(VEC_last (edge
, loop
->incoming
)->flags
& EDGE_FALLTHRU
))
3752 gcc_assert (JUMP_P (prev
));
3753 prev
= PREV_INSN (prev
);
3755 emit_insn_after (seq
, prev
);
3763 #ifdef ENABLE_CHECKING
3764 if (loop
->head
!= loop
->incoming_dest
)
3766 /* We aren't entering the loop at the top. Since we've established
3767 that the loop is entered only at one point, this means there
3768 can't be fallthru edges into the head. Any such fallthru edges
3769 would become invalid when we insert the new block, so verify
3770 that this does not in fact happen. */
3771 FOR_EACH_EDGE (e
, ei
, loop
->head
->preds
)
3772 gcc_assert (!(e
->flags
& EDGE_FALLTHRU
));
3776 emit_insn_before (seq
, BB_HEAD (loop
->head
));
3777 seq
= emit_label_before (gen_label_rtx (), seq
);
3779 new_bb
= create_basic_block (seq
, seq_end
, loop
->head
->prev_bb
);
3780 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
3782 if (!(e
->flags
& EDGE_FALLTHRU
)
3783 || e
->dest
!= loop
->head
)
3784 redirect_edge_and_branch_force (e
, new_bb
);
3786 redirect_edge_succ (e
, new_bb
);
3788 e
= make_edge (new_bb
, loop
->head
, 0);
3791 delete_insn (loop
->loop_end
);
3792 /* Insert the loop end label before the last instruction of the loop. */
3793 emit_label_before (loop
->end_label
, loop
->last_insn
);
3798 /* A callback for the hw-doloop pass. Called when a loop we have discovered
3799 turns out not to be optimizable; we have to split the doloop_end pattern
3800 into a subtract and a test. */
3802 hwloop_fail (hwloop_info loop
)
3804 rtx insn
= loop
->loop_end
;
3806 if (DPREG_P (loop
->iter_reg
))
3808 /* If loop->iter_reg is a DREG or PREG, we can split it here
3809 without scratch register. */
3812 emit_insn_before (gen_addsi3 (loop
->iter_reg
,
3817 test
= gen_rtx_NE (VOIDmode
, loop
->iter_reg
, const0_rtx
);
3818 insn
= emit_jump_insn_before (gen_cbranchsi4 (test
,
3819 loop
->iter_reg
, const0_rtx
,
3823 JUMP_LABEL (insn
) = loop
->start_label
;
3824 LABEL_NUSES (loop
->start_label
)++;
3825 delete_insn (loop
->loop_end
);
3829 splitting_loops
= 1;
3830 try_split (PATTERN (insn
), insn
, 1);
3831 splitting_loops
= 0;
3835 /* A callback for the hw-doloop pass. This function examines INSN; if
3836 it is a loop_end pattern we recognize, return the reg rtx for the
3837 loop counter. Otherwise, return NULL_RTX. */
3840 hwloop_pattern_reg (rtx insn
)
3844 if (!JUMP_P (insn
) || recog_memoized (insn
) != CODE_FOR_loop_end
)
3847 reg
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 1));
3853 static struct hw_doloop_hooks bfin_doloop_hooks
=
3860 /* Run from machine_dependent_reorg, this pass looks for doloop_end insns
3861 and tries to rewrite the RTL of these loops so that proper Blackfin
3862 hardware loops are generated. */
3865 bfin_reorg_loops (void)
3867 reorg_loops (true, &bfin_doloop_hooks
);
3870 /* Possibly generate a SEQUENCE out of three insns found in SLOT.
3871 Returns true if we modified the insn chain, false otherwise. */
3873 gen_one_bundle (rtx slot
[3])
3875 gcc_assert (slot
[1] != NULL_RTX
);
3877 /* Don't add extra NOPs if optimizing for size. */
3879 && (slot
[0] == NULL_RTX
|| slot
[2] == NULL_RTX
))
3882 /* Verify that we really can do the multi-issue. */
3885 rtx t
= NEXT_INSN (slot
[0]);
3886 while (t
!= slot
[1])
3888 if (GET_CODE (t
) != NOTE
3889 || NOTE_KIND (t
) != NOTE_INSN_DELETED
)
3896 rtx t
= NEXT_INSN (slot
[1]);
3897 while (t
!= slot
[2])
3899 if (GET_CODE (t
) != NOTE
3900 || NOTE_KIND (t
) != NOTE_INSN_DELETED
)
3906 if (slot
[0] == NULL_RTX
)
3908 slot
[0] = emit_insn_before (gen_mnop (), slot
[1]);
3909 df_insn_rescan (slot
[0]);
3911 if (slot
[2] == NULL_RTX
)
3913 slot
[2] = emit_insn_after (gen_forced_nop (), slot
[1]);
3914 df_insn_rescan (slot
[2]);
3917 /* Avoid line number information being printed inside one bundle. */
3918 if (INSN_LOCATOR (slot
[1])
3919 && INSN_LOCATOR (slot
[1]) != INSN_LOCATOR (slot
[0]))
3920 INSN_LOCATOR (slot
[1]) = INSN_LOCATOR (slot
[0]);
3921 if (INSN_LOCATOR (slot
[2])
3922 && INSN_LOCATOR (slot
[2]) != INSN_LOCATOR (slot
[0]))
3923 INSN_LOCATOR (slot
[2]) = INSN_LOCATOR (slot
[0]);
3925 /* Terminate them with "|| " instead of ";" in the output. */
3926 PUT_MODE (slot
[0], SImode
);
3927 PUT_MODE (slot
[1], SImode
);
3928 /* Terminate the bundle, for the benefit of reorder_var_tracking_notes. */
3929 PUT_MODE (slot
[2], QImode
);
3933 /* Go through all insns, and use the information generated during scheduling
3934 to generate SEQUENCEs to represent bundles of instructions issued
3938 bfin_gen_bundles (void)
3947 slot
[0] = slot
[1] = slot
[2] = NULL_RTX
;
3948 for (insn
= BB_HEAD (bb
);; insn
= next
)
3951 rtx delete_this
= NULL_RTX
;
3953 if (NONDEBUG_INSN_P (insn
))
3955 enum attr_type type
= get_attr_type (insn
);
3957 if (type
== TYPE_STALL
)
3959 gcc_assert (n_filled
== 0);
3964 if (type
== TYPE_DSP32
|| type
== TYPE_DSP32SHIFTIMM
)
3966 else if (slot
[1] == NULL_RTX
)
3974 next
= NEXT_INSN (insn
);
3975 while (next
&& insn
!= BB_END (bb
)
3977 && GET_CODE (PATTERN (next
)) != USE
3978 && GET_CODE (PATTERN (next
)) != CLOBBER
))
3981 next
= NEXT_INSN (insn
);
3984 /* BB_END can change due to emitting extra NOPs, so check here. */
3985 at_end
= insn
== BB_END (bb
);
3986 if (delete_this
== NULL_RTX
&& (at_end
|| GET_MODE (next
) == TImode
))
3989 || !gen_one_bundle (slot
))
3990 && slot
[0] != NULL_RTX
)
3992 rtx pat
= PATTERN (slot
[0]);
3993 if (GET_CODE (pat
) == SET
3994 && GET_CODE (SET_SRC (pat
)) == UNSPEC
3995 && XINT (SET_SRC (pat
), 1) == UNSPEC_32BIT
)
3997 SET_SRC (pat
) = XVECEXP (SET_SRC (pat
), 0, 0);
3998 INSN_CODE (slot
[0]) = -1;
3999 df_insn_rescan (slot
[0]);
4003 slot
[0] = slot
[1] = slot
[2] = NULL_RTX
;
4005 if (delete_this
!= NULL_RTX
)
4006 delete_insn (delete_this
);
4013 /* Ensure that no var tracking notes are emitted in the middle of a
4014 three-instruction bundle. */
4017 reorder_var_tracking_notes (void)
4023 rtx queue
= NULL_RTX
;
4024 bool in_bundle
= false;
4026 for (insn
= BB_HEAD (bb
); insn
!= BB_END (bb
); insn
= next
)
4028 next
= NEXT_INSN (insn
);
4032 /* Emit queued up notes at the last instruction of a bundle. */
4033 if (GET_MODE (insn
) == QImode
)
4037 rtx next_queue
= PREV_INSN (queue
);
4038 PREV_INSN (NEXT_INSN (insn
)) = queue
;
4039 NEXT_INSN (queue
) = NEXT_INSN (insn
);
4040 NEXT_INSN (insn
) = queue
;
4041 PREV_INSN (queue
) = insn
;
4046 else if (GET_MODE (insn
) == SImode
)
4049 else if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_VAR_LOCATION
)
4053 rtx prev
= PREV_INSN (insn
);
4054 PREV_INSN (next
) = prev
;
4055 NEXT_INSN (prev
) = next
;
4057 PREV_INSN (insn
) = queue
;
4065 /* On some silicon revisions, functions shorter than a certain number of cycles
4066 can cause unpredictable behaviour. Work around this by adding NOPs as
4069 workaround_rts_anomaly (void)
4071 rtx insn
, first_insn
= NULL_RTX
;
4074 if (! ENABLE_WA_RETS
)
4077 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4081 if (BARRIER_P (insn
))
4084 if (NOTE_P (insn
) || LABEL_P (insn
))
4087 if (first_insn
== NULL_RTX
)
4089 pat
= PATTERN (insn
);
4090 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
4091 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
4092 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
4100 if (recog_memoized (insn
) == CODE_FOR_return_internal
)
4103 /* Nothing to worry about for direct jumps. */
4104 if (!any_condjump_p (insn
))
4110 else if (INSN_P (insn
))
4112 rtx pat
= PATTERN (insn
);
4113 int this_cycles
= 1;
4115 if (GET_CODE (pat
) == PARALLEL
)
4117 if (push_multiple_operation (pat
, VOIDmode
)
4118 || pop_multiple_operation (pat
, VOIDmode
))
4119 this_cycles
= n_regs_to_save
;
4123 int icode
= recog_memoized (insn
);
4125 if (icode
== CODE_FOR_link
)
4127 else if (icode
== CODE_FOR_unlink
)
4129 else if (icode
== CODE_FOR_mulsi3
)
4132 if (this_cycles
>= cycles
)
4135 cycles
-= this_cycles
;
4140 emit_insn_before (gen_nop (), first_insn
);
4145 /* Return an insn type for INSN that can be used by the caller for anomaly
4146 workarounds. This differs from plain get_attr_type in that it handles
4149 static enum attr_type
4150 type_for_anomaly (rtx insn
)
4152 rtx pat
= PATTERN (insn
);
4153 if (GET_CODE (pat
) == SEQUENCE
)
4156 t
= get_attr_type (XVECEXP (pat
, 0, 1));
4159 t
= get_attr_type (XVECEXP (pat
, 0, 2));
4165 return get_attr_type (insn
);
4168 /* Return true iff the address found in MEM is based on the register
4169 NP_REG and optionally has a positive offset. */
4171 harmless_null_pointer_p (rtx mem
, int np_reg
)
4173 mem
= XEXP (mem
, 0);
4174 if (GET_CODE (mem
) == POST_INC
|| GET_CODE (mem
) == POST_DEC
)
4175 mem
= XEXP (mem
, 0);
4176 if (REG_P (mem
) && (int) REGNO (mem
) == np_reg
)
4178 if (GET_CODE (mem
) == PLUS
4179 && REG_P (XEXP (mem
, 0)) && (int) REGNO (XEXP (mem
, 0)) == np_reg
)
4181 mem
= XEXP (mem
, 1);
4182 if (GET_CODE (mem
) == CONST_INT
&& INTVAL (mem
) > 0)
4188 /* Return nonzero if INSN contains any loads that may trap. */
4191 trapping_loads_p (rtx insn
, int np_reg
, bool after_np_branch
)
4193 rtx mem
= SET_SRC (single_set (insn
));
4195 if (!after_np_branch
)
4197 return ((np_reg
== -1 || !harmless_null_pointer_p (mem
, np_reg
))
4198 && may_trap_p (mem
));
4201 /* Return INSN if it is of TYPE_MCLD. Alternatively, if INSN is the start of
4202 a three-insn bundle, see if one of them is a load and return that if so.
4203 Return NULL_RTX if the insn does not contain loads. */
4205 find_load (rtx insn
)
4207 if (!NONDEBUG_INSN_P (insn
))
4209 if (get_attr_type (insn
) == TYPE_MCLD
)
4211 if (GET_MODE (insn
) != SImode
)
4214 insn
= NEXT_INSN (insn
);
4215 if ((GET_MODE (insn
) == SImode
|| GET_MODE (insn
) == QImode
)
4216 && get_attr_type (insn
) == TYPE_MCLD
)
4218 } while (GET_MODE (insn
) != QImode
);
4222 /* Determine whether PAT is an indirect call pattern. */
4224 indirect_call_p (rtx pat
)
4226 if (GET_CODE (pat
) == PARALLEL
)
4227 pat
= XVECEXP (pat
, 0, 0);
4228 if (GET_CODE (pat
) == SET
)
4229 pat
= SET_SRC (pat
);
4230 gcc_assert (GET_CODE (pat
) == CALL
);
4231 pat
= XEXP (pat
, 0);
4232 gcc_assert (GET_CODE (pat
) == MEM
);
4233 pat
= XEXP (pat
, 0);
4238 /* During workaround_speculation, track whether we're in the shadow of a
4239 conditional branch that tests a P register for NULL. If so, we can omit
4240 emitting NOPs if we see a load from that P register, since a speculative
4241 access at address 0 isn't a problem, and the load is executed in all other
4243 Global for communication with note_np_check_stores through note_stores.
4245 int np_check_regno
= -1;
4246 bool np_after_branch
= false;
4248 /* Subroutine of workaround_speculation, called through note_stores. */
4250 note_np_check_stores (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
4251 void *data ATTRIBUTE_UNUSED
)
4253 if (REG_P (x
) && (REGNO (x
) == REG_CC
|| (int) REGNO (x
) == np_check_regno
))
4254 np_check_regno
= -1;
4258 workaround_speculation (void)
4261 rtx last_condjump
= NULL_RTX
;
4262 int cycles_since_jump
= INT_MAX
;
4263 int delay_added
= 0;
4265 if (! ENABLE_WA_SPECULATIVE_LOADS
&& ! ENABLE_WA_SPECULATIVE_SYNCS
4266 && ! ENABLE_WA_INDIRECT_CALLS
)
4269 /* First pass: find predicted-false branches; if something after them
4270 needs nops, insert them or change the branch to predict true. */
4271 for (insn
= get_insns (); insn
; insn
= next
)
4274 int delay_needed
= 0;
4276 next
= find_next_insn_start (insn
);
4278 if (NOTE_P (insn
) || BARRIER_P (insn
))
4283 np_check_regno
= -1;
4287 pat
= PATTERN (insn
);
4288 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
4289 || GET_CODE (pat
) == ADDR_VEC
|| GET_CODE (pat
) == ADDR_DIFF_VEC
)
4292 if (GET_CODE (pat
) == ASM_INPUT
|| asm_noperands (pat
) >= 0)
4294 np_check_regno
= -1;
4300 /* Is this a condjump based on a null pointer comparison we saw
4302 if (np_check_regno
!= -1
4303 && recog_memoized (insn
) == CODE_FOR_cbranchbi4
)
4305 rtx op
= XEXP (SET_SRC (PATTERN (insn
)), 0);
4306 gcc_assert (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
4307 if (GET_CODE (op
) == NE
)
4308 np_after_branch
= true;
4310 if (any_condjump_p (insn
)
4311 && ! cbranch_predicted_taken_p (insn
))
4313 last_condjump
= insn
;
4315 cycles_since_jump
= 0;
4318 cycles_since_jump
= INT_MAX
;
4320 else if (CALL_P (insn
))
4322 np_check_regno
= -1;
4323 if (cycles_since_jump
< INT_MAX
)
4324 cycles_since_jump
++;
4325 if (indirect_call_p (pat
) && ENABLE_WA_INDIRECT_CALLS
)
4330 else if (NONDEBUG_INSN_P (insn
))
4332 rtx load_insn
= find_load (insn
);
4333 enum attr_type type
= type_for_anomaly (insn
);
4335 if (cycles_since_jump
< INT_MAX
)
4336 cycles_since_jump
++;
4338 /* Detect a comparison of a P register with zero. If we later
4339 see a condjump based on it, we have found a null pointer
4341 if (recog_memoized (insn
) == CODE_FOR_compare_eq
)
4343 rtx src
= SET_SRC (PATTERN (insn
));
4344 if (REG_P (XEXP (src
, 0))
4345 && P_REGNO_P (REGNO (XEXP (src
, 0)))
4346 && XEXP (src
, 1) == const0_rtx
)
4348 np_check_regno
= REGNO (XEXP (src
, 0));
4349 np_after_branch
= false;
4352 np_check_regno
= -1;
4355 if (load_insn
&& ENABLE_WA_SPECULATIVE_LOADS
)
4357 if (trapping_loads_p (load_insn
, np_check_regno
,
4361 else if (type
== TYPE_SYNC
&& ENABLE_WA_SPECULATIVE_SYNCS
)
4364 /* See if we need to forget about a null pointer comparison
4365 we found earlier. */
4366 if (recog_memoized (insn
) != CODE_FOR_compare_eq
)
4368 note_stores (PATTERN (insn
), note_np_check_stores
, NULL
);
4369 if (np_check_regno
!= -1)
4371 if (find_regno_note (insn
, REG_INC
, np_check_regno
))
4372 np_check_regno
= -1;
4378 if (delay_needed
> cycles_since_jump
4379 && (delay_needed
- cycles_since_jump
) > delay_added
)
4383 rtx
*op
= recog_data
.operand
;
4385 delay_needed
-= cycles_since_jump
;
4387 extract_insn (last_condjump
);
4390 pat1
= gen_cbranch_predicted_taken (op
[0], op
[1], op
[2],
4392 cycles_since_jump
= INT_MAX
;
4396 /* Do not adjust cycles_since_jump in this case, so that
4397 we'll increase the number of NOPs for a subsequent insn
4399 pat1
= gen_cbranch_with_nops (op
[0], op
[1], op
[2], op
[3],
4400 GEN_INT (delay_needed
));
4401 delay_added
= delay_needed
;
4403 PATTERN (last_condjump
) = pat1
;
4404 INSN_CODE (last_condjump
) = recog (pat1
, insn
, &num_clobbers
);
4408 cycles_since_jump
= INT_MAX
;
4413 /* Second pass: for predicted-true branches, see if anything at the
4414 branch destination needs extra nops. */
4415 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4417 int cycles_since_jump
;
4419 && any_condjump_p (insn
)
4420 && (INSN_CODE (insn
) == CODE_FOR_cbranch_predicted_taken
4421 || cbranch_predicted_taken_p (insn
)))
4423 rtx target
= JUMP_LABEL (insn
);
4427 cycles_since_jump
= 0;
4428 for (; target
&& cycles_since_jump
< 3; target
= next_tgt
)
4432 next_tgt
= find_next_insn_start (target
);
4434 if (NOTE_P (target
) || BARRIER_P (target
) || LABEL_P (target
))
4437 pat
= PATTERN (target
);
4438 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
4439 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
4440 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
4443 if (NONDEBUG_INSN_P (target
))
4445 rtx load_insn
= find_load (target
);
4446 enum attr_type type
= type_for_anomaly (target
);
4447 int delay_needed
= 0;
4448 if (cycles_since_jump
< INT_MAX
)
4449 cycles_since_jump
++;
4451 if (load_insn
&& ENABLE_WA_SPECULATIVE_LOADS
)
4453 if (trapping_loads_p (load_insn
, -1, false))
4456 else if (type
== TYPE_SYNC
&& ENABLE_WA_SPECULATIVE_SYNCS
)
4459 if (delay_needed
> cycles_since_jump
)
4461 rtx prev
= prev_real_insn (label
);
4462 delay_needed
-= cycles_since_jump
;
4464 fprintf (dump_file
, "Adding %d nops after %d\n",
4465 delay_needed
, INSN_UID (label
));
4467 && INSN_CODE (prev
) == CODE_FOR_cbranch_with_nops
)
4474 "Reducing nops on insn %d.\n",
4477 x
= XVECEXP (x
, 0, 1);
4478 v
= INTVAL (XVECEXP (x
, 0, 0)) - delay_needed
;
4479 XVECEXP (x
, 0, 0) = GEN_INT (v
);
4481 while (delay_needed
-- > 0)
4482 emit_insn_after (gen_nop (), label
);
4491 /* Called just before the final scheduling pass. If we need to insert NOPs
4492 later on to work around speculative loads, insert special placeholder
4493 insns that cause loads to be delayed for as many cycles as necessary
4494 (and possible). This reduces the number of NOPs we need to add.
4495 The dummy insns we generate are later removed by bfin_gen_bundles. */
4497 add_sched_insns_for_speculation (void)
4501 if (! ENABLE_WA_SPECULATIVE_LOADS
&& ! ENABLE_WA_SPECULATIVE_SYNCS
4502 && ! ENABLE_WA_INDIRECT_CALLS
)
4505 /* First pass: find predicted-false branches; if something after them
4506 needs nops, insert them or change the branch to predict true. */
4507 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4511 if (NOTE_P (insn
) || BARRIER_P (insn
) || LABEL_P (insn
))
4514 pat
= PATTERN (insn
);
4515 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
4516 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
4517 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
4522 if (any_condjump_p (insn
)
4523 && !cbranch_predicted_taken_p (insn
))
4525 rtx n
= next_real_insn (insn
);
4526 emit_insn_before (gen_stall (GEN_INT (3)), n
);
4531 /* Second pass: for predicted-true branches, see if anything at the
4532 branch destination needs extra nops. */
4533 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4536 && any_condjump_p (insn
)
4537 && (cbranch_predicted_taken_p (insn
)))
4539 rtx target
= JUMP_LABEL (insn
);
4540 rtx next
= next_real_insn (target
);
4542 if (GET_CODE (PATTERN (next
)) == UNSPEC_VOLATILE
4543 && get_attr_type (next
) == TYPE_STALL
)
4545 emit_insn_before (gen_stall (GEN_INT (1)), next
);
4550 /* We use the machine specific reorg pass for emitting CSYNC instructions
4551 after conditional branches as needed.
4553 The Blackfin is unusual in that a code sequence like
4556 may speculatively perform the load even if the condition isn't true. This
4557 happens for a branch that is predicted not taken, because the pipeline
4558 isn't flushed or stalled, so the early stages of the following instructions,
4559 which perform the memory reference, are allowed to execute before the
4560 jump condition is evaluated.
4561 Therefore, we must insert additional instructions in all places where this
4562 could lead to incorrect behavior. The manual recommends CSYNC, while
4563 VDSP seems to use NOPs (even though its corresponding compiler option is
4566 When optimizing for speed, we emit NOPs, which seems faster than a CSYNC.
4567 When optimizing for size, we turn the branch into a predicted taken one.
4568 This may be slower due to mispredicts, but saves code size. */
4573 /* We are freeing block_for_insn in the toplev to keep compatibility
4574 with old MDEP_REORGS that are not CFG based. Recompute it now. */
4575 compute_bb_for_insn ();
4577 if (flag_schedule_insns_after_reload
)
4579 splitting_for_sched
= 1;
4581 splitting_for_sched
= 0;
4583 add_sched_insns_for_speculation ();
4585 timevar_push (TV_SCHED2
);
4586 if (flag_selective_scheduling2
4587 && !maybe_skip_selective_scheduling ())
4588 run_selective_scheduling ();
4591 timevar_pop (TV_SCHED2
);
4593 /* Examine the schedule and insert nops as necessary for 64-bit parallel
4595 bfin_gen_bundles ();
4600 /* Doloop optimization */
4601 if (cfun
->machine
->has_hardware_loops
)
4602 bfin_reorg_loops ();
4604 workaround_speculation ();
4606 if (flag_var_tracking
)
4608 timevar_push (TV_VAR_TRACKING
);
4609 variable_tracking_main ();
4610 reorder_var_tracking_notes ();
4611 timevar_pop (TV_VAR_TRACKING
);
4614 df_finish_pass (false);
4616 workaround_rts_anomaly ();
4619 /* Handle interrupt_handler, exception_handler and nmi_handler function
4620 attributes; arguments as in struct attribute_spec.handler. */
4623 handle_int_attribute (tree
*node
, tree name
,
4624 tree args ATTRIBUTE_UNUSED
,
4625 int flags ATTRIBUTE_UNUSED
,
4629 if (TREE_CODE (x
) == FUNCTION_DECL
)
4632 if (TREE_CODE (x
) != FUNCTION_TYPE
)
4634 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
4636 *no_add_attrs
= true;
4638 else if (funkind (x
) != SUBROUTINE
)
4639 error ("multiple function type attributes specified");
4644 /* Return 0 if the attributes for two types are incompatible, 1 if they
4645 are compatible, and 2 if they are nearly compatible (which causes a
4646 warning to be generated). */
4649 bfin_comp_type_attributes (const_tree type1
, const_tree type2
)
4651 e_funkind kind1
, kind2
;
4653 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
4656 kind1
= funkind (type1
);
4657 kind2
= funkind (type2
);
4662 /* Check for mismatched modifiers */
4663 if (!lookup_attribute ("nesting", TYPE_ATTRIBUTES (type1
))
4664 != !lookup_attribute ("nesting", TYPE_ATTRIBUTES (type2
)))
4667 if (!lookup_attribute ("saveall", TYPE_ATTRIBUTES (type1
))
4668 != !lookup_attribute ("saveall", TYPE_ATTRIBUTES (type2
)))
4671 if (!lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type1
))
4672 != !lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type2
)))
4675 if (!lookup_attribute ("longcall", TYPE_ATTRIBUTES (type1
))
4676 != !lookup_attribute ("longcall", TYPE_ATTRIBUTES (type2
)))
4682 /* Handle a "longcall" or "shortcall" attribute; arguments as in
4683 struct attribute_spec.handler. */
4686 bfin_handle_longcall_attribute (tree
*node
, tree name
,
4687 tree args ATTRIBUTE_UNUSED
,
4688 int flags ATTRIBUTE_UNUSED
,
4691 if (TREE_CODE (*node
) != FUNCTION_TYPE
4692 && TREE_CODE (*node
) != FIELD_DECL
4693 && TREE_CODE (*node
) != TYPE_DECL
)
4695 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
4697 *no_add_attrs
= true;
4700 if ((strcmp (IDENTIFIER_POINTER (name
), "longcall") == 0
4701 && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (*node
)))
4702 || (strcmp (IDENTIFIER_POINTER (name
), "shortcall") == 0
4703 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (*node
))))
4705 warning (OPT_Wattributes
,
4706 "can%'t apply both longcall and shortcall attributes to the same function");
4707 *no_add_attrs
= true;
4713 /* Handle a "l1_text" attribute; arguments as in
4714 struct attribute_spec.handler. */
4717 bfin_handle_l1_text_attribute (tree
*node
, tree name
, tree
ARG_UNUSED (args
),
4718 int ARG_UNUSED (flags
), bool *no_add_attrs
)
4722 if (TREE_CODE (decl
) != FUNCTION_DECL
)
4724 error ("%qE attribute only applies to functions",
4726 *no_add_attrs
= true;
4729 /* The decl may have already been given a section attribute
4730 from a previous declaration. Ensure they match. */
4731 else if (DECL_SECTION_NAME (decl
) != NULL_TREE
4732 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
4735 error ("section of %q+D conflicts with previous declaration",
4737 *no_add_attrs
= true;
4740 DECL_SECTION_NAME (decl
) = build_string (9, ".l1.text");
4745 /* Handle a "l1_data", "l1_data_A" or "l1_data_B" attribute;
4746 arguments as in struct attribute_spec.handler. */
4749 bfin_handle_l1_data_attribute (tree
*node
, tree name
, tree
ARG_UNUSED (args
),
4750 int ARG_UNUSED (flags
), bool *no_add_attrs
)
4754 if (TREE_CODE (decl
) != VAR_DECL
)
4756 error ("%qE attribute only applies to variables",
4758 *no_add_attrs
= true;
4760 else if (current_function_decl
!= NULL_TREE
4761 && !TREE_STATIC (decl
))
4763 error ("%qE attribute cannot be specified for local variables",
4765 *no_add_attrs
= true;
4769 const char *section_name
;
4771 if (strcmp (IDENTIFIER_POINTER (name
), "l1_data") == 0)
4772 section_name
= ".l1.data";
4773 else if (strcmp (IDENTIFIER_POINTER (name
), "l1_data_A") == 0)
4774 section_name
= ".l1.data.A";
4775 else if (strcmp (IDENTIFIER_POINTER (name
), "l1_data_B") == 0)
4776 section_name
= ".l1.data.B";
4780 /* The decl may have already been given a section attribute
4781 from a previous declaration. Ensure they match. */
4782 if (DECL_SECTION_NAME (decl
) != NULL_TREE
4783 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
4786 error ("section of %q+D conflicts with previous declaration",
4788 *no_add_attrs
= true;
4791 DECL_SECTION_NAME (decl
)
4792 = build_string (strlen (section_name
) + 1, section_name
);
4798 /* Handle a "l2" attribute; arguments as in struct attribute_spec.handler. */
4801 bfin_handle_l2_attribute (tree
*node
, tree
ARG_UNUSED (name
),
4802 tree
ARG_UNUSED (args
), int ARG_UNUSED (flags
),
4807 if (TREE_CODE (decl
) == FUNCTION_DECL
)
4809 if (DECL_SECTION_NAME (decl
) != NULL_TREE
4810 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
4813 error ("section of %q+D conflicts with previous declaration",
4815 *no_add_attrs
= true;
4818 DECL_SECTION_NAME (decl
) = build_string (9, ".l2.text");
4820 else if (TREE_CODE (decl
) == VAR_DECL
)
4822 if (DECL_SECTION_NAME (decl
) != NULL_TREE
4823 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
4826 error ("section of %q+D conflicts with previous declaration",
4828 *no_add_attrs
= true;
4831 DECL_SECTION_NAME (decl
) = build_string (9, ".l2.data");
4837 /* Table of valid machine attributes. */
4838 static const struct attribute_spec bfin_attribute_table
[] =
4840 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
4841 affects_type_identity } */
4842 { "interrupt_handler", 0, 0, false, true, true, handle_int_attribute
,
4844 { "exception_handler", 0, 0, false, true, true, handle_int_attribute
,
4846 { "nmi_handler", 0, 0, false, true, true, handle_int_attribute
, false },
4847 { "nesting", 0, 0, false, true, true, NULL
, false },
4848 { "kspisusp", 0, 0, false, true, true, NULL
, false },
4849 { "saveall", 0, 0, false, true, true, NULL
, false },
4850 { "longcall", 0, 0, false, true, true, bfin_handle_longcall_attribute
,
4852 { "shortcall", 0, 0, false, true, true, bfin_handle_longcall_attribute
,
4854 { "l1_text", 0, 0, true, false, false, bfin_handle_l1_text_attribute
,
4856 { "l1_data", 0, 0, true, false, false, bfin_handle_l1_data_attribute
,
4858 { "l1_data_A", 0, 0, true, false, false, bfin_handle_l1_data_attribute
,
4860 { "l1_data_B", 0, 0, true, false, false, bfin_handle_l1_data_attribute
,
4862 { "l2", 0, 0, true, false, false, bfin_handle_l2_attribute
, false },
4863 { NULL
, 0, 0, false, false, false, NULL
, false }
4866 /* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to
4867 tell the assembler to generate pointers to function descriptors in
4871 bfin_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
4873 if (TARGET_FDPIC
&& size
== UNITS_PER_WORD
)
4875 if (GET_CODE (value
) == SYMBOL_REF
4876 && SYMBOL_REF_FUNCTION_P (value
))
4878 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
4879 output_addr_const (asm_out_file
, value
);
4880 fputs (")\n", asm_out_file
);
4885 /* We've set the unaligned SI op to NULL, so we always have to
4886 handle the unaligned case here. */
4887 assemble_integer_with_op ("\t.4byte\t", value
);
4891 return default_assemble_integer (value
, size
, aligned_p
);
4894 /* Output the assembler code for a thunk function. THUNK_DECL is the
4895 declaration for the thunk function itself, FUNCTION is the decl for
4896 the target function. DELTA is an immediate constant offset to be
4897 added to THIS. If VCALL_OFFSET is nonzero, the word at
4898 *(*this + vcall_offset) should be added to THIS. */
4901 bfin_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED
,
4902 tree thunk ATTRIBUTE_UNUSED
, HOST_WIDE_INT delta
,
4903 HOST_WIDE_INT vcall_offset
, tree function
)
4906 /* The this parameter is passed as the first argument. */
4907 rtx this_rtx
= gen_rtx_REG (Pmode
, REG_R0
);
4909 /* Adjust the this parameter by a fixed constant. */
4913 if (delta
>= -64 && delta
<= 63)
4915 xops
[0] = GEN_INT (delta
);
4916 output_asm_insn ("%1 += %0;", xops
);
4918 else if (delta
>= -128 && delta
< -64)
4920 xops
[0] = GEN_INT (delta
+ 64);
4921 output_asm_insn ("%1 += -64; %1 += %0;", xops
);
4923 else if (delta
> 63 && delta
<= 126)
4925 xops
[0] = GEN_INT (delta
- 63);
4926 output_asm_insn ("%1 += 63; %1 += %0;", xops
);
4930 xops
[0] = GEN_INT (delta
);
4931 output_asm_insn ("r3.l = %h0; r3.h = %d0; %1 = %1 + r3;", xops
);
4935 /* Adjust the this parameter by a value stored in the vtable. */
4938 rtx p2tmp
= gen_rtx_REG (Pmode
, REG_P2
);
4939 rtx tmp
= gen_rtx_REG (Pmode
, REG_R3
);
4943 output_asm_insn ("%2 = r0; %2 = [%2];", xops
);
4945 /* Adjust the this parameter. */
4946 xops
[0] = gen_rtx_MEM (Pmode
, plus_constant (Pmode
, p2tmp
,
4948 if (!memory_operand (xops
[0], Pmode
))
4950 rtx tmp2
= gen_rtx_REG (Pmode
, REG_P1
);
4951 xops
[0] = GEN_INT (vcall_offset
);
4953 output_asm_insn ("%h1 = %h0; %d1 = %d0; %2 = %2 + %1", xops
);
4954 xops
[0] = gen_rtx_MEM (Pmode
, p2tmp
);
4957 output_asm_insn ("%1 = %0; %2 = %2 + %1;", xops
);
4960 xops
[0] = XEXP (DECL_RTL (function
), 0);
4961 if (1 || !flag_pic
|| (*targetm
.binds_local_p
) (function
))
4962 output_asm_insn ("jump.l\t%P0", xops
);
4965 /* Codes for all the Blackfin builtins. */
4971 BFIN_BUILTIN_COMPOSE_2X16
,
4972 BFIN_BUILTIN_EXTRACTLO
,
4973 BFIN_BUILTIN_EXTRACTHI
,
4975 BFIN_BUILTIN_SSADD_2X16
,
4976 BFIN_BUILTIN_SSSUB_2X16
,
4977 BFIN_BUILTIN_SSADDSUB_2X16
,
4978 BFIN_BUILTIN_SSSUBADD_2X16
,
4979 BFIN_BUILTIN_MULT_2X16
,
4980 BFIN_BUILTIN_MULTR_2X16
,
4981 BFIN_BUILTIN_NEG_2X16
,
4982 BFIN_BUILTIN_ABS_2X16
,
4983 BFIN_BUILTIN_MIN_2X16
,
4984 BFIN_BUILTIN_MAX_2X16
,
4986 BFIN_BUILTIN_SSADD_1X16
,
4987 BFIN_BUILTIN_SSSUB_1X16
,
4988 BFIN_BUILTIN_MULT_1X16
,
4989 BFIN_BUILTIN_MULTR_1X16
,
4990 BFIN_BUILTIN_NORM_1X16
,
4991 BFIN_BUILTIN_NEG_1X16
,
4992 BFIN_BUILTIN_ABS_1X16
,
4993 BFIN_BUILTIN_MIN_1X16
,
4994 BFIN_BUILTIN_MAX_1X16
,
4996 BFIN_BUILTIN_SUM_2X16
,
4997 BFIN_BUILTIN_DIFFHL_2X16
,
4998 BFIN_BUILTIN_DIFFLH_2X16
,
5000 BFIN_BUILTIN_SSADD_1X32
,
5001 BFIN_BUILTIN_SSSUB_1X32
,
5002 BFIN_BUILTIN_NORM_1X32
,
5003 BFIN_BUILTIN_ROUND_1X32
,
5004 BFIN_BUILTIN_NEG_1X32
,
5005 BFIN_BUILTIN_ABS_1X32
,
5006 BFIN_BUILTIN_MIN_1X32
,
5007 BFIN_BUILTIN_MAX_1X32
,
5008 BFIN_BUILTIN_MULT_1X32
,
5009 BFIN_BUILTIN_MULT_1X32X32
,
5010 BFIN_BUILTIN_MULT_1X32X32NS
,
5012 BFIN_BUILTIN_MULHISILL
,
5013 BFIN_BUILTIN_MULHISILH
,
5014 BFIN_BUILTIN_MULHISIHL
,
5015 BFIN_BUILTIN_MULHISIHH
,
5017 BFIN_BUILTIN_LSHIFT_1X16
,
5018 BFIN_BUILTIN_LSHIFT_2X16
,
5019 BFIN_BUILTIN_SSASHIFT_1X16
,
5020 BFIN_BUILTIN_SSASHIFT_2X16
,
5021 BFIN_BUILTIN_SSASHIFT_1X32
,
5023 BFIN_BUILTIN_CPLX_MUL_16
,
5024 BFIN_BUILTIN_CPLX_MAC_16
,
5025 BFIN_BUILTIN_CPLX_MSU_16
,
5027 BFIN_BUILTIN_CPLX_MUL_16_S40
,
5028 BFIN_BUILTIN_CPLX_MAC_16_S40
,
5029 BFIN_BUILTIN_CPLX_MSU_16_S40
,
5031 BFIN_BUILTIN_CPLX_SQU
,
5033 BFIN_BUILTIN_LOADBYTES
,
5038 #define def_builtin(NAME, TYPE, CODE) \
5040 add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5044 /* Set up all builtin functions for this target. */
5046 bfin_init_builtins (void)
5048 tree V2HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V2HImode
);
5049 tree void_ftype_void
5050 = build_function_type_list (void_type_node
, NULL_TREE
);
5051 tree short_ftype_short
5052 = build_function_type_list (short_integer_type_node
, short_integer_type_node
,
5054 tree short_ftype_int_int
5055 = build_function_type_list (short_integer_type_node
, integer_type_node
,
5056 integer_type_node
, NULL_TREE
);
5057 tree int_ftype_int_int
5058 = build_function_type_list (integer_type_node
, integer_type_node
,
5059 integer_type_node
, NULL_TREE
);
5061 = build_function_type_list (integer_type_node
, integer_type_node
,
5063 tree short_ftype_int
5064 = build_function_type_list (short_integer_type_node
, integer_type_node
,
5066 tree int_ftype_v2hi_v2hi
5067 = build_function_type_list (integer_type_node
, V2HI_type_node
,
5068 V2HI_type_node
, NULL_TREE
);
5069 tree v2hi_ftype_v2hi_v2hi
5070 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
5071 V2HI_type_node
, NULL_TREE
);
5072 tree v2hi_ftype_v2hi_v2hi_v2hi
5073 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
5074 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
5075 tree v2hi_ftype_int_int
5076 = build_function_type_list (V2HI_type_node
, integer_type_node
,
5077 integer_type_node
, NULL_TREE
);
5078 tree v2hi_ftype_v2hi_int
5079 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
5080 integer_type_node
, NULL_TREE
);
5081 tree int_ftype_short_short
5082 = build_function_type_list (integer_type_node
, short_integer_type_node
,
5083 short_integer_type_node
, NULL_TREE
);
5084 tree v2hi_ftype_v2hi
5085 = build_function_type_list (V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
5086 tree short_ftype_v2hi
5087 = build_function_type_list (short_integer_type_node
, V2HI_type_node
,
5090 = build_function_type_list (integer_type_node
,
5091 build_pointer_type (integer_type_node
),
5094 /* Add the remaining MMX insns with somewhat more complicated types. */
5095 def_builtin ("__builtin_bfin_csync", void_ftype_void
, BFIN_BUILTIN_CSYNC
);
5096 def_builtin ("__builtin_bfin_ssync", void_ftype_void
, BFIN_BUILTIN_SSYNC
);
5098 def_builtin ("__builtin_bfin_ones", short_ftype_int
, BFIN_BUILTIN_ONES
);
5100 def_builtin ("__builtin_bfin_compose_2x16", v2hi_ftype_int_int
,
5101 BFIN_BUILTIN_COMPOSE_2X16
);
5102 def_builtin ("__builtin_bfin_extract_hi", short_ftype_v2hi
,
5103 BFIN_BUILTIN_EXTRACTHI
);
5104 def_builtin ("__builtin_bfin_extract_lo", short_ftype_v2hi
,
5105 BFIN_BUILTIN_EXTRACTLO
);
5107 def_builtin ("__builtin_bfin_min_fr2x16", v2hi_ftype_v2hi_v2hi
,
5108 BFIN_BUILTIN_MIN_2X16
);
5109 def_builtin ("__builtin_bfin_max_fr2x16", v2hi_ftype_v2hi_v2hi
,
5110 BFIN_BUILTIN_MAX_2X16
);
5112 def_builtin ("__builtin_bfin_add_fr2x16", v2hi_ftype_v2hi_v2hi
,
5113 BFIN_BUILTIN_SSADD_2X16
);
5114 def_builtin ("__builtin_bfin_sub_fr2x16", v2hi_ftype_v2hi_v2hi
,
5115 BFIN_BUILTIN_SSSUB_2X16
);
5116 def_builtin ("__builtin_bfin_dspaddsubsat", v2hi_ftype_v2hi_v2hi
,
5117 BFIN_BUILTIN_SSADDSUB_2X16
);
5118 def_builtin ("__builtin_bfin_dspsubaddsat", v2hi_ftype_v2hi_v2hi
,
5119 BFIN_BUILTIN_SSSUBADD_2X16
);
5120 def_builtin ("__builtin_bfin_mult_fr2x16", v2hi_ftype_v2hi_v2hi
,
5121 BFIN_BUILTIN_MULT_2X16
);
5122 def_builtin ("__builtin_bfin_multr_fr2x16", v2hi_ftype_v2hi_v2hi
,
5123 BFIN_BUILTIN_MULTR_2X16
);
5124 def_builtin ("__builtin_bfin_negate_fr2x16", v2hi_ftype_v2hi
,
5125 BFIN_BUILTIN_NEG_2X16
);
5126 def_builtin ("__builtin_bfin_abs_fr2x16", v2hi_ftype_v2hi
,
5127 BFIN_BUILTIN_ABS_2X16
);
5129 def_builtin ("__builtin_bfin_min_fr1x16", short_ftype_int_int
,
5130 BFIN_BUILTIN_MIN_1X16
);
5131 def_builtin ("__builtin_bfin_max_fr1x16", short_ftype_int_int
,
5132 BFIN_BUILTIN_MAX_1X16
);
5134 def_builtin ("__builtin_bfin_add_fr1x16", short_ftype_int_int
,
5135 BFIN_BUILTIN_SSADD_1X16
);
5136 def_builtin ("__builtin_bfin_sub_fr1x16", short_ftype_int_int
,
5137 BFIN_BUILTIN_SSSUB_1X16
);
5138 def_builtin ("__builtin_bfin_mult_fr1x16", short_ftype_int_int
,
5139 BFIN_BUILTIN_MULT_1X16
);
5140 def_builtin ("__builtin_bfin_multr_fr1x16", short_ftype_int_int
,
5141 BFIN_BUILTIN_MULTR_1X16
);
5142 def_builtin ("__builtin_bfin_negate_fr1x16", short_ftype_short
,
5143 BFIN_BUILTIN_NEG_1X16
);
5144 def_builtin ("__builtin_bfin_abs_fr1x16", short_ftype_short
,
5145 BFIN_BUILTIN_ABS_1X16
);
5146 def_builtin ("__builtin_bfin_norm_fr1x16", short_ftype_int
,
5147 BFIN_BUILTIN_NORM_1X16
);
5149 def_builtin ("__builtin_bfin_sum_fr2x16", short_ftype_v2hi
,
5150 BFIN_BUILTIN_SUM_2X16
);
5151 def_builtin ("__builtin_bfin_diff_hl_fr2x16", short_ftype_v2hi
,
5152 BFIN_BUILTIN_DIFFHL_2X16
);
5153 def_builtin ("__builtin_bfin_diff_lh_fr2x16", short_ftype_v2hi
,
5154 BFIN_BUILTIN_DIFFLH_2X16
);
5156 def_builtin ("__builtin_bfin_mulhisill", int_ftype_v2hi_v2hi
,
5157 BFIN_BUILTIN_MULHISILL
);
5158 def_builtin ("__builtin_bfin_mulhisihl", int_ftype_v2hi_v2hi
,
5159 BFIN_BUILTIN_MULHISIHL
);
5160 def_builtin ("__builtin_bfin_mulhisilh", int_ftype_v2hi_v2hi
,
5161 BFIN_BUILTIN_MULHISILH
);
5162 def_builtin ("__builtin_bfin_mulhisihh", int_ftype_v2hi_v2hi
,
5163 BFIN_BUILTIN_MULHISIHH
);
5165 def_builtin ("__builtin_bfin_min_fr1x32", int_ftype_int_int
,
5166 BFIN_BUILTIN_MIN_1X32
);
5167 def_builtin ("__builtin_bfin_max_fr1x32", int_ftype_int_int
,
5168 BFIN_BUILTIN_MAX_1X32
);
5170 def_builtin ("__builtin_bfin_add_fr1x32", int_ftype_int_int
,
5171 BFIN_BUILTIN_SSADD_1X32
);
5172 def_builtin ("__builtin_bfin_sub_fr1x32", int_ftype_int_int
,
5173 BFIN_BUILTIN_SSSUB_1X32
);
5174 def_builtin ("__builtin_bfin_negate_fr1x32", int_ftype_int
,
5175 BFIN_BUILTIN_NEG_1X32
);
5176 def_builtin ("__builtin_bfin_abs_fr1x32", int_ftype_int
,
5177 BFIN_BUILTIN_ABS_1X32
);
5178 def_builtin ("__builtin_bfin_norm_fr1x32", short_ftype_int
,
5179 BFIN_BUILTIN_NORM_1X32
);
5180 def_builtin ("__builtin_bfin_round_fr1x32", short_ftype_int
,
5181 BFIN_BUILTIN_ROUND_1X32
);
5182 def_builtin ("__builtin_bfin_mult_fr1x32", int_ftype_short_short
,
5183 BFIN_BUILTIN_MULT_1X32
);
5184 def_builtin ("__builtin_bfin_mult_fr1x32x32", int_ftype_int_int
,
5185 BFIN_BUILTIN_MULT_1X32X32
);
5186 def_builtin ("__builtin_bfin_mult_fr1x32x32NS", int_ftype_int_int
,
5187 BFIN_BUILTIN_MULT_1X32X32NS
);
5190 def_builtin ("__builtin_bfin_shl_fr1x16", short_ftype_int_int
,
5191 BFIN_BUILTIN_SSASHIFT_1X16
);
5192 def_builtin ("__builtin_bfin_shl_fr2x16", v2hi_ftype_v2hi_int
,
5193 BFIN_BUILTIN_SSASHIFT_2X16
);
5194 def_builtin ("__builtin_bfin_lshl_fr1x16", short_ftype_int_int
,
5195 BFIN_BUILTIN_LSHIFT_1X16
);
5196 def_builtin ("__builtin_bfin_lshl_fr2x16", v2hi_ftype_v2hi_int
,
5197 BFIN_BUILTIN_LSHIFT_2X16
);
5198 def_builtin ("__builtin_bfin_shl_fr1x32", int_ftype_int_int
,
5199 BFIN_BUILTIN_SSASHIFT_1X32
);
5201 /* Complex numbers. */
5202 def_builtin ("__builtin_bfin_cmplx_add", v2hi_ftype_v2hi_v2hi
,
5203 BFIN_BUILTIN_SSADD_2X16
);
5204 def_builtin ("__builtin_bfin_cmplx_sub", v2hi_ftype_v2hi_v2hi
,
5205 BFIN_BUILTIN_SSSUB_2X16
);
5206 def_builtin ("__builtin_bfin_cmplx_mul", v2hi_ftype_v2hi_v2hi
,
5207 BFIN_BUILTIN_CPLX_MUL_16
);
5208 def_builtin ("__builtin_bfin_cmplx_mac", v2hi_ftype_v2hi_v2hi_v2hi
,
5209 BFIN_BUILTIN_CPLX_MAC_16
);
5210 def_builtin ("__builtin_bfin_cmplx_msu", v2hi_ftype_v2hi_v2hi_v2hi
,
5211 BFIN_BUILTIN_CPLX_MSU_16
);
5212 def_builtin ("__builtin_bfin_cmplx_mul_s40", v2hi_ftype_v2hi_v2hi
,
5213 BFIN_BUILTIN_CPLX_MUL_16_S40
);
5214 def_builtin ("__builtin_bfin_cmplx_mac_s40", v2hi_ftype_v2hi_v2hi_v2hi
,
5215 BFIN_BUILTIN_CPLX_MAC_16_S40
);
5216 def_builtin ("__builtin_bfin_cmplx_msu_s40", v2hi_ftype_v2hi_v2hi_v2hi
,
5217 BFIN_BUILTIN_CPLX_MSU_16_S40
);
5218 def_builtin ("__builtin_bfin_csqu_fr16", v2hi_ftype_v2hi
,
5219 BFIN_BUILTIN_CPLX_SQU
);
5221 /* "Unaligned" load. */
5222 def_builtin ("__builtin_bfin_loadbytes", int_ftype_pint
,
5223 BFIN_BUILTIN_LOADBYTES
);
5228 struct builtin_description
5230 const enum insn_code icode
;
5231 const char *const name
;
5232 const enum bfin_builtins code
;
5236 static const struct builtin_description bdesc_2arg
[] =
5238 { CODE_FOR_composev2hi
, "__builtin_bfin_compose_2x16", BFIN_BUILTIN_COMPOSE_2X16
, -1 },
5240 { CODE_FOR_ssashiftv2hi3
, "__builtin_bfin_shl_fr2x16", BFIN_BUILTIN_SSASHIFT_2X16
, -1 },
5241 { CODE_FOR_ssashifthi3
, "__builtin_bfin_shl_fr1x16", BFIN_BUILTIN_SSASHIFT_1X16
, -1 },
5242 { CODE_FOR_lshiftv2hi3
, "__builtin_bfin_lshl_fr2x16", BFIN_BUILTIN_LSHIFT_2X16
, -1 },
5243 { CODE_FOR_lshifthi3
, "__builtin_bfin_lshl_fr1x16", BFIN_BUILTIN_LSHIFT_1X16
, -1 },
5244 { CODE_FOR_ssashiftsi3
, "__builtin_bfin_shl_fr1x32", BFIN_BUILTIN_SSASHIFT_1X32
, -1 },
5246 { CODE_FOR_sminhi3
, "__builtin_bfin_min_fr1x16", BFIN_BUILTIN_MIN_1X16
, -1 },
5247 { CODE_FOR_smaxhi3
, "__builtin_bfin_max_fr1x16", BFIN_BUILTIN_MAX_1X16
, -1 },
5248 { CODE_FOR_ssaddhi3
, "__builtin_bfin_add_fr1x16", BFIN_BUILTIN_SSADD_1X16
, -1 },
5249 { CODE_FOR_sssubhi3
, "__builtin_bfin_sub_fr1x16", BFIN_BUILTIN_SSSUB_1X16
, -1 },
5251 { CODE_FOR_sminsi3
, "__builtin_bfin_min_fr1x32", BFIN_BUILTIN_MIN_1X32
, -1 },
5252 { CODE_FOR_smaxsi3
, "__builtin_bfin_max_fr1x32", BFIN_BUILTIN_MAX_1X32
, -1 },
5253 { CODE_FOR_ssaddsi3
, "__builtin_bfin_add_fr1x32", BFIN_BUILTIN_SSADD_1X32
, -1 },
5254 { CODE_FOR_sssubsi3
, "__builtin_bfin_sub_fr1x32", BFIN_BUILTIN_SSSUB_1X32
, -1 },
5256 { CODE_FOR_sminv2hi3
, "__builtin_bfin_min_fr2x16", BFIN_BUILTIN_MIN_2X16
, -1 },
5257 { CODE_FOR_smaxv2hi3
, "__builtin_bfin_max_fr2x16", BFIN_BUILTIN_MAX_2X16
, -1 },
5258 { CODE_FOR_ssaddv2hi3
, "__builtin_bfin_add_fr2x16", BFIN_BUILTIN_SSADD_2X16
, -1 },
5259 { CODE_FOR_sssubv2hi3
, "__builtin_bfin_sub_fr2x16", BFIN_BUILTIN_SSSUB_2X16
, -1 },
5260 { CODE_FOR_ssaddsubv2hi3
, "__builtin_bfin_dspaddsubsat", BFIN_BUILTIN_SSADDSUB_2X16
, -1 },
5261 { CODE_FOR_sssubaddv2hi3
, "__builtin_bfin_dspsubaddsat", BFIN_BUILTIN_SSSUBADD_2X16
, -1 },
5263 { CODE_FOR_flag_mulhisi
, "__builtin_bfin_mult_fr1x32", BFIN_BUILTIN_MULT_1X32
, MACFLAG_NONE
},
5264 { CODE_FOR_flag_mulhi
, "__builtin_bfin_mult_fr1x16", BFIN_BUILTIN_MULT_1X16
, MACFLAG_T
},
5265 { CODE_FOR_flag_mulhi
, "__builtin_bfin_multr_fr1x16", BFIN_BUILTIN_MULTR_1X16
, MACFLAG_NONE
},
5266 { CODE_FOR_flag_mulv2hi
, "__builtin_bfin_mult_fr2x16", BFIN_BUILTIN_MULT_2X16
, MACFLAG_T
},
5267 { CODE_FOR_flag_mulv2hi
, "__builtin_bfin_multr_fr2x16", BFIN_BUILTIN_MULTR_2X16
, MACFLAG_NONE
},
5269 { CODE_FOR_mulhisi_ll
, "__builtin_bfin_mulhisill", BFIN_BUILTIN_MULHISILL
, -1 },
5270 { CODE_FOR_mulhisi_lh
, "__builtin_bfin_mulhisilh", BFIN_BUILTIN_MULHISILH
, -1 },
5271 { CODE_FOR_mulhisi_hl
, "__builtin_bfin_mulhisihl", BFIN_BUILTIN_MULHISIHL
, -1 },
5272 { CODE_FOR_mulhisi_hh
, "__builtin_bfin_mulhisihh", BFIN_BUILTIN_MULHISIHH
, -1 }
5276 static const struct builtin_description bdesc_1arg
[] =
5278 { CODE_FOR_loadbytes
, "__builtin_bfin_loadbytes", BFIN_BUILTIN_LOADBYTES
, 0 },
5280 { CODE_FOR_ones
, "__builtin_bfin_ones", BFIN_BUILTIN_ONES
, 0 },
5282 { CODE_FOR_clrsbhi2
, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16
, 0 },
5283 { CODE_FOR_ssneghi2
, "__builtin_bfin_negate_fr1x16", BFIN_BUILTIN_NEG_1X16
, 0 },
5284 { CODE_FOR_abshi2
, "__builtin_bfin_abs_fr1x16", BFIN_BUILTIN_ABS_1X16
, 0 },
5286 { CODE_FOR_clrsbsi2
, "__builtin_bfin_norm_fr1x32", BFIN_BUILTIN_NORM_1X32
, 0 },
5287 { CODE_FOR_ssroundsi2
, "__builtin_bfin_round_fr1x32", BFIN_BUILTIN_ROUND_1X32
, 0 },
5288 { CODE_FOR_ssnegsi2
, "__builtin_bfin_negate_fr1x32", BFIN_BUILTIN_NEG_1X32
, 0 },
5289 { CODE_FOR_ssabssi2
, "__builtin_bfin_abs_fr1x32", BFIN_BUILTIN_ABS_1X32
, 0 },
5291 { CODE_FOR_movv2hi_hi_low
, "__builtin_bfin_extract_lo", BFIN_BUILTIN_EXTRACTLO
, 0 },
5292 { CODE_FOR_movv2hi_hi_high
, "__builtin_bfin_extract_hi", BFIN_BUILTIN_EXTRACTHI
, 0 },
5293 { CODE_FOR_ssnegv2hi2
, "__builtin_bfin_negate_fr2x16", BFIN_BUILTIN_NEG_2X16
, 0 },
5294 { CODE_FOR_ssabsv2hi2
, "__builtin_bfin_abs_fr2x16", BFIN_BUILTIN_ABS_2X16
, 0 }
5297 /* Errors in the source file can cause expand_expr to return const0_rtx
5298 where we expect a vector. To avoid crashing, use one of the vector
5299 clear instructions. */
5301 safe_vector_operand (rtx x
, enum machine_mode mode
)
5303 if (x
!= const0_rtx
)
5305 x
= gen_reg_rtx (SImode
);
5307 emit_insn (gen_movsi (x
, CONST0_RTX (SImode
)));
5308 return gen_lowpart (mode
, x
);
5311 /* Subroutine of bfin_expand_builtin to take care of binop insns. MACFLAG is -1
5312 if this is a normal binary op, or one of the MACFLAG_xxx constants. */
5315 bfin_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
,
5319 tree arg0
= CALL_EXPR_ARG (exp
, 0);
5320 tree arg1
= CALL_EXPR_ARG (exp
, 1);
5321 rtx op0
= expand_normal (arg0
);
5322 rtx op1
= expand_normal (arg1
);
5323 enum machine_mode op0mode
= GET_MODE (op0
);
5324 enum machine_mode op1mode
= GET_MODE (op1
);
5325 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
5326 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
5327 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
5329 if (VECTOR_MODE_P (mode0
))
5330 op0
= safe_vector_operand (op0
, mode0
);
5331 if (VECTOR_MODE_P (mode1
))
5332 op1
= safe_vector_operand (op1
, mode1
);
5335 || GET_MODE (target
) != tmode
5336 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5337 target
= gen_reg_rtx (tmode
);
5339 if ((op0mode
== SImode
|| op0mode
== VOIDmode
) && mode0
== HImode
)
5342 op0
= gen_lowpart (HImode
, op0
);
5344 if ((op1mode
== SImode
|| op1mode
== VOIDmode
) && mode1
== HImode
)
5347 op1
= gen_lowpart (HImode
, op1
);
5349 /* In case the insn wants input operands in modes different from
5350 the result, abort. */
5351 gcc_assert ((op0mode
== mode0
|| op0mode
== VOIDmode
)
5352 && (op1mode
== mode1
|| op1mode
== VOIDmode
));
5354 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
5355 op0
= copy_to_mode_reg (mode0
, op0
);
5356 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
5357 op1
= copy_to_mode_reg (mode1
, op1
);
5360 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
5362 pat
= GEN_FCN (icode
) (target
, op0
, op1
, GEN_INT (macflag
));
5370 /* Subroutine of bfin_expand_builtin to take care of unop insns. */
5373 bfin_expand_unop_builtin (enum insn_code icode
, tree exp
,
5377 tree arg0
= CALL_EXPR_ARG (exp
, 0);
5378 rtx op0
= expand_normal (arg0
);
5379 enum machine_mode op0mode
= GET_MODE (op0
);
5380 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
5381 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
5384 || GET_MODE (target
) != tmode
5385 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5386 target
= gen_reg_rtx (tmode
);
5388 if (VECTOR_MODE_P (mode0
))
5389 op0
= safe_vector_operand (op0
, mode0
);
5391 if (op0mode
== SImode
&& mode0
== HImode
)
5394 op0
= gen_lowpart (HImode
, op0
);
5396 gcc_assert (op0mode
== mode0
|| op0mode
== VOIDmode
);
5398 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
5399 op0
= copy_to_mode_reg (mode0
, op0
);
5401 pat
= GEN_FCN (icode
) (target
, op0
);
5408 /* Expand an expression EXP that calls a built-in function,
5409 with result going to TARGET if that's convenient
5410 (and in mode MODE if that's convenient).
5411 SUBTARGET may be used as the target for computing one of EXP's operands.
5412 IGNORE is nonzero if the value is to be ignored. */
5415 bfin_expand_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
5416 rtx subtarget ATTRIBUTE_UNUSED
,
5417 enum machine_mode mode ATTRIBUTE_UNUSED
,
5418 int ignore ATTRIBUTE_UNUSED
)
5421 enum insn_code icode
;
5422 const struct builtin_description
*d
;
5423 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
5424 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
5425 tree arg0
, arg1
, arg2
;
5426 rtx op0
, op1
, op2
, accvec
, pat
, tmp1
, tmp2
, a0reg
, a1reg
;
5427 enum machine_mode tmode
, mode0
;
5431 case BFIN_BUILTIN_CSYNC
:
5432 emit_insn (gen_csync ());
5434 case BFIN_BUILTIN_SSYNC
:
5435 emit_insn (gen_ssync ());
5438 case BFIN_BUILTIN_DIFFHL_2X16
:
5439 case BFIN_BUILTIN_DIFFLH_2X16
:
5440 case BFIN_BUILTIN_SUM_2X16
:
5441 arg0
= CALL_EXPR_ARG (exp
, 0);
5442 op0
= expand_normal (arg0
);
5443 icode
= (fcode
== BFIN_BUILTIN_DIFFHL_2X16
? CODE_FOR_subhilov2hi3
5444 : fcode
== BFIN_BUILTIN_DIFFLH_2X16
? CODE_FOR_sublohiv2hi3
5445 : CODE_FOR_ssaddhilov2hi3
);
5446 tmode
= insn_data
[icode
].operand
[0].mode
;
5447 mode0
= insn_data
[icode
].operand
[1].mode
;
5450 || GET_MODE (target
) != tmode
5451 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5452 target
= gen_reg_rtx (tmode
);
5454 if (VECTOR_MODE_P (mode0
))
5455 op0
= safe_vector_operand (op0
, mode0
);
5457 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
5458 op0
= copy_to_mode_reg (mode0
, op0
);
5460 pat
= GEN_FCN (icode
) (target
, op0
, op0
);
5466 case BFIN_BUILTIN_MULT_1X32X32
:
5467 case BFIN_BUILTIN_MULT_1X32X32NS
:
5468 arg0
= CALL_EXPR_ARG (exp
, 0);
5469 arg1
= CALL_EXPR_ARG (exp
, 1);
5470 op0
= expand_normal (arg0
);
5471 op1
= expand_normal (arg1
);
5473 || !register_operand (target
, SImode
))
5474 target
= gen_reg_rtx (SImode
);
5475 if (! register_operand (op0
, SImode
))
5476 op0
= copy_to_mode_reg (SImode
, op0
);
5477 if (! register_operand (op1
, SImode
))
5478 op1
= copy_to_mode_reg (SImode
, op1
);
5480 a1reg
= gen_rtx_REG (PDImode
, REG_A1
);
5481 a0reg
= gen_rtx_REG (PDImode
, REG_A0
);
5482 tmp1
= gen_lowpart (V2HImode
, op0
);
5483 tmp2
= gen_lowpart (V2HImode
, op1
);
5484 emit_insn (gen_flag_macinit1hi (a1reg
,
5485 gen_lowpart (HImode
, op0
),
5486 gen_lowpart (HImode
, op1
),
5487 GEN_INT (MACFLAG_FU
)));
5488 emit_insn (gen_lshrpdi3 (a1reg
, a1reg
, GEN_INT (16)));
5490 if (fcode
== BFIN_BUILTIN_MULT_1X32X32
)
5491 emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg
, a1reg
, tmp1
, tmp2
,
5492 const1_rtx
, const1_rtx
,
5493 const1_rtx
, const0_rtx
, a1reg
,
5494 const0_rtx
, GEN_INT (MACFLAG_NONE
),
5495 GEN_INT (MACFLAG_M
)));
5498 /* For saturating multiplication, there's exactly one special case
5499 to be handled: multiplying the smallest negative value with
5500 itself. Due to shift correction in fractional multiplies, this
5501 can overflow. Iff this happens, OP2 will contain 1, which, when
5502 added in 32 bits to the smallest negative, wraps to the largest
5503 positive, which is the result we want. */
5504 op2
= gen_reg_rtx (V2HImode
);
5505 emit_insn (gen_packv2hi (op2
, tmp1
, tmp2
, const0_rtx
, const0_rtx
));
5506 emit_insn (gen_movsibi (gen_rtx_REG (BImode
, REG_CC
),
5507 gen_lowpart (SImode
, op2
)));
5508 emit_insn (gen_flag_mul_macv2hi_parts_acconly_andcc0 (a0reg
, a1reg
, tmp1
, tmp2
,
5509 const1_rtx
, const1_rtx
,
5510 const1_rtx
, const0_rtx
, a1reg
,
5511 const0_rtx
, GEN_INT (MACFLAG_NONE
),
5512 GEN_INT (MACFLAG_M
)));
5513 op2
= gen_reg_rtx (SImode
);
5514 emit_insn (gen_movbisi (op2
, gen_rtx_REG (BImode
, REG_CC
)));
5516 emit_insn (gen_flag_machi_parts_acconly (a1reg
, tmp2
, tmp1
,
5517 const1_rtx
, const0_rtx
,
5518 a1reg
, const0_rtx
, GEN_INT (MACFLAG_M
)));
5519 emit_insn (gen_ashrpdi3 (a1reg
, a1reg
, GEN_INT (15)));
5520 emit_insn (gen_sum_of_accumulators (target
, a0reg
, a0reg
, a1reg
));
5521 if (fcode
== BFIN_BUILTIN_MULT_1X32X32NS
)
5522 emit_insn (gen_addsi3 (target
, target
, op2
));
5525 case BFIN_BUILTIN_CPLX_MUL_16
:
5526 case BFIN_BUILTIN_CPLX_MUL_16_S40
:
5527 arg0
= CALL_EXPR_ARG (exp
, 0);
5528 arg1
= CALL_EXPR_ARG (exp
, 1);
5529 op0
= expand_normal (arg0
);
5530 op1
= expand_normal (arg1
);
5531 accvec
= gen_reg_rtx (V2PDImode
);
5532 icode
= CODE_FOR_flag_macv2hi_parts
;
5533 tmode
= insn_data
[icode
].operand
[0].mode
;
5536 || GET_MODE (target
) != V2HImode
5537 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
5538 target
= gen_reg_rtx (tmode
);
5539 if (! register_operand (op0
, GET_MODE (op0
)))
5540 op0
= copy_to_mode_reg (GET_MODE (op0
), op0
);
5541 if (! register_operand (op1
, GET_MODE (op1
)))
5542 op1
= copy_to_mode_reg (GET_MODE (op1
), op1
);
5544 if (fcode
== BFIN_BUILTIN_CPLX_MUL_16
)
5545 emit_insn (gen_flag_macinit1v2hi_parts (accvec
, op0
, op1
, const0_rtx
,
5546 const0_rtx
, const0_rtx
,
5547 const1_rtx
, GEN_INT (MACFLAG_W32
)));
5549 emit_insn (gen_flag_macinit1v2hi_parts (accvec
, op0
, op1
, const0_rtx
,
5550 const0_rtx
, const0_rtx
,
5551 const1_rtx
, GEN_INT (MACFLAG_NONE
)));
5552 emit_insn (gen_flag_macv2hi_parts (target
, op0
, op1
, const1_rtx
,
5553 const1_rtx
, const1_rtx
,
5554 const0_rtx
, accvec
, const1_rtx
, const0_rtx
,
5555 GEN_INT (MACFLAG_NONE
), accvec
));
5559 case BFIN_BUILTIN_CPLX_MAC_16
:
5560 case BFIN_BUILTIN_CPLX_MSU_16
:
5561 case BFIN_BUILTIN_CPLX_MAC_16_S40
:
5562 case BFIN_BUILTIN_CPLX_MSU_16_S40
:
5563 arg0
= CALL_EXPR_ARG (exp
, 0);
5564 arg1
= CALL_EXPR_ARG (exp
, 1);
5565 arg2
= CALL_EXPR_ARG (exp
, 2);
5566 op0
= expand_normal (arg0
);
5567 op1
= expand_normal (arg1
);
5568 op2
= expand_normal (arg2
);
5569 accvec
= gen_reg_rtx (V2PDImode
);
5570 icode
= CODE_FOR_flag_macv2hi_parts
;
5571 tmode
= insn_data
[icode
].operand
[0].mode
;
5574 || GET_MODE (target
) != V2HImode
5575 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
5576 target
= gen_reg_rtx (tmode
);
5577 if (! register_operand (op1
, GET_MODE (op1
)))
5578 op1
= copy_to_mode_reg (GET_MODE (op1
), op1
);
5579 if (! register_operand (op2
, GET_MODE (op2
)))
5580 op2
= copy_to_mode_reg (GET_MODE (op2
), op2
);
5582 tmp1
= gen_reg_rtx (SImode
);
5583 tmp2
= gen_reg_rtx (SImode
);
5584 emit_insn (gen_ashlsi3 (tmp1
, gen_lowpart (SImode
, op0
), GEN_INT (16)));
5585 emit_move_insn (tmp2
, gen_lowpart (SImode
, op0
));
5586 emit_insn (gen_movstricthi_1 (gen_lowpart (HImode
, tmp2
), const0_rtx
));
5587 emit_insn (gen_load_accumulator_pair (accvec
, tmp1
, tmp2
));
5588 if (fcode
== BFIN_BUILTIN_CPLX_MAC_16
5589 || fcode
== BFIN_BUILTIN_CPLX_MSU_16
)
5590 emit_insn (gen_flag_macv2hi_parts_acconly (accvec
, op1
, op2
, const0_rtx
,
5591 const0_rtx
, const0_rtx
,
5592 const1_rtx
, accvec
, const0_rtx
,
5594 GEN_INT (MACFLAG_W32
)));
5596 emit_insn (gen_flag_macv2hi_parts_acconly (accvec
, op1
, op2
, const0_rtx
,
5597 const0_rtx
, const0_rtx
,
5598 const1_rtx
, accvec
, const0_rtx
,
5600 GEN_INT (MACFLAG_NONE
)));
5601 if (fcode
== BFIN_BUILTIN_CPLX_MAC_16
5602 || fcode
== BFIN_BUILTIN_CPLX_MAC_16_S40
)
5612 emit_insn (gen_flag_macv2hi_parts (target
, op1
, op2
, const1_rtx
,
5613 const1_rtx
, const1_rtx
,
5614 const0_rtx
, accvec
, tmp1
, tmp2
,
5615 GEN_INT (MACFLAG_NONE
), accvec
));
5619 case BFIN_BUILTIN_CPLX_SQU
:
5620 arg0
= CALL_EXPR_ARG (exp
, 0);
5621 op0
= expand_normal (arg0
);
5622 accvec
= gen_reg_rtx (V2PDImode
);
5623 icode
= CODE_FOR_flag_mulv2hi
;
5624 tmp1
= gen_reg_rtx (V2HImode
);
5625 tmp2
= gen_reg_rtx (V2HImode
);
5628 || GET_MODE (target
) != V2HImode
5629 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
5630 target
= gen_reg_rtx (V2HImode
);
5631 if (! register_operand (op0
, GET_MODE (op0
)))
5632 op0
= copy_to_mode_reg (GET_MODE (op0
), op0
);
5634 emit_insn (gen_flag_mulv2hi (tmp1
, op0
, op0
, GEN_INT (MACFLAG_NONE
)));
5636 emit_insn (gen_flag_mulhi_parts (gen_lowpart (HImode
, tmp2
), op0
, op0
,
5637 const0_rtx
, const1_rtx
,
5638 GEN_INT (MACFLAG_NONE
)));
5640 emit_insn (gen_ssaddhi3_high_parts (target
, tmp2
, tmp2
, tmp2
, const0_rtx
,
5642 emit_insn (gen_sssubhi3_low_parts (target
, target
, tmp1
, tmp1
,
5643 const0_rtx
, const1_rtx
));
5651 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
5652 if (d
->code
== fcode
)
5653 return bfin_expand_binop_builtin (d
->icode
, exp
, target
,
5656 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
5657 if (d
->code
== fcode
)
5658 return bfin_expand_unop_builtin (d
->icode
, exp
, target
);
5664 bfin_conditional_register_usage (void)
5666 /* initialize condition code flag register rtx */
5667 bfin_cc_rtx
= gen_rtx_REG (BImode
, REG_CC
);
5668 bfin_rets_rtx
= gen_rtx_REG (Pmode
, REG_RETS
);
5670 call_used_regs
[FDPIC_REGNO
] = 1;
5671 if (!TARGET_FDPIC
&& flag_pic
)
5673 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
5674 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
5678 #undef TARGET_INIT_BUILTINS
5679 #define TARGET_INIT_BUILTINS bfin_init_builtins
5681 #undef TARGET_EXPAND_BUILTIN
5682 #define TARGET_EXPAND_BUILTIN bfin_expand_builtin
5684 #undef TARGET_ASM_GLOBALIZE_LABEL
5685 #define TARGET_ASM_GLOBALIZE_LABEL bfin_globalize_label
5687 #undef TARGET_ASM_FILE_START
5688 #define TARGET_ASM_FILE_START output_file_start
5690 #undef TARGET_ATTRIBUTE_TABLE
5691 #define TARGET_ATTRIBUTE_TABLE bfin_attribute_table
5693 #undef TARGET_COMP_TYPE_ATTRIBUTES
5694 #define TARGET_COMP_TYPE_ATTRIBUTES bfin_comp_type_attributes
5696 #undef TARGET_RTX_COSTS
5697 #define TARGET_RTX_COSTS bfin_rtx_costs
5699 #undef TARGET_ADDRESS_COST
5700 #define TARGET_ADDRESS_COST bfin_address_cost
5702 #undef TARGET_REGISTER_MOVE_COST
5703 #define TARGET_REGISTER_MOVE_COST bfin_register_move_cost
5705 #undef TARGET_MEMORY_MOVE_COST
5706 #define TARGET_MEMORY_MOVE_COST bfin_memory_move_cost
5708 #undef TARGET_ASM_INTEGER
5709 #define TARGET_ASM_INTEGER bfin_assemble_integer
5711 #undef TARGET_MACHINE_DEPENDENT_REORG
5712 #define TARGET_MACHINE_DEPENDENT_REORG bfin_reorg
5714 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5715 #define TARGET_FUNCTION_OK_FOR_SIBCALL bfin_function_ok_for_sibcall
5717 #undef TARGET_ASM_OUTPUT_MI_THUNK
5718 #define TARGET_ASM_OUTPUT_MI_THUNK bfin_output_mi_thunk
5719 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5720 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
5722 #undef TARGET_SCHED_ADJUST_COST
5723 #define TARGET_SCHED_ADJUST_COST bfin_adjust_cost
5725 #undef TARGET_SCHED_ISSUE_RATE
5726 #define TARGET_SCHED_ISSUE_RATE bfin_issue_rate
5728 #undef TARGET_PROMOTE_FUNCTION_MODE
5729 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
5731 #undef TARGET_ARG_PARTIAL_BYTES
5732 #define TARGET_ARG_PARTIAL_BYTES bfin_arg_partial_bytes
5734 #undef TARGET_FUNCTION_ARG
5735 #define TARGET_FUNCTION_ARG bfin_function_arg
5737 #undef TARGET_FUNCTION_ARG_ADVANCE
5738 #define TARGET_FUNCTION_ARG_ADVANCE bfin_function_arg_advance
5740 #undef TARGET_PASS_BY_REFERENCE
5741 #define TARGET_PASS_BY_REFERENCE bfin_pass_by_reference
5743 #undef TARGET_SETUP_INCOMING_VARARGS
5744 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
5746 #undef TARGET_STRUCT_VALUE_RTX
5747 #define TARGET_STRUCT_VALUE_RTX bfin_struct_value_rtx
5749 #undef TARGET_VECTOR_MODE_SUPPORTED_P
5750 #define TARGET_VECTOR_MODE_SUPPORTED_P bfin_vector_mode_supported_p
5752 #undef TARGET_OPTION_OVERRIDE
5753 #define TARGET_OPTION_OVERRIDE bfin_option_override
5755 #undef TARGET_SECONDARY_RELOAD
5756 #define TARGET_SECONDARY_RELOAD bfin_secondary_reload
5758 #undef TARGET_CLASS_LIKELY_SPILLED_P
5759 #define TARGET_CLASS_LIKELY_SPILLED_P bfin_class_likely_spilled_p
5761 #undef TARGET_DELEGITIMIZE_ADDRESS
5762 #define TARGET_DELEGITIMIZE_ADDRESS bfin_delegitimize_address
5764 #undef TARGET_LEGITIMATE_CONSTANT_P
5765 #define TARGET_LEGITIMATE_CONSTANT_P bfin_legitimate_constant_p
5767 #undef TARGET_CANNOT_FORCE_CONST_MEM
5768 #define TARGET_CANNOT_FORCE_CONST_MEM bfin_cannot_force_const_mem
5770 #undef TARGET_RETURN_IN_MEMORY
5771 #define TARGET_RETURN_IN_MEMORY bfin_return_in_memory
5773 #undef TARGET_LEGITIMATE_ADDRESS_P
5774 #define TARGET_LEGITIMATE_ADDRESS_P bfin_legitimate_address_p
5776 #undef TARGET_FRAME_POINTER_REQUIRED
5777 #define TARGET_FRAME_POINTER_REQUIRED bfin_frame_pointer_required
5779 #undef TARGET_CAN_ELIMINATE
5780 #define TARGET_CAN_ELIMINATE bfin_can_eliminate
5782 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5783 #define TARGET_CONDITIONAL_REGISTER_USAGE bfin_conditional_register_usage
5785 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
5786 #define TARGET_ASM_TRAMPOLINE_TEMPLATE bfin_asm_trampoline_template
5787 #undef TARGET_TRAMPOLINE_INIT
5788 #define TARGET_TRAMPOLINE_INIT bfin_trampoline_init
5790 #undef TARGET_EXTRA_LIVE_ON_ENTRY
5791 #define TARGET_EXTRA_LIVE_ON_ENTRY bfin_extra_live_on_entry
5793 /* Passes after sched2 can break the helpful TImode annotations that
5794 haifa-sched puts on every insn. Just do scheduling in reorg. */
5795 #undef TARGET_DELAY_SCHED2
5796 #define TARGET_DELAY_SCHED2 true
5798 /* Variable tracking should be run after all optimizations which
5799 change order of insns. It also needs a valid CFG. */
5800 #undef TARGET_DELAY_VARTRACK
5801 #define TARGET_DELAY_VARTRACK true
5803 struct gcc_target targetm
= TARGET_INITIALIZER
;