1 /* The Blackfin code generation auxiliary output file.
2 Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4 Contributed by Analog Devices.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-codes.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
41 #include "target-def.h"
43 #include "diagnostic-core.h"
47 #include "integrate.h"
49 #include "langhooks.h"
50 #include "bfin-protos.h"
52 #include "tm-constrs.h"
54 #include "basic-block.h"
55 #include "cfglayout.h"
58 #include "sel-sched.h"
61 /* A C structure for machine-specific, per-function data.
62 This is added to the cfun structure. */
63 struct GTY(()) machine_function
65 /* Set if we are notified by the doloop pass that a hardware loop
67 int has_hardware_loops
;
69 /* Set if we create a memcpy pattern that uses loop registers. */
70 int has_loopreg_clobber
;
73 /* RTX for condition code flag register and RETS register */
74 extern GTY(()) rtx bfin_cc_rtx
;
75 extern GTY(()) rtx bfin_rets_rtx
;
76 rtx bfin_cc_rtx
, bfin_rets_rtx
;
78 int max_arg_registers
= 0;
80 /* Arrays used when emitting register names. */
81 const char *short_reg_names
[] = SHORT_REGISTER_NAMES
;
82 const char *high_reg_names
[] = HIGH_REGISTER_NAMES
;
83 const char *dregs_pair_names
[] = DREGS_PAIR_NAMES
;
84 const char *byte_reg_names
[] = BYTE_REGISTER_NAMES
;
86 static int arg_regs
[] = FUNCTION_ARG_REGISTERS
;
87 static int ret_regs
[] = FUNCTION_RETURN_REGISTERS
;
89 int splitting_for_sched
, splitting_loops
;
92 bfin_globalize_label (FILE *stream
, const char *name
)
94 fputs (".global ", stream
);
95 assemble_name (stream
, name
);
101 output_file_start (void)
103 FILE *file
= asm_out_file
;
106 fprintf (file
, ".file \"%s\";\n", input_filename
);
108 for (i
= 0; arg_regs
[i
] >= 0; i
++)
110 max_arg_registers
= i
; /* how many arg reg used */
113 /* Examine machine-dependent attributes of function type FUNTYPE and return its
114 type. See the definition of E_FUNKIND. */
117 funkind (const_tree funtype
)
119 tree attrs
= TYPE_ATTRIBUTES (funtype
);
120 if (lookup_attribute ("interrupt_handler", attrs
))
121 return INTERRUPT_HANDLER
;
122 else if (lookup_attribute ("exception_handler", attrs
))
123 return EXCPT_HANDLER
;
124 else if (lookup_attribute ("nmi_handler", attrs
))
130 /* Legitimize PIC addresses. If the address is already position-independent,
131 we return ORIG. Newly generated position-independent addresses go into a
132 reg. This is REG if nonzero, otherwise we allocate register(s) as
133 necessary. PICREG is the register holding the pointer to the PIC offset
137 legitimize_pic_address (rtx orig
, rtx reg
, rtx picreg
)
142 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
147 if (TARGET_ID_SHARED_LIBRARY
)
148 unspec
= UNSPEC_MOVE_PIC
;
149 else if (GET_CODE (addr
) == SYMBOL_REF
150 && SYMBOL_REF_FUNCTION_P (addr
))
151 unspec
= UNSPEC_FUNCDESC_GOT17M4
;
153 unspec
= UNSPEC_MOVE_FDPIC
;
157 gcc_assert (can_create_pseudo_p ());
158 reg
= gen_reg_rtx (Pmode
);
161 tmp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), unspec
);
162 new_rtx
= gen_const_mem (Pmode
, gen_rtx_PLUS (Pmode
, picreg
, tmp
));
164 emit_move_insn (reg
, new_rtx
);
165 if (picreg
== pic_offset_table_rtx
)
166 crtl
->uses_pic_offset_table
= 1;
170 else if (GET_CODE (addr
) == CONST
|| GET_CODE (addr
) == PLUS
)
174 if (GET_CODE (addr
) == CONST
)
176 addr
= XEXP (addr
, 0);
177 gcc_assert (GET_CODE (addr
) == PLUS
);
180 if (XEXP (addr
, 0) == picreg
)
185 gcc_assert (can_create_pseudo_p ());
186 reg
= gen_reg_rtx (Pmode
);
189 base
= legitimize_pic_address (XEXP (addr
, 0), reg
, picreg
);
190 addr
= legitimize_pic_address (XEXP (addr
, 1),
191 base
== reg
? NULL_RTX
: reg
,
194 if (GET_CODE (addr
) == CONST_INT
)
196 gcc_assert (! reload_in_progress
&& ! reload_completed
);
197 addr
= force_reg (Pmode
, addr
);
200 if (GET_CODE (addr
) == PLUS
&& CONSTANT_P (XEXP (addr
, 1)))
202 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (addr
, 0));
203 addr
= XEXP (addr
, 1);
206 return gen_rtx_PLUS (Pmode
, base
, addr
);
212 /* Stack frame layout. */
214 /* For a given REGNO, determine whether it must be saved in the function
215 prologue. IS_INTHANDLER specifies whether we're generating a normal
216 prologue or an interrupt/exception one. */
218 must_save_p (bool is_inthandler
, unsigned regno
)
220 if (D_REGNO_P (regno
))
222 bool is_eh_return_reg
= false;
223 if (crtl
->calls_eh_return
)
228 unsigned test
= EH_RETURN_DATA_REGNO (j
);
229 if (test
== INVALID_REGNUM
)
232 is_eh_return_reg
= true;
236 return (is_eh_return_reg
237 || (df_regs_ever_live_p (regno
)
238 && !fixed_regs
[regno
]
239 && (is_inthandler
|| !call_used_regs
[regno
])));
241 else if (P_REGNO_P (regno
))
243 return ((df_regs_ever_live_p (regno
)
244 && !fixed_regs
[regno
]
245 && (is_inthandler
|| !call_used_regs
[regno
]))
247 && (ENABLE_WA_05000283
|| ENABLE_WA_05000315
)
250 && regno
== PIC_OFFSET_TABLE_REGNUM
251 && (crtl
->uses_pic_offset_table
252 || (TARGET_ID_SHARED_LIBRARY
&& !current_function_is_leaf
))));
255 return ((is_inthandler
|| !call_used_regs
[regno
])
256 && (df_regs_ever_live_p (regno
)
257 || (!leaf_function_p () && call_used_regs
[regno
])));
261 /* Compute the number of DREGS to save with a push_multiple operation.
262 This could include registers that aren't modified in the function,
263 since push_multiple only takes a range of registers.
264 If IS_INTHANDLER, then everything that is live must be saved, even
265 if normally call-clobbered.
266 If CONSECUTIVE, return the number of registers we can save in one
267 instruction with a push/pop multiple instruction. */
270 n_dregs_to_save (bool is_inthandler
, bool consecutive
)
275 for (i
= REG_R7
+ 1; i
-- != REG_R0
;)
277 if (must_save_p (is_inthandler
, i
))
279 else if (consecutive
)
285 /* Like n_dregs_to_save, but compute number of PREGS to save. */
288 n_pregs_to_save (bool is_inthandler
, bool consecutive
)
293 for (i
= REG_P5
+ 1; i
-- != REG_P0
;)
294 if (must_save_p (is_inthandler
, i
))
296 else if (consecutive
)
301 /* Determine if we are going to save the frame pointer in the prologue. */
304 must_save_fp_p (void)
306 return df_regs_ever_live_p (REG_FP
);
309 /* Determine if we are going to save the RETS register. */
311 must_save_rets_p (void)
313 return df_regs_ever_live_p (REG_RETS
);
317 stack_frame_needed_p (void)
319 /* EH return puts a new return address into the frame using an
320 address relative to the frame pointer. */
321 if (crtl
->calls_eh_return
)
323 return frame_pointer_needed
;
326 /* Emit code to save registers in the prologue. SAVEALL is nonzero if we
327 must save all registers; this is used for interrupt handlers.
328 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
329 this for an interrupt (or exception) handler. */
332 expand_prologue_reg_save (rtx spreg
, int saveall
, bool is_inthandler
)
334 rtx predec1
= gen_rtx_PRE_DEC (SImode
, spreg
);
335 rtx predec
= gen_rtx_MEM (SImode
, predec1
);
336 int ndregs
= saveall
? 8 : n_dregs_to_save (is_inthandler
, false);
337 int npregs
= saveall
? 6 : n_pregs_to_save (is_inthandler
, false);
338 int ndregs_consec
= saveall
? 8 : n_dregs_to_save (is_inthandler
, true);
339 int npregs_consec
= saveall
? 6 : n_pregs_to_save (is_inthandler
, true);
341 int total_consec
= ndregs_consec
+ npregs_consec
;
344 if (saveall
|| is_inthandler
)
346 rtx insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, REG_ASTAT
));
348 RTX_FRAME_RELATED_P (insn
) = 1;
349 for (dregno
= REG_LT0
; dregno
<= REG_LB1
; dregno
++)
350 if (! current_function_is_leaf
351 || cfun
->machine
->has_hardware_loops
352 || cfun
->machine
->has_loopreg_clobber
353 || (ENABLE_WA_05000257
354 && (dregno
== REG_LC0
|| dregno
== REG_LC1
)))
356 insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, dregno
));
357 RTX_FRAME_RELATED_P (insn
) = 1;
361 if (total_consec
!= 0)
364 rtx val
= GEN_INT (-total_consec
* 4);
365 rtx pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_consec
+ 2));
367 XVECEXP (pat
, 0, 0) = gen_rtx_UNSPEC (VOIDmode
, gen_rtvec (1, val
),
368 UNSPEC_PUSH_MULTIPLE
);
369 XVECEXP (pat
, 0, total_consec
+ 1) = gen_rtx_SET (VOIDmode
, spreg
,
373 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, total_consec
+ 1)) = 1;
374 d_to_save
= ndregs_consec
;
375 dregno
= REG_R7
+ 1 - ndregs_consec
;
376 pregno
= REG_P5
+ 1 - npregs_consec
;
377 for (i
= 0; i
< total_consec
; i
++)
379 rtx memref
= gen_rtx_MEM (word_mode
,
380 gen_rtx_PLUS (Pmode
, spreg
,
381 GEN_INT (- i
* 4 - 4)));
385 subpat
= gen_rtx_SET (VOIDmode
, memref
, gen_rtx_REG (word_mode
,
391 subpat
= gen_rtx_SET (VOIDmode
, memref
, gen_rtx_REG (word_mode
,
394 XVECEXP (pat
, 0, i
+ 1) = subpat
;
395 RTX_FRAME_RELATED_P (subpat
) = 1;
397 insn
= emit_insn (pat
);
398 RTX_FRAME_RELATED_P (insn
) = 1;
401 for (dregno
= REG_R0
; ndregs
!= ndregs_consec
; dregno
++)
403 if (must_save_p (is_inthandler
, dregno
))
405 rtx insn
= emit_move_insn (predec
, gen_rtx_REG (word_mode
, dregno
));
406 RTX_FRAME_RELATED_P (insn
) = 1;
410 for (pregno
= REG_P0
; npregs
!= npregs_consec
; pregno
++)
412 if (must_save_p (is_inthandler
, pregno
))
414 rtx insn
= emit_move_insn (predec
, gen_rtx_REG (word_mode
, pregno
));
415 RTX_FRAME_RELATED_P (insn
) = 1;
419 for (i
= REG_P7
+ 1; i
< REG_CC
; i
++)
422 && (df_regs_ever_live_p (i
)
423 || (!leaf_function_p () && call_used_regs
[i
]))))
426 if (i
== REG_A0
|| i
== REG_A1
)
427 insn
= emit_move_insn (gen_rtx_MEM (PDImode
, predec1
),
428 gen_rtx_REG (PDImode
, i
));
430 insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, i
));
431 RTX_FRAME_RELATED_P (insn
) = 1;
435 /* Emit code to restore registers in the epilogue. SAVEALL is nonzero if we
436 must save all registers; this is used for interrupt handlers.
437 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
438 this for an interrupt (or exception) handler. */
441 expand_epilogue_reg_restore (rtx spreg
, bool saveall
, bool is_inthandler
)
443 rtx postinc1
= gen_rtx_POST_INC (SImode
, spreg
);
444 rtx postinc
= gen_rtx_MEM (SImode
, postinc1
);
446 int ndregs
= saveall
? 8 : n_dregs_to_save (is_inthandler
, false);
447 int npregs
= saveall
? 6 : n_pregs_to_save (is_inthandler
, false);
448 int ndregs_consec
= saveall
? 8 : n_dregs_to_save (is_inthandler
, true);
449 int npregs_consec
= saveall
? 6 : n_pregs_to_save (is_inthandler
, true);
450 int total_consec
= ndregs_consec
+ npregs_consec
;
454 /* A slightly crude technique to stop flow from trying to delete "dead"
456 MEM_VOLATILE_P (postinc
) = 1;
458 for (i
= REG_CC
- 1; i
> REG_P7
; i
--)
461 && (df_regs_ever_live_p (i
)
462 || (!leaf_function_p () && call_used_regs
[i
]))))
464 if (i
== REG_A0
|| i
== REG_A1
)
466 rtx mem
= gen_rtx_MEM (PDImode
, postinc1
);
467 MEM_VOLATILE_P (mem
) = 1;
468 emit_move_insn (gen_rtx_REG (PDImode
, i
), mem
);
471 emit_move_insn (gen_rtx_REG (SImode
, i
), postinc
);
474 regno
= REG_P5
- npregs_consec
;
475 for (; npregs
!= npregs_consec
; regno
--)
477 if (must_save_p (is_inthandler
, regno
))
479 emit_move_insn (gen_rtx_REG (word_mode
, regno
), postinc
);
483 regno
= REG_R7
- ndregs_consec
;
484 for (; ndregs
!= ndregs_consec
; regno
--)
486 if (must_save_p (is_inthandler
, regno
))
488 emit_move_insn (gen_rtx_REG (word_mode
, regno
), postinc
);
493 if (total_consec
!= 0)
495 rtx pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_consec
+ 1));
497 = gen_rtx_SET (VOIDmode
, spreg
,
498 gen_rtx_PLUS (Pmode
, spreg
,
499 GEN_INT (total_consec
* 4)));
501 if (npregs_consec
> 0)
506 for (i
= 0; i
< total_consec
; i
++)
509 ? gen_rtx_PLUS (Pmode
, spreg
, GEN_INT (i
* 4))
511 rtx memref
= gen_rtx_MEM (word_mode
, addr
);
514 XVECEXP (pat
, 0, i
+ 1)
515 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (word_mode
, regno
), memref
);
517 if (npregs_consec
> 0)
519 if (--npregs_consec
== 0)
524 insn
= emit_insn (pat
);
525 RTX_FRAME_RELATED_P (insn
) = 1;
527 if (saveall
|| is_inthandler
)
529 for (regno
= REG_LB1
; regno
>= REG_LT0
; regno
--)
530 if (! current_function_is_leaf
531 || cfun
->machine
->has_hardware_loops
532 || cfun
->machine
->has_loopreg_clobber
533 || (ENABLE_WA_05000257
&& (regno
== REG_LC0
|| regno
== REG_LC1
)))
534 emit_move_insn (gen_rtx_REG (SImode
, regno
), postinc
);
536 emit_move_insn (gen_rtx_REG (SImode
, REG_ASTAT
), postinc
);
540 /* Perform any needed actions needed for a function that is receiving a
541 variable number of arguments.
545 MODE and TYPE are the mode and type of the current parameter.
547 PRETEND_SIZE is a variable that should be set to the amount of stack
548 that must be pushed by the prolog to pretend that our caller pushed
551 Normally, this macro will push all remaining incoming registers on the
552 stack and set PRETEND_SIZE to the length of the registers pushed.
555 - VDSP C compiler manual (our ABI) says that a variable args function
556 should save the R0, R1 and R2 registers in the stack.
557 - The caller will always leave space on the stack for the
558 arguments that are passed in registers, so we dont have
559 to leave any extra space.
560 - now, the vastart pointer can access all arguments from the stack. */
563 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
564 enum machine_mode mode ATTRIBUTE_UNUSED
,
565 tree type ATTRIBUTE_UNUSED
, int *pretend_size
,
574 /* The move for named arguments will be generated automatically by the
575 compiler. We need to generate the move rtx for the unnamed arguments
576 if they are in the first 3 words. We assume at least 1 named argument
577 exists, so we never generate [ARGP] = R0 here. */
579 for (i
= cum
->words
+ 1; i
< max_arg_registers
; i
++)
581 mem
= gen_rtx_MEM (Pmode
,
582 plus_constant (arg_pointer_rtx
, (i
* UNITS_PER_WORD
)));
583 emit_move_insn (mem
, gen_rtx_REG (Pmode
, i
));
589 /* Value should be nonzero if functions must have frame pointers.
590 Zero means the frame pointer need not be set up (and parms may
591 be accessed via the stack pointer) in functions that seem suitable. */
594 bfin_frame_pointer_required (void)
596 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
598 if (fkind
!= SUBROUTINE
)
601 /* We turn on -fomit-frame-pointer if -momit-leaf-frame-pointer is used,
602 so we have to override it for non-leaf functions. */
603 if (TARGET_OMIT_LEAF_FRAME_POINTER
&& ! current_function_is_leaf
)
609 /* Return the number of registers pushed during the prologue. */
612 n_regs_saved_by_prologue (void)
614 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
615 bool is_inthandler
= fkind
!= SUBROUTINE
;
616 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
617 bool all
= (lookup_attribute ("saveall", attrs
) != NULL_TREE
618 || (is_inthandler
&& !current_function_is_leaf
));
619 int ndregs
= all
? 8 : n_dregs_to_save (is_inthandler
, false);
620 int npregs
= all
? 6 : n_pregs_to_save (is_inthandler
, false);
621 int n
= ndregs
+ npregs
;
624 if (all
|| stack_frame_needed_p ())
628 if (must_save_fp_p ())
630 if (must_save_rets_p ())
634 if (fkind
!= SUBROUTINE
|| all
)
636 /* Increment once for ASTAT. */
638 if (! current_function_is_leaf
639 || cfun
->machine
->has_hardware_loops
640 || cfun
->machine
->has_loopreg_clobber
)
646 if (fkind
!= SUBROUTINE
)
649 if (lookup_attribute ("nesting", attrs
))
653 for (i
= REG_P7
+ 1; i
< REG_CC
; i
++)
655 || (fkind
!= SUBROUTINE
656 && (df_regs_ever_live_p (i
)
657 || (!leaf_function_p () && call_used_regs
[i
]))))
658 n
+= i
== REG_A0
|| i
== REG_A1
? 2 : 1;
663 /* Given FROM and TO register numbers, say whether this elimination is
664 allowed. Frame pointer elimination is automatically handled.
666 All other eliminations are valid. */
669 bfin_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
671 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
674 /* Return the offset between two registers, one to be eliminated, and the other
675 its replacement, at the start of a routine. */
678 bfin_initial_elimination_offset (int from
, int to
)
680 HOST_WIDE_INT offset
= 0;
682 if (from
== ARG_POINTER_REGNUM
)
683 offset
= n_regs_saved_by_prologue () * 4;
685 if (to
== STACK_POINTER_REGNUM
)
687 if (crtl
->outgoing_args_size
>= FIXED_STACK_AREA
)
688 offset
+= crtl
->outgoing_args_size
;
689 else if (crtl
->outgoing_args_size
)
690 offset
+= FIXED_STACK_AREA
;
692 offset
+= get_frame_size ();
698 /* Emit code to load a constant CONSTANT into register REG; setting
699 RTX_FRAME_RELATED_P on all insns we generate if RELATED is true.
700 Make sure that the insns we generate need not be split. */
703 frame_related_constant_load (rtx reg
, HOST_WIDE_INT constant
, bool related
)
706 rtx cst
= GEN_INT (constant
);
708 if (constant
>= -32768 && constant
< 65536)
709 insn
= emit_move_insn (reg
, cst
);
712 /* We don't call split_load_immediate here, since dwarf2out.c can get
713 confused about some of the more clever sequences it can generate. */
714 insn
= emit_insn (gen_movsi_high (reg
, cst
));
716 RTX_FRAME_RELATED_P (insn
) = 1;
717 insn
= emit_insn (gen_movsi_low (reg
, reg
, cst
));
720 RTX_FRAME_RELATED_P (insn
) = 1;
723 /* Generate efficient code to add a value to a P register.
724 Set RTX_FRAME_RELATED_P on the generated insns if FRAME is nonzero.
725 EPILOGUE_P is zero if this function is called for prologue,
726 otherwise it's nonzero. And it's less than zero if this is for
730 add_to_reg (rtx reg
, HOST_WIDE_INT value
, int frame
, int epilogue_p
)
735 /* Choose whether to use a sequence using a temporary register, or
736 a sequence with multiple adds. We can add a signed 7-bit value
737 in one instruction. */
738 if (value
> 120 || value
< -120)
746 /* For prologue or normal epilogue, P1 can be safely used
747 as the temporary register. For sibcall epilogue, we try to find
748 a call used P register, which will be restored in epilogue.
749 If we cannot find such a P register, we have to use one I register
753 tmpreg
= gen_rtx_REG (SImode
, REG_P1
);
757 for (i
= REG_P0
; i
<= REG_P5
; i
++)
758 if ((df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
760 && i
== PIC_OFFSET_TABLE_REGNUM
761 && (crtl
->uses_pic_offset_table
762 || (TARGET_ID_SHARED_LIBRARY
763 && ! current_function_is_leaf
))))
766 tmpreg
= gen_rtx_REG (SImode
, i
);
769 tmpreg
= gen_rtx_REG (SImode
, REG_P1
);
770 tmpreg2
= gen_rtx_REG (SImode
, REG_I0
);
771 emit_move_insn (tmpreg2
, tmpreg
);
776 frame_related_constant_load (tmpreg
, value
, TRUE
);
778 insn
= emit_move_insn (tmpreg
, GEN_INT (value
));
780 insn
= emit_insn (gen_addsi3 (reg
, reg
, tmpreg
));
782 RTX_FRAME_RELATED_P (insn
) = 1;
784 if (tmpreg2
!= NULL_RTX
)
785 emit_move_insn (tmpreg
, tmpreg2
);
796 /* We could use -62, but that would leave the stack unaligned, so
800 insn
= emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
802 RTX_FRAME_RELATED_P (insn
) = 1;
808 /* Generate a LINK insn for a frame sized FRAME_SIZE. If this constant
809 is too large, generate a sequence of insns that has the same effect.
810 SPREG contains (reg:SI REG_SP). */
813 emit_link_insn (rtx spreg
, HOST_WIDE_INT frame_size
)
815 HOST_WIDE_INT link_size
= frame_size
;
819 if (link_size
> 262140)
822 /* Use a LINK insn with as big a constant as possible, then subtract
823 any remaining size from the SP. */
824 insn
= emit_insn (gen_link (GEN_INT (-8 - link_size
)));
825 RTX_FRAME_RELATED_P (insn
) = 1;
827 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
829 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
830 gcc_assert (GET_CODE (set
) == SET
);
831 RTX_FRAME_RELATED_P (set
) = 1;
834 frame_size
-= link_size
;
838 /* Must use a call-clobbered PREG that isn't the static chain. */
839 rtx tmpreg
= gen_rtx_REG (Pmode
, REG_P1
);
841 frame_related_constant_load (tmpreg
, -frame_size
, TRUE
);
842 insn
= emit_insn (gen_addsi3 (spreg
, spreg
, tmpreg
));
843 RTX_FRAME_RELATED_P (insn
) = 1;
847 /* Return the number of bytes we must reserve for outgoing arguments
848 in the current function's stack frame. */
853 if (crtl
->outgoing_args_size
)
855 if (crtl
->outgoing_args_size
>= FIXED_STACK_AREA
)
856 return crtl
->outgoing_args_size
;
858 return FIXED_STACK_AREA
;
863 /* Save RETS and FP, and allocate a stack frame. ALL is true if the
864 function must save all its registers (true only for certain interrupt
868 do_link (rtx spreg
, HOST_WIDE_INT frame_size
, bool all
)
870 frame_size
+= arg_area_size ();
873 || stack_frame_needed_p ()
874 || (must_save_rets_p () && must_save_fp_p ()))
875 emit_link_insn (spreg
, frame_size
);
878 if (must_save_rets_p ())
880 rtx pat
= gen_movsi (gen_rtx_MEM (Pmode
,
881 gen_rtx_PRE_DEC (Pmode
, spreg
)),
883 rtx insn
= emit_insn (pat
);
884 RTX_FRAME_RELATED_P (insn
) = 1;
886 if (must_save_fp_p ())
888 rtx pat
= gen_movsi (gen_rtx_MEM (Pmode
,
889 gen_rtx_PRE_DEC (Pmode
, spreg
)),
890 gen_rtx_REG (Pmode
, REG_FP
));
891 rtx insn
= emit_insn (pat
);
892 RTX_FRAME_RELATED_P (insn
) = 1;
894 add_to_reg (spreg
, -frame_size
, 1, 0);
898 /* Like do_link, but used for epilogues to deallocate the stack frame.
899 EPILOGUE_P is zero if this function is called for prologue,
900 otherwise it's nonzero. And it's less than zero if this is for
904 do_unlink (rtx spreg
, HOST_WIDE_INT frame_size
, bool all
, int epilogue_p
)
906 frame_size
+= arg_area_size ();
908 if (stack_frame_needed_p ())
909 emit_insn (gen_unlink ());
912 rtx postinc
= gen_rtx_MEM (Pmode
, gen_rtx_POST_INC (Pmode
, spreg
));
914 add_to_reg (spreg
, frame_size
, 0, epilogue_p
);
915 if (all
|| must_save_fp_p ())
917 rtx fpreg
= gen_rtx_REG (Pmode
, REG_FP
);
918 emit_move_insn (fpreg
, postinc
);
921 if (all
|| must_save_rets_p ())
923 emit_move_insn (bfin_rets_rtx
, postinc
);
924 emit_use (bfin_rets_rtx
);
929 /* Generate a prologue suitable for a function of kind FKIND. This is
930 called for interrupt and exception handler prologues.
931 SPREG contains (reg:SI REG_SP). */
934 expand_interrupt_handler_prologue (rtx spreg
, e_funkind fkind
, bool all
)
936 HOST_WIDE_INT frame_size
= get_frame_size ();
937 rtx predec1
= gen_rtx_PRE_DEC (SImode
, spreg
);
938 rtx predec
= gen_rtx_MEM (SImode
, predec1
);
940 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
941 tree kspisusp
= lookup_attribute ("kspisusp", attrs
);
945 insn
= emit_move_insn (spreg
, gen_rtx_REG (Pmode
, REG_USP
));
946 RTX_FRAME_RELATED_P (insn
) = 1;
949 /* We need space on the stack in case we need to save the argument
951 if (fkind
== EXCPT_HANDLER
)
953 insn
= emit_insn (gen_addsi3 (spreg
, spreg
, GEN_INT (-12)));
954 RTX_FRAME_RELATED_P (insn
) = 1;
957 /* If we're calling other functions, they won't save their call-clobbered
958 registers, so we must save everything here. */
959 if (!current_function_is_leaf
)
961 expand_prologue_reg_save (spreg
, all
, true);
963 if (ENABLE_WA_05000283
|| ENABLE_WA_05000315
)
965 rtx chipid
= GEN_INT (trunc_int_for_mode (0xFFC00014, SImode
));
966 rtx p5reg
= gen_rtx_REG (Pmode
, REG_P5
);
967 emit_insn (gen_movbi (bfin_cc_rtx
, const1_rtx
));
968 emit_insn (gen_movsi_high (p5reg
, chipid
));
969 emit_insn (gen_movsi_low (p5reg
, p5reg
, chipid
));
970 emit_insn (gen_dummy_load (p5reg
, bfin_cc_rtx
));
973 if (lookup_attribute ("nesting", attrs
))
975 rtx srcreg
= gen_rtx_REG (Pmode
, ret_regs
[fkind
]);
976 insn
= emit_move_insn (predec
, srcreg
);
977 RTX_FRAME_RELATED_P (insn
) = 1;
980 do_link (spreg
, frame_size
, all
);
982 if (fkind
== EXCPT_HANDLER
)
984 rtx r0reg
= gen_rtx_REG (SImode
, REG_R0
);
985 rtx r1reg
= gen_rtx_REG (SImode
, REG_R1
);
986 rtx r2reg
= gen_rtx_REG (SImode
, REG_R2
);
988 emit_move_insn (r0reg
, gen_rtx_REG (SImode
, REG_SEQSTAT
));
989 emit_insn (gen_ashrsi3 (r0reg
, r0reg
, GEN_INT (26)));
990 emit_insn (gen_ashlsi3 (r0reg
, r0reg
, GEN_INT (26)));
991 emit_move_insn (r1reg
, spreg
);
992 emit_move_insn (r2reg
, gen_rtx_REG (Pmode
, REG_FP
));
993 emit_insn (gen_addsi3 (r2reg
, r2reg
, GEN_INT (8)));
997 /* Generate an epilogue suitable for a function of kind FKIND. This is
998 called for interrupt and exception handler epilogues.
999 SPREG contains (reg:SI REG_SP). */
1002 expand_interrupt_handler_epilogue (rtx spreg
, e_funkind fkind
, bool all
)
1004 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1005 rtx postinc1
= gen_rtx_POST_INC (SImode
, spreg
);
1006 rtx postinc
= gen_rtx_MEM (SImode
, postinc1
);
1008 /* A slightly crude technique to stop flow from trying to delete "dead"
1010 MEM_VOLATILE_P (postinc
) = 1;
1012 do_unlink (spreg
, get_frame_size (), all
, 1);
1014 if (lookup_attribute ("nesting", attrs
))
1016 rtx srcreg
= gen_rtx_REG (Pmode
, ret_regs
[fkind
]);
1017 emit_move_insn (srcreg
, postinc
);
1020 /* If we're calling other functions, they won't save their call-clobbered
1021 registers, so we must save (and restore) everything here. */
1022 if (!current_function_is_leaf
)
1025 expand_epilogue_reg_restore (spreg
, all
, true);
1027 /* Deallocate any space we left on the stack in case we needed to save the
1028 argument registers. */
1029 if (fkind
== EXCPT_HANDLER
)
1030 emit_insn (gen_addsi3 (spreg
, spreg
, GEN_INT (12)));
1032 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
, ret_regs
[fkind
])));
1035 /* Used while emitting the prologue to generate code to load the correct value
1036 into the PIC register, which is passed in DEST. */
1039 bfin_load_pic_reg (rtx dest
)
1041 struct cgraph_local_info
*i
= NULL
;
1044 i
= cgraph_local_info (current_function_decl
);
1046 /* Functions local to the translation unit don't need to reload the
1047 pic reg, since the caller always passes a usable one. */
1049 return pic_offset_table_rtx
;
1051 if (global_options_set
.x_bfin_library_id
)
1052 addr
= plus_constant (pic_offset_table_rtx
, -4 - bfin_library_id
* 4);
1054 addr
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
1055 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1056 UNSPEC_LIBRARY_OFFSET
));
1057 emit_insn (gen_movsi (dest
, gen_rtx_MEM (Pmode
, addr
)));
1061 /* Generate RTL for the prologue of the current function. */
1064 bfin_expand_prologue (void)
1066 HOST_WIDE_INT frame_size
= get_frame_size ();
1067 rtx spreg
= gen_rtx_REG (Pmode
, REG_SP
);
1068 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1069 rtx pic_reg_loaded
= NULL_RTX
;
1070 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1071 bool all
= lookup_attribute ("saveall", attrs
) != NULL_TREE
;
1073 if (fkind
!= SUBROUTINE
)
1075 expand_interrupt_handler_prologue (spreg
, fkind
, all
);
1079 if (crtl
->limit_stack
1080 || (TARGET_STACK_CHECK_L1
1081 && !DECL_NO_LIMIT_STACK (current_function_decl
)))
1083 HOST_WIDE_INT offset
1084 = bfin_initial_elimination_offset (ARG_POINTER_REGNUM
,
1085 STACK_POINTER_REGNUM
);
1086 rtx lim
= crtl
->limit_stack
? stack_limit_rtx
: NULL_RTX
;
1087 rtx tmp
= gen_rtx_REG (Pmode
, REG_R3
);
1088 rtx p2reg
= gen_rtx_REG (Pmode
, REG_P2
);
1090 emit_move_insn (tmp
, p2reg
);
1093 emit_move_insn (p2reg
, gen_int_mode (0xFFB00000, SImode
));
1094 emit_move_insn (p2reg
, gen_rtx_MEM (Pmode
, p2reg
));
1097 if (GET_CODE (lim
) == SYMBOL_REF
)
1099 if (TARGET_ID_SHARED_LIBRARY
)
1101 rtx p1reg
= gen_rtx_REG (Pmode
, REG_P1
);
1103 pic_reg_loaded
= bfin_load_pic_reg (p2reg
);
1104 val
= legitimize_pic_address (stack_limit_rtx
, p1reg
,
1106 emit_move_insn (p1reg
, val
);
1107 frame_related_constant_load (p2reg
, offset
, FALSE
);
1108 emit_insn (gen_addsi3 (p2reg
, p2reg
, p1reg
));
1113 rtx limit
= plus_constant (lim
, offset
);
1114 emit_move_insn (p2reg
, limit
);
1121 emit_move_insn (p2reg
, lim
);
1122 add_to_reg (p2reg
, offset
, 0, 0);
1125 emit_insn (gen_compare_lt (bfin_cc_rtx
, spreg
, lim
));
1126 emit_insn (gen_trapifcc ());
1127 emit_move_insn (p2reg
, tmp
);
1129 expand_prologue_reg_save (spreg
, all
, false);
1131 do_link (spreg
, frame_size
, all
);
1133 if (TARGET_ID_SHARED_LIBRARY
1135 && (crtl
->uses_pic_offset_table
1136 || !current_function_is_leaf
))
1137 bfin_load_pic_reg (pic_offset_table_rtx
);
1140 /* Generate RTL for the epilogue of the current function. NEED_RETURN is zero
1141 if this is for a sibcall. EH_RETURN is nonzero if we're expanding an
1142 eh_return pattern. SIBCALL_P is true if this is a sibcall epilogue,
1146 bfin_expand_epilogue (int need_return
, int eh_return
, bool sibcall_p
)
1148 rtx spreg
= gen_rtx_REG (Pmode
, REG_SP
);
1149 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1150 int e
= sibcall_p
? -1 : 1;
1151 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1152 bool all
= lookup_attribute ("saveall", attrs
) != NULL_TREE
;
1154 if (fkind
!= SUBROUTINE
)
1156 expand_interrupt_handler_epilogue (spreg
, fkind
, all
);
1160 do_unlink (spreg
, get_frame_size (), all
, e
);
1162 expand_epilogue_reg_restore (spreg
, all
, false);
1164 /* Omit the return insn if this is for a sibcall. */
1169 emit_insn (gen_addsi3 (spreg
, spreg
, gen_rtx_REG (Pmode
, REG_P2
)));
1171 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
, REG_RETS
)));
1174 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
1177 bfin_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
1178 unsigned int new_reg
)
1180 /* Interrupt functions can only use registers that have already been
1181 saved by the prologue, even if they would normally be
1184 if (funkind (TREE_TYPE (current_function_decl
)) != SUBROUTINE
1185 && !df_regs_ever_live_p (new_reg
))
1191 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
1193 bfin_extra_live_on_entry (bitmap regs
)
1196 bitmap_set_bit (regs
, FDPIC_REGNO
);
1199 /* Return the value of the return address for the frame COUNT steps up
1200 from the current frame, after the prologue.
1201 We punt for everything but the current frame by returning const0_rtx. */
1204 bfin_return_addr_rtx (int count
)
1209 return get_hard_reg_initial_val (Pmode
, REG_RETS
);
1213 bfin_delegitimize_address (rtx orig_x
)
1217 if (GET_CODE (x
) != MEM
)
1221 if (GET_CODE (x
) == PLUS
1222 && GET_CODE (XEXP (x
, 1)) == UNSPEC
1223 && XINT (XEXP (x
, 1), 1) == UNSPEC_MOVE_PIC
1224 && GET_CODE (XEXP (x
, 0)) == REG
1225 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
1226 return XVECEXP (XEXP (x
, 1), 0, 0);
1231 /* This predicate is used to compute the length of a load/store insn.
1232 OP is a MEM rtx, we return nonzero if its addressing mode requires a
1233 32-bit instruction. */
1236 effective_address_32bit_p (rtx op
, enum machine_mode mode
)
1238 HOST_WIDE_INT offset
;
1240 mode
= GET_MODE (op
);
1243 if (GET_CODE (op
) != PLUS
)
1245 gcc_assert (REG_P (op
) || GET_CODE (op
) == POST_INC
1246 || GET_CODE (op
) == PRE_DEC
|| GET_CODE (op
) == POST_DEC
);
1250 if (GET_CODE (XEXP (op
, 1)) == UNSPEC
)
1253 offset
= INTVAL (XEXP (op
, 1));
1255 /* All byte loads use a 16-bit offset. */
1256 if (GET_MODE_SIZE (mode
) == 1)
1259 if (GET_MODE_SIZE (mode
) == 4)
1261 /* Frame pointer relative loads can use a negative offset, all others
1262 are restricted to a small positive one. */
1263 if (XEXP (op
, 0) == frame_pointer_rtx
)
1264 return offset
< -128 || offset
> 60;
1265 return offset
< 0 || offset
> 60;
1268 /* Must be HImode now. */
1269 return offset
< 0 || offset
> 30;
1272 /* Returns true if X is a memory reference using an I register. */
1274 bfin_dsp_memref_p (rtx x
)
1279 if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_INC
1280 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == PRE_DEC
)
1285 /* Return cost of the memory address ADDR.
1286 All addressing modes are equally cheap on the Blackfin. */
1289 bfin_address_cost (rtx addr ATTRIBUTE_UNUSED
, bool speed ATTRIBUTE_UNUSED
)
1294 /* Subroutine of print_operand; used to print a memory reference X to FILE. */
1297 print_address_operand (FILE *file
, rtx x
)
1299 switch (GET_CODE (x
))
1302 output_address (XEXP (x
, 0));
1303 fprintf (file
, "+");
1304 output_address (XEXP (x
, 1));
1308 fprintf (file
, "--");
1309 output_address (XEXP (x
, 0));
1312 output_address (XEXP (x
, 0));
1313 fprintf (file
, "++");
1316 output_address (XEXP (x
, 0));
1317 fprintf (file
, "--");
1321 gcc_assert (GET_CODE (x
) != MEM
);
1322 print_operand (file
, x
, 0);
1327 /* Adding intp DImode support by Tony
1333 print_operand (FILE *file
, rtx x
, char code
)
1335 enum machine_mode mode
;
1339 if (GET_MODE (current_output_insn
) == SImode
)
1340 fprintf (file
, " ||");
1342 fprintf (file
, ";");
1346 mode
= GET_MODE (x
);
1351 switch (GET_CODE (x
))
1354 fprintf (file
, "e");
1357 fprintf (file
, "ne");
1360 fprintf (file
, "g");
1363 fprintf (file
, "l");
1366 fprintf (file
, "ge");
1369 fprintf (file
, "le");
1372 fprintf (file
, "g");
1375 fprintf (file
, "l");
1378 fprintf (file
, "ge");
1381 fprintf (file
, "le");
1384 output_operand_lossage ("invalid %%j value");
1388 case 'J': /* reverse logic */
1389 switch (GET_CODE(x
))
1392 fprintf (file
, "ne");
1395 fprintf (file
, "e");
1398 fprintf (file
, "le");
1401 fprintf (file
, "ge");
1404 fprintf (file
, "l");
1407 fprintf (file
, "g");
1410 fprintf (file
, "le");
1413 fprintf (file
, "ge");
1416 fprintf (file
, "l");
1419 fprintf (file
, "g");
1422 output_operand_lossage ("invalid %%J value");
1427 switch (GET_CODE (x
))
1433 fprintf (file
, "%s", short_reg_names
[REGNO (x
)]);
1435 output_operand_lossage ("invalid operand for code '%c'", code
);
1437 else if (code
== 'd')
1440 fprintf (file
, "%s", high_reg_names
[REGNO (x
)]);
1442 output_operand_lossage ("invalid operand for code '%c'", code
);
1444 else if (code
== 'w')
1446 if (REGNO (x
) == REG_A0
|| REGNO (x
) == REG_A1
)
1447 fprintf (file
, "%s.w", reg_names
[REGNO (x
)]);
1449 output_operand_lossage ("invalid operand for code '%c'", code
);
1451 else if (code
== 'x')
1453 if (REGNO (x
) == REG_A0
|| REGNO (x
) == REG_A1
)
1454 fprintf (file
, "%s.x", reg_names
[REGNO (x
)]);
1456 output_operand_lossage ("invalid operand for code '%c'", code
);
1458 else if (code
== 'v')
1460 if (REGNO (x
) == REG_A0
)
1461 fprintf (file
, "AV0");
1462 else if (REGNO (x
) == REG_A1
)
1463 fprintf (file
, "AV1");
1465 output_operand_lossage ("invalid operand for code '%c'", code
);
1467 else if (code
== 'D')
1469 if (D_REGNO_P (REGNO (x
)))
1470 fprintf (file
, "%s", dregs_pair_names
[REGNO (x
)]);
1472 output_operand_lossage ("invalid operand for code '%c'", code
);
1474 else if (code
== 'H')
1476 if ((mode
== DImode
|| mode
== DFmode
) && REG_P (x
))
1477 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
1479 output_operand_lossage ("invalid operand for code '%c'", code
);
1481 else if (code
== 'T')
1483 if (D_REGNO_P (REGNO (x
)))
1484 fprintf (file
, "%s", byte_reg_names
[REGNO (x
)]);
1486 output_operand_lossage ("invalid operand for code '%c'", code
);
1489 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1495 print_address_operand (file
, x
);
1507 fputs ("(FU)", file
);
1510 fputs ("(T)", file
);
1513 fputs ("(TFU)", file
);
1516 fputs ("(W32)", file
);
1519 fputs ("(IS)", file
);
1522 fputs ("(IU)", file
);
1525 fputs ("(IH)", file
);
1528 fputs ("(M)", file
);
1531 fputs ("(IS,M)", file
);
1534 fputs ("(ISS2)", file
);
1537 fputs ("(S2RND)", file
);
1544 else if (code
== 'b')
1546 if (INTVAL (x
) == 0)
1548 else if (INTVAL (x
) == 1)
1554 /* Moves to half registers with d or h modifiers always use unsigned
1556 else if (code
== 'd')
1557 x
= GEN_INT ((INTVAL (x
) >> 16) & 0xffff);
1558 else if (code
== 'h')
1559 x
= GEN_INT (INTVAL (x
) & 0xffff);
1560 else if (code
== 'N')
1561 x
= GEN_INT (-INTVAL (x
));
1562 else if (code
== 'X')
1563 x
= GEN_INT (exact_log2 (0xffffffff & INTVAL (x
)));
1564 else if (code
== 'Y')
1565 x
= GEN_INT (exact_log2 (0xffffffff & ~INTVAL (x
)));
1566 else if (code
== 'Z')
1567 /* Used for LINK insns. */
1568 x
= GEN_INT (-8 - INTVAL (x
));
1573 output_addr_const (file
, x
);
1577 output_operand_lossage ("invalid const_double operand");
1581 switch (XINT (x
, 1))
1583 case UNSPEC_MOVE_PIC
:
1584 output_addr_const (file
, XVECEXP (x
, 0, 0));
1585 fprintf (file
, "@GOT");
1588 case UNSPEC_MOVE_FDPIC
:
1589 output_addr_const (file
, XVECEXP (x
, 0, 0));
1590 fprintf (file
, "@GOT17M4");
1593 case UNSPEC_FUNCDESC_GOT17M4
:
1594 output_addr_const (file
, XVECEXP (x
, 0, 0));
1595 fprintf (file
, "@FUNCDESC_GOT17M4");
1598 case UNSPEC_LIBRARY_OFFSET
:
1599 fprintf (file
, "_current_shared_library_p5_offset_");
1608 output_addr_const (file
, x
);
1613 /* Argument support functions. */
1615 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1616 for a call to a function whose data type is FNTYPE.
1617 For a library call, FNTYPE is 0.
1618 VDSP C Compiler manual, our ABI says that
1619 first 3 words of arguments will use R0, R1 and R2.
1623 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
1624 rtx libname ATTRIBUTE_UNUSED
)
1626 static CUMULATIVE_ARGS zero_cum
;
1630 /* Set up the number of registers to use for passing arguments. */
1632 cum
->nregs
= max_arg_registers
;
1633 cum
->arg_regs
= arg_regs
;
1635 cum
->call_cookie
= CALL_NORMAL
;
1636 /* Check for a longcall attribute. */
1637 if (fntype
&& lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
)))
1638 cum
->call_cookie
|= CALL_SHORT
;
1639 else if (fntype
&& lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
)))
1640 cum
->call_cookie
|= CALL_LONG
;
1645 /* Update the data in CUM to advance over an argument
1646 of mode MODE and data type TYPE.
1647 (TYPE is null for libcalls where that information may not be available.) */
1650 bfin_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1651 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1653 int count
, bytes
, words
;
1655 bytes
= (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1656 words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1658 cum
->words
+= words
;
1659 cum
->nregs
-= words
;
1661 if (cum
->nregs
<= 0)
1664 cum
->arg_regs
= NULL
;
1668 for (count
= 1; count
<= words
; count
++)
1675 /* Define where to put the arguments to a function.
1676 Value is zero to push the argument on the stack,
1677 or a hard register in which to store the argument.
1679 MODE is the argument's machine mode.
1680 TYPE is the data type of the argument (as a tree).
1681 This is null for libcalls where that information may
1683 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1684 the preceding args and about the function being called.
1685 NAMED is nonzero if this argument is a named parameter
1686 (otherwise it is an extra parameter matching an ellipsis). */
1689 bfin_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1690 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1693 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1695 if (mode
== VOIDmode
)
1696 /* Compute operand 2 of the call insn. */
1697 return GEN_INT (cum
->call_cookie
);
1703 return gen_rtx_REG (mode
, *(cum
->arg_regs
));
1708 /* For an arg passed partly in registers and partly in memory,
1709 this is the number of bytes passed in registers.
1710 For args passed entirely in registers or entirely in memory, zero.
1712 Refer VDSP C Compiler manual, our ABI.
1713 First 3 words are in registers. So, if an argument is larger
1714 than the registers available, it will span the register and
1718 bfin_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1719 tree type ATTRIBUTE_UNUSED
,
1720 bool named ATTRIBUTE_UNUSED
)
1723 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1724 int bytes_left
= cum
->nregs
* UNITS_PER_WORD
;
1729 if (bytes_left
== 0)
1731 if (bytes
> bytes_left
)
1736 /* Variable sized types are passed by reference. */
1739 bfin_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
1740 enum machine_mode mode ATTRIBUTE_UNUSED
,
1741 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1743 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
1746 /* Decide whether a type should be returned in memory (true)
1747 or in a register (false). This is called by the macro
1748 TARGET_RETURN_IN_MEMORY. */
1751 bfin_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1753 int size
= int_size_in_bytes (type
);
1754 return size
> 2 * UNITS_PER_WORD
|| size
== -1;
1757 /* Register in which address to store a structure value
1758 is passed to a function. */
1760 bfin_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
1761 int incoming ATTRIBUTE_UNUSED
)
1763 return gen_rtx_REG (Pmode
, REG_P0
);
1766 /* Return true when register may be used to pass function parameters. */
1769 function_arg_regno_p (int n
)
1772 for (i
= 0; arg_regs
[i
] != -1; i
++)
1773 if (n
== arg_regs
[i
])
1778 /* Returns 1 if OP contains a symbol reference */
1781 symbolic_reference_mentioned_p (rtx op
)
1783 register const char *fmt
;
1786 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1789 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
1790 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
1796 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
1797 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
1801 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
1808 /* Decide whether we can make a sibling call to a function. DECL is the
1809 declaration of the function being targeted by the call and EXP is the
1810 CALL_EXPR representing the call. */
1813 bfin_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
1814 tree exp ATTRIBUTE_UNUSED
)
1816 struct cgraph_local_info
*this_func
, *called_func
;
1817 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1818 if (fkind
!= SUBROUTINE
)
1820 if (!TARGET_ID_SHARED_LIBRARY
|| TARGET_SEP_DATA
)
1823 /* When compiling for ID shared libraries, can't sibcall a local function
1824 from a non-local function, because the local function thinks it does
1825 not need to reload P5 in the prologue, but the sibcall wil pop P5 in the
1826 sibcall epilogue, and we end up with the wrong value in P5. */
1829 /* Not enough information. */
1832 this_func
= cgraph_local_info (current_function_decl
);
1833 called_func
= cgraph_local_info (decl
);
1836 return !called_func
->local
|| this_func
->local
;
1839 /* Write a template for a trampoline to F. */
1842 bfin_asm_trampoline_template (FILE *f
)
1846 fprintf (f
, "\t.dd\t0x00000000\n"); /* 0 */
1847 fprintf (f
, "\t.dd\t0x00000000\n"); /* 0 */
1848 fprintf (f
, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */
1849 fprintf (f
, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */
1850 fprintf (f
, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */
1851 fprintf (f
, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */
1852 fprintf (f
, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */
1853 fprintf (f
, "\t.dw\t0x9149\n"); /* p1 = [p1] */
1854 fprintf (f
, "\t.dw\t0x0051\n"); /* jump (p1)*/
1858 fprintf (f
, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */
1859 fprintf (f
, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */
1860 fprintf (f
, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */
1861 fprintf (f
, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */
1862 fprintf (f
, "\t.dw\t0x0051\n"); /* jump (p1)*/
1866 /* Emit RTL insns to initialize the variable parts of a trampoline at
1867 M_TRAMP. FNDECL is the target function. CHAIN_VALUE is an RTX for
1868 the static chain value for the function. */
1871 bfin_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
1873 rtx t1
= copy_to_reg (XEXP (DECL_RTL (fndecl
), 0));
1874 rtx t2
= copy_to_reg (chain_value
);
1878 emit_block_move (m_tramp
, assemble_trampoline_template (),
1879 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
1883 rtx a
= force_reg (Pmode
, plus_constant (XEXP (m_tramp
, 0), 8));
1884 mem
= adjust_address (m_tramp
, Pmode
, 0);
1885 emit_move_insn (mem
, a
);
1889 mem
= adjust_address (m_tramp
, HImode
, i
+ 2);
1890 emit_move_insn (mem
, gen_lowpart (HImode
, t1
));
1891 emit_insn (gen_ashrsi3 (t1
, t1
, GEN_INT (16)));
1892 mem
= adjust_address (m_tramp
, HImode
, i
+ 6);
1893 emit_move_insn (mem
, gen_lowpart (HImode
, t1
));
1895 mem
= adjust_address (m_tramp
, HImode
, i
+ 10);
1896 emit_move_insn (mem
, gen_lowpart (HImode
, t2
));
1897 emit_insn (gen_ashrsi3 (t2
, t2
, GEN_INT (16)));
1898 mem
= adjust_address (m_tramp
, HImode
, i
+ 14);
1899 emit_move_insn (mem
, gen_lowpart (HImode
, t2
));
1902 /* Emit insns to move operands[1] into operands[0]. */
1905 emit_pic_move (rtx
*operands
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1907 rtx temp
= reload_in_progress
? operands
[0] : gen_reg_rtx (Pmode
);
1909 gcc_assert (!TARGET_FDPIC
|| !(reload_in_progress
|| reload_completed
));
1910 if (GET_CODE (operands
[0]) == MEM
&& SYMBOLIC_CONST (operands
[1]))
1911 operands
[1] = force_reg (SImode
, operands
[1]);
1913 operands
[1] = legitimize_pic_address (operands
[1], temp
,
1914 TARGET_FDPIC
? OUR_FDPIC_REG
1915 : pic_offset_table_rtx
);
1918 /* Expand a move operation in mode MODE. The operands are in OPERANDS.
1919 Returns true if no further code must be generated, false if the caller
1920 should generate an insn to move OPERANDS[1] to OPERANDS[0]. */
1923 expand_move (rtx
*operands
, enum machine_mode mode
)
1925 rtx op
= operands
[1];
1926 if ((TARGET_ID_SHARED_LIBRARY
|| TARGET_FDPIC
)
1927 && SYMBOLIC_CONST (op
))
1928 emit_pic_move (operands
, mode
);
1929 else if (mode
== SImode
&& GET_CODE (op
) == CONST
1930 && GET_CODE (XEXP (op
, 0)) == PLUS
1931 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
1932 && !targetm
.legitimate_constant_p (mode
, op
))
1934 rtx dest
= operands
[0];
1936 gcc_assert (!reload_in_progress
&& !reload_completed
);
1938 op0
= force_reg (mode
, XEXP (op
, 0));
1940 if (!insn_data
[CODE_FOR_addsi3
].operand
[2].predicate (op1
, mode
))
1941 op1
= force_reg (mode
, op1
);
1942 if (GET_CODE (dest
) == MEM
)
1943 dest
= gen_reg_rtx (mode
);
1944 emit_insn (gen_addsi3 (dest
, op0
, op1
));
1945 if (dest
== operands
[0])
1949 /* Don't generate memory->memory or constant->memory moves, go through a
1951 else if ((reload_in_progress
| reload_completed
) == 0
1952 && GET_CODE (operands
[0]) == MEM
1953 && GET_CODE (operands
[1]) != REG
)
1954 operands
[1] = force_reg (mode
, operands
[1]);
1958 /* Split one or more DImode RTL references into pairs of SImode
1959 references. The RTL can be REG, offsettable MEM, integer constant, or
1960 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
1961 split and "num" is its length. lo_half and hi_half are output arrays
1962 that parallel "operands". */
1965 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
1969 rtx op
= operands
[num
];
1971 /* simplify_subreg refuse to split volatile memory addresses,
1972 but we still have to handle it. */
1973 if (GET_CODE (op
) == MEM
)
1975 lo_half
[num
] = adjust_address (op
, SImode
, 0);
1976 hi_half
[num
] = adjust_address (op
, SImode
, 4);
1980 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
1981 GET_MODE (op
) == VOIDmode
1982 ? DImode
: GET_MODE (op
), 0);
1983 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
1984 GET_MODE (op
) == VOIDmode
1985 ? DImode
: GET_MODE (op
), 4);
1991 bfin_longcall_p (rtx op
, int call_cookie
)
1993 gcc_assert (GET_CODE (op
) == SYMBOL_REF
);
1994 if (SYMBOL_REF_WEAK (op
))
1996 if (call_cookie
& CALL_SHORT
)
1998 if (call_cookie
& CALL_LONG
)
2000 if (TARGET_LONG_CALLS
)
2005 /* Expand a call instruction. FNADDR is the call target, RETVAL the return value.
2006 COOKIE is a CONST_INT holding the call_cookie prepared init_cumulative_args.
2007 SIBCALL is nonzero if this is a sibling call. */
2010 bfin_expand_call (rtx retval
, rtx fnaddr
, rtx callarg1
, rtx cookie
, int sibcall
)
2012 rtx use
= NULL
, call
;
2013 rtx callee
= XEXP (fnaddr
, 0);
2016 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REGNO
);
2017 rtx retsreg
= gen_rtx_REG (Pmode
, REG_RETS
);
2020 /* In an untyped call, we can get NULL for operand 2. */
2021 if (cookie
== NULL_RTX
)
2022 cookie
= const0_rtx
;
2024 /* Static functions and indirect calls don't need the pic register. */
2025 if (!TARGET_FDPIC
&& flag_pic
2026 && GET_CODE (callee
) == SYMBOL_REF
2027 && !SYMBOL_REF_LOCAL_P (callee
))
2028 use_reg (&use
, pic_offset_table_rtx
);
2032 int caller_in_sram
, callee_in_sram
;
2034 /* 0 is not in sram, 1 is in L1 sram, 2 is in L2 sram. */
2035 caller_in_sram
= callee_in_sram
= 0;
2037 if (lookup_attribute ("l1_text",
2038 DECL_ATTRIBUTES (cfun
->decl
)) != NULL_TREE
)
2040 else if (lookup_attribute ("l2",
2041 DECL_ATTRIBUTES (cfun
->decl
)) != NULL_TREE
)
2044 if (GET_CODE (callee
) == SYMBOL_REF
2045 && SYMBOL_REF_DECL (callee
) && DECL_P (SYMBOL_REF_DECL (callee
)))
2047 if (lookup_attribute
2049 DECL_ATTRIBUTES (SYMBOL_REF_DECL (callee
))) != NULL_TREE
)
2051 else if (lookup_attribute
2053 DECL_ATTRIBUTES (SYMBOL_REF_DECL (callee
))) != NULL_TREE
)
2057 if (GET_CODE (callee
) != SYMBOL_REF
2058 || bfin_longcall_p (callee
, INTVAL (cookie
))
2059 || (GET_CODE (callee
) == SYMBOL_REF
2060 && !SYMBOL_REF_LOCAL_P (callee
)
2061 && TARGET_INLINE_PLT
)
2062 || caller_in_sram
!= callee_in_sram
2063 || (caller_in_sram
&& callee_in_sram
2064 && (GET_CODE (callee
) != SYMBOL_REF
2065 || !SYMBOL_REF_LOCAL_P (callee
))))
2068 if (! address_operand (addr
, Pmode
))
2069 addr
= force_reg (Pmode
, addr
);
2071 fnaddr
= gen_reg_rtx (SImode
);
2072 emit_insn (gen_load_funcdescsi (fnaddr
, addr
));
2073 fnaddr
= gen_rtx_MEM (Pmode
, fnaddr
);
2075 picreg
= gen_reg_rtx (SImode
);
2076 emit_insn (gen_load_funcdescsi (picreg
,
2077 plus_constant (addr
, 4)));
2082 else if ((!register_no_elim_operand (callee
, Pmode
)
2083 && GET_CODE (callee
) != SYMBOL_REF
)
2084 || (GET_CODE (callee
) == SYMBOL_REF
2085 && ((TARGET_ID_SHARED_LIBRARY
&& !TARGET_LEAF_ID_SHARED_LIBRARY
)
2086 || bfin_longcall_p (callee
, INTVAL (cookie
)))))
2088 callee
= copy_to_mode_reg (Pmode
, callee
);
2089 fnaddr
= gen_rtx_MEM (Pmode
, callee
);
2091 call
= gen_rtx_CALL (VOIDmode
, fnaddr
, callarg1
);
2094 call
= gen_rtx_SET (VOIDmode
, retval
, call
);
2096 pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nelts
));
2098 XVECEXP (pat
, 0, n
++) = call
;
2100 XVECEXP (pat
, 0, n
++) = gen_rtx_USE (VOIDmode
, picreg
);
2101 XVECEXP (pat
, 0, n
++) = gen_rtx_USE (VOIDmode
, cookie
);
2103 XVECEXP (pat
, 0, n
++) = ret_rtx
;
2105 XVECEXP (pat
, 0, n
++) = gen_rtx_CLOBBER (VOIDmode
, retsreg
);
2106 call
= emit_call_insn (pat
);
2108 CALL_INSN_FUNCTION_USAGE (call
) = use
;
2111 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
2114 hard_regno_mode_ok (int regno
, enum machine_mode mode
)
2116 /* Allow only dregs to store value of mode HI or QI */
2117 enum reg_class rclass
= REGNO_REG_CLASS (regno
);
2122 if (mode
== V2HImode
)
2123 return D_REGNO_P (regno
);
2124 if (rclass
== CCREGS
)
2125 return mode
== BImode
;
2126 if (mode
== PDImode
|| mode
== V2PDImode
)
2127 return regno
== REG_A0
|| regno
== REG_A1
;
2129 /* Allow all normal 32-bit regs, except REG_M3, in case regclass ever comes
2130 up with a bad register class (such as ALL_REGS) for DImode. */
2132 return regno
< REG_M3
;
2135 && TEST_HARD_REG_BIT (reg_class_contents
[PROLOGUE_REGS
], regno
))
2138 return TEST_HARD_REG_BIT (reg_class_contents
[MOST_REGS
], regno
);
2141 /* Implements target hook vector_mode_supported_p. */
2144 bfin_vector_mode_supported_p (enum machine_mode mode
)
2146 return mode
== V2HImode
;
2149 /* Return the cost of moving data from a register in class CLASS1 to
2150 one in class CLASS2. A cost of 2 is the default. */
2153 bfin_register_move_cost (enum machine_mode mode
,
2154 enum reg_class class1
, enum reg_class class2
)
2156 /* These need secondary reloads, so they're more expensive. */
2157 if ((class1
== CCREGS
&& !reg_class_subset_p (class2
, DREGS
))
2158 || (class2
== CCREGS
&& !reg_class_subset_p (class1
, DREGS
)))
2161 /* If optimizing for size, always prefer reg-reg over reg-memory moves. */
2165 if (GET_MODE_CLASS (mode
) == MODE_INT
)
2167 /* Discourage trying to use the accumulators. */
2168 if (TEST_HARD_REG_BIT (reg_class_contents
[class1
], REG_A0
)
2169 || TEST_HARD_REG_BIT (reg_class_contents
[class1
], REG_A1
)
2170 || TEST_HARD_REG_BIT (reg_class_contents
[class2
], REG_A0
)
2171 || TEST_HARD_REG_BIT (reg_class_contents
[class2
], REG_A1
))
2177 /* Return the cost of moving data of mode M between a
2178 register and memory. A value of 2 is the default; this cost is
2179 relative to those in `REGISTER_MOVE_COST'.
2181 ??? In theory L1 memory has single-cycle latency. We should add a switch
2182 that tells the compiler whether we expect to use only L1 memory for the
2183 program; it'll make the costs more accurate. */
2186 bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2187 enum reg_class rclass
,
2188 int in ATTRIBUTE_UNUSED
)
2190 /* Make memory accesses slightly more expensive than any register-register
2191 move. Also, penalize non-DP registers, since they need secondary
2192 reloads to load and store. */
2193 if (! reg_class_subset_p (rclass
, DPREGS
))
2199 /* Inform reload about cases where moving X with a mode MODE to a register in
2200 RCLASS requires an extra scratch register. Return the class needed for the
2201 scratch register. */
2204 bfin_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
2205 enum machine_mode mode
, secondary_reload_info
*sri
)
2207 /* If we have HImode or QImode, we can only use DREGS as secondary registers;
2208 in most other cases we can also use PREGS. */
2209 enum reg_class default_class
= GET_MODE_SIZE (mode
) >= 4 ? DPREGS
: DREGS
;
2210 enum reg_class x_class
= NO_REGS
;
2211 enum rtx_code code
= GET_CODE (x
);
2212 enum reg_class rclass
= (enum reg_class
) rclass_i
;
2215 x
= SUBREG_REG (x
), code
= GET_CODE (x
);
2218 int regno
= REGNO (x
);
2219 if (regno
>= FIRST_PSEUDO_REGISTER
)
2220 regno
= reg_renumber
[regno
];
2225 x_class
= REGNO_REG_CLASS (regno
);
2228 /* We can be asked to reload (plus (FP) (large_constant)) into a DREG.
2229 This happens as a side effect of register elimination, and we need
2230 a scratch register to do it. */
2231 if (fp_plus_const_operand (x
, mode
))
2233 rtx op2
= XEXP (x
, 1);
2234 int large_constant_p
= ! satisfies_constraint_Ks7 (op2
);
2236 if (rclass
== PREGS
|| rclass
== PREGS_CLOBBERED
)
2238 /* If destination is a DREG, we can do this without a scratch register
2239 if the constant is valid for an add instruction. */
2240 if ((rclass
== DREGS
|| rclass
== DPREGS
)
2241 && ! large_constant_p
)
2243 /* Reloading to anything other than a DREG? Use a PREG scratch
2245 sri
->icode
= CODE_FOR_reload_insi
;
2249 /* Data can usually be moved freely between registers of most classes.
2250 AREGS are an exception; they can only move to or from another register
2251 in AREGS or one in DREGS. They can also be assigned the constant 0. */
2252 if (x_class
== AREGS
|| x_class
== EVEN_AREGS
|| x_class
== ODD_AREGS
)
2253 return (rclass
== DREGS
|| rclass
== AREGS
|| rclass
== EVEN_AREGS
2254 || rclass
== ODD_AREGS
2257 if (rclass
== AREGS
|| rclass
== EVEN_AREGS
|| rclass
== ODD_AREGS
)
2261 sri
->icode
= in_p
? CODE_FOR_reload_inpdi
: CODE_FOR_reload_outpdi
;
2265 if (x
!= const0_rtx
&& x_class
!= DREGS
)
2273 /* CCREGS can only be moved from/to DREGS. */
2274 if (rclass
== CCREGS
&& x_class
!= DREGS
)
2276 if (x_class
== CCREGS
&& rclass
!= DREGS
)
2279 /* All registers other than AREGS can load arbitrary constants. The only
2280 case that remains is MEM. */
2282 if (! reg_class_subset_p (rclass
, default_class
))
2283 return default_class
;
2288 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
2291 bfin_class_likely_spilled_p (reg_class_t rclass
)
2295 case PREGS_CLOBBERED
:
2311 static struct machine_function
*
2312 bfin_init_machine_status (void)
2314 return ggc_alloc_cleared_machine_function ();
2317 /* Implement the TARGET_OPTION_OVERRIDE hook. */
2320 bfin_option_override (void)
2322 /* If processor type is not specified, enable all workarounds. */
2323 if (bfin_cpu_type
== BFIN_CPU_UNKNOWN
)
2327 for (i
= 0; bfin_cpus
[i
].name
!= NULL
; i
++)
2328 bfin_workarounds
|= bfin_cpus
[i
].workarounds
;
2330 bfin_si_revision
= 0xffff;
2333 if (bfin_csync_anomaly
== 1)
2334 bfin_workarounds
|= WA_SPECULATIVE_SYNCS
;
2335 else if (bfin_csync_anomaly
== 0)
2336 bfin_workarounds
&= ~WA_SPECULATIVE_SYNCS
;
2338 if (bfin_specld_anomaly
== 1)
2339 bfin_workarounds
|= WA_SPECULATIVE_LOADS
;
2340 else if (bfin_specld_anomaly
== 0)
2341 bfin_workarounds
&= ~WA_SPECULATIVE_LOADS
;
2343 if (TARGET_OMIT_LEAF_FRAME_POINTER
)
2344 flag_omit_frame_pointer
= 1;
2346 #ifdef SUBTARGET_FDPIC_NOT_SUPPORTED
2348 error ("-mfdpic is not supported, please use a bfin-linux-uclibc target");
2351 /* Library identification */
2352 if (global_options_set
.x_bfin_library_id
&& ! TARGET_ID_SHARED_LIBRARY
)
2353 error ("-mshared-library-id= specified without -mid-shared-library");
2355 if (stack_limit_rtx
&& TARGET_FDPIC
)
2357 warning (0, "-fstack-limit- options are ignored with -mfdpic; use -mstack-check-l1");
2358 stack_limit_rtx
= NULL_RTX
;
2361 if (stack_limit_rtx
&& TARGET_STACK_CHECK_L1
)
2362 error ("can%'t use multiple stack checking methods together");
2364 if (TARGET_ID_SHARED_LIBRARY
&& TARGET_FDPIC
)
2365 error ("ID shared libraries and FD-PIC mode can%'t be used together");
2367 /* Don't allow the user to specify -mid-shared-library and -msep-data
2368 together, as it makes little sense from a user's point of view... */
2369 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
2370 error ("cannot specify both -msep-data and -mid-shared-library");
2371 /* ... internally, however, it's nearly the same. */
2372 if (TARGET_SEP_DATA
)
2373 target_flags
|= MASK_ID_SHARED_LIBRARY
| MASK_LEAF_ID_SHARED_LIBRARY
;
2375 if (TARGET_ID_SHARED_LIBRARY
&& flag_pic
== 0)
2378 /* There is no single unaligned SI op for PIC code. Sometimes we
2379 need to use ".4byte" and sometimes we need to use ".picptr".
2380 See bfin_assemble_integer for details. */
2382 targetm
.asm_out
.unaligned_op
.si
= 0;
2384 /* Silently turn off flag_pic if not doing FDPIC or ID shared libraries,
2385 since we don't support it and it'll just break. */
2386 if (flag_pic
&& !TARGET_FDPIC
&& !TARGET_ID_SHARED_LIBRARY
)
2389 if (TARGET_MULTICORE
&& bfin_cpu_type
!= BFIN_CPU_BF561
)
2390 error ("-mmulticore can only be used with BF561");
2392 if (TARGET_COREA
&& !TARGET_MULTICORE
)
2393 error ("-mcorea should be used with -mmulticore");
2395 if (TARGET_COREB
&& !TARGET_MULTICORE
)
2396 error ("-mcoreb should be used with -mmulticore");
2398 if (TARGET_COREA
&& TARGET_COREB
)
2399 error ("-mcorea and -mcoreb can%'t be used together");
2401 flag_schedule_insns
= 0;
2403 init_machine_status
= bfin_init_machine_status
;
2406 /* Return the destination address of BRANCH.
2407 We need to use this instead of get_attr_length, because the
2408 cbranch_with_nops pattern conservatively sets its length to 6, and
2409 we still prefer to use shorter sequences. */
2412 branch_dest (rtx branch
)
2416 rtx pat
= PATTERN (branch
);
2417 if (GET_CODE (pat
) == PARALLEL
)
2418 pat
= XVECEXP (pat
, 0, 0);
2419 dest
= SET_SRC (pat
);
2420 if (GET_CODE (dest
) == IF_THEN_ELSE
)
2421 dest
= XEXP (dest
, 1);
2422 dest
= XEXP (dest
, 0);
2423 dest_uid
= INSN_UID (dest
);
2424 return INSN_ADDRESSES (dest_uid
);
2427 /* Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates
2428 it's a branch that's predicted taken. */
2431 cbranch_predicted_taken_p (rtx insn
)
2433 rtx x
= find_reg_note (insn
, REG_BR_PROB
, 0);
2437 int pred_val
= INTVAL (XEXP (x
, 0));
2439 return pred_val
>= REG_BR_PROB_BASE
/ 2;
2445 /* Templates for use by asm_conditional_branch. */
2447 static const char *ccbranch_templates
[][3] = {
2448 { "if !cc jump %3;", "if cc jump 4 (bp); jump.s %3;", "if cc jump 6 (bp); jump.l %3;" },
2449 { "if cc jump %3;", "if !cc jump 4 (bp); jump.s %3;", "if !cc jump 6 (bp); jump.l %3;" },
2450 { "if !cc jump %3 (bp);", "if cc jump 4; jump.s %3;", "if cc jump 6; jump.l %3;" },
2451 { "if cc jump %3 (bp);", "if !cc jump 4; jump.s %3;", "if !cc jump 6; jump.l %3;" },
2454 /* Output INSN, which is a conditional branch instruction with operands
2457 We deal with the various forms of conditional branches that can be generated
2458 by bfin_reorg to prevent the hardware from doing speculative loads, by
2459 - emitting a sufficient number of nops, if N_NOPS is nonzero, or
2460 - always emitting the branch as predicted taken, if PREDICT_TAKEN is true.
2461 Either of these is only necessary if the branch is short, otherwise the
2462 template we use ends in an unconditional jump which flushes the pipeline
2466 asm_conditional_branch (rtx insn
, rtx
*operands
, int n_nops
, int predict_taken
)
2468 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
2469 /* Note : offset for instructions like if cc jmp; jump.[sl] offset
2470 is to be taken from start of if cc rather than jump.
2471 Range for jump.s is (-4094, 4096) instead of (-4096, 4094)
2473 int len
= (offset
>= -1024 && offset
<= 1022 ? 0
2474 : offset
>= -4094 && offset
<= 4096 ? 1
2476 int bp
= predict_taken
&& len
== 0 ? 1 : cbranch_predicted_taken_p (insn
);
2477 int idx
= (bp
<< 1) | (GET_CODE (operands
[0]) == EQ
? BRF
: BRT
);
2478 output_asm_insn (ccbranch_templates
[idx
][len
], operands
);
2479 gcc_assert (n_nops
== 0 || !bp
);
2481 while (n_nops
-- > 0)
2482 output_asm_insn ("nop;", NULL
);
2485 /* Emit rtl for a comparison operation CMP in mode MODE. Operands have been
2486 stored in bfin_compare_op0 and bfin_compare_op1 already. */
2489 bfin_gen_compare (rtx cmp
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2491 enum rtx_code code1
, code2
;
2492 rtx op0
= XEXP (cmp
, 0), op1
= XEXP (cmp
, 1);
2493 rtx tem
= bfin_cc_rtx
;
2494 enum rtx_code code
= GET_CODE (cmp
);
2496 /* If we have a BImode input, then we already have a compare result, and
2497 do not need to emit another comparison. */
2498 if (GET_MODE (op0
) == BImode
)
2500 gcc_assert ((code
== NE
|| code
== EQ
) && op1
== const0_rtx
);
2501 tem
= op0
, code2
= code
;
2506 /* bfin has these conditions */
2516 code1
= reverse_condition (code
);
2520 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
2521 gen_rtx_fmt_ee (code1
, BImode
, op0
, op1
)));
2524 return gen_rtx_fmt_ee (code2
, BImode
, tem
, CONST0_RTX (BImode
));
2527 /* Return nonzero iff C has exactly one bit set if it is interpreted
2528 as a 32-bit constant. */
2531 log2constp (unsigned HOST_WIDE_INT c
)
2534 return c
!= 0 && (c
& (c
-1)) == 0;
2537 /* Returns the number of consecutive least significant zeros in the binary
2538 representation of *V.
2539 We modify *V to contain the original value arithmetically shifted right by
2540 the number of zeroes. */
2543 shiftr_zero (HOST_WIDE_INT
*v
)
2545 unsigned HOST_WIDE_INT tmp
= *v
;
2546 unsigned HOST_WIDE_INT sgn
;
2552 sgn
= tmp
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1));
2553 while ((tmp
& 0x1) == 0 && n
<= 32)
2555 tmp
= (tmp
>> 1) | sgn
;
2562 /* After reload, split the load of an immediate constant. OPERANDS are the
2563 operands of the movsi_insn pattern which we are splitting. We return
2564 nonzero if we emitted a sequence to load the constant, zero if we emitted
2565 nothing because we want to use the splitter's default sequence. */
2568 split_load_immediate (rtx operands
[])
2570 HOST_WIDE_INT val
= INTVAL (operands
[1]);
2572 HOST_WIDE_INT shifted
= val
;
2573 HOST_WIDE_INT shifted_compl
= ~val
;
2574 int num_zero
= shiftr_zero (&shifted
);
2575 int num_compl_zero
= shiftr_zero (&shifted_compl
);
2576 unsigned int regno
= REGNO (operands
[0]);
2578 /* This case takes care of single-bit set/clear constants, which we could
2579 also implement with BITSET/BITCLR. */
2581 && shifted
>= -32768 && shifted
< 65536
2582 && (D_REGNO_P (regno
)
2583 || (regno
>= REG_P0
&& regno
<= REG_P7
&& num_zero
<= 2)))
2585 emit_insn (gen_movsi (operands
[0], GEN_INT (shifted
)));
2586 emit_insn (gen_ashlsi3 (operands
[0], operands
[0], GEN_INT (num_zero
)));
2591 tmp
|= -(tmp
& 0x8000);
2593 /* If high word has one bit set or clear, try to use a bit operation. */
2594 if (D_REGNO_P (regno
))
2596 if (log2constp (val
& 0xFFFF0000))
2598 emit_insn (gen_movsi (operands
[0], GEN_INT (val
& 0xFFFF)));
2599 emit_insn (gen_iorsi3 (operands
[0], operands
[0], GEN_INT (val
& 0xFFFF0000)));
2602 else if (log2constp (val
| 0xFFFF) && (val
& 0x8000) != 0)
2604 emit_insn (gen_movsi (operands
[0], GEN_INT (tmp
)));
2605 emit_insn (gen_andsi3 (operands
[0], operands
[0], GEN_INT (val
| 0xFFFF)));
2609 if (D_REGNO_P (regno
))
2611 if (tmp
>= -64 && tmp
<= 63)
2613 emit_insn (gen_movsi (operands
[0], GEN_INT (tmp
)));
2614 emit_insn (gen_movstricthi_high (operands
[0], GEN_INT (val
& -65536)));
2618 if ((val
& 0xFFFF0000) == 0)
2620 emit_insn (gen_movsi (operands
[0], const0_rtx
));
2621 emit_insn (gen_movsi_low (operands
[0], operands
[0], operands
[1]));
2625 if ((val
& 0xFFFF0000) == 0xFFFF0000)
2627 emit_insn (gen_movsi (operands
[0], constm1_rtx
));
2628 emit_insn (gen_movsi_low (operands
[0], operands
[0], operands
[1]));
2633 /* Need DREGs for the remaining case. */
2638 && num_compl_zero
&& shifted_compl
>= -64 && shifted_compl
<= 63)
2640 /* If optimizing for size, generate a sequence that has more instructions
2642 emit_insn (gen_movsi (operands
[0], GEN_INT (shifted_compl
)));
2643 emit_insn (gen_ashlsi3 (operands
[0], operands
[0],
2644 GEN_INT (num_compl_zero
)));
2645 emit_insn (gen_one_cmplsi2 (operands
[0], operands
[0]));
2651 /* Return true if the legitimate memory address for a memory operand of mode
2652 MODE. Return false if not. */
2655 bfin_valid_add (enum machine_mode mode
, HOST_WIDE_INT value
)
2657 unsigned HOST_WIDE_INT v
= value
> 0 ? value
: -value
;
2658 int sz
= GET_MODE_SIZE (mode
);
2659 int shift
= sz
== 1 ? 0 : sz
== 2 ? 1 : 2;
2660 /* The usual offsettable_memref machinery doesn't work so well for this
2661 port, so we deal with the problem here. */
2662 if (value
> 0 && sz
== 8)
2664 return (v
& ~(0x7fff << shift
)) == 0;
2668 bfin_valid_reg_p (unsigned int regno
, int strict
, enum machine_mode mode
,
2669 enum rtx_code outer_code
)
2672 return REGNO_OK_FOR_BASE_STRICT_P (regno
, mode
, outer_code
, SCRATCH
);
2674 return REGNO_OK_FOR_BASE_NONSTRICT_P (regno
, mode
, outer_code
, SCRATCH
);
2677 /* Recognize an RTL expression that is a valid memory address for an
2678 instruction. The MODE argument is the machine mode for the MEM expression
2679 that wants to use this address.
2681 Blackfin addressing modes are as follows:
2687 W [ Preg + uimm16m2 ]
2696 bfin_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
2698 switch (GET_CODE (x
)) {
2700 if (bfin_valid_reg_p (REGNO (x
), strict
, mode
, MEM
))
2704 if (REG_P (XEXP (x
, 0))
2705 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, PLUS
)
2706 && ((GET_CODE (XEXP (x
, 1)) == UNSPEC
&& mode
== SImode
)
2707 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2708 && bfin_valid_add (mode
, INTVAL (XEXP (x
, 1))))))
2713 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode
)
2714 && REG_P (XEXP (x
, 0))
2715 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, POST_INC
))
2718 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode
)
2719 && XEXP (x
, 0) == stack_pointer_rtx
2720 && REG_P (XEXP (x
, 0))
2721 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, PRE_DEC
))
2730 /* Decide whether we can force certain constants to memory. If we
2731 decide we can't, the caller should be able to cope with it in
2735 bfin_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
,
2736 rtx x ATTRIBUTE_UNUSED
)
2738 /* We have only one class of non-legitimate constants, and our movsi
2739 expander knows how to handle them. Dropping these constants into the
2740 data section would only shift the problem - we'd still get relocs
2741 outside the object, in the data section rather than the text section. */
2745 /* Ensure that for any constant of the form symbol + offset, the offset
2746 remains within the object. Any other constants are ok.
2747 This ensures that flat binaries never have to deal with relocations
2748 crossing section boundaries. */
2751 bfin_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2754 HOST_WIDE_INT offset
;
2756 if (GET_CODE (x
) != CONST
)
2760 gcc_assert (GET_CODE (x
) == PLUS
);
2764 if (GET_CODE (sym
) != SYMBOL_REF
2765 || GET_CODE (x
) != CONST_INT
)
2767 offset
= INTVAL (x
);
2769 if (SYMBOL_REF_DECL (sym
) == 0)
2772 || offset
>= int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (sym
))))
2779 bfin_rtx_costs (rtx x
, int code_i
, int outer_code_i
, int *total
, bool speed
)
2781 enum rtx_code code
= (enum rtx_code
) code_i
;
2782 enum rtx_code outer_code
= (enum rtx_code
) outer_code_i
;
2783 int cost2
= COSTS_N_INSNS (1);
2789 if (outer_code
== SET
|| outer_code
== PLUS
)
2790 *total
= satisfies_constraint_Ks7 (x
) ? 0 : cost2
;
2791 else if (outer_code
== AND
)
2792 *total
= log2constp (~INTVAL (x
)) ? 0 : cost2
;
2793 else if (outer_code
== LE
|| outer_code
== LT
|| outer_code
== EQ
)
2794 *total
= (INTVAL (x
) >= -4 && INTVAL (x
) <= 3) ? 0 : cost2
;
2795 else if (outer_code
== LEU
|| outer_code
== LTU
)
2796 *total
= (INTVAL (x
) >= 0 && INTVAL (x
) <= 7) ? 0 : cost2
;
2797 else if (outer_code
== MULT
)
2798 *total
= (INTVAL (x
) == 2 || INTVAL (x
) == 4) ? 0 : cost2
;
2799 else if (outer_code
== ASHIFT
&& (INTVAL (x
) == 1 || INTVAL (x
) == 2))
2801 else if (outer_code
== ASHIFT
|| outer_code
== ASHIFTRT
2802 || outer_code
== LSHIFTRT
)
2803 *total
= (INTVAL (x
) >= 0 && INTVAL (x
) <= 31) ? 0 : cost2
;
2804 else if (outer_code
== IOR
|| outer_code
== XOR
)
2805 *total
= (INTVAL (x
) & (INTVAL (x
) - 1)) == 0 ? 0 : cost2
;
2814 *total
= COSTS_N_INSNS (2);
2820 if (GET_MODE (x
) == SImode
)
2822 if (GET_CODE (op0
) == MULT
2823 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
2825 HOST_WIDE_INT val
= INTVAL (XEXP (op0
, 1));
2826 if (val
== 2 || val
== 4)
2829 *total
+= rtx_cost (XEXP (op0
, 0), outer_code
, speed
);
2830 *total
+= rtx_cost (op1
, outer_code
, speed
);
2835 if (GET_CODE (op0
) != REG
2836 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2837 *total
+= rtx_cost (op0
, SET
, speed
);
2838 #if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer
2839 towards creating too many induction variables. */
2840 if (!reg_or_7bit_operand (op1
, SImode
))
2841 *total
+= rtx_cost (op1
, SET
, speed
);
2844 else if (GET_MODE (x
) == DImode
)
2847 if (GET_CODE (op1
) != CONST_INT
2848 || !satisfies_constraint_Ks7 (op1
))
2849 *total
+= rtx_cost (op1
, PLUS
, speed
);
2850 if (GET_CODE (op0
) != REG
2851 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2852 *total
+= rtx_cost (op0
, PLUS
, speed
);
2857 if (GET_MODE (x
) == DImode
)
2866 if (GET_MODE (x
) == DImode
)
2873 if (GET_CODE (op0
) != REG
2874 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2875 *total
+= rtx_cost (op0
, code
, speed
);
2885 /* Handle special cases of IOR: rotates, ALIGN insns, movstricthi_high. */
2888 if ((GET_CODE (op0
) == LSHIFTRT
&& GET_CODE (op1
) == ASHIFT
)
2889 || (GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == ZERO_EXTEND
)
2890 || (GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
2891 || (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == CONST_INT
))
2898 if (GET_CODE (op0
) != REG
2899 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2900 *total
+= rtx_cost (op0
, code
, speed
);
2902 if (GET_MODE (x
) == DImode
)
2908 if (GET_MODE (x
) != SImode
)
2913 if (! rhs_andsi3_operand (XEXP (x
, 1), SImode
))
2914 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
2918 if (! regorlog2_operand (XEXP (x
, 1), SImode
))
2919 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
2926 if (outer_code
== SET
2927 && XEXP (x
, 1) == const1_rtx
2928 && GET_CODE (XEXP (x
, 2)) == CONST_INT
)
2944 if (GET_CODE (op0
) == GET_CODE (op1
)
2945 && (GET_CODE (op0
) == ZERO_EXTEND
2946 || GET_CODE (op0
) == SIGN_EXTEND
))
2948 *total
= COSTS_N_INSNS (1);
2949 op0
= XEXP (op0
, 0);
2950 op1
= XEXP (op1
, 0);
2953 *total
= COSTS_N_INSNS (1);
2955 *total
= COSTS_N_INSNS (3);
2957 if (GET_CODE (op0
) != REG
2958 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2959 *total
+= rtx_cost (op0
, MULT
, speed
);
2960 if (GET_CODE (op1
) != REG
2961 && (GET_CODE (op1
) != SUBREG
|| GET_CODE (SUBREG_REG (op1
)) != REG
))
2962 *total
+= rtx_cost (op1
, MULT
, speed
);
2968 *total
= COSTS_N_INSNS (32);
2973 if (outer_code
== SET
)
2982 /* Used for communication between {push,pop}_multiple_operation (which
2983 we use not only as a predicate) and the corresponding output functions. */
2984 static int first_preg_to_save
, first_dreg_to_save
;
2985 static int n_regs_to_save
;
2988 push_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2990 int lastdreg
= 8, lastpreg
= 6;
2993 first_preg_to_save
= lastpreg
;
2994 first_dreg_to_save
= lastdreg
;
2995 for (i
= 1, group
= 0; i
< XVECLEN (op
, 0) - 1; i
++)
2997 rtx t
= XVECEXP (op
, 0, i
);
3001 if (GET_CODE (t
) != SET
)
3005 dest
= SET_DEST (t
);
3006 if (GET_CODE (dest
) != MEM
|| ! REG_P (src
))
3008 dest
= XEXP (dest
, 0);
3009 if (GET_CODE (dest
) != PLUS
3010 || ! REG_P (XEXP (dest
, 0))
3011 || REGNO (XEXP (dest
, 0)) != REG_SP
3012 || GET_CODE (XEXP (dest
, 1)) != CONST_INT
3013 || INTVAL (XEXP (dest
, 1)) != -i
* 4)
3016 regno
= REGNO (src
);
3019 if (D_REGNO_P (regno
))
3022 first_dreg_to_save
= lastdreg
= regno
- REG_R0
;
3024 else if (regno
>= REG_P0
&& regno
<= REG_P7
)
3027 first_preg_to_save
= lastpreg
= regno
- REG_P0
;
3037 if (regno
>= REG_P0
&& regno
<= REG_P7
)
3040 first_preg_to_save
= lastpreg
= regno
- REG_P0
;
3042 else if (regno
!= REG_R0
+ lastdreg
+ 1)
3047 else if (group
== 2)
3049 if (regno
!= REG_P0
+ lastpreg
+ 1)
3054 n_regs_to_save
= 8 - first_dreg_to_save
+ 6 - first_preg_to_save
;
3059 pop_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3061 int lastdreg
= 8, lastpreg
= 6;
3064 for (i
= 1, group
= 0; i
< XVECLEN (op
, 0); i
++)
3066 rtx t
= XVECEXP (op
, 0, i
);
3070 if (GET_CODE (t
) != SET
)
3074 dest
= SET_DEST (t
);
3075 if (GET_CODE (src
) != MEM
|| ! REG_P (dest
))
3077 src
= XEXP (src
, 0);
3081 if (! REG_P (src
) || REGNO (src
) != REG_SP
)
3084 else if (GET_CODE (src
) != PLUS
3085 || ! REG_P (XEXP (src
, 0))
3086 || REGNO (XEXP (src
, 0)) != REG_SP
3087 || GET_CODE (XEXP (src
, 1)) != CONST_INT
3088 || INTVAL (XEXP (src
, 1)) != (i
- 1) * 4)
3091 regno
= REGNO (dest
);
3094 if (regno
== REG_R7
)
3099 else if (regno
!= REG_P0
+ lastpreg
- 1)
3104 else if (group
== 1)
3106 if (regno
!= REG_R0
+ lastdreg
- 1)
3112 first_dreg_to_save
= lastdreg
;
3113 first_preg_to_save
= lastpreg
;
3114 n_regs_to_save
= 8 - first_dreg_to_save
+ 6 - first_preg_to_save
;
3118 /* Emit assembly code for one multi-register push described by INSN, with
3119 operands in OPERANDS. */
3122 output_push_multiple (rtx insn
, rtx
*operands
)
3127 /* Validate the insn again, and compute first_[dp]reg_to_save. */
3128 ok
= push_multiple_operation (PATTERN (insn
), VOIDmode
);
3131 if (first_dreg_to_save
== 8)
3132 sprintf (buf
, "[--sp] = ( p5:%d );\n", first_preg_to_save
);
3133 else if (first_preg_to_save
== 6)
3134 sprintf (buf
, "[--sp] = ( r7:%d );\n", first_dreg_to_save
);
3136 sprintf (buf
, "[--sp] = ( r7:%d, p5:%d );\n",
3137 first_dreg_to_save
, first_preg_to_save
);
3139 output_asm_insn (buf
, operands
);
3142 /* Emit assembly code for one multi-register pop described by INSN, with
3143 operands in OPERANDS. */
3146 output_pop_multiple (rtx insn
, rtx
*operands
)
3151 /* Validate the insn again, and compute first_[dp]reg_to_save. */
3152 ok
= pop_multiple_operation (PATTERN (insn
), VOIDmode
);
3155 if (first_dreg_to_save
== 8)
3156 sprintf (buf
, "( p5:%d ) = [sp++];\n", first_preg_to_save
);
3157 else if (first_preg_to_save
== 6)
3158 sprintf (buf
, "( r7:%d ) = [sp++];\n", first_dreg_to_save
);
3160 sprintf (buf
, "( r7:%d, p5:%d ) = [sp++];\n",
3161 first_dreg_to_save
, first_preg_to_save
);
3163 output_asm_insn (buf
, operands
);
3166 /* Adjust DST and SRC by OFFSET bytes, and generate one move in mode MODE. */
3169 single_move_for_movmem (rtx dst
, rtx src
, enum machine_mode mode
, HOST_WIDE_INT offset
)
3171 rtx scratch
= gen_reg_rtx (mode
);
3174 srcmem
= adjust_address_nv (src
, mode
, offset
);
3175 dstmem
= adjust_address_nv (dst
, mode
, offset
);
3176 emit_move_insn (scratch
, srcmem
);
3177 emit_move_insn (dstmem
, scratch
);
3180 /* Expand a string move operation of COUNT_EXP bytes from SRC to DST, with
3181 alignment ALIGN_EXP. Return true if successful, false if we should fall
3182 back on a different method. */
3185 bfin_expand_movmem (rtx dst
, rtx src
, rtx count_exp
, rtx align_exp
)
3187 rtx srcreg
, destreg
, countreg
;
3188 HOST_WIDE_INT align
= 0;
3189 unsigned HOST_WIDE_INT count
= 0;
3191 if (GET_CODE (align_exp
) == CONST_INT
)
3192 align
= INTVAL (align_exp
);
3193 if (GET_CODE (count_exp
) == CONST_INT
)
3195 count
= INTVAL (count_exp
);
3197 if (!TARGET_INLINE_ALL_STRINGOPS
&& count
> 64)
3202 /* If optimizing for size, only do single copies inline. */
3205 if (count
== 2 && align
< 2)
3207 if (count
== 4 && align
< 4)
3209 if (count
!= 1 && count
!= 2 && count
!= 4)
3212 if (align
< 2 && count
!= 1)
3215 destreg
= copy_to_mode_reg (Pmode
, XEXP (dst
, 0));
3216 if (destreg
!= XEXP (dst
, 0))
3217 dst
= replace_equiv_address_nv (dst
, destreg
);
3218 srcreg
= copy_to_mode_reg (Pmode
, XEXP (src
, 0));
3219 if (srcreg
!= XEXP (src
, 0))
3220 src
= replace_equiv_address_nv (src
, srcreg
);
3222 if (count
!= 0 && align
>= 2)
3224 unsigned HOST_WIDE_INT offset
= 0;
3228 if ((count
& ~3) == 4)
3230 single_move_for_movmem (dst
, src
, SImode
, offset
);
3233 else if (count
& ~3)
3235 HOST_WIDE_INT new_count
= ((count
>> 2) & 0x3fffffff) - 1;
3236 countreg
= copy_to_mode_reg (Pmode
, GEN_INT (new_count
));
3238 emit_insn (gen_rep_movsi (destreg
, srcreg
, countreg
, destreg
, srcreg
));
3239 cfun
->machine
->has_loopreg_clobber
= true;
3243 single_move_for_movmem (dst
, src
, HImode
, offset
);
3249 if ((count
& ~1) == 2)
3251 single_move_for_movmem (dst
, src
, HImode
, offset
);
3254 else if (count
& ~1)
3256 HOST_WIDE_INT new_count
= ((count
>> 1) & 0x7fffffff) - 1;
3257 countreg
= copy_to_mode_reg (Pmode
, GEN_INT (new_count
));
3259 emit_insn (gen_rep_movhi (destreg
, srcreg
, countreg
, destreg
, srcreg
));
3260 cfun
->machine
->has_loopreg_clobber
= true;
3265 single_move_for_movmem (dst
, src
, QImode
, offset
);
3272 /* Compute the alignment for a local variable.
3273 TYPE is the data type, and ALIGN is the alignment that
3274 the object would ordinarily have. The value of this macro is used
3275 instead of that alignment to align the object. */
3278 bfin_local_alignment (tree type
, unsigned align
)
3280 /* Increasing alignment for (relatively) big types allows the builtin
3281 memcpy can use 32 bit loads/stores. */
3282 if (TYPE_SIZE (type
)
3283 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
3284 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) > 8
3285 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 32)
3290 /* Implement TARGET_SCHED_ISSUE_RATE. */
3293 bfin_issue_rate (void)
3299 bfin_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3301 enum attr_type dep_insn_type
;
3302 int dep_insn_code_number
;
3304 /* Anti and output dependencies have zero cost. */
3305 if (REG_NOTE_KIND (link
) != 0)
3308 dep_insn_code_number
= recog_memoized (dep_insn
);
3310 /* If we can't recognize the insns, we can't really do anything. */
3311 if (dep_insn_code_number
< 0 || recog_memoized (insn
) < 0)
3314 dep_insn_type
= get_attr_type (dep_insn
);
3316 if (dep_insn_type
== TYPE_MOVE
|| dep_insn_type
== TYPE_MCLD
)
3318 rtx pat
= PATTERN (dep_insn
);
3321 if (GET_CODE (pat
) == PARALLEL
)
3322 pat
= XVECEXP (pat
, 0, 0);
3323 dest
= SET_DEST (pat
);
3324 src
= SET_SRC (pat
);
3325 if (! ADDRESS_REGNO_P (REGNO (dest
))
3326 || ! (MEM_P (src
) || D_REGNO_P (REGNO (src
))))
3328 return cost
+ (dep_insn_type
== TYPE_MOVE
? 4 : 3);
3334 /* This function acts like NEXT_INSN, but is aware of three-insn bundles and
3335 skips all subsequent parallel instructions if INSN is the start of such
3338 find_next_insn_start (rtx insn
)
3340 if (GET_MODE (insn
) == SImode
)
3342 while (GET_MODE (insn
) != QImode
)
3343 insn
= NEXT_INSN (insn
);
3345 return NEXT_INSN (insn
);
3348 /* This function acts like PREV_INSN, but is aware of three-insn bundles and
3349 skips all subsequent parallel instructions if INSN is the start of such
3352 find_prev_insn_start (rtx insn
)
3354 insn
= PREV_INSN (insn
);
3355 gcc_assert (GET_MODE (insn
) != SImode
);
3356 if (GET_MODE (insn
) == QImode
)
3358 while (GET_MODE (PREV_INSN (insn
)) == SImode
)
3359 insn
= PREV_INSN (insn
);
3364 /* Increment the counter for the number of loop instructions in the
3365 current function. */
3368 bfin_hardware_loop (void)
3370 cfun
->machine
->has_hardware_loops
++;
3373 /* Maximum loop nesting depth. */
3374 #define MAX_LOOP_DEPTH 2
3376 /* Maximum size of a loop. */
3377 #define MAX_LOOP_LENGTH 2042
3379 /* Maximum distance of the LSETUP instruction from the loop start. */
3380 #define MAX_LSETUP_DISTANCE 30
3382 /* We need to keep a vector of loops */
3383 typedef struct loop_info_d
*loop_info
;
3384 DEF_VEC_P (loop_info
);
3385 DEF_VEC_ALLOC_P (loop_info
,heap
);
3387 /* Information about a loop we have found (or are in the process of
3389 struct GTY (()) loop_info_d
3391 /* loop number, for dumps */
3394 /* All edges that jump into and out of the loop. */
3395 VEC(edge
,gc
) *incoming
;
3397 /* We can handle two cases: all incoming edges have the same destination
3398 block, or all incoming edges have the same source block. These two
3399 members are set to the common source or destination we found, or NULL
3400 if different blocks were found. If both are NULL the loop can't be
3402 basic_block incoming_src
;
3403 basic_block incoming_dest
;
3405 /* First block in the loop. This is the one branched to by the loop_end
3409 /* Last block in the loop (the one with the loop_end insn). */
3412 /* The successor block of the loop. This is the one the loop_end insn
3414 basic_block successor
;
3416 /* The last instruction in the tail. */
3419 /* The loop_end insn. */
3422 /* The iteration register. */
3425 /* The new label placed at the beginning of the loop. */
3428 /* The new label placed at the end of the loop. */
3431 /* The length of the loop. */
3434 /* The nesting depth of the loop. */
3437 /* Nonzero if we can't optimize this loop. */
3440 /* True if we have visited this loop. */
3443 /* True if this loop body clobbers any of LC0, LT0, or LB0. */
3446 /* True if this loop body clobbers any of LC1, LT1, or LB1. */
3449 /* Next loop in the graph. */
3450 struct loop_info_d
*next
;
3452 /* Immediate outer loop of this loop. */
3453 struct loop_info_d
*outer
;
3455 /* Vector of blocks only within the loop, including those within
3457 VEC (basic_block
,heap
) *blocks
;
3459 /* Same information in a bitmap. */
3460 bitmap block_bitmap
;
3462 /* Vector of inner loops within this loop */
3463 VEC (loop_info
,heap
) *loops
;
3467 bfin_dump_loops (loop_info loops
)
3471 for (loop
= loops
; loop
; loop
= loop
->next
)
3477 fprintf (dump_file
, ";; loop %d: ", loop
->loop_no
);
3479 fprintf (dump_file
, "(bad) ");
3480 fprintf (dump_file
, "{head:%d, depth:%d}", loop
->head
->index
, loop
->depth
);
3482 fprintf (dump_file
, " blocks: [ ");
3483 FOR_EACH_VEC_ELT (basic_block
, loop
->blocks
, ix
, b
)
3484 fprintf (dump_file
, "%d ", b
->index
);
3485 fprintf (dump_file
, "] ");
3487 fprintf (dump_file
, " inner loops: [ ");
3488 FOR_EACH_VEC_ELT (loop_info
, loop
->loops
, ix
, i
)
3489 fprintf (dump_file
, "%d ", i
->loop_no
);
3490 fprintf (dump_file
, "]\n");
3492 fprintf (dump_file
, "\n");
3495 /* Scan the blocks of LOOP (and its inferiors) looking for basic block
3496 BB. Return true, if we find it. */
3499 bfin_bb_in_loop (loop_info loop
, basic_block bb
)
3501 return bitmap_bit_p (loop
->block_bitmap
, bb
->index
);
3504 /* Scan the blocks of LOOP (and its inferiors) looking for uses of
3505 REG. Return true, if we find any. Don't count the loop's loop_end
3506 insn if it matches LOOP_END. */
3509 bfin_scan_loop (loop_info loop
, rtx reg
, rtx loop_end
)
3514 FOR_EACH_VEC_ELT (basic_block
, loop
->blocks
, ix
, bb
)
3518 for (insn
= BB_HEAD (bb
);
3519 insn
!= NEXT_INSN (BB_END (bb
));
3520 insn
= NEXT_INSN (insn
))
3524 if (insn
== loop_end
)
3526 if (reg_mentioned_p (reg
, PATTERN (insn
)))
3533 /* Estimate the length of INSN conservatively. */
3536 length_for_loop (rtx insn
)
3539 if (JUMP_P (insn
) && any_condjump_p (insn
) && !optimize_size
)
3541 if (ENABLE_WA_SPECULATIVE_SYNCS
)
3543 else if (ENABLE_WA_SPECULATIVE_LOADS
)
3546 else if (LABEL_P (insn
))
3548 if (ENABLE_WA_SPECULATIVE_SYNCS
)
3552 if (NONDEBUG_INSN_P (insn
))
3553 length
+= get_attr_length (insn
);
3558 /* Optimize LOOP. */
3561 bfin_optimize_loop (loop_info loop
)
3565 rtx insn
, last_insn
;
3566 rtx loop_init
, start_label
, end_label
;
3567 rtx reg_lc0
, reg_lc1
, reg_lt0
, reg_lt1
, reg_lb0
, reg_lb1
;
3568 rtx iter_reg
, scratchreg
, scratch_init
, scratch_init_insn
;
3569 rtx lc_reg
, lt_reg
, lb_reg
;
3573 int inner_depth
= 0;
3583 fprintf (dump_file
, ";; loop %d bad when found\n", loop
->loop_no
);
3587 /* Every loop contains in its list of inner loops every loop nested inside
3588 it, even if there are intermediate loops. This works because we're doing
3589 a depth-first search here and never visit a loop more than once. */
3590 FOR_EACH_VEC_ELT (loop_info
, loop
->loops
, ix
, inner
)
3592 bfin_optimize_loop (inner
);
3594 if (!inner
->bad
&& inner_depth
< inner
->depth
)
3596 inner_depth
= inner
->depth
;
3598 loop
->clobber_loop0
|= inner
->clobber_loop0
;
3599 loop
->clobber_loop1
|= inner
->clobber_loop1
;
3603 loop
->depth
= inner_depth
+ 1;
3604 if (loop
->depth
> MAX_LOOP_DEPTH
)
3607 fprintf (dump_file
, ";; loop %d too deep\n", loop
->loop_no
);
3611 /* Get the loop iteration register. */
3612 iter_reg
= loop
->iter_reg
;
3614 if (!REG_P (iter_reg
))
3617 fprintf (dump_file
, ";; loop %d iteration count not in a register\n",
3621 scratchreg
= NULL_RTX
;
3622 scratch_init
= iter_reg
;
3623 scratch_init_insn
= NULL_RTX
;
3624 if (!PREG_P (iter_reg
) && loop
->incoming_src
)
3626 basic_block bb_in
= loop
->incoming_src
;
3628 for (i
= REG_P0
; i
<= REG_P5
; i
++)
3629 if ((df_regs_ever_live_p (i
)
3630 || (funkind (TREE_TYPE (current_function_decl
)) == SUBROUTINE
3631 && call_used_regs
[i
]))
3632 && !REGNO_REG_SET_P (df_get_live_out (bb_in
), i
))
3634 scratchreg
= gen_rtx_REG (SImode
, i
);
3637 for (insn
= BB_END (bb_in
); insn
!= BB_HEAD (bb_in
);
3638 insn
= PREV_INSN (insn
))
3641 if (NOTE_P (insn
) || BARRIER_P (insn
))
3643 set
= single_set (insn
);
3644 if (set
&& rtx_equal_p (SET_DEST (set
), iter_reg
))
3646 if (CONSTANT_P (SET_SRC (set
)))
3648 scratch_init
= SET_SRC (set
);
3649 scratch_init_insn
= insn
;
3653 else if (reg_mentioned_p (iter_reg
, PATTERN (insn
)))
3658 if (loop
->incoming_src
)
3660 /* Make sure the predecessor is before the loop start label, as required by
3661 the LSETUP instruction. */
3663 insn
= BB_END (loop
->incoming_src
);
3664 /* If we have to insert the LSETUP before a jump, count that jump in the
3666 if (VEC_length (edge
, loop
->incoming
) > 1
3667 || !(VEC_last (edge
, loop
->incoming
)->flags
& EDGE_FALLTHRU
))
3669 gcc_assert (JUMP_P (insn
));
3670 insn
= PREV_INSN (insn
);
3673 for (; insn
&& insn
!= loop
->start_label
; insn
= NEXT_INSN (insn
))
3674 length
+= length_for_loop (insn
);
3679 fprintf (dump_file
, ";; loop %d lsetup not before loop_start\n",
3684 /* Account for the pop of a scratch register where necessary. */
3685 if (!PREG_P (iter_reg
) && scratchreg
== NULL_RTX
3686 && ENABLE_WA_LOAD_LCREGS
)
3689 if (length
> MAX_LSETUP_DISTANCE
)
3692 fprintf (dump_file
, ";; loop %d lsetup too far away\n", loop
->loop_no
);
3697 /* Check if start_label appears before loop_end and calculate the
3698 offset between them. We calculate the length of instructions
3701 for (insn
= loop
->start_label
;
3702 insn
&& insn
!= loop
->loop_end
;
3703 insn
= NEXT_INSN (insn
))
3704 length
+= length_for_loop (insn
);
3709 fprintf (dump_file
, ";; loop %d start_label not before loop_end\n",
3714 loop
->length
= length
;
3715 if (loop
->length
> MAX_LOOP_LENGTH
)
3718 fprintf (dump_file
, ";; loop %d too long\n", loop
->loop_no
);
3722 /* Scan all the blocks to make sure they don't use iter_reg. */
3723 if (bfin_scan_loop (loop
, iter_reg
, loop
->loop_end
))
3726 fprintf (dump_file
, ";; loop %d uses iterator\n", loop
->loop_no
);
3730 /* Scan all the insns to see if the loop body clobber
3731 any hardware loop registers. */
3733 reg_lc0
= gen_rtx_REG (SImode
, REG_LC0
);
3734 reg_lc1
= gen_rtx_REG (SImode
, REG_LC1
);
3735 reg_lt0
= gen_rtx_REG (SImode
, REG_LT0
);
3736 reg_lt1
= gen_rtx_REG (SImode
, REG_LT1
);
3737 reg_lb0
= gen_rtx_REG (SImode
, REG_LB0
);
3738 reg_lb1
= gen_rtx_REG (SImode
, REG_LB1
);
3740 FOR_EACH_VEC_ELT (basic_block
, loop
->blocks
, ix
, bb
)
3744 for (insn
= BB_HEAD (bb
);
3745 insn
!= NEXT_INSN (BB_END (bb
));
3746 insn
= NEXT_INSN (insn
))
3751 if (reg_set_p (reg_lc0
, insn
)
3752 || reg_set_p (reg_lt0
, insn
)
3753 || reg_set_p (reg_lb0
, insn
))
3754 loop
->clobber_loop0
= 1;
3756 if (reg_set_p (reg_lc1
, insn
)
3757 || reg_set_p (reg_lt1
, insn
)
3758 || reg_set_p (reg_lb1
, insn
))
3759 loop
->clobber_loop1
|= 1;
3763 if ((loop
->clobber_loop0
&& loop
->clobber_loop1
)
3764 || (loop
->depth
== MAX_LOOP_DEPTH
&& loop
->clobber_loop0
))
3766 loop
->depth
= MAX_LOOP_DEPTH
+ 1;
3768 fprintf (dump_file
, ";; loop %d no loop reg available\n",
3773 /* There should be an instruction before the loop_end instruction
3774 in the same basic block. And the instruction must not be
3776 - CONDITIONAL BRANCH
3780 - Returns (RTS, RTN, etc.) */
3783 last_insn
= find_prev_insn_start (loop
->loop_end
);
3787 for (; last_insn
!= BB_HEAD (bb
);
3788 last_insn
= find_prev_insn_start (last_insn
))
3789 if (NONDEBUG_INSN_P (last_insn
))
3792 if (last_insn
!= BB_HEAD (bb
))
3795 if (single_pred_p (bb
)
3796 && single_pred_edge (bb
)->flags
& EDGE_FALLTHRU
3797 && single_pred (bb
) != ENTRY_BLOCK_PTR
)
3799 bb
= single_pred (bb
);
3800 last_insn
= BB_END (bb
);
3805 last_insn
= NULL_RTX
;
3813 fprintf (dump_file
, ";; loop %d has no last instruction\n",
3818 if (JUMP_P (last_insn
) && !any_condjump_p (last_insn
))
3821 fprintf (dump_file
, ";; loop %d has bad last instruction\n",
3825 /* In all other cases, try to replace a bad last insn with a nop. */
3826 else if (JUMP_P (last_insn
)
3827 || CALL_P (last_insn
)
3828 || get_attr_type (last_insn
) == TYPE_SYNC
3829 || get_attr_type (last_insn
) == TYPE_CALL
3830 || get_attr_seq_insns (last_insn
) == SEQ_INSNS_MULTI
3831 || recog_memoized (last_insn
) == CODE_FOR_return_internal
3832 || GET_CODE (PATTERN (last_insn
)) == ASM_INPUT
3833 || asm_noperands (PATTERN (last_insn
)) >= 0)
3835 if (loop
->length
+ 2 > MAX_LOOP_LENGTH
)
3838 fprintf (dump_file
, ";; loop %d too long\n", loop
->loop_no
);
3842 fprintf (dump_file
, ";; loop %d has bad last insn; replace with nop\n",
3845 last_insn
= emit_insn_after (gen_forced_nop (), last_insn
);
3848 loop
->last_insn
= last_insn
;
3850 /* The loop is good for replacement. */
3851 start_label
= loop
->start_label
;
3852 end_label
= gen_label_rtx ();
3853 iter_reg
= loop
->iter_reg
;
3855 if (loop
->depth
== 1 && !loop
->clobber_loop1
)
3860 loop
->clobber_loop1
= 1;
3867 loop
->clobber_loop0
= 1;
3870 loop
->end_label
= end_label
;
3872 /* Create a sequence containing the loop setup. */
3875 /* LSETUP only accepts P registers. If we have one, we can use it,
3876 otherwise there are several ways of working around the problem.
3877 If we're not affected by anomaly 312, we can load the LC register
3878 from any iteration register, and use LSETUP without initialization.
3879 If we've found a P scratch register that's not live here, we can
3880 instead copy the iter_reg into that and use an initializing LSETUP.
3881 If all else fails, push and pop P0 and use it as a scratch. */
3882 if (P_REGNO_P (REGNO (iter_reg
)))
3884 loop_init
= gen_lsetup_with_autoinit (lt_reg
, start_label
,
3887 seq_end
= emit_insn (loop_init
);
3889 else if (!ENABLE_WA_LOAD_LCREGS
&& DPREG_P (iter_reg
))
3891 emit_insn (gen_movsi (lc_reg
, iter_reg
));
3892 loop_init
= gen_lsetup_without_autoinit (lt_reg
, start_label
,
3895 seq_end
= emit_insn (loop_init
);
3897 else if (scratchreg
!= NULL_RTX
)
3899 emit_insn (gen_movsi (scratchreg
, scratch_init
));
3900 loop_init
= gen_lsetup_with_autoinit (lt_reg
, start_label
,
3902 lc_reg
, scratchreg
);
3903 seq_end
= emit_insn (loop_init
);
3904 if (scratch_init_insn
!= NULL_RTX
)
3905 delete_insn (scratch_init_insn
);
3909 rtx p0reg
= gen_rtx_REG (SImode
, REG_P0
);
3910 rtx push
= gen_frame_mem (SImode
,
3911 gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
));
3912 rtx pop
= gen_frame_mem (SImode
,
3913 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3914 emit_insn (gen_movsi (push
, p0reg
));
3915 emit_insn (gen_movsi (p0reg
, scratch_init
));
3916 loop_init
= gen_lsetup_with_autoinit (lt_reg
, start_label
,
3919 emit_insn (loop_init
);
3920 seq_end
= emit_insn (gen_movsi (p0reg
, pop
));
3921 if (scratch_init_insn
!= NULL_RTX
)
3922 delete_insn (scratch_init_insn
);
3927 fprintf (dump_file
, ";; replacing loop %d initializer with\n",
3929 print_rtl_single (dump_file
, loop_init
);
3930 fprintf (dump_file
, ";; replacing loop %d terminator with\n",
3932 print_rtl_single (dump_file
, loop
->loop_end
);
3935 /* If the loop isn't entered at the top, also create a jump to the entry
3937 if (!loop
->incoming_src
&& loop
->head
!= loop
->incoming_dest
)
3939 rtx label
= BB_HEAD (loop
->incoming_dest
);
3940 /* If we're jumping to the final basic block in the loop, and there's
3941 only one cheap instruction before the end (typically an increment of
3942 an induction variable), we can just emit a copy here instead of a
3944 if (loop
->incoming_dest
== loop
->tail
3945 && next_real_insn (label
) == last_insn
3946 && asm_noperands (last_insn
) < 0
3947 && GET_CODE (PATTERN (last_insn
)) == SET
)
3949 seq_end
= emit_insn (copy_rtx (PATTERN (last_insn
)));
3953 emit_jump_insn (gen_jump (label
));
3954 seq_end
= emit_barrier ();
3961 if (loop
->incoming_src
)
3963 rtx prev
= BB_END (loop
->incoming_src
);
3964 if (VEC_length (edge
, loop
->incoming
) > 1
3965 || !(VEC_last (edge
, loop
->incoming
)->flags
& EDGE_FALLTHRU
))
3967 gcc_assert (JUMP_P (prev
));
3968 prev
= PREV_INSN (prev
);
3970 emit_insn_after (seq
, prev
);
3978 #ifdef ENABLE_CHECKING
3979 if (loop
->head
!= loop
->incoming_dest
)
3981 /* We aren't entering the loop at the top. Since we've established
3982 that the loop is entered only at one point, this means there
3983 can't be fallthru edges into the head. Any such fallthru edges
3984 would become invalid when we insert the new block, so verify
3985 that this does not in fact happen. */
3986 FOR_EACH_EDGE (e
, ei
, loop
->head
->preds
)
3987 gcc_assert (!(e
->flags
& EDGE_FALLTHRU
));
3991 emit_insn_before (seq
, BB_HEAD (loop
->head
));
3992 seq
= emit_label_before (gen_label_rtx (), seq
);
3994 new_bb
= create_basic_block (seq
, seq_end
, loop
->head
->prev_bb
);
3995 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
3997 if (!(e
->flags
& EDGE_FALLTHRU
)
3998 || e
->dest
!= loop
->head
)
3999 redirect_edge_and_branch_force (e
, new_bb
);
4001 redirect_edge_succ (e
, new_bb
);
4003 e
= make_edge (new_bb
, loop
->head
, 0);
4006 delete_insn (loop
->loop_end
);
4007 /* Insert the loop end label before the last instruction of the loop. */
4008 emit_label_before (loop
->end_label
, loop
->last_insn
);
4015 fprintf (dump_file
, ";; loop %d is bad\n", loop
->loop_no
);
4019 if (DPREG_P (loop
->iter_reg
))
4021 /* If loop->iter_reg is a DREG or PREG, we can split it here
4022 without scratch register. */
4025 emit_insn_before (gen_addsi3 (loop
->iter_reg
,
4030 test
= gen_rtx_NE (VOIDmode
, loop
->iter_reg
, const0_rtx
);
4031 insn
= emit_jump_insn_before (gen_cbranchsi4 (test
,
4032 loop
->iter_reg
, const0_rtx
,
4036 JUMP_LABEL (insn
) = loop
->start_label
;
4037 LABEL_NUSES (loop
->start_label
)++;
4038 delete_insn (loop
->loop_end
);
4042 /* Called from bfin_reorg_loops when a potential loop end is found. LOOP is
4043 a newly set up structure describing the loop, it is this function's
4044 responsibility to fill most of it. TAIL_BB and TAIL_INSN point to the
4045 loop_end insn and its enclosing basic block. */
4048 bfin_discover_loop (loop_info loop
, basic_block tail_bb
, rtx tail_insn
)
4052 VEC (basic_block
,heap
) *works
= VEC_alloc (basic_block
,heap
,20);
4054 loop
->tail
= tail_bb
;
4055 loop
->head
= BRANCH_EDGE (tail_bb
)->dest
;
4056 loop
->successor
= FALLTHRU_EDGE (tail_bb
)->dest
;
4057 loop
->loop_end
= tail_insn
;
4058 loop
->last_insn
= NULL_RTX
;
4059 loop
->iter_reg
= SET_DEST (XVECEXP (PATTERN (tail_insn
), 0, 1));
4060 loop
->depth
= loop
->length
= 0;
4062 loop
->clobber_loop0
= loop
->clobber_loop1
= 0;
4065 loop
->incoming
= VEC_alloc (edge
, gc
, 2);
4066 loop
->start_label
= XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (tail_insn
), 0, 0)), 1), 0);
4067 loop
->end_label
= NULL_RTX
;
4070 VEC_safe_push (basic_block
, heap
, works
, loop
->head
);
4072 while (VEC_iterate (basic_block
, works
, dwork
++, bb
))
4076 if (bb
== EXIT_BLOCK_PTR
)
4078 /* We've reached the exit block. The loop must be bad. */
4081 ";; Loop is bad - reached exit block while scanning\n");
4086 if (!bitmap_set_bit (loop
->block_bitmap
, bb
->index
))
4089 /* We've not seen this block before. Add it to the loop's
4090 list and then add each successor to the work list. */
4092 VEC_safe_push (basic_block
, heap
, loop
->blocks
, bb
);
4096 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
4098 basic_block succ
= EDGE_SUCC (bb
, ei
.index
)->dest
;
4099 if (!REGNO_REG_SET_P (df_get_live_in (succ
),
4100 REGNO (loop
->iter_reg
)))
4102 if (!VEC_space (basic_block
, works
, 1))
4106 VEC_block_remove (basic_block
, works
, 0, dwork
);
4110 VEC_reserve (basic_block
, heap
, works
, 1);
4112 VEC_quick_push (basic_block
, works
, succ
);
4117 /* Find the predecessor, and make sure nothing else jumps into this loop. */
4121 FOR_EACH_VEC_ELT (basic_block
, loop
->blocks
, dwork
, bb
)
4125 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
4127 basic_block pred
= e
->src
;
4129 if (!bfin_bb_in_loop (loop
, pred
))
4132 fprintf (dump_file
, ";; Loop %d: incoming edge %d -> %d\n",
4133 loop
->loop_no
, pred
->index
,
4135 VEC_safe_push (edge
, gc
, loop
->incoming
, e
);
4140 for (pass
= 0, retry
= 1; retry
&& pass
< 2; pass
++)
4147 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
4151 loop
->incoming_src
= e
->src
;
4152 loop
->incoming_dest
= e
->dest
;
4157 if (e
->dest
!= loop
->incoming_dest
)
4158 loop
->incoming_dest
= NULL
;
4159 if (e
->src
!= loop
->incoming_src
)
4160 loop
->incoming_src
= NULL
;
4162 if (loop
->incoming_src
== NULL
&& loop
->incoming_dest
== NULL
)
4168 ";; retrying loop %d with forwarder blocks\n",
4176 ";; can't find suitable entry for loop %d\n",
4184 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
4186 if (forwarder_block_p (e
->src
))
4193 ";; Adding forwarder block %d to loop %d and retrying\n",
4194 e
->src
->index
, loop
->loop_no
);
4195 VEC_safe_push (basic_block
, heap
, loop
->blocks
, e
->src
);
4196 bitmap_set_bit (loop
->block_bitmap
, e
->src
->index
);
4197 FOR_EACH_EDGE (e2
, ei2
, e
->src
->preds
)
4198 VEC_safe_push (edge
, gc
, loop
->incoming
, e2
);
4199 VEC_unordered_remove (edge
, loop
->incoming
, ei
.index
);
4207 fprintf (dump_file
, ";; No forwarder blocks found\n");
4215 VEC_free (basic_block
, heap
, works
);
4218 /* Analyze the structure of the loops in the current function. Use STACK
4219 for bitmap allocations. Returns all the valid candidates for hardware
4220 loops found in this function. */
4222 bfin_discover_loops (bitmap_obstack
*stack
, FILE *dump_file
)
4224 loop_info loops
= NULL
;
4230 /* Find all the possible loop tails. This means searching for every
4231 loop_end instruction. For each one found, create a loop_info
4232 structure and add the head block to the work list. */
4235 rtx tail
= BB_END (bb
);
4237 while (GET_CODE (tail
) == NOTE
)
4238 tail
= PREV_INSN (tail
);
4242 if (INSN_P (tail
) && recog_memoized (tail
) == CODE_FOR_loop_end
)
4245 /* A possible loop end */
4247 /* There's a degenerate case we can handle - an empty loop consisting
4248 of only a back branch. Handle that by deleting the branch. */
4249 insn
= BB_HEAD (BRANCH_EDGE (bb
)->dest
);
4250 if (next_real_insn (insn
) == tail
)
4254 fprintf (dump_file
, ";; degenerate loop ending at\n");
4255 print_rtl_single (dump_file
, tail
);
4257 delete_insn_and_edges (tail
);
4261 loop
= XNEW (struct loop_info_d
);
4264 loop
->loop_no
= nloops
++;
4265 loop
->blocks
= VEC_alloc (basic_block
, heap
, 20);
4266 loop
->block_bitmap
= BITMAP_ALLOC (stack
);
4271 fprintf (dump_file
, ";; potential loop %d ending at\n",
4273 print_rtl_single (dump_file
, tail
);
4276 bfin_discover_loop (loop
, bb
, tail
);
4280 tmp_bitmap
= BITMAP_ALLOC (stack
);
4281 /* Compute loop nestings. */
4282 for (loop
= loops
; loop
; loop
= loop
->next
)
4288 for (other
= loop
->next
; other
; other
= other
->next
)
4293 bitmap_and (tmp_bitmap
, other
->block_bitmap
, loop
->block_bitmap
);
4294 if (bitmap_empty_p (tmp_bitmap
))
4296 if (bitmap_equal_p (tmp_bitmap
, other
->block_bitmap
))
4298 other
->outer
= loop
;
4299 VEC_safe_push (loop_info
, heap
, loop
->loops
, other
);
4301 else if (bitmap_equal_p (tmp_bitmap
, loop
->block_bitmap
))
4303 loop
->outer
= other
;
4304 VEC_safe_push (loop_info
, heap
, other
->loops
, loop
);
4310 ";; can't find suitable nesting for loops %d and %d\n",
4311 loop
->loop_no
, other
->loop_no
);
4312 loop
->bad
= other
->bad
= 1;
4316 BITMAP_FREE (tmp_bitmap
);
4321 /* Free up the loop structures in LOOPS. */
4323 free_loops (loop_info loops
)
4327 loop_info loop
= loops
;
4329 VEC_free (loop_info
, heap
, loop
->loops
);
4330 VEC_free (basic_block
, heap
, loop
->blocks
);
4331 BITMAP_FREE (loop
->block_bitmap
);
4336 #define BB_AUX_INDEX(BB) ((intptr_t)(BB)->aux)
4338 /* The taken-branch edge from the loop end can actually go forward. Since the
4339 Blackfin's LSETUP instruction requires that the loop end be after the loop
4340 start, try to reorder a loop's basic blocks when we find such a case. */
4342 bfin_reorder_loops (loop_info loops
, FILE *dump_file
)
4349 cfg_layout_initialize (0);
4351 for (loop
= loops
; loop
; loop
= loop
->next
)
4361 /* Recreate an index for basic blocks that represents their order. */
4362 for (bb
= ENTRY_BLOCK_PTR
->next_bb
, index
= 0;
4363 bb
!= EXIT_BLOCK_PTR
;
4364 bb
= bb
->next_bb
, index
++)
4365 bb
->aux
= (PTR
) index
;
4367 if (BB_AUX_INDEX (loop
->head
) < BB_AUX_INDEX (loop
->tail
))
4370 FOR_EACH_EDGE (e
, ei
, loop
->head
->succs
)
4372 if (bitmap_bit_p (loop
->block_bitmap
, e
->dest
->index
)
4373 && BB_AUX_INDEX (e
->dest
) < BB_AUX_INDEX (loop
->tail
))
4375 basic_block start_bb
= e
->dest
;
4376 basic_block start_prev_bb
= start_bb
->prev_bb
;
4379 fprintf (dump_file
, ";; Moving block %d before block %d\n",
4380 loop
->head
->index
, start_bb
->index
);
4381 loop
->head
->prev_bb
->next_bb
= loop
->head
->next_bb
;
4382 loop
->head
->next_bb
->prev_bb
= loop
->head
->prev_bb
;
4384 loop
->head
->prev_bb
= start_prev_bb
;
4385 loop
->head
->next_bb
= start_bb
;
4386 start_prev_bb
->next_bb
= start_bb
->prev_bb
= loop
->head
;
4390 loops
= loops
->next
;
4395 if (bb
->next_bb
!= EXIT_BLOCK_PTR
)
4396 bb
->aux
= bb
->next_bb
;
4400 cfg_layout_finalize ();
4404 /* Run from machine_dependent_reorg, this pass looks for doloop_end insns
4405 and tries to rewrite the RTL of these loops so that proper Blackfin
4406 hardware loops are generated. */
4409 bfin_reorg_loops (FILE *dump_file
)
4411 loop_info loops
= NULL
;
4414 bitmap_obstack stack
;
4416 bitmap_obstack_initialize (&stack
);
4419 fprintf (dump_file
, ";; Find loops, first pass\n\n");
4421 loops
= bfin_discover_loops (&stack
, dump_file
);
4424 bfin_dump_loops (loops
);
4426 bfin_reorder_loops (loops
, dump_file
);
4430 fprintf (dump_file
, ";; Find loops, second pass\n\n");
4432 loops
= bfin_discover_loops (&stack
, dump_file
);
4435 fprintf (dump_file
, ";; All loops found:\n\n");
4436 bfin_dump_loops (loops
);
4439 /* Now apply the optimizations. */
4440 for (loop
= loops
; loop
; loop
= loop
->next
)
4441 bfin_optimize_loop (loop
);
4445 fprintf (dump_file
, ";; After hardware loops optimization:\n\n");
4446 bfin_dump_loops (loops
);
4452 print_rtl (dump_file
, get_insns ());
4457 splitting_loops
= 1;
4460 rtx insn
= BB_END (bb
);
4464 try_split (PATTERN (insn
), insn
, 1);
4466 splitting_loops
= 0;
4469 /* Possibly generate a SEQUENCE out of three insns found in SLOT.
4470 Returns true if we modified the insn chain, false otherwise. */
4472 gen_one_bundle (rtx slot
[3])
4474 gcc_assert (slot
[1] != NULL_RTX
);
4476 /* Don't add extra NOPs if optimizing for size. */
4478 && (slot
[0] == NULL_RTX
|| slot
[2] == NULL_RTX
))
4481 /* Verify that we really can do the multi-issue. */
4484 rtx t
= NEXT_INSN (slot
[0]);
4485 while (t
!= slot
[1])
4487 if (GET_CODE (t
) != NOTE
4488 || NOTE_KIND (t
) != NOTE_INSN_DELETED
)
4495 rtx t
= NEXT_INSN (slot
[1]);
4496 while (t
!= slot
[2])
4498 if (GET_CODE (t
) != NOTE
4499 || NOTE_KIND (t
) != NOTE_INSN_DELETED
)
4505 if (slot
[0] == NULL_RTX
)
4507 slot
[0] = emit_insn_before (gen_mnop (), slot
[1]);
4508 df_insn_rescan (slot
[0]);
4510 if (slot
[2] == NULL_RTX
)
4512 slot
[2] = emit_insn_after (gen_forced_nop (), slot
[1]);
4513 df_insn_rescan (slot
[2]);
4516 /* Avoid line number information being printed inside one bundle. */
4517 if (INSN_LOCATOR (slot
[1])
4518 && INSN_LOCATOR (slot
[1]) != INSN_LOCATOR (slot
[0]))
4519 INSN_LOCATOR (slot
[1]) = INSN_LOCATOR (slot
[0]);
4520 if (INSN_LOCATOR (slot
[2])
4521 && INSN_LOCATOR (slot
[2]) != INSN_LOCATOR (slot
[0]))
4522 INSN_LOCATOR (slot
[2]) = INSN_LOCATOR (slot
[0]);
4524 /* Terminate them with "|| " instead of ";" in the output. */
4525 PUT_MODE (slot
[0], SImode
);
4526 PUT_MODE (slot
[1], SImode
);
4527 /* Terminate the bundle, for the benefit of reorder_var_tracking_notes. */
4528 PUT_MODE (slot
[2], QImode
);
4532 /* Go through all insns, and use the information generated during scheduling
4533 to generate SEQUENCEs to represent bundles of instructions issued
4537 bfin_gen_bundles (void)
4546 slot
[0] = slot
[1] = slot
[2] = NULL_RTX
;
4547 for (insn
= BB_HEAD (bb
);; insn
= next
)
4550 rtx delete_this
= NULL_RTX
;
4552 if (NONDEBUG_INSN_P (insn
))
4554 enum attr_type type
= get_attr_type (insn
);
4556 if (type
== TYPE_STALL
)
4558 gcc_assert (n_filled
== 0);
4563 if (type
== TYPE_DSP32
|| type
== TYPE_DSP32SHIFTIMM
)
4565 else if (slot
[1] == NULL_RTX
)
4573 next
= NEXT_INSN (insn
);
4574 while (next
&& insn
!= BB_END (bb
)
4576 && GET_CODE (PATTERN (next
)) != USE
4577 && GET_CODE (PATTERN (next
)) != CLOBBER
))
4580 next
= NEXT_INSN (insn
);
4583 /* BB_END can change due to emitting extra NOPs, so check here. */
4584 at_end
= insn
== BB_END (bb
);
4585 if (delete_this
== NULL_RTX
&& (at_end
|| GET_MODE (next
) == TImode
))
4588 || !gen_one_bundle (slot
))
4589 && slot
[0] != NULL_RTX
)
4591 rtx pat
= PATTERN (slot
[0]);
4592 if (GET_CODE (pat
) == SET
4593 && GET_CODE (SET_SRC (pat
)) == UNSPEC
4594 && XINT (SET_SRC (pat
), 1) == UNSPEC_32BIT
)
4596 SET_SRC (pat
) = XVECEXP (SET_SRC (pat
), 0, 0);
4597 INSN_CODE (slot
[0]) = -1;
4598 df_insn_rescan (slot
[0]);
4602 slot
[0] = slot
[1] = slot
[2] = NULL_RTX
;
4604 if (delete_this
!= NULL_RTX
)
4605 delete_insn (delete_this
);
4612 /* Ensure that no var tracking notes are emitted in the middle of a
4613 three-instruction bundle. */
4616 reorder_var_tracking_notes (void)
4622 rtx queue
= NULL_RTX
;
4623 bool in_bundle
= false;
4625 for (insn
= BB_HEAD (bb
); insn
!= BB_END (bb
); insn
= next
)
4627 next
= NEXT_INSN (insn
);
4631 /* Emit queued up notes at the last instruction of a bundle. */
4632 if (GET_MODE (insn
) == QImode
)
4636 rtx next_queue
= PREV_INSN (queue
);
4637 PREV_INSN (NEXT_INSN (insn
)) = queue
;
4638 NEXT_INSN (queue
) = NEXT_INSN (insn
);
4639 NEXT_INSN (insn
) = queue
;
4640 PREV_INSN (queue
) = insn
;
4645 else if (GET_MODE (insn
) == SImode
)
4648 else if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_VAR_LOCATION
)
4652 rtx prev
= PREV_INSN (insn
);
4653 PREV_INSN (next
) = prev
;
4654 NEXT_INSN (prev
) = next
;
4656 PREV_INSN (insn
) = queue
;
4664 /* On some silicon revisions, functions shorter than a certain number of cycles
4665 can cause unpredictable behaviour. Work around this by adding NOPs as
4668 workaround_rts_anomaly (void)
4670 rtx insn
, first_insn
= NULL_RTX
;
4673 if (! ENABLE_WA_RETS
)
4676 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4680 if (BARRIER_P (insn
))
4683 if (NOTE_P (insn
) || LABEL_P (insn
))
4686 if (first_insn
== NULL_RTX
)
4688 pat
= PATTERN (insn
);
4689 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
4690 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
4691 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
4699 if (recog_memoized (insn
) == CODE_FOR_return_internal
)
4702 /* Nothing to worry about for direct jumps. */
4703 if (!any_condjump_p (insn
))
4709 else if (INSN_P (insn
))
4711 rtx pat
= PATTERN (insn
);
4712 int this_cycles
= 1;
4714 if (GET_CODE (pat
) == PARALLEL
)
4716 if (push_multiple_operation (pat
, VOIDmode
)
4717 || pop_multiple_operation (pat
, VOIDmode
))
4718 this_cycles
= n_regs_to_save
;
4722 int icode
= recog_memoized (insn
);
4724 if (icode
== CODE_FOR_link
)
4726 else if (icode
== CODE_FOR_unlink
)
4728 else if (icode
== CODE_FOR_mulsi3
)
4731 if (this_cycles
>= cycles
)
4734 cycles
-= this_cycles
;
4739 emit_insn_before (gen_nop (), first_insn
);
4744 /* Return an insn type for INSN that can be used by the caller for anomaly
4745 workarounds. This differs from plain get_attr_type in that it handles
4748 static enum attr_type
4749 type_for_anomaly (rtx insn
)
4751 rtx pat
= PATTERN (insn
);
4752 if (GET_CODE (pat
) == SEQUENCE
)
4755 t
= get_attr_type (XVECEXP (pat
, 0, 1));
4758 t
= get_attr_type (XVECEXP (pat
, 0, 2));
4764 return get_attr_type (insn
);
4767 /* Return true iff the address found in MEM is based on the register
4768 NP_REG and optionally has a positive offset. */
4770 harmless_null_pointer_p (rtx mem
, int np_reg
)
4772 mem
= XEXP (mem
, 0);
4773 if (GET_CODE (mem
) == POST_INC
|| GET_CODE (mem
) == POST_DEC
)
4774 mem
= XEXP (mem
, 0);
4775 if (REG_P (mem
) && (int) REGNO (mem
) == np_reg
)
4777 if (GET_CODE (mem
) == PLUS
4778 && REG_P (XEXP (mem
, 0)) && (int) REGNO (XEXP (mem
, 0)) == np_reg
)
4780 mem
= XEXP (mem
, 1);
4781 if (GET_CODE (mem
) == CONST_INT
&& INTVAL (mem
) > 0)
4787 /* Return nonzero if INSN contains any loads that may trap. */
4790 trapping_loads_p (rtx insn
, int np_reg
, bool after_np_branch
)
4792 rtx mem
= SET_SRC (single_set (insn
));
4794 if (!after_np_branch
)
4796 return ((np_reg
== -1 || !harmless_null_pointer_p (mem
, np_reg
))
4797 && may_trap_p (mem
));
4800 /* Return INSN if it is of TYPE_MCLD. Alternatively, if INSN is the start of
4801 a three-insn bundle, see if one of them is a load and return that if so.
4802 Return NULL_RTX if the insn does not contain loads. */
4804 find_load (rtx insn
)
4806 if (!NONDEBUG_INSN_P (insn
))
4808 if (get_attr_type (insn
) == TYPE_MCLD
)
4810 if (GET_MODE (insn
) != SImode
)
4813 insn
= NEXT_INSN (insn
);
4814 if ((GET_MODE (insn
) == SImode
|| GET_MODE (insn
) == QImode
)
4815 && get_attr_type (insn
) == TYPE_MCLD
)
4817 } while (GET_MODE (insn
) != QImode
);
4821 /* Determine whether PAT is an indirect call pattern. */
4823 indirect_call_p (rtx pat
)
4825 if (GET_CODE (pat
) == PARALLEL
)
4826 pat
= XVECEXP (pat
, 0, 0);
4827 if (GET_CODE (pat
) == SET
)
4828 pat
= SET_SRC (pat
);
4829 gcc_assert (GET_CODE (pat
) == CALL
);
4830 pat
= XEXP (pat
, 0);
4831 gcc_assert (GET_CODE (pat
) == MEM
);
4832 pat
= XEXP (pat
, 0);
4837 /* During workaround_speculation, track whether we're in the shadow of a
4838 conditional branch that tests a P register for NULL. If so, we can omit
4839 emitting NOPs if we see a load from that P register, since a speculative
4840 access at address 0 isn't a problem, and the load is executed in all other
4842 Global for communication with note_np_check_stores through note_stores.
4844 int np_check_regno
= -1;
4845 bool np_after_branch
= false;
4847 /* Subroutine of workaround_speculation, called through note_stores. */
4849 note_np_check_stores (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
4850 void *data ATTRIBUTE_UNUSED
)
4852 if (REG_P (x
) && (REGNO (x
) == REG_CC
|| (int) REGNO (x
) == np_check_regno
))
4853 np_check_regno
= -1;
4857 workaround_speculation (void)
4860 rtx last_condjump
= NULL_RTX
;
4861 int cycles_since_jump
= INT_MAX
;
4862 int delay_added
= 0;
4864 if (! ENABLE_WA_SPECULATIVE_LOADS
&& ! ENABLE_WA_SPECULATIVE_SYNCS
4865 && ! ENABLE_WA_INDIRECT_CALLS
)
4868 /* First pass: find predicted-false branches; if something after them
4869 needs nops, insert them or change the branch to predict true. */
4870 for (insn
= get_insns (); insn
; insn
= next
)
4873 int delay_needed
= 0;
4875 next
= find_next_insn_start (insn
);
4877 if (NOTE_P (insn
) || BARRIER_P (insn
))
4882 np_check_regno
= -1;
4886 pat
= PATTERN (insn
);
4887 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
4888 || GET_CODE (pat
) == ADDR_VEC
|| GET_CODE (pat
) == ADDR_DIFF_VEC
)
4891 if (GET_CODE (pat
) == ASM_INPUT
|| asm_noperands (pat
) >= 0)
4893 np_check_regno
= -1;
4899 /* Is this a condjump based on a null pointer comparison we saw
4901 if (np_check_regno
!= -1
4902 && recog_memoized (insn
) == CODE_FOR_cbranchbi4
)
4904 rtx op
= XEXP (SET_SRC (PATTERN (insn
)), 0);
4905 gcc_assert (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
4906 if (GET_CODE (op
) == NE
)
4907 np_after_branch
= true;
4909 if (any_condjump_p (insn
)
4910 && ! cbranch_predicted_taken_p (insn
))
4912 last_condjump
= insn
;
4914 cycles_since_jump
= 0;
4917 cycles_since_jump
= INT_MAX
;
4919 else if (CALL_P (insn
))
4921 np_check_regno
= -1;
4922 if (cycles_since_jump
< INT_MAX
)
4923 cycles_since_jump
++;
4924 if (indirect_call_p (pat
) && ENABLE_WA_INDIRECT_CALLS
)
4929 else if (NONDEBUG_INSN_P (insn
))
4931 rtx load_insn
= find_load (insn
);
4932 enum attr_type type
= type_for_anomaly (insn
);
4934 if (cycles_since_jump
< INT_MAX
)
4935 cycles_since_jump
++;
4937 /* Detect a comparison of a P register with zero. If we later
4938 see a condjump based on it, we have found a null pointer
4940 if (recog_memoized (insn
) == CODE_FOR_compare_eq
)
4942 rtx src
= SET_SRC (PATTERN (insn
));
4943 if (REG_P (XEXP (src
, 0))
4944 && P_REGNO_P (REGNO (XEXP (src
, 0)))
4945 && XEXP (src
, 1) == const0_rtx
)
4947 np_check_regno
= REGNO (XEXP (src
, 0));
4948 np_after_branch
= false;
4951 np_check_regno
= -1;
4954 if (load_insn
&& ENABLE_WA_SPECULATIVE_LOADS
)
4956 if (trapping_loads_p (load_insn
, np_check_regno
,
4960 else if (type
== TYPE_SYNC
&& ENABLE_WA_SPECULATIVE_SYNCS
)
4963 /* See if we need to forget about a null pointer comparison
4964 we found earlier. */
4965 if (recog_memoized (insn
) != CODE_FOR_compare_eq
)
4967 note_stores (PATTERN (insn
), note_np_check_stores
, NULL
);
4968 if (np_check_regno
!= -1)
4970 if (find_regno_note (insn
, REG_INC
, np_check_regno
))
4971 np_check_regno
= -1;
4977 if (delay_needed
> cycles_since_jump
4978 && (delay_needed
- cycles_since_jump
) > delay_added
)
4982 rtx
*op
= recog_data
.operand
;
4984 delay_needed
-= cycles_since_jump
;
4986 extract_insn (last_condjump
);
4989 pat1
= gen_cbranch_predicted_taken (op
[0], op
[1], op
[2],
4991 cycles_since_jump
= INT_MAX
;
4995 /* Do not adjust cycles_since_jump in this case, so that
4996 we'll increase the number of NOPs for a subsequent insn
4998 pat1
= gen_cbranch_with_nops (op
[0], op
[1], op
[2], op
[3],
4999 GEN_INT (delay_needed
));
5000 delay_added
= delay_needed
;
5002 PATTERN (last_condjump
) = pat1
;
5003 INSN_CODE (last_condjump
) = recog (pat1
, insn
, &num_clobbers
);
5007 cycles_since_jump
= INT_MAX
;
5012 /* Second pass: for predicted-true branches, see if anything at the
5013 branch destination needs extra nops. */
5014 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5016 int cycles_since_jump
;
5018 && any_condjump_p (insn
)
5019 && (INSN_CODE (insn
) == CODE_FOR_cbranch_predicted_taken
5020 || cbranch_predicted_taken_p (insn
)))
5022 rtx target
= JUMP_LABEL (insn
);
5026 cycles_since_jump
= 0;
5027 for (; target
&& cycles_since_jump
< 3; target
= next_tgt
)
5031 next_tgt
= find_next_insn_start (target
);
5033 if (NOTE_P (target
) || BARRIER_P (target
) || LABEL_P (target
))
5036 pat
= PATTERN (target
);
5037 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
5038 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
5039 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
5042 if (NONDEBUG_INSN_P (target
))
5044 rtx load_insn
= find_load (target
);
5045 enum attr_type type
= type_for_anomaly (target
);
5046 int delay_needed
= 0;
5047 if (cycles_since_jump
< INT_MAX
)
5048 cycles_since_jump
++;
5050 if (load_insn
&& ENABLE_WA_SPECULATIVE_LOADS
)
5052 if (trapping_loads_p (load_insn
, -1, false))
5055 else if (type
== TYPE_SYNC
&& ENABLE_WA_SPECULATIVE_SYNCS
)
5058 if (delay_needed
> cycles_since_jump
)
5060 rtx prev
= prev_real_insn (label
);
5061 delay_needed
-= cycles_since_jump
;
5063 fprintf (dump_file
, "Adding %d nops after %d\n",
5064 delay_needed
, INSN_UID (label
));
5066 && INSN_CODE (prev
) == CODE_FOR_cbranch_with_nops
)
5073 "Reducing nops on insn %d.\n",
5076 x
= XVECEXP (x
, 0, 1);
5077 v
= INTVAL (XVECEXP (x
, 0, 0)) - delay_needed
;
5078 XVECEXP (x
, 0, 0) = GEN_INT (v
);
5080 while (delay_needed
-- > 0)
5081 emit_insn_after (gen_nop (), label
);
5090 /* Called just before the final scheduling pass. If we need to insert NOPs
5091 later on to work around speculative loads, insert special placeholder
5092 insns that cause loads to be delayed for as many cycles as necessary
5093 (and possible). This reduces the number of NOPs we need to add.
5094 The dummy insns we generate are later removed by bfin_gen_bundles. */
5096 add_sched_insns_for_speculation (void)
5100 if (! ENABLE_WA_SPECULATIVE_LOADS
&& ! ENABLE_WA_SPECULATIVE_SYNCS
5101 && ! ENABLE_WA_INDIRECT_CALLS
)
5104 /* First pass: find predicted-false branches; if something after them
5105 needs nops, insert them or change the branch to predict true. */
5106 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5110 if (NOTE_P (insn
) || BARRIER_P (insn
) || LABEL_P (insn
))
5113 pat
= PATTERN (insn
);
5114 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
5115 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
5116 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
5121 if (any_condjump_p (insn
)
5122 && !cbranch_predicted_taken_p (insn
))
5124 rtx n
= next_real_insn (insn
);
5125 emit_insn_before (gen_stall (GEN_INT (3)), n
);
5130 /* Second pass: for predicted-true branches, see if anything at the
5131 branch destination needs extra nops. */
5132 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5135 && any_condjump_p (insn
)
5136 && (cbranch_predicted_taken_p (insn
)))
5138 rtx target
= JUMP_LABEL (insn
);
5139 rtx next
= next_real_insn (target
);
5141 if (GET_CODE (PATTERN (next
)) == UNSPEC_VOLATILE
5142 && get_attr_type (next
) == TYPE_STALL
)
5144 emit_insn_before (gen_stall (GEN_INT (1)), next
);
5149 /* We use the machine specific reorg pass for emitting CSYNC instructions
5150 after conditional branches as needed.
5152 The Blackfin is unusual in that a code sequence like
5155 may speculatively perform the load even if the condition isn't true. This
5156 happens for a branch that is predicted not taken, because the pipeline
5157 isn't flushed or stalled, so the early stages of the following instructions,
5158 which perform the memory reference, are allowed to execute before the
5159 jump condition is evaluated.
5160 Therefore, we must insert additional instructions in all places where this
5161 could lead to incorrect behavior. The manual recommends CSYNC, while
5162 VDSP seems to use NOPs (even though its corresponding compiler option is
5165 When optimizing for speed, we emit NOPs, which seems faster than a CSYNC.
5166 When optimizing for size, we turn the branch into a predicted taken one.
5167 This may be slower due to mispredicts, but saves code size. */
5172 /* We are freeing block_for_insn in the toplev to keep compatibility
5173 with old MDEP_REORGS that are not CFG based. Recompute it now. */
5174 compute_bb_for_insn ();
5176 if (flag_schedule_insns_after_reload
)
5178 splitting_for_sched
= 1;
5180 splitting_for_sched
= 0;
5182 add_sched_insns_for_speculation ();
5184 timevar_push (TV_SCHED2
);
5185 if (flag_selective_scheduling2
5186 && !maybe_skip_selective_scheduling ())
5187 run_selective_scheduling ();
5190 timevar_pop (TV_SCHED2
);
5192 /* Examine the schedule and insert nops as necessary for 64-bit parallel
5194 bfin_gen_bundles ();
5199 /* Doloop optimization */
5200 if (cfun
->machine
->has_hardware_loops
)
5201 bfin_reorg_loops (dump_file
);
5203 workaround_speculation ();
5205 if (flag_var_tracking
)
5207 timevar_push (TV_VAR_TRACKING
);
5208 variable_tracking_main ();
5209 reorder_var_tracking_notes ();
5210 timevar_pop (TV_VAR_TRACKING
);
5213 df_finish_pass (false);
5215 workaround_rts_anomaly ();
5218 /* Handle interrupt_handler, exception_handler and nmi_handler function
5219 attributes; arguments as in struct attribute_spec.handler. */
5222 handle_int_attribute (tree
*node
, tree name
,
5223 tree args ATTRIBUTE_UNUSED
,
5224 int flags ATTRIBUTE_UNUSED
,
5228 if (TREE_CODE (x
) == FUNCTION_DECL
)
5231 if (TREE_CODE (x
) != FUNCTION_TYPE
)
5233 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5235 *no_add_attrs
= true;
5237 else if (funkind (x
) != SUBROUTINE
)
5238 error ("multiple function type attributes specified");
5243 /* Return 0 if the attributes for two types are incompatible, 1 if they
5244 are compatible, and 2 if they are nearly compatible (which causes a
5245 warning to be generated). */
5248 bfin_comp_type_attributes (const_tree type1
, const_tree type2
)
5250 e_funkind kind1
, kind2
;
5252 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
5255 kind1
= funkind (type1
);
5256 kind2
= funkind (type2
);
5261 /* Check for mismatched modifiers */
5262 if (!lookup_attribute ("nesting", TYPE_ATTRIBUTES (type1
))
5263 != !lookup_attribute ("nesting", TYPE_ATTRIBUTES (type2
)))
5266 if (!lookup_attribute ("saveall", TYPE_ATTRIBUTES (type1
))
5267 != !lookup_attribute ("saveall", TYPE_ATTRIBUTES (type2
)))
5270 if (!lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type1
))
5271 != !lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type2
)))
5274 if (!lookup_attribute ("longcall", TYPE_ATTRIBUTES (type1
))
5275 != !lookup_attribute ("longcall", TYPE_ATTRIBUTES (type2
)))
5281 /* Handle a "longcall" or "shortcall" attribute; arguments as in
5282 struct attribute_spec.handler. */
5285 bfin_handle_longcall_attribute (tree
*node
, tree name
,
5286 tree args ATTRIBUTE_UNUSED
,
5287 int flags ATTRIBUTE_UNUSED
,
5290 if (TREE_CODE (*node
) != FUNCTION_TYPE
5291 && TREE_CODE (*node
) != FIELD_DECL
5292 && TREE_CODE (*node
) != TYPE_DECL
)
5294 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5296 *no_add_attrs
= true;
5299 if ((strcmp (IDENTIFIER_POINTER (name
), "longcall") == 0
5300 && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (*node
)))
5301 || (strcmp (IDENTIFIER_POINTER (name
), "shortcall") == 0
5302 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (*node
))))
5304 warning (OPT_Wattributes
,
5305 "can%'t apply both longcall and shortcall attributes to the same function");
5306 *no_add_attrs
= true;
5312 /* Handle a "l1_text" attribute; arguments as in
5313 struct attribute_spec.handler. */
5316 bfin_handle_l1_text_attribute (tree
*node
, tree name
, tree
ARG_UNUSED (args
),
5317 int ARG_UNUSED (flags
), bool *no_add_attrs
)
5321 if (TREE_CODE (decl
) != FUNCTION_DECL
)
5323 error ("%qE attribute only applies to functions",
5325 *no_add_attrs
= true;
5328 /* The decl may have already been given a section attribute
5329 from a previous declaration. Ensure they match. */
5330 else if (DECL_SECTION_NAME (decl
) != NULL_TREE
5331 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
5334 error ("section of %q+D conflicts with previous declaration",
5336 *no_add_attrs
= true;
5339 DECL_SECTION_NAME (decl
) = build_string (9, ".l1.text");
5344 /* Handle a "l1_data", "l1_data_A" or "l1_data_B" attribute;
5345 arguments as in struct attribute_spec.handler. */
5348 bfin_handle_l1_data_attribute (tree
*node
, tree name
, tree
ARG_UNUSED (args
),
5349 int ARG_UNUSED (flags
), bool *no_add_attrs
)
5353 if (TREE_CODE (decl
) != VAR_DECL
)
5355 error ("%qE attribute only applies to variables",
5357 *no_add_attrs
= true;
5359 else if (current_function_decl
!= NULL_TREE
5360 && !TREE_STATIC (decl
))
5362 error ("%qE attribute cannot be specified for local variables",
5364 *no_add_attrs
= true;
5368 const char *section_name
;
5370 if (strcmp (IDENTIFIER_POINTER (name
), "l1_data") == 0)
5371 section_name
= ".l1.data";
5372 else if (strcmp (IDENTIFIER_POINTER (name
), "l1_data_A") == 0)
5373 section_name
= ".l1.data.A";
5374 else if (strcmp (IDENTIFIER_POINTER (name
), "l1_data_B") == 0)
5375 section_name
= ".l1.data.B";
5379 /* The decl may have already been given a section attribute
5380 from a previous declaration. Ensure they match. */
5381 if (DECL_SECTION_NAME (decl
) != NULL_TREE
5382 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
5385 error ("section of %q+D conflicts with previous declaration",
5387 *no_add_attrs
= true;
5390 DECL_SECTION_NAME (decl
)
5391 = build_string (strlen (section_name
) + 1, section_name
);
5397 /* Handle a "l2" attribute; arguments as in struct attribute_spec.handler. */
5400 bfin_handle_l2_attribute (tree
*node
, tree
ARG_UNUSED (name
),
5401 tree
ARG_UNUSED (args
), int ARG_UNUSED (flags
),
5406 if (TREE_CODE (decl
) == FUNCTION_DECL
)
5408 if (DECL_SECTION_NAME (decl
) != NULL_TREE
5409 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
5412 error ("section of %q+D conflicts with previous declaration",
5414 *no_add_attrs
= true;
5417 DECL_SECTION_NAME (decl
) = build_string (9, ".l2.text");
5419 else if (TREE_CODE (decl
) == VAR_DECL
)
5421 if (DECL_SECTION_NAME (decl
) != NULL_TREE
5422 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
5425 error ("section of %q+D conflicts with previous declaration",
5427 *no_add_attrs
= true;
5430 DECL_SECTION_NAME (decl
) = build_string (9, ".l2.data");
5436 /* Table of valid machine attributes. */
5437 static const struct attribute_spec bfin_attribute_table
[] =
5439 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5440 affects_type_identity } */
5441 { "interrupt_handler", 0, 0, false, true, true, handle_int_attribute
,
5443 { "exception_handler", 0, 0, false, true, true, handle_int_attribute
,
5445 { "nmi_handler", 0, 0, false, true, true, handle_int_attribute
, false },
5446 { "nesting", 0, 0, false, true, true, NULL
, false },
5447 { "kspisusp", 0, 0, false, true, true, NULL
, false },
5448 { "saveall", 0, 0, false, true, true, NULL
, false },
5449 { "longcall", 0, 0, false, true, true, bfin_handle_longcall_attribute
,
5451 { "shortcall", 0, 0, false, true, true, bfin_handle_longcall_attribute
,
5453 { "l1_text", 0, 0, true, false, false, bfin_handle_l1_text_attribute
,
5455 { "l1_data", 0, 0, true, false, false, bfin_handle_l1_data_attribute
,
5457 { "l1_data_A", 0, 0, true, false, false, bfin_handle_l1_data_attribute
,
5459 { "l1_data_B", 0, 0, true, false, false, bfin_handle_l1_data_attribute
,
5461 { "l2", 0, 0, true, false, false, bfin_handle_l2_attribute
, false },
5462 { NULL
, 0, 0, false, false, false, NULL
, false }
5465 /* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to
5466 tell the assembler to generate pointers to function descriptors in
5470 bfin_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
5472 if (TARGET_FDPIC
&& size
== UNITS_PER_WORD
)
5474 if (GET_CODE (value
) == SYMBOL_REF
5475 && SYMBOL_REF_FUNCTION_P (value
))
5477 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
5478 output_addr_const (asm_out_file
, value
);
5479 fputs (")\n", asm_out_file
);
5484 /* We've set the unaligned SI op to NULL, so we always have to
5485 handle the unaligned case here. */
5486 assemble_integer_with_op ("\t.4byte\t", value
);
5490 return default_assemble_integer (value
, size
, aligned_p
);
5493 /* Output the assembler code for a thunk function. THUNK_DECL is the
5494 declaration for the thunk function itself, FUNCTION is the decl for
5495 the target function. DELTA is an immediate constant offset to be
5496 added to THIS. If VCALL_OFFSET is nonzero, the word at
5497 *(*this + vcall_offset) should be added to THIS. */
5500 bfin_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED
,
5501 tree thunk ATTRIBUTE_UNUSED
, HOST_WIDE_INT delta
,
5502 HOST_WIDE_INT vcall_offset
, tree function
)
5505 /* The this parameter is passed as the first argument. */
5506 rtx this_rtx
= gen_rtx_REG (Pmode
, REG_R0
);
5508 /* Adjust the this parameter by a fixed constant. */
5512 if (delta
>= -64 && delta
<= 63)
5514 xops
[0] = GEN_INT (delta
);
5515 output_asm_insn ("%1 += %0;", xops
);
5517 else if (delta
>= -128 && delta
< -64)
5519 xops
[0] = GEN_INT (delta
+ 64);
5520 output_asm_insn ("%1 += -64; %1 += %0;", xops
);
5522 else if (delta
> 63 && delta
<= 126)
5524 xops
[0] = GEN_INT (delta
- 63);
5525 output_asm_insn ("%1 += 63; %1 += %0;", xops
);
5529 xops
[0] = GEN_INT (delta
);
5530 output_asm_insn ("r3.l = %h0; r3.h = %d0; %1 = %1 + r3;", xops
);
5534 /* Adjust the this parameter by a value stored in the vtable. */
5537 rtx p2tmp
= gen_rtx_REG (Pmode
, REG_P2
);
5538 rtx tmp
= gen_rtx_REG (Pmode
, REG_R3
);
5542 output_asm_insn ("%2 = r0; %2 = [%2];", xops
);
5544 /* Adjust the this parameter. */
5545 xops
[0] = gen_rtx_MEM (Pmode
, plus_constant (p2tmp
, vcall_offset
));
5546 if (!memory_operand (xops
[0], Pmode
))
5548 rtx tmp2
= gen_rtx_REG (Pmode
, REG_P1
);
5549 xops
[0] = GEN_INT (vcall_offset
);
5551 output_asm_insn ("%h1 = %h0; %d1 = %d0; %2 = %2 + %1", xops
);
5552 xops
[0] = gen_rtx_MEM (Pmode
, p2tmp
);
5555 output_asm_insn ("%1 = %0; %2 = %2 + %1;", xops
);
5558 xops
[0] = XEXP (DECL_RTL (function
), 0);
5559 if (1 || !flag_pic
|| (*targetm
.binds_local_p
) (function
))
5560 output_asm_insn ("jump.l\t%P0", xops
);
5563 /* Codes for all the Blackfin builtins. */
5569 BFIN_BUILTIN_COMPOSE_2X16
,
5570 BFIN_BUILTIN_EXTRACTLO
,
5571 BFIN_BUILTIN_EXTRACTHI
,
5573 BFIN_BUILTIN_SSADD_2X16
,
5574 BFIN_BUILTIN_SSSUB_2X16
,
5575 BFIN_BUILTIN_SSADDSUB_2X16
,
5576 BFIN_BUILTIN_SSSUBADD_2X16
,
5577 BFIN_BUILTIN_MULT_2X16
,
5578 BFIN_BUILTIN_MULTR_2X16
,
5579 BFIN_BUILTIN_NEG_2X16
,
5580 BFIN_BUILTIN_ABS_2X16
,
5581 BFIN_BUILTIN_MIN_2X16
,
5582 BFIN_BUILTIN_MAX_2X16
,
5584 BFIN_BUILTIN_SSADD_1X16
,
5585 BFIN_BUILTIN_SSSUB_1X16
,
5586 BFIN_BUILTIN_MULT_1X16
,
5587 BFIN_BUILTIN_MULTR_1X16
,
5588 BFIN_BUILTIN_NORM_1X16
,
5589 BFIN_BUILTIN_NEG_1X16
,
5590 BFIN_BUILTIN_ABS_1X16
,
5591 BFIN_BUILTIN_MIN_1X16
,
5592 BFIN_BUILTIN_MAX_1X16
,
5594 BFIN_BUILTIN_SUM_2X16
,
5595 BFIN_BUILTIN_DIFFHL_2X16
,
5596 BFIN_BUILTIN_DIFFLH_2X16
,
5598 BFIN_BUILTIN_SSADD_1X32
,
5599 BFIN_BUILTIN_SSSUB_1X32
,
5600 BFIN_BUILTIN_NORM_1X32
,
5601 BFIN_BUILTIN_ROUND_1X32
,
5602 BFIN_BUILTIN_NEG_1X32
,
5603 BFIN_BUILTIN_ABS_1X32
,
5604 BFIN_BUILTIN_MIN_1X32
,
5605 BFIN_BUILTIN_MAX_1X32
,
5606 BFIN_BUILTIN_MULT_1X32
,
5607 BFIN_BUILTIN_MULT_1X32X32
,
5608 BFIN_BUILTIN_MULT_1X32X32NS
,
5610 BFIN_BUILTIN_MULHISILL
,
5611 BFIN_BUILTIN_MULHISILH
,
5612 BFIN_BUILTIN_MULHISIHL
,
5613 BFIN_BUILTIN_MULHISIHH
,
5615 BFIN_BUILTIN_LSHIFT_1X16
,
5616 BFIN_BUILTIN_LSHIFT_2X16
,
5617 BFIN_BUILTIN_SSASHIFT_1X16
,
5618 BFIN_BUILTIN_SSASHIFT_2X16
,
5619 BFIN_BUILTIN_SSASHIFT_1X32
,
5621 BFIN_BUILTIN_CPLX_MUL_16
,
5622 BFIN_BUILTIN_CPLX_MAC_16
,
5623 BFIN_BUILTIN_CPLX_MSU_16
,
5625 BFIN_BUILTIN_CPLX_MUL_16_S40
,
5626 BFIN_BUILTIN_CPLX_MAC_16_S40
,
5627 BFIN_BUILTIN_CPLX_MSU_16_S40
,
5629 BFIN_BUILTIN_CPLX_SQU
,
5631 BFIN_BUILTIN_LOADBYTES
,
5636 #define def_builtin(NAME, TYPE, CODE) \
5638 add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5642 /* Set up all builtin functions for this target. */
5644 bfin_init_builtins (void)
5646 tree V2HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V2HImode
);
5647 tree void_ftype_void
5648 = build_function_type_list (void_type_node
, NULL_TREE
);
5649 tree short_ftype_short
5650 = build_function_type_list (short_integer_type_node
, short_integer_type_node
,
5652 tree short_ftype_int_int
5653 = build_function_type_list (short_integer_type_node
, integer_type_node
,
5654 integer_type_node
, NULL_TREE
);
5655 tree int_ftype_int_int
5656 = build_function_type_list (integer_type_node
, integer_type_node
,
5657 integer_type_node
, NULL_TREE
);
5659 = build_function_type_list (integer_type_node
, integer_type_node
,
5661 tree short_ftype_int
5662 = build_function_type_list (short_integer_type_node
, integer_type_node
,
5664 tree int_ftype_v2hi_v2hi
5665 = build_function_type_list (integer_type_node
, V2HI_type_node
,
5666 V2HI_type_node
, NULL_TREE
);
5667 tree v2hi_ftype_v2hi_v2hi
5668 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
5669 V2HI_type_node
, NULL_TREE
);
5670 tree v2hi_ftype_v2hi_v2hi_v2hi
5671 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
5672 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
5673 tree v2hi_ftype_int_int
5674 = build_function_type_list (V2HI_type_node
, integer_type_node
,
5675 integer_type_node
, NULL_TREE
);
5676 tree v2hi_ftype_v2hi_int
5677 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
5678 integer_type_node
, NULL_TREE
);
5679 tree int_ftype_short_short
5680 = build_function_type_list (integer_type_node
, short_integer_type_node
,
5681 short_integer_type_node
, NULL_TREE
);
5682 tree v2hi_ftype_v2hi
5683 = build_function_type_list (V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
5684 tree short_ftype_v2hi
5685 = build_function_type_list (short_integer_type_node
, V2HI_type_node
,
5688 = build_function_type_list (integer_type_node
,
5689 build_pointer_type (integer_type_node
),
5692 /* Add the remaining MMX insns with somewhat more complicated types. */
5693 def_builtin ("__builtin_bfin_csync", void_ftype_void
, BFIN_BUILTIN_CSYNC
);
5694 def_builtin ("__builtin_bfin_ssync", void_ftype_void
, BFIN_BUILTIN_SSYNC
);
5696 def_builtin ("__builtin_bfin_ones", short_ftype_int
, BFIN_BUILTIN_ONES
);
5698 def_builtin ("__builtin_bfin_compose_2x16", v2hi_ftype_int_int
,
5699 BFIN_BUILTIN_COMPOSE_2X16
);
5700 def_builtin ("__builtin_bfin_extract_hi", short_ftype_v2hi
,
5701 BFIN_BUILTIN_EXTRACTHI
);
5702 def_builtin ("__builtin_bfin_extract_lo", short_ftype_v2hi
,
5703 BFIN_BUILTIN_EXTRACTLO
);
5705 def_builtin ("__builtin_bfin_min_fr2x16", v2hi_ftype_v2hi_v2hi
,
5706 BFIN_BUILTIN_MIN_2X16
);
5707 def_builtin ("__builtin_bfin_max_fr2x16", v2hi_ftype_v2hi_v2hi
,
5708 BFIN_BUILTIN_MAX_2X16
);
5710 def_builtin ("__builtin_bfin_add_fr2x16", v2hi_ftype_v2hi_v2hi
,
5711 BFIN_BUILTIN_SSADD_2X16
);
5712 def_builtin ("__builtin_bfin_sub_fr2x16", v2hi_ftype_v2hi_v2hi
,
5713 BFIN_BUILTIN_SSSUB_2X16
);
5714 def_builtin ("__builtin_bfin_dspaddsubsat", v2hi_ftype_v2hi_v2hi
,
5715 BFIN_BUILTIN_SSADDSUB_2X16
);
5716 def_builtin ("__builtin_bfin_dspsubaddsat", v2hi_ftype_v2hi_v2hi
,
5717 BFIN_BUILTIN_SSSUBADD_2X16
);
5718 def_builtin ("__builtin_bfin_mult_fr2x16", v2hi_ftype_v2hi_v2hi
,
5719 BFIN_BUILTIN_MULT_2X16
);
5720 def_builtin ("__builtin_bfin_multr_fr2x16", v2hi_ftype_v2hi_v2hi
,
5721 BFIN_BUILTIN_MULTR_2X16
);
5722 def_builtin ("__builtin_bfin_negate_fr2x16", v2hi_ftype_v2hi
,
5723 BFIN_BUILTIN_NEG_2X16
);
5724 def_builtin ("__builtin_bfin_abs_fr2x16", v2hi_ftype_v2hi
,
5725 BFIN_BUILTIN_ABS_2X16
);
5727 def_builtin ("__builtin_bfin_min_fr1x16", short_ftype_int_int
,
5728 BFIN_BUILTIN_MIN_1X16
);
5729 def_builtin ("__builtin_bfin_max_fr1x16", short_ftype_int_int
,
5730 BFIN_BUILTIN_MAX_1X16
);
5732 def_builtin ("__builtin_bfin_add_fr1x16", short_ftype_int_int
,
5733 BFIN_BUILTIN_SSADD_1X16
);
5734 def_builtin ("__builtin_bfin_sub_fr1x16", short_ftype_int_int
,
5735 BFIN_BUILTIN_SSSUB_1X16
);
5736 def_builtin ("__builtin_bfin_mult_fr1x16", short_ftype_int_int
,
5737 BFIN_BUILTIN_MULT_1X16
);
5738 def_builtin ("__builtin_bfin_multr_fr1x16", short_ftype_int_int
,
5739 BFIN_BUILTIN_MULTR_1X16
);
5740 def_builtin ("__builtin_bfin_negate_fr1x16", short_ftype_short
,
5741 BFIN_BUILTIN_NEG_1X16
);
5742 def_builtin ("__builtin_bfin_abs_fr1x16", short_ftype_short
,
5743 BFIN_BUILTIN_ABS_1X16
);
5744 def_builtin ("__builtin_bfin_norm_fr1x16", short_ftype_int
,
5745 BFIN_BUILTIN_NORM_1X16
);
5747 def_builtin ("__builtin_bfin_sum_fr2x16", short_ftype_v2hi
,
5748 BFIN_BUILTIN_SUM_2X16
);
5749 def_builtin ("__builtin_bfin_diff_hl_fr2x16", short_ftype_v2hi
,
5750 BFIN_BUILTIN_DIFFHL_2X16
);
5751 def_builtin ("__builtin_bfin_diff_lh_fr2x16", short_ftype_v2hi
,
5752 BFIN_BUILTIN_DIFFLH_2X16
);
5754 def_builtin ("__builtin_bfin_mulhisill", int_ftype_v2hi_v2hi
,
5755 BFIN_BUILTIN_MULHISILL
);
5756 def_builtin ("__builtin_bfin_mulhisihl", int_ftype_v2hi_v2hi
,
5757 BFIN_BUILTIN_MULHISIHL
);
5758 def_builtin ("__builtin_bfin_mulhisilh", int_ftype_v2hi_v2hi
,
5759 BFIN_BUILTIN_MULHISILH
);
5760 def_builtin ("__builtin_bfin_mulhisihh", int_ftype_v2hi_v2hi
,
5761 BFIN_BUILTIN_MULHISIHH
);
5763 def_builtin ("__builtin_bfin_min_fr1x32", int_ftype_int_int
,
5764 BFIN_BUILTIN_MIN_1X32
);
5765 def_builtin ("__builtin_bfin_max_fr1x32", int_ftype_int_int
,
5766 BFIN_BUILTIN_MAX_1X32
);
5768 def_builtin ("__builtin_bfin_add_fr1x32", int_ftype_int_int
,
5769 BFIN_BUILTIN_SSADD_1X32
);
5770 def_builtin ("__builtin_bfin_sub_fr1x32", int_ftype_int_int
,
5771 BFIN_BUILTIN_SSSUB_1X32
);
5772 def_builtin ("__builtin_bfin_negate_fr1x32", int_ftype_int
,
5773 BFIN_BUILTIN_NEG_1X32
);
5774 def_builtin ("__builtin_bfin_abs_fr1x32", int_ftype_int
,
5775 BFIN_BUILTIN_ABS_1X32
);
5776 def_builtin ("__builtin_bfin_norm_fr1x32", short_ftype_int
,
5777 BFIN_BUILTIN_NORM_1X32
);
5778 def_builtin ("__builtin_bfin_round_fr1x32", short_ftype_int
,
5779 BFIN_BUILTIN_ROUND_1X32
);
5780 def_builtin ("__builtin_bfin_mult_fr1x32", int_ftype_short_short
,
5781 BFIN_BUILTIN_MULT_1X32
);
5782 def_builtin ("__builtin_bfin_mult_fr1x32x32", int_ftype_int_int
,
5783 BFIN_BUILTIN_MULT_1X32X32
);
5784 def_builtin ("__builtin_bfin_mult_fr1x32x32NS", int_ftype_int_int
,
5785 BFIN_BUILTIN_MULT_1X32X32NS
);
5788 def_builtin ("__builtin_bfin_shl_fr1x16", short_ftype_int_int
,
5789 BFIN_BUILTIN_SSASHIFT_1X16
);
5790 def_builtin ("__builtin_bfin_shl_fr2x16", v2hi_ftype_v2hi_int
,
5791 BFIN_BUILTIN_SSASHIFT_2X16
);
5792 def_builtin ("__builtin_bfin_lshl_fr1x16", short_ftype_int_int
,
5793 BFIN_BUILTIN_LSHIFT_1X16
);
5794 def_builtin ("__builtin_bfin_lshl_fr2x16", v2hi_ftype_v2hi_int
,
5795 BFIN_BUILTIN_LSHIFT_2X16
);
5796 def_builtin ("__builtin_bfin_shl_fr1x32", int_ftype_int_int
,
5797 BFIN_BUILTIN_SSASHIFT_1X32
);
5799 /* Complex numbers. */
5800 def_builtin ("__builtin_bfin_cmplx_add", v2hi_ftype_v2hi_v2hi
,
5801 BFIN_BUILTIN_SSADD_2X16
);
5802 def_builtin ("__builtin_bfin_cmplx_sub", v2hi_ftype_v2hi_v2hi
,
5803 BFIN_BUILTIN_SSSUB_2X16
);
5804 def_builtin ("__builtin_bfin_cmplx_mul", v2hi_ftype_v2hi_v2hi
,
5805 BFIN_BUILTIN_CPLX_MUL_16
);
5806 def_builtin ("__builtin_bfin_cmplx_mac", v2hi_ftype_v2hi_v2hi_v2hi
,
5807 BFIN_BUILTIN_CPLX_MAC_16
);
5808 def_builtin ("__builtin_bfin_cmplx_msu", v2hi_ftype_v2hi_v2hi_v2hi
,
5809 BFIN_BUILTIN_CPLX_MSU_16
);
5810 def_builtin ("__builtin_bfin_cmplx_mul_s40", v2hi_ftype_v2hi_v2hi
,
5811 BFIN_BUILTIN_CPLX_MUL_16_S40
);
5812 def_builtin ("__builtin_bfin_cmplx_mac_s40", v2hi_ftype_v2hi_v2hi_v2hi
,
5813 BFIN_BUILTIN_CPLX_MAC_16_S40
);
5814 def_builtin ("__builtin_bfin_cmplx_msu_s40", v2hi_ftype_v2hi_v2hi_v2hi
,
5815 BFIN_BUILTIN_CPLX_MSU_16_S40
);
5816 def_builtin ("__builtin_bfin_csqu_fr16", v2hi_ftype_v2hi
,
5817 BFIN_BUILTIN_CPLX_SQU
);
5819 /* "Unaligned" load. */
5820 def_builtin ("__builtin_bfin_loadbytes", int_ftype_pint
,
5821 BFIN_BUILTIN_LOADBYTES
);
5826 struct builtin_description
5828 const enum insn_code icode
;
5829 const char *const name
;
5830 const enum bfin_builtins code
;
5834 static const struct builtin_description bdesc_2arg
[] =
5836 { CODE_FOR_composev2hi
, "__builtin_bfin_compose_2x16", BFIN_BUILTIN_COMPOSE_2X16
, -1 },
5838 { CODE_FOR_ssashiftv2hi3
, "__builtin_bfin_shl_fr2x16", BFIN_BUILTIN_SSASHIFT_2X16
, -1 },
5839 { CODE_FOR_ssashifthi3
, "__builtin_bfin_shl_fr1x16", BFIN_BUILTIN_SSASHIFT_1X16
, -1 },
5840 { CODE_FOR_lshiftv2hi3
, "__builtin_bfin_lshl_fr2x16", BFIN_BUILTIN_LSHIFT_2X16
, -1 },
5841 { CODE_FOR_lshifthi3
, "__builtin_bfin_lshl_fr1x16", BFIN_BUILTIN_LSHIFT_1X16
, -1 },
5842 { CODE_FOR_ssashiftsi3
, "__builtin_bfin_shl_fr1x32", BFIN_BUILTIN_SSASHIFT_1X32
, -1 },
5844 { CODE_FOR_sminhi3
, "__builtin_bfin_min_fr1x16", BFIN_BUILTIN_MIN_1X16
, -1 },
5845 { CODE_FOR_smaxhi3
, "__builtin_bfin_max_fr1x16", BFIN_BUILTIN_MAX_1X16
, -1 },
5846 { CODE_FOR_ssaddhi3
, "__builtin_bfin_add_fr1x16", BFIN_BUILTIN_SSADD_1X16
, -1 },
5847 { CODE_FOR_sssubhi3
, "__builtin_bfin_sub_fr1x16", BFIN_BUILTIN_SSSUB_1X16
, -1 },
5849 { CODE_FOR_sminsi3
, "__builtin_bfin_min_fr1x32", BFIN_BUILTIN_MIN_1X32
, -1 },
5850 { CODE_FOR_smaxsi3
, "__builtin_bfin_max_fr1x32", BFIN_BUILTIN_MAX_1X32
, -1 },
5851 { CODE_FOR_ssaddsi3
, "__builtin_bfin_add_fr1x32", BFIN_BUILTIN_SSADD_1X32
, -1 },
5852 { CODE_FOR_sssubsi3
, "__builtin_bfin_sub_fr1x32", BFIN_BUILTIN_SSSUB_1X32
, -1 },
5854 { CODE_FOR_sminv2hi3
, "__builtin_bfin_min_fr2x16", BFIN_BUILTIN_MIN_2X16
, -1 },
5855 { CODE_FOR_smaxv2hi3
, "__builtin_bfin_max_fr2x16", BFIN_BUILTIN_MAX_2X16
, -1 },
5856 { CODE_FOR_ssaddv2hi3
, "__builtin_bfin_add_fr2x16", BFIN_BUILTIN_SSADD_2X16
, -1 },
5857 { CODE_FOR_sssubv2hi3
, "__builtin_bfin_sub_fr2x16", BFIN_BUILTIN_SSSUB_2X16
, -1 },
5858 { CODE_FOR_ssaddsubv2hi3
, "__builtin_bfin_dspaddsubsat", BFIN_BUILTIN_SSADDSUB_2X16
, -1 },
5859 { CODE_FOR_sssubaddv2hi3
, "__builtin_bfin_dspsubaddsat", BFIN_BUILTIN_SSSUBADD_2X16
, -1 },
5861 { CODE_FOR_flag_mulhisi
, "__builtin_bfin_mult_fr1x32", BFIN_BUILTIN_MULT_1X32
, MACFLAG_NONE
},
5862 { CODE_FOR_flag_mulhi
, "__builtin_bfin_mult_fr1x16", BFIN_BUILTIN_MULT_1X16
, MACFLAG_T
},
5863 { CODE_FOR_flag_mulhi
, "__builtin_bfin_multr_fr1x16", BFIN_BUILTIN_MULTR_1X16
, MACFLAG_NONE
},
5864 { CODE_FOR_flag_mulv2hi
, "__builtin_bfin_mult_fr2x16", BFIN_BUILTIN_MULT_2X16
, MACFLAG_T
},
5865 { CODE_FOR_flag_mulv2hi
, "__builtin_bfin_multr_fr2x16", BFIN_BUILTIN_MULTR_2X16
, MACFLAG_NONE
},
5867 { CODE_FOR_mulhisi_ll
, "__builtin_bfin_mulhisill", BFIN_BUILTIN_MULHISILL
, -1 },
5868 { CODE_FOR_mulhisi_lh
, "__builtin_bfin_mulhisilh", BFIN_BUILTIN_MULHISILH
, -1 },
5869 { CODE_FOR_mulhisi_hl
, "__builtin_bfin_mulhisihl", BFIN_BUILTIN_MULHISIHL
, -1 },
5870 { CODE_FOR_mulhisi_hh
, "__builtin_bfin_mulhisihh", BFIN_BUILTIN_MULHISIHH
, -1 }
5874 static const struct builtin_description bdesc_1arg
[] =
5876 { CODE_FOR_loadbytes
, "__builtin_bfin_loadbytes", BFIN_BUILTIN_LOADBYTES
, 0 },
5878 { CODE_FOR_ones
, "__builtin_bfin_ones", BFIN_BUILTIN_ONES
, 0 },
5880 { CODE_FOR_signbitshi2
, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16
, 0 },
5881 { CODE_FOR_ssneghi2
, "__builtin_bfin_negate_fr1x16", BFIN_BUILTIN_NEG_1X16
, 0 },
5882 { CODE_FOR_abshi2
, "__builtin_bfin_abs_fr1x16", BFIN_BUILTIN_ABS_1X16
, 0 },
5884 { CODE_FOR_signbitssi2
, "__builtin_bfin_norm_fr1x32", BFIN_BUILTIN_NORM_1X32
, 0 },
5885 { CODE_FOR_ssroundsi2
, "__builtin_bfin_round_fr1x32", BFIN_BUILTIN_ROUND_1X32
, 0 },
5886 { CODE_FOR_ssnegsi2
, "__builtin_bfin_negate_fr1x32", BFIN_BUILTIN_NEG_1X32
, 0 },
5887 { CODE_FOR_ssabssi2
, "__builtin_bfin_abs_fr1x32", BFIN_BUILTIN_ABS_1X32
, 0 },
5889 { CODE_FOR_movv2hi_hi_low
, "__builtin_bfin_extract_lo", BFIN_BUILTIN_EXTRACTLO
, 0 },
5890 { CODE_FOR_movv2hi_hi_high
, "__builtin_bfin_extract_hi", BFIN_BUILTIN_EXTRACTHI
, 0 },
5891 { CODE_FOR_ssnegv2hi2
, "__builtin_bfin_negate_fr2x16", BFIN_BUILTIN_NEG_2X16
, 0 },
5892 { CODE_FOR_ssabsv2hi2
, "__builtin_bfin_abs_fr2x16", BFIN_BUILTIN_ABS_2X16
, 0 }
5895 /* Errors in the source file can cause expand_expr to return const0_rtx
5896 where we expect a vector. To avoid crashing, use one of the vector
5897 clear instructions. */
5899 safe_vector_operand (rtx x
, enum machine_mode mode
)
5901 if (x
!= const0_rtx
)
5903 x
= gen_reg_rtx (SImode
);
5905 emit_insn (gen_movsi (x
, CONST0_RTX (SImode
)));
5906 return gen_lowpart (mode
, x
);
5909 /* Subroutine of bfin_expand_builtin to take care of binop insns. MACFLAG is -1
5910 if this is a normal binary op, or one of the MACFLAG_xxx constants. */
5913 bfin_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
,
5917 tree arg0
= CALL_EXPR_ARG (exp
, 0);
5918 tree arg1
= CALL_EXPR_ARG (exp
, 1);
5919 rtx op0
= expand_normal (arg0
);
5920 rtx op1
= expand_normal (arg1
);
5921 enum machine_mode op0mode
= GET_MODE (op0
);
5922 enum machine_mode op1mode
= GET_MODE (op1
);
5923 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
5924 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
5925 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
5927 if (VECTOR_MODE_P (mode0
))
5928 op0
= safe_vector_operand (op0
, mode0
);
5929 if (VECTOR_MODE_P (mode1
))
5930 op1
= safe_vector_operand (op1
, mode1
);
5933 || GET_MODE (target
) != tmode
5934 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5935 target
= gen_reg_rtx (tmode
);
5937 if ((op0mode
== SImode
|| op0mode
== VOIDmode
) && mode0
== HImode
)
5940 op0
= gen_lowpart (HImode
, op0
);
5942 if ((op1mode
== SImode
|| op1mode
== VOIDmode
) && mode1
== HImode
)
5945 op1
= gen_lowpart (HImode
, op1
);
5947 /* In case the insn wants input operands in modes different from
5948 the result, abort. */
5949 gcc_assert ((op0mode
== mode0
|| op0mode
== VOIDmode
)
5950 && (op1mode
== mode1
|| op1mode
== VOIDmode
));
5952 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
5953 op0
= copy_to_mode_reg (mode0
, op0
);
5954 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
5955 op1
= copy_to_mode_reg (mode1
, op1
);
5958 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
5960 pat
= GEN_FCN (icode
) (target
, op0
, op1
, GEN_INT (macflag
));
5968 /* Subroutine of bfin_expand_builtin to take care of unop insns. */
5971 bfin_expand_unop_builtin (enum insn_code icode
, tree exp
,
5975 tree arg0
= CALL_EXPR_ARG (exp
, 0);
5976 rtx op0
= expand_normal (arg0
);
5977 enum machine_mode op0mode
= GET_MODE (op0
);
5978 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
5979 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
5982 || GET_MODE (target
) != tmode
5983 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5984 target
= gen_reg_rtx (tmode
);
5986 if (VECTOR_MODE_P (mode0
))
5987 op0
= safe_vector_operand (op0
, mode0
);
5989 if (op0mode
== SImode
&& mode0
== HImode
)
5992 op0
= gen_lowpart (HImode
, op0
);
5994 gcc_assert (op0mode
== mode0
|| op0mode
== VOIDmode
);
5996 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
5997 op0
= copy_to_mode_reg (mode0
, op0
);
5999 pat
= GEN_FCN (icode
) (target
, op0
);
6006 /* Expand an expression EXP that calls a built-in function,
6007 with result going to TARGET if that's convenient
6008 (and in mode MODE if that's convenient).
6009 SUBTARGET may be used as the target for computing one of EXP's operands.
6010 IGNORE is nonzero if the value is to be ignored. */
6013 bfin_expand_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
6014 rtx subtarget ATTRIBUTE_UNUSED
,
6015 enum machine_mode mode ATTRIBUTE_UNUSED
,
6016 int ignore ATTRIBUTE_UNUSED
)
6019 enum insn_code icode
;
6020 const struct builtin_description
*d
;
6021 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
6022 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6023 tree arg0
, arg1
, arg2
;
6024 rtx op0
, op1
, op2
, accvec
, pat
, tmp1
, tmp2
, a0reg
, a1reg
;
6025 enum machine_mode tmode
, mode0
;
6029 case BFIN_BUILTIN_CSYNC
:
6030 emit_insn (gen_csync ());
6032 case BFIN_BUILTIN_SSYNC
:
6033 emit_insn (gen_ssync ());
6036 case BFIN_BUILTIN_DIFFHL_2X16
:
6037 case BFIN_BUILTIN_DIFFLH_2X16
:
6038 case BFIN_BUILTIN_SUM_2X16
:
6039 arg0
= CALL_EXPR_ARG (exp
, 0);
6040 op0
= expand_normal (arg0
);
6041 icode
= (fcode
== BFIN_BUILTIN_DIFFHL_2X16
? CODE_FOR_subhilov2hi3
6042 : fcode
== BFIN_BUILTIN_DIFFLH_2X16
? CODE_FOR_sublohiv2hi3
6043 : CODE_FOR_ssaddhilov2hi3
);
6044 tmode
= insn_data
[icode
].operand
[0].mode
;
6045 mode0
= insn_data
[icode
].operand
[1].mode
;
6048 || GET_MODE (target
) != tmode
6049 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6050 target
= gen_reg_rtx (tmode
);
6052 if (VECTOR_MODE_P (mode0
))
6053 op0
= safe_vector_operand (op0
, mode0
);
6055 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6056 op0
= copy_to_mode_reg (mode0
, op0
);
6058 pat
= GEN_FCN (icode
) (target
, op0
, op0
);
6064 case BFIN_BUILTIN_MULT_1X32X32
:
6065 case BFIN_BUILTIN_MULT_1X32X32NS
:
6066 arg0
= CALL_EXPR_ARG (exp
, 0);
6067 arg1
= CALL_EXPR_ARG (exp
, 1);
6068 op0
= expand_normal (arg0
);
6069 op1
= expand_normal (arg1
);
6071 || !register_operand (target
, SImode
))
6072 target
= gen_reg_rtx (SImode
);
6073 if (! register_operand (op0
, SImode
))
6074 op0
= copy_to_mode_reg (SImode
, op0
);
6075 if (! register_operand (op1
, SImode
))
6076 op1
= copy_to_mode_reg (SImode
, op1
);
6078 a1reg
= gen_rtx_REG (PDImode
, REG_A1
);
6079 a0reg
= gen_rtx_REG (PDImode
, REG_A0
);
6080 tmp1
= gen_lowpart (V2HImode
, op0
);
6081 tmp2
= gen_lowpart (V2HImode
, op1
);
6082 emit_insn (gen_flag_macinit1hi (a1reg
,
6083 gen_lowpart (HImode
, op0
),
6084 gen_lowpart (HImode
, op1
),
6085 GEN_INT (MACFLAG_FU
)));
6086 emit_insn (gen_lshrpdi3 (a1reg
, a1reg
, GEN_INT (16)));
6088 if (fcode
== BFIN_BUILTIN_MULT_1X32X32
)
6089 emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg
, a1reg
, tmp1
, tmp2
,
6090 const1_rtx
, const1_rtx
,
6091 const1_rtx
, const0_rtx
, a1reg
,
6092 const0_rtx
, GEN_INT (MACFLAG_NONE
),
6093 GEN_INT (MACFLAG_M
)));
6096 /* For saturating multiplication, there's exactly one special case
6097 to be handled: multiplying the smallest negative value with
6098 itself. Due to shift correction in fractional multiplies, this
6099 can overflow. Iff this happens, OP2 will contain 1, which, when
6100 added in 32 bits to the smallest negative, wraps to the largest
6101 positive, which is the result we want. */
6102 op2
= gen_reg_rtx (V2HImode
);
6103 emit_insn (gen_packv2hi (op2
, tmp1
, tmp2
, const0_rtx
, const0_rtx
));
6104 emit_insn (gen_movsibi (gen_rtx_REG (BImode
, REG_CC
),
6105 gen_lowpart (SImode
, op2
)));
6106 emit_insn (gen_flag_mul_macv2hi_parts_acconly_andcc0 (a0reg
, a1reg
, tmp1
, tmp2
,
6107 const1_rtx
, const1_rtx
,
6108 const1_rtx
, const0_rtx
, a1reg
,
6109 const0_rtx
, GEN_INT (MACFLAG_NONE
),
6110 GEN_INT (MACFLAG_M
)));
6111 op2
= gen_reg_rtx (SImode
);
6112 emit_insn (gen_movbisi (op2
, gen_rtx_REG (BImode
, REG_CC
)));
6114 emit_insn (gen_flag_machi_parts_acconly (a1reg
, tmp2
, tmp1
,
6115 const1_rtx
, const0_rtx
,
6116 a1reg
, const0_rtx
, GEN_INT (MACFLAG_M
)));
6117 emit_insn (gen_ashrpdi3 (a1reg
, a1reg
, GEN_INT (15)));
6118 emit_insn (gen_sum_of_accumulators (target
, a0reg
, a0reg
, a1reg
));
6119 if (fcode
== BFIN_BUILTIN_MULT_1X32X32NS
)
6120 emit_insn (gen_addsi3 (target
, target
, op2
));
6123 case BFIN_BUILTIN_CPLX_MUL_16
:
6124 case BFIN_BUILTIN_CPLX_MUL_16_S40
:
6125 arg0
= CALL_EXPR_ARG (exp
, 0);
6126 arg1
= CALL_EXPR_ARG (exp
, 1);
6127 op0
= expand_normal (arg0
);
6128 op1
= expand_normal (arg1
);
6129 accvec
= gen_reg_rtx (V2PDImode
);
6130 icode
= CODE_FOR_flag_macv2hi_parts
;
6131 tmode
= insn_data
[icode
].operand
[0].mode
;
6134 || GET_MODE (target
) != V2HImode
6135 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
6136 target
= gen_reg_rtx (tmode
);
6137 if (! register_operand (op0
, GET_MODE (op0
)))
6138 op0
= copy_to_mode_reg (GET_MODE (op0
), op0
);
6139 if (! register_operand (op1
, GET_MODE (op1
)))
6140 op1
= copy_to_mode_reg (GET_MODE (op1
), op1
);
6142 if (fcode
== BFIN_BUILTIN_CPLX_MUL_16
)
6143 emit_insn (gen_flag_macinit1v2hi_parts (accvec
, op0
, op1
, const0_rtx
,
6144 const0_rtx
, const0_rtx
,
6145 const1_rtx
, GEN_INT (MACFLAG_W32
)));
6147 emit_insn (gen_flag_macinit1v2hi_parts (accvec
, op0
, op1
, const0_rtx
,
6148 const0_rtx
, const0_rtx
,
6149 const1_rtx
, GEN_INT (MACFLAG_NONE
)));
6150 emit_insn (gen_flag_macv2hi_parts (target
, op0
, op1
, const1_rtx
,
6151 const1_rtx
, const1_rtx
,
6152 const0_rtx
, accvec
, const1_rtx
, const0_rtx
,
6153 GEN_INT (MACFLAG_NONE
), accvec
));
6157 case BFIN_BUILTIN_CPLX_MAC_16
:
6158 case BFIN_BUILTIN_CPLX_MSU_16
:
6159 case BFIN_BUILTIN_CPLX_MAC_16_S40
:
6160 case BFIN_BUILTIN_CPLX_MSU_16_S40
:
6161 arg0
= CALL_EXPR_ARG (exp
, 0);
6162 arg1
= CALL_EXPR_ARG (exp
, 1);
6163 arg2
= CALL_EXPR_ARG (exp
, 2);
6164 op0
= expand_normal (arg0
);
6165 op1
= expand_normal (arg1
);
6166 op2
= expand_normal (arg2
);
6167 accvec
= gen_reg_rtx (V2PDImode
);
6168 icode
= CODE_FOR_flag_macv2hi_parts
;
6169 tmode
= insn_data
[icode
].operand
[0].mode
;
6172 || GET_MODE (target
) != V2HImode
6173 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
6174 target
= gen_reg_rtx (tmode
);
6175 if (! register_operand (op1
, GET_MODE (op1
)))
6176 op1
= copy_to_mode_reg (GET_MODE (op1
), op1
);
6177 if (! register_operand (op2
, GET_MODE (op2
)))
6178 op2
= copy_to_mode_reg (GET_MODE (op2
), op2
);
6180 tmp1
= gen_reg_rtx (SImode
);
6181 tmp2
= gen_reg_rtx (SImode
);
6182 emit_insn (gen_ashlsi3 (tmp1
, gen_lowpart (SImode
, op0
), GEN_INT (16)));
6183 emit_move_insn (tmp2
, gen_lowpart (SImode
, op0
));
6184 emit_insn (gen_movstricthi_1 (gen_lowpart (HImode
, tmp2
), const0_rtx
));
6185 emit_insn (gen_load_accumulator_pair (accvec
, tmp1
, tmp2
));
6186 if (fcode
== BFIN_BUILTIN_CPLX_MAC_16
6187 || fcode
== BFIN_BUILTIN_CPLX_MSU_16
)
6188 emit_insn (gen_flag_macv2hi_parts_acconly (accvec
, op1
, op2
, const0_rtx
,
6189 const0_rtx
, const0_rtx
,
6190 const1_rtx
, accvec
, const0_rtx
,
6192 GEN_INT (MACFLAG_W32
)));
6194 emit_insn (gen_flag_macv2hi_parts_acconly (accvec
, op1
, op2
, const0_rtx
,
6195 const0_rtx
, const0_rtx
,
6196 const1_rtx
, accvec
, const0_rtx
,
6198 GEN_INT (MACFLAG_NONE
)));
6199 if (fcode
== BFIN_BUILTIN_CPLX_MAC_16
6200 || fcode
== BFIN_BUILTIN_CPLX_MAC_16_S40
)
6210 emit_insn (gen_flag_macv2hi_parts (target
, op1
, op2
, const1_rtx
,
6211 const1_rtx
, const1_rtx
,
6212 const0_rtx
, accvec
, tmp1
, tmp2
,
6213 GEN_INT (MACFLAG_NONE
), accvec
));
6217 case BFIN_BUILTIN_CPLX_SQU
:
6218 arg0
= CALL_EXPR_ARG (exp
, 0);
6219 op0
= expand_normal (arg0
);
6220 accvec
= gen_reg_rtx (V2PDImode
);
6221 icode
= CODE_FOR_flag_mulv2hi
;
6222 tmp1
= gen_reg_rtx (V2HImode
);
6223 tmp2
= gen_reg_rtx (V2HImode
);
6226 || GET_MODE (target
) != V2HImode
6227 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
6228 target
= gen_reg_rtx (V2HImode
);
6229 if (! register_operand (op0
, GET_MODE (op0
)))
6230 op0
= copy_to_mode_reg (GET_MODE (op0
), op0
);
6232 emit_insn (gen_flag_mulv2hi (tmp1
, op0
, op0
, GEN_INT (MACFLAG_NONE
)));
6234 emit_insn (gen_flag_mulhi_parts (gen_lowpart (HImode
, tmp2
), op0
, op0
,
6235 const0_rtx
, const1_rtx
,
6236 GEN_INT (MACFLAG_NONE
)));
6238 emit_insn (gen_ssaddhi3_high_parts (target
, tmp2
, tmp2
, tmp2
, const0_rtx
,
6240 emit_insn (gen_sssubhi3_low_parts (target
, target
, tmp1
, tmp1
,
6241 const0_rtx
, const1_rtx
));
6249 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
6250 if (d
->code
== fcode
)
6251 return bfin_expand_binop_builtin (d
->icode
, exp
, target
,
6254 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
6255 if (d
->code
== fcode
)
6256 return bfin_expand_unop_builtin (d
->icode
, exp
, target
);
6262 bfin_conditional_register_usage (void)
6264 /* initialize condition code flag register rtx */
6265 bfin_cc_rtx
= gen_rtx_REG (BImode
, REG_CC
);
6266 bfin_rets_rtx
= gen_rtx_REG (Pmode
, REG_RETS
);
6268 call_used_regs
[FDPIC_REGNO
] = 1;
6269 if (!TARGET_FDPIC
&& flag_pic
)
6271 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
6272 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
6276 #undef TARGET_INIT_BUILTINS
6277 #define TARGET_INIT_BUILTINS bfin_init_builtins
6279 #undef TARGET_EXPAND_BUILTIN
6280 #define TARGET_EXPAND_BUILTIN bfin_expand_builtin
6282 #undef TARGET_ASM_GLOBALIZE_LABEL
6283 #define TARGET_ASM_GLOBALIZE_LABEL bfin_globalize_label
6285 #undef TARGET_ASM_FILE_START
6286 #define TARGET_ASM_FILE_START output_file_start
6288 #undef TARGET_ATTRIBUTE_TABLE
6289 #define TARGET_ATTRIBUTE_TABLE bfin_attribute_table
6291 #undef TARGET_COMP_TYPE_ATTRIBUTES
6292 #define TARGET_COMP_TYPE_ATTRIBUTES bfin_comp_type_attributes
6294 #undef TARGET_RTX_COSTS
6295 #define TARGET_RTX_COSTS bfin_rtx_costs
6297 #undef TARGET_ADDRESS_COST
6298 #define TARGET_ADDRESS_COST bfin_address_cost
6300 #undef TARGET_ASM_INTEGER
6301 #define TARGET_ASM_INTEGER bfin_assemble_integer
6303 #undef TARGET_MACHINE_DEPENDENT_REORG
6304 #define TARGET_MACHINE_DEPENDENT_REORG bfin_reorg
6306 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
6307 #define TARGET_FUNCTION_OK_FOR_SIBCALL bfin_function_ok_for_sibcall
6309 #undef TARGET_ASM_OUTPUT_MI_THUNK
6310 #define TARGET_ASM_OUTPUT_MI_THUNK bfin_output_mi_thunk
6311 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
6312 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
6314 #undef TARGET_SCHED_ADJUST_COST
6315 #define TARGET_SCHED_ADJUST_COST bfin_adjust_cost
6317 #undef TARGET_SCHED_ISSUE_RATE
6318 #define TARGET_SCHED_ISSUE_RATE bfin_issue_rate
6320 #undef TARGET_PROMOTE_FUNCTION_MODE
6321 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
6323 #undef TARGET_ARG_PARTIAL_BYTES
6324 #define TARGET_ARG_PARTIAL_BYTES bfin_arg_partial_bytes
6326 #undef TARGET_FUNCTION_ARG
6327 #define TARGET_FUNCTION_ARG bfin_function_arg
6329 #undef TARGET_FUNCTION_ARG_ADVANCE
6330 #define TARGET_FUNCTION_ARG_ADVANCE bfin_function_arg_advance
6332 #undef TARGET_PASS_BY_REFERENCE
6333 #define TARGET_PASS_BY_REFERENCE bfin_pass_by_reference
6335 #undef TARGET_SETUP_INCOMING_VARARGS
6336 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
6338 #undef TARGET_STRUCT_VALUE_RTX
6339 #define TARGET_STRUCT_VALUE_RTX bfin_struct_value_rtx
6341 #undef TARGET_VECTOR_MODE_SUPPORTED_P
6342 #define TARGET_VECTOR_MODE_SUPPORTED_P bfin_vector_mode_supported_p
6344 #undef TARGET_OPTION_OVERRIDE
6345 #define TARGET_OPTION_OVERRIDE bfin_option_override
6347 #undef TARGET_SECONDARY_RELOAD
6348 #define TARGET_SECONDARY_RELOAD bfin_secondary_reload
6350 #undef TARGET_CLASS_LIKELY_SPILLED_P
6351 #define TARGET_CLASS_LIKELY_SPILLED_P bfin_class_likely_spilled_p
6353 #undef TARGET_DELEGITIMIZE_ADDRESS
6354 #define TARGET_DELEGITIMIZE_ADDRESS bfin_delegitimize_address
6356 #undef TARGET_LEGITIMATE_CONSTANT_P
6357 #define TARGET_LEGITIMATE_CONSTANT_P bfin_legitimate_constant_p
6359 #undef TARGET_CANNOT_FORCE_CONST_MEM
6360 #define TARGET_CANNOT_FORCE_CONST_MEM bfin_cannot_force_const_mem
6362 #undef TARGET_RETURN_IN_MEMORY
6363 #define TARGET_RETURN_IN_MEMORY bfin_return_in_memory
6365 #undef TARGET_LEGITIMATE_ADDRESS_P
6366 #define TARGET_LEGITIMATE_ADDRESS_P bfin_legitimate_address_p
6368 #undef TARGET_FRAME_POINTER_REQUIRED
6369 #define TARGET_FRAME_POINTER_REQUIRED bfin_frame_pointer_required
6371 #undef TARGET_CAN_ELIMINATE
6372 #define TARGET_CAN_ELIMINATE bfin_can_eliminate
6374 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6375 #define TARGET_CONDITIONAL_REGISTER_USAGE bfin_conditional_register_usage
6377 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
6378 #define TARGET_ASM_TRAMPOLINE_TEMPLATE bfin_asm_trampoline_template
6379 #undef TARGET_TRAMPOLINE_INIT
6380 #define TARGET_TRAMPOLINE_INIT bfin_trampoline_init
6382 #undef TARGET_EXTRA_LIVE_ON_ENTRY
6383 #define TARGET_EXTRA_LIVE_ON_ENTRY bfin_extra_live_on_entry
6385 /* Passes after sched2 can break the helpful TImode annotations that
6386 haifa-sched puts on every insn. Just do scheduling in reorg. */
6387 #undef TARGET_DELAY_SCHED2
6388 #define TARGET_DELAY_SCHED2 true
6390 /* Variable tracking should be run after all optimizations which
6391 change order of insns. It also needs a valid CFG. */
6392 #undef TARGET_DELAY_VARTRACK
6393 #define TARGET_DELAY_VARTRACK true
6395 struct gcc_target targetm
= TARGET_INITIALIZER
;