1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2017 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "stringpool.h"
39 #include "diagnostic-core.h"
40 #include "conditions.h"
41 #include "insn-attr.h"
44 #include "stor-layout.h"
50 #include "tm-constrs.h"
53 /* This file should be included last. */
54 #include "target-def.h"
56 /* Usable when we have an amount to add or subtract, and want the
57 optimal size of the insn. */
58 #define ADDITIVE_SIZE_MODIFIER(size) \
59 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
61 #define LOSE_AND_RETURN(msgid, x) \
64 cris_operand_lossage (msgid, x); \
68 enum cris_retinsn_type
69 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
71 /* Per-function machine data. */
72 struct GTY(()) machine_function
74 int needs_return_address_on_stack
;
76 /* This is the number of registers we save in the prologue due to
80 enum cris_retinsn_type return_type
;
83 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
85 static char cris_output_insn_is_bound
= 0;
87 /* In code for output macros, this is how we know whether e.g. constant
88 goes in code or in a static initializer. */
89 static int in_code
= 0;
91 /* Fix for reg_overlap_mentioned_p. */
92 static int cris_reg_overlap_mentioned_p (rtx
, rtx
);
94 static machine_mode
cris_promote_function_mode (const_tree
, machine_mode
,
95 int *, const_tree
, int);
97 static unsigned int cris_atomic_align_for_mode (machine_mode
);
99 static void cris_print_base (rtx
, FILE *);
101 static void cris_print_index (rtx
, FILE *);
103 static void cris_output_addr_const (FILE *, rtx
);
105 static struct machine_function
* cris_init_machine_status (void);
107 static rtx
cris_struct_value_rtx (tree
, int);
109 static void cris_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
110 tree type
, int *, int);
112 static int cris_initial_frame_pointer_offset (void);
114 static void cris_operand_lossage (const char *, rtx
);
116 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
118 static void cris_print_operand (FILE *, rtx
, int);
120 static void cris_print_operand_address (FILE *, machine_mode
, rtx
);
122 static bool cris_print_operand_punct_valid_p (unsigned char code
);
124 static bool cris_output_addr_const_extra (FILE *, rtx
);
126 static void cris_conditional_register_usage (void);
128 static void cris_asm_output_mi_thunk
129 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
131 static void cris_file_start (void);
132 static void cris_init_libfuncs (void);
134 static reg_class_t
cris_preferred_reload_class (rtx
, reg_class_t
);
136 static int cris_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
137 static int cris_memory_move_cost (machine_mode
, reg_class_t
, bool);
138 static bool cris_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
139 static int cris_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
140 static bool cris_pass_by_reference (cumulative_args_t
, machine_mode
,
142 static int cris_arg_partial_bytes (cumulative_args_t
, machine_mode
,
144 static rtx
cris_function_arg (cumulative_args_t
, machine_mode
,
146 static rtx
cris_function_incoming_arg (cumulative_args_t
,
147 machine_mode
, const_tree
, bool);
148 static void cris_function_arg_advance (cumulative_args_t
, machine_mode
,
150 static rtx_insn
*cris_md_asm_adjust (vec
<rtx
> &, vec
<rtx
> &,
152 vec
<rtx
> &, HARD_REG_SET
&);
153 static bool cris_cannot_force_const_mem (machine_mode
, rtx
);
155 static void cris_option_override (void);
157 static bool cris_frame_pointer_required (void);
159 static void cris_asm_trampoline_template (FILE *);
160 static void cris_trampoline_init (rtx
, tree
, rtx
);
162 static rtx
cris_function_value(const_tree
, const_tree
, bool);
163 static rtx
cris_libcall_value (machine_mode
, const_rtx
);
164 static bool cris_function_value_regno_p (const unsigned int);
165 static void cris_file_end (void);
167 /* This is the parsed result of the "-max-stack-stackframe=" option. If
168 it (still) is zero, then there was no such option given. */
169 int cris_max_stackframe
= 0;
171 /* This is the parsed result of the "-march=" option, if given. */
172 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
174 #undef TARGET_ASM_ALIGNED_HI_OP
175 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
176 #undef TARGET_ASM_ALIGNED_SI_OP
177 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
178 #undef TARGET_ASM_ALIGNED_DI_OP
179 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
181 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
182 available in ELF. These "normal" pseudos do not have any alignment
183 constraints or side-effects. */
184 #undef TARGET_ASM_UNALIGNED_HI_OP
185 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
187 #undef TARGET_ASM_UNALIGNED_SI_OP
188 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
190 #undef TARGET_ASM_UNALIGNED_DI_OP
191 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
193 #undef TARGET_PRINT_OPERAND
194 #define TARGET_PRINT_OPERAND cris_print_operand
195 #undef TARGET_PRINT_OPERAND_ADDRESS
196 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
197 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
198 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
199 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
200 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra
202 #undef TARGET_CONDITIONAL_REGISTER_USAGE
203 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
205 #undef TARGET_ASM_OUTPUT_MI_THUNK
206 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
207 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
208 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
210 #undef TARGET_ASM_FILE_START
211 #define TARGET_ASM_FILE_START cris_file_start
212 #undef TARGET_ASM_FILE_END
213 #define TARGET_ASM_FILE_END cris_file_end
215 #undef TARGET_INIT_LIBFUNCS
216 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
219 #define TARGET_LRA_P hook_bool_void_false
221 #undef TARGET_LEGITIMATE_ADDRESS_P
222 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
224 #undef TARGET_LEGITIMATE_CONSTANT_P
225 #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p
227 #undef TARGET_PREFERRED_RELOAD_CLASS
228 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
230 #undef TARGET_REGISTER_MOVE_COST
231 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
232 #undef TARGET_MEMORY_MOVE_COST
233 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
234 #undef TARGET_RTX_COSTS
235 #define TARGET_RTX_COSTS cris_rtx_costs
236 #undef TARGET_ADDRESS_COST
237 #define TARGET_ADDRESS_COST cris_address_cost
239 #undef TARGET_PROMOTE_FUNCTION_MODE
240 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
242 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
243 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
245 #undef TARGET_STRUCT_VALUE_RTX
246 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
247 #undef TARGET_SETUP_INCOMING_VARARGS
248 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
249 #undef TARGET_PASS_BY_REFERENCE
250 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
251 #undef TARGET_ARG_PARTIAL_BYTES
252 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
253 #undef TARGET_FUNCTION_ARG
254 #define TARGET_FUNCTION_ARG cris_function_arg
255 #undef TARGET_FUNCTION_INCOMING_ARG
256 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
257 #undef TARGET_FUNCTION_ARG_ADVANCE
258 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
259 #undef TARGET_MD_ASM_ADJUST
260 #define TARGET_MD_ASM_ADJUST cris_md_asm_adjust
262 #undef TARGET_CANNOT_FORCE_CONST_MEM
263 #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem
265 #undef TARGET_FRAME_POINTER_REQUIRED
266 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
268 #undef TARGET_OPTION_OVERRIDE
269 #define TARGET_OPTION_OVERRIDE cris_option_override
271 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
272 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
273 #undef TARGET_TRAMPOLINE_INIT
274 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
276 #undef TARGET_FUNCTION_VALUE
277 #define TARGET_FUNCTION_VALUE cris_function_value
278 #undef TARGET_LIBCALL_VALUE
279 #define TARGET_LIBCALL_VALUE cris_libcall_value
280 #undef TARGET_FUNCTION_VALUE_REGNO_P
281 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
283 struct gcc_target targetm
= TARGET_INITIALIZER
;
285 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
288 cris_movem_load_rest_p (rtx op
, int offs
)
290 unsigned int reg_count
= XVECLEN (op
, 0) - offs
;
296 unsigned int regno
= 0;
298 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
299 other than (MEM reg). */
301 || GET_CODE (XVECEXP (op
, 0, offs
)) != SET
302 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
)))
303 || !MEM_P (SET_SRC (XVECEXP (op
, 0, offs
))))
306 /* Check a possible post-inc indicator. */
307 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, offs
+ 1))) == PLUS
)
309 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 0);
310 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 1);
316 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
317 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
318 || !CONST_INT_P (inc
)
319 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
329 regno
= reg_count
- 1;
332 elt
= XVECEXP (op
, 0, offs
);
333 src_addr
= XEXP (SET_SRC (elt
), 0);
335 if (GET_CODE (elt
) != SET
336 || !REG_P (SET_DEST (elt
))
337 || GET_MODE (SET_DEST (elt
)) != SImode
338 || REGNO (SET_DEST (elt
)) != regno
339 || !MEM_P (SET_SRC (elt
))
340 || GET_MODE (SET_SRC (elt
)) != SImode
341 || !memory_address_p (SImode
, src_addr
))
344 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
346 rtx elt
= XVECEXP (op
, 0, i
);
349 if (GET_CODE (elt
) != SET
350 || !REG_P (SET_DEST (elt
))
351 || GET_MODE (SET_DEST (elt
)) != SImode
352 || REGNO (SET_DEST (elt
)) != regno
353 || !MEM_P (SET_SRC (elt
))
354 || GET_MODE (SET_SRC (elt
)) != SImode
355 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
356 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
357 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
358 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
365 /* Worker function for predicate for the parallel contents in a movem
369 cris_store_multiple_op_p (rtx op
)
371 int reg_count
= XVECLEN (op
, 0);
382 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
383 other than (MEM reg) and (MEM (PLUS reg const)). */
387 elt
= XVECEXP (op
, 0, 0);
389 if (GET_CODE (elt
) != SET
)
392 dest
= SET_DEST (elt
);
394 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
397 dest_addr
= XEXP (dest
, 0);
399 /* Check a possible post-inc indicator. */
400 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
402 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
403 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
409 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
410 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
411 || !CONST_INT_P (inc
)
412 /* Support increment by number of registers, and by the offset
413 of the destination, if it has the form (MEM (PLUS reg
415 || !((REG_P (dest_addr
)
416 && REGNO (dest_addr
) == REGNO (reg
)
417 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
418 || (GET_CODE (dest_addr
) == PLUS
419 && REG_P (XEXP (dest_addr
, 0))
420 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
421 && CONST_INT_P (XEXP (dest_addr
, 1))
422 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
433 regno
= reg_count
- 1;
436 if (GET_CODE (elt
) != SET
437 || !REG_P (SET_SRC (elt
))
438 || GET_MODE (SET_SRC (elt
)) != SImode
439 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
440 || !MEM_P (SET_DEST (elt
))
441 || GET_MODE (SET_DEST (elt
)) != SImode
)
444 if (REG_P (dest_addr
))
446 dest_base
= dest_addr
;
449 else if (GET_CODE (dest_addr
) == PLUS
450 && REG_P (XEXP (dest_addr
, 0))
451 && CONST_INT_P (XEXP (dest_addr
, 1)))
453 dest_base
= XEXP (dest_addr
, 0);
454 offset
= INTVAL (XEXP (dest_addr
, 1));
459 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
461 rtx elt
= XVECEXP (op
, 0, i
);
464 if (GET_CODE (elt
) != SET
465 || !REG_P (SET_SRC (elt
))
466 || GET_MODE (SET_SRC (elt
)) != SImode
467 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
468 || !MEM_P (SET_DEST (elt
))
469 || GET_MODE (SET_DEST (elt
)) != SImode
470 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
471 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
472 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
473 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
480 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
483 cris_conditional_register_usage (void)
485 /* FIXME: This isn't nice. We should be able to use that register for
486 something else if the PIC table isn't needed. */
488 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
]
489 = call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
491 /* Allow use of ACR (PC in pre-V32) and tweak order. */
494 static const int reg_alloc_order_v32
[] = REG_ALLOC_ORDER_V32
;
497 fixed_regs
[CRIS_ACR_REGNUM
] = 0;
500 i
< sizeof (reg_alloc_order_v32
)/sizeof (reg_alloc_order_v32
[0]);
502 reg_alloc_order
[i
] = reg_alloc_order_v32
[i
];
505 if (TARGET_HAS_MUL_INSNS
)
506 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
508 /* On early versions, we must use the 16-bit condition-code register,
509 which has another name. */
510 if (cris_cpu_version
< 8)
511 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
514 /* Return crtl->uses_pic_offset_table. For use in cris.md,
515 since some generated files do not include function.h. */
518 cris_cfun_uses_pic_table (void)
520 return crtl
->uses_pic_offset_table
;
523 /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM.
524 We can't put PIC addresses in the constant pool, not even the ones that
525 can be reached as pc-relative as we can't tell when or how to do that. */
528 cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
530 enum cris_symbol_type t
= cris_symbol_type_of (x
);
534 || t
== cris_got_symbol
535 || t
== cris_rel_symbol
;
538 /* Given an rtx, return the text string corresponding to the CODE of X.
539 Intended for use in the assembly language output section of a
545 cris_output_insn_is_bound
= 0;
546 switch (GET_CODE (x
))
555 /* This function is for retrieving a part of an instruction name for
556 an operator, for immediate output. If that ever happens for
557 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
559 internal_error ("MULT case in cris_op_str");
587 /* Used to control the sign/zero-extend character for the 'E' modifier.
589 cris_output_insn_is_bound
= 1;
593 return "Unknown operator";
597 /* Emit an error message when we're in an asm, and a fatal error for
598 "normal" insns. Formatted output isn't easily implemented, since we
599 use output_operand_lossage to output the actual message and handle the
600 categorization of the error. */
603 cris_operand_lossage (const char *msgid
, rtx op
)
606 output_operand_lossage ("%s", msgid
);
609 /* Print an index part of an address to file. */
612 cris_print_index (rtx index
, FILE *file
)
614 /* Make the index "additive" unless we'll output a negative number, in
615 which case the sign character is free (as in free beer). */
616 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
620 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
621 else if (CRIS_CONSTANT_P (index
))
622 cris_output_addr_const (file
, index
);
623 else if (GET_CODE (index
) == MULT
)
625 fprintf (file
, "$%s.",
626 reg_names
[REGNO (XEXP (index
, 0))]);
628 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
630 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
632 rtx inner
= XEXP (index
, 0);
633 rtx inner_inner
= XEXP (inner
, 0);
635 if (GET_CODE (inner_inner
) == POST_INC
)
637 fprintf (file
, "[$%s+].",
638 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
639 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
643 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
645 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
648 else if (MEM_P (index
))
650 rtx inner
= XEXP (index
, 0);
651 if (GET_CODE (inner
) == POST_INC
)
652 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
654 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
657 cris_operand_lossage ("unexpected index-type in cris_print_index",
661 /* Print a base rtx of an address to file. */
664 cris_print_base (rtx base
, FILE *file
)
667 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
668 else if (GET_CODE (base
) == POST_INC
)
670 gcc_assert (REGNO (XEXP (base
, 0)) != CRIS_ACR_REGNUM
);
671 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
674 cris_operand_lossage ("unexpected base-type in cris_print_base",
678 /* Usable as a guard in expressions. */
681 cris_fatal (char *arg
)
683 internal_error (arg
);
685 /* We'll never get here; this is just to appease compilers. */
689 /* Return nonzero if REGNO is an ordinary register that *needs* to be
690 saved together with other registers, possibly by a MOVEM instruction,
691 or is saved for target-independent reasons. There may be
692 target-dependent reasons to save the register anyway; this is just a
693 wrapper for a complicated conditional. */
696 cris_reg_saved_in_regsave_area (unsigned int regno
, bool got_really_used
)
699 (((df_regs_ever_live_p (regno
)
700 && !call_used_regs
[regno
])
701 || (regno
== PIC_OFFSET_TABLE_REGNUM
703 /* It is saved anyway, if there would be a gap. */
705 && df_regs_ever_live_p (regno
+ 1)
706 && !call_used_regs
[regno
+ 1]))))
707 && (regno
!= FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
708 && regno
!= CRIS_SRP_REGNUM
)
709 || (crtl
->calls_eh_return
710 && (regno
== EH_RETURN_DATA_REGNO (0)
711 || regno
== EH_RETURN_DATA_REGNO (1)
712 || regno
== EH_RETURN_DATA_REGNO (2)
713 || regno
== EH_RETURN_DATA_REGNO (3)));
716 /* The PRINT_OPERAND worker. */
719 cris_print_operand (FILE *file
, rtx x
, int code
)
723 /* Size-strings corresponding to MULT expressions. */
724 static const char *const mults
[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
726 /* New code entries should just be added to the switch below. If
727 handling is finished, just return. If handling was just a
728 modification of the operand, the modified operand should be put in
729 "operand", and then do a break to let default handling
730 (zero-modifier) output the operand. */
735 /* Print the unsigned supplied integer as if it were signed
736 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
737 if (!satisfies_constraint_O (x
))
738 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
739 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
740 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
744 /* Print assembler code for operator. */
745 fprintf (file
, "%s", cris_op_str (operand
));
750 /* A movem modifier working on a parallel; output the register
754 if (GET_CODE (x
) != PARALLEL
)
755 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
757 /* The second item can be (set reg (plus reg const)) to denote a
760 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
762 : XVECLEN (x
, 0) - 1);
764 fprintf (file
, "$%s", reg_names
[regno
]);
770 /* A similar movem modifier; output the memory operand. */
773 if (GET_CODE (x
) != PARALLEL
)
774 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
776 /* The lowest mem operand is in the first item, but perhaps it
777 needs to be output as postincremented. */
778 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
779 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
780 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
782 /* The second item can be a (set reg (plus reg const)) to denote
784 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
786 /* It's a post-increment, if the address is a naked (reg). */
788 addr
= gen_rtx_POST_INC (SImode
, addr
);
791 /* Otherwise, it's a side-effect; RN=RN+M. */
792 fprintf (file
, "[$%s=$%s%s%d]",
793 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
794 reg_names
[REGNO (XEXP (addr
, 0))],
795 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
796 (int) INTVAL (XEXP (addr
, 1)));
800 output_address (VOIDmode
, addr
);
805 /* Adjust a power of two to its log2. */
806 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
807 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
808 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
812 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
813 respectively. This modifier also terminates the inhibiting
814 effects of the 'x' modifier. */
815 cris_output_insn_is_bound
= 0;
816 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
820 if (INTVAL (x
) <= 255)
822 else if (INTVAL (x
) <= 65535)
832 /* For a non-integer, print the size of the operand. */
833 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
834 ? 'd' : GET_MODE (x
) == HImode
? 'w'
835 : GET_MODE (x
) == QImode
? 'b'
836 /* If none of the above, emit an erroneous size letter. */
842 /* Const_int: print b for -127 <= x <= 255,
843 w for -32768 <= x <= 65535, else die. */
845 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
846 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
847 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
851 /* If this is a GOT-symbol, print the size-letter corresponding to
852 -fpic/-fPIC. For everything else, print "d". */
854 && GET_CODE (x
) == CONST
855 && GET_CODE (XEXP (x
, 0)) == UNSPEC
856 && XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
861 /* Output a 'nop' if there's nothing for the delay slot.
862 This method stolen from the sparc files. */
863 if (dbr_sequence_length () == 0)
864 fputs ("\n\tnop", file
);
868 /* Output directive for alignment padded with "nop" insns.
869 Optimizing for size, it's plain 4-byte alignment, otherwise we
870 align the section to a cache-line (32 bytes) and skip at max 2
871 bytes, i.e. we skip if it's the last insn on a cache-line. The
872 latter is faster by a small amount (for two test-programs 99.6%
873 and 99.9%) and larger by a small amount (ditto 100.1% and
874 100.2%). This is supposed to be the simplest yet performance-
875 wise least intrusive way to make sure the immediately following
876 (supposed) muls/mulu insn isn't located at the end of a
880 ? ".p2alignw 2,0x050f\n\t"
881 : ".p2alignw 5,0x050f,2\n\t", file
);
885 /* The PIC register. */
887 internal_error ("invalid use of ':' modifier");
888 fprintf (file
, "$%s", reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
892 /* Print high (most significant) part of something. */
893 switch (GET_CODE (operand
))
896 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
897 value is kept here, and so may be other than 0 or -1. */
898 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
899 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
903 /* High part of a long long constant. */
904 if (GET_MODE (operand
) == VOIDmode
)
906 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
910 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
913 /* Print reg + 1. Check that there's not an attempt to print
914 high-parts of registers like stack-pointer or higher, except
915 for SRP (where the "high part" is MOF). */
916 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
917 && (REGNO (operand
) != CRIS_SRP_REGNUM
918 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
919 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
920 LOSE_AND_RETURN ("bad register", operand
);
921 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
925 /* Adjust memory address to high part. */
927 rtx adj_mem
= operand
;
929 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
931 /* Adjust so we can use two SImode in DImode.
932 Calling adj_offsettable_operand will make sure it is an
933 offsettable address. Don't do this for a postincrement
934 though; it should remain as it was. */
935 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
937 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
939 output_address (VOIDmode
, XEXP (adj_mem
, 0));
944 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
948 /* Strip the MEM expression. */
949 operand
= XEXP (operand
, 0);
953 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
954 iterators and attributes in cris.md to avoid the need for %x
955 and %E (and %e) and state passed between those modifiers. */
956 cris_output_insn_is_bound
= 0;
959 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
960 cris_output_insn_is_bound is nonzero. */
961 if (GET_CODE (operand
) != SIGN_EXTEND
962 && GET_CODE (operand
) != ZERO_EXTEND
963 && !CONST_INT_P (operand
))
964 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
966 if (cris_output_insn_is_bound
)
968 cris_output_insn_is_bound
= 0;
972 putc (GET_CODE (operand
) == SIGN_EXTEND
973 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
978 /* Print the size letter of the inner element. We can do it by
979 calling ourselves with the 's' modifier. */
980 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
981 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
982 cris_print_operand (file
, XEXP (operand
, 0), 's');
986 /* Print the least significant part of operand. */
987 if (GET_CODE (operand
) == CONST_DOUBLE
)
989 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
992 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
994 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
995 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
998 /* Otherwise the least significant part equals the normal part,
999 so handle it normally. */
1003 /* When emitting an add for the high part of a DImode constant, we
1004 want to use addq for 0 and adds.w for -1. */
1005 if (!CONST_INT_P (operand
))
1006 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
1007 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
1011 /* For const_int operands, print the additive mnemonic and the
1012 modified operand (byte-sized operands don't save anything):
1013 N=MIN_INT..-65536: add.d N
1014 -65535..-64: subu.w -N
1018 65536..MAX_INT: add.d N.
1019 (Emitted mnemonics are capitalized to simplify testing.)
1020 For anything else (N.B: only register is valid), print "add.d". */
1021 if (REG_P (operand
))
1023 fprintf (file
, "Add.d ");
1025 /* Deal with printing the operand by dropping through to the
1032 gcc_assert (CONST_INT_P (operand
));
1034 val
= INTVAL (operand
);
1035 if (!IN_RANGE (val
, -65535, 65535))
1036 fprintf (file
, "Add.d %d", val
);
1037 else if (val
<= -64)
1038 fprintf (file
, "Subu.w %d", -val
);
1040 fprintf (file
, "Subq %d", -val
);
1042 fprintf (file
, "Addq %d", val
);
1043 else if (val
<= 65535)
1044 fprintf (file
, "Addu.w %d", val
);
1050 /* If the operand is an integer -31..31, print "q" else ".d". */
1051 if (CONST_INT_P (operand
) && IN_RANGE (INTVAL (operand
), -31, 31))
1052 fprintf (file
, "q");
1054 fprintf (file
, ".d");
1058 /* If this is a GOT symbol, force it to be emitted as :GOT and
1059 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
1060 Avoid making this too much of a special case. */
1061 if (flag_pic
== 1 && CRIS_CONSTANT_P (operand
))
1063 int flag_pic_save
= flag_pic
;
1066 cris_output_addr_const (file
, operand
);
1067 flag_pic
= flag_pic_save
;
1073 /* When emitting an sub for the high part of a DImode constant, we
1074 want to use subq for 0 and subs.w for -1. */
1075 if (!CONST_INT_P (operand
))
1076 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1077 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1081 /* Print the operand as the index-part of an address.
1082 Easiest way out is to use cris_print_index. */
1083 cris_print_index (operand
, file
);
1087 /* Print the size letter for an operand to a MULT, which must be a
1088 const_int with a suitable value. */
1089 if (!CONST_INT_P (operand
) || INTVAL (operand
) > 4)
1090 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1091 fprintf (file
, "%s", mults
[INTVAL (operand
)]);
1095 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1097 && GET_CODE (operand
) == CONST
1098 && GET_CODE (XEXP (operand
, 0)) == UNSPEC
1099 && XINT (XEXP (operand
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
1100 fprintf (file
, "u.w");
1102 fprintf (file
, ".d");
1106 /* No code, print as usual. */
1110 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1113 /* Print an operand as without a modifier letter. */
1114 switch (GET_CODE (operand
))
1117 if (REGNO (operand
) > 15
1118 && REGNO (operand
) != CRIS_MOF_REGNUM
1119 && REGNO (operand
) != CRIS_SRP_REGNUM
1120 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1121 internal_error ("internal error: bad register: %d", REGNO (operand
));
1122 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1126 output_address (GET_MODE (operand
), XEXP (operand
, 0));
1130 if (GET_MODE (operand
) == VOIDmode
)
1131 /* A long long constant. */
1132 output_addr_const (file
, operand
);
1135 /* Only single precision is allowed as plain operands the
1139 /* FIXME: Perhaps check overflow of the "single". */
1140 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operand
), l
);
1142 fprintf (file
, "0x%lx", l
);
1149 cris_output_addr_const (file
, operand
);
1155 /* For a (MULT (reg X) const_int) we output "rX.S". */
1156 int i
= CONST_INT_P (XEXP (operand
, 1))
1157 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1158 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1159 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1162 || (!CONST_INT_P (XEXP (operand
, 0))
1163 && !CONST_INT_P (XEXP (operand
, 1))))
1164 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1166 cris_print_base (reg
, file
);
1167 fprintf (file
, ".%c",
1168 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1170 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1176 /* No need to handle all strange variants, let output_addr_const
1178 if (CRIS_CONSTANT_P (operand
))
1180 cris_output_addr_const (file
, operand
);
1184 LOSE_AND_RETURN ("unexpected operand", x
);
1189 cris_print_operand_punct_valid_p (unsigned char code
)
1191 return (code
== '#' || code
== '!' || code
== ':');
1194 /* The PRINT_OPERAND_ADDRESS worker. */
1197 cris_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
1199 /* All these were inside MEM:s so output indirection characters. */
1202 if (CONSTANT_ADDRESS_P (x
))
1203 cris_output_addr_const (file
, x
);
1204 else if (cris_base_or_autoincr_p (x
, true))
1205 cris_print_base (x
, file
);
1206 else if (GET_CODE (x
) == PLUS
)
1212 if (cris_base_p (x1
, true))
1214 cris_print_base (x1
, file
);
1215 cris_print_index (x2
, file
);
1217 else if (cris_base_p (x2
, true))
1219 cris_print_base (x2
, file
);
1220 cris_print_index (x1
, file
);
1223 LOSE_AND_RETURN ("unrecognized address", x
);
1227 /* A DIP. Output more indirection characters. */
1229 cris_print_base (XEXP (x
, 0), file
);
1233 LOSE_AND_RETURN ("unrecognized address", x
);
1238 /* The RETURN_ADDR_RTX worker.
1239 We mark that the return address is used, either by EH or
1240 __builtin_return_address, for use by the function prologue and
1241 epilogue. FIXME: This isn't optimal; we just use the mark in the
1242 prologue and epilogue to say that the return address is to be stored
1243 in the stack frame. We could return SRP for leaf-functions and use the
1244 initial-value machinery. */
1247 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1249 cfun
->machine
->needs_return_address_on_stack
= 1;
1251 /* The return-address is stored just above the saved frame-pointer (if
1252 present). Apparently we can't eliminate from the frame-pointer in
1253 that direction, so use the incoming args (maybe pretended) pointer. */
1255 ? gen_rtx_MEM (Pmode
, plus_constant (Pmode
, virtual_incoming_args_rtx
, -4))
1259 /* Accessor used in cris.md:return because cfun->machine isn't available
1263 cris_return_address_on_stack (void)
1265 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1266 || cfun
->machine
->needs_return_address_on_stack
;
1269 /* Accessor used in cris.md:return because cfun->machine isn't available
1273 cris_return_address_on_stack_for_return (void)
1275 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1276 : cris_return_address_on_stack ();
1279 /* This handles FP -> SP elimination offset. */
1282 cris_initial_frame_pointer_offset (void)
1286 /* Initial offset is 0 if we don't have a frame pointer. */
1288 bool got_really_used
= false;
1290 if (crtl
->uses_pic_offset_table
)
1292 push_topmost_sequence ();
1294 = reg_used_between_p (pic_offset_table_rtx
, get_insns (),
1296 pop_topmost_sequence ();
1299 /* And 4 for each register pushed. */
1300 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1301 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1304 /* And then, last, we add the locals allocated. */
1305 offs
+= get_frame_size ();
1307 /* And more; the accumulated args size. */
1308 offs
+= crtl
->outgoing_args_size
;
1310 /* Then round it off, in case we use aligned stack. */
1311 if (TARGET_STACK_ALIGN
)
1312 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1317 /* The INITIAL_ELIMINATION_OFFSET worker.
1318 Calculate the difference between imaginary registers such as frame
1319 pointer and the stack pointer. Used to eliminate the frame pointer
1320 and imaginary arg pointer. */
1323 cris_initial_elimination_offset (int fromreg
, int toreg
)
1326 = cris_initial_frame_pointer_offset ();
1328 /* We should be able to use regs_ever_live and related prologue
1329 information here, or alpha should not as well. */
1330 bool return_address_on_stack
= cris_return_address_on_stack ();
1332 /* Here we act as if the frame-pointer were needed. */
1333 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1335 if (fromreg
== ARG_POINTER_REGNUM
1336 && toreg
== FRAME_POINTER_REGNUM
)
1337 return ap_fp_offset
;
1339 /* Between the frame pointer and the stack are only "normal" stack
1340 variables and saved registers. */
1341 if (fromreg
== FRAME_POINTER_REGNUM
1342 && toreg
== STACK_POINTER_REGNUM
)
1343 return fp_sp_offset
;
1345 /* We need to balance out the frame pointer here. */
1346 if (fromreg
== ARG_POINTER_REGNUM
1347 && toreg
== STACK_POINTER_REGNUM
)
1348 return ap_fp_offset
+ fp_sp_offset
- 4;
1353 /* Nonzero if X is a hard reg that can be used as an index. */
1355 reg_ok_for_base_p (const_rtx x
, bool strict
)
1357 return ((! strict
&& ! HARD_REGISTER_P (x
))
1358 || REGNO_OK_FOR_BASE_P (REGNO (x
)));
1361 /* Nonzero if X is a hard reg that can be used as an index. */
1363 reg_ok_for_index_p (const_rtx x
, bool strict
)
1365 return reg_ok_for_base_p (x
, strict
);
1368 /* No symbol can be used as an index (or more correct, as a base) together
1369 with a register with PIC; the PIC register must be there. */
1372 cris_constant_index_p (const_rtx x
)
1374 return (CRIS_CONSTANT_P (x
) && (!flag_pic
|| cris_valid_pic_const (x
, true)));
1377 /* True if X is a valid base register. */
1380 cris_base_p (const_rtx x
, bool strict
)
1382 return (REG_P (x
) && reg_ok_for_base_p (x
, strict
));
1385 /* True if X is a valid index register. */
1388 cris_index_p (const_rtx x
, bool strict
)
1390 return (REG_P (x
) && reg_ok_for_index_p (x
, strict
));
1393 /* True if X is a valid base register with or without autoincrement. */
1396 cris_base_or_autoincr_p (const_rtx x
, bool strict
)
1398 return (cris_base_p (x
, strict
)
1399 || (GET_CODE (x
) == POST_INC
1400 && cris_base_p (XEXP (x
, 0), strict
)
1401 && REGNO (XEXP (x
, 0)) != CRIS_ACR_REGNUM
));
1404 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1407 cris_bdap_index_p (const_rtx x
, bool strict
)
1410 && GET_MODE (x
) == SImode
1411 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1412 || (GET_CODE (x
) == SIGN_EXTEND
1413 && MEM_P (XEXP (x
, 0))
1414 && (GET_MODE (XEXP (x
, 0)) == HImode
1415 || GET_MODE (XEXP (x
, 0)) == QImode
)
1416 && cris_base_or_autoincr_p (XEXP (XEXP (x
, 0), 0), strict
)));
1419 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1422 cris_biap_index_p (const_rtx x
, bool strict
)
1424 return (cris_index_p (x
, strict
)
1425 || (GET_CODE (x
) == MULT
1426 && cris_index_p (XEXP (x
, 0), strict
)
1427 && cris_scale_int_operand (XEXP (x
, 1), VOIDmode
)));
1430 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P.
1432 A PIC operand looks like a normal symbol here. At output we dress it
1433 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local
1434 symbol) so we exclude all addressing modes where we can't replace a
1435 plain "symbol" with that. A global PIC symbol does not fit anywhere
1436 here (but is thankfully a general_operand in itself). A local PIC
1437 symbol is valid for the plain "symbol + offset" case. */
1440 cris_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1444 if (cris_base_or_autoincr_p (x
, strict
))
1446 else if (TARGET_V32
)
1447 /* Nothing else is valid then. */
1449 else if (cris_constant_index_p (x
))
1452 else if (GET_CODE (x
) == PLUS
)
1457 if ((cris_base_p (x1
, strict
) && cris_constant_index_p (x2
))
1458 || (cris_base_p (x2
, strict
) && cris_constant_index_p (x1
))
1459 /* BDAP Rs[+], Rd. */
1460 || (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1461 && ((cris_base_p (x1
, strict
)
1462 && cris_bdap_index_p (x2
, strict
))
1463 || (cris_base_p (x2
, strict
)
1464 && cris_bdap_index_p (x1
, strict
))
1466 || (cris_base_p (x1
, strict
)
1467 && cris_biap_index_p (x2
, strict
))
1468 || (cris_base_p (x2
, strict
)
1469 && cris_biap_index_p (x1
, strict
)))))
1474 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1475 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1476 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1483 /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle
1484 PIC constants that aren't legitimized. FIXME: there used to be a
1485 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle
1486 PIC constants, but no more (4.7 era); testcase: glibc init-first.c.
1487 While that may be seen as a bug, that guarantee seems a wart by design,
1488 so don't bother; fix the documentation instead. */
1491 cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1493 enum cris_symbol_type t
;
1496 return LEGITIMATE_PIC_OPERAND_P (x
);
1498 t
= cris_symbol_type_of (x
);
1502 || t
== cris_offsettable_symbol
1503 || t
== cris_unspec
;
1506 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1509 cris_reload_address_legitimized (rtx x
,
1510 machine_mode mode ATTRIBUTE_UNUSED
,
1511 int opnum ATTRIBUTE_UNUSED
,
1513 int ind_levels ATTRIBUTE_UNUSED
)
1515 enum reload_type type
= (enum reload_type
) itype
;
1519 if (GET_CODE (x
) != PLUS
)
1527 op1p
= &XEXP (x
, 1);
1532 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1534 rtx op00
= XEXP (op0
, 0);
1535 rtx op000
= XEXP (op00
, 0);
1536 rtx
*op000p
= &XEXP (op00
, 0);
1538 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1540 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1542 bool something_reloaded
= false;
1544 if (GET_CODE (op000
) == POST_INC
1545 && REG_P (XEXP (op000
, 0))
1546 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1547 /* No, this gets too complicated and is too rare to care
1548 about trying to improve on the general code Here.
1549 As the return-value is an all-or-nothing indicator, we
1550 punt on the other register too. */
1554 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1556 /* The address of the inner mem is a pseudo or wrong
1557 reg: reload that. */
1558 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1559 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1560 something_reloaded
= true;
1563 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1565 /* Base register is a pseudo or wrong reg: reload it. */
1566 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1567 GET_MODE (x
), VOIDmode
, 0, 0,
1569 something_reloaded
= true;
1572 gcc_assert (something_reloaded
);
1582 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1584 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1585 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1586 out a constant into the constant pool, we will trap this case and
1587 return something a bit more sane. FIXME: Check if this is a bug.
1588 Beware that we must not "override" classes that can be specified as
1589 constraint letters, or else asm operands using them will fail when
1590 they need to be reloaded. FIXME: Investigate whether that constitutes
1594 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
1596 if (rclass
!= ACR_REGS
1597 && rclass
!= MOF_REGS
1598 && rclass
!= MOF_SRP_REGS
1599 && rclass
!= SRP_REGS
1600 && rclass
!= CC0_REGS
1601 && rclass
!= SPECIAL_REGS
)
1602 return GENNONACR_REGS
;
1607 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1610 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1611 reg_class_t from
, reg_class_t to
)
1613 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1614 their move cost within that class is higher. How about 7? That's 3
1615 for a move to a GENERAL_REGS register, 3 for the move from the
1616 GENERAL_REGS register, and 1 for the increased register pressure.
1617 Also, it's higher than the memory move cost, as it should.
1618 We also do this for ALL_REGS, since we don't want that class to be
1619 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1620 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1621 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1622 used when a GENERAL_REGS should be used, even if there are call-saved
1623 GENERAL_REGS left to allocate. This is because the fall-back when
1624 the most preferred register class isn't available, isn't the next
1625 (or next good) wider register class, but the *most widest* register
1626 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1628 if ((reg_classes_intersect_p (from
, SPECIAL_REGS
)
1629 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1630 || from
== ALL_REGS
|| to
== ALL_REGS
)
1633 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1634 generally prefer GENERAL_REGS. */
1635 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1636 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1642 /* Worker function for TARGET_MEMORY_MOVE_COST.
1644 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1648 cris_memory_move_cost (machine_mode mode
,
1649 reg_class_t rclass ATTRIBUTE_UNUSED
,
1650 bool in ATTRIBUTE_UNUSED
)
1659 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1660 FIXME: this code is historical; its functionality should be
1661 refactored to look at insn attributes and moved to
1662 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1665 cris_normal_notice_update_cc (rtx exp
, rtx insn
)
1667 /* "Normal" means, for:
1672 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1673 register or (v32 and (...) is -32..-1), then CC does not change.
1674 CC_NO_OVERFLOW unless (...) is reg or mem.
1683 (set (reg1) (mem (bdap/biap)))
1684 (set (reg2) (bdap/biap))):
1685 CC is (reg1) and (mem (reg2))
1688 (set (mem (bdap/biap)) (reg1)) [or 0]
1689 (set (reg2) (bdap/biap))):
1692 (where reg and mem includes strict_low_parts variants thereof)
1694 For all others, assume CC is clobbered.
1695 Note that we do not have to care about setting CC_NO_OVERFLOW,
1696 since the overflow flag is set to 0 (i.e. right) for
1697 instructions where it does not have any sane sense, but where
1698 other flags have meanings. (This includes shifts; the carry is
1701 Note that there are other parallel constructs we could match,
1702 but we don't do that yet. */
1704 if (GET_CODE (exp
) == SET
)
1706 /* FIXME: Check when this happens. It looks like we should
1707 actually do a CC_STATUS_INIT here to be safe. */
1708 if (SET_DEST (exp
) == pc_rtx
)
1711 /* Record CC0 changes, so we do not have to output multiple
1713 if (SET_DEST (exp
) == cc0_rtx
)
1717 if (GET_CODE (SET_SRC (exp
)) == COMPARE
1718 && XEXP (SET_SRC (exp
), 1) == const0_rtx
)
1719 cc_status
.value1
= XEXP (SET_SRC (exp
), 0);
1721 cc_status
.value1
= SET_SRC (exp
);
1723 /* Handle flags for the special btstq on one bit. */
1724 if (GET_CODE (cc_status
.value1
) == ZERO_EXTRACT
1725 && XEXP (cc_status
.value1
, 1) == const1_rtx
)
1727 if (CONST_INT_P (XEXP (cc_status
.value1
, 0)))
1729 cc_status
.flags
= CC_INVERTED
;
1731 /* A one-bit btstq. */
1732 cc_status
.flags
= CC_Z_IN_NOT_N
;
1735 else if (GET_CODE (SET_SRC (exp
)) == COMPARE
)
1737 if (!REG_P (XEXP (SET_SRC (exp
), 0))
1738 && XEXP (SET_SRC (exp
), 1) != const0_rtx
)
1739 /* For some reason gcc will not canonicalize compare
1740 operations, reversing the sign by itself if
1741 operands are in wrong order. */
1742 /* (But NOT inverted; eq is still eq.) */
1743 cc_status
.flags
= CC_REVERSED
;
1745 /* This seems to be overlooked by gcc. FIXME: Check again.
1746 FIXME: Is it really safe? */
1748 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp
)),
1749 XEXP (SET_SRC (exp
), 0),
1750 XEXP (SET_SRC (exp
), 1));
1754 else if (REG_P (SET_DEST (exp
))
1755 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1756 && REG_P (XEXP (SET_DEST (exp
), 0))))
1758 /* A register is set; normally CC is set to show that no
1759 test insn is needed. Catch the exceptions. */
1761 /* If not to cc0, then no "set"s in non-natural mode give
1763 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp
))) > UNITS_PER_WORD
1764 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp
))) == MODE_FLOAT
)
1766 /* ... except add:s and sub:s in DImode. */
1767 if (GET_MODE (SET_DEST (exp
)) == DImode
1768 && (GET_CODE (SET_SRC (exp
)) == PLUS
1769 || GET_CODE (SET_SRC (exp
)) == MINUS
))
1772 cc_status
.value1
= SET_DEST (exp
);
1773 cc_status
.value2
= SET_SRC (exp
);
1775 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1777 cc_status
.value2
= 0;
1779 /* Add and sub may set V, which gets us
1780 unoptimizable results in "gt" and "le" condition
1782 cc_status
.flags
|= CC_NO_OVERFLOW
;
1787 else if (SET_SRC (exp
) == const0_rtx
1788 || (REG_P (SET_SRC (exp
))
1789 && (REGNO (SET_SRC (exp
))
1790 > CRIS_LAST_GENERAL_REGISTER
))
1792 && REG_P (SET_DEST (exp
))
1793 && satisfies_constraint_I (SET_SRC (exp
))))
1795 /* There's no CC0 change for this case. Just check
1797 if (cc_status
.value1
1798 && modified_in_p (cc_status
.value1
, insn
))
1799 cc_status
.value1
= 0;
1801 if (cc_status
.value2
1802 && modified_in_p (cc_status
.value2
, insn
))
1803 cc_status
.value2
= 0;
1810 cc_status
.value1
= SET_DEST (exp
);
1811 cc_status
.value2
= SET_SRC (exp
);
1813 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1815 cc_status
.value2
= 0;
1817 /* Some operations may set V, which gets us
1818 unoptimizable results in "gt" and "le" condition
1820 if (GET_CODE (SET_SRC (exp
)) == PLUS
1821 || GET_CODE (SET_SRC (exp
)) == MINUS
1822 || GET_CODE (SET_SRC (exp
)) == NEG
)
1823 cc_status
.flags
|= CC_NO_OVERFLOW
;
1825 /* For V32, nothing with a register destination sets
1826 C and V usefully. */
1828 cc_status
.flags
|= CC_NO_OVERFLOW
;
1833 else if (MEM_P (SET_DEST (exp
))
1834 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1835 && MEM_P (XEXP (SET_DEST (exp
), 0))))
1837 /* When SET to MEM, then CC is not changed (except for
1839 if (cc_status
.value1
1840 && modified_in_p (cc_status
.value1
, insn
))
1841 cc_status
.value1
= 0;
1843 if (cc_status
.value2
1844 && modified_in_p (cc_status
.value2
, insn
))
1845 cc_status
.value2
= 0;
1850 else if (GET_CODE (exp
) == PARALLEL
)
1852 if (GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1853 && GET_CODE (XVECEXP (exp
, 0, 1)) == SET
1854 && REG_P (XEXP (XVECEXP (exp
, 0, 1), 0)))
1856 if (REG_P (XEXP (XVECEXP (exp
, 0, 0), 0))
1857 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 1)))
1861 /* For "move.S [rx=ry+o],rz", say CC reflects
1862 value1=rz and value2=[rx] */
1863 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1865 = replace_equiv_address (XEXP (XVECEXP (exp
, 0, 0), 1),
1866 XEXP (XVECEXP (exp
, 0, 1), 0));
1868 /* Huh? A side-effect cannot change the destination
1870 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1872 internal_error ("internal error: sideeffect-insn affecting main effect");
1874 /* For V32, moves to registers don't set C and V. */
1876 cc_status
.flags
|= CC_NO_OVERFLOW
;
1879 else if ((REG_P (XEXP (XVECEXP (exp
, 0, 0), 1))
1880 || XEXP (XVECEXP (exp
, 0, 0), 1) == const0_rtx
)
1881 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1883 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1884 say flags are not changed, except for overlap. */
1885 if (cc_status
.value1
1886 && modified_in_p (cc_status
.value1
, insn
))
1887 cc_status
.value1
= 0;
1889 if (cc_status
.value2
1890 && modified_in_p (cc_status
.value2
, insn
))
1891 cc_status
.value2
= 0;
1898 /* If we got here, the case wasn't covered by the code above. */
1902 /* This function looks into the pattern to see how this insn affects
1905 Used when to eliminate test insns before a condition-code user,
1906 such as a "scc" insn or a conditional branch. This includes
1907 checking if the entities that cc was updated by, are changed by the
1910 Currently a jumble of the old peek-inside-the-insn and the newer
1911 check-cc-attribute methods. */
1914 cris_notice_update_cc (rtx exp
, rtx_insn
*insn
)
1916 enum attr_cc attrval
= get_attr_cc (insn
);
1918 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1919 to still set CC_REVERSED as below, since that's required by some
1920 compare insn alternatives. (FIXME: GCC should do this virtual
1921 operand swap by itself.) A test-case that may otherwise fail is
1922 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1927 if (attrval
== CC_REV
)
1928 cc_status
.flags
= CC_REVERSED
;
1932 /* Slowly, we're converting to using attributes to control the setting
1933 of condition-code status. */
1937 /* Even if it is "none", a setting may clobber a previous
1938 cc-value, so check. */
1939 if (GET_CODE (exp
) == SET
)
1941 if (cc_status
.value1
1942 && modified_in_p (cc_status
.value1
, insn
))
1943 cc_status
.value1
= 0;
1945 if (cc_status
.value2
1946 && modified_in_p (cc_status
.value2
, insn
))
1947 cc_status
.value2
= 0;
1958 cris_normal_notice_update_cc (exp
, insn
);
1960 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1961 can change bge => bpl and blt => bmi by passing on to the cc0
1962 user that V should not be considered; bgt and ble are taken
1963 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1964 if (attrval
== CC_NOOV32
&& TARGET_V32
)
1965 cc_status
.flags
|= CC_NO_OVERFLOW
;
1969 internal_error ("unknown cc_attr value");
1975 /* Return != 0 if the return sequence for the current function is short,
1976 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1977 registers must be saved, so return 0 then. */
1980 cris_simple_epilogue (void)
1983 unsigned int reglimit
= STACK_POINTER_REGNUM
;
1984 bool got_really_used
= false;
1986 if (! reload_completed
1987 || frame_pointer_needed
1988 || get_frame_size () != 0
1989 || crtl
->args
.pretend_args_size
1991 || crtl
->outgoing_args_size
1992 || crtl
->calls_eh_return
1994 /* If we're not supposed to emit prologue and epilogue, we must
1995 not emit return-type instructions. */
1996 || !TARGET_PROLOGUE_EPILOGUE
)
1999 /* Can't return from stacked return address with v32. */
2000 if (TARGET_V32
&& cris_return_address_on_stack ())
2003 if (crtl
->uses_pic_offset_table
)
2005 push_topmost_sequence ();
2007 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
2008 pop_topmost_sequence ();
2011 /* No simple epilogue if there are saved registers. */
2012 for (regno
= 0; regno
< reglimit
; regno
++)
2013 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2019 /* Emit checking that MEM is aligned for an access in MODE, failing
2020 that, executing a "break 8" (or call to abort, if "break 8" is
2024 cris_emit_trap_for_misalignment (rtx mem
)
2026 rtx addr
, reg
, ok_label
, andop
;
2028 int natural_alignment
;
2029 gcc_assert (MEM_P (mem
));
2031 natural_alignment
= GET_MODE_SIZE (GET_MODE (mem
));
2032 addr
= XEXP (mem
, 0);
2033 reg
= force_reg (Pmode
, addr
);
2034 ok_label
= gen_label_rtx ();
2036 /* This will yield a btstq without a separate register used, usually -
2037 with the exception for PRE hoisting the "and" but not the branch
2038 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
2039 andop
= gen_rtx_AND (Pmode
, reg
, GEN_INT (natural_alignment
- 1));
2040 emit_cmp_and_jump_insns (force_reg (SImode
, andop
), const0_rtx
, EQ
,
2041 NULL_RTX
, Pmode
, 1, ok_label
);
2042 jmp
= get_last_insn ();
2043 gcc_assert (JUMP_P (jmp
));
2045 predict_insn_def (jmp
, PRED_NORETURN
, TAKEN
);
2046 expand_builtin_trap ();
2047 emit_label (ok_label
);
2050 /* Expand a return insn (just one insn) marked as using SRP or stack
2051 slot depending on parameter ON_STACK. */
2054 cris_expand_return (bool on_stack
)
2056 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
2057 tell "ret" from "jump [sp+]". Some, but not all, other parts of
2058 GCC expect just (return) to do the right thing when optimizing, so
2059 we do that until they're fixed. Currently, all return insns in a
2060 function must be the same (not really a limiting factor) so we need
2061 to check that it doesn't change half-way through. */
2062 emit_jump_insn (ret_rtx
);
2064 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
2065 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
2067 cfun
->machine
->return_type
2068 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
2071 /* Compute a (partial) cost for rtx X. Return true if the complete
2072 cost has been computed, and false if subexpressions should be
2073 scanned. In either case, *TOTAL contains the cost result. */
2076 cris_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno
,
2077 int *total
, bool speed
)
2079 int code
= GET_CODE (x
);
2085 HOST_WIDE_INT val
= INTVAL (x
);
2088 else if (val
< 32 && val
>= -32)
2090 /* Eight or 16 bits are a word and cycle more expensive. */
2091 else if (val
<= 32767 && val
>= -32768)
2093 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
2094 another word. FIXME: This isn't linear to 16 bits. */
2110 if (x
!= CONST0_RTX (mode
== VOIDmode
? DImode
: mode
))
2113 /* Make 0.0 cheap, else test-insns will not be used. */
2118 /* If we have one arm of an ADDI, make sure it gets the cost of
2119 one insn, i.e. zero cost for this operand, and just the cost
2120 of the PLUS, as the insn is created by combine from a PLUS
2121 and an ASHIFT, and the MULT cost below would make the
2122 combined value be larger than the separate insns. The insn
2123 validity is checked elsewhere by combine.
2125 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
2126 function should be rewritten. */
2127 if (outer_code
== PLUS
&& cris_biap_index_p (x
, false))
2133 /* Identify values that are no powers of two. Powers of 2 are
2134 taken care of already and those values should not be changed. */
2135 if (!CONST_INT_P (XEXP (x
, 1))
2136 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2138 /* If we have a multiply insn, then the cost is between
2139 1 and 2 "fast" instructions. */
2140 if (TARGET_HAS_MUL_INSNS
)
2142 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2146 /* Estimate as 4 + 4 * #ofbits. */
2147 *total
= COSTS_N_INSNS (132);
2156 if (!CONST_INT_P (XEXP (x
, 1))
2157 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2159 /* Estimate this as 4 + 8 * #of bits. */
2160 *total
= COSTS_N_INSNS (260);
2166 if (CONST_INT_P (XEXP (x
, 1))
2167 /* Two constants may actually happen before optimization. */
2168 && !CONST_INT_P (XEXP (x
, 0))
2169 && !satisfies_constraint_I (XEXP (x
, 1)))
2172 = (rtx_cost (XEXP (x
, 0), mode
, (enum rtx_code
) outer_code
,
2174 + 2 * GET_MODE_NUNITS (mode
));
2180 if (outer_code
!= COMPARE
)
2184 case ZERO_EXTEND
: case SIGN_EXTEND
:
2185 *total
= rtx_cost (XEXP (x
, 0), VOIDmode
, (enum rtx_code
) outer_code
,
2194 /* The ADDRESS_COST worker. */
2197 cris_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
2198 addr_space_t as ATTRIBUTE_UNUSED
,
2199 bool speed ATTRIBUTE_UNUSED
)
2201 /* The metric to use for the cost-macros is unclear.
2202 The metric used here is (the number of cycles needed) / 2,
2203 where we consider equal a cycle for a word of code and a cycle to
2204 read memory. FIXME: Adding "+ 1" to all values would avoid
2205 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
2206 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2207 Unfortunately(?) such a hack would expose other pessimizations,
2208 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2209 loop there, without apparent reason. */
2211 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2212 if (cris_base_or_autoincr_p (x
, false))
2215 /* An indirect mem must be a DIP. This means two bytes extra for code,
2216 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2220 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2221 an extra DIP prefix and 4 bytes of constant in most cases. */
2225 /* Handle BIAP and BDAP prefixes. */
2226 if (GET_CODE (x
) == PLUS
)
2228 rtx tem1
= XEXP (x
, 0);
2229 rtx tem2
= XEXP (x
, 1);
2231 /* Local extended canonicalization rule: the first operand must
2232 be REG, unless it's an operation (MULT). */
2233 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
2234 tem1
= tem2
, tem2
= XEXP (x
, 0);
2236 /* We'll "assume" we have canonical RTX now. */
2237 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
2239 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2240 recognize the typical MULT which is always in tem1 because of
2241 insn canonicalization. */
2242 if ((GET_CODE (tem1
) == MULT
&& cris_biap_index_p (tem1
, false))
2246 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2247 PLUS is always found in tem2. */
2248 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
2251 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2253 if (satisfies_constraint_L (tem2
))
2256 /* A BDAP with some other constant is 2 bytes extra. */
2257 if (CRIS_CONSTANT_P (tem2
))
2258 return (2 + 2 + 2) / 2;
2260 /* BDAP with something indirect should have a higher cost than
2261 BIAP with register. FIXME: Should it cost like a MEM or more? */
2262 return (2 + 2 + 2) / 2;
2265 /* What else? Return a high cost. It matters only for valid
2266 addressing modes. */
2270 /* Check various objections to the side-effect. Used in the test-part
2271 of an anonymous insn describing an insn with a possible side-effect.
2272 Returns nonzero if the implied side-effect is ok.
2275 ops : An array of rtx:es. lreg, rreg, rval,
2276 The variables multop and other_op are indexes into this,
2277 or -1 if they are not applicable.
2278 lreg : The register that gets assigned in the side-effect.
2279 rreg : One register in the side-effect expression
2280 rval : The other register, or an int.
2281 multop : An integer to multiply rval with.
2282 other_op : One of the entities of the main effect,
2283 whose mode we must consider. */
2286 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
2287 int lreg
, int rreg
, int rval
,
2288 int multop
, int other_op
)
2290 /* Find what value to multiply with, for rx =ry + rz * n. */
2291 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
2293 rtx reg_rtx
= ops
[rreg
];
2294 rtx val_rtx
= ops
[rval
];
2296 /* The operands may be swapped. Canonicalize them in reg_rtx and
2297 val_rtx, where reg_rtx always is a reg (for this constraint to
2299 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2300 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2302 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2303 we have no business. */
2304 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2307 /* Don't do this when -mno-split. */
2308 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2311 /* The mult expression may be hidden in lreg. FIXME: Add more
2312 commentary about that. */
2313 if (GET_CODE (val_rtx
) == MULT
)
2315 mult
= INTVAL (XEXP (val_rtx
, 1));
2316 val_rtx
= XEXP (val_rtx
, 0);
2320 /* First check the "other operand". */
2323 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2326 /* Check if the lvalue register is the same as the "other
2327 operand". If so, the result is undefined and we shouldn't do
2328 this. FIXME: Check again. */
2329 if ((cris_base_p (ops
[lreg
], reload_in_progress
|| reload_completed
)
2330 && cris_base_p (ops
[other_op
],
2331 reload_in_progress
|| reload_completed
)
2332 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2333 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2337 /* Do not accept frame_pointer_rtx as any operand. */
2338 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2339 || ops
[rval
] == frame_pointer_rtx
2340 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2344 && ! cris_base_p (val_rtx
, reload_in_progress
|| reload_completed
))
2347 /* Do not allow rx = rx + n if a normal add or sub with same size
2349 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2350 && CONST_INT_P (val_rtx
)
2351 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2354 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2355 if (CRIS_CONSTANT_P (val_rtx
))
2359 && cris_base_or_autoincr_p (XEXP (val_rtx
, 0),
2360 reload_in_progress
|| reload_completed
))
2363 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2364 && MEM_P (XEXP (val_rtx
, 0))
2365 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx
, 0), 0),
2366 reload_in_progress
|| reload_completed
))
2369 /* If we got here, it's not a valid addressing mode. */
2372 else if (code
== MULT
2374 && cris_base_p (val_rtx
,
2375 reload_in_progress
|| reload_completed
)))
2377 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2378 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2379 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2382 /* Do not allow bad multiply-values. */
2383 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2386 /* Only allow r + ... */
2387 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2390 /* If we got here, all seems ok.
2391 (All checks need to be done above). */
2395 /* If we get here, the caller got its initial tests wrong. */
2396 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2399 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2400 insn for other reasons. */
2403 cris_cc0_user_requires_cmp (rtx_insn
*insn
)
2405 rtx_insn
*cc0_user
= NULL
;
2409 gcc_assert (insn
!= NULL
);
2414 cc0_user
= next_cc0_user (insn
);
2415 if (cc0_user
== NULL
)
2418 body
= PATTERN (cc0_user
);
2419 set
= single_set (cc0_user
);
2421 /* Users can be sCC and bCC. */
2422 if (JUMP_P (cc0_user
)
2423 && GET_CODE (body
) == SET
2424 && SET_DEST (body
) == pc_rtx
2425 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
2426 && XEXP (XEXP (SET_SRC (body
), 0), 0) == cc0_rtx
)
2429 GET_CODE (XEXP (SET_SRC (body
), 0)) == GT
2430 || GET_CODE (XEXP (SET_SRC (body
), 0)) == LE
;
2435 GET_CODE (SET_SRC (body
)) == GT
2436 || GET_CODE (SET_SRC (body
)) == LE
;
2442 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2443 does not handle the case where the IN operand is strict_low_part; it
2444 does handle it for X. Test-case in Axis-20010516. This function takes
2445 care of that for THIS port. FIXME: strict_low_part is going away
2449 cris_reg_overlap_mentioned_p (rtx x
, rtx in
)
2451 /* The function reg_overlap_mentioned now handles when X is
2452 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2453 if (GET_CODE (in
) == STRICT_LOW_PART
)
2456 return reg_overlap_mentioned_p (x
, in
);
2459 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2460 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2464 cris_valid_pic_const (const_rtx x
, bool any_operand
)
2466 gcc_assert (flag_pic
);
2468 switch (GET_CODE (x
))
2477 if (GET_CODE (x
) != CONST
)
2482 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2483 if (GET_CODE (x
) == PLUS
2484 && GET_CODE (XEXP (x
, 0)) == UNSPEC
2485 && (XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREL
2486 || XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_PCREL
)
2487 && CONST_INT_P (XEXP (x
, 1)))
2490 if (GET_CODE (x
) == UNSPEC
)
2491 switch (XINT (x
, 1))
2493 /* A PCREL operand is only valid for call and movsi. */
2494 case CRIS_UNSPEC_PLT_PCREL
:
2495 case CRIS_UNSPEC_PCREL
:
2496 return !any_operand
;
2498 case CRIS_UNSPEC_PLT_GOTREL
:
2499 case CRIS_UNSPEC_PLTGOTREAD
:
2500 case CRIS_UNSPEC_GOTREAD
:
2501 case CRIS_UNSPEC_GOTREL
:
2507 return cris_symbol_type_of (x
) == cris_no_symbol
;
2510 /* Helper function to find the right symbol-type to generate,
2511 given the original (non-PIC) representation. */
2513 enum cris_symbol_type
2514 cris_symbol_type_of (const_rtx x
)
2516 switch (GET_CODE (x
))
2520 ? (SYMBOL_REF_LOCAL_P (x
)
2521 ? cris_rel_symbol
: cris_got_symbol
)
2522 : cris_offsettable_symbol
;
2525 return flag_pic
? cris_rel_symbol
: cris_offsettable_symbol
;
2528 return cris_symbol_type_of (XEXP (x
, 0));
2533 enum cris_symbol_type t1
= cris_symbol_type_of (XEXP (x
, 0));
2534 enum cris_symbol_type t2
= cris_symbol_type_of (XEXP (x
, 1));
2536 gcc_assert (t1
== cris_no_symbol
|| t2
== cris_no_symbol
);
2538 if (t1
== cris_got_symbol
|| t2
== cris_got_symbol
)
2539 return cris_got_symbol_needing_fixup
;
2541 return t1
!= cris_no_symbol
? t1
: t2
;
2546 return cris_no_symbol
;
2552 fatal_insn ("unrecognized supposed constant", x
);
2558 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2561 cris_legitimate_pic_operand (rtx x
)
2563 /* Symbols are not valid PIC operands as-is; just constants. */
2564 return cris_valid_pic_const (x
, true);
2567 /* Queue an .ident string in the queue of top-level asm statements.
2568 If the front-end is done, we must be being called from toplev.c.
2569 In that case, do nothing. */
2571 cris_asm_output_ident (const char *string
)
2573 if (symtab
->state
!= PARSING
)
2576 default_asm_output_ident_directive (string
);
2579 /* The ASM_OUTPUT_CASE_END worker. */
2582 cris_asm_output_case_end (FILE *stream
, int num
, rtx_insn
*table
)
2584 /* Step back, over the label for the table, to the actual casejump and
2585 assert that we find only what's expected. */
2586 rtx_insn
*whole_jump_insn
= prev_nonnote_nondebug_insn (table
);
2587 gcc_assert (whole_jump_insn
!= NULL_RTX
&& LABEL_P (whole_jump_insn
));
2588 whole_jump_insn
= prev_nonnote_nondebug_insn (whole_jump_insn
);
2589 gcc_assert (whole_jump_insn
!= NULL_RTX
2590 && (JUMP_P (whole_jump_insn
)
2591 || (TARGET_V32
&& INSN_P (whole_jump_insn
)
2592 && GET_CODE (PATTERN (whole_jump_insn
)) == SEQUENCE
)));
2593 /* Get the pattern of the casejump, so we can extract the default label. */
2594 rtx whole_jump_pat
= PATTERN (whole_jump_insn
);
2598 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2599 filled. We also output the offset word a little differently. */
2601 = (GET_CODE (whole_jump_pat
) == SEQUENCE
2602 ? PATTERN (XVECEXP (whole_jump_pat
, 0, 0)) : whole_jump_pat
);
2604 asm_fprintf (stream
,
2605 "\t.word %LL%d-.%s\n",
2606 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2607 (parallel_jump
, 0, 0),
2609 (TARGET_PDEBUG
? "; default" : ""));
2613 asm_fprintf (stream
,
2614 "\t.word %LL%d-%LL%d%s\n",
2615 CODE_LABEL_NUMBER (XEXP
2617 (XEXP (XVECEXP (whole_jump_pat
, 0, 0), 1),
2620 (TARGET_PDEBUG
? "; default" : ""));
2623 /* The TARGET_OPTION_OVERRIDE worker.
2624 As is the norm, this also parses -mfoo=bar type parameters. */
2627 cris_option_override (void)
2629 if (cris_max_stackframe_str
)
2631 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2633 /* Do some sanity checking. */
2634 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2635 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2636 cris_max_stackframe
, 0x20000000);
2639 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2640 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2641 cris_cpu_version
= CRIS_CPU_SVINTO
;
2642 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2643 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2645 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2649 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2651 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2652 cris_cpu_version
= 3;
2654 if (strcmp ("svinto", cris_cpu_str
) == 0
2655 || strcmp ("etrax100", cris_cpu_str
) == 0)
2656 cris_cpu_version
= 8;
2658 if (strcmp ("ng", cris_cpu_str
) == 0
2659 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2660 cris_cpu_version
= 10;
2662 if (cris_cpu_version
< 0 || cris_cpu_version
> 32)
2663 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2666 /* Set the target flags. */
2667 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2668 target_flags
|= MASK_ETRAX4_ADD
;
2670 /* If this is Svinto or higher, align for 32 bit accesses. */
2671 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2673 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2674 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2677 /* Note that we do not add new flags when it can be completely
2678 described with a macro that uses -mcpu=X. So
2679 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2685 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2687 if (strcmp ("etrax4", cris_tune_str
) == 0)
2690 if (strcmp ("svinto", cris_tune_str
) == 0
2691 || strcmp ("etrax100", cris_tune_str
) == 0)
2694 if (strcmp ("ng", cris_tune_str
) == 0
2695 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2698 if (cris_tune
< 0 || cris_tune
> 32)
2699 error ("unknown CRIS cpu version specification in -mtune= : %s",
2702 if (cris_tune
>= CRIS_CPU_SVINTO
)
2703 /* We have currently nothing more to tune than alignment for
2706 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2707 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2710 if (cris_cpu_version
>= CRIS_CPU_V32
)
2711 target_flags
&= ~(MASK_SIDE_EFFECT_PREFIXES
|MASK_MUL_BUG
);
2715 /* Use error rather than warning, so invalid use is easily
2716 detectable. Still change to the values we expect, to avoid
2720 error ("-fPIC and -fpic are not supported in this configuration");
2724 /* Turn off function CSE. We need to have the addresses reach the
2725 call expanders to get PLT-marked, as they could otherwise be
2726 compared against zero directly or indirectly. After visiting the
2727 call expanders they will then be cse:ed, as the call expanders
2728 force_reg the addresses, effectively forcing flag_no_function_cse
2730 flag_no_function_cse
= 1;
2733 /* Set the per-function-data initializer. */
2734 init_machine_status
= cris_init_machine_status
;
2737 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2740 cris_asm_output_mi_thunk (FILE *stream
,
2741 tree thunkdecl ATTRIBUTE_UNUSED
,
2742 HOST_WIDE_INT delta
,
2743 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2746 /* Make sure unwind info is emitted for the thunk if needed. */
2747 final_start_function (emit_barrier (), stream
, 1);
2750 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2751 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2752 reg_names
[CRIS_FIRST_ARG_REG
]);
2754 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2755 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2756 reg_names
[CRIS_FIRST_ARG_REG
]);
2760 const char *name
= XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0);
2762 name
= (* targetm
.strip_name_encoding
) (name
);
2766 fprintf (stream
, "\tba ");
2767 assemble_name (stream
, name
);
2768 fprintf (stream
, "%s\n\tnop\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2772 fprintf (stream
, "\tadd.d ");
2773 assemble_name (stream
, name
);
2774 fprintf (stream
, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2779 fprintf (stream
, "\tjump ");
2780 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2781 fprintf (stream
, "\n");
2784 fprintf (stream
, "\tnop\n");
2787 final_end_function ();
2790 /* Boilerplate emitted at start of file.
2792 NO_APP *only at file start* means faster assembly. It also means
2793 comments are not allowed. In some cases comments will be output
2794 for debugging purposes. Make sure they are allowed then. */
2796 cris_file_start (void)
2798 /* These expressions can vary at run time, so we cannot put
2799 them into TARGET_INITIALIZER. */
2800 targetm
.asm_file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2802 default_file_start ();
2805 /* Output that goes at the end of the file, similarly. */
2808 cris_file_end (void)
2810 /* For CRIS, the default is to assume *no* executable stack, so output
2811 an executable-stack-note only when needed. */
2812 if (TARGET_LINUX
&& trampolines_created
)
2813 file_end_indicate_exec_stack ();
2816 /* Rename the function calls for integer multiply and divide. */
2818 cris_init_libfuncs (void)
2820 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2821 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2822 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2823 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2824 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2826 /* Atomic data being unaligned is unfortunately a reality.
2828 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS
)
2830 set_optab_libfunc (sync_compare_and_swap_optab
, SImode
,
2831 "__cris_atcmpxchgr32");
2832 set_optab_libfunc (sync_compare_and_swap_optab
, HImode
,
2833 "__cris_atcmpxchgr16");
2837 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2841 cris_init_expanders (void)
2843 /* Nothing here at the moment. */
2846 /* Zero initialization is OK for all current fields. */
2848 static struct machine_function
*
2849 cris_init_machine_status (void)
2851 return ggc_cleared_alloc
<machine_function
> ();
2854 /* Split a 2 word move (DI or presumably DF) into component parts.
2855 Originally a copy of gen_split_move_double in m32r.c. */
2858 cris_split_movdx (rtx
*operands
)
2860 machine_mode mode
= GET_MODE (operands
[0]);
2861 rtx dest
= operands
[0];
2862 rtx src
= operands
[1];
2865 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2866 longer happen; after reload there are no SUBREGs any more, and we're
2867 only called after reload. */
2868 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2873 int dregno
= REGNO (dest
);
2875 /* Reg-to-reg copy. */
2878 int sregno
= REGNO (src
);
2880 int reverse
= (dregno
== sregno
+ 1);
2882 /* We normally copy the low-numbered register first. However, if
2883 the first register operand 0 is the same as the second register of
2884 operand 1, we must copy in the opposite order. */
2885 emit_insn (gen_rtx_SET (operand_subword (dest
, reverse
, TRUE
, mode
),
2886 operand_subword (src
, reverse
, TRUE
, mode
)));
2888 emit_insn (gen_rtx_SET (operand_subword (dest
, !reverse
, TRUE
, mode
),
2889 operand_subword (src
, !reverse
, TRUE
, mode
)));
2891 /* Constant-to-reg copy. */
2892 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2895 split_double (src
, &words
[0], &words
[1]);
2896 emit_insn (gen_rtx_SET (operand_subword (dest
, 0, TRUE
, mode
),
2899 emit_insn (gen_rtx_SET (operand_subword (dest
, 1, TRUE
, mode
),
2902 /* Mem-to-reg copy. */
2903 else if (MEM_P (src
))
2905 /* If the high-address word is used in the address, we must load it
2906 last. Otherwise, load it first. */
2907 rtx addr
= XEXP (src
, 0);
2908 int reverse
= (refers_to_regno_p (dregno
, addr
) != 0);
2910 /* The original code implies that we can't do
2911 move.x [rN+],rM move.x [rN],rM+1
2912 when rN is dead, because of REG_NOTES damage. That is
2913 consistent with what I've seen, so don't try it.
2915 We have two different cases here; if the addr is POST_INC,
2916 just pass it through, otherwise add constants. */
2918 if (GET_CODE (addr
) == POST_INC
)
2923 /* Whenever we emit insns with post-incremented
2924 addresses ourselves, we must add a post-inc note
2926 mem
= change_address (src
, SImode
, addr
);
2928 = gen_rtx_SET (operand_subword (dest
, 0, TRUE
, mode
), mem
);
2929 insn
= emit_insn (insn
);
2930 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2932 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2935 mem
= copy_rtx (mem
);
2937 = gen_rtx_SET (operand_subword (dest
, 1, TRUE
, mode
), mem
);
2938 insn
= emit_insn (insn
);
2939 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2941 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2946 /* Make sure we don't get any other addresses with
2947 embedded postincrements. They should be stopped in
2948 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2950 if (side_effects_p (addr
))
2951 fatal_insn ("unexpected side-effects in address", addr
);
2953 emit_insn (gen_rtx_SET
2954 (operand_subword (dest
, reverse
, TRUE
, mode
),
2957 plus_constant (Pmode
, addr
,
2958 reverse
* UNITS_PER_WORD
))));
2959 emit_insn (gen_rtx_SET
2960 (operand_subword (dest
, ! reverse
, TRUE
, mode
),
2963 plus_constant (Pmode
, addr
,
2969 internal_error ("unknown src");
2971 /* Reg-to-mem copy or clear mem. */
2972 else if (MEM_P (dest
)
2974 || src
== const0_rtx
2975 || src
== CONST0_RTX (DFmode
)))
2977 rtx addr
= XEXP (dest
, 0);
2979 if (GET_CODE (addr
) == POST_INC
)
2984 /* Whenever we emit insns with post-incremented addresses
2985 ourselves, we must add a post-inc note manually. */
2986 mem
= change_address (dest
, SImode
, addr
);
2988 = gen_rtx_SET (mem
, operand_subword (src
, 0, TRUE
, mode
));
2989 insn
= emit_insn (insn
);
2990 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2992 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2995 mem
= copy_rtx (mem
);
2996 insn
= gen_rtx_SET (mem
, operand_subword (src
, 1, TRUE
, mode
));
2997 insn
= emit_insn (insn
);
2998 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3000 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3005 /* Make sure we don't get any other addresses with embedded
3006 postincrements. They should be stopped in
3007 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
3008 if (side_effects_p (addr
))
3009 fatal_insn ("unexpected side-effects in address", addr
);
3011 emit_insn (gen_rtx_SET
3012 (change_address (dest
, SImode
, addr
),
3013 operand_subword (src
, 0, TRUE
, mode
)));
3015 emit_insn (gen_rtx_SET
3016 (change_address (dest
, SImode
,
3017 plus_constant (Pmode
, addr
,
3019 operand_subword (src
, 1, TRUE
, mode
)));
3024 internal_error ("unknown dest");
3031 /* The expander for the prologue pattern name. */
3034 cris_expand_prologue (void)
3037 int size
= get_frame_size ();
3038 /* Shorten the used name for readability. */
3039 int cfoa_size
= crtl
->outgoing_args_size
;
3040 int last_movem_reg
= -1;
3043 int return_address_on_stack
= cris_return_address_on_stack ();
3044 int got_really_used
= false;
3045 int n_movem_regs
= 0;
3046 int pretend
= crtl
->args
.pretend_args_size
;
3048 /* Don't do anything if no prologues or epilogues are wanted. */
3049 if (!TARGET_PROLOGUE_EPILOGUE
)
3052 CRIS_ASSERT (size
>= 0);
3054 if (crtl
->uses_pic_offset_table
)
3056 /* A reference may have been optimized out (like the abort () in
3057 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3059 push_topmost_sequence ();
3061 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3062 pop_topmost_sequence ();
3065 /* Align the size to what's best for the CPU model. */
3066 if (TARGET_STACK_ALIGN
)
3067 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3071 /* See also cris_setup_incoming_varargs where
3072 cfun->machine->stdarg_regs is set. There are other setters of
3073 crtl->args.pretend_args_size than stdarg handling, like
3074 for an argument passed with parts in R13 and stack. We must
3075 not store R13 into the pretend-area for that case, as GCC does
3076 that itself. "Our" store would be marked as redundant and GCC
3077 will attempt to remove it, which will then be flagged as an
3078 internal error; trying to remove a frame-related insn. */
3079 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
3081 framesize
+= pretend
;
3083 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
3085 regno
--, pretend
-= 4, stdarg_regs
--)
3087 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3088 plus_constant (Pmode
,
3091 /* FIXME: When dwarf2 frame output and unless asynchronous
3092 exceptions, make dwarf2 bundle together all stack
3093 adjustments like it does for registers between stack
3095 RTX_FRAME_RELATED_P (insn
) = 1;
3097 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3098 set_mem_alias_set (mem
, get_varargs_alias_set ());
3099 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, regno
));
3101 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
3102 the value isn't restored, so we don't want to tell dwarf2
3103 that it's been stored to stack, else EH handling info would
3107 /* For other setters of crtl->args.pretend_args_size, we
3108 just adjust the stack by leaving the remaining size in
3109 "pretend", handled below. */
3112 /* Save SRP if not a leaf function. */
3113 if (return_address_on_stack
)
3115 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3116 plus_constant (Pmode
, stack_pointer_rtx
,
3119 RTX_FRAME_RELATED_P (insn
) = 1;
3121 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3122 set_mem_alias_set (mem
, get_frame_alias_set ());
3123 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, CRIS_SRP_REGNUM
));
3124 RTX_FRAME_RELATED_P (insn
) = 1;
3128 /* Set up the frame pointer, if needed. */
3129 if (frame_pointer_needed
)
3131 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3132 plus_constant (Pmode
, stack_pointer_rtx
,
3135 RTX_FRAME_RELATED_P (insn
) = 1;
3137 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3138 set_mem_alias_set (mem
, get_frame_alias_set ());
3139 insn
= emit_move_insn (mem
, frame_pointer_rtx
);
3140 RTX_FRAME_RELATED_P (insn
) = 1;
3142 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
3143 RTX_FRAME_RELATED_P (insn
) = 1;
3148 /* Between frame-pointer and saved registers lie the area for local
3149 variables. If we get here with "pretended" size remaining, count
3150 it into the general stack size. */
3153 /* Get a contiguous sequence of registers, starting with R0, that need
3155 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3157 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3161 /* Check if movem may be used for registers so far. */
3162 if (regno
== last_movem_reg
+ 1)
3163 /* Yes, update next expected register. */
3164 last_movem_reg
= regno
;
3167 /* We cannot use movem for all registers. We have to flush
3168 any movem:ed registers we got so far. */
3169 if (last_movem_reg
!= -1)
3172 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3174 /* It is a win to use a side-effect assignment for
3175 64 <= size <= 128. But side-effect on movem was
3176 not usable for CRIS v0..3. Also only do it if
3177 side-effects insns are allowed. */
3178 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3179 && (last_movem_reg
+ 1) * 4 + size
<= 128
3180 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3181 && TARGET_SIDE_EFFECT_PREFIXES
)
3184 = gen_rtx_MEM (SImode
,
3185 plus_constant (Pmode
, stack_pointer_rtx
,
3186 -(n_saved
* 4 + size
)));
3187 set_mem_alias_set (mem
, get_frame_alias_set ());
3189 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3190 -(n_saved
* 4 + size
),
3196 = gen_rtx_SET (stack_pointer_rtx
,
3197 plus_constant (Pmode
, stack_pointer_rtx
,
3198 -(n_saved
* 4 + size
)));
3199 insn
= emit_insn (insn
);
3200 RTX_FRAME_RELATED_P (insn
) = 1;
3202 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3203 set_mem_alias_set (mem
, get_frame_alias_set ());
3204 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3208 framesize
+= n_saved
* 4 + size
;
3209 last_movem_reg
= -1;
3213 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3214 plus_constant (Pmode
,
3217 RTX_FRAME_RELATED_P (insn
) = 1;
3219 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3220 set_mem_alias_set (mem
, get_frame_alias_set ());
3221 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, regno
));
3222 RTX_FRAME_RELATED_P (insn
) = 1;
3224 framesize
+= 4 + size
;
3230 /* Check after, if we could movem all registers. This is the normal case. */
3231 if (last_movem_reg
!= -1)
3234 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3236 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3237 do it if side-effects insns are allowed. */
3238 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3239 && (last_movem_reg
+ 1) * 4 + size
<= 128
3240 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3241 && TARGET_SIDE_EFFECT_PREFIXES
)
3244 = gen_rtx_MEM (SImode
,
3245 plus_constant (Pmode
, stack_pointer_rtx
,
3246 -(n_saved
* 4 + size
)));
3247 set_mem_alias_set (mem
, get_frame_alias_set ());
3248 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3249 -(n_saved
* 4 + size
), true);
3254 = gen_rtx_SET (stack_pointer_rtx
,
3255 plus_constant (Pmode
, stack_pointer_rtx
,
3256 -(n_saved
* 4 + size
)));
3257 insn
= emit_insn (insn
);
3258 RTX_FRAME_RELATED_P (insn
) = 1;
3260 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3261 set_mem_alias_set (mem
, get_frame_alias_set ());
3262 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
3265 framesize
+= n_saved
* 4 + size
;
3266 /* We have to put outgoing argument space after regs. */
3269 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3270 plus_constant (Pmode
,
3273 RTX_FRAME_RELATED_P (insn
) = 1;
3274 framesize
+= cfoa_size
;
3277 else if ((size
+ cfoa_size
) > 0)
3279 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3280 plus_constant (Pmode
,
3282 -(cfoa_size
+ size
))));
3283 RTX_FRAME_RELATED_P (insn
) = 1;
3284 framesize
+= size
+ cfoa_size
;
3287 /* Set up the PIC register, if it is used. */
3288 if (got_really_used
)
3291 = gen_rtx_UNSPEC (SImode
, gen_rtvec (1, const0_rtx
), CRIS_UNSPEC_GOT
);
3292 emit_move_insn (pic_offset_table_rtx
, got
);
3294 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3295 follow exceptional paths and tries to delete the GOT load as
3296 unused, if it isn't used on the non-exceptional paths. Other
3297 ports have similar or other cover-ups, or plain bugs marking
3298 the GOT register load as maybe-dead. To see this, remove the
3299 line below and try libsupc++/vec.cc or a trivial
3300 "static void y (); void x () {try {y ();} catch (...) {}}". */
3301 emit_use (pic_offset_table_rtx
);
3304 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
3305 warning (0, "stackframe too big: %d bytes", framesize
);
3308 /* The expander for the epilogue pattern. */
3311 cris_expand_epilogue (void)
3314 int size
= get_frame_size ();
3315 int last_movem_reg
= -1;
3316 int argspace_offset
= crtl
->outgoing_args_size
;
3317 int pretend
= crtl
->args
.pretend_args_size
;
3319 bool return_address_on_stack
= cris_return_address_on_stack ();
3320 /* A reference may have been optimized out
3321 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3322 so check that it's still used. */
3323 int got_really_used
= false;
3324 int n_movem_regs
= 0;
3326 if (!TARGET_PROLOGUE_EPILOGUE
)
3329 if (crtl
->uses_pic_offset_table
)
3331 /* A reference may have been optimized out (like the abort () in
3332 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3334 push_topmost_sequence ();
3336 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3337 pop_topmost_sequence ();
3340 /* Align byte count of stack frame. */
3341 if (TARGET_STACK_ALIGN
)
3342 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3344 /* Check how many saved regs we can movem. They start at r0 and must
3347 regno
< FIRST_PSEUDO_REGISTER
;
3349 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3353 if (regno
== last_movem_reg
+ 1)
3354 last_movem_reg
= regno
;
3359 /* If there was only one register that really needed to be saved
3360 through movem, don't use movem. */
3361 if (n_movem_regs
== 1)
3362 last_movem_reg
= -1;
3364 /* Now emit "normal" move insns for all regs higher than the movem
3366 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
3367 regno
> last_movem_reg
;
3369 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3373 if (argspace_offset
)
3375 /* There is an area for outgoing parameters located before
3376 the saved registers. We have to adjust for that. */
3377 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3378 plus_constant (Pmode
, stack_pointer_rtx
,
3380 /* Make sure we only do this once. */
3381 argspace_offset
= 0;
3384 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3385 stack_pointer_rtx
));
3386 set_mem_alias_set (mem
, get_frame_alias_set ());
3387 insn
= emit_move_insn (gen_raw_REG (SImode
, regno
), mem
);
3389 /* Whenever we emit insns with post-incremented addresses
3390 ourselves, we must add a post-inc note manually. */
3392 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3395 /* If we have any movem-restore, do it now. */
3396 if (last_movem_reg
!= -1)
3400 if (argspace_offset
)
3402 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3403 plus_constant (Pmode
, stack_pointer_rtx
,
3405 argspace_offset
= 0;
3408 mem
= gen_rtx_MEM (SImode
,
3409 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3410 set_mem_alias_set (mem
, get_frame_alias_set ());
3412 = emit_insn (cris_gen_movem_load (mem
,
3413 GEN_INT (last_movem_reg
+ 1), 0));
3414 /* Whenever we emit insns with post-incremented addresses
3415 ourselves, we must add a post-inc note manually. */
3416 if (side_effects_p (PATTERN (insn
)))
3418 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3421 /* If we don't clobber all of the allocated stack area (we've already
3422 deallocated saved registers), GCC might want to schedule loads from
3423 the stack to *after* the stack-pointer restore, which introduces an
3424 interrupt race condition. This happened for the initial-value
3425 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3426 other failure for that test). It also happened for the stack slot
3427 for the return value in (one version of)
3428 linux/fs/dcache.c:__d_lookup, at least with "-O2
3429 -fno-omit-frame-pointer". */
3431 /* Restore frame pointer if necessary. */
3432 if (frame_pointer_needed
)
3436 emit_insn (gen_cris_frame_deallocated_barrier ());
3438 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
3439 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3440 stack_pointer_rtx
));
3441 set_mem_alias_set (mem
, get_frame_alias_set ());
3442 insn
= emit_move_insn (frame_pointer_rtx
, mem
);
3444 /* Whenever we emit insns with post-incremented addresses
3445 ourselves, we must add a post-inc note manually. */
3447 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3449 else if ((size
+ argspace_offset
) != 0)
3451 emit_insn (gen_cris_frame_deallocated_barrier ());
3453 /* If there was no frame-pointer to restore sp from, we must
3454 explicitly deallocate local variables. */
3456 /* Handle space for outgoing parameters that hasn't been handled
3458 size
+= argspace_offset
;
3460 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3461 plus_constant (Pmode
, stack_pointer_rtx
, size
)));
3464 /* If this function has no pushed register parameters
3465 (stdargs/varargs), and if it is not a leaf function, then we have
3466 the return address on the stack. */
3467 if (return_address_on_stack
&& pretend
== 0)
3469 if (TARGET_V32
|| crtl
->calls_eh_return
)
3473 rtx srpreg
= gen_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3474 mem
= gen_rtx_MEM (SImode
,
3475 gen_rtx_POST_INC (SImode
,
3476 stack_pointer_rtx
));
3477 set_mem_alias_set (mem
, get_frame_alias_set ());
3478 insn
= emit_move_insn (srpreg
, mem
);
3480 /* Whenever we emit insns with post-incremented addresses
3481 ourselves, we must add a post-inc note manually. */
3483 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3485 if (crtl
->calls_eh_return
)
3486 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3488 gen_raw_REG (SImode
, CRIS_STACKADJ_REG
)));
3489 cris_expand_return (false);
3492 cris_expand_return (true);
3497 /* If we pushed some register parameters, then adjust the stack for
3501 /* If SRP is stored on the way, we need to restore it first. */
3502 if (return_address_on_stack
)
3505 rtx srpreg
= gen_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3508 mem
= gen_rtx_MEM (SImode
,
3509 gen_rtx_POST_INC (SImode
,
3510 stack_pointer_rtx
));
3511 set_mem_alias_set (mem
, get_frame_alias_set ());
3512 insn
= emit_move_insn (srpreg
, mem
);
3514 /* Whenever we emit insns with post-incremented addresses
3515 ourselves, we must add a post-inc note manually. */
3517 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3520 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3521 plus_constant (Pmode
, stack_pointer_rtx
,
3525 /* Perform the "physical" unwinding that the EH machinery calculated. */
3526 if (crtl
->calls_eh_return
)
3527 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3529 gen_raw_REG (SImode
, CRIS_STACKADJ_REG
)));
3530 cris_expand_return (false);
3533 /* Worker function for generating movem from mem for load_multiple. */
3536 cris_gen_movem_load (rtx src
, rtx nregs_rtx
, int nprefix
)
3538 int nregs
= INTVAL (nregs_rtx
);
3542 rtx srcreg
= XEXP (src
, 0);
3543 unsigned int regno
= nregs
- 1;
3552 if (GET_CODE (srcreg
) == POST_INC
)
3553 srcreg
= XEXP (srcreg
, 0);
3555 CRIS_ASSERT (REG_P (srcreg
));
3557 /* Don't use movem for just one insn. The insns are equivalent except
3558 for the pipeline hazard (on v32); movem does not forward the loaded
3559 registers so there's a three cycles penalty for their use. */
3561 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3563 vec
= rtvec_alloc (nprefix
+ nregs
3564 + (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3566 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3568 RTVEC_ELT (vec
, nprefix
+ 1)
3569 = gen_rtx_SET (srcreg
, plus_constant (Pmode
, srcreg
, nregs
* 4));
3573 src
= replace_equiv_address (src
, srcreg
);
3574 RTVEC_ELT (vec
, nprefix
)
3575 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
), src
);
3578 for (i
= 1; i
< nregs
; i
++, eltno
++)
3580 RTVEC_ELT (vec
, nprefix
+ eltno
)
3581 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
),
3582 adjust_address_nv (src
, SImode
, i
* 4));
3586 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3589 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3590 are added that the dwarf2 machinery understands. */
3593 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3596 int nregs
= INTVAL (nregs_rtx
);
3601 rtx destreg
= XEXP (dest
, 0);
3602 unsigned int regno
= nregs
- 1;
3611 if (GET_CODE (destreg
) == POST_INC
)
3612 increment
+= nregs
* 4;
3614 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3615 destreg
= XEXP (destreg
, 0);
3617 CRIS_ASSERT (REG_P (destreg
));
3619 /* Don't use movem for just one insn. The insns are equivalent except
3620 for the pipeline hazard (on v32); movem does not forward the loaded
3621 registers so there's a three cycles penalty for use. */
3624 rtx mov
= gen_rtx_SET (dest
, gen_rtx_REG (SImode
, 0));
3628 insn
= emit_insn (mov
);
3630 RTX_FRAME_RELATED_P (insn
) = 1;
3634 /* If there was a request for a side-effect, create the ordinary
3636 vec
= rtvec_alloc (2);
3638 RTVEC_ELT (vec
, 0) = mov
;
3639 RTVEC_ELT (vec
, 1) = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3643 RTX_FRAME_RELATED_P (mov
) = 1;
3644 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3649 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3651 = gen_rtx_SET (replace_equiv_address (dest
,
3652 plus_constant (Pmode
, destreg
,
3654 gen_rtx_REG (SImode
, regno
));
3657 /* The dwarf2 info wants this mark on each component in a parallel
3658 that's part of the prologue (though it's optional on the first
3661 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3666 = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3668 ? increment
: nregs
* 4));
3672 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3674 /* Don't call adjust_address_nv on a post-incremented address if
3676 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3677 dest
= replace_equiv_address (dest
, destreg
);
3680 for (i
= 1; i
< nregs
; i
++, eltno
++)
3682 RTVEC_ELT (vec
, eltno
)
3683 = gen_rtx_SET (adjust_address_nv (dest
, SImode
, i
* 4),
3684 gen_rtx_REG (SImode
, regno
));
3686 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3691 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3693 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3694 we need to keep the stack adjustment separate, after the
3695 MEM-setters. Else the stack-adjustment in the second component of
3696 the parallel would be mishandled; the offsets for the SETs that
3697 follow it would be wrong. We prepare for this by adding a
3698 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3699 followed by the increment. Note that we have FRAME_RELATED_P on
3700 all the SETs, including the original stack adjustment SET in the
3706 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3707 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3708 for (i
= 1; i
< nregs
; i
++)
3710 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3711 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3712 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, seq
);
3715 RTX_FRAME_RELATED_P (insn
) = 1;
3721 /* Worker function for expanding the address for PIC function calls. */
3724 cris_expand_pic_call_address (rtx
*opp
, rtx
*markerp
)
3728 gcc_assert (flag_pic
&& MEM_P (op
));
3731 /* It might be that code can be generated that jumps to 0 (or to a
3732 specific address). Don't die on that. (There is a
3734 if (CONSTANT_P (op
) && !CONST_INT_P (op
))
3736 enum cris_symbol_type t
= cris_symbol_type_of (op
);
3738 CRIS_ASSERT (can_create_pseudo_p ());
3740 /* For local symbols (non-PLT), just get the plain symbol
3741 reference into a register. For symbols that can be PLT, make
3743 if (t
== cris_rel_symbol
)
3745 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3746 into a register caused performance regression for 3.2.1,
3747 observable in __floatdidf and elsewhere in libgcc. */
3750 rtx sym
= GET_CODE (op
) != CONST
? op
: get_related_value (op
);
3751 HOST_WIDE_INT offs
= get_integer_term (op
);
3753 /* We can't get calls to sym+N, N integer, can we? */
3754 gcc_assert (offs
== 0);
3756 op
= gen_rtx_CONST (Pmode
,
3757 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, sym
),
3758 CRIS_UNSPEC_PCREL
));
3761 op
= force_reg (Pmode
, op
);
3764 *markerp
= const0_rtx
;
3766 else if (t
== cris_got_symbol
)
3768 if (TARGET_AVOID_GOTPLT
)
3770 /* Change a "jsr sym" into (allocate register rM, rO)
3771 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM"
3772 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3773 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))"
3777 crtl
->uses_pic_offset_table
= 1;
3778 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3780 ? CRIS_UNSPEC_PLT_PCREL
3781 : CRIS_UNSPEC_PLT_GOTREL
);
3782 tem
= gen_rtx_CONST (Pmode
, tem
);
3787 rm
= gen_reg_rtx (Pmode
);
3788 emit_move_insn (rm
, tem
);
3789 ro
= gen_reg_rtx (Pmode
);
3790 if (expand_binop (Pmode
, add_optab
, rm
,
3791 pic_offset_table_rtx
,
3792 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3793 internal_error ("expand_binop failed in movsi got");
3799 /* Change a "jsr sym" into (allocate register rM, rO)
3800 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3801 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3802 marked as not trapping and not aliasing. No "move.d
3803 [rO],rP" as that would invite to re-use of a value
3804 that should not be reused. FIXME: Need a peephole2
3805 for cases when this is cse:d from the call, to change
3806 back to just get the PLT entry address, so we don't
3807 resolve the same symbol over and over (the memory
3808 access of the PLTGOT isn't constant). */
3809 rtx tem
, mem
, rm
, ro
;
3811 gcc_assert (can_create_pseudo_p ());
3812 crtl
->uses_pic_offset_table
= 1;
3813 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3814 CRIS_UNSPEC_PLTGOTREAD
);
3815 rm
= gen_reg_rtx (Pmode
);
3816 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3817 ro
= gen_reg_rtx (Pmode
);
3818 if (expand_binop (Pmode
, add_optab
, rm
,
3819 pic_offset_table_rtx
,
3820 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3821 internal_error ("expand_binop failed in movsi got");
3822 mem
= gen_rtx_MEM (Pmode
, ro
);
3824 /* This MEM doesn't alias anything. Whether it aliases
3825 other same symbols is unimportant. */
3826 set_mem_alias_set (mem
, new_alias_set ());
3827 MEM_NOTRAP_P (mem
) = 1;
3831 /* We need to prepare this call to go through the PLT; we
3832 need to make GOT available. */
3833 *markerp
= pic_offset_table_rtx
;
3836 /* Can't possibly get anything else for a function-call, right? */
3837 fatal_insn ("unidentifiable call op", op
);
3839 /* If the validizing variant is called, it will try to validize
3840 the address as a valid any-operand constant, but as it's only
3841 valid for calls and moves, it will fail and always be forced
3843 *opp
= replace_equiv_address_nv (*opp
, op
);
3846 /* Can't tell what locality a call to a non-constant address has;
3847 better make the GOT register alive at it.
3848 FIXME: Can we see whether the register has known constant
3850 *markerp
= pic_offset_table_rtx
;
3853 /* Make sure operands are in the right order for an addsi3 insn as
3854 generated by a define_split. Nothing but REG_P as the first
3855 operand is recognized by addsi3 after reload. OPERANDS contains
3856 the operands, with the first at OPERANDS[N] and the second at
3860 cris_order_for_addsi3 (rtx
*operands
, int n
)
3862 if (!REG_P (operands
[n
]))
3864 rtx tem
= operands
[n
];
3865 operands
[n
] = operands
[n
+ 1];
3866 operands
[n
+ 1] = tem
;
3870 /* Use from within code, from e.g. PRINT_OPERAND and
3871 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3872 different things depending on whether code operand or constant is
3876 cris_output_addr_const (FILE *file
, rtx x
)
3879 output_addr_const (file
, x
);
3883 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3886 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3888 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3890 if (flag_pic
&& in_code
> 0)
3892 const char *origstr
= XSTR (x
, 0);
3894 str
= (* targetm
.strip_name_encoding
) (origstr
);
3895 assemble_name (file
, str
);
3898 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3899 output_operand_lossage ("PIC register isn't set up");
3902 assemble_name (file
, XSTR (x
, 0));
3905 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3908 cris_asm_output_label_ref (FILE *file
, char *buf
)
3910 if (flag_pic
&& in_code
> 0)
3912 assemble_name (file
, buf
);
3915 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3916 internal_error ("emitting PIC operand, but PIC register "
3920 assemble_name (file
, buf
);
3923 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
3926 cris_output_addr_const_extra (FILE *file
, rtx xconst
)
3928 switch (GET_CODE (xconst
))
3933 x
= XVECEXP (xconst
, 0, 0);
3934 CRIS_ASSERT (GET_CODE (x
) == SYMBOL_REF
3935 || GET_CODE (x
) == LABEL_REF
3936 || GET_CODE (x
) == CONST
);
3937 output_addr_const (file
, x
);
3938 switch (XINT (xconst
, 1))
3940 case CRIS_UNSPEC_PCREL
:
3941 /* We only get this with -fpic/PIC to tell it apart from an
3942 invalid symbol. We can't tell here, but it should only
3943 be the operand of a call or movsi. */
3944 gcc_assert (TARGET_V32
&& flag_pic
);
3947 case CRIS_UNSPEC_PLT_PCREL
:
3948 gcc_assert (TARGET_V32
);
3949 fprintf (file
, ":PLT");
3952 case CRIS_UNSPEC_PLT_GOTREL
:
3953 gcc_assert (!TARGET_V32
);
3954 fprintf (file
, ":PLTG");
3957 case CRIS_UNSPEC_GOTREL
:
3958 gcc_assert (!TARGET_V32
);
3959 fprintf (file
, ":GOTOFF");
3962 case CRIS_UNSPEC_GOTREAD
:
3964 fprintf (file
, ":GOT16");
3966 fprintf (file
, ":GOT");
3969 case CRIS_UNSPEC_PLTGOTREAD
:
3971 fprintf (file
, CRIS_GOTPLT_SUFFIX
"16");
3973 fprintf (file
, CRIS_GOTPLT_SUFFIX
);
3986 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3989 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3990 int incoming ATTRIBUTE_UNUSED
)
3992 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
3995 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3998 cris_setup_incoming_varargs (cumulative_args_t ca_v
,
3999 machine_mode mode ATTRIBUTE_UNUSED
,
4000 tree type ATTRIBUTE_UNUSED
,
4001 int *pretend_arg_size
,
4004 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4006 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4008 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
4009 cfun
->machine
->stdarg_regs
= stdarg_regs
;
4010 *pretend_arg_size
= stdarg_regs
* 4;
4014 fprintf (asm_out_file
,
4015 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
4016 ca
->regs
, *pretend_arg_size
, second_time
);
4019 /* Return true if TYPE must be passed by invisible reference.
4020 For cris, we pass <= 8 bytes by value, others by reference. */
4023 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
4024 machine_mode mode
, const_tree type
,
4025 bool named ATTRIBUTE_UNUSED
)
4027 return (targetm
.calls
.must_pass_in_stack (mode
, type
)
4028 || CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 8);
4031 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
4032 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
4033 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
4036 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
4038 int *punsignedp ATTRIBUTE_UNUSED
,
4039 const_tree fntype ATTRIBUTE_UNUSED
,
4042 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
4043 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
4044 Maybe pointless as of now, but let's keep the old behavior. */
4045 if (for_return
== 1)
4047 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
4050 /* Atomic types require alignment to be at least their "natural" size. */
4053 cris_atomic_align_for_mode (machine_mode mode
)
4055 return GET_MODE_BITSIZE (mode
);
4058 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4062 cris_function_value(const_tree type
,
4063 const_tree func ATTRIBUTE_UNUSED
,
4064 bool outgoing ATTRIBUTE_UNUSED
)
4066 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
4069 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4073 cris_libcall_value (machine_mode mode
,
4074 const_rtx fun ATTRIBUTE_UNUSED
)
4076 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
4079 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4083 cris_function_value_regno_p (const unsigned int regno
)
4085 return (regno
== CRIS_FIRST_ARG_REG
);
4089 cris_arg_partial_bytes (cumulative_args_t ca
, machine_mode mode
,
4090 tree type
, bool named ATTRIBUTE_UNUSED
)
4092 if (get_cumulative_args (ca
)->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
4093 && !targetm
.calls
.must_pass_in_stack (mode
, type
)
4094 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 4
4095 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) <= 8)
4096 return UNITS_PER_WORD
;
4102 cris_function_arg_1 (cumulative_args_t ca_v
,
4103 machine_mode mode ATTRIBUTE_UNUSED
,
4104 const_tree type ATTRIBUTE_UNUSED
,
4105 bool named
, bool incoming
)
4107 const CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4109 if ((!incoming
|| named
) && ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4110 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
+ ca
->regs
);
4115 /* Worker function for TARGET_FUNCTION_ARG.
4116 The void_type_node is sent as a "closing" call. */
4119 cris_function_arg (cumulative_args_t ca
, machine_mode mode
,
4120 const_tree type
, bool named
)
4122 return cris_function_arg_1 (ca
, mode
, type
, named
, false);
4125 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
4127 The differences between this and the previous, is that this one checks
4128 that an argument is named, since incoming stdarg/varargs arguments are
4129 pushed onto the stack, and we don't have to check against the "closing"
4130 void_type_node TYPE parameter. */
4133 cris_function_incoming_arg (cumulative_args_t ca
, machine_mode mode
,
4134 const_tree type
, bool named
)
4136 return cris_function_arg_1 (ca
, mode
, type
, named
, true);
4139 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
4142 cris_function_arg_advance (cumulative_args_t ca_v
, machine_mode mode
,
4143 const_tree type
, bool named ATTRIBUTE_UNUSED
)
4145 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4147 ca
->regs
+= (3 + CRIS_FUNCTION_ARG_SIZE (mode
, type
)) / 4;
4150 /* Worker function for TARGET_MD_ASM_ADJUST. */
4153 cris_md_asm_adjust (vec
<rtx
> &outputs
, vec
<rtx
> &inputs
,
4154 vec
<const char *> &constraints
,
4155 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
4157 /* For the time being, all asms clobber condition codes.
4158 Revisit when there's a reasonable use for inputs/outputs
4159 that mention condition codes. */
4160 clobbers
.safe_push (gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
));
4161 SET_HARD_REG_BIT (clobbered_regs
, CRIS_CC0_REGNUM
);
4163 /* Determine if the source using MOF. If it is, automatically
4164 clobbering MOF would cause it to have impossible constraints. */
4166 /* Look for a use of the MOF constraint letter: h. */
4167 for (unsigned i
= 0, n
= constraints
.length(); i
< n
; ++i
)
4168 if (strchr (constraints
[i
], 'h') != NULL
)
4171 /* Look for an output or an input that touches MOF. */
4172 rtx mof_reg
= gen_rtx_REG (SImode
, CRIS_MOF_REGNUM
);
4173 for (unsigned i
= 0, n
= outputs
.length(); i
< n
; ++i
)
4174 if (reg_overlap_mentioned_p (mof_reg
, outputs
[i
]))
4176 for (unsigned i
= 0, n
= inputs
.length(); i
< n
; ++i
)
4177 if (reg_overlap_mentioned_p (mof_reg
, inputs
[i
]))
4180 /* No direct reference to MOF or its constraint.
4181 Clobber it for backward compatibility. */
4182 clobbers
.safe_push (mof_reg
);
4183 SET_HARD_REG_BIT (clobbered_regs
, CRIS_MOF_REGNUM
);
4187 /* Implement TARGET_FRAME_POINTER_REQUIRED.
4189 Really only needed if the stack frame has variable length (alloca
4190 or variable sized local arguments (GNU C extension). See PR39499 and
4191 PR38609 for the reason this isn't just 0. */
4194 cris_frame_pointer_required (void)
4196 return !crtl
->sp_is_unchanging
;
4199 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
4201 This looks too complicated, and it is. I assigned r7 to be the
4202 static chain register, but it is call-saved, so we have to save it,
4203 and come back to restore it after the call, so we have to save srp...
4204 Anyway, trampolines are rare enough that we can cope with this
4205 somewhat lack of elegance.
4206 (Do not be tempted to "straighten up" whitespace in the asms; the
4207 assembler #NO_APP state mandates strict spacing). */
4208 /* ??? See the i386 regparm=3 implementation that pushes the static
4209 chain value to the stack in the trampoline, and uses a call-saved
4210 register when called directly. */
4213 cris_asm_trampoline_template (FILE *f
)
4217 /* This normally-unused nop insn acts as an instruction to
4218 the simulator to flush its instruction cache. None of
4219 the other instructions in the trampoline template suits
4220 as a trigger for V32. The pc-relative addressing mode
4221 works nicely as a trigger for V10.
4222 FIXME: Have specific V32 template (possibly avoiding the
4223 use of a special instruction). */
4224 fprintf (f
, "\tclearf x\n");
4225 /* We have to use a register as an intermediate, choosing
4226 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4227 so we can use it for address indirection and jsr target. */
4228 fprintf (f
, "\tmove $r1,$mof\n");
4230 fprintf (f
, "\tmove.d 0,$r1\n");
4231 fprintf (f
, "\tmove.d $%s,[$r1]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4232 fprintf (f
, "\taddq 6,$r1\n");
4233 fprintf (f
, "\tmove $mof,[$r1]\n");
4234 fprintf (f
, "\taddq 6,$r1\n");
4235 fprintf (f
, "\tmove $srp,[$r1]\n");
4237 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4239 fprintf (f
, "\tmove.d 0,$r1\n");
4240 fprintf (f
, "\tjsr $r1\n");
4241 fprintf (f
, "\tsetf\n");
4243 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4245 fprintf (f
, "\tmove.d 0,$r1\n");
4247 fprintf (f
, "\tmove.d 0,$r9\n");
4248 fprintf (f
, "\tjump $r9\n");
4249 fprintf (f
, "\tsetf\n");
4253 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4254 fprintf (f
, "\tmove $srp,[$pc+22]\n");
4255 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4256 fprintf (f
, "\tjsr 0\n");
4257 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4258 fprintf (f
, "\tjump 0\n");
4262 /* Implement TARGET_TRAMPOLINE_INIT. */
4265 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4267 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4268 rtx tramp
= XEXP (m_tramp
, 0);
4271 emit_block_move (m_tramp
, assemble_trampoline_template (),
4272 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4276 mem
= adjust_address (m_tramp
, SImode
, 6);
4277 emit_move_insn (mem
, plus_constant (Pmode
, tramp
, 38));
4278 mem
= adjust_address (m_tramp
, SImode
, 22);
4279 emit_move_insn (mem
, chain_value
);
4280 mem
= adjust_address (m_tramp
, SImode
, 28);
4281 emit_move_insn (mem
, fnaddr
);
4285 mem
= adjust_address (m_tramp
, SImode
, 10);
4286 emit_move_insn (mem
, chain_value
);
4287 mem
= adjust_address (m_tramp
, SImode
, 16);
4288 emit_move_insn (mem
, fnaddr
);
4291 /* Note that there is no need to do anything with the cache for
4292 sake of a trampoline. */
4297 /* Various small functions to replace macros. Only called from a
4298 debugger. They might collide with gcc functions or system functions,
4299 so only emit them when '#if 1' above. */
4301 enum rtx_code
Get_code (rtx
);
4306 return GET_CODE (x
);
4309 const char *Get_mode (rtx
);
4314 return GET_MODE_NAME (GET_MODE (x
));
4317 rtx
Xexp (rtx
, int);
4325 rtx
Xvecexp (rtx
, int, int);
4328 Xvecexp (rtx x
, int n
, int m
)
4330 return XVECEXP (x
, n
, m
);
4333 int Get_rtx_len (rtx
);
4338 return GET_RTX_LENGTH (GET_CODE (x
));
4341 /* Use upper-case to distinguish from local variables that are sometimes
4342 called next_insn and prev_insn. */
4344 rtx
Next_insn (rtx
);
4347 Next_insn (rtx insn
)
4349 return NEXT_INSN (insn
);
4352 rtx
Prev_insn (rtx
);
4355 Prev_insn (rtx insn
)
4357 return PREV_INSN (insn
);
4361 #include "gt-cris.h"
4365 * eval: (c-set-style "gnu")
4366 * indent-tabs-mode: t