1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 #include "diagnostic-core.h"
43 #include "basic-block.h"
47 #include "target-def.h"
48 #include "targhooks.h"
49 #include "integrate.h"
50 #include "langhooks.h"
54 #define FRV_INLINE inline
57 /* The maximum number of distinct NOP patterns. There are three:
58 nop, fnop and mnop. */
59 #define NUM_NOP_PATTERNS 3
61 /* Classification of instructions and units: integer, floating-point/media,
62 branch and control. */
63 enum frv_insn_group
{ GROUP_I
, GROUP_FM
, GROUP_B
, GROUP_C
, NUM_GROUPS
};
65 /* The DFA names of the units, in packet order. */
66 static const char *const frv_unit_names
[] =
76 /* The classification of each unit in frv_unit_names[]. */
77 static const enum frv_insn_group frv_unit_groups
[ARRAY_SIZE (frv_unit_names
)] =
87 /* Return the DFA unit code associated with the Nth unit of integer
88 or floating-point group GROUP, */
89 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
91 /* Return the number of integer or floating-point unit UNIT
92 (1 for I1, 2 for F2, etc.). */
93 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
95 /* The DFA unit number for each unit in frv_unit_names[]. */
96 static int frv_unit_codes
[ARRAY_SIZE (frv_unit_names
)];
98 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
99 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
100 no instruction of type T has been seen. */
101 static unsigned int frv_type_to_unit
[TYPE_UNKNOWN
+ 1];
103 /* An array of dummy nop INSNs, one for each type of nop that the
105 static GTY(()) rtx frv_nops
[NUM_NOP_PATTERNS
];
107 /* The number of nop instructions in frv_nops[]. */
108 static unsigned int frv_num_nops
;
110 /* The type of access. FRV_IO_UNKNOWN means the access can be either
111 a read or a write. */
112 enum frv_io_type
{ FRV_IO_UNKNOWN
, FRV_IO_READ
, FRV_IO_WRITE
};
114 /* Information about one __builtin_read or __builtin_write access, or
115 the combination of several such accesses. The most general value
116 is all-zeros (an unknown access to an unknown address). */
118 enum frv_io_type type
;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address
;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs
; /* possible registers to allocate */
155 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t
;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op
;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t
;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list
;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg
;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite
;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs
;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec
;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap
;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr
;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
255 /* Cached value of frv_stack_info. */
256 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
258 /* Forward references */
260 static void frv_option_override (void);
261 static bool frv_legitimate_address_p (enum machine_mode
, rtx
, bool);
262 static int frv_default_flags_for_cpu (void);
263 static int frv_string_begins_with (const_tree
, const char *);
264 static FRV_INLINE
bool frv_small_data_reloc_p (rtx
, int);
265 static void frv_print_operand (FILE *, rtx
, int);
266 static void frv_print_operand_address (FILE *, rtx
);
267 static bool frv_print_operand_punct_valid_p (unsigned char code
);
268 static void frv_print_operand_memory_reference_reg
270 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
271 static int frv_print_operand_jump_hint (rtx
);
272 static const char *comparison_string (enum rtx_code
, rtx
);
273 static rtx
frv_function_value (const_tree
, const_tree
,
275 static rtx
frv_libcall_value (enum machine_mode
,
277 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
278 static rtx
single_set_pattern (rtx
);
279 static int frv_function_contains_far_jump (void);
280 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
284 static rtx
frv_frame_offset_rtx (int);
285 static rtx
frv_frame_mem (enum machine_mode
, rtx
, int);
286 static rtx
frv_dwarf_store (rtx
, int);
287 static void frv_frame_insn (rtx
, rtx
);
288 static void frv_frame_access (frv_frame_accessor_t
*,
290 static void frv_frame_access_multi (frv_frame_accessor_t
*,
292 static void frv_frame_access_standard_regs (enum frv_stack_op
,
294 static struct machine_function
*frv_init_machine_status (void);
295 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
296 static enum machine_mode
frv_matching_accg_mode (enum machine_mode
);
297 static rtx
frv_read_argument (tree
, unsigned int);
298 static rtx
frv_read_iacc_argument (enum machine_mode
, tree
, unsigned int);
299 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
300 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
301 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
302 static rtx
frv_legitimize_tls_address (rtx
, enum tls_model
);
303 static rtx
frv_legitimize_address (rtx
, rtx
, enum machine_mode
);
304 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
305 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
306 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
307 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
308 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
309 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
310 static rtx
frv_expand_int_void2arg (enum insn_code
, tree
);
311 static rtx
frv_expand_prefetches (enum insn_code
, tree
);
312 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
313 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
314 static rtx
frv_expand_mclracc_builtin (tree
);
315 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
316 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
317 static rtx
frv_expand_noargs_builtin (enum insn_code
);
318 static void frv_split_iacc_move (rtx
, rtx
);
319 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
320 static int frv_clear_registers_used (rtx
*, void *);
321 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
322 static rtx
frv_ifcvt_rewrite_mem (rtx
, enum machine_mode
, rtx
);
323 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
324 static int frv_acc_group_1 (rtx
*, void *);
325 static unsigned int frv_insn_unit (rtx
);
326 static bool frv_issues_to_branch_unit_p (rtx
);
327 static int frv_cond_flags (rtx
);
328 static bool frv_regstate_conflict_p (regstate_t
, regstate_t
);
329 static int frv_registers_conflict_p_1 (rtx
*, void *);
330 static bool frv_registers_conflict_p (rtx
);
331 static void frv_registers_update_1 (rtx
, const_rtx
, void *);
332 static void frv_registers_update (rtx
);
333 static void frv_start_packet (void);
334 static void frv_start_packet_block (void);
335 static void frv_finish_packet (void (*) (void));
336 static bool frv_pack_insn_p (rtx
);
337 static void frv_add_insn_to_packet (rtx
);
338 static void frv_insert_nop_in_packet (rtx
);
339 static bool frv_for_each_packet (void (*) (void));
340 static bool frv_sort_insn_group_1 (enum frv_insn_group
,
341 unsigned int, unsigned int,
342 unsigned int, unsigned int,
344 static int frv_compare_insns (const void *, const void *);
345 static void frv_sort_insn_group (enum frv_insn_group
);
346 static void frv_reorder_packet (void);
347 static void frv_fill_unused_units (enum frv_insn_group
);
348 static void frv_align_label (void);
349 static void frv_reorg_packet (void);
350 static void frv_register_nop (rtx
);
351 static void frv_reorg (void);
352 static void frv_pack_insns (void);
353 static void frv_function_prologue (FILE *, HOST_WIDE_INT
);
354 static void frv_function_epilogue (FILE *, HOST_WIDE_INT
);
355 static bool frv_assemble_integer (rtx
, unsigned, int);
356 static void frv_init_builtins (void);
357 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
358 static void frv_init_libfuncs (void);
359 static bool frv_in_small_data_p (const_tree
);
360 static void frv_asm_output_mi_thunk
361 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
362 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS
*,
365 static rtx
frv_expand_builtin_saveregs (void);
366 static void frv_expand_builtin_va_start (tree
, rtx
);
367 static bool frv_rtx_costs (rtx
, int, int, int*, bool);
368 static int frv_register_move_cost (enum machine_mode
,
369 reg_class_t
, reg_class_t
);
370 static int frv_memory_move_cost (enum machine_mode
,
372 static void frv_asm_out_constructor (rtx
, int);
373 static void frv_asm_out_destructor (rtx
, int);
374 static bool frv_function_symbol_referenced_p (rtx
);
375 static bool frv_cannot_force_const_mem (enum machine_mode
, rtx
);
376 static const char *unspec_got_name (int);
377 static void frv_output_const_unspec (FILE *,
378 const struct frv_unspec
*);
379 static bool frv_function_ok_for_sibcall (tree
, tree
);
380 static rtx
frv_struct_value_rtx (tree
, int);
381 static bool frv_must_pass_in_stack (enum machine_mode mode
, const_tree type
);
382 static int frv_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
384 static rtx
frv_function_arg (CUMULATIVE_ARGS
*, enum machine_mode
,
386 static rtx
frv_function_incoming_arg (CUMULATIVE_ARGS
*, enum machine_mode
,
388 static void frv_function_arg_advance (CUMULATIVE_ARGS
*, enum machine_mode
,
390 static unsigned int frv_function_arg_boundary (enum machine_mode
,
392 static void frv_output_dwarf_dtprel (FILE *, int, rtx
)
394 static reg_class_t
frv_secondary_reload (bool, rtx
, reg_class_t
,
396 secondary_reload_info
*);
397 static bool frv_frame_pointer_required (void);
398 static bool frv_can_eliminate (const int, const int);
399 static void frv_conditional_register_usage (void);
400 static void frv_trampoline_init (rtx
, tree
, rtx
);
401 static bool frv_class_likely_spilled_p (reg_class_t
);
403 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
404 static const struct default_options frv_option_optimization_table
[] =
406 { OPT_LEVELS_1_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
407 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
410 /* Allow us to easily change the default for -malloc-cc. */
411 #ifndef DEFAULT_NO_ALLOC_CC
412 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
414 #define MASK_DEFAULT_ALLOC_CC 0
417 /* Initialize the GCC target structure. */
418 #undef TARGET_PRINT_OPERAND
419 #define TARGET_PRINT_OPERAND frv_print_operand
420 #undef TARGET_PRINT_OPERAND_ADDRESS
421 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
422 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
423 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
424 #undef TARGET_ASM_FUNCTION_PROLOGUE
425 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
426 #undef TARGET_ASM_FUNCTION_EPILOGUE
427 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
428 #undef TARGET_ASM_INTEGER
429 #define TARGET_ASM_INTEGER frv_assemble_integer
430 #undef TARGET_DEFAULT_TARGET_FLAGS
431 #define TARGET_DEFAULT_TARGET_FLAGS \
432 (MASK_DEFAULT_ALLOC_CC \
439 #undef TARGET_OPTION_OVERRIDE
440 #define TARGET_OPTION_OVERRIDE frv_option_override
441 #undef TARGET_OPTION_OPTIMIZATION_TABLE
442 #define TARGET_OPTION_OPTIMIZATION_TABLE frv_option_optimization_table
443 #undef TARGET_INIT_BUILTINS
444 #define TARGET_INIT_BUILTINS frv_init_builtins
445 #undef TARGET_EXPAND_BUILTIN
446 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
447 #undef TARGET_INIT_LIBFUNCS
448 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
449 #undef TARGET_IN_SMALL_DATA_P
450 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
451 #undef TARGET_REGISTER_MOVE_COST
452 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
453 #undef TARGET_MEMORY_MOVE_COST
454 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
455 #undef TARGET_RTX_COSTS
456 #define TARGET_RTX_COSTS frv_rtx_costs
457 #undef TARGET_ASM_CONSTRUCTOR
458 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
459 #undef TARGET_ASM_DESTRUCTOR
460 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
462 #undef TARGET_ASM_OUTPUT_MI_THUNK
463 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
464 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
465 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
467 #undef TARGET_SCHED_ISSUE_RATE
468 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
470 #undef TARGET_LEGITIMIZE_ADDRESS
471 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
473 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
474 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
475 #undef TARGET_CANNOT_FORCE_CONST_MEM
476 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
478 #undef TARGET_HAVE_TLS
479 #define TARGET_HAVE_TLS HAVE_AS_TLS
481 #undef TARGET_STRUCT_VALUE_RTX
482 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
483 #undef TARGET_MUST_PASS_IN_STACK
484 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
485 #undef TARGET_PASS_BY_REFERENCE
486 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
487 #undef TARGET_ARG_PARTIAL_BYTES
488 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
489 #undef TARGET_FUNCTION_ARG
490 #define TARGET_FUNCTION_ARG frv_function_arg
491 #undef TARGET_FUNCTION_INCOMING_ARG
492 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
493 #undef TARGET_FUNCTION_ARG_ADVANCE
494 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
495 #undef TARGET_FUNCTION_ARG_BOUNDARY
496 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
498 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
499 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
500 #undef TARGET_SETUP_INCOMING_VARARGS
501 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
502 #undef TARGET_MACHINE_DEPENDENT_REORG
503 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
505 #undef TARGET_EXPAND_BUILTIN_VA_START
506 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
509 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
510 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
513 #undef TARGET_CLASS_LIKELY_SPILLED_P
514 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
516 #undef TARGET_SECONDARY_RELOAD
517 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
519 #undef TARGET_LEGITIMATE_ADDRESS_P
520 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
522 #undef TARGET_FRAME_POINTER_REQUIRED
523 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
525 #undef TARGET_CAN_ELIMINATE
526 #define TARGET_CAN_ELIMINATE frv_can_eliminate
528 #undef TARGET_CONDITIONAL_REGISTER_USAGE
529 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
531 #undef TARGET_TRAMPOLINE_INIT
532 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
534 #undef TARGET_FUNCTION_VALUE
535 #define TARGET_FUNCTION_VALUE frv_function_value
536 #undef TARGET_LIBCALL_VALUE
537 #define TARGET_LIBCALL_VALUE frv_libcall_value
539 struct gcc_target targetm
= TARGET_INITIALIZER
;
541 #define FRV_SYMBOL_REF_TLS_P(RTX) \
542 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
545 /* Any function call that satisfies the machine-independent
546 requirements is eligible on FR-V. */
549 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
550 tree exp ATTRIBUTE_UNUSED
)
555 /* Return true if SYMBOL is a small data symbol and relocation RELOC
556 can be used to access it directly in a load or store. */
558 static FRV_INLINE
bool
559 frv_small_data_reloc_p (rtx symbol
, int reloc
)
561 return (GET_CODE (symbol
) == SYMBOL_REF
562 && SYMBOL_REF_SMALL_P (symbol
)
563 && (!TARGET_FDPIC
|| flag_pic
== 1)
564 && (reloc
== R_FRV_GOTOFF12
|| reloc
== R_FRV_GPREL12
));
567 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
571 frv_const_unspec_p (rtx x
, struct frv_unspec
*unspec
)
573 if (GET_CODE (x
) == CONST
)
577 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
579 unspec
->offset
+= INTVAL (XEXP (x
, 1));
582 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOT
)
584 unspec
->symbol
= XVECEXP (x
, 0, 0);
585 unspec
->reloc
= INTVAL (XVECEXP (x
, 0, 1));
587 if (unspec
->offset
== 0)
590 if (frv_small_data_reloc_p (unspec
->symbol
, unspec
->reloc
)
591 && unspec
->offset
> 0
592 && unspec
->offset
< g_switch_value
)
599 /* Decide whether we can force certain constants to memory. If we
600 decide we can't, the caller should be able to cope with it in
603 We never allow constants to be forced into memory for TARGET_FDPIC.
604 This is necessary for several reasons:
606 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
607 target-independent code will try to force them into the constant
608 pool, thus leading to infinite recursion.
610 2. We can never introduce new constant pool references during reload.
611 Any such reference would require use of the pseudo FDPIC register.
613 3. We can't represent a constant added to a function pointer (which is
614 not the same as a pointer to a function+constant).
616 4. In many cases, it's more efficient to calculate the constant in-line. */
619 frv_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
,
620 rtx x ATTRIBUTE_UNUSED
)
626 frv_default_flags_for_cpu (void)
628 switch (frv_cpu_type
)
630 case FRV_CPU_GENERIC
:
631 return MASK_DEFAULT_FRV
;
634 return MASK_DEFAULT_FR550
;
638 return MASK_DEFAULT_FR500
;
641 return MASK_DEFAULT_FR450
;
645 return MASK_DEFAULT_FR400
;
649 return MASK_DEFAULT_SIMPLE
;
656 /* Implement TARGET_OPTION_OVERRIDE. */
659 frv_option_override (void)
664 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
666 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
667 linker about linking pic and non-pic code. */
670 if (!flag_pic
) /* -fPIC */
673 if (!global_options_set
.x_g_switch_value
) /* -G0 */
679 /* A C expression whose value is a register class containing hard
680 register REGNO. In general there is more than one such class;
681 choose a class which is "minimal", meaning that no smaller class
682 also contains the register. */
684 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
686 enum reg_class rclass
;
690 int gpr_reg
= regno
- GPR_FIRST
;
692 if (gpr_reg
== GR8_REG
)
695 else if (gpr_reg
== GR9_REG
)
698 else if (gpr_reg
== GR14_REG
)
699 rclass
= FDPIC_FPTR_REGS
;
701 else if (gpr_reg
== FDPIC_REGNO
)
704 else if ((gpr_reg
& 3) == 0)
707 else if ((gpr_reg
& 1) == 0)
714 else if (FPR_P (regno
))
716 int fpr_reg
= regno
- GPR_FIRST
;
717 if ((fpr_reg
& 3) == 0)
718 rclass
= QUAD_FPR_REGS
;
720 else if ((fpr_reg
& 1) == 0)
727 else if (regno
== LR_REGNO
)
730 else if (regno
== LCR_REGNO
)
733 else if (ICC_P (regno
))
736 else if (FCC_P (regno
))
739 else if (ICR_P (regno
))
742 else if (FCR_P (regno
))
745 else if (ACC_P (regno
))
747 int r
= regno
- ACC_FIRST
;
749 rclass
= QUAD_ACC_REGS
;
750 else if ((r
& 1) == 0)
751 rclass
= EVEN_ACC_REGS
;
756 else if (ACCG_P (regno
))
762 regno_reg_class
[regno
] = rclass
;
765 /* Check for small data option */
766 if (!global_options_set
.x_g_switch_value
&& !TARGET_LIBPIC
)
767 g_switch_value
= SDATA_DEFAULT_SIZE
;
769 /* There is no single unaligned SI op for PIC code. Sometimes we
770 need to use ".4byte" and sometimes we need to use ".picptr".
771 See frv_assemble_integer for details. */
772 if (flag_pic
|| TARGET_FDPIC
)
773 targetm
.asm_out
.unaligned_op
.si
= 0;
775 if ((target_flags_explicit
& MASK_LINKED_FP
) == 0)
776 target_flags
|= MASK_LINKED_FP
;
778 if ((target_flags_explicit
& MASK_OPTIMIZE_MEMBAR
) == 0)
779 target_flags
|= MASK_OPTIMIZE_MEMBAR
;
781 for (i
= 0; i
< ARRAY_SIZE (frv_unit_names
); i
++)
782 frv_unit_codes
[i
] = get_cpu_unit_code (frv_unit_names
[i
]);
784 for (i
= 0; i
< ARRAY_SIZE (frv_type_to_unit
); i
++)
785 frv_type_to_unit
[i
] = ARRAY_SIZE (frv_unit_codes
);
787 init_machine_status
= frv_init_machine_status
;
791 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
794 frv_string_begins_with (const_tree name
, const char *prefix
)
796 const int prefix_len
= strlen (prefix
);
798 /* Remember: NAME's length includes the null terminator. */
799 return (TREE_STRING_LENGTH (name
) > prefix_len
800 && strncmp (TREE_STRING_POINTER (name
), prefix
, prefix_len
) == 0);
803 /* Zero or more C statements that may conditionally modify two variables
804 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
805 been initialized from the two preceding macros.
807 This is necessary in case the fixed or call-clobbered registers depend on
810 You need not define this macro if it has no work to do.
812 If the usage of an entire class of registers depends on the target flags,
813 you may indicate this to GCC by using this macro to modify `fixed_regs' and
814 `call_used_regs' to 1 for each of the registers in the classes which should
815 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
816 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
818 (However, if this class is not included in `GENERAL_REGS' and all of the
819 insn patterns whose constraints permit this class are controlled by target
820 switches, then GCC will automatically avoid using these registers when the
821 target switches are opposed to them.) */
824 frv_conditional_register_usage (void)
828 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
829 fixed_regs
[i
] = call_used_regs
[i
] = 1;
831 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
832 fixed_regs
[i
] = call_used_regs
[i
] = 1;
834 /* Reserve the registers used for conditional execution. At present, we need
835 1 ICC and 1 ICR register. */
836 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
837 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
841 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
842 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
843 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
844 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
848 fixed_regs
[GPR_FIRST
+ 16] = fixed_regs
[GPR_FIRST
+ 17] =
849 call_used_regs
[GPR_FIRST
+ 16] = call_used_regs
[GPR_FIRST
+ 17] = 0;
852 /* If -fpic, SDA_BASE_REG is the PIC register. */
853 if (g_switch_value
== 0 && !flag_pic
)
854 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
857 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
863 * Compute the stack frame layout
866 * +---------------+-----------------------+-----------------------+
867 * |Register |type |caller-save/callee-save|
868 * +---------------+-----------------------+-----------------------+
869 * |GR0 |Zero register | - |
870 * |GR1 |Stack pointer(SP) | - |
871 * |GR2 |Frame pointer(FP) | - |
872 * |GR3 |Hidden parameter | caller save |
873 * |GR4-GR7 | - | caller save |
874 * |GR8-GR13 |Argument register | caller save |
875 * |GR14-GR15 | - | caller save |
876 * |GR16-GR31 | - | callee save |
877 * |GR32-GR47 | - | caller save |
878 * |GR48-GR63 | - | callee save |
879 * |FR0-FR15 | - | caller save |
880 * |FR16-FR31 | - | callee save |
881 * |FR32-FR47 | - | caller save |
882 * |FR48-FR63 | - | callee save |
883 * +---------------+-----------------------+-----------------------+
887 * SP-> |-----------------------------------|
889 * |-----------------------------------|
890 * | Register save area |
891 * |-----------------------------------|
892 * | Local variable save area |
893 * FP-> |-----------------------------------|
895 * |-----------------------------------|
896 * | Hidden parameter save area |
897 * |-----------------------------------|
898 * | Return address(LR) storage area |
899 * |-----------------------------------|
900 * | Padding for alignment |
901 * |-----------------------------------|
902 * | Register argument area |
903 * OLD SP-> |-----------------------------------|
905 * |-----------------------------------|
908 * Argument area/Parameter area:
910 * When a function is called, this area is used for argument transfer. When
911 * the argument is set up by the caller function, this area is referred to as
912 * the argument area. When the argument is referenced by the callee function,
913 * this area is referred to as the parameter area. The area is allocated when
914 * all arguments cannot be placed on the argument register at the time of
917 * Register save area:
919 * This is a register save area that must be guaranteed for the caller
920 * function. This area is not secured when the register save operation is not
923 * Local variable save area:
925 * This is the area for local variables and temporary variables.
929 * This area stores the FP value of the caller function.
931 * Hidden parameter save area:
933 * This area stores the start address of the return value storage
934 * area for a struct/union return function.
935 * When a struct/union is used as the return value, the caller
936 * function stores the return value storage area start address in
937 * register GR3 and passes it to the caller function.
938 * The callee function interprets the address stored in the GR3
939 * as the return value storage area start address.
940 * When register GR3 needs to be saved into memory, the callee
941 * function saves it in the hidden parameter save area. This
942 * area is not secured when the save operation is not needed.
944 * Return address(LR) storage area:
946 * This area saves the LR. The LR stores the address of a return to the caller
947 * function for the purpose of function calling.
949 * Argument register area:
951 * This area saves the argument register. This area is not secured when the
952 * save operation is not needed.
956 * Arguments, the count of which equals the count of argument registers (6
957 * words), are positioned in registers GR8 to GR13 and delivered to the callee
958 * function. When a struct/union return function is called, the return value
959 * area address is stored in register GR3. Arguments not placed in the
960 * argument registers will be stored in the stack argument area for transfer
961 * purposes. When an 8-byte type argument is to be delivered using registers,
962 * it is divided into two and placed in two registers for transfer. When
963 * argument registers must be saved to memory, the callee function secures an
964 * argument register save area in the stack. In this case, a continuous
965 * argument register save area must be established in the parameter area. The
966 * argument register save area must be allocated as needed to cover the size of
967 * the argument register to be saved. If the function has a variable count of
968 * arguments, it saves all argument registers in the argument register save
971 * Argument Extension Format:
973 * When an argument is to be stored in the stack, its type is converted to an
974 * extended type in accordance with the individual argument type. The argument
975 * is freed by the caller function after the return from the callee function is
978 * +-----------------------+---------------+------------------------+
979 * | Argument Type |Extended Type |Stack Storage Size(byte)|
980 * +-----------------------+---------------+------------------------+
982 * |signed char |int | 4 |
983 * |unsigned char |int | 4 |
984 * |[signed] short int |int | 4 |
985 * |unsigned short int |int | 4 |
986 * |[signed] int |No extension | 4 |
987 * |unsigned int |No extension | 4 |
988 * |[signed] long int |No extension | 4 |
989 * |unsigned long int |No extension | 4 |
990 * |[signed] long long int |No extension | 8 |
991 * |unsigned long long int |No extension | 8 |
992 * |float |double | 8 |
993 * |double |No extension | 8 |
994 * |long double |No extension | 8 |
995 * |pointer |No extension | 4 |
996 * |struct/union |- | 4 (*1) |
997 * +-----------------------+---------------+------------------------+
999 * When a struct/union is to be delivered as an argument, the caller copies it
1000 * to the local variable area and delivers the address of that area.
1004 * +-------------------------------+----------------------+
1005 * |Return Value Type |Return Value Interface|
1006 * +-------------------------------+----------------------+
1008 * |[signed|unsigned] char |GR8 |
1009 * |[signed|unsigned] short int |GR8 |
1010 * |[signed|unsigned] int |GR8 |
1011 * |[signed|unsigned] long int |GR8 |
1013 * |[signed|unsigned] long long int|GR8 & GR9 |
1015 * |double |GR8 & GR9 |
1016 * |long double |GR8 & GR9 |
1017 * |struct/union |(*1) |
1018 * +-------------------------------+----------------------+
1020 * When a struct/union is used as the return value, the caller function stores
1021 * the start address of the return value storage area into GR3 and then passes
1022 * it to the callee function. The callee function interprets GR3 as the start
1023 * address of the return value storage area. When this address needs to be
1024 * saved in memory, the callee function secures the hidden parameter save area
1025 * and saves the address in that area.
1029 frv_stack_info (void)
1031 static frv_stack_t info
, zero_info
;
1032 frv_stack_t
*info_ptr
= &info
;
1033 tree fndecl
= current_function_decl
;
1041 /* If we've already calculated the values and reload is complete,
1043 if (frv_stack_cache
)
1044 return frv_stack_cache
;
1046 /* Zero all fields. */
1049 /* Set up the register range information. */
1050 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
1051 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
1052 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
1053 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
1055 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
1056 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
1057 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
1058 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
1060 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
1061 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
1062 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
1063 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
1065 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
1066 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
1067 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
1068 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
1070 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
1071 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
1072 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
1074 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
1075 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
1076 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
1077 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
1078 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
1080 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
1081 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= FRV_STRUCT_VALUE_REGNUM
;
1082 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= FRV_STRUCT_VALUE_REGNUM
;
1083 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
1085 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
1086 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
1087 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
1088 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
1090 /* Determine if this is a stdarg function. If so, allocate space to store
1097 /* Find the last argument, and see if it is __builtin_va_alist. */
1098 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
1100 next_arg
= DECL_CHAIN (cur_arg
);
1101 if (next_arg
== (tree
)0)
1103 if (DECL_NAME (cur_arg
)
1104 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1112 /* Iterate over all of the register ranges. */
1113 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1115 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1116 int first
= reg_ptr
->first
;
1117 int last
= reg_ptr
->last
;
1119 int size_2words
= 0;
1122 /* Calculate which registers need to be saved & save area size. */
1126 for (regno
= first
; regno
<= last
; regno
++)
1128 if ((df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1129 || (crtl
->calls_eh_return
1130 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1131 || (!TARGET_FDPIC
&& flag_pic
1132 && crtl
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1134 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1135 size_1word
+= UNITS_PER_WORD
;
1140 /* Calculate whether we need to create a frame after everything else
1141 has been processed. */
1146 if (df_regs_ever_live_p (LR_REGNO
)
1148 /* This is set for __builtin_return_address, etc. */
1149 || cfun
->machine
->frame_needed
1150 || (TARGET_LINKED_FP
&& frame_pointer_needed
)
1151 || (!TARGET_FDPIC
&& flag_pic
1152 && crtl
->uses_pic_offset_table
))
1154 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1155 size_1word
+= UNITS_PER_WORD
;
1159 case STACK_REGS_STDARG
:
1162 /* If this is a stdarg function with a non varardic
1163 argument split between registers and the stack,
1164 adjust the saved registers downward. */
1165 last
-= (ADDR_ALIGN (crtl
->args
.pretend_args_size
, UNITS_PER_WORD
)
1168 for (regno
= first
; regno
<= last
; regno
++)
1170 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1171 size_1word
+= UNITS_PER_WORD
;
1174 info_ptr
->stdarg_size
= size_1word
;
1178 case STACK_REGS_STRUCT
:
1179 if (cfun
->returns_struct
)
1181 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1182 size_1word
+= UNITS_PER_WORD
;
1190 /* If this is a field, it only takes one word. */
1191 if (reg_ptr
->field_p
)
1192 size_1word
= UNITS_PER_WORD
;
1194 /* Determine which register pairs can be saved together. */
1195 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1197 for (regno
= first
; regno
< last
; regno
+= 2)
1199 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1201 size_2words
+= 2 * UNITS_PER_WORD
;
1202 size_1word
-= 2 * UNITS_PER_WORD
;
1203 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1204 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1209 reg_ptr
->size_1word
= size_1word
;
1210 reg_ptr
->size_2words
= size_2words
;
1212 if (! reg_ptr
->special_p
)
1214 info_ptr
->regs_size_1word
+= size_1word
;
1215 info_ptr
->regs_size_2words
+= size_2words
;
1220 /* Set up the sizes of each each field in the frame body, making the sizes
1221 of each be divisible by the size of a dword if dword operations might
1222 be used, or the size of a word otherwise. */
1223 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1225 info_ptr
->parameter_size
= ADDR_ALIGN (crtl
->outgoing_args_size
, alignment
);
1226 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1227 + info_ptr
->regs_size_1word
,
1229 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1231 info_ptr
->pretend_size
= crtl
->args
.pretend_args_size
;
1233 /* Work out the size of the frame, excluding the header. Both the frame
1234 body and register parameter area will be dword-aligned. */
1235 info_ptr
->total_size
1236 = (ADDR_ALIGN (info_ptr
->parameter_size
1237 + info_ptr
->regs_size
1238 + info_ptr
->vars_size
,
1240 + ADDR_ALIGN (info_ptr
->pretend_size
1241 + info_ptr
->stdarg_size
,
1242 2 * UNITS_PER_WORD
));
1244 /* See if we need to create a frame at all, if so add header area. */
1245 if (info_ptr
->total_size
> 0
1246 || frame_pointer_needed
1247 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1248 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1250 offset
= info_ptr
->parameter_size
;
1251 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1252 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1254 /* Calculate the offsets to save normal register pairs. */
1255 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1257 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1258 if (! reg_ptr
->special_p
)
1260 int first
= reg_ptr
->first
;
1261 int last
= reg_ptr
->last
;
1264 for (regno
= first
; regno
<= last
; regno
++)
1265 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1266 && regno
!= FRAME_POINTER_REGNUM
1267 && (regno
< FIRST_ARG_REGNUM
1268 || regno
> LAST_ARG_REGNUM
))
1270 info_ptr
->reg_offset
[regno
] = offset
;
1271 offset
+= 2 * UNITS_PER_WORD
;
1276 /* Calculate the offsets to save normal single registers. */
1277 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1279 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1280 if (! reg_ptr
->special_p
)
1282 int first
= reg_ptr
->first
;
1283 int last
= reg_ptr
->last
;
1286 for (regno
= first
; regno
<= last
; regno
++)
1287 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1288 && regno
!= FRAME_POINTER_REGNUM
1289 && (regno
< FIRST_ARG_REGNUM
1290 || regno
> LAST_ARG_REGNUM
))
1292 info_ptr
->reg_offset
[regno
] = offset
;
1293 offset
+= UNITS_PER_WORD
;
1298 /* Calculate the offset to save the local variables at. */
1299 offset
= ADDR_ALIGN (offset
, alignment
);
1300 if (info_ptr
->vars_size
)
1302 info_ptr
->vars_offset
= offset
;
1303 offset
+= info_ptr
->vars_size
;
1306 /* Align header to a dword-boundary. */
1307 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1309 /* Calculate the offsets in the fixed frame. */
1310 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1311 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1312 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1314 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1315 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1316 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1318 if (cfun
->returns_struct
)
1320 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1321 info_ptr
->reg_offset
[FRV_STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1322 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1325 /* Calculate the offsets to store the arguments passed in registers
1326 for stdarg functions. The register pairs are first and the single
1327 register if any is last. The register save area starts on a
1329 if (info_ptr
->stdarg_size
)
1331 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1332 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1335 /* Skip the header. */
1336 offset
+= 4 * UNITS_PER_WORD
;
1337 for (regno
= first
; regno
<= last
; regno
++)
1339 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1341 info_ptr
->reg_offset
[regno
] = offset
;
1342 offset
+= 2 * UNITS_PER_WORD
;
1344 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1346 info_ptr
->reg_offset
[regno
] = offset
;
1347 offset
+= UNITS_PER_WORD
;
1353 if (reload_completed
)
1354 frv_stack_cache
= info_ptr
;
1360 /* Print the information about the frv stack offsets, etc. when debugging. */
1363 frv_debug_stack (frv_stack_t
*info
)
1368 info
= frv_stack_info ();
1370 fprintf (stderr
, "\nStack information for function %s:\n",
1371 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1372 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1375 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1376 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1377 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1378 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1379 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1381 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1382 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1383 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1384 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1386 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1388 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1389 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1391 int first
= regs
->first
;
1392 int last
= regs
->last
;
1395 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1396 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1397 regs
->size_1word
, regs
->size_2words
);
1399 for (regno
= first
; regno
<= last
; regno
++)
1401 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1402 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1403 info
->reg_offset
[regno
]);
1405 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1406 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1407 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1410 fputc ('\n', stderr
);
1420 /* Used during final to control the packing of insns. The value is
1421 1 if the current instruction should be packed with the next one,
1422 0 if it shouldn't or -1 if packing is disabled altogether. */
1424 static int frv_insn_packing_flag
;
1426 /* True if the current function contains a far jump. */
1429 frv_function_contains_far_jump (void)
1431 rtx insn
= get_insns ();
1433 && !(GET_CODE (insn
) == JUMP_INSN
1434 /* Ignore tablejump patterns. */
1435 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
1436 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
1437 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1438 insn
= NEXT_INSN (insn
);
1439 return (insn
!= NULL
);
1442 /* For the FRV, this function makes sure that a function with far jumps
1443 will return correctly. It also does the VLIW packing. */
1446 frv_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1448 /* If no frame was created, check whether the function uses a call
1449 instruction to implement a far jump. If so, save the link in gr3 and
1450 replace all returns to LR with returns to GR3. GR3 is used because it
1451 is call-clobbered, because is not available to the register allocator,
1452 and because all functions that take a hidden argument pointer will have
1454 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1458 /* Just to check that the above comment is true. */
1459 gcc_assert (!df_regs_ever_live_p (GPR_FIRST
+ 3));
1461 /* Generate the instruction that saves the link register. */
1462 fprintf (file
, "\tmovsg lr,gr3\n");
1464 /* Replace the LR with GR3 in *return_internal patterns. The insn
1465 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1466 simply emit a different assembly directive because bralr and jmpl
1467 execute in different units. */
1468 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1469 if (GET_CODE (insn
) == JUMP_INSN
)
1471 rtx pattern
= PATTERN (insn
);
1472 if (GET_CODE (pattern
) == PARALLEL
1473 && XVECLEN (pattern
, 0) >= 2
1474 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1475 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1477 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1478 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1479 SET_REGNO (address
, GPR_FIRST
+ 3);
1486 /* Allow the garbage collector to free the nops created by frv_reorg. */
1487 memset (frv_nops
, 0, sizeof (frv_nops
));
1491 /* Return the next available temporary register in a given class. */
1494 frv_alloc_temp_reg (
1495 frv_tmp_reg_t
*info
, /* which registers are available */
1496 enum reg_class rclass
, /* register class desired */
1497 enum machine_mode mode
, /* mode to allocate register with */
1498 int mark_as_used
, /* register not available after allocation */
1499 int no_abort
) /* return NULL instead of aborting */
1501 int regno
= info
->next_reg
[ (int)rclass
];
1502 int orig_regno
= regno
;
1503 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)rclass
];
1508 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1509 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1512 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1514 if (regno
== orig_regno
)
1516 gcc_assert (no_abort
);
1521 nr
= HARD_REGNO_NREGS (regno
, mode
);
1522 info
->next_reg
[ (int)rclass
] = regno
+ nr
;
1525 for (i
= 0; i
< nr
; i
++)
1526 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1528 return gen_rtx_REG (mode
, regno
);
1532 /* Return an rtx with the value OFFSET, which will either be a register or a
1533 signed 12-bit integer. It can be used as the second operand in an "add"
1534 instruction, or as the index in a load or store.
1536 The function returns a constant rtx if OFFSET is small enough, otherwise
1537 it loads the constant into register OFFSET_REGNO and returns that. */
1539 frv_frame_offset_rtx (int offset
)
1541 rtx offset_rtx
= GEN_INT (offset
);
1542 if (IN_RANGE (offset
, -2048, 2047))
1546 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1547 if (IN_RANGE (offset
, -32768, 32767))
1548 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1551 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1552 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1558 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1559 prologue and epilogue uses such expressions to access the stack. */
1561 frv_frame_mem (enum machine_mode mode
, rtx base
, int offset
)
1563 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1565 frv_frame_offset_rtx (offset
)));
1568 /* Generate a frame-related expression:
1570 (set REG (mem (plus (sp) (const_int OFFSET)))).
1572 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1573 instructions. Marking the expressions as frame-related is superfluous if
1574 the note contains just a single set. But if the note contains a PARALLEL
1575 or SEQUENCE that has several sets, each set must be individually marked
1576 as frame-related. */
1578 frv_dwarf_store (rtx reg
, int offset
)
1580 rtx set
= gen_rtx_SET (VOIDmode
,
1581 gen_rtx_MEM (GET_MODE (reg
),
1582 plus_constant (stack_pointer_rtx
,
1585 RTX_FRAME_RELATED_P (set
) = 1;
1589 /* Emit a frame-related instruction whose pattern is PATTERN. The
1590 instruction is the last in a sequence that cumulatively performs the
1591 operation described by DWARF_PATTERN. The instruction is marked as
1592 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1595 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1597 rtx insn
= emit_insn (pattern
);
1598 RTX_FRAME_RELATED_P (insn
) = 1;
1599 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1604 /* Emit instructions that transfer REG to or from the memory location (sp +
1605 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1606 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1607 function to store registers and only the epilogue uses it to load them.
1609 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1610 The generated instruction will use BASE as its base register. BASE may
1611 simply be the stack pointer, but if several accesses are being made to a
1612 region far away from the stack pointer, it may be more efficient to set
1613 up a temporary instead.
1615 Store instructions will be frame-related and will be annotated with the
1616 overall effect of the store. Load instructions will be followed by a
1617 (use) to prevent later optimizations from zapping them.
1619 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1620 as a temporary in such cases. */
1622 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1624 enum machine_mode mode
= GET_MODE (reg
);
1625 rtx mem
= frv_frame_mem (mode
,
1627 stack_offset
- accessor
->base_offset
);
1629 if (accessor
->op
== FRV_LOAD
)
1631 if (SPR_P (REGNO (reg
)))
1633 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1634 emit_insn (gen_rtx_SET (VOIDmode
, temp
, mem
));
1635 emit_insn (gen_rtx_SET (VOIDmode
, reg
, temp
));
1639 /* We cannot use reg+reg addressing for DImode access. */
1641 && GET_CODE (XEXP (mem
, 0)) == PLUS
1642 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1643 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1645 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1647 emit_move_insn (temp
,
1648 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1649 XEXP (XEXP (mem
, 0), 1)));
1650 mem
= gen_rtx_MEM (DImode
, temp
);
1652 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1658 if (SPR_P (REGNO (reg
)))
1660 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1661 emit_insn (gen_rtx_SET (VOIDmode
, temp
, reg
));
1662 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, temp
),
1663 frv_dwarf_store (reg
, stack_offset
));
1665 else if (mode
== DImode
)
1667 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1668 with a separate save for each register. */
1669 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1670 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1671 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1672 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1674 /* Also we cannot use reg+reg addressing. */
1675 if (GET_CODE (XEXP (mem
, 0)) == PLUS
1676 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1677 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1679 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1680 emit_move_insn (temp
,
1681 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1682 XEXP (XEXP (mem
, 0), 1)));
1683 mem
= gen_rtx_MEM (DImode
, temp
);
1686 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1687 gen_rtx_PARALLEL (VOIDmode
,
1688 gen_rtvec (2, set1
, set2
)));
1691 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1692 frv_dwarf_store (reg
, stack_offset
));
1696 /* A function that uses frv_frame_access to transfer a group of registers to
1697 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1698 is the stack information generated by frv_stack_info, and REG_SET is the
1699 number of the register set to transfer. */
1701 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1705 frv_stack_regs_t
*regs_info
;
1708 regs_info
= &info
->regs
[reg_set
];
1709 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1710 if (info
->save_p
[regno
])
1711 frv_frame_access (accessor
,
1712 info
->save_p
[regno
] == REG_SAVE_2WORDS
1713 ? gen_rtx_REG (DImode
, regno
)
1714 : gen_rtx_REG (SImode
, regno
),
1715 info
->reg_offset
[regno
]);
1718 /* Save or restore callee-saved registers that are kept outside the frame
1719 header. The function saves the registers if OP is FRV_STORE and restores
1720 them if OP is FRV_LOAD. INFO is the stack information generated by
1723 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1725 frv_frame_accessor_t accessor
;
1728 accessor
.base
= stack_pointer_rtx
;
1729 accessor
.base_offset
= 0;
1730 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1731 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1732 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1736 /* Called after register allocation to add any instructions needed for the
1737 prologue. Using a prologue insn is favored compared to putting all of the
1738 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1739 it allows the scheduler to intermix instructions with the saves of
1740 the caller saved registers. In some cases, it might be necessary
1741 to emit a barrier instruction as the last insn to prevent such
1744 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1745 so that the debug info generation code can handle them properly. */
1747 frv_expand_prologue (void)
1749 frv_stack_t
*info
= frv_stack_info ();
1750 rtx sp
= stack_pointer_rtx
;
1751 rtx fp
= frame_pointer_rtx
;
1752 frv_frame_accessor_t accessor
;
1754 if (TARGET_DEBUG_STACK
)
1755 frv_debug_stack (info
);
1757 if (info
->total_size
== 0)
1760 /* We're interested in three areas of the frame here:
1762 A: the register save area
1764 C: the header after B
1766 If the frame pointer isn't used, we'll have to set up A, B and C
1767 using the stack pointer. If the frame pointer is used, we'll access
1771 B: set up using sp or a temporary (see below)
1774 We set up B using the stack pointer if the frame is small enough.
1775 Otherwise, it's more efficient to copy the old stack pointer into a
1776 temporary and use that.
1778 Note that it's important to make sure the prologue and epilogue use the
1779 same registers to access A and C, since doing otherwise will confuse
1780 the aliasing code. */
1782 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1783 isn't used, the same method will serve for C. */
1784 accessor
.op
= FRV_STORE
;
1785 if (frame_pointer_needed
&& info
->total_size
> 2048)
1787 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1788 accessor
.base_offset
= info
->total_size
;
1789 emit_insn (gen_movsi (accessor
.base
, sp
));
1793 accessor
.base
= stack_pointer_rtx
;
1794 accessor
.base_offset
= 0;
1797 /* Allocate the stack space. */
1799 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1800 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1802 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1805 gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1808 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1809 and point the new one to that location. */
1810 if (frame_pointer_needed
)
1812 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1814 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1815 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1817 rtx asm_src
= plus_constant (accessor
.base
,
1818 fp_offset
- accessor
.base_offset
);
1819 rtx dwarf_src
= plus_constant (sp
, fp_offset
);
1821 /* Store the old frame pointer at (sp + FP_OFFSET). */
1822 frv_frame_access (&accessor
, fp
, fp_offset
);
1824 /* Set up the new frame pointer. */
1825 frv_frame_insn (gen_rtx_SET (VOIDmode
, fp
, asm_src
),
1826 gen_rtx_SET (VOIDmode
, fp
, dwarf_src
));
1828 /* Access region C from the frame pointer. */
1830 accessor
.base_offset
= fp_offset
;
1833 /* Set up region C. */
1834 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1835 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1836 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1838 /* Set up region A. */
1839 frv_frame_access_standard_regs (FRV_STORE
, info
);
1841 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1842 scheduler from moving loads before the stores saving the registers. */
1843 if (info
->stdarg_size
> 0)
1844 emit_insn (gen_blockage ());
1846 /* Set up pic register/small data register for this function. */
1847 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
1848 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1849 gen_rtx_REG (Pmode
, LR_REGNO
),
1850 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1854 /* Under frv, all of the work is done via frv_expand_epilogue, but
1855 this function provides a convenient place to do cleanup. */
1858 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
1859 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1861 frv_stack_cache
= (frv_stack_t
*)0;
1863 /* Zap last used registers for conditional execution. */
1864 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1866 /* Release the bitmap of created insns. */
1867 BITMAP_FREE (frv_ifcvt
.scratch_insns_bitmap
);
1871 /* Called after register allocation to add any instructions needed for the
1872 epilogue. Using an epilogue insn is favored compared to putting all of the
1873 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1874 it allows the scheduler to intermix instructions with the saves of
1875 the caller saved registers. In some cases, it might be necessary
1876 to emit a barrier instruction as the last insn to prevent such
1880 frv_expand_epilogue (bool emit_return
)
1882 frv_stack_t
*info
= frv_stack_info ();
1883 rtx fp
= frame_pointer_rtx
;
1884 rtx sp
= stack_pointer_rtx
;
1888 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1890 /* Restore the stack pointer to its original value if alloca or the like
1892 if (! current_function_sp_is_unchanging
)
1893 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1895 /* Restore the callee-saved registers that were used in this function. */
1896 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1898 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1899 no return instruction should be emitted. */
1900 if (info
->save_p
[LR_REGNO
])
1905 /* Use the same method to access the link register's slot as we did in
1906 the prologue. In other words, use the frame pointer if available,
1907 otherwise use the stack pointer.
1909 LR_OFFSET is the offset of the link register's slot from the start
1910 of the frame and MEM is a memory rtx for it. */
1911 lr_offset
= info
->reg_offset
[LR_REGNO
];
1912 if (frame_pointer_needed
)
1913 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1915 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1917 /* Load the old link register into a GPR. */
1918 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1919 emit_insn (gen_rtx_SET (VOIDmode
, return_addr
, mem
));
1922 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1924 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1925 the load is preserved. */
1926 if (frame_pointer_needed
)
1928 emit_insn (gen_rtx_SET (VOIDmode
, fp
, gen_rtx_MEM (Pmode
, fp
)));
1932 /* Deallocate the stack frame. */
1933 if (info
->total_size
!= 0)
1935 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1936 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1939 /* If this function uses eh_return, add the final stack adjustment now. */
1940 if (crtl
->calls_eh_return
)
1941 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1944 emit_jump_insn (gen_epilogue_return (return_addr
));
1947 rtx lr
= return_addr
;
1949 if (REGNO (return_addr
) != LR_REGNO
)
1951 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1952 emit_move_insn (lr
, return_addr
);
1960 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1963 frv_asm_output_mi_thunk (FILE *file
,
1964 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1965 HOST_WIDE_INT delta
,
1966 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1969 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1970 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1971 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1972 const char *parallel
= (frv_issue_rate () > 1 ? ".p" : "");
1974 /* Do the add using an addi if possible. */
1975 if (IN_RANGE (delta
, -2048, 2047))
1976 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1979 const char *const name_add
= reg_names
[TEMP_REGNO
];
1980 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1981 parallel
, delta
, name_add
);
1982 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1984 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1989 const char *name_pic
= reg_names
[FDPIC_REGNO
];
1990 name_jmp
= reg_names
[FDPIC_FPTR_REGNO
];
1994 fprintf (file
, "\tsethi%s #gotofffuncdeschi(", parallel
);
1995 assemble_name (file
, name_func
);
1996 fprintf (file
, "),%s\n", name_jmp
);
1998 fprintf (file
, "\tsetlo #gotofffuncdesclo(");
1999 assemble_name (file
, name_func
);
2000 fprintf (file
, "),%s\n", name_jmp
);
2002 fprintf (file
, "\tldd @(%s,%s), %s\n", name_jmp
, name_pic
, name_jmp
);
2006 fprintf (file
, "\tlddo @(%s,#gotofffuncdesc12(", name_pic
);
2007 assemble_name (file
, name_func
);
2008 fprintf (file
, "\t)), %s\n", name_jmp
);
2013 fprintf (file
, "\tsethi%s #hi(", parallel
);
2014 assemble_name (file
, name_func
);
2015 fprintf (file
, "),%s\n", name_jmp
);
2017 fprintf (file
, "\tsetlo #lo(");
2018 assemble_name (file
, name_func
);
2019 fprintf (file
, "),%s\n", name_jmp
);
2023 /* Use JUMP_REGNO as a temporary PIC register. */
2024 const char *name_lr
= reg_names
[LR_REGNO
];
2025 const char *name_gppic
= name_jmp
;
2026 const char *name_tmp
= reg_names
[TEMP_REGNO
];
2028 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
2029 fprintf (file
, "\tcall 1f\n");
2030 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
2031 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
2032 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
2033 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
2034 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
2036 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
2037 assemble_name (file
, name_func
);
2038 fprintf (file
, "),%s\n", name_tmp
);
2040 fprintf (file
, "\tsetlo #gprello(");
2041 assemble_name (file
, name_func
);
2042 fprintf (file
, "),%s\n", name_tmp
);
2044 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
2047 /* Jump to the function address. */
2048 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
2053 /* On frv, create a frame whenever we need to create stack. */
2056 frv_frame_pointer_required (void)
2058 /* If we forgoing the usual linkage requirements, we only need
2059 a frame pointer if the stack pointer might change. */
2060 if (!TARGET_LINKED_FP
)
2061 return !current_function_sp_is_unchanging
;
2063 if (! current_function_is_leaf
)
2066 if (get_frame_size () != 0)
2072 if (!current_function_sp_is_unchanging
)
2075 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
2081 if (cfun
->machine
->frame_needed
)
2088 /* Worker function for TARGET_CAN_ELIMINATE. */
2091 frv_can_eliminate (const int from
, const int to
)
2093 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
2094 ? ! frame_pointer_needed
2098 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2099 initial difference between the specified pair of registers. This macro must
2100 be defined if `ELIMINABLE_REGS' is defined. */
2102 /* See frv_stack_info for more details on the frv stack frame. */
2105 frv_initial_elimination_offset (int from
, int to
)
2107 frv_stack_t
*info
= frv_stack_info ();
2110 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2111 ret
= info
->total_size
- info
->pretend_size
;
2113 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2114 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
2116 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2117 ret
= (info
->total_size
2118 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2119 - info
->pretend_size
);
2124 if (TARGET_DEBUG_STACK
)
2125 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2126 reg_names
[from
], reg_names
[to
], ret
);
2132 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2135 frv_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
2136 enum machine_mode mode
,
2137 tree type ATTRIBUTE_UNUSED
,
2141 if (TARGET_DEBUG_ARG
)
2143 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2144 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2148 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2151 frv_expand_builtin_saveregs (void)
2153 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2155 if (TARGET_DEBUG_ARG
)
2156 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2159 return gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2163 /* Expand __builtin_va_start to do the va_start macro. */
2166 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
2169 int num
= crtl
->args
.info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2171 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2172 GEN_INT (UNITS_PER_WORD
* num
));
2174 if (TARGET_DEBUG_ARG
)
2176 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2177 crtl
->args
.info
, num
);
2179 debug_rtx (nextarg
);
2182 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2183 fold_convert (TREE_TYPE (valist
),
2184 make_tree (sizetype
, nextarg
)));
2185 TREE_SIDE_EFFECTS (t
) = 1;
2187 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2191 /* Expand a block move operation, and return 1 if successful. Return 0
2192 if we should let the compiler generate normal code.
2194 operands[0] is the destination
2195 operands[1] is the source
2196 operands[2] is the length
2197 operands[3] is the alignment */
2199 /* Maximum number of loads to do before doing the stores */
2200 #ifndef MAX_MOVE_REG
2201 #define MAX_MOVE_REG 4
2204 /* Maximum number of total loads to do. */
2205 #ifndef TOTAL_MOVE_REG
2206 #define TOTAL_MOVE_REG 8
2210 frv_expand_block_move (rtx operands
[])
2212 rtx orig_dest
= operands
[0];
2213 rtx orig_src
= operands
[1];
2214 rtx bytes_rtx
= operands
[2];
2215 rtx align_rtx
= operands
[3];
2216 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2229 rtx stores
[MAX_MOVE_REG
];
2231 enum machine_mode mode
;
2233 /* If this is not a fixed size move, just call memcpy. */
2237 /* This should be a fixed size alignment. */
2238 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2240 align
= INTVAL (align_rtx
);
2242 /* Anything to move? */
2243 bytes
= INTVAL (bytes_rtx
);
2247 /* Don't support real large moves. */
2248 if (bytes
> TOTAL_MOVE_REG
*align
)
2251 /* Move the address into scratch registers. */
2252 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2253 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2255 num_reg
= offset
= 0;
2256 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2258 /* Calculate the correct offset for src/dest. */
2262 dest_addr
= dest_reg
;
2266 src_addr
= plus_constant (src_reg
, offset
);
2267 dest_addr
= plus_constant (dest_reg
, offset
);
2270 /* Generate the appropriate load and store, saving the stores
2272 if (bytes
>= 4 && align
>= 4)
2274 else if (bytes
>= 2 && align
>= 2)
2279 move_bytes
= GET_MODE_SIZE (mode
);
2280 tmp_reg
= gen_reg_rtx (mode
);
2281 src_mem
= change_address (orig_src
, mode
, src_addr
);
2282 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2283 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
, src_mem
));
2284 stores
[num_reg
++] = gen_rtx_SET (VOIDmode
, dest_mem
, tmp_reg
);
2286 if (num_reg
>= MAX_MOVE_REG
)
2288 for (i
= 0; i
< num_reg
; i
++)
2289 emit_insn (stores
[i
]);
2294 for (i
= 0; i
< num_reg
; i
++)
2295 emit_insn (stores
[i
]);
2301 /* Expand a block clear operation, and return 1 if successful. Return 0
2302 if we should let the compiler generate normal code.
2304 operands[0] is the destination
2305 operands[1] is the length
2306 operands[3] is the alignment */
2309 frv_expand_block_clear (rtx operands
[])
2311 rtx orig_dest
= operands
[0];
2312 rtx bytes_rtx
= operands
[1];
2313 rtx align_rtx
= operands
[3];
2314 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2322 enum machine_mode mode
;
2324 /* If this is not a fixed size move, just call memcpy. */
2328 /* This should be a fixed size alignment. */
2329 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2331 align
= INTVAL (align_rtx
);
2333 /* Anything to move? */
2334 bytes
= INTVAL (bytes_rtx
);
2338 /* Don't support real large clears. */
2339 if (bytes
> TOTAL_MOVE_REG
*align
)
2342 /* Move the address into a scratch register. */
2343 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2346 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2348 /* Calculate the correct offset for src/dest. */
2349 dest_addr
= ((offset
== 0)
2351 : plus_constant (dest_reg
, offset
));
2353 /* Generate the appropriate store of gr0. */
2354 if (bytes
>= 4 && align
>= 4)
2356 else if (bytes
>= 2 && align
>= 2)
2361 clear_bytes
= GET_MODE_SIZE (mode
);
2362 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2363 emit_insn (gen_rtx_SET (VOIDmode
, dest_mem
, const0_rtx
));
2370 /* The following variable is used to output modifiers of assembler
2371 code of the current output insn. */
2373 static rtx
*frv_insn_operands
;
2375 /* The following function is used to add assembler insn code suffix .p
2376 if it is necessary. */
2379 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2383 if (frv_insn_packing_flag
<= 0)
2386 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2389 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2390 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2392 int letter
= *ptr
++;
2395 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2396 while ((c
= *ptr
) >= '0' && c
<= '9')
2408 /* Set up the packing bit for the current output insn. Note that this
2409 function is not called for asm insns. */
2412 frv_final_prescan_insn (rtx insn
, rtx
*opvec
,
2413 int noperands ATTRIBUTE_UNUSED
)
2417 if (frv_insn_packing_flag
>= 0)
2419 frv_insn_operands
= opvec
;
2420 frv_insn_packing_flag
= PACKING_FLAG_P (insn
);
2422 else if (recog_memoized (insn
) >= 0
2423 && get_attr_acc_group (insn
) == ACC_GROUP_ODD
)
2424 /* Packing optimizations have been disabled, but INSN can only
2425 be issued in M1. Insert an mnop in M0. */
2426 fprintf (asm_out_file
, "\tmnop.p\n");
2432 /* A C expression whose value is RTL representing the address in a stack frame
2433 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2434 an RTL expression for the address of the stack frame itself.
2436 If you don't define this macro, the default is to return the value of
2437 FRAMEADDR--that is, the stack frame address is also the address of the stack
2438 word that points to the previous frame. */
2440 /* The default is correct, but we need to make sure the frame gets created. */
2442 frv_dynamic_chain_address (rtx frame
)
2444 cfun
->machine
->frame_needed
= 1;
2449 /* A C expression whose value is RTL representing the value of the return
2450 address for the frame COUNT steps up from the current frame, after the
2451 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2452 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2455 The value of the expression must always be the correct address when COUNT is
2456 zero, but may be `NULL_RTX' if there is not way to determine the return
2457 address of other frames. */
2460 frv_return_addr_rtx (int count
, rtx frame
)
2464 cfun
->machine
->frame_needed
= 1;
2465 return gen_rtx_MEM (Pmode
, plus_constant (frame
, 8));
2468 /* Given a memory reference MEMREF, interpret the referenced memory as
2469 an array of MODE values, and return a reference to the element
2470 specified by INDEX. Assume that any pre-modification implicit in
2471 MEMREF has already happened.
2473 MEMREF must be a legitimate operand for modes larger than SImode.
2474 frv_legitimate_address_p forbids register+register addresses, which
2475 this function cannot handle. */
2477 frv_index_memory (rtx memref
, enum machine_mode mode
, int index
)
2479 rtx base
= XEXP (memref
, 0);
2480 if (GET_CODE (base
) == PRE_MODIFY
)
2481 base
= XEXP (base
, 0);
2482 return change_address (memref
, mode
,
2483 plus_constant (base
, index
* GET_MODE_SIZE (mode
)));
2487 /* Print a memory address as an operand to reference that memory location. */
2489 frv_print_operand_address (FILE * stream
, rtx x
)
2491 if (GET_CODE (x
) == MEM
)
2494 switch (GET_CODE (x
))
2497 fputs (reg_names
[ REGNO (x
)], stream
);
2501 fprintf (stream
, "%ld", (long) INTVAL (x
));
2505 assemble_name (stream
, XSTR (x
, 0));
2510 output_addr_const (stream
, x
);
2514 /* Poorly constructed asm statements can trigger this alternative.
2515 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2516 frv_print_operand_memory_reference (stream
, x
, 0);
2523 fatal_insn ("bad insn to frv_print_operand_address:", x
);
2528 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2530 int regno
= true_regnum (x
);
2532 fputs (reg_names
[regno
], stream
);
2534 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x
);
2537 /* Print a memory reference suitable for the ld/st instructions. */
2540 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2542 struct frv_unspec unspec
;
2546 switch (GET_CODE (x
))
2553 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2555 x1
= XEXP (XEXP (x
, 1), 1);
2565 if (GET_CODE (x0
) == CONST_INT
)
2573 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2582 else if (GET_CODE (x1
) != CONST_INT
)
2583 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2586 fputs ("@(", stream
);
2588 fputs (reg_names
[GPR_R0
], stream
);
2589 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2590 frv_print_operand_memory_reference_reg (stream
, x0
);
2592 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2594 fputs (",", stream
);
2596 fputs (reg_names
[GPR_R0
], stream
);
2600 switch (GET_CODE (x1
))
2604 frv_print_operand_memory_reference_reg (stream
, x1
);
2608 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2612 if (!frv_const_unspec_p (x1
, &unspec
))
2613 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1
);
2614 frv_output_const_unspec (stream
, &unspec
);
2618 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2622 fputs (")", stream
);
2626 /* Return 2 for likely branches and 0 for non-likely branches */
2628 #define FRV_JUMP_LIKELY 2
2629 #define FRV_JUMP_NOT_LIKELY 0
2632 frv_print_operand_jump_hint (rtx insn
)
2637 HOST_WIDE_INT prob
= -1;
2638 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2640 gcc_assert (GET_CODE (insn
) == JUMP_INSN
);
2642 /* Assume any non-conditional jump is likely. */
2643 if (! any_condjump_p (insn
))
2644 ret
= FRV_JUMP_LIKELY
;
2648 labelref
= condjump_label (insn
);
2651 rtx label
= XEXP (labelref
, 0);
2652 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2657 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2659 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2663 prob
= INTVAL (XEXP (note
, 0));
2664 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2666 : FRV_JUMP_NOT_LIKELY
);
2678 case UNKNOWN
: direction
= "unknown jump direction"; break;
2679 case BACKWARD
: direction
= "jump backward"; break;
2680 case FORWARD
: direction
= "jump forward"; break;
2684 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2685 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2686 (long)INSN_UID (insn
), direction
, (long)prob
,
2687 (long)REG_BR_PROB_BASE
, ret
);
2695 /* Return the comparison operator to use for CODE given that the ICC
2699 comparison_string (enum rtx_code code
, rtx op0
)
2701 bool is_nz_p
= GET_MODE (op0
) == CC_NZmode
;
2704 default: output_operand_lossage ("bad condition code");
2705 case EQ
: return "eq";
2706 case NE
: return "ne";
2707 case LT
: return is_nz_p
? "n" : "lt";
2708 case LE
: return "le";
2709 case GT
: return "gt";
2710 case GE
: return is_nz_p
? "p" : "ge";
2711 case LTU
: return is_nz_p
? "no" : "c";
2712 case LEU
: return is_nz_p
? "eq" : "ls";
2713 case GTU
: return is_nz_p
? "ne" : "hi";
2714 case GEU
: return is_nz_p
? "ra" : "nc";
2718 /* Print an operand to an assembler instruction.
2720 `%' followed by a letter and a digit says to output an operand in an
2721 alternate fashion. Four letters have standard, built-in meanings
2722 described below. The hook `TARGET_PRINT_OPERAND' can define
2723 additional letters with nonstandard meanings.
2725 `%cDIGIT' can be used to substitute an operand that is a constant value
2726 without the syntax that normally indicates an immediate operand.
2728 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2731 `%aDIGIT' can be used to substitute an operand as if it were a memory
2732 reference, with the actual operand treated as the address. This may be
2733 useful when outputting a "load address" instruction, because often the
2734 assembler syntax for such an instruction requires you to write the operand
2735 as if it were a memory reference.
2737 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2739 `%=' outputs a number which is unique to each instruction in the entire
2740 compilation. This is useful for making local labels to be referred to more
2741 than once in a single template that generates multiple assembler
2744 `%' followed by a punctuation character specifies a substitution that
2745 does not use an operand. Only one case is standard: `%%' outputs a
2746 `%' into the assembler code. Other nonstandard cases can be defined
2747 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2748 punctuation characters are valid with the
2749 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2752 frv_print_operand (FILE * file
, rtx x
, int code
)
2754 struct frv_unspec unspec
;
2755 HOST_WIDE_INT value
;
2758 if (code
!= 0 && !ISALPHA (code
))
2761 else if (GET_CODE (x
) == CONST_INT
)
2764 else if (GET_CODE (x
) == CONST_DOUBLE
)
2766 if (GET_MODE (x
) == SFmode
)
2771 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2772 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2776 else if (GET_MODE (x
) == VOIDmode
)
2777 value
= CONST_DOUBLE_LOW (x
);
2780 fatal_insn ("bad insn in frv_print_operand, bad const_double", x
);
2791 fputs (reg_names
[GPR_R0
], file
);
2795 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2799 /* Output small data area base register (gr16). */
2800 fputs (reg_names
[SDA_BASE_REG
], file
);
2804 /* Output pic register (gr17). */
2805 fputs (reg_names
[PIC_REGNO
], file
);
2809 /* Output the temporary integer CCR register. */
2810 fputs (reg_names
[ICR_TEMP
], file
);
2814 /* Output the temporary integer CC register. */
2815 fputs (reg_names
[ICC_TEMP
], file
);
2818 /* case 'a': print an address. */
2821 /* Print appropriate test for integer branch false operation. */
2822 fputs (comparison_string (reverse_condition (GET_CODE (x
)),
2823 XEXP (x
, 0)), file
);
2827 /* Print appropriate test for integer branch true operation. */
2828 fputs (comparison_string (GET_CODE (x
), XEXP (x
, 0)), file
);
2832 /* Print 1 for a NE and 0 for an EQ to give the final argument
2833 for a conditional instruction. */
2834 if (GET_CODE (x
) == NE
)
2837 else if (GET_CODE (x
) == EQ
)
2841 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x
);
2845 /* Print appropriate test for floating point branch false operation. */
2846 switch (GET_CODE (x
))
2849 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x
);
2851 case EQ
: fputs ("ne", file
); break;
2852 case NE
: fputs ("eq", file
); break;
2853 case LT
: fputs ("uge", file
); break;
2854 case LE
: fputs ("ug", file
); break;
2855 case GT
: fputs ("ule", file
); break;
2856 case GE
: fputs ("ul", file
); break;
2861 /* Print appropriate test for floating point branch true operation. */
2862 switch (GET_CODE (x
))
2865 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x
);
2867 case EQ
: fputs ("eq", file
); break;
2868 case NE
: fputs ("ne", file
); break;
2869 case LT
: fputs ("lt", file
); break;
2870 case LE
: fputs ("le", file
); break;
2871 case GT
: fputs ("gt", file
); break;
2872 case GE
: fputs ("ge", file
); break;
2877 /* Print appropriate GOT function. */
2878 if (GET_CODE (x
) != CONST_INT
)
2879 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x
);
2880 fputs (unspec_got_name (INTVAL (x
)), file
);
2884 /* Print 'i' if the operand is a constant, or is a memory reference that
2886 if (GET_CODE (x
) == MEM
)
2887 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2888 ? XEXP (XEXP (x
, 0), 1)
2890 else if (GET_CODE (x
) == PLUS
)
2893 switch (GET_CODE (x
))
2907 /* For jump instructions, print 'i' if the operand is a constant or
2908 is an expression that adds a constant. */
2909 if (GET_CODE (x
) == CONST_INT
)
2914 if (GET_CODE (x
) == CONST_INT
2915 || (GET_CODE (x
) == PLUS
2916 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2917 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2923 /* Print the lower register of a double word register pair */
2924 if (GET_CODE (x
) == REG
)
2925 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2927 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x
);
2930 /* case 'l': print a LABEL_REF. */
2934 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2935 for the second word of double memory operations. */
2936 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2937 switch (GET_CODE (x
))
2940 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x
);
2943 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2951 frv_print_operand_memory_reference (file
, x
, offset
);
2957 /* Print the opcode of a command. */
2958 switch (GET_CODE (x
))
2961 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x
);
2963 case PLUS
: fputs ("add", file
); break;
2964 case MINUS
: fputs ("sub", file
); break;
2965 case AND
: fputs ("and", file
); break;
2966 case IOR
: fputs ("or", file
); break;
2967 case XOR
: fputs ("xor", file
); break;
2968 case ASHIFT
: fputs ("sll", file
); break;
2969 case ASHIFTRT
: fputs ("sra", file
); break;
2970 case LSHIFTRT
: fputs ("srl", file
); break;
2974 /* case 'n': negate and print a constant int. */
2977 /* Print PIC label using operand as the number. */
2978 if (GET_CODE (x
) != CONST_INT
)
2979 fatal_insn ("bad insn to frv_print_operand, P modifier:", x
);
2981 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2985 /* Print 'u' if the operand is a update load/store. */
2986 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
2991 /* If value is 0, print gr0, otherwise it must be a register. */
2992 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
2993 fputs (reg_names
[GPR_R0
], file
);
2995 else if (GET_CODE (x
) == REG
)
2996 fputs (reg_names
[REGNO (x
)], file
);
2999 fatal_insn ("bad insn in frv_print_operand, z case", x
);
3003 /* Print constant in hex. */
3004 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3006 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
3013 if (GET_CODE (x
) == REG
)
3014 fputs (reg_names
[REGNO (x
)], file
);
3016 else if (GET_CODE (x
) == CONST_INT
3017 || GET_CODE (x
) == CONST_DOUBLE
)
3018 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
3020 else if (frv_const_unspec_p (x
, &unspec
))
3021 frv_output_const_unspec (file
, &unspec
);
3023 else if (GET_CODE (x
) == MEM
)
3024 frv_print_operand_address (file
, XEXP (x
, 0));
3026 else if (CONSTANT_ADDRESS_P (x
))
3027 frv_print_operand_address (file
, x
);
3030 fatal_insn ("bad insn in frv_print_operand, 0 case", x
);
3035 fatal_insn ("frv_print_operand: unknown code", x
);
3043 frv_print_operand_punct_valid_p (unsigned char code
)
3045 return (code
== '.' || code
== '#' || code
== '@' || code
== '~'
3046 || code
== '*' || code
== '&');
3050 /* A C statement (sans semicolon) for initializing the variable CUM for the
3051 state at the beginning of the argument list. The variable has type
3052 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3053 of the function which will receive the args, or 0 if the args are to a
3054 compiler support library function. The value of INDIRECT is nonzero when
3055 processing an indirect call, for example a call through a function pointer.
3056 The value of INDIRECT is zero for a call to an explicitly named function, a
3057 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3058 arguments for the function being compiled.
3060 When processing a call to a compiler support library function, LIBNAME
3061 identifies which one. It is a `symbol_ref' rtx which contains the name of
3062 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3063 being processed. Thus, each time this macro is called, either LIBNAME or
3064 FNTYPE is nonzero, but never both of them at once. */
3067 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
3073 *cum
= FIRST_ARG_REGNUM
;
3075 if (TARGET_DEBUG_ARG
)
3077 fprintf (stderr
, "\ninit_cumulative_args:");
3078 if (!fndecl
&& fntype
)
3079 fputs (" indirect", stderr
);
3082 fputs (" incoming", stderr
);
3086 tree ret_type
= TREE_TYPE (fntype
);
3087 fprintf (stderr
, " return=%s,",
3088 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
3091 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3092 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3094 if (cfun
->returns_struct
)
3095 fprintf (stderr
, " return-struct");
3097 putc ('\n', stderr
);
3102 /* Return true if we should pass an argument on the stack rather than
3106 frv_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
3108 if (mode
== BLKmode
)
3112 return AGGREGATE_TYPE_P (type
);
3115 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3116 argument with the specified mode and type. If it is not defined,
3117 `PARM_BOUNDARY' is used for all arguments. */
3120 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED
,
3121 const_tree type ATTRIBUTE_UNUSED
)
3123 return BITS_PER_WORD
;
3127 frv_function_arg_1 (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3128 const_tree type ATTRIBUTE_UNUSED
, bool named
,
3129 bool incoming ATTRIBUTE_UNUSED
)
3131 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3136 /* Return a marker for use in the call instruction. */
3137 if (xmode
== VOIDmode
)
3143 else if (arg_num
<= LAST_ARG_REGNUM
)
3145 ret
= gen_rtx_REG (xmode
, arg_num
);
3146 debstr
= reg_names
[arg_num
];
3155 if (TARGET_DEBUG_ARG
)
3157 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3158 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3164 frv_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3165 const_tree type
, bool named
)
3167 return frv_function_arg_1 (cum
, mode
, type
, named
, false);
3171 frv_function_incoming_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3172 const_tree type
, bool named
)
3174 return frv_function_arg_1 (cum
, mode
, type
, named
, true);
3178 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3179 advance past an argument in the argument list. The values MODE, TYPE and
3180 NAMED describe that argument. Once this is done, the variable CUM is
3181 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3183 This macro need not do anything if the argument in question was passed on
3184 the stack. The compiler knows how to track the amount of stack space used
3185 for arguments without any special help. */
3188 frv_function_arg_advance (CUMULATIVE_ARGS
*cum
,
3189 enum machine_mode mode
,
3190 const_tree type ATTRIBUTE_UNUSED
,
3193 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3194 int bytes
= GET_MODE_SIZE (xmode
);
3195 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3198 *cum
= arg_num
+ words
;
3200 if (TARGET_DEBUG_ARG
)
3202 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3203 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3207 /* A C expression for the number of words, at the beginning of an argument,
3208 must be put in registers. The value must be zero for arguments that are
3209 passed entirely in registers or that are entirely pushed on the stack.
3211 On some machines, certain arguments must be passed partially in registers
3212 and partially in memory. On these machines, typically the first N words of
3213 arguments are passed in registers, and the rest on the stack. If a
3214 multi-word argument (a `double' or a structure) crosses that boundary, its
3215 first few words must be passed in registers and the rest must be pushed.
3216 This macro tells the compiler when this occurs, and how many of the words
3217 should go in registers.
3219 `FUNCTION_ARG' for these arguments should return the first register to be
3220 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3221 the called function. */
3224 frv_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3225 tree type ATTRIBUTE_UNUSED
, bool named ATTRIBUTE_UNUSED
)
3227 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3228 int bytes
= GET_MODE_SIZE (xmode
);
3229 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3233 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3234 ? LAST_ARG_REGNUM
- arg_num
+ 1
3236 ret
*= UNITS_PER_WORD
;
3238 if (TARGET_DEBUG_ARG
&& ret
)
3239 fprintf (stderr
, "frv_arg_partial_bytes: %d\n", ret
);
3245 /* Implements TARGET_FUNCTION_VALUE. */
3248 frv_function_value (const_tree valtype
,
3249 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
3250 bool outgoing ATTRIBUTE_UNUSED
)
3252 return gen_rtx_REG (TYPE_MODE (valtype
), RETURN_VALUE_REGNUM
);
3256 /* Implements TARGET_LIBCALL_VALUE. */
3259 frv_libcall_value (enum machine_mode mode
,
3260 const_rtx fun ATTRIBUTE_UNUSED
)
3262 return gen_rtx_REG (mode
, RETURN_VALUE_REGNUM
);
3266 /* Implements FUNCTION_VALUE_REGNO_P. */
3269 frv_function_value_regno_p (const unsigned int regno
)
3271 return (regno
== RETURN_VALUE_REGNUM
);
3274 /* Return true if a register is ok to use as a base or index register. */
3276 static FRV_INLINE
int
3277 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3283 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3285 if (regno
== ARG_POINTER_REGNUM
)
3288 return (regno
>= FIRST_PSEUDO_REGISTER
);
3292 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3293 RTX) is a legitimate memory address on the target machine for a memory
3294 operand of mode MODE.
3296 It usually pays to define several simpler macros to serve as subroutines for
3297 this one. Otherwise it may be too complicated to understand.
3299 This macro must exist in two variants: a strict variant and a non-strict
3300 one. The strict variant is used in the reload pass. It must be defined so
3301 that any pseudo-register that has not been allocated a hard register is
3302 considered a memory reference. In contexts where some kind of register is
3303 required, a pseudo-register with no hard register must be rejected.
3305 The non-strict variant is used in other passes. It must be defined to
3306 accept all pseudo-registers in every context where some kind of register is
3309 Compiler source files that want to use the strict variant of this macro
3310 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3311 conditional to define the strict variant in that case and the non-strict
3314 Normally, constant addresses which are the sum of a `symbol_ref' and an
3315 integer are stored inside a `const' RTX to mark them as constant.
3316 Therefore, there is no need to recognize such sums specifically as
3317 legitimate addresses. Normally you would simply recognize any `const' as
3320 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3321 constant sums that are not marked with `const'. It assumes that a
3322 naked `plus' indicates indexing. If so, then you *must* reject such
3323 naked constant sums as illegitimate addresses, so that none of them
3324 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3327 frv_legitimate_address_p_1 (enum machine_mode mode
,
3331 int allow_double_reg_p
)
3335 HOST_WIDE_INT value
;
3338 if (FRV_SYMBOL_REF_TLS_P (x
))
3341 switch (GET_CODE (x
))
3348 if (GET_CODE (x
) != REG
)
3354 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3360 if (GET_CODE (x0
) != REG
3361 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3362 || GET_CODE (x1
) != PLUS
3363 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3364 || GET_CODE (XEXP (x1
, 1)) != REG
3365 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3372 /* 12-bit immediate */
3377 ret
= IN_RANGE (INTVAL (x
), -2048, 2047);
3379 /* If we can't use load/store double operations, make sure we can
3380 address the second word. */
3381 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3382 ret
= IN_RANGE (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3391 if (GET_CODE (x0
) == SUBREG
)
3392 x0
= SUBREG_REG (x0
);
3394 if (GET_CODE (x0
) != REG
)
3397 regno0
= REGNO (x0
);
3398 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3401 switch (GET_CODE (x1
))
3407 x1
= SUBREG_REG (x1
);
3408 if (GET_CODE (x1
) != REG
)
3414 /* Do not allow reg+reg addressing for modes > 1 word if we
3415 can't depend on having move double instructions. */
3416 if (!allow_double_reg_p
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3419 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3423 /* 12-bit immediate */
3428 value
= INTVAL (x1
);
3429 ret
= IN_RANGE (value
, -2048, 2047);
3431 /* If we can't use load/store double operations, make sure we can
3432 address the second word. */
3433 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3434 ret
= IN_RANGE (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3439 if (!condexec_p
&& got12_operand (x1
, VOIDmode
))
3447 if (TARGET_DEBUG_ADDR
)
3449 fprintf (stderr
, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3450 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3451 (condexec_p
) ? ", inside conditional code" : "");
3459 frv_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
3461 return frv_legitimate_address_p_1 (mode
, x
, strict_p
, FALSE
, FALSE
);
3464 /* Given an ADDR, generate code to inline the PLT. */
3466 gen_inlined_tls_plt (rtx addr
)
3469 rtx picreg
= get_hard_reg_initial_val (Pmode
, FDPIC_REG
);
3472 dest
= gen_reg_rtx (DImode
);
3479 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3480 calll #gettlsoff(ADDR)@(gr8, gr0)
3482 emit_insn (gen_tls_lddi (dest
, addr
, picreg
));
3489 sethi.p #gottlsdeschi(ADDR), gr8
3490 setlo #gottlsdesclo(ADDR), gr8
3491 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3492 calll #gettlsoff(ADDR)@(gr8, gr0)
3494 rtx reguse
= gen_reg_rtx (Pmode
);
3495 emit_insn (gen_tlsoff_hilo (reguse
, addr
, GEN_INT (R_FRV_GOTTLSDESCHI
)));
3496 emit_insn (gen_tls_tlsdesc_ldd (dest
, picreg
, reguse
, addr
));
3499 retval
= gen_reg_rtx (Pmode
);
3500 emit_insn (gen_tls_indirect_call (retval
, addr
, dest
, picreg
));
3504 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3505 the destination address. */
3507 gen_tlsmoff (rtx addr
, rtx reg
)
3509 rtx dest
= gen_reg_rtx (Pmode
);
3513 /* sethi.p #tlsmoffhi(x), grA
3514 setlo #tlsmofflo(x), grA
3516 dest
= gen_reg_rtx (Pmode
);
3517 emit_insn (gen_tlsoff_hilo (dest
, addr
,
3518 GEN_INT (R_FRV_TLSMOFFHI
)));
3519 dest
= gen_rtx_PLUS (Pmode
, dest
, reg
);
3523 /* addi grB, #tlsmoff12(x), grC
3525 ld/st @(grB, #tlsmoff12(x)), grC
3527 dest
= gen_reg_rtx (Pmode
);
3528 emit_insn (gen_symGOTOFF2reg_i (dest
, addr
, reg
,
3529 GEN_INT (R_FRV_TLSMOFF12
)));
3534 /* Generate code for a TLS address. */
3536 frv_legitimize_tls_address (rtx addr
, enum tls_model model
)
3538 rtx dest
, tp
= gen_rtx_REG (Pmode
, 29);
3539 rtx picreg
= get_hard_reg_initial_val (Pmode
, 15);
3543 case TLS_MODEL_INITIAL_EXEC
:
3547 ldi @(gr15, #gottlsoff12(x)), gr5
3549 dest
= gen_reg_rtx (Pmode
);
3550 emit_insn (gen_tls_load_gottlsoff12 (dest
, addr
, picreg
));
3551 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3555 /* -fPIC or anything else.
3557 sethi.p #gottlsoffhi(x), gr14
3558 setlo #gottlsofflo(x), gr14
3559 ld #tlsoff(x)@(gr15, gr14), gr9
3561 rtx tmp
= gen_reg_rtx (Pmode
);
3562 dest
= gen_reg_rtx (Pmode
);
3563 emit_insn (gen_tlsoff_hilo (tmp
, addr
,
3564 GEN_INT (R_FRV_GOTTLSOFF_HI
)));
3566 emit_insn (gen_tls_tlsoff_ld (dest
, picreg
, tmp
, addr
));
3567 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3570 case TLS_MODEL_LOCAL_DYNAMIC
:
3574 if (TARGET_INLINE_PLT
)
3575 retval
= gen_inlined_tls_plt (GEN_INT (0));
3578 /* call #gettlsoff(0) */
3579 retval
= gen_reg_rtx (Pmode
);
3580 emit_insn (gen_call_gettlsoff (retval
, GEN_INT (0), picreg
));
3583 reg
= gen_reg_rtx (Pmode
);
3584 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
3585 gen_rtx_PLUS (Pmode
,
3588 dest
= gen_tlsmoff (addr
, reg
);
3591 dest = gen_reg_rtx (Pmode);
3592 emit_insn (gen_tlsoff_hilo (dest, addr,
3593 GEN_INT (R_FRV_TLSMOFFHI)));
3594 dest = gen_rtx_PLUS (Pmode, dest, reg);
3598 case TLS_MODEL_LOCAL_EXEC
:
3599 dest
= gen_tlsmoff (addr
, gen_rtx_REG (Pmode
, 29));
3601 case TLS_MODEL_GLOBAL_DYNAMIC
:
3605 if (TARGET_INLINE_PLT
)
3606 retval
= gen_inlined_tls_plt (addr
);
3609 /* call #gettlsoff(x) */
3610 retval
= gen_reg_rtx (Pmode
);
3611 emit_insn (gen_call_gettlsoff (retval
, addr
, picreg
));
3613 dest
= gen_rtx_PLUS (Pmode
, retval
, tp
);
3624 frv_legitimize_address (rtx x
,
3625 rtx oldx ATTRIBUTE_UNUSED
,
3626 enum machine_mode mode ATTRIBUTE_UNUSED
)
3628 if (GET_CODE (x
) == SYMBOL_REF
)
3630 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3632 return frv_legitimize_tls_address (x
, model
);
3638 /* Test whether a local function descriptor is canonical, i.e.,
3639 whether we can use FUNCDESC_GOTOFF to compute the address of the
3643 frv_local_funcdesc_p (rtx fnx
)
3646 enum symbol_visibility vis
;
3649 if (! SYMBOL_REF_LOCAL_P (fnx
))
3652 fn
= SYMBOL_REF_DECL (fnx
);
3657 vis
= DECL_VISIBILITY (fn
);
3659 if (vis
== VISIBILITY_PROTECTED
)
3660 /* Private function descriptors for protected functions are not
3661 canonical. Temporarily change the visibility to global. */
3662 vis
= VISIBILITY_DEFAULT
;
3663 else if (flag_shlib
)
3664 /* If we're already compiling for a shared library (that, unlike
3665 executables, can't assume that the existence of a definition
3666 implies local binding), we can skip the re-testing. */
3669 ret
= default_binds_local_p_1 (fn
, flag_pic
);
3671 DECL_VISIBILITY (fn
) = vis
;
3676 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3680 frv_gen_GPsym2reg (rtx dest
, rtx src
)
3682 tree gp
= get_identifier ("_gp");
3683 rtx gp_sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (gp
));
3685 return gen_symGOT2reg (dest
, gp_sym
, src
, GEN_INT (R_FRV_GOT12
));
3689 unspec_got_name (int i
)
3693 case R_FRV_GOT12
: return "got12";
3694 case R_FRV_GOTHI
: return "gothi";
3695 case R_FRV_GOTLO
: return "gotlo";
3696 case R_FRV_FUNCDESC
: return "funcdesc";
3697 case R_FRV_FUNCDESC_GOT12
: return "gotfuncdesc12";
3698 case R_FRV_FUNCDESC_GOTHI
: return "gotfuncdeschi";
3699 case R_FRV_FUNCDESC_GOTLO
: return "gotfuncdesclo";
3700 case R_FRV_FUNCDESC_VALUE
: return "funcdescvalue";
3701 case R_FRV_FUNCDESC_GOTOFF12
: return "gotofffuncdesc12";
3702 case R_FRV_FUNCDESC_GOTOFFHI
: return "gotofffuncdeschi";
3703 case R_FRV_FUNCDESC_GOTOFFLO
: return "gotofffuncdesclo";
3704 case R_FRV_GOTOFF12
: return "gotoff12";
3705 case R_FRV_GOTOFFHI
: return "gotoffhi";
3706 case R_FRV_GOTOFFLO
: return "gotofflo";
3707 case R_FRV_GPREL12
: return "gprel12";
3708 case R_FRV_GPRELHI
: return "gprelhi";
3709 case R_FRV_GPRELLO
: return "gprello";
3710 case R_FRV_GOTTLSOFF_HI
: return "gottlsoffhi";
3711 case R_FRV_GOTTLSOFF_LO
: return "gottlsofflo";
3712 case R_FRV_TLSMOFFHI
: return "tlsmoffhi";
3713 case R_FRV_TLSMOFFLO
: return "tlsmofflo";
3714 case R_FRV_TLSMOFF12
: return "tlsmoff12";
3715 case R_FRV_TLSDESCHI
: return "tlsdeschi";
3716 case R_FRV_TLSDESCLO
: return "tlsdesclo";
3717 case R_FRV_GOTTLSDESCHI
: return "gottlsdeschi";
3718 case R_FRV_GOTTLSDESCLO
: return "gottlsdesclo";
3719 default: gcc_unreachable ();
3723 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3724 is added inside the relocation operator. */
3727 frv_output_const_unspec (FILE *stream
, const struct frv_unspec
*unspec
)
3729 fprintf (stream
, "#%s(", unspec_got_name (unspec
->reloc
));
3730 output_addr_const (stream
, plus_constant (unspec
->symbol
, unspec
->offset
));
3731 fputs (")", stream
);
3734 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3735 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3736 otherwise return ORIG_X. */
3739 frv_find_base_term (rtx x
)
3741 struct frv_unspec unspec
;
3743 if (frv_const_unspec_p (x
, &unspec
)
3744 && frv_small_data_reloc_p (unspec
.symbol
, unspec
.reloc
))
3745 return plus_constant (unspec
.symbol
, unspec
.offset
);
3750 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3751 the operand is used by a predicated instruction. */
3754 frv_legitimate_memory_operand (rtx op
, enum machine_mode mode
, int condexec_p
)
3756 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3757 && GET_CODE (op
) == MEM
3758 && frv_legitimate_address_p_1 (mode
, XEXP (op
, 0),
3759 reload_completed
, condexec_p
, FALSE
));
3763 frv_expand_fdpic_call (rtx
*operands
, bool ret_value
, bool sibcall
)
3765 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
3766 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REG
);
3772 rvrtx
= operands
[0];
3776 addr
= XEXP (operands
[0], 0);
3778 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3779 any calls that would involve a PLT, but can't tell, since we
3780 don't know whether an extern function is going to be provided by
3781 a separate translation unit or imported from a separate module.
3782 When compiling for shared libraries, if the function has default
3783 visibility, we assume it's overridable, so we inline the PLT, but
3784 for executables, we don't really have a way to make a good
3785 decision: a function is as likely to be imported from a shared
3786 library as it is to be defined in the executable itself. We
3787 assume executables will get global functions defined locally,
3788 whereas shared libraries will have them potentially overridden,
3789 so we only inline PLTs when compiling for shared libraries.
3791 In order to mark a function as local to a shared library, any
3792 non-default visibility attribute suffices. Unfortunately,
3793 there's no simple way to tag a function declaration as ``in a
3794 different module'', which we could then use to trigger PLT
3795 inlining on executables. There's -minline-plt, but it affects
3796 all external functions, so one would have to also mark function
3797 declarations available in the same module with non-default
3798 visibility, which is advantageous in itself. */
3799 if (GET_CODE (addr
) == SYMBOL_REF
3800 && ((!SYMBOL_REF_LOCAL_P (addr
) && TARGET_INLINE_PLT
)
3804 dest
= gen_reg_rtx (SImode
);
3806 x
= gen_symGOTOFF2reg_hilo (dest
, addr
, OUR_FDPIC_REG
,
3807 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3809 x
= gen_symGOTOFF2reg (dest
, addr
, OUR_FDPIC_REG
,
3810 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3812 crtl
->uses_pic_offset_table
= TRUE
;
3815 else if (GET_CODE (addr
) == SYMBOL_REF
)
3817 /* These are always either local, or handled through a local
3820 c
= gen_call_value_fdpicsi (rvrtx
, addr
, operands
[1],
3821 operands
[2], picreg
, lr
);
3823 c
= gen_call_fdpicsi (addr
, operands
[1], operands
[2], picreg
, lr
);
3827 else if (! ldd_address_operand (addr
, Pmode
))
3828 addr
= force_reg (Pmode
, addr
);
3830 picreg
= gen_reg_rtx (DImode
);
3831 emit_insn (gen_movdi_ldd (picreg
, addr
));
3833 if (sibcall
&& ret_value
)
3834 c
= gen_sibcall_value_fdpicdi (rvrtx
, picreg
, const0_rtx
);
3836 c
= gen_sibcall_fdpicdi (picreg
, const0_rtx
);
3838 c
= gen_call_value_fdpicdi (rvrtx
, picreg
, const0_rtx
, lr
);
3840 c
= gen_call_fdpicdi (picreg
, const0_rtx
, lr
);
3844 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3845 process these separately from any offsets, such that we add any
3846 offsets to the function descriptor (the actual pointer), not to the
3847 function address. */
3850 frv_function_symbol_referenced_p (rtx x
)
3856 if (GET_CODE (x
) == SYMBOL_REF
)
3857 return SYMBOL_REF_FUNCTION_P (x
);
3859 length
= GET_RTX_LENGTH (GET_CODE (x
));
3860 format
= GET_RTX_FORMAT (GET_CODE (x
));
3862 for (j
= 0; j
< length
; ++j
)
3867 if (frv_function_symbol_referenced_p (XEXP (x
, j
)))
3873 if (XVEC (x
, j
) != 0)
3876 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
3877 if (frv_function_symbol_referenced_p (XVECEXP (x
, j
, k
)))
3883 /* Nothing to do. */
3891 /* Return true if the memory operand is one that can be conditionally
3895 condexec_memory_operand (rtx op
, enum machine_mode mode
)
3897 enum machine_mode op_mode
= GET_MODE (op
);
3900 if (mode
!= VOIDmode
&& op_mode
!= mode
)
3915 if (GET_CODE (op
) != MEM
)
3918 addr
= XEXP (op
, 0);
3919 return frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
);
3922 /* Return true if the bare return instruction can be used outside of the
3923 epilog code. For frv, we only do it if there was no stack allocation. */
3926 direct_return_p (void)
3930 if (!reload_completed
)
3933 info
= frv_stack_info ();
3934 return (info
->total_size
== 0);
3939 frv_emit_move (enum machine_mode mode
, rtx dest
, rtx src
)
3941 if (GET_CODE (src
) == SYMBOL_REF
)
3943 enum tls_model model
= SYMBOL_REF_TLS_MODEL (src
);
3945 src
= frv_legitimize_tls_address (src
, model
);
3951 if (frv_emit_movsi (dest
, src
))
3960 if (!reload_in_progress
3961 && !reload_completed
3962 && !register_operand (dest
, mode
)
3963 && !reg_or_0_operand (src
, mode
))
3964 src
= copy_to_mode_reg (mode
, src
);
3971 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3974 /* Emit code to handle a MOVSI, adding in the small data register or pic
3975 register if needed to load up addresses. Return TRUE if the appropriate
3976 instructions are emitted. */
3979 frv_emit_movsi (rtx dest
, rtx src
)
3981 int base_regno
= -1;
3984 struct frv_unspec old_unspec
;
3986 if (!reload_in_progress
3987 && !reload_completed
3988 && !register_operand (dest
, SImode
)
3989 && (!reg_or_0_operand (src
, SImode
)
3990 /* Virtual registers will almost always be replaced by an
3991 add instruction, so expose this to CSE by copying to
3992 an intermediate register. */
3993 || (GET_CODE (src
) == REG
3994 && IN_RANGE (REGNO (src
),
3995 FIRST_VIRTUAL_REGISTER
,
3996 LAST_VIRTUAL_POINTER_REGISTER
))))
3998 emit_insn (gen_rtx_SET (VOIDmode
, dest
, copy_to_mode_reg (SImode
, src
)));
4002 /* Explicitly add in the PIC or small data register if needed. */
4003 switch (GET_CODE (src
))
4012 /* Using GPREL12, we use a single GOT entry for all symbols
4013 in read-only sections, but trade sequences such as:
4015 sethi #gothi(label), gr#
4016 setlo #gotlo(label), gr#
4021 ld @(gr15,#got12(_gp)), gr#
4022 sethi #gprelhi(label), gr##
4023 setlo #gprello(label), gr##
4026 We may often be able to share gr# for multiple
4027 computations of GPREL addresses, and we may often fold
4028 the final add into the pair of registers of a load or
4029 store instruction, so it's often profitable. Even when
4030 optimizing for size, we're trading a GOT entry for an
4031 additional instruction, which trades GOT space
4032 (read-write) for code size (read-only, shareable), as
4033 long as the symbol is not used in more than two different
4036 With -fpie/-fpic, we'd be trading a single load for a
4037 sequence of 4 instructions, because the offset of the
4038 label can't be assumed to be addressable with 12 bits, so
4039 we don't do this. */
4040 if (TARGET_GPREL_RO
)
4041 unspec
= R_FRV_GPREL12
;
4043 unspec
= R_FRV_GOT12
;
4046 base_regno
= PIC_REGNO
;
4051 if (frv_const_unspec_p (src
, &old_unspec
))
4054 if (TARGET_FDPIC
&& frv_function_symbol_referenced_p (XEXP (src
, 0)))
4057 src
= force_reg (GET_MODE (XEXP (src
, 0)), XEXP (src
, 0));
4058 emit_move_insn (dest
, src
);
4063 sym
= XEXP (sym
, 0);
4064 if (GET_CODE (sym
) == PLUS
4065 && GET_CODE (XEXP (sym
, 0)) == SYMBOL_REF
4066 && GET_CODE (XEXP (sym
, 1)) == CONST_INT
)
4067 sym
= XEXP (sym
, 0);
4068 if (GET_CODE (sym
) == SYMBOL_REF
)
4070 else if (GET_CODE (sym
) == LABEL_REF
)
4073 goto handle_whatever
;
4081 enum tls_model model
= SYMBOL_REF_TLS_MODEL (sym
);
4085 src
= frv_legitimize_tls_address (src
, model
);
4086 emit_move_insn (dest
, src
);
4090 if (SYMBOL_REF_FUNCTION_P (sym
))
4092 if (frv_local_funcdesc_p (sym
))
4093 unspec
= R_FRV_FUNCDESC_GOTOFF12
;
4095 unspec
= R_FRV_FUNCDESC_GOT12
;
4099 if (CONSTANT_POOL_ADDRESS_P (sym
))
4100 switch (GET_CODE (get_pool_constant (sym
)))
4107 unspec
= R_FRV_GOTOFF12
;
4112 if (TARGET_GPREL_RO
)
4113 unspec
= R_FRV_GPREL12
;
4115 unspec
= R_FRV_GOT12
;
4118 else if (SYMBOL_REF_LOCAL_P (sym
)
4119 && !SYMBOL_REF_EXTERNAL_P (sym
)
4120 && SYMBOL_REF_DECL (sym
)
4121 && (!DECL_P (SYMBOL_REF_DECL (sym
))
4122 || !DECL_COMMON (SYMBOL_REF_DECL (sym
))))
4124 tree decl
= SYMBOL_REF_DECL (sym
);
4125 tree init
= TREE_CODE (decl
) == VAR_DECL
4126 ? DECL_INITIAL (decl
)
4127 : TREE_CODE (decl
) == CONSTRUCTOR
4130 bool named_section
, readonly
;
4132 if (init
&& init
!= error_mark_node
)
4133 reloc
= compute_reloc_for_constant (init
);
4135 named_section
= TREE_CODE (decl
) == VAR_DECL
4136 && lookup_attribute ("section", DECL_ATTRIBUTES (decl
));
4137 readonly
= decl_readonly_section (decl
, reloc
);
4140 unspec
= R_FRV_GOT12
;
4142 unspec
= R_FRV_GOTOFF12
;
4143 else if (readonly
&& TARGET_GPREL_RO
)
4144 unspec
= R_FRV_GPREL12
;
4146 unspec
= R_FRV_GOT12
;
4149 unspec
= R_FRV_GOT12
;
4153 else if (SYMBOL_REF_SMALL_P (sym
))
4154 base_regno
= SDA_BASE_REG
;
4157 base_regno
= PIC_REGNO
;
4162 if (base_regno
>= 0)
4164 if (GET_CODE (sym
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (sym
))
4165 emit_insn (gen_symGOTOFF2reg (dest
, src
,
4166 gen_rtx_REG (Pmode
, base_regno
),
4167 GEN_INT (R_FRV_GPREL12
)));
4169 emit_insn (gen_symGOTOFF2reg_hilo (dest
, src
,
4170 gen_rtx_REG (Pmode
, base_regno
),
4171 GEN_INT (R_FRV_GPREL12
)));
4172 if (base_regno
== PIC_REGNO
)
4173 crtl
->uses_pic_offset_table
= TRUE
;
4181 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4182 new uses of it once reload has begun. */
4183 gcc_assert (!reload_in_progress
&& !reload_completed
);
4187 case R_FRV_GOTOFF12
:
4188 if (!frv_small_data_reloc_p (sym
, unspec
))
4189 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4192 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4195 if (!frv_small_data_reloc_p (sym
, unspec
))
4196 x
= gen_symGPREL2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4199 x
= gen_symGPREL2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4201 case R_FRV_FUNCDESC_GOTOFF12
:
4203 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4206 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4210 x
= gen_symGOT2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4213 x
= gen_symGOT2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4217 crtl
->uses_pic_offset_table
= TRUE
;
4226 /* Return a string to output a single word move. */
4229 output_move_single (rtx operands
[], rtx insn
)
4231 rtx dest
= operands
[0];
4232 rtx src
= operands
[1];
4234 if (GET_CODE (dest
) == REG
)
4236 int dest_regno
= REGNO (dest
);
4237 enum machine_mode mode
= GET_MODE (dest
);
4239 if (GPR_P (dest_regno
))
4241 if (GET_CODE (src
) == REG
)
4243 /* gpr <- some sort of register */
4244 int src_regno
= REGNO (src
);
4246 if (GPR_P (src_regno
))
4247 return "mov %1, %0";
4249 else if (FPR_P (src_regno
))
4250 return "movfg %1, %0";
4252 else if (SPR_P (src_regno
))
4253 return "movsg %1, %0";
4256 else if (GET_CODE (src
) == MEM
)
4265 return "ldsb%I1%U1 %M1,%0";
4268 return "ldsh%I1%U1 %M1,%0";
4272 return "ld%I1%U1 %M1, %0";
4276 else if (GET_CODE (src
) == CONST_INT
4277 || GET_CODE (src
) == CONST_DOUBLE
)
4279 /* gpr <- integer/floating constant */
4280 HOST_WIDE_INT value
;
4282 if (GET_CODE (src
) == CONST_INT
)
4283 value
= INTVAL (src
);
4285 else if (mode
== SFmode
)
4290 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
4291 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4296 value
= CONST_DOUBLE_LOW (src
);
4298 if (IN_RANGE (value
, -32768, 32767))
4299 return "setlos %1, %0";
4304 else if (GET_CODE (src
) == SYMBOL_REF
4305 || GET_CODE (src
) == LABEL_REF
4306 || GET_CODE (src
) == CONST
)
4312 else if (FPR_P (dest_regno
))
4314 if (GET_CODE (src
) == REG
)
4316 /* fpr <- some sort of register */
4317 int src_regno
= REGNO (src
);
4319 if (GPR_P (src_regno
))
4320 return "movgf %1, %0";
4322 else if (FPR_P (src_regno
))
4324 if (TARGET_HARD_FLOAT
)
4325 return "fmovs %1, %0";
4327 return "mor %1, %1, %0";
4331 else if (GET_CODE (src
) == MEM
)
4340 return "ldbf%I1%U1 %M1,%0";
4343 return "ldhf%I1%U1 %M1,%0";
4347 return "ldf%I1%U1 %M1, %0";
4351 else if (ZERO_P (src
))
4352 return "movgf %., %0";
4355 else if (SPR_P (dest_regno
))
4357 if (GET_CODE (src
) == REG
)
4359 /* spr <- some sort of register */
4360 int src_regno
= REGNO (src
);
4362 if (GPR_P (src_regno
))
4363 return "movgs %1, %0";
4365 else if (ZERO_P (src
))
4366 return "movgs %., %0";
4370 else if (GET_CODE (dest
) == MEM
)
4372 if (GET_CODE (src
) == REG
)
4374 int src_regno
= REGNO (src
);
4375 enum machine_mode mode
= GET_MODE (dest
);
4377 if (GPR_P (src_regno
))
4385 return "stb%I0%U0 %1, %M0";
4388 return "sth%I0%U0 %1, %M0";
4392 return "st%I0%U0 %1, %M0";
4396 else if (FPR_P (src_regno
))
4404 return "stbf%I0%U0 %1, %M0";
4407 return "sthf%I0%U0 %1, %M0";
4411 return "stf%I0%U0 %1, %M0";
4416 else if (ZERO_P (src
))
4418 switch (GET_MODE (dest
))
4424 return "stb%I0%U0 %., %M0";
4427 return "sth%I0%U0 %., %M0";
4431 return "st%I0%U0 %., %M0";
4436 fatal_insn ("bad output_move_single operand", insn
);
4441 /* Return a string to output a double word move. */
4444 output_move_double (rtx operands
[], rtx insn
)
4446 rtx dest
= operands
[0];
4447 rtx src
= operands
[1];
4448 enum machine_mode mode
= GET_MODE (dest
);
4450 if (GET_CODE (dest
) == REG
)
4452 int dest_regno
= REGNO (dest
);
4454 if (GPR_P (dest_regno
))
4456 if (GET_CODE (src
) == REG
)
4458 /* gpr <- some sort of register */
4459 int src_regno
= REGNO (src
);
4461 if (GPR_P (src_regno
))
4464 else if (FPR_P (src_regno
))
4466 if (((dest_regno
- GPR_FIRST
) & 1) == 0
4467 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4468 return "movfgd %1, %0";
4474 else if (GET_CODE (src
) == MEM
)
4477 if (dbl_memory_one_insn_operand (src
, mode
))
4478 return "ldd%I1%U1 %M1, %0";
4483 else if (GET_CODE (src
) == CONST_INT
4484 || GET_CODE (src
) == CONST_DOUBLE
)
4488 else if (FPR_P (dest_regno
))
4490 if (GET_CODE (src
) == REG
)
4492 /* fpr <- some sort of register */
4493 int src_regno
= REGNO (src
);
4495 if (GPR_P (src_regno
))
4497 if (((dest_regno
- FPR_FIRST
) & 1) == 0
4498 && ((src_regno
- GPR_FIRST
) & 1) == 0)
4499 return "movgfd %1, %0";
4504 else if (FPR_P (src_regno
))
4507 && ((dest_regno
- FPR_FIRST
) & 1) == 0
4508 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4509 return "fmovd %1, %0";
4515 else if (GET_CODE (src
) == MEM
)
4518 if (dbl_memory_one_insn_operand (src
, mode
))
4519 return "lddf%I1%U1 %M1, %0";
4524 else if (ZERO_P (src
))
4529 else if (GET_CODE (dest
) == MEM
)
4531 if (GET_CODE (src
) == REG
)
4533 int src_regno
= REGNO (src
);
4535 if (GPR_P (src_regno
))
4537 if (((src_regno
- GPR_FIRST
) & 1) == 0
4538 && dbl_memory_one_insn_operand (dest
, mode
))
4539 return "std%I0%U0 %1, %M0";
4544 if (FPR_P (src_regno
))
4546 if (((src_regno
- FPR_FIRST
) & 1) == 0
4547 && dbl_memory_one_insn_operand (dest
, mode
))
4548 return "stdf%I0%U0 %1, %M0";
4554 else if (ZERO_P (src
))
4556 if (dbl_memory_one_insn_operand (dest
, mode
))
4557 return "std%I0%U0 %., %M0";
4563 fatal_insn ("bad output_move_double operand", insn
);
4568 /* Return a string to output a single word conditional move.
4569 Operand0 -- EQ/NE of ccr register and 0
4570 Operand1 -- CCR register
4571 Operand2 -- destination
4572 Operand3 -- source */
4575 output_condmove_single (rtx operands
[], rtx insn
)
4577 rtx dest
= operands
[2];
4578 rtx src
= operands
[3];
4580 if (GET_CODE (dest
) == REG
)
4582 int dest_regno
= REGNO (dest
);
4583 enum machine_mode mode
= GET_MODE (dest
);
4585 if (GPR_P (dest_regno
))
4587 if (GET_CODE (src
) == REG
)
4589 /* gpr <- some sort of register */
4590 int src_regno
= REGNO (src
);
4592 if (GPR_P (src_regno
))
4593 return "cmov %z3, %2, %1, %e0";
4595 else if (FPR_P (src_regno
))
4596 return "cmovfg %3, %2, %1, %e0";
4599 else if (GET_CODE (src
) == MEM
)
4608 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4611 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4615 return "cld%I3%U3 %M3, %2, %1, %e0";
4619 else if (ZERO_P (src
))
4620 return "cmov %., %2, %1, %e0";
4623 else if (FPR_P (dest_regno
))
4625 if (GET_CODE (src
) == REG
)
4627 /* fpr <- some sort of register */
4628 int src_regno
= REGNO (src
);
4630 if (GPR_P (src_regno
))
4631 return "cmovgf %3, %2, %1, %e0";
4633 else if (FPR_P (src_regno
))
4635 if (TARGET_HARD_FLOAT
)
4636 return "cfmovs %3,%2,%1,%e0";
4638 return "cmor %3, %3, %2, %1, %e0";
4642 else if (GET_CODE (src
) == MEM
)
4645 if (mode
== SImode
|| mode
== SFmode
)
4646 return "cldf%I3%U3 %M3, %2, %1, %e0";
4649 else if (ZERO_P (src
))
4650 return "cmovgf %., %2, %1, %e0";
4654 else if (GET_CODE (dest
) == MEM
)
4656 if (GET_CODE (src
) == REG
)
4658 int src_regno
= REGNO (src
);
4659 enum machine_mode mode
= GET_MODE (dest
);
4661 if (GPR_P (src_regno
))
4669 return "cstb%I2%U2 %3, %M2, %1, %e0";
4672 return "csth%I2%U2 %3, %M2, %1, %e0";
4676 return "cst%I2%U2 %3, %M2, %1, %e0";
4680 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
4681 return "cstf%I2%U2 %3, %M2, %1, %e0";
4684 else if (ZERO_P (src
))
4686 enum machine_mode mode
= GET_MODE (dest
);
4693 return "cstb%I2%U2 %., %M2, %1, %e0";
4696 return "csth%I2%U2 %., %M2, %1, %e0";
4700 return "cst%I2%U2 %., %M2, %1, %e0";
4705 fatal_insn ("bad output_condmove_single operand", insn
);
4710 /* Emit the appropriate code to do a comparison, returning the register the
4711 comparison was done it. */
4714 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
4716 enum machine_mode cc_mode
;
4719 /* Floating point doesn't have comparison against a constant. */
4720 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
4721 op1
= force_reg (GET_MODE (op0
), op1
);
4723 /* Possibly disable using anything but a fixed register in order to work
4724 around cse moving comparisons past function calls. */
4725 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
4726 cc_reg
= ((TARGET_ALLOC_CC
)
4727 ? gen_reg_rtx (cc_mode
)
4728 : gen_rtx_REG (cc_mode
,
4729 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
4731 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
4732 gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
4738 /* Emit code for a conditional branch.
4739 XXX: I originally wanted to add a clobber of a CCR register to use in
4740 conditional execution, but that confuses the rest of the compiler. */
4743 frv_emit_cond_branch (rtx operands
[])
4748 enum rtx_code test
= GET_CODE (operands
[0]);
4749 rtx cc_reg
= frv_emit_comparison (test
, operands
[1], operands
[2]);
4750 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
4752 /* Branches generate:
4754 (if_then_else (<test>, <cc_reg>, (const_int 0))
4755 (label_ref <branch_label>)
4757 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
4758 test_rtx
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4759 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
4760 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_else
));
4765 /* Emit code to set a gpr to 1/0 based on a comparison. */
4768 frv_emit_scc (rtx operands
[])
4774 enum rtx_code test
= GET_CODE (operands
[1]);
4775 rtx cc_reg
= frv_emit_comparison (test
, operands
[2], operands
[3]);
4777 /* SCC instructions generate:
4778 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4779 (clobber (<ccr_reg>))]) */
4780 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
4781 set
= gen_rtx_SET (VOIDmode
, operands
[0], test_rtx
);
4783 cr_reg
= ((TARGET_ALLOC_CC
)
4784 ? gen_reg_rtx (CC_CCRmode
)
4785 : gen_rtx_REG (CC_CCRmode
,
4786 ((GET_MODE (cc_reg
) == CC_FPmode
)
4790 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4791 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
4796 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4797 the separate insns. */
4800 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
4806 /* Set the appropriate CCR bit. */
4807 emit_insn (gen_rtx_SET (VOIDmode
,
4809 gen_rtx_fmt_ee (GET_CODE (test
),
4814 /* Move the value into the destination. */
4815 emit_move_insn (dest
, GEN_INT (value
));
4817 /* Move 0 into the destination if the test failed */
4818 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4819 gen_rtx_EQ (GET_MODE (cr_reg
),
4822 gen_rtx_SET (VOIDmode
, dest
, const0_rtx
)));
4824 /* Finish up, return sequence. */
4831 /* Emit the code for a conditional move, return TRUE if we could do the
4835 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
4842 enum rtx_code test
= GET_CODE (test_rtx
);
4843 rtx cc_reg
= frv_emit_comparison (test
,
4844 XEXP (test_rtx
, 0), XEXP (test_rtx
, 1));
4845 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
4847 /* Conditional move instructions generate:
4848 (parallel [(set <target>
4849 (if_then_else (<test> <cc_reg> (const_int 0))
4852 (clobber (<ccr_reg>))]) */
4854 /* Handle various cases of conditional move involving two constants. */
4855 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4857 HOST_WIDE_INT value1
= INTVAL (src1
);
4858 HOST_WIDE_INT value2
= INTVAL (src2
);
4860 /* Having 0 as one of the constants can be done by loading the other
4861 constant, and optionally moving in gr0. */
4862 if (value1
== 0 || value2
== 0)
4865 /* If the first value is within an addi range and also the difference
4866 between the two fits in an addi's range, load up the difference, then
4867 conditionally move in 0, and then unconditionally add the first
4869 else if (IN_RANGE (value1
, -2048, 2047)
4870 && IN_RANGE (value2
- value1
, -2048, 2047))
4873 /* If neither condition holds, just force the constant into a
4877 src1
= force_reg (GET_MODE (dest
), src1
);
4878 src2
= force_reg (GET_MODE (dest
), src2
);
4882 /* If one value is a register, insure the other value is either 0 or a
4886 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
4887 src1
= force_reg (GET_MODE (dest
), src1
);
4889 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
4890 src2
= force_reg (GET_MODE (dest
), src2
);
4893 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4894 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
4896 set
= gen_rtx_SET (VOIDmode
, dest
, if_rtx
);
4898 cr_reg
= ((TARGET_ALLOC_CC
)
4899 ? gen_reg_rtx (CC_CCRmode
)
4900 : gen_rtx_REG (CC_CCRmode
,
4901 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
4903 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4904 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
4909 /* Split a conditional move into constituent parts, returning a SEQUENCE
4910 containing all of the insns. */
4913 frv_split_cond_move (rtx operands
[])
4915 rtx dest
= operands
[0];
4916 rtx test
= operands
[1];
4917 rtx cc_reg
= operands
[2];
4918 rtx src1
= operands
[3];
4919 rtx src2
= operands
[4];
4920 rtx cr_reg
= operands
[5];
4922 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
4926 /* Set the appropriate CCR bit. */
4927 emit_insn (gen_rtx_SET (VOIDmode
,
4929 gen_rtx_fmt_ee (GET_CODE (test
),
4934 /* Handle various cases of conditional move involving two constants. */
4935 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4937 HOST_WIDE_INT value1
= INTVAL (src1
);
4938 HOST_WIDE_INT value2
= INTVAL (src2
);
4940 /* Having 0 as one of the constants can be done by loading the other
4941 constant, and optionally moving in gr0. */
4944 emit_move_insn (dest
, src2
);
4945 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4946 gen_rtx_NE (cr_mode
, cr_reg
,
4948 gen_rtx_SET (VOIDmode
, dest
, src1
)));
4951 else if (value2
== 0)
4953 emit_move_insn (dest
, src1
);
4954 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4955 gen_rtx_EQ (cr_mode
, cr_reg
,
4957 gen_rtx_SET (VOIDmode
, dest
, src2
)));
4960 /* If the first value is within an addi range and also the difference
4961 between the two fits in an addi's range, load up the difference, then
4962 conditionally move in 0, and then unconditionally add the first
4964 else if (IN_RANGE (value1
, -2048, 2047)
4965 && IN_RANGE (value2
- value1
, -2048, 2047))
4967 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
4969 : gen_rtx_SUBREG (SImode
, dest
, 0));
4971 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
4972 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4973 gen_rtx_NE (cr_mode
, cr_reg
,
4975 gen_rtx_SET (VOIDmode
, dest_si
,
4977 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
4985 /* Emit the conditional move for the test being true if needed. */
4986 if (! rtx_equal_p (dest
, src1
))
4987 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4988 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
4989 gen_rtx_SET (VOIDmode
, dest
, src1
)));
4991 /* Emit the conditional move for the test being false if needed. */
4992 if (! rtx_equal_p (dest
, src2
))
4993 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4994 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
4995 gen_rtx_SET (VOIDmode
, dest
, src2
)));
4998 /* Finish up, return sequence. */
5005 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5006 memory location that is not known to be dword-aligned. */
5008 frv_split_double_load (rtx dest
, rtx source
)
5010 int regno
= REGNO (dest
);
5011 rtx dest1
= gen_highpart (SImode
, dest
);
5012 rtx dest2
= gen_lowpart (SImode
, dest
);
5013 rtx address
= XEXP (source
, 0);
5015 /* If the address is pre-modified, load the lower-numbered register
5016 first, then load the other register using an integer offset from
5017 the modified base register. This order should always be safe,
5018 since the pre-modification cannot affect the same registers as the
5021 The situation for other loads is more complicated. Loading one
5022 of the registers could affect the value of ADDRESS, so we must
5023 be careful which order we do them in. */
5024 if (GET_CODE (address
) == PRE_MODIFY
5025 || ! refers_to_regno_p (regno
, regno
+ 1, address
, NULL
))
5027 /* It is safe to load the lower-numbered register first. */
5028 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5029 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5033 /* ADDRESS is not pre-modified and the address depends on the
5034 lower-numbered register. Load the higher-numbered register
5036 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5037 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5041 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5042 and SOURCE is either a double register or the constant zero. */
5044 frv_split_double_store (rtx dest
, rtx source
)
5046 rtx dest1
= change_address (dest
, SImode
, NULL
);
5047 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
5048 if (ZERO_P (source
))
5050 emit_move_insn (dest1
, CONST0_RTX (SImode
));
5051 emit_move_insn (dest2
, CONST0_RTX (SImode
));
5055 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
5056 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
5061 /* Split a min/max operation returning a SEQUENCE containing all of the
5065 frv_split_minmax (rtx operands
[])
5067 rtx dest
= operands
[0];
5068 rtx minmax
= operands
[1];
5069 rtx src1
= operands
[2];
5070 rtx src2
= operands
[3];
5071 rtx cc_reg
= operands
[4];
5072 rtx cr_reg
= operands
[5];
5074 enum rtx_code test_code
;
5075 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
5079 /* Figure out which test to use. */
5080 switch (GET_CODE (minmax
))
5085 case SMIN
: test_code
= LT
; break;
5086 case SMAX
: test_code
= GT
; break;
5087 case UMIN
: test_code
= LTU
; break;
5088 case UMAX
: test_code
= GTU
; break;
5091 /* Issue the compare instruction. */
5092 emit_insn (gen_rtx_SET (VOIDmode
,
5094 gen_rtx_COMPARE (GET_MODE (cc_reg
),
5097 /* Set the appropriate CCR bit. */
5098 emit_insn (gen_rtx_SET (VOIDmode
,
5100 gen_rtx_fmt_ee (test_code
,
5105 /* If are taking the min/max of a nonzero constant, load that first, and
5106 then do a conditional move of the other value. */
5107 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
5109 gcc_assert (!rtx_equal_p (dest
, src1
));
5111 emit_move_insn (dest
, src2
);
5112 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5113 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5114 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5117 /* Otherwise, do each half of the move. */
5120 /* Emit the conditional move for the test being true if needed. */
5121 if (! rtx_equal_p (dest
, src1
))
5122 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5123 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5124 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5126 /* Emit the conditional move for the test being false if needed. */
5127 if (! rtx_equal_p (dest
, src2
))
5128 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5129 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5130 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5133 /* Finish up, return sequence. */
5140 /* Split an integer abs operation returning a SEQUENCE containing all of the
5144 frv_split_abs (rtx operands
[])
5146 rtx dest
= operands
[0];
5147 rtx src
= operands
[1];
5148 rtx cc_reg
= operands
[2];
5149 rtx cr_reg
= operands
[3];
5154 /* Issue the compare < 0 instruction. */
5155 emit_insn (gen_rtx_SET (VOIDmode
,
5157 gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
5159 /* Set the appropriate CCR bit. */
5160 emit_insn (gen_rtx_SET (VOIDmode
,
5162 gen_rtx_fmt_ee (LT
, CC_CCRmode
, cc_reg
, const0_rtx
)));
5164 /* Emit the conditional negate if the value is negative. */
5165 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5166 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
5167 gen_negsi2 (dest
, src
)));
5169 /* Emit the conditional move for the test being false if needed. */
5170 if (! rtx_equal_p (dest
, src
))
5171 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5172 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
5173 gen_rtx_SET (VOIDmode
, dest
, src
)));
5175 /* Finish up, return sequence. */
5182 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5183 register used in an insn. */
5186 frv_clear_registers_used (rtx
*ptr
, void *data
)
5188 if (GET_CODE (*ptr
) == REG
)
5190 int regno
= REGNO (*ptr
);
5191 HARD_REG_SET
*p_regs
= (HARD_REG_SET
*)data
;
5193 if (regno
< FIRST_PSEUDO_REGISTER
)
5195 int reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (*ptr
));
5197 while (regno
< reg_max
)
5199 CLEAR_HARD_REG_BIT (*p_regs
, regno
);
5209 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5211 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5212 initialize the static storage. */
5214 frv_ifcvt_init_extra_fields (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
5216 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5217 frv_ifcvt
.cur_scratch_regs
= 0;
5218 frv_ifcvt
.num_nested_cond_exec
= 0;
5219 frv_ifcvt
.cr_reg
= NULL_RTX
;
5220 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
5221 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
5222 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
5223 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5227 /* Internal function to add a potential insn to the list of insns to be inserted
5228 if the conditional execution conversion is successful. */
5231 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
5233 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
5235 link
->jump
= before_p
; /* Mark to add this before or after insn. */
5236 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
5237 frv_ifcvt
.added_insns_list
);
5239 if (TARGET_DEBUG_COND_EXEC
)
5242 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5243 (before_p
) ? "before" : "after",
5244 (int)INSN_UID (insn
));
5246 debug_rtx (pattern
);
5251 /* A C expression to modify the code described by the conditional if
5252 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5253 FALSE_EXPR for converting if-then and if-then-else code to conditional
5254 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5255 tests cannot be converted. */
5258 frv_ifcvt_modify_tests (ce_if_block_t
*ce_info
, rtx
*p_true
, rtx
*p_false
)
5260 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
5261 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
5262 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
5263 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
5264 rtx true_expr
= *p_true
;
5268 enum machine_mode mode
= GET_MODE (true_expr
);
5272 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
5274 rtx sub_cond_exec_reg
;
5276 enum rtx_code code_true
;
5277 enum rtx_code code_false
;
5278 enum reg_class cc_class
;
5279 enum reg_class cr_class
;
5282 reg_set_iterator rsi
;
5284 /* Make sure we are only dealing with hard registers. Also honor the
5285 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5287 if (!reload_completed
|| !TARGET_COND_EXEC
5288 || (!TARGET_NESTED_CE
&& ce_info
->pass
> 1))
5291 /* Figure out which registers we can allocate for our own purposes. Only
5292 consider registers that are not preserved across function calls and are
5293 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5294 if we did not need to use them in reloading other registers. */
5295 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
5296 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
5297 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
5298 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
5299 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
5301 /* If this is a nested IF, we need to discover whether the CC registers that
5302 are set/used inside of the block are used anywhere else. If not, we can
5303 change them to be the CC register that is paired with the CR register that
5304 controls the outermost IF block. */
5305 if (ce_info
->pass
> 1)
5307 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
5308 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5309 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5311 if (REGNO_REG_SET_P (df_get_live_in (then_bb
), j
))
5315 && REGNO_REG_SET_P (df_get_live_in (else_bb
), j
))
5319 && REGNO_REG_SET_P (df_get_live_in (join_bb
), j
))
5322 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
5326 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
5327 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
5329 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5330 frv_ifcvt
.cur_scratch_regs
= 0;
5332 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
5333 * sizeof (basic_block
));
5339 /* Remove anything live at the beginning of the join block from being
5340 available for allocation. */
5341 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb
), 0, regno
, rsi
)
5343 if (regno
< FIRST_PSEUDO_REGISTER
)
5344 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5348 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5350 if (ce_info
->num_multiple_test_blocks
)
5352 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
5354 while (multiple_test_bb
!= test_bb
)
5356 bb
[num_bb
++] = multiple_test_bb
;
5357 multiple_test_bb
= EDGE_PRED (multiple_test_bb
, 0)->src
;
5361 /* Add in the THEN and ELSE blocks to be scanned. */
5362 bb
[num_bb
++] = then_bb
;
5364 bb
[num_bb
++] = else_bb
;
5366 sub_cond_exec_reg
= NULL_RTX
;
5367 frv_ifcvt
.num_nested_cond_exec
= 0;
5369 /* Scan all of the blocks for registers that must not be allocated. */
5370 for (j
= 0; j
< num_bb
; j
++)
5372 rtx last_insn
= BB_END (bb
[j
]);
5373 rtx insn
= BB_HEAD (bb
[j
]);
5377 fprintf (dump_file
, "Scanning %s block %d, start %d, end %d\n",
5378 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
5380 (int) INSN_UID (BB_HEAD (bb
[j
])),
5381 (int) INSN_UID (BB_END (bb
[j
])));
5383 /* Anything live at the beginning of the block is obviously unavailable
5385 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb
[j
]), 0, regno
, rsi
)
5387 if (regno
< FIRST_PSEUDO_REGISTER
)
5388 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5391 /* Loop through the insns in the block. */
5394 /* Mark any new registers that are created as being unavailable for
5395 allocation. Also see if the CC register used in nested IFs can be
5401 int skip_nested_if
= FALSE
;
5403 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
5404 (void *)&tmp_reg
->regs
);
5406 pattern
= PATTERN (insn
);
5407 if (GET_CODE (pattern
) == COND_EXEC
)
5409 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
5411 if (reg
!= sub_cond_exec_reg
)
5413 sub_cond_exec_reg
= reg
;
5414 frv_ifcvt
.num_nested_cond_exec
++;
5418 set
= single_set_pattern (pattern
);
5421 rtx dest
= SET_DEST (set
);
5422 rtx src
= SET_SRC (set
);
5424 if (GET_CODE (dest
) == REG
)
5426 int regno
= REGNO (dest
);
5427 enum rtx_code src_code
= GET_CODE (src
);
5429 if (CC_P (regno
) && src_code
== COMPARE
)
5430 skip_nested_if
= TRUE
;
5432 else if (CR_P (regno
)
5433 && (src_code
== IF_THEN_ELSE
5434 || COMPARISON_P (src
)))
5435 skip_nested_if
= TRUE
;
5439 if (! skip_nested_if
)
5440 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
5441 (void *)&frv_ifcvt
.nested_cc_ok_rewrite
);
5444 if (insn
== last_insn
)
5447 insn
= NEXT_INSN (insn
);
5451 /* If this is a nested if, rewrite the CC registers that are available to
5452 include the ones that can be rewritten, to increase the chance of being
5453 able to allocate a paired CC/CR register combination. */
5454 if (ce_info
->pass
> 1)
5456 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5457 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
5458 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
5460 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
5466 fprintf (dump_file
, "Available GPRs: ");
5468 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
5469 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5471 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5472 if (++num_gprs
> GPR_TEMP_NUM
+2)
5476 fprintf (dump_file
, "%s\nAvailable CRs: ",
5477 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
5479 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
5480 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5481 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5483 fputs ("\n", dump_file
);
5485 if (ce_info
->pass
> 1)
5487 fprintf (dump_file
, "Modifiable CCs: ");
5488 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5489 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5490 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5492 fprintf (dump_file
, "\n%d nested COND_EXEC statements\n",
5493 frv_ifcvt
.num_nested_cond_exec
);
5497 /* Allocate the appropriate temporary condition code register. Try to
5498 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5499 that conditional cmp's can be done. */
5500 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5502 cr_class
= ICR_REGS
;
5503 cc_class
= ICC_REGS
;
5504 cc_first
= ICC_FIRST
;
5507 else if (mode
== CC_FPmode
)
5509 cr_class
= FCR_REGS
;
5510 cc_class
= FCC_REGS
;
5511 cc_first
= FCC_FIRST
;
5516 cc_first
= cc_last
= 0;
5517 cr_class
= cc_class
= NO_REGS
;
5520 cc
= XEXP (true_expr
, 0);
5521 nested_cc
= cr
= NULL_RTX
;
5522 if (cc_class
!= NO_REGS
)
5524 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5525 so we can execute a csubcc/caddcc/cfcmps instruction. */
5528 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
5530 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
5532 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
5533 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
5535 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
5536 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
5539 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
5540 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
5550 fprintf (dump_file
, "Could not allocate a CR temporary register\n");
5557 "Will use %s for conditional execution, %s for nested comparisons\n",
5558 reg_names
[ REGNO (cr
)],
5559 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
5561 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5562 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5563 bit being true. We don't do this for floating point, because of NaNs. */
5564 code
= GET_CODE (true_expr
);
5565 if (GET_MODE (cc
) != CC_FPmode
)
5567 code
= reverse_condition (code
);
5577 check_insn
= gen_rtx_SET (VOIDmode
, cr
,
5578 gen_rtx_fmt_ee (code
, CC_CCRmode
, cc
, const0_rtx
));
5580 /* Record the check insn to be inserted later. */
5581 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
5583 /* Update the tests. */
5584 frv_ifcvt
.cr_reg
= cr
;
5585 frv_ifcvt
.nested_cc_reg
= nested_cc
;
5586 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
5587 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
5590 /* Fail, don't do this conditional execution. */
5593 *p_false
= NULL_RTX
;
5595 fprintf (dump_file
, "Disabling this conditional execution.\n");
5601 /* A C expression to modify the code described by the conditional if
5602 information CE_INFO, for the basic block BB, possibly updating the tests in
5603 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5604 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5605 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5607 /* p_true and p_false are given expressions of the form:
5609 (and (eq:CC_CCR (reg:CC_CCR)
5615 frv_ifcvt_modify_multiple_tests (ce_if_block_t
*ce_info
,
5620 rtx old_true
= XEXP (*p_true
, 0);
5621 rtx old_false
= XEXP (*p_false
, 0);
5622 rtx true_expr
= XEXP (*p_true
, 1);
5623 rtx false_expr
= XEXP (*p_false
, 1);
5626 rtx cr
= XEXP (old_true
, 0);
5628 rtx new_cr
= NULL_RTX
;
5629 rtx
*p_new_cr
= (rtx
*)0;
5633 enum reg_class cr_class
;
5634 enum machine_mode mode
= GET_MODE (true_expr
);
5635 rtx (*logical_func
)(rtx
, rtx
, rtx
);
5637 if (TARGET_DEBUG_COND_EXEC
)
5640 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5641 ce_info
->and_and_p
? "&&" : "||");
5643 debug_rtx (*p_true
);
5645 fputs ("\nfalse insn:\n", stderr
);
5646 debug_rtx (*p_false
);
5649 if (!TARGET_MULTI_CE
)
5652 if (GET_CODE (cr
) != REG
)
5655 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5657 cr_class
= ICR_REGS
;
5658 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
5660 else if (mode
== CC_FPmode
)
5662 cr_class
= FCR_REGS
;
5663 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
5668 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5669 more &&/|| tests. */
5673 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
5674 CC_CCRmode
, TRUE
, TRUE
);
5679 if (ce_info
->and_and_p
)
5681 old_test
= old_false
;
5682 test_expr
= true_expr
;
5683 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
5684 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5685 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5689 old_test
= old_false
;
5690 test_expr
= false_expr
;
5691 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
5692 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5693 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5696 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5697 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5699 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
5701 /* Now add the conditional check insn. */
5702 cc
= XEXP (test_expr
, 0);
5703 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
5704 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
5706 check_insn
= gen_rtx_SET (VOIDmode
, new_cr
, if_else
);
5708 /* Add the new check insn to the list of check insns that need to be
5710 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
5712 if (TARGET_DEBUG_COND_EXEC
)
5714 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5717 debug_rtx (*p_true
);
5719 fputs ("\nfalse insn:\n", stderr
);
5720 debug_rtx (*p_false
);
5726 *p_true
= *p_false
= NULL_RTX
;
5728 /* If we allocated a CR register, release it. */
5731 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
5732 *p_new_cr
= NULL_RTX
;
5735 if (TARGET_DEBUG_COND_EXEC
)
5736 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
5742 /* Return a register which will be loaded with a value if an IF block is
5743 converted to conditional execution. This is used to rewrite instructions
5744 that use constants to ones that just use registers. */
5747 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
5749 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
5753 /* We know gr0 == 0, so replace any errant uses. */
5754 if (value
== const0_rtx
)
5755 return gen_rtx_REG (SImode
, GPR_FIRST
);
5757 /* First search all registers currently loaded to see if we have an
5758 applicable constant. */
5759 if (CONSTANT_P (value
)
5760 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
5762 for (i
= 0; i
< num_alloc
; i
++)
5764 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
5765 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
5769 /* Have we exhausted the number of registers available? */
5770 if (num_alloc
>= GPR_TEMP_NUM
)
5773 fprintf (dump_file
, "Too many temporary registers allocated\n");
5778 /* Allocate the new register. */
5779 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
5783 fputs ("Could not find a scratch register\n", dump_file
);
5788 frv_ifcvt
.cur_scratch_regs
++;
5789 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (VOIDmode
, reg
, value
);
5793 if (GET_CODE (value
) == CONST_INT
)
5794 fprintf (dump_file
, "Register %s will hold %ld\n",
5795 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
5797 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
5798 fprintf (dump_file
, "Register %s will hold LR\n",
5799 reg_names
[ REGNO (reg
)]);
5802 fprintf (dump_file
, "Register %s will hold a saved value\n",
5803 reg_names
[ REGNO (reg
)]);
5810 /* Update a MEM used in conditional code that might contain an offset to put
5811 the offset into a scratch register, so that the conditional load/store
5812 operations can be used. This function returns the original pointer if the
5813 MEM is valid to use in conditional code, NULL if we can't load up the offset
5814 into a temporary register, or the new MEM if we were successful. */
5817 frv_ifcvt_rewrite_mem (rtx mem
, enum machine_mode mode
, rtx insn
)
5819 rtx addr
= XEXP (mem
, 0);
5821 if (!frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
))
5823 if (GET_CODE (addr
) == PLUS
)
5825 rtx addr_op0
= XEXP (addr
, 0);
5826 rtx addr_op1
= XEXP (addr
, 1);
5828 if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
5830 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
5834 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
5841 else if (CONSTANT_P (addr
))
5842 addr
= frv_ifcvt_load_value (addr
, insn
);
5847 if (addr
== NULL_RTX
)
5850 else if (XEXP (mem
, 0) != addr
)
5851 return change_address (mem
, mode
, addr
);
5858 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5859 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5862 single_set_pattern (rtx pattern
)
5867 if (GET_CODE (pattern
) == COND_EXEC
)
5868 pattern
= COND_EXEC_CODE (pattern
);
5870 if (GET_CODE (pattern
) == SET
)
5873 else if (GET_CODE (pattern
) == PARALLEL
)
5875 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
5877 rtx sub
= XVECEXP (pattern
, 0, i
);
5879 switch (GET_CODE (sub
))
5903 /* A C expression to modify the code described by the conditional if
5904 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5905 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5906 insn cannot be converted to be executed conditionally. */
5909 frv_ifcvt_modify_insn (ce_if_block_t
*ce_info
,
5913 rtx orig_ce_pattern
= pattern
;
5919 gcc_assert (GET_CODE (pattern
) == COND_EXEC
);
5921 test
= COND_EXEC_TEST (pattern
);
5922 if (GET_CODE (test
) == AND
)
5924 rtx cr
= frv_ifcvt
.cr_reg
;
5927 op0
= XEXP (test
, 0);
5928 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
5931 op1
= XEXP (test
, 1);
5932 test_reg
= XEXP (op1
, 0);
5933 if (GET_CODE (test_reg
) != REG
)
5936 /* Is this the first nested if block in this sequence? If so, generate
5937 an andcr or andncr. */
5938 if (! frv_ifcvt
.last_nested_if_cr
)
5942 frv_ifcvt
.last_nested_if_cr
= test_reg
;
5943 if (GET_CODE (op0
) == NE
)
5944 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
5946 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
5948 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
5951 /* If this isn't the first statement in the nested if sequence, see if we
5952 are dealing with the same register. */
5953 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
5956 COND_EXEC_TEST (pattern
) = test
= op1
;
5959 /* If this isn't a nested if, reset state variables. */
5962 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5965 set
= single_set_pattern (pattern
);
5968 rtx dest
= SET_DEST (set
);
5969 rtx src
= SET_SRC (set
);
5970 enum machine_mode mode
= GET_MODE (dest
);
5972 /* Check for normal binary operators. */
5973 if (mode
== SImode
&& ARITHMETIC_P (src
))
5975 op0
= XEXP (src
, 0);
5976 op1
= XEXP (src
, 1);
5978 if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
5980 op1
= frv_ifcvt_load_value (op1
, insn
);
5982 COND_EXEC_CODE (pattern
)
5983 = gen_rtx_SET (VOIDmode
, dest
, gen_rtx_fmt_ee (GET_CODE (src
),
5991 /* For multiply by a constant, we need to handle the sign extending
5992 correctly. Add a USE of the value after the multiply to prevent flow
5993 from cratering because only one register out of the two were used. */
5994 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
5996 op0
= XEXP (src
, 0);
5997 op1
= XEXP (src
, 1);
5998 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
6000 op1
= frv_ifcvt_load_value (op1
, insn
);
6003 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
6004 COND_EXEC_CODE (pattern
)
6005 = gen_rtx_SET (VOIDmode
, dest
,
6006 gen_rtx_MULT (DImode
, op0
, op1
));
6012 frv_ifcvt_add_insn (gen_use (dest
), insn
, FALSE
);
6015 /* If we are just loading a constant created for a nested conditional
6016 execution statement, just load the constant without any conditional
6017 execution, since we know that the constant will not interfere with any
6019 else if (frv_ifcvt
.scratch_insns_bitmap
6020 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
6022 && REG_P (SET_DEST (set
))
6023 /* We must not unconditionally set a scratch reg chosen
6024 for a nested if-converted block if its incoming
6025 value from the TEST block (or the result of the THEN
6026 branch) could/should propagate to the JOIN block.
6027 It suffices to test whether the register is live at
6028 the JOIN point: if it's live there, we can infer
6029 that we set it in the former JOIN block of the
6030 nested if-converted block (otherwise it wouldn't
6031 have been available as a scratch register), and it
6032 is either propagated through or set in the other
6033 conditional block. It's probably not worth trying
6034 to catch the latter case, and it could actually
6035 limit scheduling of the combined block quite
6038 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->join_bb
),
6039 REGNO (SET_DEST (set
))))
6040 /* Similarly, we must not unconditionally set a reg
6041 used as scratch in the THEN branch if the same reg
6042 is live in the ELSE branch. */
6043 && (! ce_info
->else_bb
6044 || BLOCK_FOR_INSN (insn
) == ce_info
->else_bb
6045 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->else_bb
),
6046 REGNO (SET_DEST (set
))))))
6049 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
6052 int changed_p
= FALSE
;
6054 /* Check for just loading up a constant */
6055 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
6057 src
= frv_ifcvt_load_value (src
, insn
);
6064 /* See if we need to fix up stores */
6065 if (GET_CODE (dest
) == MEM
)
6067 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
6072 else if (new_mem
!= dest
)
6079 /* See if we need to fix up loads */
6080 if (GET_CODE (src
) == MEM
)
6082 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
6087 else if (new_mem
!= src
)
6094 /* If either src or destination changed, redo SET. */
6096 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
6099 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6100 rewriting the CC register to be the same as the paired CC/CR register
6102 else if (mode
== CC_CCRmode
&& COMPARISON_P (src
))
6104 int regno
= REGNO (XEXP (src
, 0));
6107 if (ce_info
->pass
> 1
6108 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
6109 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
6111 src
= gen_rtx_fmt_ee (GET_CODE (src
),
6113 frv_ifcvt
.nested_cc_reg
,
6117 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
6118 pattern
= gen_rtx_SET (VOIDmode
, dest
, if_else
);
6121 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6122 else if (ce_info
->pass
> 1
6123 && GET_CODE (dest
) == REG
6124 && CC_P (REGNO (dest
))
6125 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
6126 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
6128 && GET_CODE (src
) == COMPARE
)
6130 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
6131 COND_EXEC_CODE (pattern
)
6132 = gen_rtx_SET (VOIDmode
, frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
6136 if (TARGET_DEBUG_COND_EXEC
)
6138 rtx orig_pattern
= PATTERN (insn
);
6140 PATTERN (insn
) = pattern
;
6142 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6146 PATTERN (insn
) = orig_pattern
;
6152 if (TARGET_DEBUG_COND_EXEC
)
6154 rtx orig_pattern
= PATTERN (insn
);
6156 PATTERN (insn
) = orig_ce_pattern
;
6158 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6162 PATTERN (insn
) = orig_pattern
;
6169 /* A C expression to perform any final machine dependent modifications in
6170 converting code to conditional execution in the code described by the
6171 conditional if information CE_INFO. */
6174 frv_ifcvt_modify_final (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6178 rtx p
= frv_ifcvt
.added_insns_list
;
6181 /* Loop inserting the check insns. The last check insn is the first test,
6182 and is the appropriate place to insert constants. */
6187 rtx check_and_insert_insns
= XEXP (p
, 0);
6190 check_insn
= XEXP (check_and_insert_insns
, 0);
6191 existing_insn
= XEXP (check_and_insert_insns
, 1);
6194 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6195 the existing insn, otherwise it is to be inserted AFTER. */
6196 if (check_and_insert_insns
->jump
)
6198 emit_insn_before (check_insn
, existing_insn
);
6199 check_and_insert_insns
->jump
= 0;
6202 emit_insn_after (check_insn
, existing_insn
);
6204 free_EXPR_LIST_node (check_and_insert_insns
);
6205 free_EXPR_LIST_node (old_p
);
6207 while (p
!= NULL_RTX
);
6209 /* Load up any constants needed into temp gprs */
6210 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6212 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
6213 if (! frv_ifcvt
.scratch_insns_bitmap
)
6214 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_ALLOC (NULL
);
6215 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
6216 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6219 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6220 frv_ifcvt
.cur_scratch_regs
= 0;
6224 /* A C expression to cancel any machine dependent modifications in converting
6225 code to conditional execution in the code described by the conditional if
6226 information CE_INFO. */
6229 frv_ifcvt_modify_cancel (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6232 rtx p
= frv_ifcvt
.added_insns_list
;
6234 /* Loop freeing up the EXPR_LIST's allocated. */
6235 while (p
!= NULL_RTX
)
6237 rtx check_and_jump
= XEXP (p
, 0);
6241 free_EXPR_LIST_node (check_and_jump
);
6242 free_EXPR_LIST_node (old_p
);
6245 /* Release any temporary gprs allocated. */
6246 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6247 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6249 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6250 frv_ifcvt
.cur_scratch_regs
= 0;
6254 /* A C expression for the size in bytes of the trampoline, as an integer.
6258 setlo #0, <static_chain>
6260 sethi #0, <static_chain>
6261 jmpl @(gr0,<jmp_reg>) */
6264 frv_trampoline_size (void)
6267 /* Allocate room for the function descriptor and the lddi
6270 return 5 /* instructions */ * 4 /* instruction size. */;
6274 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6275 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6276 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6277 should be passed to the function when it is called.
6282 setlo #0, <static_chain>
6284 sethi #0, <static_chain>
6285 jmpl @(gr0,<jmp_reg>) */
6288 frv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
6290 rtx addr
= XEXP (m_tramp
, 0);
6291 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6292 rtx sc_reg
= force_reg (Pmode
, static_chain
);
6294 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
6295 LCT_NORMAL
, VOIDmode
, 4,
6297 GEN_INT (frv_trampoline_size ()), SImode
,
6303 /* Many machines have some registers that cannot be copied directly to or from
6304 memory or even from other types of registers. An example is the `MQ'
6305 register, which on most machines, can only be copied to or from general
6306 registers, but not memory. Some machines allow copying all registers to and
6307 from memory, but require a scratch register for stores to some memory
6308 locations (e.g., those with symbolic address on the RT, and those with
6309 certain symbolic address on the SPARC when compiling PIC). In some cases,
6310 both an intermediate and a scratch register are required.
6312 You should define these macros to indicate to the reload phase that it may
6313 need to allocate at least one register for a reload in addition to the
6314 register to contain the data. Specifically, if copying X to a register
6315 RCLASS in MODE requires an intermediate register, you should define
6316 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6317 whose registers can be used as intermediate registers or scratch registers.
6319 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6320 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6321 largest register class required. If the requirements for input and output
6322 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6323 instead of defining both macros identically.
6325 The values returned by these macros are often `GENERAL_REGS'. Return
6326 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6327 to or from a register of RCLASS in MODE without requiring a scratch register.
6328 Do not define this macro if it would always return `NO_REGS'.
6330 If a scratch register is required (either with or without an intermediate
6331 register), you should define patterns for `reload_inM' or `reload_outM', as
6332 required.. These patterns, which will normally be implemented with a
6333 `define_expand', should be similar to the `movM' patterns, except that
6334 operand 2 is the scratch register.
6336 Define constraints for the reload register and scratch register that contain
6337 a single register class. If the original reload register (whose class is
6338 RCLASS) can meet the constraint given in the pattern, the value returned by
6339 these macros is used for the class of the scratch register. Otherwise, two
6340 additional reload registers are required. Their classes are obtained from
6341 the constraints in the insn pattern.
6343 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6344 either be in a hard register or in memory. Use `true_regnum' to find out;
6345 it will return -1 if the pseudo is in memory and the hard register number if
6346 it is in a register.
6348 These macros should not be used in the case where a particular class of
6349 registers can only be copied to memory and not to another class of
6350 registers. In that case, secondary reload registers are not needed and
6351 would not be helpful. Instead, a stack location must be used to perform the
6352 copy and the `movM' pattern should use memory as an intermediate storage.
6353 This case often occurs between floating-point and general registers. */
6356 frv_secondary_reload_class (enum reg_class rclass
,
6357 enum machine_mode mode ATTRIBUTE_UNUSED
,
6368 /* Accumulators/Accumulator guard registers need to go through floating
6374 if (x
&& GET_CODE (x
) == REG
)
6376 int regno
= REGNO (x
);
6378 if (ACC_P (regno
) || ACCG_P (regno
))
6383 /* Nonzero constants should be loaded into an FPR through a GPR. */
6387 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
6393 /* All of these types need gpr registers. */
6405 /* The accumulators need fpr registers. */
6417 /* This hook exists to catch the case where secondary_reload_class() is
6418 called from init_reg_autoinc() in regclass.c - before the reload optabs
6419 have been initialised. */
6422 frv_secondary_reload (bool in_p
, rtx x
, reg_class_t reload_class_i
,
6423 enum machine_mode reload_mode
,
6424 secondary_reload_info
* sri
)
6426 enum reg_class rclass
= NO_REGS
;
6427 enum reg_class reload_class
= (enum reg_class
) reload_class_i
;
6429 if (sri
->prev_sri
&& sri
->prev_sri
->t_icode
!= CODE_FOR_nothing
)
6431 sri
->icode
= sri
->prev_sri
->t_icode
;
6435 rclass
= frv_secondary_reload_class (reload_class
, reload_mode
, x
);
6437 if (rclass
!= NO_REGS
)
6439 enum insn_code icode
6440 = direct_optab_handler (in_p
? reload_in_optab
: reload_out_optab
,
6444 /* This happens when then the reload_[in|out]_optabs have
6445 not been initialised. */
6446 sri
->t_icode
= CODE_FOR_nothing
;
6451 /* Fall back to the default secondary reload handler. */
6452 return default_secondary_reload (in_p
, x
, reload_class
, reload_mode
, sri
);
6456 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6459 frv_class_likely_spilled_p (reg_class_t rclass
)
6469 case FDPIC_FPTR_REGS
:
6491 /* An expression for the alignment of a structure field FIELD if the
6492 alignment computed in the usual way is COMPUTED. GCC uses this
6493 value instead of the value in `BIGGEST_ALIGNMENT' or
6494 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6496 /* The definition type of the bit field data is either char, short, long or
6497 long long. The maximum bit size is the number of bits of its own type.
6499 The bit field data is assigned to a storage unit that has an adequate size
6500 for bit field data retention and is located at the smallest address.
6502 Consecutive bit field data are packed at consecutive bits having the same
6503 storage unit, with regard to the type, beginning with the MSB and continuing
6506 If a field to be assigned lies over a bit field type boundary, its
6507 assignment is completed by aligning it with a boundary suitable for the
6510 When a bit field having a bit length of 0 is declared, it is forcibly
6511 assigned to the next storage unit.
6524 &x 00000000 00000000 00000000 00000000
6527 &x+4 00000000 00000000 00000000 00000000
6530 &x+8 00000000 00000000 00000000 00000000
6533 &x+12 00000000 00000000 00000000 00000000
6539 frv_adjust_field_align (tree field
, int computed
)
6541 /* Make sure that the bitfield is not wider than the type. */
6542 if (DECL_BIT_FIELD (field
)
6543 && !DECL_ARTIFICIAL (field
))
6545 tree parent
= DECL_CONTEXT (field
);
6546 tree prev
= NULL_TREE
;
6549 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= DECL_CHAIN (cur
))
6551 if (TREE_CODE (cur
) != FIELD_DECL
)
6559 /* If this isn't a :0 field and if the previous element is a bitfield
6560 also, see if the type is different, if so, we will need to align the
6561 bit-field to the next boundary. */
6563 && ! DECL_PACKED (field
)
6564 && ! integer_zerop (DECL_SIZE (field
))
6565 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
6567 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
6568 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
6569 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
6577 /* A C expression that is nonzero if it is permissible to store a value of mode
6578 MODE in hard register number REGNO (or in several registers starting with
6579 that one). For a machine where all registers are equivalent, a suitable
6582 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6584 It is not necessary for this macro to check for the numbers of fixed
6585 registers, because the allocation mechanism considers them to be always
6588 On some machines, double-precision values must be kept in even/odd register
6589 pairs. The way to implement that is to define this macro to reject odd
6590 register numbers for such modes.
6592 The minimum requirement for a mode to be OK in a register is that the
6593 `movMODE' instruction pattern support moves between the register and any
6594 other hard register for which the mode is OK; and that moving a value into
6595 the register and back out not alter it.
6597 Since the same instruction used to move `SImode' will work for all narrower
6598 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6599 to distinguish between these modes, provided you define patterns `movhi',
6600 etc., to take advantage of this. This is useful because of the interaction
6601 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6602 all integer modes to be tieable.
6604 Many machines have special registers for floating point arithmetic. Often
6605 people assume that floating point machine modes are allowed only in floating
6606 point registers. This is not true. Any registers that can hold integers
6607 can safely *hold* a floating point machine mode, whether or not floating
6608 arithmetic can be done on it in those registers. Integer move instructions
6609 can be used to move the values.
6611 On some machines, though, the converse is true: fixed-point machine modes
6612 may not go in floating registers. This is true if the floating registers
6613 normalize any value stored in them, because storing a non-floating value
6614 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6615 fixed-point machine modes in floating registers. But if the floating
6616 registers do not automatically normalize, if you can store any bit pattern
6617 in one and retrieve it unchanged without a trap, then any machine mode may
6618 go in a floating register, so you can define this macro to say so.
6620 The primary significance of special floating registers is rather that they
6621 are the registers acceptable in floating point arithmetic instructions.
6622 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6623 writing the proper constraints for those instructions.
6625 On some machines, the floating registers are especially slow to access, so
6626 that it is better to store a value in a stack frame than in such a register
6627 if floating point arithmetic is not being done. As long as the floating
6628 registers are not in class `GENERAL_REGS', they will not be used unless some
6629 pattern's constraint asks for one. */
6632 frv_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
6642 return ICC_P (regno
) || GPR_P (regno
);
6645 return CR_P (regno
) || GPR_P (regno
);
6648 return FCC_P (regno
) || GPR_P (regno
);
6654 /* Set BASE to the first register in REGNO's class. Set MASK to the
6655 bits that must be clear in (REGNO - BASE) for the register to be
6657 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
6661 /* ACCGs store one byte. Two-byte quantities must start in
6662 even-numbered registers, four-byte ones in registers whose
6663 numbers are divisible by four, and so on. */
6665 mask
= GET_MODE_SIZE (mode
) - 1;
6669 /* The other registers store one word. */
6670 if (GPR_P (regno
) || regno
== AP_FIRST
)
6673 else if (FPR_P (regno
))
6676 else if (ACC_P (regno
))
6679 else if (SPR_P (regno
))
6680 return mode
== SImode
;
6682 /* Fill in the table. */
6686 /* Anything smaller than an SI is OK in any word-sized register. */
6687 if (GET_MODE_SIZE (mode
) < 4)
6690 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
6692 return (((regno
- base
) & mask
) == 0);
6699 /* A C expression for the number of consecutive hard registers, starting at
6700 register number REGNO, required to hold a value of mode MODE.
6702 On a machine where all registers are exactly one word, a suitable definition
6705 #define HARD_REGNO_NREGS(REGNO, MODE) \
6706 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6707 / UNITS_PER_WORD)) */
6709 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6710 that we can build the appropriate instructions to properly reload the
6711 values. Also, make the byte-sized accumulator guards use one guard
6715 frv_hard_regno_nregs (int regno
, enum machine_mode mode
)
6718 return GET_MODE_SIZE (mode
);
6720 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6724 /* A C expression for the maximum number of consecutive registers of
6725 class RCLASS needed to hold a value of mode MODE.
6727 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6728 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6729 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6731 This macro helps control the handling of multiple-word values in
6734 This declaration is required. */
6737 frv_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
6739 if (rclass
== ACCG_REGS
)
6740 /* An N-byte value requires N accumulator guards. */
6741 return GET_MODE_SIZE (mode
);
6743 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6747 /* A C expression that is nonzero if X is a legitimate constant for an
6748 immediate operand on the target machine. You can assume that X satisfies
6749 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6750 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6753 frv_legitimate_constant_p (rtx x
)
6755 enum machine_mode mode
= GET_MODE (x
);
6757 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6758 means that the move expanders will be expected to deal with most
6759 kinds of constant, regardless of what we return here.
6761 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6762 a constant can be entered into reg_equiv_constant[]. If we return true,
6763 reload can create new instances of the constant whenever it likes.
6765 The idea is therefore to accept as many constants as possible (to give
6766 reload more freedom) while rejecting constants that can only be created
6767 at certain times. In particular, anything with a symbolic component will
6768 require use of the pseudo FDPIC register, which is only available before
6771 return LEGITIMATE_PIC_OPERAND_P (x
);
6773 /* All of the integer constants are ok. */
6774 if (GET_CODE (x
) != CONST_DOUBLE
)
6777 /* double integer constants are ok. */
6778 if (mode
== VOIDmode
|| mode
== DImode
)
6781 /* 0 is always ok. */
6782 if (x
== CONST0_RTX (mode
))
6785 /* If floating point is just emulated, allow any constant, since it will be
6786 constructed in the GPRs. */
6787 if (!TARGET_HAS_FPRS
)
6790 if (mode
== DFmode
&& !TARGET_DOUBLE
)
6793 /* Otherwise store the constant away and do a load. */
6797 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6798 CC_NZ for comparisons against zero in which a single Z or N flag test
6799 is enough, CC_UNS for other unsigned comparisons, and CC for other
6800 signed comparisons. */
6803 frv_select_cc_mode (enum rtx_code code
, rtx x
, rtx y
)
6805 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6814 return y
== const0_rtx
? CC_NZmode
: CCmode
;
6820 return y
== const0_rtx
? CC_NZmode
: CC_UNSmode
;
6828 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6830 #define HIGH_COST 40
6831 #define MEDIUM_COST 3
6835 frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
6836 reg_class_t from
, reg_class_t to
)
6920 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6923 frv_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
6924 reg_class_t rclass ATTRIBUTE_UNUSED
,
6925 bool in ATTRIBUTE_UNUSED
)
6931 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6932 use ".picptr" to generate safe relocations for PIC code. We also
6933 need a fixup entry for aligned (non-debugging) code. */
6936 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
6938 if ((flag_pic
|| TARGET_FDPIC
) && size
== UNITS_PER_WORD
)
6940 if (GET_CODE (value
) == CONST
6941 || GET_CODE (value
) == SYMBOL_REF
6942 || GET_CODE (value
) == LABEL_REF
)
6944 if (TARGET_FDPIC
&& GET_CODE (value
) == SYMBOL_REF
6945 && SYMBOL_REF_FUNCTION_P (value
))
6947 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
6948 output_addr_const (asm_out_file
, value
);
6949 fputs (")\n", asm_out_file
);
6952 else if (TARGET_FDPIC
&& GET_CODE (value
) == CONST
6953 && frv_function_symbol_referenced_p (value
))
6955 if (aligned_p
&& !TARGET_FDPIC
)
6957 static int label_num
= 0;
6961 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
6962 p
= (* targetm
.strip_name_encoding
) (buf
);
6964 fprintf (asm_out_file
, "%s:\n", p
);
6965 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
6966 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
6967 fprintf (asm_out_file
, "\t.previous\n");
6969 assemble_integer_with_op ("\t.picptr\t", value
);
6974 /* We've set the unaligned SI op to NULL, so we always have to
6975 handle the unaligned case here. */
6976 assemble_integer_with_op ("\t.4byte\t", value
);
6980 return default_assemble_integer (value
, size
, aligned_p
);
6983 /* Function to set up the backend function structure. */
6985 static struct machine_function
*
6986 frv_init_machine_status (void)
6988 return ggc_alloc_cleared_machine_function ();
6991 /* Implement TARGET_SCHED_ISSUE_RATE. */
6994 frv_issue_rate (void)
6999 switch (frv_cpu_type
)
7003 case FRV_CPU_SIMPLE
:
7011 case FRV_CPU_GENERIC
:
7013 case FRV_CPU_TOMCAT
:
7021 /* A for_each_rtx callback. If X refers to an accumulator, return
7022 ACC_GROUP_ODD if the bit 2 of the register number is set and
7023 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7027 frv_acc_group_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
7031 if (ACC_P (REGNO (*x
)))
7032 return (REGNO (*x
) - ACC_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7033 if (ACCG_P (REGNO (*x
)))
7034 return (REGNO (*x
) - ACCG_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7039 /* Return the value of INSN's acc_group attribute. */
7042 frv_acc_group (rtx insn
)
7044 /* This distinction only applies to the FR550 packing constraints. */
7045 if (frv_cpu_type
!= FRV_CPU_FR550
)
7046 return ACC_GROUP_NONE
;
7047 return for_each_rtx (&PATTERN (insn
), frv_acc_group_1
, 0);
7050 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7051 INSN will try to claim first. Since this value depends only on the
7052 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7055 frv_insn_unit (rtx insn
)
7057 enum attr_type type
;
7059 type
= get_attr_type (insn
);
7060 if (frv_type_to_unit
[type
] == ARRAY_SIZE (frv_unit_codes
))
7062 /* We haven't seen this type of instruction before. */
7066 /* Issue the instruction on its own to see which unit it prefers. */
7067 state
= alloca (state_size ());
7068 state_reset (state
);
7069 state_transition (state
, insn
);
7071 /* Find out which unit was taken. */
7072 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_codes
); unit
++)
7073 if (cpu_unit_reservation_p (state
, frv_unit_codes
[unit
]))
7076 gcc_assert (unit
!= ARRAY_SIZE (frv_unit_codes
));
7078 frv_type_to_unit
[type
] = unit
;
7080 return frv_type_to_unit
[type
];
7083 /* Return true if INSN issues to a branch unit. */
7086 frv_issues_to_branch_unit_p (rtx insn
)
7088 return frv_unit_groups
[frv_insn_unit (insn
)] == GROUP_B
;
7091 /* The instructions in the packet, partitioned into groups. */
7092 struct frv_packet_group
{
7093 /* How many instructions in the packet belong to this group. */
7094 unsigned int num_insns
;
7096 /* A list of the instructions that belong to this group, in the order
7097 they appear in the rtl stream. */
7098 rtx insns
[ARRAY_SIZE (frv_unit_codes
)];
7100 /* The contents of INSNS after they have been sorted into the correct
7101 assembly-language order. Element X issues to unit X. The list may
7102 contain extra nops. */
7103 rtx sorted
[ARRAY_SIZE (frv_unit_codes
)];
7105 /* The member of frv_nops[] to use in sorted[]. */
7109 /* The current state of the packing pass, implemented by frv_pack_insns. */
7111 /* The state of the pipeline DFA. */
7114 /* Which hardware registers are set within the current packet,
7115 and the conditions under which they are set. */
7116 regstate_t regstate
[FIRST_PSEUDO_REGISTER
];
7118 /* The memory locations that have been modified so far in this
7119 packet. MEM is the memref and COND is the regstate_t condition
7120 under which it is set. */
7126 /* The number of valid entries in MEMS. The value is larger than
7127 ARRAY_SIZE (mems) if there were too many mems to record. */
7128 unsigned int num_mems
;
7130 /* The maximum number of instructions that can be packed together. */
7131 unsigned int issue_rate
;
7133 /* The instructions in the packet, partitioned into groups. */
7134 struct frv_packet_group groups
[NUM_GROUPS
];
7136 /* The instructions that make up the current packet. */
7137 rtx insns
[ARRAY_SIZE (frv_unit_codes
)];
7138 unsigned int num_insns
;
7141 /* Return the regstate_t flags for the given COND_EXEC condition.
7142 Abort if the condition isn't in the right form. */
7145 frv_cond_flags (rtx cond
)
7147 gcc_assert ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
7148 && GET_CODE (XEXP (cond
, 0)) == REG
7149 && CR_P (REGNO (XEXP (cond
, 0)))
7150 && XEXP (cond
, 1) == const0_rtx
);
7151 return ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
7152 | (GET_CODE (cond
) == NE
7154 : REGSTATE_IF_FALSE
));
7158 /* Return true if something accessed under condition COND2 can
7159 conflict with something written under condition COND1. */
7162 frv_regstate_conflict_p (regstate_t cond1
, regstate_t cond2
)
7164 /* If either reference was unconditional, we have a conflict. */
7165 if ((cond1
& REGSTATE_IF_EITHER
) == 0
7166 || (cond2
& REGSTATE_IF_EITHER
) == 0)
7169 /* The references might conflict if they were controlled by
7171 if ((cond1
& REGSTATE_CC_MASK
) != (cond2
& REGSTATE_CC_MASK
))
7174 /* They definitely conflict if they are controlled by the
7176 if ((cond1
& cond2
& REGSTATE_IF_EITHER
) != 0)
7183 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7184 the current packet. DATA points to a regstate_t that describes the
7185 condition under which *X might be set or used. */
7188 frv_registers_conflict_p_1 (rtx
*x
, void *data
)
7190 unsigned int regno
, i
;
7193 cond
= *(regstate_t
*) data
;
7195 if (GET_CODE (*x
) == REG
)
7196 FOR_EACH_REGNO (regno
, *x
)
7197 if ((frv_packet
.regstate
[regno
] & REGSTATE_MODIFIED
) != 0)
7198 if (frv_regstate_conflict_p (frv_packet
.regstate
[regno
], cond
))
7201 if (GET_CODE (*x
) == MEM
)
7203 /* If we ran out of memory slots, assume a conflict. */
7204 if (frv_packet
.num_mems
> ARRAY_SIZE (frv_packet
.mems
))
7207 /* Check for output or true dependencies with earlier MEMs. */
7208 for (i
= 0; i
< frv_packet
.num_mems
; i
++)
7209 if (frv_regstate_conflict_p (frv_packet
.mems
[i
].cond
, cond
))
7211 if (true_dependence (frv_packet
.mems
[i
].mem
, VOIDmode
,
7215 if (output_dependence (frv_packet
.mems
[i
].mem
, *x
))
7220 /* The return values of calls aren't significant: they describe
7221 the effect of the call as a whole, not of the insn itself. */
7222 if (GET_CODE (*x
) == SET
&& GET_CODE (SET_SRC (*x
)) == CALL
)
7224 if (for_each_rtx (&SET_SRC (*x
), frv_registers_conflict_p_1
, data
))
7229 /* Check subexpressions. */
7234 /* Return true if something in X might depend on an instruction
7235 in the current packet. */
7238 frv_registers_conflict_p (rtx x
)
7243 if (GET_CODE (x
) == COND_EXEC
)
7245 if (for_each_rtx (&XEXP (x
, 0), frv_registers_conflict_p_1
, &flags
))
7248 flags
|= frv_cond_flags (XEXP (x
, 0));
7251 return for_each_rtx (&x
, frv_registers_conflict_p_1
, &flags
);
7255 /* A note_stores callback. DATA points to the regstate_t condition
7256 under which X is modified. Update FRV_PACKET accordingly. */
7259 frv_registers_update_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7263 if (GET_CODE (x
) == REG
)
7264 FOR_EACH_REGNO (regno
, x
)
7265 frv_packet
.regstate
[regno
] |= *(regstate_t
*) data
;
7267 if (GET_CODE (x
) == MEM
)
7269 if (frv_packet
.num_mems
< ARRAY_SIZE (frv_packet
.mems
))
7271 frv_packet
.mems
[frv_packet
.num_mems
].mem
= x
;
7272 frv_packet
.mems
[frv_packet
.num_mems
].cond
= *(regstate_t
*) data
;
7274 frv_packet
.num_mems
++;
7279 /* Update the register state information for an instruction whose
7283 frv_registers_update (rtx x
)
7287 flags
= REGSTATE_MODIFIED
;
7288 if (GET_CODE (x
) == COND_EXEC
)
7290 flags
|= frv_cond_flags (XEXP (x
, 0));
7293 note_stores (x
, frv_registers_update_1
, &flags
);
7297 /* Initialize frv_packet for the start of a new packet. */
7300 frv_start_packet (void)
7302 enum frv_insn_group group
;
7304 memset (frv_packet
.regstate
, 0, sizeof (frv_packet
.regstate
));
7305 frv_packet
.num_mems
= 0;
7306 frv_packet
.num_insns
= 0;
7307 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7308 group
= (enum frv_insn_group
) (group
+ 1))
7309 frv_packet
.groups
[group
].num_insns
= 0;
7313 /* Likewise for the start of a new basic block. */
7316 frv_start_packet_block (void)
7318 state_reset (frv_packet
.dfa_state
);
7319 frv_start_packet ();
7323 /* Finish the current packet, if any, and start a new one. Call
7324 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7327 frv_finish_packet (void (*handle_packet
) (void))
7329 if (frv_packet
.num_insns
> 0)
7332 state_transition (frv_packet
.dfa_state
, 0);
7333 frv_start_packet ();
7338 /* Return true if INSN can be added to the current packet. Update
7339 the DFA state on success. */
7342 frv_pack_insn_p (rtx insn
)
7344 /* See if the packet is already as long as it can be. */
7345 if (frv_packet
.num_insns
== frv_packet
.issue_rate
)
7348 /* If the scheduler thought that an instruction should start a packet,
7349 it's usually a good idea to believe it. It knows much more about
7350 the latencies than we do.
7352 There are some exceptions though:
7354 - Conditional instructions are scheduled on the assumption that
7355 they will be executed. This is usually a good thing, since it
7356 tends to avoid unnecessary stalls in the conditional code.
7357 But we want to pack conditional instructions as tightly as
7358 possible, in order to optimize the case where they aren't
7361 - The scheduler will always put branches on their own, even
7362 if there's no real dependency.
7364 - There's no point putting a call in its own packet unless
7366 if (frv_packet
.num_insns
> 0
7367 && GET_CODE (insn
) == INSN
7368 && GET_MODE (insn
) == TImode
7369 && GET_CODE (PATTERN (insn
)) != COND_EXEC
)
7372 /* Check for register conflicts. Don't do this for setlo since any
7373 conflict will be with the partnering sethi, with which it can
7375 if (get_attr_type (insn
) != TYPE_SETLO
)
7376 if (frv_registers_conflict_p (PATTERN (insn
)))
7379 return state_transition (frv_packet
.dfa_state
, insn
) < 0;
7383 /* Add instruction INSN to the current packet. */
7386 frv_add_insn_to_packet (rtx insn
)
7388 struct frv_packet_group
*packet_group
;
7390 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7391 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7392 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7394 frv_registers_update (PATTERN (insn
));
7398 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7399 packet ends in a branch or call, insert the nop before it, otherwise
7403 frv_insert_nop_in_packet (rtx insn
)
7405 struct frv_packet_group
*packet_group
;
7408 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7409 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
7410 if (GET_CODE (last
) != INSN
)
7412 insn
= emit_insn_before (PATTERN (insn
), last
);
7413 frv_packet
.insns
[frv_packet
.num_insns
- 1] = insn
;
7414 frv_packet
.insns
[frv_packet
.num_insns
++] = last
;
7418 insn
= emit_insn_after (PATTERN (insn
), last
);
7419 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7421 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7425 /* If packing is enabled, divide the instructions into packets and
7426 return true. Call HANDLE_PACKET for each complete packet. */
7429 frv_for_each_packet (void (*handle_packet
) (void))
7431 rtx insn
, next_insn
;
7433 frv_packet
.issue_rate
= frv_issue_rate ();
7435 /* Early exit if we don't want to pack insns. */
7437 || !flag_schedule_insns_after_reload
7438 || !TARGET_VLIW_BRANCH
7439 || frv_packet
.issue_rate
== 1)
7442 /* Set up the initial packing state. */
7444 frv_packet
.dfa_state
= alloca (state_size ());
7446 frv_start_packet_block ();
7447 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
7452 code
= GET_CODE (insn
);
7453 next_insn
= NEXT_INSN (insn
);
7455 if (code
== CODE_LABEL
)
7457 frv_finish_packet (handle_packet
);
7458 frv_start_packet_block ();
7462 switch (GET_CODE (PATTERN (insn
)))
7471 /* Calls mustn't be packed on a TOMCAT. */
7472 if (GET_CODE (insn
) == CALL_INSN
&& frv_cpu_type
== FRV_CPU_TOMCAT
)
7473 frv_finish_packet (handle_packet
);
7475 /* Since the last instruction in a packet determines the EH
7476 region, any exception-throwing instruction must come at
7477 the end of reordered packet. Insns that issue to a
7478 branch unit are bound to come last; for others it's
7479 too hard to predict. */
7480 eh_insn_p
= (find_reg_note (insn
, REG_EH_REGION
, NULL
) != NULL
);
7481 if (eh_insn_p
&& !frv_issues_to_branch_unit_p (insn
))
7482 frv_finish_packet (handle_packet
);
7484 /* Finish the current packet if we can't add INSN to it.
7485 Simulate cycles until INSN is ready to issue. */
7486 if (!frv_pack_insn_p (insn
))
7488 frv_finish_packet (handle_packet
);
7489 while (!frv_pack_insn_p (insn
))
7490 state_transition (frv_packet
.dfa_state
, 0);
7493 /* Add the instruction to the packet. */
7494 frv_add_insn_to_packet (insn
);
7496 /* Calls and jumps end a packet, as do insns that throw
7498 if (code
== CALL_INSN
|| code
== JUMP_INSN
|| eh_insn_p
)
7499 frv_finish_packet (handle_packet
);
7503 frv_finish_packet (handle_packet
);
7508 /* Subroutine of frv_sort_insn_group. We are trying to sort
7509 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7510 language order. We have already picked a new position for
7511 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7512 These instructions will occupy elements [0, LOWER_SLOT) and
7513 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7514 the DFA state after issuing these instructions.
7516 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7517 of the unused instructions. Return true if one such permutation gives
7518 a valid ordering, leaving the successful permutation in sorted[].
7519 Do not modify sorted[] until a valid permutation is found. */
7522 frv_sort_insn_group_1 (enum frv_insn_group group
,
7523 unsigned int lower_slot
, unsigned int upper_slot
,
7524 unsigned int issued
, unsigned int num_insns
,
7527 struct frv_packet_group
*packet_group
;
7533 /* Early success if we've filled all the slots. */
7534 if (lower_slot
== upper_slot
)
7537 packet_group
= &frv_packet
.groups
[group
];
7538 dfa_size
= state_size ();
7539 test_state
= alloca (dfa_size
);
7541 /* Try issuing each unused instruction. */
7542 for (i
= num_insns
- 1; i
+ 1 != 0; i
--)
7543 if (~issued
& (1 << i
))
7545 insn
= packet_group
->sorted
[i
];
7546 memcpy (test_state
, state
, dfa_size
);
7547 if (state_transition (test_state
, insn
) < 0
7548 && cpu_unit_reservation_p (test_state
,
7549 NTH_UNIT (group
, upper_slot
- 1))
7550 && frv_sort_insn_group_1 (group
, lower_slot
, upper_slot
- 1,
7551 issued
| (1 << i
), num_insns
,
7554 packet_group
->sorted
[upper_slot
- 1] = insn
;
7562 /* Compare two instructions by their frv_insn_unit. */
7565 frv_compare_insns (const void *first
, const void *second
)
7567 const rtx
*const insn1
= (rtx
const *) first
,
7568 *const insn2
= (rtx
const *) second
;
7569 return frv_insn_unit (*insn1
) - frv_insn_unit (*insn2
);
7572 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7573 and sort it into assembly language order. See frv.md for a description of
7577 frv_sort_insn_group (enum frv_insn_group group
)
7579 struct frv_packet_group
*packet_group
;
7580 unsigned int first
, i
, nop
, max_unit
, num_slots
;
7581 state_t state
, test_state
;
7584 packet_group
= &frv_packet
.groups
[group
];
7586 /* Assume no nop is needed. */
7587 packet_group
->nop
= 0;
7589 if (packet_group
->num_insns
== 0)
7592 /* Copy insns[] to sorted[]. */
7593 memcpy (packet_group
->sorted
, packet_group
->insns
,
7594 sizeof (rtx
) * packet_group
->num_insns
);
7596 /* Sort sorted[] by the unit that each insn tries to take first. */
7597 if (packet_group
->num_insns
> 1)
7598 qsort (packet_group
->sorted
, packet_group
->num_insns
,
7599 sizeof (rtx
), frv_compare_insns
);
7601 /* That's always enough for branch and control insns. */
7602 if (group
== GROUP_B
|| group
== GROUP_C
)
7605 dfa_size
= state_size ();
7606 state
= alloca (dfa_size
);
7607 test_state
= alloca (dfa_size
);
7609 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7610 consecutively and such that the DFA takes unit X when sorted[X]
7611 is added. Set STATE to the new DFA state. */
7612 state_reset (test_state
);
7613 for (first
= 0; first
< packet_group
->num_insns
; first
++)
7615 memcpy (state
, test_state
, dfa_size
);
7616 if (state_transition (test_state
, packet_group
->sorted
[first
]) >= 0
7617 || !cpu_unit_reservation_p (test_state
, NTH_UNIT (group
, first
)))
7621 /* If all the instructions issued in ascending order, we're done. */
7622 if (first
== packet_group
->num_insns
)
7625 /* Add nops to the end of sorted[] and try each permutation until
7626 we find one that works. */
7627 for (nop
= 0; nop
< frv_num_nops
; nop
++)
7629 max_unit
= frv_insn_unit (frv_nops
[nop
]);
7630 if (frv_unit_groups
[max_unit
] == group
)
7632 packet_group
->nop
= frv_nops
[nop
];
7633 num_slots
= UNIT_NUMBER (max_unit
) + 1;
7634 for (i
= packet_group
->num_insns
; i
< num_slots
; i
++)
7635 packet_group
->sorted
[i
] = frv_nops
[nop
];
7636 if (frv_sort_insn_group_1 (group
, first
, num_slots
,
7637 (1 << first
) - 1, num_slots
, state
))
7644 /* Sort the current packet into assembly-language order. Set packing
7645 flags as appropriate. */
7648 frv_reorder_packet (void)
7650 unsigned int cursor
[NUM_GROUPS
];
7651 rtx insns
[ARRAY_SIZE (frv_unit_groups
)];
7652 unsigned int unit
, to
, from
;
7653 enum frv_insn_group group
;
7654 struct frv_packet_group
*packet_group
;
7656 /* First sort each group individually. */
7657 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7658 group
= (enum frv_insn_group
) (group
+ 1))
7661 frv_sort_insn_group (group
);
7664 /* Go through the unit template and try add an instruction from
7665 that unit's group. */
7667 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_groups
); unit
++)
7669 group
= frv_unit_groups
[unit
];
7670 packet_group
= &frv_packet
.groups
[group
];
7671 if (cursor
[group
] < packet_group
->num_insns
)
7673 /* frv_reorg should have added nops for us. */
7674 gcc_assert (packet_group
->sorted
[cursor
[group
]]
7675 != packet_group
->nop
);
7676 insns
[to
++] = packet_group
->sorted
[cursor
[group
]++];
7680 gcc_assert (to
== frv_packet
.num_insns
);
7682 /* Clear the last instruction's packing flag, thus marking the end of
7683 a packet. Reorder the other instructions relative to it. */
7684 CLEAR_PACKING_FLAG (insns
[to
- 1]);
7685 for (from
= 0; from
< to
- 1; from
++)
7687 remove_insn (insns
[from
]);
7688 add_insn_before (insns
[from
], insns
[to
- 1], NULL
);
7689 SET_PACKING_FLAG (insns
[from
]);
7694 /* Divide instructions into packets. Reorder the contents of each
7695 packet so that they are in the correct assembly-language order.
7697 Since this pass can change the raw meaning of the rtl stream, it must
7698 only be called at the last minute, just before the instructions are
7702 frv_pack_insns (void)
7704 if (frv_for_each_packet (frv_reorder_packet
))
7705 frv_insn_packing_flag
= 0;
7707 frv_insn_packing_flag
= -1;
7710 /* See whether we need to add nops to group GROUP in order to
7711 make a valid packet. */
7714 frv_fill_unused_units (enum frv_insn_group group
)
7716 unsigned int non_nops
, nops
, i
;
7717 struct frv_packet_group
*packet_group
;
7719 packet_group
= &frv_packet
.groups
[group
];
7721 /* Sort the instructions into assembly-language order.
7722 Use nops to fill slots that are otherwise unused. */
7723 frv_sort_insn_group (group
);
7725 /* See how many nops are needed before the final useful instruction. */
7727 for (non_nops
= 0; non_nops
< packet_group
->num_insns
; non_nops
++)
7728 while (packet_group
->sorted
[i
++] == packet_group
->nop
)
7731 /* Insert that many nops into the instruction stream. */
7733 frv_insert_nop_in_packet (packet_group
->nop
);
7736 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7739 frv_same_doubleword_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7741 if (io1
->const_address
!= 0 && io2
->const_address
!= 0)
7742 return io1
->const_address
== io2
->const_address
;
7744 if (io1
->var_address
!= 0 && io2
->var_address
!= 0)
7745 return rtx_equal_p (io1
->var_address
, io2
->var_address
);
7750 /* Return true if operations IO1 and IO2 are guaranteed to complete
7754 frv_io_fixed_order_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7756 /* The order of writes is always preserved. */
7757 if (io1
->type
== FRV_IO_WRITE
&& io2
->type
== FRV_IO_WRITE
)
7760 /* The order of reads isn't preserved. */
7761 if (io1
->type
!= FRV_IO_WRITE
&& io2
->type
!= FRV_IO_WRITE
)
7764 /* One operation is a write and the other is (or could be) a read.
7765 The order is only guaranteed if the accesses are to the same
7767 return frv_same_doubleword_p (io1
, io2
);
7770 /* Generalize I/O operation X so that it covers both X and Y. */
7773 frv_io_union (struct frv_io
*x
, const struct frv_io
*y
)
7775 if (x
->type
!= y
->type
)
7776 x
->type
= FRV_IO_UNKNOWN
;
7777 if (!frv_same_doubleword_p (x
, y
))
7779 x
->const_address
= 0;
7784 /* Fill IO with information about the load or store associated with
7785 membar instruction INSN. */
7788 frv_extract_membar (struct frv_io
*io
, rtx insn
)
7790 extract_insn (insn
);
7791 io
->type
= (enum frv_io_type
) INTVAL (recog_data
.operand
[2]);
7792 io
->const_address
= INTVAL (recog_data
.operand
[1]);
7793 io
->var_address
= XEXP (recog_data
.operand
[0], 0);
7796 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7797 if X is a register and *DATA depends on X. */
7800 frv_io_check_address (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7802 rtx
*other
= (rtx
*) data
;
7804 if (REG_P (x
) && *other
!= 0 && reg_overlap_mentioned_p (x
, *other
))
7808 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7809 Remove every modified register from the set. */
7812 frv_io_handle_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7814 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7818 FOR_EACH_REGNO (regno
, x
)
7819 CLEAR_HARD_REG_BIT (*set
, regno
);
7822 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7823 Add every register in *X to the set. */
7826 frv_io_handle_use_1 (rtx
*x
, void *data
)
7828 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7832 FOR_EACH_REGNO (regno
, *x
)
7833 SET_HARD_REG_BIT (*set
, regno
);
7838 /* A note_stores callback that applies frv_io_handle_use_1 to an
7839 entire rhs value. */
7842 frv_io_handle_use (rtx
*x
, void *data
)
7844 for_each_rtx (x
, frv_io_handle_use_1
, data
);
7847 /* Go through block BB looking for membars to remove. There are two
7848 cases where intra-block analysis is enough:
7850 - a membar is redundant if it occurs between two consecutive I/O
7851 operations and if those operations are guaranteed to complete
7854 - a membar for a __builtin_read is redundant if the result is
7855 used before the next I/O operation is issued.
7857 If the last membar in the block could not be removed, and there
7858 are guaranteed to be no I/O operations between that membar and
7859 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7862 Describe the block's first I/O operation in *NEXT_IO. Describe
7863 an unknown operation if the block doesn't do any I/O. */
7866 frv_optimize_membar_local (basic_block bb
, struct frv_io
*next_io
,
7869 HARD_REG_SET used_regs
;
7870 rtx next_membar
, set
, insn
;
7873 /* NEXT_IO is the next I/O operation to be performed after the current
7874 instruction. It starts off as being an unknown operation. */
7875 memset (next_io
, 0, sizeof (*next_io
));
7877 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7878 next_is_end_p
= true;
7880 /* If the current instruction is a __builtin_read or __builtin_write,
7881 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7882 is null if the membar has already been deleted.
7884 Note that the initialization here should only be needed to
7885 suppress warnings. */
7888 /* USED_REGS is the set of registers that are used before the
7889 next I/O instruction. */
7890 CLEAR_HARD_REG_SET (used_regs
);
7892 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
); insn
= PREV_INSN (insn
))
7893 if (GET_CODE (insn
) == CALL_INSN
)
7895 /* We can't predict what a call will do to volatile memory. */
7896 memset (next_io
, 0, sizeof (struct frv_io
));
7897 next_is_end_p
= false;
7898 CLEAR_HARD_REG_SET (used_regs
);
7900 else if (INSN_P (insn
))
7901 switch (recog_memoized (insn
))
7903 case CODE_FOR_optional_membar_qi
:
7904 case CODE_FOR_optional_membar_hi
:
7905 case CODE_FOR_optional_membar_si
:
7906 case CODE_FOR_optional_membar_di
:
7910 /* Local information isn't enough to decide whether this
7911 membar is needed. Stash it away for later. */
7912 *last_membar
= insn
;
7913 frv_extract_membar (next_io
, insn
);
7914 next_is_end_p
= false;
7918 /* Check whether the I/O operation before INSN could be
7919 reordered with one described by NEXT_IO. If it can't,
7920 INSN will not be needed. */
7921 struct frv_io prev_io
;
7923 frv_extract_membar (&prev_io
, insn
);
7924 if (frv_io_fixed_order_p (&prev_io
, next_io
))
7928 ";; [Local] Removing membar %d since order"
7929 " of accesses is guaranteed\n",
7930 INSN_UID (next_membar
));
7932 insn
= NEXT_INSN (insn
);
7933 delete_insn (next_membar
);
7941 /* Invalidate NEXT_IO's address if it depends on something that
7942 is clobbered by INSN. */
7943 if (next_io
->var_address
)
7944 note_stores (PATTERN (insn
), frv_io_check_address
,
7945 &next_io
->var_address
);
7947 /* If the next membar is associated with a __builtin_read,
7948 see if INSN reads from that address. If it does, and if
7949 the destination register is used before the next I/O access,
7950 there is no need for the membar. */
7951 set
= PATTERN (insn
);
7952 if (next_io
->type
== FRV_IO_READ
7953 && next_io
->var_address
!= 0
7955 && GET_CODE (set
) == SET
7956 && GET_CODE (SET_DEST (set
)) == REG
7957 && TEST_HARD_REG_BIT (used_regs
, REGNO (SET_DEST (set
))))
7961 src
= SET_SRC (set
);
7962 if (GET_CODE (src
) == ZERO_EXTEND
)
7963 src
= XEXP (src
, 0);
7965 if (GET_CODE (src
) == MEM
7966 && rtx_equal_p (XEXP (src
, 0), next_io
->var_address
))
7970 ";; [Local] Removing membar %d since the target"
7971 " of %d is used before the I/O operation\n",
7972 INSN_UID (next_membar
), INSN_UID (insn
));
7974 if (next_membar
== *last_membar
)
7977 delete_insn (next_membar
);
7982 /* If INSN has volatile references, forget about any registers
7983 that are used after it. Otherwise forget about uses that
7984 are (or might be) defined by INSN. */
7985 if (volatile_refs_p (PATTERN (insn
)))
7986 CLEAR_HARD_REG_SET (used_regs
);
7988 note_stores (PATTERN (insn
), frv_io_handle_set
, &used_regs
);
7990 note_uses (&PATTERN (insn
), frv_io_handle_use
, &used_regs
);
7995 /* See if MEMBAR, the last membar instruction in BB, can be removed.
7996 FIRST_IO[X] describes the first operation performed by basic block X. */
7999 frv_optimize_membar_global (basic_block bb
, struct frv_io
*first_io
,
8002 struct frv_io this_io
, next_io
;
8006 /* We need to keep the membar if there is an edge to the exit block. */
8007 FOR_EACH_EDGE (succ
, ei
, bb
->succs
)
8008 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8009 if (succ
->dest
== EXIT_BLOCK_PTR
)
8012 /* Work out the union of all successor blocks. */
8013 ei
= ei_start (bb
->succs
);
8014 ei_cond (ei
, &succ
);
8015 /* next_io = first_io[bb->succ->dest->index]; */
8016 next_io
= first_io
[succ
->dest
->index
];
8017 ei
= ei_start (bb
->succs
);
8018 if (ei_cond (ei
, &succ
))
8020 for (ei_next (&ei
); ei_cond (ei
, &succ
); ei_next (&ei
))
8021 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8022 frv_io_union (&next_io
, &first_io
[succ
->dest
->index
]);
8027 frv_extract_membar (&this_io
, membar
);
8028 if (frv_io_fixed_order_p (&this_io
, &next_io
))
8032 ";; [Global] Removing membar %d since order of accesses"
8033 " is guaranteed\n", INSN_UID (membar
));
8035 delete_insn (membar
);
8039 /* Remove redundant membars from the current function. */
8042 frv_optimize_membar (void)
8045 struct frv_io
*first_io
;
8048 compute_bb_for_insn ();
8049 first_io
= XCNEWVEC (struct frv_io
, last_basic_block
);
8050 last_membar
= XCNEWVEC (rtx
, last_basic_block
);
8053 frv_optimize_membar_local (bb
, &first_io
[bb
->index
],
8054 &last_membar
[bb
->index
]);
8057 if (last_membar
[bb
->index
] != 0)
8058 frv_optimize_membar_global (bb
, first_io
, last_membar
[bb
->index
]);
8064 /* Used by frv_reorg to keep track of the current packet's address. */
8065 static unsigned int frv_packet_address
;
8067 /* If the current packet falls through to a label, try to pad the packet
8068 with nops in order to fit the label's alignment requirements. */
8071 frv_align_label (void)
8073 unsigned int alignment
, target
, nop
;
8074 rtx x
, last
, barrier
, label
;
8076 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8077 maximum alignment of that packet, LABEL to the last label between
8078 the packets, and BARRIER to the last barrier. */
8079 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8080 label
= barrier
= 0;
8082 for (x
= NEXT_INSN (last
); x
!= 0 && !INSN_P (x
); x
= NEXT_INSN (x
))
8086 unsigned int subalign
= 1 << label_to_alignment (x
);
8087 alignment
= MAX (alignment
, subalign
);
8094 /* If -malign-labels, and the packet falls through to an unaligned
8095 label, try introducing a nop to align that label to 8 bytes. */
8096 if (TARGET_ALIGN_LABELS
8099 && frv_packet
.num_insns
< frv_packet
.issue_rate
)
8100 alignment
= MAX (alignment
, 8);
8102 /* Advance the address to the end of the current packet. */
8103 frv_packet_address
+= frv_packet
.num_insns
* 4;
8105 /* Work out the target address, after alignment. */
8106 target
= (frv_packet_address
+ alignment
- 1) & -alignment
;
8108 /* If the packet falls through to the label, try to find an efficient
8109 padding sequence. */
8112 /* First try adding nops to the current packet. */
8113 for (nop
= 0; nop
< frv_num_nops
; nop
++)
8114 while (frv_packet_address
< target
&& frv_pack_insn_p (frv_nops
[nop
]))
8116 frv_insert_nop_in_packet (frv_nops
[nop
]);
8117 frv_packet_address
+= 4;
8120 /* If we still haven't reached the target, add some new packets that
8121 contain only nops. If there are two types of nop, insert an
8122 alternating sequence of frv_nops[0] and frv_nops[1], which will
8123 lead to packets like:
8130 etc. Just emit frv_nops[0] if that's the only nop we have. */
8131 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8133 while (frv_packet_address
< target
)
8135 last
= emit_insn_after (PATTERN (frv_nops
[nop
]), last
);
8136 frv_packet_address
+= 4;
8137 if (frv_num_nops
> 1)
8142 frv_packet_address
= target
;
8145 /* Subroutine of frv_reorg, called after each packet has been constructed
8149 frv_reorg_packet (void)
8151 frv_fill_unused_units (GROUP_I
);
8152 frv_fill_unused_units (GROUP_FM
);
8156 /* Add an instruction with pattern NOP to frv_nops[]. */
8159 frv_register_nop (rtx nop
)
8161 nop
= make_insn_raw (nop
);
8162 NEXT_INSN (nop
) = 0;
8163 PREV_INSN (nop
) = 0;
8164 frv_nops
[frv_num_nops
++] = nop
;
8167 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8168 into packets and check whether we need to insert nops in order to
8169 fulfill the processor's issue requirements. Also, if the user has
8170 requested a certain alignment for a label, try to meet that alignment
8171 by inserting nops in the previous packet. */
8176 if (optimize
> 0 && TARGET_OPTIMIZE_MEMBAR
&& cfun
->machine
->has_membar_p
)
8177 frv_optimize_membar ();
8180 frv_register_nop (gen_nop ());
8182 frv_register_nop (gen_mnop ());
8183 if (TARGET_HARD_FLOAT
)
8184 frv_register_nop (gen_fnop ());
8186 /* Estimate the length of each branch. Although this may change after
8187 we've inserted nops, it will only do so in big functions. */
8188 shorten_branches (get_insns ());
8190 frv_packet_address
= 0;
8191 frv_for_each_packet (frv_reorg_packet
);
8194 #define def_builtin(name, type, code) \
8195 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8197 struct builtin_description
8199 enum insn_code icode
;
8201 enum frv_builtins code
;
8202 enum rtx_code comparison
;
8206 /* Media intrinsics that take a single, constant argument. */
8208 static struct builtin_description bdesc_set
[] =
8210 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, UNKNOWN
, 0 }
8213 /* Media intrinsics that take just one argument. */
8215 static struct builtin_description bdesc_1arg
[] =
8217 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, UNKNOWN
, 0 },
8218 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, UNKNOWN
, 0 },
8219 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, UNKNOWN
, 0 },
8220 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, UNKNOWN
, 0},
8221 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, UNKNOWN
, 0 },
8222 { CODE_FOR_scutss
, "__SCUTSS", FRV_BUILTIN_SCUTSS
, UNKNOWN
, 0 }
8225 /* Media intrinsics that take two arguments. */
8227 static struct builtin_description bdesc_2arg
[] =
8229 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, UNKNOWN
, 0},
8230 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, UNKNOWN
, 0},
8231 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, UNKNOWN
, 0},
8232 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, UNKNOWN
, 0},
8233 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, UNKNOWN
, 0},
8234 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, UNKNOWN
, 0},
8235 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, UNKNOWN
, 0},
8236 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, UNKNOWN
, 0},
8237 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, UNKNOWN
, 0},
8238 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, UNKNOWN
, 0},
8239 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, UNKNOWN
, 0},
8240 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, UNKNOWN
, 0},
8241 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, UNKNOWN
, 0},
8242 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, UNKNOWN
, 0},
8243 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, UNKNOWN
, 0},
8244 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, UNKNOWN
, 0},
8245 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, UNKNOWN
, 0},
8246 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, UNKNOWN
, 0},
8247 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, UNKNOWN
, 0},
8248 { CODE_FOR_mqlclrhs
, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS
, UNKNOWN
, 0},
8249 { CODE_FOR_mqlmths
, "__MQLMTHS", FRV_BUILTIN_MQLMTHS
, UNKNOWN
, 0},
8250 { CODE_FOR_smul
, "__SMUL", FRV_BUILTIN_SMUL
, UNKNOWN
, 0},
8251 { CODE_FOR_umul
, "__UMUL", FRV_BUILTIN_UMUL
, UNKNOWN
, 0},
8252 { CODE_FOR_addss
, "__ADDSS", FRV_BUILTIN_ADDSS
, UNKNOWN
, 0},
8253 { CODE_FOR_subss
, "__SUBSS", FRV_BUILTIN_SUBSS
, UNKNOWN
, 0},
8254 { CODE_FOR_slass
, "__SLASS", FRV_BUILTIN_SLASS
, UNKNOWN
, 0},
8255 { CODE_FOR_scan
, "__SCAN", FRV_BUILTIN_SCAN
, UNKNOWN
, 0}
8258 /* Integer intrinsics that take two arguments and have no return value. */
8260 static struct builtin_description bdesc_int_void2arg
[] =
8262 { CODE_FOR_smass
, "__SMASS", FRV_BUILTIN_SMASS
, UNKNOWN
, 0},
8263 { CODE_FOR_smsss
, "__SMSSS", FRV_BUILTIN_SMSSS
, UNKNOWN
, 0},
8264 { CODE_FOR_smu
, "__SMU", FRV_BUILTIN_SMU
, UNKNOWN
, 0}
8267 static struct builtin_description bdesc_prefetches
[] =
8269 { CODE_FOR_frv_prefetch0
, "__data_prefetch0", FRV_BUILTIN_PREFETCH0
, UNKNOWN
,
8271 { CODE_FOR_frv_prefetch
, "__data_prefetch", FRV_BUILTIN_PREFETCH
, UNKNOWN
, 0}
8274 /* Media intrinsics that take two arguments, the first being an ACC number. */
8276 static struct builtin_description bdesc_cut
[] =
8278 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, UNKNOWN
, 0},
8279 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, UNKNOWN
, 0},
8280 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, UNKNOWN
, 0}
8283 /* Two-argument media intrinsics with an immediate second argument. */
8285 static struct builtin_description bdesc_2argimm
[] =
8287 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, UNKNOWN
, 0},
8288 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, UNKNOWN
, 0},
8289 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, UNKNOWN
, 0},
8290 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, UNKNOWN
, 0},
8291 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, UNKNOWN
, 0},
8292 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, UNKNOWN
, 0},
8293 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, UNKNOWN
, 0},
8294 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, UNKNOWN
, 0},
8295 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, UNKNOWN
, 0},
8296 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, UNKNOWN
, 0},
8297 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, UNKNOWN
, 0},
8298 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, UNKNOWN
, 0},
8299 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, UNKNOWN
, 0},
8300 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, UNKNOWN
, 0},
8301 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, UNKNOWN
, 0},
8302 { CODE_FOR_mqsllhi
, "__MQSLLHI", FRV_BUILTIN_MQSLLHI
, UNKNOWN
, 0},
8303 { CODE_FOR_mqsrahi
, "__MQSRAHI", FRV_BUILTIN_MQSRAHI
, UNKNOWN
, 0}
8306 /* Media intrinsics that take two arguments and return void, the first argument
8307 being a pointer to 4 words in memory. */
8309 static struct builtin_description bdesc_void2arg
[] =
8311 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, UNKNOWN
, 0},
8312 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, UNKNOWN
, 0},
8315 /* Media intrinsics that take three arguments, the first being a const_int that
8316 denotes an accumulator, and that return void. */
8318 static struct builtin_description bdesc_void3arg
[] =
8320 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, UNKNOWN
, 0},
8321 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, UNKNOWN
, 0},
8322 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, UNKNOWN
, 0},
8323 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, UNKNOWN
, 0},
8324 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, UNKNOWN
, 0},
8325 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, UNKNOWN
, 0},
8326 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, UNKNOWN
, 0},
8327 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, UNKNOWN
, 0},
8328 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, UNKNOWN
, 0},
8329 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, UNKNOWN
, 0},
8330 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, UNKNOWN
, 0},
8331 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, UNKNOWN
, 0},
8332 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, UNKNOWN
, 0},
8333 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, UNKNOWN
, 0},
8334 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, UNKNOWN
, 0},
8335 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, UNKNOWN
, 0},
8336 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, UNKNOWN
, 0},
8337 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, UNKNOWN
, 0},
8338 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, UNKNOWN
, 0},
8339 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, UNKNOWN
, 0},
8340 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, UNKNOWN
, 0},
8341 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, UNKNOWN
, 0},
8342 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, UNKNOWN
, 0},
8343 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, UNKNOWN
, 0},
8344 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, UNKNOWN
, 0}
8347 /* Media intrinsics that take two accumulator numbers as argument and
8350 static struct builtin_description bdesc_voidacc
[] =
8352 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, UNKNOWN
, 0},
8353 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, UNKNOWN
, 0},
8354 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, UNKNOWN
, 0},
8355 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, UNKNOWN
, 0},
8356 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, UNKNOWN
, 0},
8357 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, UNKNOWN
, 0}
8360 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8361 a normal move and the ICODE is for the membar. */
8363 static struct builtin_description bdesc_loads
[] =
8365 { CODE_FOR_optional_membar_qi
, "__builtin_read8",
8366 FRV_BUILTIN_READ8
, UNKNOWN
, 0},
8367 { CODE_FOR_optional_membar_hi
, "__builtin_read16",
8368 FRV_BUILTIN_READ16
, UNKNOWN
, 0},
8369 { CODE_FOR_optional_membar_si
, "__builtin_read32",
8370 FRV_BUILTIN_READ32
, UNKNOWN
, 0},
8371 { CODE_FOR_optional_membar_di
, "__builtin_read64",
8372 FRV_BUILTIN_READ64
, UNKNOWN
, 0}
8375 /* Likewise stores. */
8377 static struct builtin_description bdesc_stores
[] =
8379 { CODE_FOR_optional_membar_qi
, "__builtin_write8",
8380 FRV_BUILTIN_WRITE8
, UNKNOWN
, 0},
8381 { CODE_FOR_optional_membar_hi
, "__builtin_write16",
8382 FRV_BUILTIN_WRITE16
, UNKNOWN
, 0},
8383 { CODE_FOR_optional_membar_si
, "__builtin_write32",
8384 FRV_BUILTIN_WRITE32
, UNKNOWN
, 0},
8385 { CODE_FOR_optional_membar_di
, "__builtin_write64",
8386 FRV_BUILTIN_WRITE64
, UNKNOWN
, 0},
8389 /* Initialize media builtins. */
8392 frv_init_builtins (void)
8394 tree endlink
= void_list_node
;
8395 tree accumulator
= integer_type_node
;
8396 tree integer
= integer_type_node
;
8397 tree voidt
= void_type_node
;
8398 tree uhalf
= short_unsigned_type_node
;
8399 tree sword1
= long_integer_type_node
;
8400 tree uword1
= long_unsigned_type_node
;
8401 tree sword2
= long_long_integer_type_node
;
8402 tree uword2
= long_long_unsigned_type_node
;
8403 tree uword4
= build_pointer_type (uword1
);
8404 tree vptr
= build_pointer_type (build_type_variant (void_type_node
, 0, 1));
8405 tree ubyte
= unsigned_char_type_node
;
8406 tree iacc
= integer_type_node
;
8408 #define UNARY(RET, T1) \
8409 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8411 #define BINARY(RET, T1, T2) \
8412 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8413 tree_cons (NULL_TREE, T2, endlink)))
8415 #define TRINARY(RET, T1, T2, T3) \
8416 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8417 tree_cons (NULL_TREE, T2, \
8418 tree_cons (NULL_TREE, T3, endlink))))
8420 #define QUAD(RET, T1, T2, T3, T4) \
8421 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8422 tree_cons (NULL_TREE, T2, \
8423 tree_cons (NULL_TREE, T3, \
8424 tree_cons (NULL_TREE, T4, endlink)))))
8426 tree void_ftype_void
= build_function_type (voidt
, endlink
);
8428 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
8429 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
8430 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
8431 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
8432 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
8433 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
8434 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
8435 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
8436 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
8438 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
8439 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
8440 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
8441 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
8442 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
8443 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
8444 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
8445 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
8446 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
8447 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
8448 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
8450 tree sw1_ftype_int
= UNARY (sword1
, integer
);
8451 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
8452 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
8454 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
8455 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
8456 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
8457 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
8458 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
8459 tree uw2_ftype_uh_uh_uh_uh
= QUAD (uword2
, uhalf
, uhalf
, uhalf
, uhalf
);
8461 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
8462 tree sw2_ftype_sw2_int
= BINARY (sword2
, sword2
, integer
);
8463 tree uw2_ftype_uw1_uw1
= BINARY (uword2
, uword1
, uword1
);
8464 tree sw2_ftype_sw1_sw1
= BINARY (sword2
, sword1
, sword1
);
8465 tree void_ftype_sw1_sw1
= BINARY (voidt
, sword1
, sword1
);
8466 tree void_ftype_iacc_sw2
= BINARY (voidt
, iacc
, sword2
);
8467 tree void_ftype_iacc_sw1
= BINARY (voidt
, iacc
, sword1
);
8468 tree sw1_ftype_sw1
= UNARY (sword1
, sword1
);
8469 tree sw2_ftype_iacc
= UNARY (sword2
, iacc
);
8470 tree sw1_ftype_iacc
= UNARY (sword1
, iacc
);
8471 tree void_ftype_ptr
= UNARY (voidt
, const_ptr_type_node
);
8472 tree uw1_ftype_vptr
= UNARY (uword1
, vptr
);
8473 tree uw2_ftype_vptr
= UNARY (uword2
, vptr
);
8474 tree void_ftype_vptr_ub
= BINARY (voidt
, vptr
, ubyte
);
8475 tree void_ftype_vptr_uh
= BINARY (voidt
, vptr
, uhalf
);
8476 tree void_ftype_vptr_uw1
= BINARY (voidt
, vptr
, uword1
);
8477 tree void_ftype_vptr_uw2
= BINARY (voidt
, vptr
, uword2
);
8479 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
8480 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
8481 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
8482 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
8483 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
8484 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
8485 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
8486 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
8487 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
8488 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
8489 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
8490 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
8491 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
8492 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
8493 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
8494 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
8495 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
8496 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
8497 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
8498 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
8499 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
8500 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
8501 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
8502 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
8503 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
8504 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
8505 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
8506 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
8507 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
8508 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
8509 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
8510 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
8511 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
8512 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
8513 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
8514 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
8515 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
8516 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
8517 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
8518 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
8519 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
8520 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
8521 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
8522 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
8523 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
8524 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
8525 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
8526 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
8527 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
8528 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh
, FRV_BUILTIN_MDPACKH
);
8529 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
8530 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
8531 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
8532 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
8533 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
8534 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
8535 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
8536 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
8537 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
8538 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
8539 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
8540 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
8541 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
8542 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
8543 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
8544 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
8545 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
8546 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
8547 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
8548 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
8549 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
8550 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
8551 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
8552 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
8553 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
8554 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
8555 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
8556 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
8557 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
8558 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
8559 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
8560 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
8561 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
8562 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
8563 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLCLRHS
);
8564 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLMTHS
);
8565 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int
, FRV_BUILTIN_MQSLLHI
);
8566 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int
, FRV_BUILTIN_MQSRAHI
);
8567 def_builtin ("__SMUL", sw2_ftype_sw1_sw1
, FRV_BUILTIN_SMUL
);
8568 def_builtin ("__UMUL", uw2_ftype_uw1_uw1
, FRV_BUILTIN_UMUL
);
8569 def_builtin ("__SMASS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMASS
);
8570 def_builtin ("__SMSSS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMSSS
);
8571 def_builtin ("__SMU", void_ftype_sw1_sw1
, FRV_BUILTIN_SMU
);
8572 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_ADDSS
);
8573 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SUBSS
);
8574 def_builtin ("__SLASS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SLASS
);
8575 def_builtin ("__SCAN", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SCAN
);
8576 def_builtin ("__SCUTSS", sw1_ftype_sw1
, FRV_BUILTIN_SCUTSS
);
8577 def_builtin ("__IACCreadll", sw2_ftype_iacc
, FRV_BUILTIN_IACCreadll
);
8578 def_builtin ("__IACCreadl", sw1_ftype_iacc
, FRV_BUILTIN_IACCreadl
);
8579 def_builtin ("__IACCsetll", void_ftype_iacc_sw2
, FRV_BUILTIN_IACCsetll
);
8580 def_builtin ("__IACCsetl", void_ftype_iacc_sw1
, FRV_BUILTIN_IACCsetl
);
8581 def_builtin ("__data_prefetch0", void_ftype_ptr
, FRV_BUILTIN_PREFETCH0
);
8582 def_builtin ("__data_prefetch", void_ftype_ptr
, FRV_BUILTIN_PREFETCH
);
8583 def_builtin ("__builtin_read8", uw1_ftype_vptr
, FRV_BUILTIN_READ8
);
8584 def_builtin ("__builtin_read16", uw1_ftype_vptr
, FRV_BUILTIN_READ16
);
8585 def_builtin ("__builtin_read32", uw1_ftype_vptr
, FRV_BUILTIN_READ32
);
8586 def_builtin ("__builtin_read64", uw2_ftype_vptr
, FRV_BUILTIN_READ64
);
8588 def_builtin ("__builtin_write8", void_ftype_vptr_ub
, FRV_BUILTIN_WRITE8
);
8589 def_builtin ("__builtin_write16", void_ftype_vptr_uh
, FRV_BUILTIN_WRITE16
);
8590 def_builtin ("__builtin_write32", void_ftype_vptr_uw1
, FRV_BUILTIN_WRITE32
);
8591 def_builtin ("__builtin_write64", void_ftype_vptr_uw2
, FRV_BUILTIN_WRITE64
);
8599 /* Set the names for various arithmetic operations according to the
8602 frv_init_libfuncs (void)
8604 set_optab_libfunc (smod_optab
, SImode
, "__modi");
8605 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
8607 set_optab_libfunc (add_optab
, DImode
, "__addll");
8608 set_optab_libfunc (sub_optab
, DImode
, "__subll");
8609 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
8610 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
8611 set_optab_libfunc (smod_optab
, DImode
, "__modll");
8612 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
8613 set_optab_libfunc (and_optab
, DImode
, "__andll");
8614 set_optab_libfunc (ior_optab
, DImode
, "__orll");
8615 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
8616 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
8618 set_optab_libfunc (add_optab
, SFmode
, "__addf");
8619 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
8620 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
8621 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
8623 set_optab_libfunc (add_optab
, DFmode
, "__addd");
8624 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
8625 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
8626 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
8628 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
8629 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
8631 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
8632 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8633 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
8634 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8636 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
8637 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8638 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
8639 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8641 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
8642 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
8643 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
8644 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
8647 /* Convert an integer constant to an accumulator register. ICODE is the
8648 code of the target instruction, OPNUM is the number of the
8649 accumulator operand and OPVAL is the constant integer. Try both
8650 ACC and ACCG registers; only report an error if neither fit the
8654 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
8659 /* ACCs and ACCGs are implicit global registers if media intrinsics
8660 are being used. We set up this lazily to avoid creating lots of
8661 unnecessary call_insn rtl in non-media code. */
8662 for (i
= 0; i
<= ACC_MASK
; i
++)
8663 if ((i
& ACC_MASK
) == i
)
8664 global_regs
[i
+ ACC_FIRST
] = global_regs
[i
+ ACCG_FIRST
] = 1;
8666 if (GET_CODE (opval
) != CONST_INT
)
8668 error ("accumulator is not a constant integer");
8671 if ((INTVAL (opval
) & ~ACC_MASK
) != 0)
8673 error ("accumulator number is out of bounds");
8677 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
8678 ACC_FIRST
+ INTVAL (opval
));
8679 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8680 SET_REGNO (reg
, ACCG_FIRST
+ INTVAL (opval
));
8682 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8684 error ("inappropriate accumulator for %qs", insn_data
[icode
].name
);
8690 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8693 static enum machine_mode
8694 frv_matching_accg_mode (enum machine_mode mode
)
8712 /* Given that a __builtin_read or __builtin_write function is accessing
8713 address ADDRESS, return the value that should be used as operand 1
8717 frv_io_address_cookie (rtx address
)
8719 return (GET_CODE (address
) == CONST_INT
8720 ? GEN_INT (INTVAL (address
) / 8 * 8)
8724 /* Return the accumulator guard that should be paired with accumulator
8725 register ACC. The mode of the returned register is in the same
8726 class as ACC, but is four times smaller. */
8729 frv_matching_accg_for_acc (rtx acc
)
8731 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
8732 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
8735 /* Read the requested argument from the call EXP given by INDEX.
8736 Return the value as an rtx. */
8739 frv_read_argument (tree exp
, unsigned int index
)
8741 return expand_normal (CALL_EXPR_ARG (exp
, index
));
8744 /* Like frv_read_argument, but interpret the argument as the number
8745 of an IACC register and return a (reg:MODE ...) rtx for it. */
8748 frv_read_iacc_argument (enum machine_mode mode
, tree call
,
8754 op
= frv_read_argument (call
, index
);
8755 if (GET_CODE (op
) != CONST_INT
8757 || INTVAL (op
) > IACC_LAST
- IACC_FIRST
8758 || ((INTVAL (op
) * 4) & (GET_MODE_SIZE (mode
) - 1)) != 0)
8760 error ("invalid IACC argument");
8764 /* IACCs are implicit global registers. We set up this lazily to
8765 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8767 regno
= INTVAL (op
) + IACC_FIRST
;
8768 for (i
= 0; i
< HARD_REGNO_NREGS (regno
, mode
); i
++)
8769 global_regs
[regno
+ i
] = 1;
8771 return gen_rtx_REG (mode
, regno
);
8774 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8775 The instruction should require a constant operand of some sort. The
8776 function prints an error if OPVAL is not valid. */
8779 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
8781 if (GET_CODE (opval
) != CONST_INT
)
8783 error ("%qs expects a constant argument", insn_data
[icode
].name
);
8786 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
8788 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
8794 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8795 if it's not null, has the right mode, and satisfies operand 0's
8799 frv_legitimize_target (enum insn_code icode
, rtx target
)
8801 enum machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
8804 || GET_MODE (target
) != mode
8805 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
8806 return gen_reg_rtx (mode
);
8811 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8812 check whether ARG satisfies the operand's constraints. If it doesn't,
8813 copy ARG to a temporary register and return that. Otherwise return ARG
8817 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
8819 enum machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
8821 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
8824 return copy_to_mode_reg (mode
, arg
);
8827 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8830 frv_volatile_memref (enum machine_mode mode
, rtx arg
)
8834 mem
= gen_rtx_MEM (mode
, memory_address (mode
, arg
));
8835 MEM_VOLATILE_P (mem
) = 1;
8839 /* Expand builtins that take a single, constant argument. At the moment,
8840 only MHDSETS falls into this category. */
8843 frv_expand_set_builtin (enum insn_code icode
, tree call
, rtx target
)
8846 rtx op0
= frv_read_argument (call
, 0);
8848 if (! frv_check_constant_argument (icode
, 1, op0
))
8851 target
= frv_legitimize_target (icode
, target
);
8852 pat
= GEN_FCN (icode
) (target
, op0
);
8860 /* Expand builtins that take one operand. */
8863 frv_expand_unop_builtin (enum insn_code icode
, tree call
, rtx target
)
8866 rtx op0
= frv_read_argument (call
, 0);
8868 target
= frv_legitimize_target (icode
, target
);
8869 op0
= frv_legitimize_argument (icode
, 1, op0
);
8870 pat
= GEN_FCN (icode
) (target
, op0
);
8878 /* Expand builtins that take two operands. */
8881 frv_expand_binop_builtin (enum insn_code icode
, tree call
, rtx target
)
8884 rtx op0
= frv_read_argument (call
, 0);
8885 rtx op1
= frv_read_argument (call
, 1);
8887 target
= frv_legitimize_target (icode
, target
);
8888 op0
= frv_legitimize_argument (icode
, 1, op0
);
8889 op1
= frv_legitimize_argument (icode
, 2, op1
);
8890 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8898 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8902 frv_expand_cut_builtin (enum insn_code icode
, tree call
, rtx target
)
8905 rtx op0
= frv_read_argument (call
, 0);
8906 rtx op1
= frv_read_argument (call
, 1);
8909 target
= frv_legitimize_target (icode
, target
);
8910 op0
= frv_int_to_acc (icode
, 1, op0
);
8914 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
8916 if (! frv_check_constant_argument (icode
, 2, op1
))
8920 op1
= frv_legitimize_argument (icode
, 2, op1
);
8922 op2
= frv_matching_accg_for_acc (op0
);
8923 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8931 /* Expand builtins that take two operands and the second is immediate. */
8934 frv_expand_binopimm_builtin (enum insn_code icode
, tree call
, rtx target
)
8937 rtx op0
= frv_read_argument (call
, 0);
8938 rtx op1
= frv_read_argument (call
, 1);
8940 if (! frv_check_constant_argument (icode
, 2, op1
))
8943 target
= frv_legitimize_target (icode
, target
);
8944 op0
= frv_legitimize_argument (icode
, 1, op0
);
8945 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8953 /* Expand builtins that take two operands, the first operand being a pointer to
8954 ints and return void. */
8957 frv_expand_voidbinop_builtin (enum insn_code icode
, tree call
)
8960 rtx op0
= frv_read_argument (call
, 0);
8961 rtx op1
= frv_read_argument (call
, 1);
8962 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8965 if (GET_CODE (op0
) != MEM
)
8969 if (! offsettable_address_p (0, mode0
, op0
))
8971 reg
= gen_reg_rtx (Pmode
);
8972 emit_insn (gen_rtx_SET (VOIDmode
, reg
, op0
));
8975 op0
= gen_rtx_MEM (SImode
, reg
);
8978 addr
= XEXP (op0
, 0);
8979 if (! offsettable_address_p (0, mode0
, addr
))
8980 addr
= copy_to_mode_reg (Pmode
, op0
);
8982 op0
= change_address (op0
, V4SImode
, addr
);
8983 op1
= frv_legitimize_argument (icode
, 1, op1
);
8984 pat
= GEN_FCN (icode
) (op0
, op1
);
8992 /* Expand builtins that take two long operands and return void. */
8995 frv_expand_int_void2arg (enum insn_code icode
, tree call
)
8998 rtx op0
= frv_read_argument (call
, 0);
8999 rtx op1
= frv_read_argument (call
, 1);
9001 op0
= frv_legitimize_argument (icode
, 1, op0
);
9002 op1
= frv_legitimize_argument (icode
, 1, op1
);
9003 pat
= GEN_FCN (icode
) (op0
, op1
);
9011 /* Expand prefetch builtins. These take a single address as argument. */
9014 frv_expand_prefetches (enum insn_code icode
, tree call
)
9017 rtx op0
= frv_read_argument (call
, 0);
9019 pat
= GEN_FCN (icode
) (force_reg (Pmode
, op0
));
9027 /* Expand builtins that take three operands and return void. The first
9028 argument must be a constant that describes a pair or quad accumulators. A
9029 fourth argument is created that is the accumulator guard register that
9030 corresponds to the accumulator. */
9033 frv_expand_voidtriop_builtin (enum insn_code icode
, tree call
)
9036 rtx op0
= frv_read_argument (call
, 0);
9037 rtx op1
= frv_read_argument (call
, 1);
9038 rtx op2
= frv_read_argument (call
, 2);
9041 op0
= frv_int_to_acc (icode
, 0, op0
);
9045 op1
= frv_legitimize_argument (icode
, 1, op1
);
9046 op2
= frv_legitimize_argument (icode
, 2, op2
);
9047 op3
= frv_matching_accg_for_acc (op0
);
9048 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9056 /* Expand builtins that perform accumulator-to-accumulator operations.
9057 These builtins take two accumulator numbers as argument and return
9061 frv_expand_voidaccop_builtin (enum insn_code icode
, tree call
)
9064 rtx op0
= frv_read_argument (call
, 0);
9065 rtx op1
= frv_read_argument (call
, 1);
9069 op0
= frv_int_to_acc (icode
, 0, op0
);
9073 op1
= frv_int_to_acc (icode
, 1, op1
);
9077 op2
= frv_matching_accg_for_acc (op0
);
9078 op3
= frv_matching_accg_for_acc (op1
);
9079 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9087 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9088 membar and TARGET_MODE is the mode that the loaded value should have. */
9091 frv_expand_load_builtin (enum insn_code icode
, enum machine_mode target_mode
,
9092 tree call
, rtx target
)
9094 rtx op0
= frv_read_argument (call
, 0);
9095 rtx cookie
= frv_io_address_cookie (op0
);
9097 if (target
== 0 || !REG_P (target
))
9098 target
= gen_reg_rtx (target_mode
);
9099 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9100 convert_move (target
, op0
, 1);
9101 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_READ
)));
9102 cfun
->machine
->has_membar_p
= 1;
9106 /* Likewise __builtin_write* functions. */
9109 frv_expand_store_builtin (enum insn_code icode
, tree call
)
9111 rtx op0
= frv_read_argument (call
, 0);
9112 rtx op1
= frv_read_argument (call
, 1);
9113 rtx cookie
= frv_io_address_cookie (op0
);
9115 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9116 convert_move (op0
, force_reg (insn_data
[icode
].operand
[0].mode
, op1
), 1);
9117 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_WRITE
)));
9118 cfun
->machine
->has_membar_p
= 1;
9122 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9123 each argument forms one word of the two double-word input registers.
9124 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9125 to put the return value. */
9128 frv_expand_mdpackh_builtin (tree call
, rtx target
)
9130 enum insn_code icode
= CODE_FOR_mdpackh
;
9132 rtx arg1
= frv_read_argument (call
, 0);
9133 rtx arg2
= frv_read_argument (call
, 1);
9134 rtx arg3
= frv_read_argument (call
, 2);
9135 rtx arg4
= frv_read_argument (call
, 3);
9137 target
= frv_legitimize_target (icode
, target
);
9138 op0
= gen_reg_rtx (DImode
);
9139 op1
= gen_reg_rtx (DImode
);
9141 /* The high half of each word is not explicitly initialized, so indicate
9142 that the input operands are not live before this point. */
9146 /* Move each argument into the low half of its associated input word. */
9147 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 2), arg1
);
9148 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 6), arg2
);
9149 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 2), arg3
);
9150 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 6), arg4
);
9152 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9160 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9161 number as argument. */
9164 frv_expand_mclracc_builtin (tree call
)
9166 enum insn_code icode
= CODE_FOR_mclracc
;
9168 rtx op0
= frv_read_argument (call
, 0);
9170 op0
= frv_int_to_acc (icode
, 0, op0
);
9174 pat
= GEN_FCN (icode
) (op0
);
9181 /* Expand builtins that take no arguments. */
9184 frv_expand_noargs_builtin (enum insn_code icode
)
9186 rtx pat
= GEN_FCN (icode
) (const0_rtx
);
9193 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9194 number or accumulator guard number as argument and return an SI integer. */
9197 frv_expand_mrdacc_builtin (enum insn_code icode
, tree call
)
9200 rtx target
= gen_reg_rtx (SImode
);
9201 rtx op0
= frv_read_argument (call
, 0);
9203 op0
= frv_int_to_acc (icode
, 1, op0
);
9207 pat
= GEN_FCN (icode
) (target
, op0
);
9215 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9216 accumulator guard as their first argument and an SImode value as their
9220 frv_expand_mwtacc_builtin (enum insn_code icode
, tree call
)
9223 rtx op0
= frv_read_argument (call
, 0);
9224 rtx op1
= frv_read_argument (call
, 1);
9226 op0
= frv_int_to_acc (icode
, 0, op0
);
9230 op1
= frv_legitimize_argument (icode
, 1, op1
);
9231 pat
= GEN_FCN (icode
) (op0
, op1
);
9238 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9239 to move DImode values into and out of IACC0. */
9242 frv_split_iacc_move (rtx dest
, rtx src
)
9244 enum machine_mode inner
;
9247 inner
= GET_MODE (dest
);
9248 for (i
= 0; i
< GET_MODE_SIZE (inner
); i
+= GET_MODE_SIZE (SImode
))
9249 emit_move_insn (simplify_gen_subreg (SImode
, dest
, inner
, i
),
9250 simplify_gen_subreg (SImode
, src
, inner
, i
));
9253 /* Expand builtins. */
9256 frv_expand_builtin (tree exp
,
9258 rtx subtarget ATTRIBUTE_UNUSED
,
9259 enum machine_mode mode ATTRIBUTE_UNUSED
,
9260 int ignore ATTRIBUTE_UNUSED
)
9262 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9263 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9265 struct builtin_description
*d
;
9267 if (fcode
< FRV_BUILTIN_FIRST_NONMEDIA
&& !TARGET_MEDIA
)
9269 error ("media functions are not available unless -mmedia is used");
9275 case FRV_BUILTIN_MCOP1
:
9276 case FRV_BUILTIN_MCOP2
:
9277 case FRV_BUILTIN_MDUNPACKH
:
9278 case FRV_BUILTIN_MBTOHE
:
9279 if (! TARGET_MEDIA_REV1
)
9281 error ("this media function is only available on the fr500");
9286 case FRV_BUILTIN_MQXMACHS
:
9287 case FRV_BUILTIN_MQXMACXHS
:
9288 case FRV_BUILTIN_MQMACXHS
:
9289 case FRV_BUILTIN_MADDACCS
:
9290 case FRV_BUILTIN_MSUBACCS
:
9291 case FRV_BUILTIN_MASACCS
:
9292 case FRV_BUILTIN_MDADDACCS
:
9293 case FRV_BUILTIN_MDSUBACCS
:
9294 case FRV_BUILTIN_MDASACCS
:
9295 case FRV_BUILTIN_MABSHS
:
9296 case FRV_BUILTIN_MDROTLI
:
9297 case FRV_BUILTIN_MCPLHI
:
9298 case FRV_BUILTIN_MCPLI
:
9299 case FRV_BUILTIN_MDCUTSSI
:
9300 case FRV_BUILTIN_MQSATHS
:
9301 case FRV_BUILTIN_MHSETLOS
:
9302 case FRV_BUILTIN_MHSETLOH
:
9303 case FRV_BUILTIN_MHSETHIS
:
9304 case FRV_BUILTIN_MHSETHIH
:
9305 case FRV_BUILTIN_MHDSETS
:
9306 case FRV_BUILTIN_MHDSETH
:
9307 if (! TARGET_MEDIA_REV2
)
9309 error ("this media function is only available on the fr400"
9315 case FRV_BUILTIN_SMASS
:
9316 case FRV_BUILTIN_SMSSS
:
9317 case FRV_BUILTIN_SMU
:
9318 case FRV_BUILTIN_ADDSS
:
9319 case FRV_BUILTIN_SUBSS
:
9320 case FRV_BUILTIN_SLASS
:
9321 case FRV_BUILTIN_SCUTSS
:
9322 case FRV_BUILTIN_IACCreadll
:
9323 case FRV_BUILTIN_IACCreadl
:
9324 case FRV_BUILTIN_IACCsetll
:
9325 case FRV_BUILTIN_IACCsetl
:
9326 if (!TARGET_FR405_BUILTINS
)
9328 error ("this builtin function is only available"
9329 " on the fr405 and fr450");
9334 case FRV_BUILTIN_PREFETCH
:
9335 if (!TARGET_FR500_FR550_BUILTINS
)
9337 error ("this builtin function is only available on the fr500"
9343 case FRV_BUILTIN_MQLCLRHS
:
9344 case FRV_BUILTIN_MQLMTHS
:
9345 case FRV_BUILTIN_MQSLLHI
:
9346 case FRV_BUILTIN_MQSRAHI
:
9347 if (!TARGET_MEDIA_FR450
)
9349 error ("this builtin function is only available on the fr450");
9358 /* Expand unique builtins. */
9362 case FRV_BUILTIN_MTRAP
:
9363 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9365 case FRV_BUILTIN_MCLRACC
:
9366 return frv_expand_mclracc_builtin (exp
);
9368 case FRV_BUILTIN_MCLRACCA
:
9370 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9372 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9374 case FRV_BUILTIN_MRDACC
:
9375 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, exp
);
9377 case FRV_BUILTIN_MRDACCG
:
9378 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, exp
);
9380 case FRV_BUILTIN_MWTACC
:
9381 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, exp
);
9383 case FRV_BUILTIN_MWTACCG
:
9384 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, exp
);
9386 case FRV_BUILTIN_MDPACKH
:
9387 return frv_expand_mdpackh_builtin (exp
, target
);
9389 case FRV_BUILTIN_IACCreadll
:
9391 rtx src
= frv_read_iacc_argument (DImode
, exp
, 0);
9392 if (target
== 0 || !REG_P (target
))
9393 target
= gen_reg_rtx (DImode
);
9394 frv_split_iacc_move (target
, src
);
9398 case FRV_BUILTIN_IACCreadl
:
9399 return frv_read_iacc_argument (SImode
, exp
, 0);
9401 case FRV_BUILTIN_IACCsetll
:
9403 rtx dest
= frv_read_iacc_argument (DImode
, exp
, 0);
9404 rtx src
= frv_read_argument (exp
, 1);
9405 frv_split_iacc_move (dest
, force_reg (DImode
, src
));
9409 case FRV_BUILTIN_IACCsetl
:
9411 rtx dest
= frv_read_iacc_argument (SImode
, exp
, 0);
9412 rtx src
= frv_read_argument (exp
, 1);
9413 emit_move_insn (dest
, force_reg (SImode
, src
));
9421 /* Expand groups of builtins. */
9423 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9424 if (d
->code
== fcode
)
9425 return frv_expand_set_builtin (d
->icode
, exp
, target
);
9427 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9428 if (d
->code
== fcode
)
9429 return frv_expand_unop_builtin (d
->icode
, exp
, target
);
9431 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9432 if (d
->code
== fcode
)
9433 return frv_expand_binop_builtin (d
->icode
, exp
, target
);
9435 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9436 if (d
->code
== fcode
)
9437 return frv_expand_cut_builtin (d
->icode
, exp
, target
);
9439 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9440 if (d
->code
== fcode
)
9441 return frv_expand_binopimm_builtin (d
->icode
, exp
, target
);
9443 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9444 if (d
->code
== fcode
)
9445 return frv_expand_voidbinop_builtin (d
->icode
, exp
);
9447 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9448 if (d
->code
== fcode
)
9449 return frv_expand_voidtriop_builtin (d
->icode
, exp
);
9451 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9452 if (d
->code
== fcode
)
9453 return frv_expand_voidaccop_builtin (d
->icode
, exp
);
9455 for (i
= 0, d
= bdesc_int_void2arg
;
9456 i
< ARRAY_SIZE (bdesc_int_void2arg
); i
++, d
++)
9457 if (d
->code
== fcode
)
9458 return frv_expand_int_void2arg (d
->icode
, exp
);
9460 for (i
= 0, d
= bdesc_prefetches
;
9461 i
< ARRAY_SIZE (bdesc_prefetches
); i
++, d
++)
9462 if (d
->code
== fcode
)
9463 return frv_expand_prefetches (d
->icode
, exp
);
9465 for (i
= 0, d
= bdesc_loads
; i
< ARRAY_SIZE (bdesc_loads
); i
++, d
++)
9466 if (d
->code
== fcode
)
9467 return frv_expand_load_builtin (d
->icode
, TYPE_MODE (TREE_TYPE (exp
)),
9470 for (i
= 0, d
= bdesc_stores
; i
< ARRAY_SIZE (bdesc_stores
); i
++, d
++)
9471 if (d
->code
== fcode
)
9472 return frv_expand_store_builtin (d
->icode
, exp
);
9478 frv_in_small_data_p (const_tree decl
)
9481 const_tree section_name
;
9483 /* Don't apply the -G flag to internal compiler structures. We
9484 should leave such structures in the main data section, partly
9485 for efficiency and partly because the size of some of them
9486 (such as C++ typeinfos) is not known until later. */
9487 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9490 /* If we already know which section the decl should be in, see if
9491 it's a small data section. */
9492 section_name
= DECL_SECTION_NAME (decl
);
9495 gcc_assert (TREE_CODE (section_name
) == STRING_CST
);
9496 if (frv_string_begins_with (section_name
, ".sdata"))
9498 if (frv_string_begins_with (section_name
, ".sbss"))
9503 size
= int_size_in_bytes (TREE_TYPE (decl
));
9504 if (size
> 0 && size
<= g_switch_value
)
9511 frv_rtx_costs (rtx x
,
9512 int code ATTRIBUTE_UNUSED
,
9513 int outer_code ATTRIBUTE_UNUSED
,
9515 bool speed ATTRIBUTE_UNUSED
)
9517 if (outer_code
== MEM
)
9519 /* Don't differentiate between memory addresses. All the ones
9520 we accept have equal cost. */
9521 *total
= COSTS_N_INSNS (0);
9528 /* Make 12-bit integers really cheap. */
9529 if (IN_RANGE (INTVAL (x
), -2048, 2047))
9540 *total
= COSTS_N_INSNS (2);
9554 if (GET_MODE (x
) == SImode
)
9555 *total
= COSTS_N_INSNS (1);
9556 else if (GET_MODE (x
) == DImode
)
9557 *total
= COSTS_N_INSNS (2);
9559 *total
= COSTS_N_INSNS (3);
9563 if (GET_MODE (x
) == SImode
)
9564 *total
= COSTS_N_INSNS (2);
9566 *total
= COSTS_N_INSNS (6); /* guess */
9573 *total
= COSTS_N_INSNS (18);
9577 *total
= COSTS_N_INSNS (3);
9586 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9588 switch_to_section (ctors_section
);
9589 assemble_align (POINTER_SIZE
);
9592 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9597 assemble_integer_with_op ("\t.picptr\t", symbol
);
9601 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9603 switch_to_section (dtors_section
);
9604 assemble_align (POINTER_SIZE
);
9607 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9612 assemble_integer_with_op ("\t.picptr\t", symbol
);
9615 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9618 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9619 int incoming ATTRIBUTE_UNUSED
)
9621 return gen_rtx_REG (Pmode
, FRV_STRUCT_VALUE_REGNUM
);
9624 #define TLS_BIAS (2048 - 16)
9626 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9627 We need to emit DTP-relative relocations. */
9630 frv_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9632 gcc_assert (size
== 4);
9633 fputs ("\t.picptr\ttlsmoff(", file
);
9634 /* We want the unbiased TLS offset, so add the bias to the
9635 expression, such that the implicit biasing cancels out. */
9636 output_addr_const (file
, plus_constant (x
, TLS_BIAS
));