1 /* Copyright (C) 1997-2015 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
29 #include "fold-const.h"
31 #include "stor-layout.h"
32 #include "stringpool.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
38 #include "insn-attr.h"
50 #include "insn-codes.h"
52 #include "diagnostic-core.h"
57 #include "cfgcleanup.h"
60 #include "targhooks.h"
61 #include "langhooks.h"
67 /* This file should be included last. */
68 #include "target-def.h"
71 #define FRV_INLINE inline
74 /* The maximum number of distinct NOP patterns. There are three:
75 nop, fnop and mnop. */
76 #define NUM_NOP_PATTERNS 3
78 /* Classification of instructions and units: integer, floating-point/media,
79 branch and control. */
80 enum frv_insn_group
{ GROUP_I
, GROUP_FM
, GROUP_B
, GROUP_C
, NUM_GROUPS
};
82 /* The DFA names of the units, in packet order. */
83 static const char *const frv_unit_names
[] =
93 /* The classification of each unit in frv_unit_names[]. */
94 static const enum frv_insn_group frv_unit_groups
[ARRAY_SIZE (frv_unit_names
)] =
104 /* Return the DFA unit code associated with the Nth unit of integer
105 or floating-point group GROUP, */
106 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
108 /* Return the number of integer or floating-point unit UNIT
109 (1 for I1, 2 for F2, etc.). */
110 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
112 /* The DFA unit number for each unit in frv_unit_names[]. */
113 static int frv_unit_codes
[ARRAY_SIZE (frv_unit_names
)];
115 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
116 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
117 no instruction of type T has been seen. */
118 static unsigned int frv_type_to_unit
[TYPE_UNKNOWN
+ 1];
120 /* An array of dummy nop INSNs, one for each type of nop that the
122 static GTY(()) rtx_insn
*frv_nops
[NUM_NOP_PATTERNS
];
124 /* The number of nop instructions in frv_nops[]. */
125 static unsigned int frv_num_nops
;
127 /* The type of access. FRV_IO_UNKNOWN means the access can be either
128 a read or a write. */
129 enum frv_io_type
{ FRV_IO_UNKNOWN
, FRV_IO_READ
, FRV_IO_WRITE
};
131 /* Information about one __builtin_read or __builtin_write access, or
132 the combination of several such accesses. The most general value
133 is all-zeros (an unknown access to an unknown address). */
135 enum frv_io_type type
;
137 /* The constant address being accessed, or zero if not known. */
138 HOST_WIDE_INT const_address
;
140 /* The run-time address, as used in operand 0 of the membar pattern. */
144 /* Return true if instruction INSN should be packed with the following
146 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
148 /* Set the value of PACKING_FLAG_P(INSN). */
149 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
150 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
152 /* Loop with REG set to each hard register in rtx X. */
153 #define FOR_EACH_REGNO(REG, X) \
154 for (REG = REGNO (X); \
155 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
158 /* This structure contains machine specific function data. */
159 struct GTY(()) machine_function
161 /* True if we have created an rtx that relies on the stack frame. */
164 /* True if this function contains at least one __builtin_{read,write}*. */
168 /* Temporary register allocation support structure. */
169 typedef struct frv_tmp_reg_struct
171 HARD_REG_SET regs
; /* possible registers to allocate */
172 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
176 /* Register state information for VLIW re-packing phase. */
177 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
178 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
179 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
180 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
182 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
184 typedef unsigned char regstate_t
;
186 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
194 /* Information required by frv_frame_access. */
197 /* This field is FRV_LOAD if registers are to be loaded from the stack and
198 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
199 the move is being done by the prologue code while FRV_LOAD implies it
200 is being done by the epilogue. */
201 enum frv_stack_op op
;
203 /* The base register to use when accessing the stack. This may be the
204 frame pointer, stack pointer, or a temporary. The choice of register
205 depends on which part of the frame is being accessed and how big the
209 /* The offset of BASE from the bottom of the current frame, in bytes. */
211 } frv_frame_accessor_t
;
213 /* Conditional execution support gathered together in one structure. */
216 /* Linked list of insns to add if the conditional execution conversion was
217 successful. Each link points to an EXPR_LIST which points to the pattern
218 of the insn to add, and the insn to be inserted before. */
219 rtx added_insns_list
;
221 /* Identify which registers are safe to allocate for if conversions to
222 conditional execution. We keep the last allocated register in the
223 register classes between COND_EXEC statements. This will mean we allocate
224 different registers for each different COND_EXEC group if we can. This
225 might allow the scheduler to intermix two different COND_EXEC sections. */
226 frv_tmp_reg_t tmp_reg
;
228 /* For nested IFs, identify which CC registers are used outside of setting
229 via a compare isnsn, and using via a check insn. This will allow us to
230 know if we can rewrite the register to use a different register that will
231 be paired with the CR register controlling the nested IF-THEN blocks. */
232 HARD_REG_SET nested_cc_ok_rewrite
;
234 /* Temporary registers allocated to hold constants during conditional
236 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
238 /* Current number of temp registers available. */
239 int cur_scratch_regs
;
241 /* Number of nested conditional execution blocks. */
242 int num_nested_cond_exec
;
244 /* Map of insns that set up constants in scratch registers. */
245 bitmap scratch_insns_bitmap
;
247 /* Conditional execution test register (CC0..CC7). */
250 /* Conditional execution compare register that is paired with cr_reg, so that
251 nested compares can be done. The csubcc and caddcc instructions don't
252 have enough bits to specify both a CC register to be set and a CR register
253 to do the test on, so the same bit number is used for both. Needless to
254 say, this is rather inconvenient for GCC. */
257 /* Extra CR registers used for &&, ||. */
261 /* Previous CR used in nested if, to make sure we are dealing with the same
262 nested if as the previous statement. */
263 rtx last_nested_if_cr
;
267 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
269 /* Map register number to smallest register class. */
270 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
272 /* Cached value of frv_stack_info. */
273 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
275 /* Forward references */
277 static void frv_option_override (void);
278 static bool frv_legitimate_address_p (machine_mode
, rtx
, bool);
279 static int frv_default_flags_for_cpu (void);
280 static int frv_string_begins_with (const char *, const char *);
281 static FRV_INLINE
bool frv_small_data_reloc_p (rtx
, int);
282 static void frv_print_operand (FILE *, rtx
, int);
283 static void frv_print_operand_address (FILE *, rtx
);
284 static bool frv_print_operand_punct_valid_p (unsigned char code
);
285 static void frv_print_operand_memory_reference_reg
287 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
288 static int frv_print_operand_jump_hint (rtx_insn
*);
289 static const char *comparison_string (enum rtx_code
, rtx
);
290 static rtx
frv_function_value (const_tree
, const_tree
,
292 static rtx
frv_libcall_value (machine_mode
,
294 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
295 static rtx
single_set_pattern (rtx
);
296 static int frv_function_contains_far_jump (void);
297 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
301 static rtx
frv_frame_offset_rtx (int);
302 static rtx
frv_frame_mem (machine_mode
, rtx
, int);
303 static rtx
frv_dwarf_store (rtx
, int);
304 static void frv_frame_insn (rtx
, rtx
);
305 static void frv_frame_access (frv_frame_accessor_t
*,
307 static void frv_frame_access_multi (frv_frame_accessor_t
*,
309 static void frv_frame_access_standard_regs (enum frv_stack_op
,
311 static struct machine_function
*frv_init_machine_status (void);
312 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
313 static machine_mode
frv_matching_accg_mode (machine_mode
);
314 static rtx
frv_read_argument (tree
, unsigned int);
315 static rtx
frv_read_iacc_argument (machine_mode
, tree
, unsigned int);
316 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
317 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
318 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
319 static rtx
frv_legitimize_tls_address (rtx
, enum tls_model
);
320 static rtx
frv_legitimize_address (rtx
, rtx
, machine_mode
);
321 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
322 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
323 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
324 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
325 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
326 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
327 static rtx
frv_expand_int_void2arg (enum insn_code
, tree
);
328 static rtx
frv_expand_prefetches (enum insn_code
, tree
);
329 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
330 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
331 static rtx
frv_expand_mclracc_builtin (tree
);
332 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
333 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
334 static rtx
frv_expand_noargs_builtin (enum insn_code
);
335 static void frv_split_iacc_move (rtx
, rtx
);
336 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
337 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
338 static rtx
frv_ifcvt_rewrite_mem (rtx
, machine_mode
, rtx
);
339 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
340 static unsigned int frv_insn_unit (rtx_insn
*);
341 static bool frv_issues_to_branch_unit_p (rtx_insn
*);
342 static int frv_cond_flags (rtx
);
343 static bool frv_regstate_conflict_p (regstate_t
, regstate_t
);
344 static bool frv_registers_conflict_p (rtx
);
345 static void frv_registers_update_1 (rtx
, const_rtx
, void *);
346 static void frv_registers_update (rtx
);
347 static void frv_start_packet (void);
348 static void frv_start_packet_block (void);
349 static void frv_finish_packet (void (*) (void));
350 static bool frv_pack_insn_p (rtx_insn
*);
351 static void frv_add_insn_to_packet (rtx_insn
*);
352 static void frv_insert_nop_in_packet (rtx_insn
*);
353 static bool frv_for_each_packet (void (*) (void));
354 static bool frv_sort_insn_group_1 (enum frv_insn_group
,
355 unsigned int, unsigned int,
356 unsigned int, unsigned int,
358 static int frv_compare_insns (const void *, const void *);
359 static void frv_sort_insn_group (enum frv_insn_group
);
360 static void frv_reorder_packet (void);
361 static void frv_fill_unused_units (enum frv_insn_group
);
362 static void frv_align_label (void);
363 static void frv_reorg_packet (void);
364 static void frv_register_nop (rtx
);
365 static void frv_reorg (void);
366 static void frv_pack_insns (void);
367 static void frv_function_prologue (FILE *, HOST_WIDE_INT
);
368 static void frv_function_epilogue (FILE *, HOST_WIDE_INT
);
369 static bool frv_assemble_integer (rtx
, unsigned, int);
370 static void frv_init_builtins (void);
371 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
372 static void frv_init_libfuncs (void);
373 static bool frv_in_small_data_p (const_tree
);
374 static void frv_asm_output_mi_thunk
375 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
376 static void frv_setup_incoming_varargs (cumulative_args_t
,
379 static rtx
frv_expand_builtin_saveregs (void);
380 static void frv_expand_builtin_va_start (tree
, rtx
);
381 static bool frv_rtx_costs (rtx
, machine_mode
, int, int,
383 static int frv_register_move_cost (machine_mode
,
384 reg_class_t
, reg_class_t
);
385 static int frv_memory_move_cost (machine_mode
,
387 static void frv_asm_out_constructor (rtx
, int);
388 static void frv_asm_out_destructor (rtx
, int);
389 static bool frv_function_symbol_referenced_p (rtx
);
390 static bool frv_legitimate_constant_p (machine_mode
, rtx
);
391 static bool frv_cannot_force_const_mem (machine_mode
, rtx
);
392 static const char *unspec_got_name (int);
393 static void frv_output_const_unspec (FILE *,
394 const struct frv_unspec
*);
395 static bool frv_function_ok_for_sibcall (tree
, tree
);
396 static rtx
frv_struct_value_rtx (tree
, int);
397 static bool frv_must_pass_in_stack (machine_mode mode
, const_tree type
);
398 static int frv_arg_partial_bytes (cumulative_args_t
, machine_mode
,
400 static rtx
frv_function_arg (cumulative_args_t
, machine_mode
,
402 static rtx
frv_function_incoming_arg (cumulative_args_t
, machine_mode
,
404 static void frv_function_arg_advance (cumulative_args_t
, machine_mode
,
406 static unsigned int frv_function_arg_boundary (machine_mode
,
408 static void frv_output_dwarf_dtprel (FILE *, int, rtx
)
410 static reg_class_t
frv_secondary_reload (bool, rtx
, reg_class_t
,
412 secondary_reload_info
*);
413 static bool frv_frame_pointer_required (void);
414 static bool frv_can_eliminate (const int, const int);
415 static void frv_conditional_register_usage (void);
416 static void frv_trampoline_init (rtx
, tree
, rtx
);
417 static bool frv_class_likely_spilled_p (reg_class_t
);
419 /* Initialize the GCC target structure. */
420 #undef TARGET_PRINT_OPERAND
421 #define TARGET_PRINT_OPERAND frv_print_operand
422 #undef TARGET_PRINT_OPERAND_ADDRESS
423 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
424 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
425 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
426 #undef TARGET_ASM_FUNCTION_PROLOGUE
427 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
428 #undef TARGET_ASM_FUNCTION_EPILOGUE
429 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
430 #undef TARGET_ASM_INTEGER
431 #define TARGET_ASM_INTEGER frv_assemble_integer
432 #undef TARGET_OPTION_OVERRIDE
433 #define TARGET_OPTION_OVERRIDE frv_option_override
434 #undef TARGET_INIT_BUILTINS
435 #define TARGET_INIT_BUILTINS frv_init_builtins
436 #undef TARGET_EXPAND_BUILTIN
437 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
438 #undef TARGET_INIT_LIBFUNCS
439 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
440 #undef TARGET_IN_SMALL_DATA_P
441 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
442 #undef TARGET_REGISTER_MOVE_COST
443 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
444 #undef TARGET_MEMORY_MOVE_COST
445 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
446 #undef TARGET_RTX_COSTS
447 #define TARGET_RTX_COSTS frv_rtx_costs
448 #undef TARGET_ASM_CONSTRUCTOR
449 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
450 #undef TARGET_ASM_DESTRUCTOR
451 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
453 #undef TARGET_ASM_OUTPUT_MI_THUNK
454 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
455 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
456 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
458 #undef TARGET_SCHED_ISSUE_RATE
459 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
461 #undef TARGET_LEGITIMIZE_ADDRESS
462 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
464 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
465 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
466 #undef TARGET_LEGITIMATE_CONSTANT_P
467 #define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p
468 #undef TARGET_CANNOT_FORCE_CONST_MEM
469 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
471 #undef TARGET_HAVE_TLS
472 #define TARGET_HAVE_TLS HAVE_AS_TLS
474 #undef TARGET_STRUCT_VALUE_RTX
475 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
476 #undef TARGET_MUST_PASS_IN_STACK
477 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
478 #undef TARGET_PASS_BY_REFERENCE
479 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
480 #undef TARGET_ARG_PARTIAL_BYTES
481 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
482 #undef TARGET_FUNCTION_ARG
483 #define TARGET_FUNCTION_ARG frv_function_arg
484 #undef TARGET_FUNCTION_INCOMING_ARG
485 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
486 #undef TARGET_FUNCTION_ARG_ADVANCE
487 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
488 #undef TARGET_FUNCTION_ARG_BOUNDARY
489 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
491 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
492 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
493 #undef TARGET_SETUP_INCOMING_VARARGS
494 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
495 #undef TARGET_MACHINE_DEPENDENT_REORG
496 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
498 #undef TARGET_EXPAND_BUILTIN_VA_START
499 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
502 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
503 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
506 #undef TARGET_CLASS_LIKELY_SPILLED_P
507 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
509 #undef TARGET_SECONDARY_RELOAD
510 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
512 #undef TARGET_LEGITIMATE_ADDRESS_P
513 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
515 #undef TARGET_FRAME_POINTER_REQUIRED
516 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
518 #undef TARGET_CAN_ELIMINATE
519 #define TARGET_CAN_ELIMINATE frv_can_eliminate
521 #undef TARGET_CONDITIONAL_REGISTER_USAGE
522 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
524 #undef TARGET_TRAMPOLINE_INIT
525 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
527 #undef TARGET_FUNCTION_VALUE
528 #define TARGET_FUNCTION_VALUE frv_function_value
529 #undef TARGET_LIBCALL_VALUE
530 #define TARGET_LIBCALL_VALUE frv_libcall_value
532 struct gcc_target targetm
= TARGET_INITIALIZER
;
534 #define FRV_SYMBOL_REF_TLS_P(RTX) \
535 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
538 /* Any function call that satisfies the machine-independent
539 requirements is eligible on FR-V. */
542 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
543 tree exp ATTRIBUTE_UNUSED
)
548 /* Return true if SYMBOL is a small data symbol and relocation RELOC
549 can be used to access it directly in a load or store. */
551 static FRV_INLINE
bool
552 frv_small_data_reloc_p (rtx symbol
, int reloc
)
554 return (GET_CODE (symbol
) == SYMBOL_REF
555 && SYMBOL_REF_SMALL_P (symbol
)
556 && (!TARGET_FDPIC
|| flag_pic
== 1)
557 && (reloc
== R_FRV_GOTOFF12
|| reloc
== R_FRV_GPREL12
));
560 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
564 frv_const_unspec_p (rtx x
, struct frv_unspec
*unspec
)
566 if (GET_CODE (x
) == CONST
)
570 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
572 unspec
->offset
+= INTVAL (XEXP (x
, 1));
575 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOT
)
577 unspec
->symbol
= XVECEXP (x
, 0, 0);
578 unspec
->reloc
= INTVAL (XVECEXP (x
, 0, 1));
580 if (unspec
->offset
== 0)
583 if (frv_small_data_reloc_p (unspec
->symbol
, unspec
->reloc
)
584 && unspec
->offset
> 0
585 && unspec
->offset
< g_switch_value
)
592 /* Decide whether we can force certain constants to memory. If we
593 decide we can't, the caller should be able to cope with it in
596 We never allow constants to be forced into memory for TARGET_FDPIC.
597 This is necessary for several reasons:
599 1. Since frv_legitimate_constant_p rejects constant pool addresses, the
600 target-independent code will try to force them into the constant
601 pool, thus leading to infinite recursion.
603 2. We can never introduce new constant pool references during reload.
604 Any such reference would require use of the pseudo FDPIC register.
606 3. We can't represent a constant added to a function pointer (which is
607 not the same as a pointer to a function+constant).
609 4. In many cases, it's more efficient to calculate the constant in-line. */
612 frv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
,
613 rtx x ATTRIBUTE_UNUSED
)
619 frv_default_flags_for_cpu (void)
621 switch (frv_cpu_type
)
623 case FRV_CPU_GENERIC
:
624 return MASK_DEFAULT_FRV
;
627 return MASK_DEFAULT_FR550
;
631 return MASK_DEFAULT_FR500
;
634 return MASK_DEFAULT_FR450
;
638 return MASK_DEFAULT_FR400
;
642 return MASK_DEFAULT_SIMPLE
;
649 /* Implement TARGET_OPTION_OVERRIDE. */
652 frv_option_override (void)
657 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
659 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
660 linker about linking pic and non-pic code. */
663 if (!flag_pic
) /* -fPIC */
666 if (!global_options_set
.x_g_switch_value
) /* -G0 */
672 /* A C expression whose value is a register class containing hard
673 register REGNO. In general there is more than one such class;
674 choose a class which is "minimal", meaning that no smaller class
675 also contains the register. */
677 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
679 enum reg_class rclass
;
683 int gpr_reg
= regno
- GPR_FIRST
;
685 if (gpr_reg
== GR8_REG
)
688 else if (gpr_reg
== GR9_REG
)
691 else if (gpr_reg
== GR14_REG
)
692 rclass
= FDPIC_FPTR_REGS
;
694 else if (gpr_reg
== FDPIC_REGNO
)
697 else if ((gpr_reg
& 3) == 0)
700 else if ((gpr_reg
& 1) == 0)
707 else if (FPR_P (regno
))
709 int fpr_reg
= regno
- GPR_FIRST
;
710 if ((fpr_reg
& 3) == 0)
711 rclass
= QUAD_FPR_REGS
;
713 else if ((fpr_reg
& 1) == 0)
720 else if (regno
== LR_REGNO
)
723 else if (regno
== LCR_REGNO
)
726 else if (ICC_P (regno
))
729 else if (FCC_P (regno
))
732 else if (ICR_P (regno
))
735 else if (FCR_P (regno
))
738 else if (ACC_P (regno
))
740 int r
= regno
- ACC_FIRST
;
742 rclass
= QUAD_ACC_REGS
;
743 else if ((r
& 1) == 0)
744 rclass
= EVEN_ACC_REGS
;
749 else if (ACCG_P (regno
))
755 regno_reg_class
[regno
] = rclass
;
758 /* Check for small data option */
759 if (!global_options_set
.x_g_switch_value
&& !TARGET_LIBPIC
)
760 g_switch_value
= SDATA_DEFAULT_SIZE
;
762 /* There is no single unaligned SI op for PIC code. Sometimes we
763 need to use ".4byte" and sometimes we need to use ".picptr".
764 See frv_assemble_integer for details. */
765 if (flag_pic
|| TARGET_FDPIC
)
766 targetm
.asm_out
.unaligned_op
.si
= 0;
768 if ((target_flags_explicit
& MASK_LINKED_FP
) == 0)
769 target_flags
|= MASK_LINKED_FP
;
771 if ((target_flags_explicit
& MASK_OPTIMIZE_MEMBAR
) == 0)
772 target_flags
|= MASK_OPTIMIZE_MEMBAR
;
774 for (i
= 0; i
< ARRAY_SIZE (frv_unit_names
); i
++)
775 frv_unit_codes
[i
] = get_cpu_unit_code (frv_unit_names
[i
]);
777 for (i
= 0; i
< ARRAY_SIZE (frv_type_to_unit
); i
++)
778 frv_type_to_unit
[i
] = ARRAY_SIZE (frv_unit_codes
);
780 init_machine_status
= frv_init_machine_status
;
784 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
787 frv_string_begins_with (const char *name
, const char *prefix
)
789 const int prefix_len
= strlen (prefix
);
791 /* Remember: NAME's length includes the null terminator. */
792 return (strncmp (name
, prefix
, prefix_len
) == 0);
795 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
798 frv_conditional_register_usage (void)
802 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
803 fixed_regs
[i
] = call_used_regs
[i
] = 1;
805 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
806 fixed_regs
[i
] = call_used_regs
[i
] = 1;
808 /* Reserve the registers used for conditional execution. At present, we need
809 1 ICC and 1 ICR register. */
810 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
811 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
815 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
816 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
817 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
818 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
822 fixed_regs
[GPR_FIRST
+ 16] = fixed_regs
[GPR_FIRST
+ 17] =
823 call_used_regs
[GPR_FIRST
+ 16] = call_used_regs
[GPR_FIRST
+ 17] = 0;
826 /* If -fpic, SDA_BASE_REG is the PIC register. */
827 if (g_switch_value
== 0 && !flag_pic
)
828 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
831 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
837 * Compute the stack frame layout
840 * +---------------+-----------------------+-----------------------+
841 * |Register |type |caller-save/callee-save|
842 * +---------------+-----------------------+-----------------------+
843 * |GR0 |Zero register | - |
844 * |GR1 |Stack pointer(SP) | - |
845 * |GR2 |Frame pointer(FP) | - |
846 * |GR3 |Hidden parameter | caller save |
847 * |GR4-GR7 | - | caller save |
848 * |GR8-GR13 |Argument register | caller save |
849 * |GR14-GR15 | - | caller save |
850 * |GR16-GR31 | - | callee save |
851 * |GR32-GR47 | - | caller save |
852 * |GR48-GR63 | - | callee save |
853 * |FR0-FR15 | - | caller save |
854 * |FR16-FR31 | - | callee save |
855 * |FR32-FR47 | - | caller save |
856 * |FR48-FR63 | - | callee save |
857 * +---------------+-----------------------+-----------------------+
861 * SP-> |-----------------------------------|
863 * |-----------------------------------|
864 * | Register save area |
865 * |-----------------------------------|
866 * | Local variable save area |
867 * FP-> |-----------------------------------|
869 * |-----------------------------------|
870 * | Hidden parameter save area |
871 * |-----------------------------------|
872 * | Return address(LR) storage area |
873 * |-----------------------------------|
874 * | Padding for alignment |
875 * |-----------------------------------|
876 * | Register argument area |
877 * OLD SP-> |-----------------------------------|
879 * |-----------------------------------|
882 * Argument area/Parameter area:
884 * When a function is called, this area is used for argument transfer. When
885 * the argument is set up by the caller function, this area is referred to as
886 * the argument area. When the argument is referenced by the callee function,
887 * this area is referred to as the parameter area. The area is allocated when
888 * all arguments cannot be placed on the argument register at the time of
891 * Register save area:
893 * This is a register save area that must be guaranteed for the caller
894 * function. This area is not secured when the register save operation is not
897 * Local variable save area:
899 * This is the area for local variables and temporary variables.
903 * This area stores the FP value of the caller function.
905 * Hidden parameter save area:
907 * This area stores the start address of the return value storage
908 * area for a struct/union return function.
909 * When a struct/union is used as the return value, the caller
910 * function stores the return value storage area start address in
911 * register GR3 and passes it to the caller function.
912 * The callee function interprets the address stored in the GR3
913 * as the return value storage area start address.
914 * When register GR3 needs to be saved into memory, the callee
915 * function saves it in the hidden parameter save area. This
916 * area is not secured when the save operation is not needed.
918 * Return address(LR) storage area:
920 * This area saves the LR. The LR stores the address of a return to the caller
921 * function for the purpose of function calling.
923 * Argument register area:
925 * This area saves the argument register. This area is not secured when the
926 * save operation is not needed.
930 * Arguments, the count of which equals the count of argument registers (6
931 * words), are positioned in registers GR8 to GR13 and delivered to the callee
932 * function. When a struct/union return function is called, the return value
933 * area address is stored in register GR3. Arguments not placed in the
934 * argument registers will be stored in the stack argument area for transfer
935 * purposes. When an 8-byte type argument is to be delivered using registers,
936 * it is divided into two and placed in two registers for transfer. When
937 * argument registers must be saved to memory, the callee function secures an
938 * argument register save area in the stack. In this case, a continuous
939 * argument register save area must be established in the parameter area. The
940 * argument register save area must be allocated as needed to cover the size of
941 * the argument register to be saved. If the function has a variable count of
942 * arguments, it saves all argument registers in the argument register save
945 * Argument Extension Format:
947 * When an argument is to be stored in the stack, its type is converted to an
948 * extended type in accordance with the individual argument type. The argument
949 * is freed by the caller function after the return from the callee function is
952 * +-----------------------+---------------+------------------------+
953 * | Argument Type |Extended Type |Stack Storage Size(byte)|
954 * +-----------------------+---------------+------------------------+
956 * |signed char |int | 4 |
957 * |unsigned char |int | 4 |
958 * |[signed] short int |int | 4 |
959 * |unsigned short int |int | 4 |
960 * |[signed] int |No extension | 4 |
961 * |unsigned int |No extension | 4 |
962 * |[signed] long int |No extension | 4 |
963 * |unsigned long int |No extension | 4 |
964 * |[signed] long long int |No extension | 8 |
965 * |unsigned long long int |No extension | 8 |
966 * |float |double | 8 |
967 * |double |No extension | 8 |
968 * |long double |No extension | 8 |
969 * |pointer |No extension | 4 |
970 * |struct/union |- | 4 (*1) |
971 * +-----------------------+---------------+------------------------+
973 * When a struct/union is to be delivered as an argument, the caller copies it
974 * to the local variable area and delivers the address of that area.
978 * +-------------------------------+----------------------+
979 * |Return Value Type |Return Value Interface|
980 * +-------------------------------+----------------------+
982 * |[signed|unsigned] char |GR8 |
983 * |[signed|unsigned] short int |GR8 |
984 * |[signed|unsigned] int |GR8 |
985 * |[signed|unsigned] long int |GR8 |
987 * |[signed|unsigned] long long int|GR8 & GR9 |
989 * |double |GR8 & GR9 |
990 * |long double |GR8 & GR9 |
991 * |struct/union |(*1) |
992 * +-------------------------------+----------------------+
994 * When a struct/union is used as the return value, the caller function stores
995 * the start address of the return value storage area into GR3 and then passes
996 * it to the callee function. The callee function interprets GR3 as the start
997 * address of the return value storage area. When this address needs to be
998 * saved in memory, the callee function secures the hidden parameter save area
999 * and saves the address in that area.
1003 frv_stack_info (void)
1005 static frv_stack_t info
, zero_info
;
1006 frv_stack_t
*info_ptr
= &info
;
1007 tree fndecl
= current_function_decl
;
1015 /* If we've already calculated the values and reload is complete,
1017 if (frv_stack_cache
)
1018 return frv_stack_cache
;
1020 /* Zero all fields. */
1023 /* Set up the register range information. */
1024 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
1025 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
1026 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
1027 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
1029 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
1030 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
1031 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
1032 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
1034 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
1035 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
1036 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
1037 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
1039 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
1040 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
1041 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
1042 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
1044 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
1045 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
1046 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
1048 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
1049 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
1050 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
1051 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
1052 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
1054 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
1055 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= FRV_STRUCT_VALUE_REGNUM
;
1056 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= FRV_STRUCT_VALUE_REGNUM
;
1057 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
1059 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
1060 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
1061 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
1062 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
1064 /* Determine if this is a stdarg function. If so, allocate space to store
1071 /* Find the last argument, and see if it is __builtin_va_alist. */
1072 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
1074 next_arg
= DECL_CHAIN (cur_arg
);
1075 if (next_arg
== (tree
)0)
1077 if (DECL_NAME (cur_arg
)
1078 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1086 /* Iterate over all of the register ranges. */
1087 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1089 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1090 int first
= reg_ptr
->first
;
1091 int last
= reg_ptr
->last
;
1093 int size_2words
= 0;
1096 /* Calculate which registers need to be saved & save area size. */
1100 for (regno
= first
; regno
<= last
; regno
++)
1102 if ((df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1103 || (crtl
->calls_eh_return
1104 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1105 || (!TARGET_FDPIC
&& flag_pic
1106 && crtl
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1108 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1109 size_1word
+= UNITS_PER_WORD
;
1114 /* Calculate whether we need to create a frame after everything else
1115 has been processed. */
1120 if (df_regs_ever_live_p (LR_REGNO
)
1122 /* This is set for __builtin_return_address, etc. */
1123 || cfun
->machine
->frame_needed
1124 || (TARGET_LINKED_FP
&& frame_pointer_needed
)
1125 || (!TARGET_FDPIC
&& flag_pic
1126 && crtl
->uses_pic_offset_table
))
1128 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1129 size_1word
+= UNITS_PER_WORD
;
1133 case STACK_REGS_STDARG
:
1136 /* If this is a stdarg function with a non varardic
1137 argument split between registers and the stack,
1138 adjust the saved registers downward. */
1139 last
-= (ADDR_ALIGN (crtl
->args
.pretend_args_size
, UNITS_PER_WORD
)
1142 for (regno
= first
; regno
<= last
; regno
++)
1144 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1145 size_1word
+= UNITS_PER_WORD
;
1148 info_ptr
->stdarg_size
= size_1word
;
1152 case STACK_REGS_STRUCT
:
1153 if (cfun
->returns_struct
)
1155 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1156 size_1word
+= UNITS_PER_WORD
;
1164 /* If this is a field, it only takes one word. */
1165 if (reg_ptr
->field_p
)
1166 size_1word
= UNITS_PER_WORD
;
1168 /* Determine which register pairs can be saved together. */
1169 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1171 for (regno
= first
; regno
< last
; regno
+= 2)
1173 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1175 size_2words
+= 2 * UNITS_PER_WORD
;
1176 size_1word
-= 2 * UNITS_PER_WORD
;
1177 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1178 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1183 reg_ptr
->size_1word
= size_1word
;
1184 reg_ptr
->size_2words
= size_2words
;
1186 if (! reg_ptr
->special_p
)
1188 info_ptr
->regs_size_1word
+= size_1word
;
1189 info_ptr
->regs_size_2words
+= size_2words
;
1194 /* Set up the sizes of each field in the frame body, making the sizes
1195 of each be divisible by the size of a dword if dword operations might
1196 be used, or the size of a word otherwise. */
1197 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1199 info_ptr
->parameter_size
= ADDR_ALIGN (crtl
->outgoing_args_size
, alignment
);
1200 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1201 + info_ptr
->regs_size_1word
,
1203 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1205 info_ptr
->pretend_size
= crtl
->args
.pretend_args_size
;
1207 /* Work out the size of the frame, excluding the header. Both the frame
1208 body and register parameter area will be dword-aligned. */
1209 info_ptr
->total_size
1210 = (ADDR_ALIGN (info_ptr
->parameter_size
1211 + info_ptr
->regs_size
1212 + info_ptr
->vars_size
,
1214 + ADDR_ALIGN (info_ptr
->pretend_size
1215 + info_ptr
->stdarg_size
,
1216 2 * UNITS_PER_WORD
));
1218 /* See if we need to create a frame at all, if so add header area. */
1219 if (info_ptr
->total_size
> 0
1220 || frame_pointer_needed
1221 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1222 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1224 offset
= info_ptr
->parameter_size
;
1225 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1226 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1228 /* Calculate the offsets to save normal register pairs. */
1229 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1231 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1232 if (! reg_ptr
->special_p
)
1234 int first
= reg_ptr
->first
;
1235 int last
= reg_ptr
->last
;
1238 for (regno
= first
; regno
<= last
; regno
++)
1239 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1240 && regno
!= FRAME_POINTER_REGNUM
1241 && (regno
< FIRST_ARG_REGNUM
1242 || regno
> LAST_ARG_REGNUM
))
1244 info_ptr
->reg_offset
[regno
] = offset
;
1245 offset
+= 2 * UNITS_PER_WORD
;
1250 /* Calculate the offsets to save normal single registers. */
1251 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1253 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1254 if (! reg_ptr
->special_p
)
1256 int first
= reg_ptr
->first
;
1257 int last
= reg_ptr
->last
;
1260 for (regno
= first
; regno
<= last
; regno
++)
1261 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1262 && regno
!= FRAME_POINTER_REGNUM
1263 && (regno
< FIRST_ARG_REGNUM
1264 || regno
> LAST_ARG_REGNUM
))
1266 info_ptr
->reg_offset
[regno
] = offset
;
1267 offset
+= UNITS_PER_WORD
;
1272 /* Calculate the offset to save the local variables at. */
1273 offset
= ADDR_ALIGN (offset
, alignment
);
1274 if (info_ptr
->vars_size
)
1276 info_ptr
->vars_offset
= offset
;
1277 offset
+= info_ptr
->vars_size
;
1280 /* Align header to a dword-boundary. */
1281 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1283 /* Calculate the offsets in the fixed frame. */
1284 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1285 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1286 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1288 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1289 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1290 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1292 if (cfun
->returns_struct
)
1294 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1295 info_ptr
->reg_offset
[FRV_STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1296 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1299 /* Calculate the offsets to store the arguments passed in registers
1300 for stdarg functions. The register pairs are first and the single
1301 register if any is last. The register save area starts on a
1303 if (info_ptr
->stdarg_size
)
1305 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1306 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1309 /* Skip the header. */
1310 offset
+= 4 * UNITS_PER_WORD
;
1311 for (regno
= first
; regno
<= last
; regno
++)
1313 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1315 info_ptr
->reg_offset
[regno
] = offset
;
1316 offset
+= 2 * UNITS_PER_WORD
;
1318 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1320 info_ptr
->reg_offset
[regno
] = offset
;
1321 offset
+= UNITS_PER_WORD
;
1327 if (reload_completed
)
1328 frv_stack_cache
= info_ptr
;
1334 /* Print the information about the frv stack offsets, etc. when debugging. */
1337 frv_debug_stack (frv_stack_t
*info
)
1342 info
= frv_stack_info ();
1344 fprintf (stderr
, "\nStack information for function %s:\n",
1345 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1346 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1349 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1350 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1351 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1352 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1353 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1355 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1356 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1357 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1358 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1360 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1362 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1363 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1365 int first
= regs
->first
;
1366 int last
= regs
->last
;
1369 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1370 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1371 regs
->size_1word
, regs
->size_2words
);
1373 for (regno
= first
; regno
<= last
; regno
++)
1375 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1376 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1377 info
->reg_offset
[regno
]);
1379 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1380 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1381 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1384 fputc ('\n', stderr
);
1394 /* Used during final to control the packing of insns. The value is
1395 1 if the current instruction should be packed with the next one,
1396 0 if it shouldn't or -1 if packing is disabled altogether. */
1398 static int frv_insn_packing_flag
;
1400 /* True if the current function contains a far jump. */
1403 frv_function_contains_far_jump (void)
1405 rtx_insn
*insn
= get_insns ();
1408 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1409 insn
= NEXT_INSN (insn
);
1410 return (insn
!= NULL
);
1413 /* For the FRV, this function makes sure that a function with far jumps
1414 will return correctly. It also does the VLIW packing. */
1417 frv_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1419 rtx_insn
*insn
, *next
, *last_call
;
1421 /* If no frame was created, check whether the function uses a call
1422 instruction to implement a far jump. If so, save the link in gr3 and
1423 replace all returns to LR with returns to GR3. GR3 is used because it
1424 is call-clobbered, because is not available to the register allocator,
1425 and because all functions that take a hidden argument pointer will have
1427 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1431 /* Just to check that the above comment is true. */
1432 gcc_assert (!df_regs_ever_live_p (GPR_FIRST
+ 3));
1434 /* Generate the instruction that saves the link register. */
1435 fprintf (file
, "\tmovsg lr,gr3\n");
1437 /* Replace the LR with GR3 in *return_internal patterns. The insn
1438 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1439 simply emit a different assembly directive because bralr and jmpl
1440 execute in different units. */
1441 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1444 rtx pattern
= PATTERN (insn
);
1445 if (GET_CODE (pattern
) == PARALLEL
1446 && XVECLEN (pattern
, 0) >= 2
1447 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1448 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1450 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1451 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1452 SET_REGNO (address
, GPR_FIRST
+ 3);
1459 /* Allow the garbage collector to free the nops created by frv_reorg. */
1460 memset (frv_nops
, 0, sizeof (frv_nops
));
1462 /* Locate CALL_ARG_LOCATION notes that have been misplaced
1463 and move them back to where they should be located. */
1465 for (insn
= get_insns (); insn
; insn
= next
)
1467 next
= NEXT_INSN (insn
);
1469 || (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
1470 && CALL_P (XVECEXP (PATTERN (insn
), 0, 0))))
1473 if (!NOTE_P (insn
) || NOTE_KIND (insn
) != NOTE_INSN_CALL_ARG_LOCATION
)
1476 if (NEXT_INSN (last_call
) == insn
)
1479 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
1480 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
1481 SET_PREV_INSN (insn
) = last_call
;
1482 SET_NEXT_INSN (insn
) = NEXT_INSN (last_call
);
1483 SET_PREV_INSN (NEXT_INSN (insn
)) = insn
;
1484 SET_NEXT_INSN (PREV_INSN (insn
)) = insn
;
1490 /* Return the next available temporary register in a given class. */
1493 frv_alloc_temp_reg (
1494 frv_tmp_reg_t
*info
, /* which registers are available */
1495 enum reg_class rclass
, /* register class desired */
1496 machine_mode mode
, /* mode to allocate register with */
1497 int mark_as_used
, /* register not available after allocation */
1498 int no_abort
) /* return NULL instead of aborting */
1500 int regno
= info
->next_reg
[ (int)rclass
];
1501 int orig_regno
= regno
;
1502 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)rclass
];
1507 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1508 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1511 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1513 if (regno
== orig_regno
)
1515 gcc_assert (no_abort
);
1520 nr
= HARD_REGNO_NREGS (regno
, mode
);
1521 info
->next_reg
[ (int)rclass
] = regno
+ nr
;
1524 for (i
= 0; i
< nr
; i
++)
1525 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1527 return gen_rtx_REG (mode
, regno
);
1531 /* Return an rtx with the value OFFSET, which will either be a register or a
1532 signed 12-bit integer. It can be used as the second operand in an "add"
1533 instruction, or as the index in a load or store.
1535 The function returns a constant rtx if OFFSET is small enough, otherwise
1536 it loads the constant into register OFFSET_REGNO and returns that. */
1538 frv_frame_offset_rtx (int offset
)
1540 rtx offset_rtx
= GEN_INT (offset
);
1541 if (IN_RANGE (offset
, -2048, 2047))
1545 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1546 if (IN_RANGE (offset
, -32768, 32767))
1547 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1550 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1551 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1557 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1558 prologue and epilogue uses such expressions to access the stack. */
1560 frv_frame_mem (machine_mode mode
, rtx base
, int offset
)
1562 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1564 frv_frame_offset_rtx (offset
)));
1567 /* Generate a frame-related expression:
1569 (set REG (mem (plus (sp) (const_int OFFSET)))).
1571 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1572 instructions. Marking the expressions as frame-related is superfluous if
1573 the note contains just a single set. But if the note contains a PARALLEL
1574 or SEQUENCE that has several sets, each set must be individually marked
1575 as frame-related. */
1577 frv_dwarf_store (rtx reg
, int offset
)
1579 rtx set
= gen_rtx_SET (gen_rtx_MEM (GET_MODE (reg
),
1580 plus_constant (Pmode
, stack_pointer_rtx
,
1583 RTX_FRAME_RELATED_P (set
) = 1;
1587 /* Emit a frame-related instruction whose pattern is PATTERN. The
1588 instruction is the last in a sequence that cumulatively performs the
1589 operation described by DWARF_PATTERN. The instruction is marked as
1590 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1593 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1595 rtx insn
= emit_insn (pattern
);
1596 RTX_FRAME_RELATED_P (insn
) = 1;
1597 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1602 /* Emit instructions that transfer REG to or from the memory location (sp +
1603 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1604 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1605 function to store registers and only the epilogue uses it to load them.
1607 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1608 The generated instruction will use BASE as its base register. BASE may
1609 simply be the stack pointer, but if several accesses are being made to a
1610 region far away from the stack pointer, it may be more efficient to set
1611 up a temporary instead.
1613 Store instructions will be frame-related and will be annotated with the
1614 overall effect of the store. Load instructions will be followed by a
1615 (use) to prevent later optimizations from zapping them.
1617 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1618 as a temporary in such cases. */
1620 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1622 machine_mode mode
= GET_MODE (reg
);
1623 rtx mem
= frv_frame_mem (mode
,
1625 stack_offset
- accessor
->base_offset
);
1627 if (accessor
->op
== FRV_LOAD
)
1629 if (SPR_P (REGNO (reg
)))
1631 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1632 emit_insn (gen_rtx_SET (temp
, mem
));
1633 emit_insn (gen_rtx_SET (reg
, temp
));
1637 /* We cannot use reg+reg addressing for DImode access. */
1639 && GET_CODE (XEXP (mem
, 0)) == PLUS
1640 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1641 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1643 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1645 emit_move_insn (temp
,
1646 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1647 XEXP (XEXP (mem
, 0), 1)));
1648 mem
= gen_rtx_MEM (DImode
, temp
);
1650 emit_insn (gen_rtx_SET (reg
, mem
));
1656 if (SPR_P (REGNO (reg
)))
1658 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1659 emit_insn (gen_rtx_SET (temp
, reg
));
1660 frv_frame_insn (gen_rtx_SET (mem
, temp
),
1661 frv_dwarf_store (reg
, stack_offset
));
1663 else if (mode
== DImode
)
1665 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1666 with a separate save for each register. */
1667 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1668 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1669 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1670 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1672 /* Also we cannot use reg+reg addressing. */
1673 if (GET_CODE (XEXP (mem
, 0)) == PLUS
1674 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1675 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1677 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1678 emit_move_insn (temp
,
1679 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1680 XEXP (XEXP (mem
, 0), 1)));
1681 mem
= gen_rtx_MEM (DImode
, temp
);
1684 frv_frame_insn (gen_rtx_SET (mem
, reg
),
1685 gen_rtx_PARALLEL (VOIDmode
,
1686 gen_rtvec (2, set1
, set2
)));
1689 frv_frame_insn (gen_rtx_SET (mem
, reg
),
1690 frv_dwarf_store (reg
, stack_offset
));
1694 /* A function that uses frv_frame_access to transfer a group of registers to
1695 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1696 is the stack information generated by frv_stack_info, and REG_SET is the
1697 number of the register set to transfer. */
1699 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1703 frv_stack_regs_t
*regs_info
;
1706 regs_info
= &info
->regs
[reg_set
];
1707 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1708 if (info
->save_p
[regno
])
1709 frv_frame_access (accessor
,
1710 info
->save_p
[regno
] == REG_SAVE_2WORDS
1711 ? gen_rtx_REG (DImode
, regno
)
1712 : gen_rtx_REG (SImode
, regno
),
1713 info
->reg_offset
[regno
]);
1716 /* Save or restore callee-saved registers that are kept outside the frame
1717 header. The function saves the registers if OP is FRV_STORE and restores
1718 them if OP is FRV_LOAD. INFO is the stack information generated by
1721 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1723 frv_frame_accessor_t accessor
;
1726 accessor
.base
= stack_pointer_rtx
;
1727 accessor
.base_offset
= 0;
1728 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1729 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1730 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1734 /* Called after register allocation to add any instructions needed for the
1735 prologue. Using a prologue insn is favored compared to putting all of the
1736 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1737 it allows the scheduler to intermix instructions with the saves of
1738 the caller saved registers. In some cases, it might be necessary
1739 to emit a barrier instruction as the last insn to prevent such
1742 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1743 so that the debug info generation code can handle them properly. */
1745 frv_expand_prologue (void)
1747 frv_stack_t
*info
= frv_stack_info ();
1748 rtx sp
= stack_pointer_rtx
;
1749 rtx fp
= frame_pointer_rtx
;
1750 frv_frame_accessor_t accessor
;
1752 if (TARGET_DEBUG_STACK
)
1753 frv_debug_stack (info
);
1755 if (flag_stack_usage_info
)
1756 current_function_static_stack_size
= info
->total_size
;
1758 if (info
->total_size
== 0)
1761 /* We're interested in three areas of the frame here:
1763 A: the register save area
1765 C: the header after B
1767 If the frame pointer isn't used, we'll have to set up A, B and C
1768 using the stack pointer. If the frame pointer is used, we'll access
1772 B: set up using sp or a temporary (see below)
1775 We set up B using the stack pointer if the frame is small enough.
1776 Otherwise, it's more efficient to copy the old stack pointer into a
1777 temporary and use that.
1779 Note that it's important to make sure the prologue and epilogue use the
1780 same registers to access A and C, since doing otherwise will confuse
1781 the aliasing code. */
1783 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1784 isn't used, the same method will serve for C. */
1785 accessor
.op
= FRV_STORE
;
1786 if (frame_pointer_needed
&& info
->total_size
> 2048)
1788 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1789 accessor
.base_offset
= info
->total_size
;
1790 emit_insn (gen_movsi (accessor
.base
, sp
));
1794 accessor
.base
= stack_pointer_rtx
;
1795 accessor
.base_offset
= 0;
1798 /* Allocate the stack space. */
1800 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1801 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1803 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1804 gen_rtx_SET (sp
, gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1807 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1808 and point the new one to that location. */
1809 if (frame_pointer_needed
)
1811 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1813 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1814 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1816 rtx asm_src
= plus_constant (Pmode
, accessor
.base
,
1817 fp_offset
- accessor
.base_offset
);
1818 rtx dwarf_src
= plus_constant (Pmode
, sp
, fp_offset
);
1820 /* Store the old frame pointer at (sp + FP_OFFSET). */
1821 frv_frame_access (&accessor
, fp
, fp_offset
);
1823 /* Set up the new frame pointer. */
1824 frv_frame_insn (gen_rtx_SET (fp
, asm_src
),
1825 gen_rtx_SET (fp
, dwarf_src
));
1827 /* Access region C from the frame pointer. */
1829 accessor
.base_offset
= fp_offset
;
1832 /* Set up region C. */
1833 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1834 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1835 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1837 /* Set up region A. */
1838 frv_frame_access_standard_regs (FRV_STORE
, info
);
1840 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1841 scheduler from moving loads before the stores saving the registers. */
1842 if (info
->stdarg_size
> 0)
1843 emit_insn (gen_blockage ());
1845 /* Set up pic register/small data register for this function. */
1846 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
1847 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1848 gen_rtx_REG (Pmode
, LR_REGNO
),
1849 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1853 /* Under frv, all of the work is done via frv_expand_epilogue, but
1854 this function provides a convenient place to do cleanup. */
1857 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
1858 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1860 frv_stack_cache
= (frv_stack_t
*)0;
1862 /* Zap last used registers for conditional execution. */
1863 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1865 /* Release the bitmap of created insns. */
1866 BITMAP_FREE (frv_ifcvt
.scratch_insns_bitmap
);
1870 /* Called after register allocation to add any instructions needed for the
1871 epilogue. Using an epilogue insn is favored compared to putting all of the
1872 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1873 it allows the scheduler to intermix instructions with the saves of
1874 the caller saved registers. In some cases, it might be necessary
1875 to emit a barrier instruction as the last insn to prevent such
1879 frv_expand_epilogue (bool emit_return
)
1881 frv_stack_t
*info
= frv_stack_info ();
1882 rtx fp
= frame_pointer_rtx
;
1883 rtx sp
= stack_pointer_rtx
;
1887 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1889 /* Restore the stack pointer to its original value if alloca or the like
1891 if (! crtl
->sp_is_unchanging
)
1892 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1894 /* Restore the callee-saved registers that were used in this function. */
1895 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1897 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1898 no return instruction should be emitted. */
1899 if (info
->save_p
[LR_REGNO
])
1904 /* Use the same method to access the link register's slot as we did in
1905 the prologue. In other words, use the frame pointer if available,
1906 otherwise use the stack pointer.
1908 LR_OFFSET is the offset of the link register's slot from the start
1909 of the frame and MEM is a memory rtx for it. */
1910 lr_offset
= info
->reg_offset
[LR_REGNO
];
1911 if (frame_pointer_needed
)
1912 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1914 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1916 /* Load the old link register into a GPR. */
1917 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1918 emit_insn (gen_rtx_SET (return_addr
, mem
));
1921 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1923 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1924 the load is preserved. */
1925 if (frame_pointer_needed
)
1927 emit_insn (gen_rtx_SET (fp
, gen_rtx_MEM (Pmode
, fp
)));
1931 /* Deallocate the stack frame. */
1932 if (info
->total_size
!= 0)
1934 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1935 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1938 /* If this function uses eh_return, add the final stack adjustment now. */
1939 if (crtl
->calls_eh_return
)
1940 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1943 emit_jump_insn (gen_epilogue_return (return_addr
));
1946 rtx lr
= return_addr
;
1948 if (REGNO (return_addr
) != LR_REGNO
)
1950 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1951 emit_move_insn (lr
, return_addr
);
1959 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1962 frv_asm_output_mi_thunk (FILE *file
,
1963 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1964 HOST_WIDE_INT delta
,
1965 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1968 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1969 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1970 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1971 const char *parallel
= (frv_issue_rate () > 1 ? ".p" : "");
1973 /* Do the add using an addi if possible. */
1974 if (IN_RANGE (delta
, -2048, 2047))
1975 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1978 const char *const name_add
= reg_names
[TEMP_REGNO
];
1979 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1980 parallel
, delta
, name_add
);
1981 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1983 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1988 const char *name_pic
= reg_names
[FDPIC_REGNO
];
1989 name_jmp
= reg_names
[FDPIC_FPTR_REGNO
];
1993 fprintf (file
, "\tsethi%s #gotofffuncdeschi(", parallel
);
1994 assemble_name (file
, name_func
);
1995 fprintf (file
, "),%s\n", name_jmp
);
1997 fprintf (file
, "\tsetlo #gotofffuncdesclo(");
1998 assemble_name (file
, name_func
);
1999 fprintf (file
, "),%s\n", name_jmp
);
2001 fprintf (file
, "\tldd @(%s,%s), %s\n", name_jmp
, name_pic
, name_jmp
);
2005 fprintf (file
, "\tlddo @(%s,#gotofffuncdesc12(", name_pic
);
2006 assemble_name (file
, name_func
);
2007 fprintf (file
, "\t)), %s\n", name_jmp
);
2012 fprintf (file
, "\tsethi%s #hi(", parallel
);
2013 assemble_name (file
, name_func
);
2014 fprintf (file
, "),%s\n", name_jmp
);
2016 fprintf (file
, "\tsetlo #lo(");
2017 assemble_name (file
, name_func
);
2018 fprintf (file
, "),%s\n", name_jmp
);
2022 /* Use JUMP_REGNO as a temporary PIC register. */
2023 const char *name_lr
= reg_names
[LR_REGNO
];
2024 const char *name_gppic
= name_jmp
;
2025 const char *name_tmp
= reg_names
[TEMP_REGNO
];
2027 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
2028 fprintf (file
, "\tcall 1f\n");
2029 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
2030 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
2031 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
2032 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
2033 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
2035 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
2036 assemble_name (file
, name_func
);
2037 fprintf (file
, "),%s\n", name_tmp
);
2039 fprintf (file
, "\tsetlo #gprello(");
2040 assemble_name (file
, name_func
);
2041 fprintf (file
, "),%s\n", name_tmp
);
2043 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
2046 /* Jump to the function address. */
2047 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
2052 /* On frv, create a frame whenever we need to create stack. */
2055 frv_frame_pointer_required (void)
2057 /* If we forgoing the usual linkage requirements, we only need
2058 a frame pointer if the stack pointer might change. */
2059 if (!TARGET_LINKED_FP
)
2060 return !crtl
->sp_is_unchanging
;
2062 if (! crtl
->is_leaf
)
2065 if (get_frame_size () != 0)
2071 if (!crtl
->sp_is_unchanging
)
2074 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
2080 if (cfun
->machine
->frame_needed
)
2087 /* Worker function for TARGET_CAN_ELIMINATE. */
2090 frv_can_eliminate (const int from
, const int to
)
2092 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
2093 ? ! frame_pointer_needed
2097 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2098 initial difference between the specified pair of registers. This macro must
2099 be defined if `ELIMINABLE_REGS' is defined. */
2101 /* See frv_stack_info for more details on the frv stack frame. */
2104 frv_initial_elimination_offset (int from
, int to
)
2106 frv_stack_t
*info
= frv_stack_info ();
2109 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2110 ret
= info
->total_size
- info
->pretend_size
;
2112 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2113 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
2115 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2116 ret
= (info
->total_size
2117 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2118 - info
->pretend_size
);
2123 if (TARGET_DEBUG_STACK
)
2124 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2125 reg_names
[from
], reg_names
[to
], ret
);
2131 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2134 frv_setup_incoming_varargs (cumulative_args_t cum_v
,
2136 tree type ATTRIBUTE_UNUSED
,
2140 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2142 if (TARGET_DEBUG_ARG
)
2144 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2145 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2149 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2152 frv_expand_builtin_saveregs (void)
2154 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2156 if (TARGET_DEBUG_ARG
)
2157 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2160 return gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2164 /* Expand __builtin_va_start to do the va_start macro. */
2167 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
2170 int num
= crtl
->args
.info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2172 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2173 GEN_INT (UNITS_PER_WORD
* num
));
2175 if (TARGET_DEBUG_ARG
)
2177 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2178 crtl
->args
.info
, num
);
2180 debug_rtx (nextarg
);
2183 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2184 fold_convert (TREE_TYPE (valist
),
2185 make_tree (sizetype
, nextarg
)));
2186 TREE_SIDE_EFFECTS (t
) = 1;
2188 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2192 /* Expand a block move operation, and return 1 if successful. Return 0
2193 if we should let the compiler generate normal code.
2195 operands[0] is the destination
2196 operands[1] is the source
2197 operands[2] is the length
2198 operands[3] is the alignment */
2200 /* Maximum number of loads to do before doing the stores */
2201 #ifndef MAX_MOVE_REG
2202 #define MAX_MOVE_REG 4
2205 /* Maximum number of total loads to do. */
2206 #ifndef TOTAL_MOVE_REG
2207 #define TOTAL_MOVE_REG 8
2211 frv_expand_block_move (rtx operands
[])
2213 rtx orig_dest
= operands
[0];
2214 rtx orig_src
= operands
[1];
2215 rtx bytes_rtx
= operands
[2];
2216 rtx align_rtx
= operands
[3];
2217 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2230 rtx stores
[MAX_MOVE_REG
];
2234 /* If this is not a fixed size move, just call memcpy. */
2238 /* This should be a fixed size alignment. */
2239 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2241 align
= INTVAL (align_rtx
);
2243 /* Anything to move? */
2244 bytes
= INTVAL (bytes_rtx
);
2248 /* Don't support real large moves. */
2249 if (bytes
> TOTAL_MOVE_REG
*align
)
2252 /* Move the address into scratch registers. */
2253 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2254 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2256 num_reg
= offset
= 0;
2257 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2259 /* Calculate the correct offset for src/dest. */
2263 dest_addr
= dest_reg
;
2267 src_addr
= plus_constant (Pmode
, src_reg
, offset
);
2268 dest_addr
= plus_constant (Pmode
, dest_reg
, offset
);
2271 /* Generate the appropriate load and store, saving the stores
2273 if (bytes
>= 4 && align
>= 4)
2275 else if (bytes
>= 2 && align
>= 2)
2280 move_bytes
= GET_MODE_SIZE (mode
);
2281 tmp_reg
= gen_reg_rtx (mode
);
2282 src_mem
= change_address (orig_src
, mode
, src_addr
);
2283 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2284 emit_insn (gen_rtx_SET (tmp_reg
, src_mem
));
2285 stores
[num_reg
++] = gen_rtx_SET (dest_mem
, tmp_reg
);
2287 if (num_reg
>= MAX_MOVE_REG
)
2289 for (i
= 0; i
< num_reg
; i
++)
2290 emit_insn (stores
[i
]);
2295 for (i
= 0; i
< num_reg
; i
++)
2296 emit_insn (stores
[i
]);
2302 /* Expand a block clear operation, and return 1 if successful. Return 0
2303 if we should let the compiler generate normal code.
2305 operands[0] is the destination
2306 operands[1] is the length
2307 operands[3] is the alignment */
2310 frv_expand_block_clear (rtx operands
[])
2312 rtx orig_dest
= operands
[0];
2313 rtx bytes_rtx
= operands
[1];
2314 rtx align_rtx
= operands
[3];
2315 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2325 /* If this is not a fixed size move, just call memcpy. */
2329 /* This should be a fixed size alignment. */
2330 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2332 align
= INTVAL (align_rtx
);
2334 /* Anything to move? */
2335 bytes
= INTVAL (bytes_rtx
);
2339 /* Don't support real large clears. */
2340 if (bytes
> TOTAL_MOVE_REG
*align
)
2343 /* Move the address into a scratch register. */
2344 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2347 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2349 /* Calculate the correct offset for src/dest. */
2350 dest_addr
= ((offset
== 0)
2352 : plus_constant (Pmode
, dest_reg
, offset
));
2354 /* Generate the appropriate store of gr0. */
2355 if (bytes
>= 4 && align
>= 4)
2357 else if (bytes
>= 2 && align
>= 2)
2362 clear_bytes
= GET_MODE_SIZE (mode
);
2363 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2364 emit_insn (gen_rtx_SET (dest_mem
, const0_rtx
));
2371 /* The following variable is used to output modifiers of assembler
2372 code of the current output insn. */
2374 static rtx
*frv_insn_operands
;
2376 /* The following function is used to add assembler insn code suffix .p
2377 if it is necessary. */
2380 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2384 if (frv_insn_packing_flag
<= 0)
2387 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2390 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2391 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2393 int letter
= *ptr
++;
2396 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2397 while ((c
= *ptr
) >= '0' && c
<= '9')
2409 /* Set up the packing bit for the current output insn. Note that this
2410 function is not called for asm insns. */
2413 frv_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec
,
2414 int noperands ATTRIBUTE_UNUSED
)
2418 if (frv_insn_packing_flag
>= 0)
2420 frv_insn_operands
= opvec
;
2421 frv_insn_packing_flag
= PACKING_FLAG_P (insn
);
2423 else if (recog_memoized (insn
) >= 0
2424 && get_attr_acc_group (insn
) == ACC_GROUP_ODD
)
2425 /* Packing optimizations have been disabled, but INSN can only
2426 be issued in M1. Insert an mnop in M0. */
2427 fprintf (asm_out_file
, "\tmnop.p\n");
2433 /* A C expression whose value is RTL representing the address in a stack frame
2434 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2435 an RTL expression for the address of the stack frame itself.
2437 If you don't define this macro, the default is to return the value of
2438 FRAMEADDR--that is, the stack frame address is also the address of the stack
2439 word that points to the previous frame. */
2441 /* The default is correct, but we need to make sure the frame gets created. */
2443 frv_dynamic_chain_address (rtx frame
)
2445 cfun
->machine
->frame_needed
= 1;
2450 /* A C expression whose value is RTL representing the value of the return
2451 address for the frame COUNT steps up from the current frame, after the
2452 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2453 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2456 The value of the expression must always be the correct address when COUNT is
2457 zero, but may be `NULL_RTX' if there is not way to determine the return
2458 address of other frames. */
2461 frv_return_addr_rtx (int count
, rtx frame
)
2465 cfun
->machine
->frame_needed
= 1;
2466 return gen_rtx_MEM (Pmode
, plus_constant (Pmode
, frame
, 8));
2469 /* Given a memory reference MEMREF, interpret the referenced memory as
2470 an array of MODE values, and return a reference to the element
2471 specified by INDEX. Assume that any pre-modification implicit in
2472 MEMREF has already happened.
2474 MEMREF must be a legitimate operand for modes larger than SImode.
2475 frv_legitimate_address_p forbids register+register addresses, which
2476 this function cannot handle. */
2478 frv_index_memory (rtx memref
, machine_mode mode
, int index
)
2480 rtx base
= XEXP (memref
, 0);
2481 if (GET_CODE (base
) == PRE_MODIFY
)
2482 base
= XEXP (base
, 0);
2483 return change_address (memref
, mode
,
2484 plus_constant (Pmode
, base
,
2485 index
* GET_MODE_SIZE (mode
)));
2489 /* Print a memory address as an operand to reference that memory location. */
2491 frv_print_operand_address (FILE * stream
, rtx x
)
2493 if (GET_CODE (x
) == MEM
)
2496 switch (GET_CODE (x
))
2499 fputs (reg_names
[ REGNO (x
)], stream
);
2503 fprintf (stream
, "%ld", (long) INTVAL (x
));
2507 assemble_name (stream
, XSTR (x
, 0));
2512 output_addr_const (stream
, x
);
2516 /* Poorly constructed asm statements can trigger this alternative.
2517 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2518 frv_print_operand_memory_reference (stream
, x
, 0);
2525 fatal_insn ("bad insn to frv_print_operand_address:", x
);
2530 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2532 int regno
= true_regnum (x
);
2534 fputs (reg_names
[regno
], stream
);
2536 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x
);
2539 /* Print a memory reference suitable for the ld/st instructions. */
2542 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2544 struct frv_unspec unspec
;
2548 switch (GET_CODE (x
))
2555 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2557 x1
= XEXP (XEXP (x
, 1), 1);
2567 if (GET_CODE (x0
) == CONST_INT
)
2575 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2584 else if (GET_CODE (x1
) != CONST_INT
)
2585 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2588 fputs ("@(", stream
);
2590 fputs (reg_names
[GPR_R0
], stream
);
2591 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2592 frv_print_operand_memory_reference_reg (stream
, x0
);
2594 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2596 fputs (",", stream
);
2598 fputs (reg_names
[GPR_R0
], stream
);
2602 switch (GET_CODE (x1
))
2606 frv_print_operand_memory_reference_reg (stream
, x1
);
2610 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2614 if (!frv_const_unspec_p (x1
, &unspec
))
2615 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1
);
2616 frv_output_const_unspec (stream
, &unspec
);
2620 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2624 fputs (")", stream
);
2628 /* Return 2 for likely branches and 0 for non-likely branches */
2630 #define FRV_JUMP_LIKELY 2
2631 #define FRV_JUMP_NOT_LIKELY 0
2634 frv_print_operand_jump_hint (rtx_insn
*insn
)
2640 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2642 gcc_assert (JUMP_P (insn
));
2644 /* Assume any non-conditional jump is likely. */
2645 if (! any_condjump_p (insn
))
2646 ret
= FRV_JUMP_LIKELY
;
2650 labelref
= condjump_label (insn
);
2653 rtx label
= XEXP (labelref
, 0);
2654 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2659 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2661 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2665 prob
= XINT (note
, 0);
2666 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2668 : FRV_JUMP_NOT_LIKELY
);
2680 case UNKNOWN
: direction
= "unknown jump direction"; break;
2681 case BACKWARD
: direction
= "jump backward"; break;
2682 case FORWARD
: direction
= "jump forward"; break;
2686 "%s: uid %ld, %s, probability = %d, max prob. = %d, hint = %d\n",
2687 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2688 (long)INSN_UID (insn
), direction
, prob
,
2689 REG_BR_PROB_BASE
, ret
);
2697 /* Return the comparison operator to use for CODE given that the ICC
2701 comparison_string (enum rtx_code code
, rtx op0
)
2703 bool is_nz_p
= GET_MODE (op0
) == CC_NZmode
;
2706 default: output_operand_lossage ("bad condition code");
2707 case EQ
: return "eq";
2708 case NE
: return "ne";
2709 case LT
: return is_nz_p
? "n" : "lt";
2710 case LE
: return "le";
2711 case GT
: return "gt";
2712 case GE
: return is_nz_p
? "p" : "ge";
2713 case LTU
: return is_nz_p
? "no" : "c";
2714 case LEU
: return is_nz_p
? "eq" : "ls";
2715 case GTU
: return is_nz_p
? "ne" : "hi";
2716 case GEU
: return is_nz_p
? "ra" : "nc";
2720 /* Print an operand to an assembler instruction.
2722 `%' followed by a letter and a digit says to output an operand in an
2723 alternate fashion. Four letters have standard, built-in meanings
2724 described below. The hook `TARGET_PRINT_OPERAND' can define
2725 additional letters with nonstandard meanings.
2727 `%cDIGIT' can be used to substitute an operand that is a constant value
2728 without the syntax that normally indicates an immediate operand.
2730 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2733 `%aDIGIT' can be used to substitute an operand as if it were a memory
2734 reference, with the actual operand treated as the address. This may be
2735 useful when outputting a "load address" instruction, because often the
2736 assembler syntax for such an instruction requires you to write the operand
2737 as if it were a memory reference.
2739 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2741 `%=' outputs a number which is unique to each instruction in the entire
2742 compilation. This is useful for making local labels to be referred to more
2743 than once in a single template that generates multiple assembler
2746 `%' followed by a punctuation character specifies a substitution that
2747 does not use an operand. Only one case is standard: `%%' outputs a
2748 `%' into the assembler code. Other nonstandard cases can be defined
2749 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2750 punctuation characters are valid with the
2751 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2754 frv_print_operand (FILE * file
, rtx x
, int code
)
2756 struct frv_unspec unspec
;
2757 HOST_WIDE_INT value
;
2760 if (code
!= 0 && !ISALPHA (code
))
2763 else if (GET_CODE (x
) == CONST_INT
)
2766 else if (GET_CODE (x
) == CONST_DOUBLE
)
2768 if (GET_MODE (x
) == SFmode
)
2772 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
2776 else if (GET_MODE (x
) == VOIDmode
)
2777 value
= CONST_DOUBLE_LOW (x
);
2780 fatal_insn ("bad insn in frv_print_operand, bad const_double", x
);
2791 fputs (reg_names
[GPR_R0
], file
);
2795 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2799 /* Output small data area base register (gr16). */
2800 fputs (reg_names
[SDA_BASE_REG
], file
);
2804 /* Output pic register (gr17). */
2805 fputs (reg_names
[PIC_REGNO
], file
);
2809 /* Output the temporary integer CCR register. */
2810 fputs (reg_names
[ICR_TEMP
], file
);
2814 /* Output the temporary integer CC register. */
2815 fputs (reg_names
[ICC_TEMP
], file
);
2818 /* case 'a': print an address. */
2821 /* Print appropriate test for integer branch false operation. */
2822 fputs (comparison_string (reverse_condition (GET_CODE (x
)),
2823 XEXP (x
, 0)), file
);
2827 /* Print appropriate test for integer branch true operation. */
2828 fputs (comparison_string (GET_CODE (x
), XEXP (x
, 0)), file
);
2832 /* Print 1 for a NE and 0 for an EQ to give the final argument
2833 for a conditional instruction. */
2834 if (GET_CODE (x
) == NE
)
2837 else if (GET_CODE (x
) == EQ
)
2841 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x
);
2845 /* Print appropriate test for floating point branch false operation. */
2846 switch (GET_CODE (x
))
2849 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x
);
2851 case EQ
: fputs ("ne", file
); break;
2852 case NE
: fputs ("eq", file
); break;
2853 case LT
: fputs ("uge", file
); break;
2854 case LE
: fputs ("ug", file
); break;
2855 case GT
: fputs ("ule", file
); break;
2856 case GE
: fputs ("ul", file
); break;
2861 /* Print appropriate test for floating point branch true operation. */
2862 switch (GET_CODE (x
))
2865 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x
);
2867 case EQ
: fputs ("eq", file
); break;
2868 case NE
: fputs ("ne", file
); break;
2869 case LT
: fputs ("lt", file
); break;
2870 case LE
: fputs ("le", file
); break;
2871 case GT
: fputs ("gt", file
); break;
2872 case GE
: fputs ("ge", file
); break;
2877 /* Print appropriate GOT function. */
2878 if (GET_CODE (x
) != CONST_INT
)
2879 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x
);
2880 fputs (unspec_got_name (INTVAL (x
)), file
);
2884 /* Print 'i' if the operand is a constant, or is a memory reference that
2886 if (GET_CODE (x
) == MEM
)
2887 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2888 ? XEXP (XEXP (x
, 0), 1)
2890 else if (GET_CODE (x
) == PLUS
)
2893 switch (GET_CODE (x
))
2907 /* For jump instructions, print 'i' if the operand is a constant or
2908 is an expression that adds a constant. */
2909 if (GET_CODE (x
) == CONST_INT
)
2914 if (GET_CODE (x
) == CONST_INT
2915 || (GET_CODE (x
) == PLUS
2916 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2917 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2923 /* Print the lower register of a double word register pair */
2924 if (GET_CODE (x
) == REG
)
2925 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2927 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x
);
2930 /* case 'l': print a LABEL_REF. */
2934 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2935 for the second word of double memory operations. */
2936 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2937 switch (GET_CODE (x
))
2940 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x
);
2943 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2951 frv_print_operand_memory_reference (file
, x
, offset
);
2957 /* Print the opcode of a command. */
2958 switch (GET_CODE (x
))
2961 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x
);
2963 case PLUS
: fputs ("add", file
); break;
2964 case MINUS
: fputs ("sub", file
); break;
2965 case AND
: fputs ("and", file
); break;
2966 case IOR
: fputs ("or", file
); break;
2967 case XOR
: fputs ("xor", file
); break;
2968 case ASHIFT
: fputs ("sll", file
); break;
2969 case ASHIFTRT
: fputs ("sra", file
); break;
2970 case LSHIFTRT
: fputs ("srl", file
); break;
2974 /* case 'n': negate and print a constant int. */
2977 /* Print PIC label using operand as the number. */
2978 if (GET_CODE (x
) != CONST_INT
)
2979 fatal_insn ("bad insn to frv_print_operand, P modifier:", x
);
2981 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2985 /* Print 'u' if the operand is a update load/store. */
2986 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
2991 /* If value is 0, print gr0, otherwise it must be a register. */
2992 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
2993 fputs (reg_names
[GPR_R0
], file
);
2995 else if (GET_CODE (x
) == REG
)
2996 fputs (reg_names
[REGNO (x
)], file
);
2999 fatal_insn ("bad insn in frv_print_operand, z case", x
);
3003 /* Print constant in hex. */
3004 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3006 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
3013 if (GET_CODE (x
) == REG
)
3014 fputs (reg_names
[REGNO (x
)], file
);
3016 else if (GET_CODE (x
) == CONST_INT
3017 || GET_CODE (x
) == CONST_DOUBLE
)
3018 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
3020 else if (frv_const_unspec_p (x
, &unspec
))
3021 frv_output_const_unspec (file
, &unspec
);
3023 else if (GET_CODE (x
) == MEM
)
3024 frv_print_operand_address (file
, XEXP (x
, 0));
3026 else if (CONSTANT_ADDRESS_P (x
))
3027 frv_print_operand_address (file
, x
);
3030 fatal_insn ("bad insn in frv_print_operand, 0 case", x
);
3035 fatal_insn ("frv_print_operand: unknown code", x
);
3043 frv_print_operand_punct_valid_p (unsigned char code
)
3045 return (code
== '.' || code
== '#' || code
== '@' || code
== '~'
3046 || code
== '*' || code
== '&');
3050 /* A C statement (sans semicolon) for initializing the variable CUM for the
3051 state at the beginning of the argument list. The variable has type
3052 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3053 of the function which will receive the args, or 0 if the args are to a
3054 compiler support library function. The value of INDIRECT is nonzero when
3055 processing an indirect call, for example a call through a function pointer.
3056 The value of INDIRECT is zero for a call to an explicitly named function, a
3057 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3058 arguments for the function being compiled.
3060 When processing a call to a compiler support library function, LIBNAME
3061 identifies which one. It is a `symbol_ref' rtx which contains the name of
3062 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3063 being processed. Thus, each time this macro is called, either LIBNAME or
3064 FNTYPE is nonzero, but never both of them at once. */
3067 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
3073 *cum
= FIRST_ARG_REGNUM
;
3075 if (TARGET_DEBUG_ARG
)
3077 fprintf (stderr
, "\ninit_cumulative_args:");
3078 if (!fndecl
&& fntype
)
3079 fputs (" indirect", stderr
);
3082 fputs (" incoming", stderr
);
3086 tree ret_type
= TREE_TYPE (fntype
);
3087 fprintf (stderr
, " return=%s,",
3088 get_tree_code_name (TREE_CODE (ret_type
)));
3091 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3092 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3094 if (cfun
->returns_struct
)
3095 fprintf (stderr
, " return-struct");
3097 putc ('\n', stderr
);
3102 /* Return true if we should pass an argument on the stack rather than
3106 frv_must_pass_in_stack (machine_mode mode
, const_tree type
)
3108 if (mode
== BLKmode
)
3112 return AGGREGATE_TYPE_P (type
);
3115 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3116 argument with the specified mode and type. If it is not defined,
3117 `PARM_BOUNDARY' is used for all arguments. */
3120 frv_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED
,
3121 const_tree type ATTRIBUTE_UNUSED
)
3123 return BITS_PER_WORD
;
3127 frv_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
3128 const_tree type ATTRIBUTE_UNUSED
, bool named
,
3129 bool incoming ATTRIBUTE_UNUSED
)
3131 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3133 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3138 /* Return a marker for use in the call instruction. */
3139 if (xmode
== VOIDmode
)
3145 else if (arg_num
<= LAST_ARG_REGNUM
)
3147 ret
= gen_rtx_REG (xmode
, arg_num
);
3148 debstr
= reg_names
[arg_num
];
3157 if (TARGET_DEBUG_ARG
)
3159 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3160 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3166 frv_function_arg (cumulative_args_t cum
, machine_mode mode
,
3167 const_tree type
, bool named
)
3169 return frv_function_arg_1 (cum
, mode
, type
, named
, false);
3173 frv_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
3174 const_tree type
, bool named
)
3176 return frv_function_arg_1 (cum
, mode
, type
, named
, true);
3180 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3181 advance past an argument in the argument list. The values MODE, TYPE and
3182 NAMED describe that argument. Once this is done, the variable CUM is
3183 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3185 This macro need not do anything if the argument in question was passed on
3186 the stack. The compiler knows how to track the amount of stack space used
3187 for arguments without any special help. */
3190 frv_function_arg_advance (cumulative_args_t cum_v
,
3192 const_tree type ATTRIBUTE_UNUSED
,
3195 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3197 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3198 int bytes
= GET_MODE_SIZE (xmode
);
3199 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3202 *cum
= arg_num
+ words
;
3204 if (TARGET_DEBUG_ARG
)
3206 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3207 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3211 /* A C expression for the number of words, at the beginning of an argument,
3212 must be put in registers. The value must be zero for arguments that are
3213 passed entirely in registers or that are entirely pushed on the stack.
3215 On some machines, certain arguments must be passed partially in registers
3216 and partially in memory. On these machines, typically the first N words of
3217 arguments are passed in registers, and the rest on the stack. If a
3218 multi-word argument (a `double' or a structure) crosses that boundary, its
3219 first few words must be passed in registers and the rest must be pushed.
3220 This macro tells the compiler when this occurs, and how many of the words
3221 should go in registers.
3223 `FUNCTION_ARG' for these arguments should return the first register to be
3224 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3225 the called function. */
3228 frv_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
3229 tree type ATTRIBUTE_UNUSED
, bool named ATTRIBUTE_UNUSED
)
3232 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3233 int bytes
= GET_MODE_SIZE (xmode
);
3234 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3235 int arg_num
= *get_cumulative_args (cum
);
3238 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3239 ? LAST_ARG_REGNUM
- arg_num
+ 1
3241 ret
*= UNITS_PER_WORD
;
3243 if (TARGET_DEBUG_ARG
&& ret
)
3244 fprintf (stderr
, "frv_arg_partial_bytes: %d\n", ret
);
3250 /* Implements TARGET_FUNCTION_VALUE. */
3253 frv_function_value (const_tree valtype
,
3254 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
3255 bool outgoing ATTRIBUTE_UNUSED
)
3257 return gen_rtx_REG (TYPE_MODE (valtype
), RETURN_VALUE_REGNUM
);
3261 /* Implements TARGET_LIBCALL_VALUE. */
3264 frv_libcall_value (machine_mode mode
,
3265 const_rtx fun ATTRIBUTE_UNUSED
)
3267 return gen_rtx_REG (mode
, RETURN_VALUE_REGNUM
);
3271 /* Implements FUNCTION_VALUE_REGNO_P. */
3274 frv_function_value_regno_p (const unsigned int regno
)
3276 return (regno
== RETURN_VALUE_REGNUM
);
3279 /* Return true if a register is ok to use as a base or index register. */
3281 static FRV_INLINE
int
3282 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3288 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3290 if (regno
== ARG_POINTER_REGNUM
)
3293 return (regno
>= FIRST_PSEUDO_REGISTER
);
3297 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3298 RTX) is a legitimate memory address on the target machine for a memory
3299 operand of mode MODE.
3301 It usually pays to define several simpler macros to serve as subroutines for
3302 this one. Otherwise it may be too complicated to understand.
3304 This macro must exist in two variants: a strict variant and a non-strict
3305 one. The strict variant is used in the reload pass. It must be defined so
3306 that any pseudo-register that has not been allocated a hard register is
3307 considered a memory reference. In contexts where some kind of register is
3308 required, a pseudo-register with no hard register must be rejected.
3310 The non-strict variant is used in other passes. It must be defined to
3311 accept all pseudo-registers in every context where some kind of register is
3314 Compiler source files that want to use the strict variant of this macro
3315 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3316 conditional to define the strict variant in that case and the non-strict
3319 Normally, constant addresses which are the sum of a `symbol_ref' and an
3320 integer are stored inside a `const' RTX to mark them as constant.
3321 Therefore, there is no need to recognize such sums specifically as
3322 legitimate addresses. Normally you would simply recognize any `const' as
3325 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3326 constant sums that are not marked with `const'. It assumes that a
3327 naked `plus' indicates indexing. If so, then you *must* reject such
3328 naked constant sums as illegitimate addresses, so that none of them
3329 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3332 frv_legitimate_address_p_1 (machine_mode mode
,
3336 int allow_double_reg_p
)
3340 HOST_WIDE_INT value
;
3343 if (FRV_SYMBOL_REF_TLS_P (x
))
3346 switch (GET_CODE (x
))
3353 if (GET_CODE (x
) != REG
)
3359 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3365 if (GET_CODE (x0
) != REG
3366 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3367 || GET_CODE (x1
) != PLUS
3368 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3369 || GET_CODE (XEXP (x1
, 1)) != REG
3370 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3377 /* 12-bit immediate */
3382 ret
= IN_RANGE (INTVAL (x
), -2048, 2047);
3384 /* If we can't use load/store double operations, make sure we can
3385 address the second word. */
3386 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3387 ret
= IN_RANGE (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3396 if (GET_CODE (x0
) == SUBREG
)
3397 x0
= SUBREG_REG (x0
);
3399 if (GET_CODE (x0
) != REG
)
3402 regno0
= REGNO (x0
);
3403 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3406 switch (GET_CODE (x1
))
3412 x1
= SUBREG_REG (x1
);
3413 if (GET_CODE (x1
) != REG
)
3419 /* Do not allow reg+reg addressing for modes > 1 word if we
3420 can't depend on having move double instructions. */
3421 if (!allow_double_reg_p
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3424 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3428 /* 12-bit immediate */
3433 value
= INTVAL (x1
);
3434 ret
= IN_RANGE (value
, -2048, 2047);
3436 /* If we can't use load/store double operations, make sure we can
3437 address the second word. */
3438 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3439 ret
= IN_RANGE (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3444 if (!condexec_p
&& got12_operand (x1
, VOIDmode
))
3452 if (TARGET_DEBUG_ADDR
)
3454 fprintf (stderr
, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3455 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3456 (condexec_p
) ? ", inside conditional code" : "");
3464 frv_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
3466 return frv_legitimate_address_p_1 (mode
, x
, strict_p
, FALSE
, FALSE
);
3469 /* Given an ADDR, generate code to inline the PLT. */
3471 gen_inlined_tls_plt (rtx addr
)
3474 rtx picreg
= get_hard_reg_initial_val (Pmode
, FDPIC_REG
);
3477 dest
= gen_reg_rtx (DImode
);
3484 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3485 calll #gettlsoff(ADDR)@(gr8, gr0)
3487 emit_insn (gen_tls_lddi (dest
, addr
, picreg
));
3494 sethi.p #gottlsdeschi(ADDR), gr8
3495 setlo #gottlsdesclo(ADDR), gr8
3496 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3497 calll #gettlsoff(ADDR)@(gr8, gr0)
3499 rtx reguse
= gen_reg_rtx (Pmode
);
3500 emit_insn (gen_tlsoff_hilo (reguse
, addr
, GEN_INT (R_FRV_GOTTLSDESCHI
)));
3501 emit_insn (gen_tls_tlsdesc_ldd (dest
, picreg
, reguse
, addr
));
3504 retval
= gen_reg_rtx (Pmode
);
3505 emit_insn (gen_tls_indirect_call (retval
, addr
, dest
, picreg
));
3509 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3510 the destination address. */
3512 gen_tlsmoff (rtx addr
, rtx reg
)
3514 rtx dest
= gen_reg_rtx (Pmode
);
3518 /* sethi.p #tlsmoffhi(x), grA
3519 setlo #tlsmofflo(x), grA
3521 dest
= gen_reg_rtx (Pmode
);
3522 emit_insn (gen_tlsoff_hilo (dest
, addr
,
3523 GEN_INT (R_FRV_TLSMOFFHI
)));
3524 dest
= gen_rtx_PLUS (Pmode
, dest
, reg
);
3528 /* addi grB, #tlsmoff12(x), grC
3530 ld/st @(grB, #tlsmoff12(x)), grC
3532 dest
= gen_reg_rtx (Pmode
);
3533 emit_insn (gen_symGOTOFF2reg_i (dest
, addr
, reg
,
3534 GEN_INT (R_FRV_TLSMOFF12
)));
3539 /* Generate code for a TLS address. */
3541 frv_legitimize_tls_address (rtx addr
, enum tls_model model
)
3543 rtx dest
, tp
= gen_rtx_REG (Pmode
, 29);
3544 rtx picreg
= get_hard_reg_initial_val (Pmode
, 15);
3548 case TLS_MODEL_INITIAL_EXEC
:
3552 ldi @(gr15, #gottlsoff12(x)), gr5
3554 dest
= gen_reg_rtx (Pmode
);
3555 emit_insn (gen_tls_load_gottlsoff12 (dest
, addr
, picreg
));
3556 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3560 /* -fPIC or anything else.
3562 sethi.p #gottlsoffhi(x), gr14
3563 setlo #gottlsofflo(x), gr14
3564 ld #tlsoff(x)@(gr15, gr14), gr9
3566 rtx tmp
= gen_reg_rtx (Pmode
);
3567 dest
= gen_reg_rtx (Pmode
);
3568 emit_insn (gen_tlsoff_hilo (tmp
, addr
,
3569 GEN_INT (R_FRV_GOTTLSOFF_HI
)));
3571 emit_insn (gen_tls_tlsoff_ld (dest
, picreg
, tmp
, addr
));
3572 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3575 case TLS_MODEL_LOCAL_DYNAMIC
:
3579 if (TARGET_INLINE_PLT
)
3580 retval
= gen_inlined_tls_plt (GEN_INT (0));
3583 /* call #gettlsoff(0) */
3584 retval
= gen_reg_rtx (Pmode
);
3585 emit_insn (gen_call_gettlsoff (retval
, GEN_INT (0), picreg
));
3588 reg
= gen_reg_rtx (Pmode
);
3589 emit_insn (gen_rtx_SET (reg
, gen_rtx_PLUS (Pmode
, retval
, tp
)));
3591 dest
= gen_tlsmoff (addr
, reg
);
3594 dest = gen_reg_rtx (Pmode);
3595 emit_insn (gen_tlsoff_hilo (dest, addr,
3596 GEN_INT (R_FRV_TLSMOFFHI)));
3597 dest = gen_rtx_PLUS (Pmode, dest, reg);
3601 case TLS_MODEL_LOCAL_EXEC
:
3602 dest
= gen_tlsmoff (addr
, gen_rtx_REG (Pmode
, 29));
3604 case TLS_MODEL_GLOBAL_DYNAMIC
:
3608 if (TARGET_INLINE_PLT
)
3609 retval
= gen_inlined_tls_plt (addr
);
3612 /* call #gettlsoff(x) */
3613 retval
= gen_reg_rtx (Pmode
);
3614 emit_insn (gen_call_gettlsoff (retval
, addr
, picreg
));
3616 dest
= gen_rtx_PLUS (Pmode
, retval
, tp
);
3627 frv_legitimize_address (rtx x
,
3628 rtx oldx ATTRIBUTE_UNUSED
,
3629 machine_mode mode ATTRIBUTE_UNUSED
)
3631 if (GET_CODE (x
) == SYMBOL_REF
)
3633 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3635 return frv_legitimize_tls_address (x
, model
);
3641 /* Test whether a local function descriptor is canonical, i.e.,
3642 whether we can use FUNCDESC_GOTOFF to compute the address of the
3646 frv_local_funcdesc_p (rtx fnx
)
3649 enum symbol_visibility vis
;
3652 if (! SYMBOL_REF_LOCAL_P (fnx
))
3655 fn
= SYMBOL_REF_DECL (fnx
);
3660 vis
= DECL_VISIBILITY (fn
);
3662 if (vis
== VISIBILITY_PROTECTED
)
3663 /* Private function descriptors for protected functions are not
3664 canonical. Temporarily change the visibility to global. */
3665 vis
= VISIBILITY_DEFAULT
;
3666 else if (flag_shlib
)
3667 /* If we're already compiling for a shared library (that, unlike
3668 executables, can't assume that the existence of a definition
3669 implies local binding), we can skip the re-testing. */
3672 ret
= default_binds_local_p_1 (fn
, flag_pic
);
3674 DECL_VISIBILITY (fn
) = vis
;
3679 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3683 frv_gen_GPsym2reg (rtx dest
, rtx src
)
3685 tree gp
= get_identifier ("_gp");
3686 rtx gp_sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (gp
));
3688 return gen_symGOT2reg (dest
, gp_sym
, src
, GEN_INT (R_FRV_GOT12
));
3692 unspec_got_name (int i
)
3696 case R_FRV_GOT12
: return "got12";
3697 case R_FRV_GOTHI
: return "gothi";
3698 case R_FRV_GOTLO
: return "gotlo";
3699 case R_FRV_FUNCDESC
: return "funcdesc";
3700 case R_FRV_FUNCDESC_GOT12
: return "gotfuncdesc12";
3701 case R_FRV_FUNCDESC_GOTHI
: return "gotfuncdeschi";
3702 case R_FRV_FUNCDESC_GOTLO
: return "gotfuncdesclo";
3703 case R_FRV_FUNCDESC_VALUE
: return "funcdescvalue";
3704 case R_FRV_FUNCDESC_GOTOFF12
: return "gotofffuncdesc12";
3705 case R_FRV_FUNCDESC_GOTOFFHI
: return "gotofffuncdeschi";
3706 case R_FRV_FUNCDESC_GOTOFFLO
: return "gotofffuncdesclo";
3707 case R_FRV_GOTOFF12
: return "gotoff12";
3708 case R_FRV_GOTOFFHI
: return "gotoffhi";
3709 case R_FRV_GOTOFFLO
: return "gotofflo";
3710 case R_FRV_GPREL12
: return "gprel12";
3711 case R_FRV_GPRELHI
: return "gprelhi";
3712 case R_FRV_GPRELLO
: return "gprello";
3713 case R_FRV_GOTTLSOFF_HI
: return "gottlsoffhi";
3714 case R_FRV_GOTTLSOFF_LO
: return "gottlsofflo";
3715 case R_FRV_TLSMOFFHI
: return "tlsmoffhi";
3716 case R_FRV_TLSMOFFLO
: return "tlsmofflo";
3717 case R_FRV_TLSMOFF12
: return "tlsmoff12";
3718 case R_FRV_TLSDESCHI
: return "tlsdeschi";
3719 case R_FRV_TLSDESCLO
: return "tlsdesclo";
3720 case R_FRV_GOTTLSDESCHI
: return "gottlsdeschi";
3721 case R_FRV_GOTTLSDESCLO
: return "gottlsdesclo";
3722 default: gcc_unreachable ();
3726 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3727 is added inside the relocation operator. */
3730 frv_output_const_unspec (FILE *stream
, const struct frv_unspec
*unspec
)
3732 fprintf (stream
, "#%s(", unspec_got_name (unspec
->reloc
));
3733 output_addr_const (stream
, plus_constant (Pmode
, unspec
->symbol
,
3735 fputs (")", stream
);
3738 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3739 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3740 otherwise return ORIG_X. */
3743 frv_find_base_term (rtx x
)
3745 struct frv_unspec unspec
;
3747 if (frv_const_unspec_p (x
, &unspec
)
3748 && frv_small_data_reloc_p (unspec
.symbol
, unspec
.reloc
))
3749 return plus_constant (Pmode
, unspec
.symbol
, unspec
.offset
);
3754 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3755 the operand is used by a predicated instruction. */
3758 frv_legitimate_memory_operand (rtx op
, machine_mode mode
, int condexec_p
)
3760 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3761 && GET_CODE (op
) == MEM
3762 && frv_legitimate_address_p_1 (mode
, XEXP (op
, 0),
3763 reload_completed
, condexec_p
, FALSE
));
3767 frv_expand_fdpic_call (rtx
*operands
, bool ret_value
, bool sibcall
)
3769 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
3770 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REG
);
3776 rvrtx
= operands
[0];
3780 addr
= XEXP (operands
[0], 0);
3782 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3783 any calls that would involve a PLT, but can't tell, since we
3784 don't know whether an extern function is going to be provided by
3785 a separate translation unit or imported from a separate module.
3786 When compiling for shared libraries, if the function has default
3787 visibility, we assume it's overridable, so we inline the PLT, but
3788 for executables, we don't really have a way to make a good
3789 decision: a function is as likely to be imported from a shared
3790 library as it is to be defined in the executable itself. We
3791 assume executables will get global functions defined locally,
3792 whereas shared libraries will have them potentially overridden,
3793 so we only inline PLTs when compiling for shared libraries.
3795 In order to mark a function as local to a shared library, any
3796 non-default visibility attribute suffices. Unfortunately,
3797 there's no simple way to tag a function declaration as ``in a
3798 different module'', which we could then use to trigger PLT
3799 inlining on executables. There's -minline-plt, but it affects
3800 all external functions, so one would have to also mark function
3801 declarations available in the same module with non-default
3802 visibility, which is advantageous in itself. */
3803 if (GET_CODE (addr
) == SYMBOL_REF
3804 && ((!SYMBOL_REF_LOCAL_P (addr
) && TARGET_INLINE_PLT
)
3808 dest
= gen_reg_rtx (SImode
);
3810 x
= gen_symGOTOFF2reg_hilo (dest
, addr
, OUR_FDPIC_REG
,
3811 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3813 x
= gen_symGOTOFF2reg (dest
, addr
, OUR_FDPIC_REG
,
3814 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3816 crtl
->uses_pic_offset_table
= TRUE
;
3819 else if (GET_CODE (addr
) == SYMBOL_REF
)
3821 /* These are always either local, or handled through a local
3824 c
= gen_call_value_fdpicsi (rvrtx
, addr
, operands
[1],
3825 operands
[2], picreg
, lr
);
3827 c
= gen_call_fdpicsi (addr
, operands
[1], operands
[2], picreg
, lr
);
3831 else if (! ldd_address_operand (addr
, Pmode
))
3832 addr
= force_reg (Pmode
, addr
);
3834 picreg
= gen_reg_rtx (DImode
);
3835 emit_insn (gen_movdi_ldd (picreg
, addr
));
3837 if (sibcall
&& ret_value
)
3838 c
= gen_sibcall_value_fdpicdi (rvrtx
, picreg
, const0_rtx
);
3840 c
= gen_sibcall_fdpicdi (picreg
, const0_rtx
);
3842 c
= gen_call_value_fdpicdi (rvrtx
, picreg
, const0_rtx
, lr
);
3844 c
= gen_call_fdpicdi (picreg
, const0_rtx
, lr
);
3848 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3849 process these separately from any offsets, such that we add any
3850 offsets to the function descriptor (the actual pointer), not to the
3851 function address. */
3854 frv_function_symbol_referenced_p (rtx x
)
3860 if (GET_CODE (x
) == SYMBOL_REF
)
3861 return SYMBOL_REF_FUNCTION_P (x
);
3863 length
= GET_RTX_LENGTH (GET_CODE (x
));
3864 format
= GET_RTX_FORMAT (GET_CODE (x
));
3866 for (j
= 0; j
< length
; ++j
)
3871 if (frv_function_symbol_referenced_p (XEXP (x
, j
)))
3877 if (XVEC (x
, j
) != 0)
3880 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
3881 if (frv_function_symbol_referenced_p (XVECEXP (x
, j
, k
)))
3887 /* Nothing to do. */
3895 /* Return true if the memory operand is one that can be conditionally
3899 condexec_memory_operand (rtx op
, machine_mode mode
)
3901 machine_mode op_mode
= GET_MODE (op
);
3904 if (mode
!= VOIDmode
&& op_mode
!= mode
)
3919 if (GET_CODE (op
) != MEM
)
3922 addr
= XEXP (op
, 0);
3923 return frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
);
3926 /* Return true if the bare return instruction can be used outside of the
3927 epilog code. For frv, we only do it if there was no stack allocation. */
3930 direct_return_p (void)
3934 if (!reload_completed
)
3937 info
= frv_stack_info ();
3938 return (info
->total_size
== 0);
3943 frv_emit_move (machine_mode mode
, rtx dest
, rtx src
)
3945 if (GET_CODE (src
) == SYMBOL_REF
)
3947 enum tls_model model
= SYMBOL_REF_TLS_MODEL (src
);
3949 src
= frv_legitimize_tls_address (src
, model
);
3955 if (frv_emit_movsi (dest
, src
))
3964 if (!reload_in_progress
3965 && !reload_completed
3966 && !register_operand (dest
, mode
)
3967 && !reg_or_0_operand (src
, mode
))
3968 src
= copy_to_mode_reg (mode
, src
);
3975 emit_insn (gen_rtx_SET (dest
, src
));
3978 /* Emit code to handle a MOVSI, adding in the small data register or pic
3979 register if needed to load up addresses. Return TRUE if the appropriate
3980 instructions are emitted. */
3983 frv_emit_movsi (rtx dest
, rtx src
)
3985 int base_regno
= -1;
3988 struct frv_unspec old_unspec
;
3990 if (!reload_in_progress
3991 && !reload_completed
3992 && !register_operand (dest
, SImode
)
3993 && (!reg_or_0_operand (src
, SImode
)
3994 /* Virtual registers will almost always be replaced by an
3995 add instruction, so expose this to CSE by copying to
3996 an intermediate register. */
3997 || (GET_CODE (src
) == REG
3998 && IN_RANGE (REGNO (src
),
3999 FIRST_VIRTUAL_REGISTER
,
4000 LAST_VIRTUAL_POINTER_REGISTER
))))
4002 emit_insn (gen_rtx_SET (dest
, copy_to_mode_reg (SImode
, src
)));
4006 /* Explicitly add in the PIC or small data register if needed. */
4007 switch (GET_CODE (src
))
4016 /* Using GPREL12, we use a single GOT entry for all symbols
4017 in read-only sections, but trade sequences such as:
4019 sethi #gothi(label), gr#
4020 setlo #gotlo(label), gr#
4025 ld @(gr15,#got12(_gp)), gr#
4026 sethi #gprelhi(label), gr##
4027 setlo #gprello(label), gr##
4030 We may often be able to share gr# for multiple
4031 computations of GPREL addresses, and we may often fold
4032 the final add into the pair of registers of a load or
4033 store instruction, so it's often profitable. Even when
4034 optimizing for size, we're trading a GOT entry for an
4035 additional instruction, which trades GOT space
4036 (read-write) for code size (read-only, shareable), as
4037 long as the symbol is not used in more than two different
4040 With -fpie/-fpic, we'd be trading a single load for a
4041 sequence of 4 instructions, because the offset of the
4042 label can't be assumed to be addressable with 12 bits, so
4043 we don't do this. */
4044 if (TARGET_GPREL_RO
)
4045 unspec
= R_FRV_GPREL12
;
4047 unspec
= R_FRV_GOT12
;
4050 base_regno
= PIC_REGNO
;
4055 if (frv_const_unspec_p (src
, &old_unspec
))
4058 if (TARGET_FDPIC
&& frv_function_symbol_referenced_p (XEXP (src
, 0)))
4061 src
= force_reg (GET_MODE (XEXP (src
, 0)), XEXP (src
, 0));
4062 emit_move_insn (dest
, src
);
4067 sym
= XEXP (sym
, 0);
4068 if (GET_CODE (sym
) == PLUS
4069 && GET_CODE (XEXP (sym
, 0)) == SYMBOL_REF
4070 && GET_CODE (XEXP (sym
, 1)) == CONST_INT
)
4071 sym
= XEXP (sym
, 0);
4072 if (GET_CODE (sym
) == SYMBOL_REF
)
4074 else if (GET_CODE (sym
) == LABEL_REF
)
4077 goto handle_whatever
;
4085 enum tls_model model
= SYMBOL_REF_TLS_MODEL (sym
);
4089 src
= frv_legitimize_tls_address (src
, model
);
4090 emit_move_insn (dest
, src
);
4094 if (SYMBOL_REF_FUNCTION_P (sym
))
4096 if (frv_local_funcdesc_p (sym
))
4097 unspec
= R_FRV_FUNCDESC_GOTOFF12
;
4099 unspec
= R_FRV_FUNCDESC_GOT12
;
4103 if (CONSTANT_POOL_ADDRESS_P (sym
))
4104 switch (GET_CODE (get_pool_constant (sym
)))
4111 unspec
= R_FRV_GOTOFF12
;
4116 if (TARGET_GPREL_RO
)
4117 unspec
= R_FRV_GPREL12
;
4119 unspec
= R_FRV_GOT12
;
4122 else if (SYMBOL_REF_LOCAL_P (sym
)
4123 && !SYMBOL_REF_EXTERNAL_P (sym
)
4124 && SYMBOL_REF_DECL (sym
)
4125 && (!DECL_P (SYMBOL_REF_DECL (sym
))
4126 || !DECL_COMMON (SYMBOL_REF_DECL (sym
))))
4128 tree decl
= SYMBOL_REF_DECL (sym
);
4129 tree init
= TREE_CODE (decl
) == VAR_DECL
4130 ? DECL_INITIAL (decl
)
4131 : TREE_CODE (decl
) == CONSTRUCTOR
4134 bool named_section
, readonly
;
4136 if (init
&& init
!= error_mark_node
)
4137 reloc
= compute_reloc_for_constant (init
);
4139 named_section
= TREE_CODE (decl
) == VAR_DECL
4140 && lookup_attribute ("section", DECL_ATTRIBUTES (decl
));
4141 readonly
= decl_readonly_section (decl
, reloc
);
4144 unspec
= R_FRV_GOT12
;
4146 unspec
= R_FRV_GOTOFF12
;
4147 else if (readonly
&& TARGET_GPREL_RO
)
4148 unspec
= R_FRV_GPREL12
;
4150 unspec
= R_FRV_GOT12
;
4153 unspec
= R_FRV_GOT12
;
4157 else if (SYMBOL_REF_SMALL_P (sym
))
4158 base_regno
= SDA_BASE_REG
;
4161 base_regno
= PIC_REGNO
;
4166 if (base_regno
>= 0)
4168 if (GET_CODE (sym
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (sym
))
4169 emit_insn (gen_symGOTOFF2reg (dest
, src
,
4170 gen_rtx_REG (Pmode
, base_regno
),
4171 GEN_INT (R_FRV_GPREL12
)));
4173 emit_insn (gen_symGOTOFF2reg_hilo (dest
, src
,
4174 gen_rtx_REG (Pmode
, base_regno
),
4175 GEN_INT (R_FRV_GPREL12
)));
4176 if (base_regno
== PIC_REGNO
)
4177 crtl
->uses_pic_offset_table
= TRUE
;
4185 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4186 new uses of it once reload has begun. */
4187 gcc_assert (!reload_in_progress
&& !reload_completed
);
4191 case R_FRV_GOTOFF12
:
4192 if (!frv_small_data_reloc_p (sym
, unspec
))
4193 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4196 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4199 if (!frv_small_data_reloc_p (sym
, unspec
))
4200 x
= gen_symGPREL2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4203 x
= gen_symGPREL2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4205 case R_FRV_FUNCDESC_GOTOFF12
:
4207 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4210 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4214 x
= gen_symGOT2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4217 x
= gen_symGOT2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4221 crtl
->uses_pic_offset_table
= TRUE
;
4230 /* Return a string to output a single word move. */
4233 output_move_single (rtx operands
[], rtx insn
)
4235 rtx dest
= operands
[0];
4236 rtx src
= operands
[1];
4238 if (GET_CODE (dest
) == REG
)
4240 int dest_regno
= REGNO (dest
);
4241 machine_mode mode
= GET_MODE (dest
);
4243 if (GPR_P (dest_regno
))
4245 if (GET_CODE (src
) == REG
)
4247 /* gpr <- some sort of register */
4248 int src_regno
= REGNO (src
);
4250 if (GPR_P (src_regno
))
4251 return "mov %1, %0";
4253 else if (FPR_P (src_regno
))
4254 return "movfg %1, %0";
4256 else if (SPR_P (src_regno
))
4257 return "movsg %1, %0";
4260 else if (GET_CODE (src
) == MEM
)
4269 return "ldsb%I1%U1 %M1,%0";
4272 return "ldsh%I1%U1 %M1,%0";
4276 return "ld%I1%U1 %M1, %0";
4280 else if (GET_CODE (src
) == CONST_INT
4281 || GET_CODE (src
) == CONST_DOUBLE
)
4283 /* gpr <- integer/floating constant */
4284 HOST_WIDE_INT value
;
4286 if (GET_CODE (src
) == CONST_INT
)
4287 value
= INTVAL (src
);
4289 else if (mode
== SFmode
)
4293 REAL_VALUE_TO_TARGET_SINGLE
4294 (*CONST_DOUBLE_REAL_VALUE (src
), l
);
4299 value
= CONST_DOUBLE_LOW (src
);
4301 if (IN_RANGE (value
, -32768, 32767))
4302 return "setlos %1, %0";
4307 else if (GET_CODE (src
) == SYMBOL_REF
4308 || GET_CODE (src
) == LABEL_REF
4309 || GET_CODE (src
) == CONST
)
4315 else if (FPR_P (dest_regno
))
4317 if (GET_CODE (src
) == REG
)
4319 /* fpr <- some sort of register */
4320 int src_regno
= REGNO (src
);
4322 if (GPR_P (src_regno
))
4323 return "movgf %1, %0";
4325 else if (FPR_P (src_regno
))
4327 if (TARGET_HARD_FLOAT
)
4328 return "fmovs %1, %0";
4330 return "mor %1, %1, %0";
4334 else if (GET_CODE (src
) == MEM
)
4343 return "ldbf%I1%U1 %M1,%0";
4346 return "ldhf%I1%U1 %M1,%0";
4350 return "ldf%I1%U1 %M1, %0";
4354 else if (ZERO_P (src
))
4355 return "movgf %., %0";
4358 else if (SPR_P (dest_regno
))
4360 if (GET_CODE (src
) == REG
)
4362 /* spr <- some sort of register */
4363 int src_regno
= REGNO (src
);
4365 if (GPR_P (src_regno
))
4366 return "movgs %1, %0";
4368 else if (ZERO_P (src
))
4369 return "movgs %., %0";
4373 else if (GET_CODE (dest
) == MEM
)
4375 if (GET_CODE (src
) == REG
)
4377 int src_regno
= REGNO (src
);
4378 machine_mode mode
= GET_MODE (dest
);
4380 if (GPR_P (src_regno
))
4388 return "stb%I0%U0 %1, %M0";
4391 return "sth%I0%U0 %1, %M0";
4395 return "st%I0%U0 %1, %M0";
4399 else if (FPR_P (src_regno
))
4407 return "stbf%I0%U0 %1, %M0";
4410 return "sthf%I0%U0 %1, %M0";
4414 return "stf%I0%U0 %1, %M0";
4419 else if (ZERO_P (src
))
4421 switch (GET_MODE (dest
))
4427 return "stb%I0%U0 %., %M0";
4430 return "sth%I0%U0 %., %M0";
4434 return "st%I0%U0 %., %M0";
4439 fatal_insn ("bad output_move_single operand", insn
);
4444 /* Return a string to output a double word move. */
4447 output_move_double (rtx operands
[], rtx insn
)
4449 rtx dest
= operands
[0];
4450 rtx src
= operands
[1];
4451 machine_mode mode
= GET_MODE (dest
);
4453 if (GET_CODE (dest
) == REG
)
4455 int dest_regno
= REGNO (dest
);
4457 if (GPR_P (dest_regno
))
4459 if (GET_CODE (src
) == REG
)
4461 /* gpr <- some sort of register */
4462 int src_regno
= REGNO (src
);
4464 if (GPR_P (src_regno
))
4467 else if (FPR_P (src_regno
))
4469 if (((dest_regno
- GPR_FIRST
) & 1) == 0
4470 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4471 return "movfgd %1, %0";
4477 else if (GET_CODE (src
) == MEM
)
4480 if (dbl_memory_one_insn_operand (src
, mode
))
4481 return "ldd%I1%U1 %M1, %0";
4486 else if (GET_CODE (src
) == CONST_INT
4487 || GET_CODE (src
) == CONST_DOUBLE
)
4491 else if (FPR_P (dest_regno
))
4493 if (GET_CODE (src
) == REG
)
4495 /* fpr <- some sort of register */
4496 int src_regno
= REGNO (src
);
4498 if (GPR_P (src_regno
))
4500 if (((dest_regno
- FPR_FIRST
) & 1) == 0
4501 && ((src_regno
- GPR_FIRST
) & 1) == 0)
4502 return "movgfd %1, %0";
4507 else if (FPR_P (src_regno
))
4510 && ((dest_regno
- FPR_FIRST
) & 1) == 0
4511 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4512 return "fmovd %1, %0";
4518 else if (GET_CODE (src
) == MEM
)
4521 if (dbl_memory_one_insn_operand (src
, mode
))
4522 return "lddf%I1%U1 %M1, %0";
4527 else if (ZERO_P (src
))
4532 else if (GET_CODE (dest
) == MEM
)
4534 if (GET_CODE (src
) == REG
)
4536 int src_regno
= REGNO (src
);
4538 if (GPR_P (src_regno
))
4540 if (((src_regno
- GPR_FIRST
) & 1) == 0
4541 && dbl_memory_one_insn_operand (dest
, mode
))
4542 return "std%I0%U0 %1, %M0";
4547 if (FPR_P (src_regno
))
4549 if (((src_regno
- FPR_FIRST
) & 1) == 0
4550 && dbl_memory_one_insn_operand (dest
, mode
))
4551 return "stdf%I0%U0 %1, %M0";
4557 else if (ZERO_P (src
))
4559 if (dbl_memory_one_insn_operand (dest
, mode
))
4560 return "std%I0%U0 %., %M0";
4566 fatal_insn ("bad output_move_double operand", insn
);
4571 /* Return a string to output a single word conditional move.
4572 Operand0 -- EQ/NE of ccr register and 0
4573 Operand1 -- CCR register
4574 Operand2 -- destination
4575 Operand3 -- source */
4578 output_condmove_single (rtx operands
[], rtx insn
)
4580 rtx dest
= operands
[2];
4581 rtx src
= operands
[3];
4583 if (GET_CODE (dest
) == REG
)
4585 int dest_regno
= REGNO (dest
);
4586 machine_mode mode
= GET_MODE (dest
);
4588 if (GPR_P (dest_regno
))
4590 if (GET_CODE (src
) == REG
)
4592 /* gpr <- some sort of register */
4593 int src_regno
= REGNO (src
);
4595 if (GPR_P (src_regno
))
4596 return "cmov %z3, %2, %1, %e0";
4598 else if (FPR_P (src_regno
))
4599 return "cmovfg %3, %2, %1, %e0";
4602 else if (GET_CODE (src
) == MEM
)
4611 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4614 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4618 return "cld%I3%U3 %M3, %2, %1, %e0";
4622 else if (ZERO_P (src
))
4623 return "cmov %., %2, %1, %e0";
4626 else if (FPR_P (dest_regno
))
4628 if (GET_CODE (src
) == REG
)
4630 /* fpr <- some sort of register */
4631 int src_regno
= REGNO (src
);
4633 if (GPR_P (src_regno
))
4634 return "cmovgf %3, %2, %1, %e0";
4636 else if (FPR_P (src_regno
))
4638 if (TARGET_HARD_FLOAT
)
4639 return "cfmovs %3,%2,%1,%e0";
4641 return "cmor %3, %3, %2, %1, %e0";
4645 else if (GET_CODE (src
) == MEM
)
4648 if (mode
== SImode
|| mode
== SFmode
)
4649 return "cldf%I3%U3 %M3, %2, %1, %e0";
4652 else if (ZERO_P (src
))
4653 return "cmovgf %., %2, %1, %e0";
4657 else if (GET_CODE (dest
) == MEM
)
4659 if (GET_CODE (src
) == REG
)
4661 int src_regno
= REGNO (src
);
4662 machine_mode mode
= GET_MODE (dest
);
4664 if (GPR_P (src_regno
))
4672 return "cstb%I2%U2 %3, %M2, %1, %e0";
4675 return "csth%I2%U2 %3, %M2, %1, %e0";
4679 return "cst%I2%U2 %3, %M2, %1, %e0";
4683 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
4684 return "cstf%I2%U2 %3, %M2, %1, %e0";
4687 else if (ZERO_P (src
))
4689 machine_mode mode
= GET_MODE (dest
);
4696 return "cstb%I2%U2 %., %M2, %1, %e0";
4699 return "csth%I2%U2 %., %M2, %1, %e0";
4703 return "cst%I2%U2 %., %M2, %1, %e0";
4708 fatal_insn ("bad output_condmove_single operand", insn
);
4713 /* Emit the appropriate code to do a comparison, returning the register the
4714 comparison was done it. */
4717 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
4719 machine_mode cc_mode
;
4722 /* Floating point doesn't have comparison against a constant. */
4723 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
4724 op1
= force_reg (GET_MODE (op0
), op1
);
4726 /* Possibly disable using anything but a fixed register in order to work
4727 around cse moving comparisons past function calls. */
4728 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
4729 cc_reg
= ((TARGET_ALLOC_CC
)
4730 ? gen_reg_rtx (cc_mode
)
4731 : gen_rtx_REG (cc_mode
,
4732 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
4734 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
4740 /* Emit code for a conditional branch.
4741 XXX: I originally wanted to add a clobber of a CCR register to use in
4742 conditional execution, but that confuses the rest of the compiler. */
4745 frv_emit_cond_branch (rtx operands
[])
4750 enum rtx_code test
= GET_CODE (operands
[0]);
4751 rtx cc_reg
= frv_emit_comparison (test
, operands
[1], operands
[2]);
4752 machine_mode cc_mode
= GET_MODE (cc_reg
);
4754 /* Branches generate:
4756 (if_then_else (<test>, <cc_reg>, (const_int 0))
4757 (label_ref <branch_label>)
4759 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
4760 test_rtx
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4761 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
4762 emit_jump_insn (gen_rtx_SET (pc_rtx
, if_else
));
4767 /* Emit code to set a gpr to 1/0 based on a comparison. */
4770 frv_emit_scc (rtx operands
[])
4776 enum rtx_code test
= GET_CODE (operands
[1]);
4777 rtx cc_reg
= frv_emit_comparison (test
, operands
[2], operands
[3]);
4779 /* SCC instructions generate:
4780 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4781 (clobber (<ccr_reg>))]) */
4782 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
4783 set
= gen_rtx_SET (operands
[0], test_rtx
);
4785 cr_reg
= ((TARGET_ALLOC_CC
)
4786 ? gen_reg_rtx (CC_CCRmode
)
4787 : gen_rtx_REG (CC_CCRmode
,
4788 ((GET_MODE (cc_reg
) == CC_FPmode
)
4792 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4793 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
4798 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4799 the separate insns. */
4802 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
4808 /* Set the appropriate CCR bit. */
4809 emit_insn (gen_rtx_SET (cr_reg
,
4810 gen_rtx_fmt_ee (GET_CODE (test
),
4815 /* Move the value into the destination. */
4816 emit_move_insn (dest
, GEN_INT (value
));
4818 /* Move 0 into the destination if the test failed */
4819 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4820 gen_rtx_EQ (GET_MODE (cr_reg
),
4823 gen_rtx_SET (dest
, const0_rtx
)));
4825 /* Finish up, return sequence. */
4832 /* Emit the code for a conditional move, return TRUE if we could do the
4836 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
4843 enum rtx_code test
= GET_CODE (test_rtx
);
4844 rtx cc_reg
= frv_emit_comparison (test
,
4845 XEXP (test_rtx
, 0), XEXP (test_rtx
, 1));
4846 machine_mode cc_mode
= GET_MODE (cc_reg
);
4848 /* Conditional move instructions generate:
4849 (parallel [(set <target>
4850 (if_then_else (<test> <cc_reg> (const_int 0))
4853 (clobber (<ccr_reg>))]) */
4855 /* Handle various cases of conditional move involving two constants. */
4856 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4858 HOST_WIDE_INT value1
= INTVAL (src1
);
4859 HOST_WIDE_INT value2
= INTVAL (src2
);
4861 /* Having 0 as one of the constants can be done by loading the other
4862 constant, and optionally moving in gr0. */
4863 if (value1
== 0 || value2
== 0)
4866 /* If the first value is within an addi range and also the difference
4867 between the two fits in an addi's range, load up the difference, then
4868 conditionally move in 0, and then unconditionally add the first
4870 else if (IN_RANGE (value1
, -2048, 2047)
4871 && IN_RANGE (value2
- value1
, -2048, 2047))
4874 /* If neither condition holds, just force the constant into a
4878 src1
= force_reg (GET_MODE (dest
), src1
);
4879 src2
= force_reg (GET_MODE (dest
), src2
);
4883 /* If one value is a register, insure the other value is either 0 or a
4887 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
4888 src1
= force_reg (GET_MODE (dest
), src1
);
4890 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
4891 src2
= force_reg (GET_MODE (dest
), src2
);
4894 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4895 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
4897 set
= gen_rtx_SET (dest
, if_rtx
);
4899 cr_reg
= ((TARGET_ALLOC_CC
)
4900 ? gen_reg_rtx (CC_CCRmode
)
4901 : gen_rtx_REG (CC_CCRmode
,
4902 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
4904 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4905 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
4910 /* Split a conditional move into constituent parts, returning a SEQUENCE
4911 containing all of the insns. */
4914 frv_split_cond_move (rtx operands
[])
4916 rtx dest
= operands
[0];
4917 rtx test
= operands
[1];
4918 rtx cc_reg
= operands
[2];
4919 rtx src1
= operands
[3];
4920 rtx src2
= operands
[4];
4921 rtx cr_reg
= operands
[5];
4923 machine_mode cr_mode
= GET_MODE (cr_reg
);
4927 /* Set the appropriate CCR bit. */
4928 emit_insn (gen_rtx_SET (cr_reg
,
4929 gen_rtx_fmt_ee (GET_CODE (test
),
4934 /* Handle various cases of conditional move involving two constants. */
4935 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4937 HOST_WIDE_INT value1
= INTVAL (src1
);
4938 HOST_WIDE_INT value2
= INTVAL (src2
);
4940 /* Having 0 as one of the constants can be done by loading the other
4941 constant, and optionally moving in gr0. */
4944 emit_move_insn (dest
, src2
);
4945 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4946 gen_rtx_NE (cr_mode
, cr_reg
,
4948 gen_rtx_SET (dest
, src1
)));
4951 else if (value2
== 0)
4953 emit_move_insn (dest
, src1
);
4954 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4955 gen_rtx_EQ (cr_mode
, cr_reg
,
4957 gen_rtx_SET (dest
, src2
)));
4960 /* If the first value is within an addi range and also the difference
4961 between the two fits in an addi's range, load up the difference, then
4962 conditionally move in 0, and then unconditionally add the first
4964 else if (IN_RANGE (value1
, -2048, 2047)
4965 && IN_RANGE (value2
- value1
, -2048, 2047))
4967 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
4969 : gen_rtx_SUBREG (SImode
, dest
, 0));
4971 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
4972 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4973 gen_rtx_NE (cr_mode
, cr_reg
,
4975 gen_rtx_SET (dest_si
, const0_rtx
)));
4976 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
4984 /* Emit the conditional move for the test being true if needed. */
4985 if (! rtx_equal_p (dest
, src1
))
4986 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4987 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
4988 gen_rtx_SET (dest
, src1
)));
4990 /* Emit the conditional move for the test being false if needed. */
4991 if (! rtx_equal_p (dest
, src2
))
4992 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4993 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
4994 gen_rtx_SET (dest
, src2
)));
4997 /* Finish up, return sequence. */
5004 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5005 memory location that is not known to be dword-aligned. */
5007 frv_split_double_load (rtx dest
, rtx source
)
5009 int regno
= REGNO (dest
);
5010 rtx dest1
= gen_highpart (SImode
, dest
);
5011 rtx dest2
= gen_lowpart (SImode
, dest
);
5012 rtx address
= XEXP (source
, 0);
5014 /* If the address is pre-modified, load the lower-numbered register
5015 first, then load the other register using an integer offset from
5016 the modified base register. This order should always be safe,
5017 since the pre-modification cannot affect the same registers as the
5020 The situation for other loads is more complicated. Loading one
5021 of the registers could affect the value of ADDRESS, so we must
5022 be careful which order we do them in. */
5023 if (GET_CODE (address
) == PRE_MODIFY
5024 || ! refers_to_regno_p (regno
, address
))
5026 /* It is safe to load the lower-numbered register first. */
5027 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5028 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5032 /* ADDRESS is not pre-modified and the address depends on the
5033 lower-numbered register. Load the higher-numbered register
5035 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5036 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5040 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5041 and SOURCE is either a double register or the constant zero. */
5043 frv_split_double_store (rtx dest
, rtx source
)
5045 rtx dest1
= change_address (dest
, SImode
, NULL
);
5046 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
5047 if (ZERO_P (source
))
5049 emit_move_insn (dest1
, CONST0_RTX (SImode
));
5050 emit_move_insn (dest2
, CONST0_RTX (SImode
));
5054 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
5055 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
5060 /* Split a min/max operation returning a SEQUENCE containing all of the
5064 frv_split_minmax (rtx operands
[])
5066 rtx dest
= operands
[0];
5067 rtx minmax
= operands
[1];
5068 rtx src1
= operands
[2];
5069 rtx src2
= operands
[3];
5070 rtx cc_reg
= operands
[4];
5071 rtx cr_reg
= operands
[5];
5073 enum rtx_code test_code
;
5074 machine_mode cr_mode
= GET_MODE (cr_reg
);
5078 /* Figure out which test to use. */
5079 switch (GET_CODE (minmax
))
5084 case SMIN
: test_code
= LT
; break;
5085 case SMAX
: test_code
= GT
; break;
5086 case UMIN
: test_code
= LTU
; break;
5087 case UMAX
: test_code
= GTU
; break;
5090 /* Issue the compare instruction. */
5091 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (GET_MODE (cc_reg
),
5094 /* Set the appropriate CCR bit. */
5095 emit_insn (gen_rtx_SET (cr_reg
, gen_rtx_fmt_ee (test_code
,
5100 /* If are taking the min/max of a nonzero constant, load that first, and
5101 then do a conditional move of the other value. */
5102 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
5104 gcc_assert (!rtx_equal_p (dest
, src1
));
5106 emit_move_insn (dest
, src2
);
5107 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5108 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5109 gen_rtx_SET (dest
, src1
)));
5112 /* Otherwise, do each half of the move. */
5115 /* Emit the conditional move for the test being true if needed. */
5116 if (! rtx_equal_p (dest
, src1
))
5117 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5118 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5119 gen_rtx_SET (dest
, src1
)));
5121 /* Emit the conditional move for the test being false if needed. */
5122 if (! rtx_equal_p (dest
, src2
))
5123 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5124 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5125 gen_rtx_SET (dest
, src2
)));
5128 /* Finish up, return sequence. */
5135 /* Split an integer abs operation returning a SEQUENCE containing all of the
5139 frv_split_abs (rtx operands
[])
5141 rtx dest
= operands
[0];
5142 rtx src
= operands
[1];
5143 rtx cc_reg
= operands
[2];
5144 rtx cr_reg
= operands
[3];
5149 /* Issue the compare < 0 instruction. */
5150 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
5152 /* Set the appropriate CCR bit. */
5153 emit_insn (gen_rtx_SET (cr_reg
, gen_rtx_fmt_ee (LT
, CC_CCRmode
,
5154 cc_reg
, const0_rtx
)));
5156 /* Emit the conditional negate if the value is negative. */
5157 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5158 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
5159 gen_negsi2 (dest
, src
)));
5161 /* Emit the conditional move for the test being false if needed. */
5162 if (! rtx_equal_p (dest
, src
))
5163 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5164 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
5165 gen_rtx_SET (dest
, src
)));
5167 /* Finish up, return sequence. */
5174 /* Initialize machine-specific if-conversion data.
5175 On the FR-V, we don't have any extra fields per se, but it is useful hook to
5176 initialize the static storage. */
5178 frv_ifcvt_machdep_init (void *ce_info ATTRIBUTE_UNUSED
)
5180 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5181 frv_ifcvt
.cur_scratch_regs
= 0;
5182 frv_ifcvt
.num_nested_cond_exec
= 0;
5183 frv_ifcvt
.cr_reg
= NULL_RTX
;
5184 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
5185 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
5186 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
5187 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5191 /* Internal function to add a potential insn to the list of insns to be inserted
5192 if the conditional execution conversion is successful. */
5195 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
5197 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
5199 link
->jump
= before_p
; /* Mark to add this before or after insn. */
5200 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
5201 frv_ifcvt
.added_insns_list
);
5203 if (TARGET_DEBUG_COND_EXEC
)
5206 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5207 (before_p
) ? "before" : "after",
5208 (int)INSN_UID (insn
));
5210 debug_rtx (pattern
);
5215 /* A C expression to modify the code described by the conditional if
5216 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5217 FALSE_EXPR for converting if-then and if-then-else code to conditional
5218 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5219 tests cannot be converted. */
5222 frv_ifcvt_modify_tests (ce_if_block
*ce_info
, rtx
*p_true
, rtx
*p_false
)
5224 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
5225 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
5226 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
5227 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
5228 rtx true_expr
= *p_true
;
5232 machine_mode mode
= GET_MODE (true_expr
);
5236 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
5238 rtx sub_cond_exec_reg
;
5240 enum rtx_code code_true
;
5241 enum rtx_code code_false
;
5242 enum reg_class cc_class
;
5243 enum reg_class cr_class
;
5246 reg_set_iterator rsi
;
5248 /* Make sure we are only dealing with hard registers. Also honor the
5249 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5251 if (!reload_completed
|| !TARGET_COND_EXEC
5252 || (!TARGET_NESTED_CE
&& ce_info
->pass
> 1))
5255 /* Figure out which registers we can allocate for our own purposes. Only
5256 consider registers that are not preserved across function calls and are
5257 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5258 if we did not need to use them in reloading other registers. */
5259 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
5260 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
5261 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
5262 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
5263 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
5265 /* If this is a nested IF, we need to discover whether the CC registers that
5266 are set/used inside of the block are used anywhere else. If not, we can
5267 change them to be the CC register that is paired with the CR register that
5268 controls the outermost IF block. */
5269 if (ce_info
->pass
> 1)
5271 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
5272 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5273 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5275 if (REGNO_REG_SET_P (df_get_live_in (then_bb
), j
))
5279 && REGNO_REG_SET_P (df_get_live_in (else_bb
), j
))
5283 && REGNO_REG_SET_P (df_get_live_in (join_bb
), j
))
5286 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
5290 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
5291 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
5293 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5294 frv_ifcvt
.cur_scratch_regs
= 0;
5296 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
5297 * sizeof (basic_block
));
5303 /* Remove anything live at the beginning of the join block from being
5304 available for allocation. */
5305 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb
), 0, regno
, rsi
)
5307 if (regno
< FIRST_PSEUDO_REGISTER
)
5308 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5312 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5314 if (ce_info
->num_multiple_test_blocks
)
5316 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
5318 while (multiple_test_bb
!= test_bb
)
5320 bb
[num_bb
++] = multiple_test_bb
;
5321 multiple_test_bb
= EDGE_PRED (multiple_test_bb
, 0)->src
;
5325 /* Add in the THEN and ELSE blocks to be scanned. */
5326 bb
[num_bb
++] = then_bb
;
5328 bb
[num_bb
++] = else_bb
;
5330 sub_cond_exec_reg
= NULL_RTX
;
5331 frv_ifcvt
.num_nested_cond_exec
= 0;
5333 /* Scan all of the blocks for registers that must not be allocated. */
5334 for (j
= 0; j
< num_bb
; j
++)
5336 rtx_insn
*last_insn
= BB_END (bb
[j
]);
5337 rtx_insn
*insn
= BB_HEAD (bb
[j
]);
5341 fprintf (dump_file
, "Scanning %s block %d, start %d, end %d\n",
5342 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
5344 (int) INSN_UID (BB_HEAD (bb
[j
])),
5345 (int) INSN_UID (BB_END (bb
[j
])));
5347 /* Anything live at the beginning of the block is obviously unavailable
5349 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb
[j
]), 0, regno
, rsi
)
5351 if (regno
< FIRST_PSEUDO_REGISTER
)
5352 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5355 /* Loop through the insns in the block. */
5358 /* Mark any new registers that are created as being unavailable for
5359 allocation. Also see if the CC register used in nested IFs can be
5365 int skip_nested_if
= FALSE
;
5366 HARD_REG_SET mentioned_regs
;
5368 CLEAR_HARD_REG_SET (mentioned_regs
);
5369 find_all_hard_regs (PATTERN (insn
), &mentioned_regs
);
5370 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, mentioned_regs
);
5372 pattern
= PATTERN (insn
);
5373 if (GET_CODE (pattern
) == COND_EXEC
)
5375 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
5377 if (reg
!= sub_cond_exec_reg
)
5379 sub_cond_exec_reg
= reg
;
5380 frv_ifcvt
.num_nested_cond_exec
++;
5384 set
= single_set_pattern (pattern
);
5387 rtx dest
= SET_DEST (set
);
5388 rtx src
= SET_SRC (set
);
5390 if (GET_CODE (dest
) == REG
)
5392 int regno
= REGNO (dest
);
5393 enum rtx_code src_code
= GET_CODE (src
);
5395 if (CC_P (regno
) && src_code
== COMPARE
)
5396 skip_nested_if
= TRUE
;
5398 else if (CR_P (regno
)
5399 && (src_code
== IF_THEN_ELSE
5400 || COMPARISON_P (src
)))
5401 skip_nested_if
= TRUE
;
5405 if (! skip_nested_if
)
5406 AND_COMPL_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
,
5410 if (insn
== last_insn
)
5413 insn
= NEXT_INSN (insn
);
5417 /* If this is a nested if, rewrite the CC registers that are available to
5418 include the ones that can be rewritten, to increase the chance of being
5419 able to allocate a paired CC/CR register combination. */
5420 if (ce_info
->pass
> 1)
5422 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5423 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
5424 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
5426 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
5432 fprintf (dump_file
, "Available GPRs: ");
5434 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
5435 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5437 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5438 if (++num_gprs
> GPR_TEMP_NUM
+2)
5442 fprintf (dump_file
, "%s\nAvailable CRs: ",
5443 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
5445 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
5446 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5447 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5449 fputs ("\n", dump_file
);
5451 if (ce_info
->pass
> 1)
5453 fprintf (dump_file
, "Modifiable CCs: ");
5454 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5455 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5456 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5458 fprintf (dump_file
, "\n%d nested COND_EXEC statements\n",
5459 frv_ifcvt
.num_nested_cond_exec
);
5463 /* Allocate the appropriate temporary condition code register. Try to
5464 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5465 that conditional cmp's can be done. */
5466 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5468 cr_class
= ICR_REGS
;
5469 cc_class
= ICC_REGS
;
5470 cc_first
= ICC_FIRST
;
5473 else if (mode
== CC_FPmode
)
5475 cr_class
= FCR_REGS
;
5476 cc_class
= FCC_REGS
;
5477 cc_first
= FCC_FIRST
;
5482 cc_first
= cc_last
= 0;
5483 cr_class
= cc_class
= NO_REGS
;
5486 cc
= XEXP (true_expr
, 0);
5487 nested_cc
= cr
= NULL_RTX
;
5488 if (cc_class
!= NO_REGS
)
5490 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5491 so we can execute a csubcc/caddcc/cfcmps instruction. */
5494 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
5496 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
5498 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
5499 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
5501 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
5502 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
5505 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
5506 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
5516 fprintf (dump_file
, "Could not allocate a CR temporary register\n");
5523 "Will use %s for conditional execution, %s for nested comparisons\n",
5524 reg_names
[ REGNO (cr
)],
5525 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
5527 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5528 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5529 bit being true. We don't do this for floating point, because of NaNs. */
5530 code
= GET_CODE (true_expr
);
5531 if (GET_MODE (cc
) != CC_FPmode
)
5533 code
= reverse_condition (code
);
5543 check_insn
= gen_rtx_SET (cr
, gen_rtx_fmt_ee (code
, CC_CCRmode
,
5546 /* Record the check insn to be inserted later. */
5547 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
5549 /* Update the tests. */
5550 frv_ifcvt
.cr_reg
= cr
;
5551 frv_ifcvt
.nested_cc_reg
= nested_cc
;
5552 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
5553 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
5556 /* Fail, don't do this conditional execution. */
5559 *p_false
= NULL_RTX
;
5561 fprintf (dump_file
, "Disabling this conditional execution.\n");
5567 /* A C expression to modify the code described by the conditional if
5568 information CE_INFO, for the basic block BB, possibly updating the tests in
5569 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5570 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5571 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5573 /* p_true and p_false are given expressions of the form:
5575 (and (eq:CC_CCR (reg:CC_CCR)
5581 frv_ifcvt_modify_multiple_tests (ce_if_block
*ce_info
,
5586 rtx old_true
= XEXP (*p_true
, 0);
5587 rtx old_false
= XEXP (*p_false
, 0);
5588 rtx true_expr
= XEXP (*p_true
, 1);
5589 rtx false_expr
= XEXP (*p_false
, 1);
5592 rtx cr
= XEXP (old_true
, 0);
5594 rtx new_cr
= NULL_RTX
;
5595 rtx
*p_new_cr
= (rtx
*)0;
5599 enum reg_class cr_class
;
5600 machine_mode mode
= GET_MODE (true_expr
);
5601 rtx (*logical_func
)(rtx
, rtx
, rtx
);
5603 if (TARGET_DEBUG_COND_EXEC
)
5606 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5607 ce_info
->and_and_p
? "&&" : "||");
5609 debug_rtx (*p_true
);
5611 fputs ("\nfalse insn:\n", stderr
);
5612 debug_rtx (*p_false
);
5615 if (!TARGET_MULTI_CE
)
5618 if (GET_CODE (cr
) != REG
)
5621 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5623 cr_class
= ICR_REGS
;
5624 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
5626 else if (mode
== CC_FPmode
)
5628 cr_class
= FCR_REGS
;
5629 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
5634 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5635 more &&/|| tests. */
5639 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
5640 CC_CCRmode
, TRUE
, TRUE
);
5645 if (ce_info
->and_and_p
)
5647 old_test
= old_false
;
5648 test_expr
= true_expr
;
5649 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
5650 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5651 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5655 old_test
= old_false
;
5656 test_expr
= false_expr
;
5657 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
5658 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5659 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5662 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5663 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5665 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
5667 /* Now add the conditional check insn. */
5668 cc
= XEXP (test_expr
, 0);
5669 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
5670 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
5672 check_insn
= gen_rtx_SET (new_cr
, if_else
);
5674 /* Add the new check insn to the list of check insns that need to be
5676 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
5678 if (TARGET_DEBUG_COND_EXEC
)
5680 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5683 debug_rtx (*p_true
);
5685 fputs ("\nfalse insn:\n", stderr
);
5686 debug_rtx (*p_false
);
5692 *p_true
= *p_false
= NULL_RTX
;
5694 /* If we allocated a CR register, release it. */
5697 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
5698 *p_new_cr
= NULL_RTX
;
5701 if (TARGET_DEBUG_COND_EXEC
)
5702 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
5708 /* Return a register which will be loaded with a value if an IF block is
5709 converted to conditional execution. This is used to rewrite instructions
5710 that use constants to ones that just use registers. */
5713 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
5715 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
5719 /* We know gr0 == 0, so replace any errant uses. */
5720 if (value
== const0_rtx
)
5721 return gen_rtx_REG (SImode
, GPR_FIRST
);
5723 /* First search all registers currently loaded to see if we have an
5724 applicable constant. */
5725 if (CONSTANT_P (value
)
5726 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
5728 for (i
= 0; i
< num_alloc
; i
++)
5730 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
5731 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
5735 /* Have we exhausted the number of registers available? */
5736 if (num_alloc
>= GPR_TEMP_NUM
)
5739 fprintf (dump_file
, "Too many temporary registers allocated\n");
5744 /* Allocate the new register. */
5745 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
5749 fputs ("Could not find a scratch register\n", dump_file
);
5754 frv_ifcvt
.cur_scratch_regs
++;
5755 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (reg
, value
);
5759 if (GET_CODE (value
) == CONST_INT
)
5760 fprintf (dump_file
, "Register %s will hold %ld\n",
5761 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
5763 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
5764 fprintf (dump_file
, "Register %s will hold LR\n",
5765 reg_names
[ REGNO (reg
)]);
5768 fprintf (dump_file
, "Register %s will hold a saved value\n",
5769 reg_names
[ REGNO (reg
)]);
5776 /* Update a MEM used in conditional code that might contain an offset to put
5777 the offset into a scratch register, so that the conditional load/store
5778 operations can be used. This function returns the original pointer if the
5779 MEM is valid to use in conditional code, NULL if we can't load up the offset
5780 into a temporary register, or the new MEM if we were successful. */
5783 frv_ifcvt_rewrite_mem (rtx mem
, machine_mode mode
, rtx insn
)
5785 rtx addr
= XEXP (mem
, 0);
5787 if (!frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
))
5789 if (GET_CODE (addr
) == PLUS
)
5791 rtx addr_op0
= XEXP (addr
, 0);
5792 rtx addr_op1
= XEXP (addr
, 1);
5794 if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
5796 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
5800 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
5807 else if (CONSTANT_P (addr
))
5808 addr
= frv_ifcvt_load_value (addr
, insn
);
5813 if (addr
== NULL_RTX
)
5816 else if (XEXP (mem
, 0) != addr
)
5817 return change_address (mem
, mode
, addr
);
5824 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5825 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5828 single_set_pattern (rtx pattern
)
5833 if (GET_CODE (pattern
) == COND_EXEC
)
5834 pattern
= COND_EXEC_CODE (pattern
);
5836 if (GET_CODE (pattern
) == SET
)
5839 else if (GET_CODE (pattern
) == PARALLEL
)
5841 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
5843 rtx sub
= XVECEXP (pattern
, 0, i
);
5845 switch (GET_CODE (sub
))
5869 /* A C expression to modify the code described by the conditional if
5870 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5871 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5872 insn cannot be converted to be executed conditionally. */
5875 frv_ifcvt_modify_insn (ce_if_block
*ce_info
,
5879 rtx orig_ce_pattern
= pattern
;
5885 gcc_assert (GET_CODE (pattern
) == COND_EXEC
);
5887 test
= COND_EXEC_TEST (pattern
);
5888 if (GET_CODE (test
) == AND
)
5890 rtx cr
= frv_ifcvt
.cr_reg
;
5893 op0
= XEXP (test
, 0);
5894 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
5897 op1
= XEXP (test
, 1);
5898 test_reg
= XEXP (op1
, 0);
5899 if (GET_CODE (test_reg
) != REG
)
5902 /* Is this the first nested if block in this sequence? If so, generate
5903 an andcr or andncr. */
5904 if (! frv_ifcvt
.last_nested_if_cr
)
5908 frv_ifcvt
.last_nested_if_cr
= test_reg
;
5909 if (GET_CODE (op0
) == NE
)
5910 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
5912 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
5914 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
5917 /* If this isn't the first statement in the nested if sequence, see if we
5918 are dealing with the same register. */
5919 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
5922 COND_EXEC_TEST (pattern
) = test
= op1
;
5925 /* If this isn't a nested if, reset state variables. */
5928 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5931 set
= single_set_pattern (pattern
);
5934 rtx dest
= SET_DEST (set
);
5935 rtx src
= SET_SRC (set
);
5936 machine_mode mode
= GET_MODE (dest
);
5938 /* Check for normal binary operators. */
5939 if (mode
== SImode
&& ARITHMETIC_P (src
))
5941 op0
= XEXP (src
, 0);
5942 op1
= XEXP (src
, 1);
5944 if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
5946 op1
= frv_ifcvt_load_value (op1
, insn
);
5948 COND_EXEC_CODE (pattern
)
5949 = gen_rtx_SET (dest
, gen_rtx_fmt_ee (GET_CODE (src
),
5957 /* For multiply by a constant, we need to handle the sign extending
5958 correctly. Add a USE of the value after the multiply to prevent flow
5959 from cratering because only one register out of the two were used. */
5960 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
5962 op0
= XEXP (src
, 0);
5963 op1
= XEXP (src
, 1);
5964 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
5966 op1
= frv_ifcvt_load_value (op1
, insn
);
5969 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
5970 COND_EXEC_CODE (pattern
)
5971 = gen_rtx_SET (dest
, gen_rtx_MULT (DImode
, op0
, op1
));
5977 frv_ifcvt_add_insn (gen_use (dest
), insn
, FALSE
);
5980 /* If we are just loading a constant created for a nested conditional
5981 execution statement, just load the constant without any conditional
5982 execution, since we know that the constant will not interfere with any
5984 else if (frv_ifcvt
.scratch_insns_bitmap
5985 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
5987 && REG_P (SET_DEST (set
))
5988 /* We must not unconditionally set a scratch reg chosen
5989 for a nested if-converted block if its incoming
5990 value from the TEST block (or the result of the THEN
5991 branch) could/should propagate to the JOIN block.
5992 It suffices to test whether the register is live at
5993 the JOIN point: if it's live there, we can infer
5994 that we set it in the former JOIN block of the
5995 nested if-converted block (otherwise it wouldn't
5996 have been available as a scratch register), and it
5997 is either propagated through or set in the other
5998 conditional block. It's probably not worth trying
5999 to catch the latter case, and it could actually
6000 limit scheduling of the combined block quite
6003 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->join_bb
),
6004 REGNO (SET_DEST (set
))))
6005 /* Similarly, we must not unconditionally set a reg
6006 used as scratch in the THEN branch if the same reg
6007 is live in the ELSE branch. */
6008 && (! ce_info
->else_bb
6009 || BLOCK_FOR_INSN (insn
) == ce_info
->else_bb
6010 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->else_bb
),
6011 REGNO (SET_DEST (set
))))))
6014 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
6017 int changed_p
= FALSE
;
6019 /* Check for just loading up a constant */
6020 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
6022 src
= frv_ifcvt_load_value (src
, insn
);
6029 /* See if we need to fix up stores */
6030 if (GET_CODE (dest
) == MEM
)
6032 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
6037 else if (new_mem
!= dest
)
6044 /* See if we need to fix up loads */
6045 if (GET_CODE (src
) == MEM
)
6047 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
6052 else if (new_mem
!= src
)
6059 /* If either src or destination changed, redo SET. */
6061 COND_EXEC_CODE (pattern
) = gen_rtx_SET (dest
, src
);
6064 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6065 rewriting the CC register to be the same as the paired CC/CR register
6067 else if (mode
== CC_CCRmode
&& COMPARISON_P (src
))
6069 int regno
= REGNO (XEXP (src
, 0));
6072 if (ce_info
->pass
> 1
6073 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
6074 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
6076 src
= gen_rtx_fmt_ee (GET_CODE (src
),
6078 frv_ifcvt
.nested_cc_reg
,
6082 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
6083 pattern
= gen_rtx_SET (dest
, if_else
);
6086 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6087 else if (ce_info
->pass
> 1
6088 && GET_CODE (dest
) == REG
6089 && CC_P (REGNO (dest
))
6090 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
6091 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
6093 && GET_CODE (src
) == COMPARE
)
6095 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
6096 COND_EXEC_CODE (pattern
)
6097 = gen_rtx_SET (frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
6101 if (TARGET_DEBUG_COND_EXEC
)
6103 rtx orig_pattern
= PATTERN (insn
);
6105 PATTERN (insn
) = pattern
;
6107 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6111 PATTERN (insn
) = orig_pattern
;
6117 if (TARGET_DEBUG_COND_EXEC
)
6119 rtx orig_pattern
= PATTERN (insn
);
6121 PATTERN (insn
) = orig_ce_pattern
;
6123 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6127 PATTERN (insn
) = orig_pattern
;
6134 /* A C expression to perform any final machine dependent modifications in
6135 converting code to conditional execution in the code described by the
6136 conditional if information CE_INFO. */
6139 frv_ifcvt_modify_final (ce_if_block
*ce_info ATTRIBUTE_UNUSED
)
6143 rtx p
= frv_ifcvt
.added_insns_list
;
6146 /* Loop inserting the check insns. The last check insn is the first test,
6147 and is the appropriate place to insert constants. */
6152 rtx check_and_insert_insns
= XEXP (p
, 0);
6155 check_insn
= XEXP (check_and_insert_insns
, 0);
6156 existing_insn
= XEXP (check_and_insert_insns
, 1);
6159 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6160 the existing insn, otherwise it is to be inserted AFTER. */
6161 if (check_and_insert_insns
->jump
)
6163 emit_insn_before (check_insn
, existing_insn
);
6164 check_and_insert_insns
->jump
= 0;
6167 emit_insn_after (check_insn
, existing_insn
);
6169 free_EXPR_LIST_node (check_and_insert_insns
);
6170 free_EXPR_LIST_node (old_p
);
6172 while (p
!= NULL_RTX
);
6174 /* Load up any constants needed into temp gprs */
6175 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6177 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
6178 if (! frv_ifcvt
.scratch_insns_bitmap
)
6179 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_ALLOC (NULL
);
6180 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
6181 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6184 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6185 frv_ifcvt
.cur_scratch_regs
= 0;
6189 /* A C expression to cancel any machine dependent modifications in converting
6190 code to conditional execution in the code described by the conditional if
6191 information CE_INFO. */
6194 frv_ifcvt_modify_cancel (ce_if_block
*ce_info ATTRIBUTE_UNUSED
)
6197 rtx p
= frv_ifcvt
.added_insns_list
;
6199 /* Loop freeing up the EXPR_LIST's allocated. */
6200 while (p
!= NULL_RTX
)
6202 rtx check_and_jump
= XEXP (p
, 0);
6206 free_EXPR_LIST_node (check_and_jump
);
6207 free_EXPR_LIST_node (old_p
);
6210 /* Release any temporary gprs allocated. */
6211 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6212 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6214 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6215 frv_ifcvt
.cur_scratch_regs
= 0;
6219 /* A C expression for the size in bytes of the trampoline, as an integer.
6223 setlo #0, <static_chain>
6225 sethi #0, <static_chain>
6226 jmpl @(gr0,<jmp_reg>) */
6229 frv_trampoline_size (void)
6232 /* Allocate room for the function descriptor and the lddi
6235 return 5 /* instructions */ * 4 /* instruction size. */;
6239 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6240 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6241 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6242 should be passed to the function when it is called.
6247 setlo #0, <static_chain>
6249 sethi #0, <static_chain>
6250 jmpl @(gr0,<jmp_reg>) */
6253 frv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
6255 rtx addr
= XEXP (m_tramp
, 0);
6256 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6257 rtx sc_reg
= force_reg (Pmode
, static_chain
);
6259 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
6260 LCT_NORMAL
, VOIDmode
, 4,
6262 GEN_INT (frv_trampoline_size ()), SImode
,
6268 /* Many machines have some registers that cannot be copied directly to or from
6269 memory or even from other types of registers. An example is the `MQ'
6270 register, which on most machines, can only be copied to or from general
6271 registers, but not memory. Some machines allow copying all registers to and
6272 from memory, but require a scratch register for stores to some memory
6273 locations (e.g., those with symbolic address on the RT, and those with
6274 certain symbolic address on the SPARC when compiling PIC). In some cases,
6275 both an intermediate and a scratch register are required.
6277 You should define these macros to indicate to the reload phase that it may
6278 need to allocate at least one register for a reload in addition to the
6279 register to contain the data. Specifically, if copying X to a register
6280 RCLASS in MODE requires an intermediate register, you should define
6281 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6282 whose registers can be used as intermediate registers or scratch registers.
6284 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6285 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6286 largest register class required. If the requirements for input and output
6287 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6288 instead of defining both macros identically.
6290 The values returned by these macros are often `GENERAL_REGS'. Return
6291 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6292 to or from a register of RCLASS in MODE without requiring a scratch register.
6293 Do not define this macro if it would always return `NO_REGS'.
6295 If a scratch register is required (either with or without an intermediate
6296 register), you should define patterns for `reload_inM' or `reload_outM', as
6297 required.. These patterns, which will normally be implemented with a
6298 `define_expand', should be similar to the `movM' patterns, except that
6299 operand 2 is the scratch register.
6301 Define constraints for the reload register and scratch register that contain
6302 a single register class. If the original reload register (whose class is
6303 RCLASS) can meet the constraint given in the pattern, the value returned by
6304 these macros is used for the class of the scratch register. Otherwise, two
6305 additional reload registers are required. Their classes are obtained from
6306 the constraints in the insn pattern.
6308 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6309 either be in a hard register or in memory. Use `true_regnum' to find out;
6310 it will return -1 if the pseudo is in memory and the hard register number if
6311 it is in a register.
6313 These macros should not be used in the case where a particular class of
6314 registers can only be copied to memory and not to another class of
6315 registers. In that case, secondary reload registers are not needed and
6316 would not be helpful. Instead, a stack location must be used to perform the
6317 copy and the `movM' pattern should use memory as an intermediate storage.
6318 This case often occurs between floating-point and general registers. */
6321 frv_secondary_reload_class (enum reg_class rclass
,
6322 machine_mode mode ATTRIBUTE_UNUSED
,
6333 /* Accumulators/Accumulator guard registers need to go through floating
6338 if (x
&& GET_CODE (x
) == REG
)
6340 int regno
= REGNO (x
);
6342 if (ACC_P (regno
) || ACCG_P (regno
))
6347 /* Nonzero constants should be loaded into an FPR through a GPR. */
6349 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
6355 /* All of these types need gpr registers. */
6367 /* The accumulators need fpr registers. */
6377 /* This hook exists to catch the case where secondary_reload_class() is
6378 called from init_reg_autoinc() in regclass.c - before the reload optabs
6379 have been initialised. */
6382 frv_secondary_reload (bool in_p
, rtx x
, reg_class_t reload_class_i
,
6383 machine_mode reload_mode
,
6384 secondary_reload_info
* sri
)
6386 enum reg_class rclass
= NO_REGS
;
6387 enum reg_class reload_class
= (enum reg_class
) reload_class_i
;
6389 if (sri
->prev_sri
&& sri
->prev_sri
->t_icode
!= CODE_FOR_nothing
)
6391 sri
->icode
= sri
->prev_sri
->t_icode
;
6395 rclass
= frv_secondary_reload_class (reload_class
, reload_mode
, x
);
6397 if (rclass
!= NO_REGS
)
6399 enum insn_code icode
6400 = direct_optab_handler (in_p
? reload_in_optab
: reload_out_optab
,
6404 /* This happens when then the reload_[in|out]_optabs have
6405 not been initialised. */
6406 sri
->t_icode
= CODE_FOR_nothing
;
6411 /* Fall back to the default secondary reload handler. */
6412 return default_secondary_reload (in_p
, x
, reload_class
, reload_mode
, sri
);
6416 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6419 frv_class_likely_spilled_p (reg_class_t rclass
)
6429 case FDPIC_FPTR_REGS
:
6449 /* An expression for the alignment of a structure field FIELD if the
6450 alignment computed in the usual way is COMPUTED. GCC uses this
6451 value instead of the value in `BIGGEST_ALIGNMENT' or
6452 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6454 /* The definition type of the bit field data is either char, short, long or
6455 long long. The maximum bit size is the number of bits of its own type.
6457 The bit field data is assigned to a storage unit that has an adequate size
6458 for bit field data retention and is located at the smallest address.
6460 Consecutive bit field data are packed at consecutive bits having the same
6461 storage unit, with regard to the type, beginning with the MSB and continuing
6464 If a field to be assigned lies over a bit field type boundary, its
6465 assignment is completed by aligning it with a boundary suitable for the
6468 When a bit field having a bit length of 0 is declared, it is forcibly
6469 assigned to the next storage unit.
6482 &x 00000000 00000000 00000000 00000000
6485 &x+4 00000000 00000000 00000000 00000000
6488 &x+8 00000000 00000000 00000000 00000000
6491 &x+12 00000000 00000000 00000000 00000000
6497 frv_adjust_field_align (tree field
, int computed
)
6499 /* Make sure that the bitfield is not wider than the type. */
6500 if (DECL_BIT_FIELD (field
)
6501 && !DECL_ARTIFICIAL (field
))
6503 tree parent
= DECL_CONTEXT (field
);
6504 tree prev
= NULL_TREE
;
6507 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= DECL_CHAIN (cur
))
6509 if (TREE_CODE (cur
) != FIELD_DECL
)
6517 /* If this isn't a :0 field and if the previous element is a bitfield
6518 also, see if the type is different, if so, we will need to align the
6519 bit-field to the next boundary. */
6521 && ! DECL_PACKED (field
)
6522 && ! integer_zerop (DECL_SIZE (field
))
6523 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
6525 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
6526 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
6527 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
6535 /* A C expression that is nonzero if it is permissible to store a value of mode
6536 MODE in hard register number REGNO (or in several registers starting with
6537 that one). For a machine where all registers are equivalent, a suitable
6540 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6542 It is not necessary for this macro to check for the numbers of fixed
6543 registers, because the allocation mechanism considers them to be always
6546 On some machines, double-precision values must be kept in even/odd register
6547 pairs. The way to implement that is to define this macro to reject odd
6548 register numbers for such modes.
6550 The minimum requirement for a mode to be OK in a register is that the
6551 `movMODE' instruction pattern support moves between the register and any
6552 other hard register for which the mode is OK; and that moving a value into
6553 the register and back out not alter it.
6555 Since the same instruction used to move `SImode' will work for all narrower
6556 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6557 to distinguish between these modes, provided you define patterns `movhi',
6558 etc., to take advantage of this. This is useful because of the interaction
6559 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6560 all integer modes to be tieable.
6562 Many machines have special registers for floating point arithmetic. Often
6563 people assume that floating point machine modes are allowed only in floating
6564 point registers. This is not true. Any registers that can hold integers
6565 can safely *hold* a floating point machine mode, whether or not floating
6566 arithmetic can be done on it in those registers. Integer move instructions
6567 can be used to move the values.
6569 On some machines, though, the converse is true: fixed-point machine modes
6570 may not go in floating registers. This is true if the floating registers
6571 normalize any value stored in them, because storing a non-floating value
6572 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6573 fixed-point machine modes in floating registers. But if the floating
6574 registers do not automatically normalize, if you can store any bit pattern
6575 in one and retrieve it unchanged without a trap, then any machine mode may
6576 go in a floating register, so you can define this macro to say so.
6578 The primary significance of special floating registers is rather that they
6579 are the registers acceptable in floating point arithmetic instructions.
6580 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6581 writing the proper constraints for those instructions.
6583 On some machines, the floating registers are especially slow to access, so
6584 that it is better to store a value in a stack frame than in such a register
6585 if floating point arithmetic is not being done. As long as the floating
6586 registers are not in class `GENERAL_REGS', they will not be used unless some
6587 pattern's constraint asks for one. */
6590 frv_hard_regno_mode_ok (int regno
, machine_mode mode
)
6600 return ICC_P (regno
) || GPR_P (regno
);
6603 return CR_P (regno
) || GPR_P (regno
);
6606 return FCC_P (regno
) || GPR_P (regno
);
6612 /* Set BASE to the first register in REGNO's class. Set MASK to the
6613 bits that must be clear in (REGNO - BASE) for the register to be
6615 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
6619 /* ACCGs store one byte. Two-byte quantities must start in
6620 even-numbered registers, four-byte ones in registers whose
6621 numbers are divisible by four, and so on. */
6623 mask
= GET_MODE_SIZE (mode
) - 1;
6627 /* The other registers store one word. */
6628 if (GPR_P (regno
) || regno
== AP_FIRST
)
6631 else if (FPR_P (regno
))
6634 else if (ACC_P (regno
))
6637 else if (SPR_P (regno
))
6638 return mode
== SImode
;
6640 /* Fill in the table. */
6644 /* Anything smaller than an SI is OK in any word-sized register. */
6645 if (GET_MODE_SIZE (mode
) < 4)
6648 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
6650 return (((regno
- base
) & mask
) == 0);
6657 /* A C expression for the number of consecutive hard registers, starting at
6658 register number REGNO, required to hold a value of mode MODE.
6660 On a machine where all registers are exactly one word, a suitable definition
6663 #define HARD_REGNO_NREGS(REGNO, MODE) \
6664 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6665 / UNITS_PER_WORD)) */
6667 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6668 that we can build the appropriate instructions to properly reload the
6669 values. Also, make the byte-sized accumulator guards use one guard
6673 frv_hard_regno_nregs (int regno
, machine_mode mode
)
6676 return GET_MODE_SIZE (mode
);
6678 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6682 /* A C expression for the maximum number of consecutive registers of
6683 class RCLASS needed to hold a value of mode MODE.
6685 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6686 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6687 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6689 This macro helps control the handling of multiple-word values in
6692 This declaration is required. */
6695 frv_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
6697 if (rclass
== ACCG_REGS
)
6698 /* An N-byte value requires N accumulator guards. */
6699 return GET_MODE_SIZE (mode
);
6701 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6705 /* A C expression that is nonzero if X is a legitimate constant for an
6706 immediate operand on the target machine. You can assume that X satisfies
6707 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6708 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6711 frv_legitimate_constant_p (machine_mode mode
, rtx x
)
6713 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6714 means that the move expanders will be expected to deal with most
6715 kinds of constant, regardless of what we return here.
6717 However, among its other duties, frv_legitimate_constant_p decides whether
6718 a constant can be entered into reg_equiv_constant[]. If we return true,
6719 reload can create new instances of the constant whenever it likes.
6721 The idea is therefore to accept as many constants as possible (to give
6722 reload more freedom) while rejecting constants that can only be created
6723 at certain times. In particular, anything with a symbolic component will
6724 require use of the pseudo FDPIC register, which is only available before
6727 return LEGITIMATE_PIC_OPERAND_P (x
);
6729 /* All of the integer constants are ok. */
6730 if (GET_CODE (x
) != CONST_DOUBLE
)
6733 /* double integer constants are ok. */
6734 if (GET_MODE (x
) == VOIDmode
|| mode
== DImode
)
6737 /* 0 is always ok. */
6738 if (x
== CONST0_RTX (mode
))
6741 /* If floating point is just emulated, allow any constant, since it will be
6742 constructed in the GPRs. */
6743 if (!TARGET_HAS_FPRS
)
6746 if (mode
== DFmode
&& !TARGET_DOUBLE
)
6749 /* Otherwise store the constant away and do a load. */
6753 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6754 CC_NZ for comparisons against zero in which a single Z or N flag test
6755 is enough, CC_UNS for other unsigned comparisons, and CC for other
6756 signed comparisons. */
6759 frv_select_cc_mode (enum rtx_code code
, rtx x
, rtx y
)
6761 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6770 return y
== const0_rtx
? CC_NZmode
: CCmode
;
6776 return y
== const0_rtx
? CC_NZmode
: CC_UNSmode
;
6784 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6786 #define HIGH_COST 40
6787 #define MEDIUM_COST 3
6791 frv_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
6792 reg_class_t from
, reg_class_t to
)
6805 case FDPIC_FPTR_REGS
:
6806 case FDPIC_CALL_REGS
:
6819 case FDPIC_FPTR_REGS
:
6820 case FDPIC_CALL_REGS
:
6845 case FDPIC_FPTR_REGS
:
6846 case FDPIC_CALL_REGS
:
6870 case FDPIC_FPTR_REGS
:
6871 case FDPIC_CALL_REGS
:
6892 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6895 frv_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
6896 reg_class_t rclass ATTRIBUTE_UNUSED
,
6897 bool in ATTRIBUTE_UNUSED
)
6903 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6904 use ".picptr" to generate safe relocations for PIC code. We also
6905 need a fixup entry for aligned (non-debugging) code. */
6908 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
6910 if ((flag_pic
|| TARGET_FDPIC
) && size
== UNITS_PER_WORD
)
6912 if (GET_CODE (value
) == CONST
6913 || GET_CODE (value
) == SYMBOL_REF
6914 || GET_CODE (value
) == LABEL_REF
)
6916 if (TARGET_FDPIC
&& GET_CODE (value
) == SYMBOL_REF
6917 && SYMBOL_REF_FUNCTION_P (value
))
6919 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
6920 output_addr_const (asm_out_file
, value
);
6921 fputs (")\n", asm_out_file
);
6924 else if (TARGET_FDPIC
&& GET_CODE (value
) == CONST
6925 && frv_function_symbol_referenced_p (value
))
6927 if (aligned_p
&& !TARGET_FDPIC
)
6929 static int label_num
= 0;
6933 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
6934 p
= (* targetm
.strip_name_encoding
) (buf
);
6936 fprintf (asm_out_file
, "%s:\n", p
);
6937 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
6938 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
6939 fprintf (asm_out_file
, "\t.previous\n");
6941 assemble_integer_with_op ("\t.picptr\t", value
);
6946 /* We've set the unaligned SI op to NULL, so we always have to
6947 handle the unaligned case here. */
6948 assemble_integer_with_op ("\t.4byte\t", value
);
6952 return default_assemble_integer (value
, size
, aligned_p
);
6955 /* Function to set up the backend function structure. */
6957 static struct machine_function
*
6958 frv_init_machine_status (void)
6960 return ggc_cleared_alloc
<machine_function
> ();
6963 /* Implement TARGET_SCHED_ISSUE_RATE. */
6966 frv_issue_rate (void)
6971 switch (frv_cpu_type
)
6975 case FRV_CPU_SIMPLE
:
6983 case FRV_CPU_GENERIC
:
6985 case FRV_CPU_TOMCAT
:
6993 /* Return the value of INSN's acc_group attribute. */
6996 frv_acc_group (rtx insn
)
6998 /* This distinction only applies to the FR550 packing constraints. */
6999 if (frv_cpu_type
== FRV_CPU_FR550
)
7001 subrtx_iterator::array_type array
;
7002 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
7005 unsigned int regno
= REGNO (*iter
);
7006 /* If REGNO refers to an accumulator, return ACC_GROUP_ODD if
7007 the bit 2 of the register number is set and ACC_GROUP_EVEN if
7010 return (regno
- ACC_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7012 return (regno
- ACCG_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7015 return ACC_GROUP_NONE
;
7018 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7019 INSN will try to claim first. Since this value depends only on the
7020 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7023 frv_insn_unit (rtx_insn
*insn
)
7025 enum attr_type type
;
7027 type
= get_attr_type (insn
);
7028 if (frv_type_to_unit
[type
] == ARRAY_SIZE (frv_unit_codes
))
7030 /* We haven't seen this type of instruction before. */
7034 /* Issue the instruction on its own to see which unit it prefers. */
7035 state
= alloca (state_size ());
7036 state_reset (state
);
7037 state_transition (state
, insn
);
7039 /* Find out which unit was taken. */
7040 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_codes
); unit
++)
7041 if (cpu_unit_reservation_p (state
, frv_unit_codes
[unit
]))
7044 gcc_assert (unit
!= ARRAY_SIZE (frv_unit_codes
));
7046 frv_type_to_unit
[type
] = unit
;
7048 return frv_type_to_unit
[type
];
7051 /* Return true if INSN issues to a branch unit. */
7054 frv_issues_to_branch_unit_p (rtx_insn
*insn
)
7056 return frv_unit_groups
[frv_insn_unit (insn
)] == GROUP_B
;
7059 /* The instructions in the packet, partitioned into groups. */
7060 struct frv_packet_group
{
7061 /* How many instructions in the packet belong to this group. */
7062 unsigned int num_insns
;
7064 /* A list of the instructions that belong to this group, in the order
7065 they appear in the rtl stream. */
7066 rtx_insn
*insns
[ARRAY_SIZE (frv_unit_codes
)];
7068 /* The contents of INSNS after they have been sorted into the correct
7069 assembly-language order. Element X issues to unit X. The list may
7070 contain extra nops. */
7071 rtx_insn
*sorted
[ARRAY_SIZE (frv_unit_codes
)];
7073 /* The member of frv_nops[] to use in sorted[]. */
7077 /* The current state of the packing pass, implemented by frv_pack_insns. */
7079 /* The state of the pipeline DFA. */
7082 /* Which hardware registers are set within the current packet,
7083 and the conditions under which they are set. */
7084 regstate_t regstate
[FIRST_PSEUDO_REGISTER
];
7086 /* The memory locations that have been modified so far in this
7087 packet. MEM is the memref and COND is the regstate_t condition
7088 under which it is set. */
7094 /* The number of valid entries in MEMS. The value is larger than
7095 ARRAY_SIZE (mems) if there were too many mems to record. */
7096 unsigned int num_mems
;
7098 /* The maximum number of instructions that can be packed together. */
7099 unsigned int issue_rate
;
7101 /* The instructions in the packet, partitioned into groups. */
7102 struct frv_packet_group groups
[NUM_GROUPS
];
7104 /* The instructions that make up the current packet. */
7105 rtx_insn
*insns
[ARRAY_SIZE (frv_unit_codes
)];
7106 unsigned int num_insns
;
7109 /* Return the regstate_t flags for the given COND_EXEC condition.
7110 Abort if the condition isn't in the right form. */
7113 frv_cond_flags (rtx cond
)
7115 gcc_assert ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
7116 && GET_CODE (XEXP (cond
, 0)) == REG
7117 && CR_P (REGNO (XEXP (cond
, 0)))
7118 && XEXP (cond
, 1) == const0_rtx
);
7119 return ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
7120 | (GET_CODE (cond
) == NE
7122 : REGSTATE_IF_FALSE
));
7126 /* Return true if something accessed under condition COND2 can
7127 conflict with something written under condition COND1. */
7130 frv_regstate_conflict_p (regstate_t cond1
, regstate_t cond2
)
7132 /* If either reference was unconditional, we have a conflict. */
7133 if ((cond1
& REGSTATE_IF_EITHER
) == 0
7134 || (cond2
& REGSTATE_IF_EITHER
) == 0)
7137 /* The references might conflict if they were controlled by
7139 if ((cond1
& REGSTATE_CC_MASK
) != (cond2
& REGSTATE_CC_MASK
))
7142 /* They definitely conflict if they are controlled by the
7144 if ((cond1
& cond2
& REGSTATE_IF_EITHER
) != 0)
7151 /* Return true if an instruction with pattern PAT depends on an
7152 instruction in the current packet. COND describes the condition
7153 under which PAT might be set or used. */
7156 frv_registers_conflict_p_1 (rtx pat
, regstate_t cond
)
7158 subrtx_var_iterator::array_type array
;
7159 FOR_EACH_SUBRTX_VAR (iter
, array
, pat
, NONCONST
)
7162 if (GET_CODE (x
) == REG
)
7165 FOR_EACH_REGNO (regno
, x
)
7166 if ((frv_packet
.regstate
[regno
] & REGSTATE_MODIFIED
) != 0)
7167 if (frv_regstate_conflict_p (frv_packet
.regstate
[regno
], cond
))
7170 else if (GET_CODE (x
) == MEM
)
7172 /* If we ran out of memory slots, assume a conflict. */
7173 if (frv_packet
.num_mems
> ARRAY_SIZE (frv_packet
.mems
))
7176 /* Check for output or true dependencies with earlier MEMs. */
7177 for (unsigned int i
= 0; i
< frv_packet
.num_mems
; i
++)
7178 if (frv_regstate_conflict_p (frv_packet
.mems
[i
].cond
, cond
))
7180 if (true_dependence (frv_packet
.mems
[i
].mem
, VOIDmode
, x
))
7183 if (output_dependence (frv_packet
.mems
[i
].mem
, x
))
7188 /* The return values of calls aren't significant: they describe
7189 the effect of the call as a whole, not of the insn itself. */
7190 else if (GET_CODE (x
) == SET
&& GET_CODE (SET_SRC (x
)) == CALL
)
7191 iter
.substitute (SET_SRC (x
));
7197 /* Return true if something in X might depend on an instruction
7198 in the current packet. */
7201 frv_registers_conflict_p (rtx x
)
7206 if (GET_CODE (x
) == COND_EXEC
)
7208 if (frv_registers_conflict_p_1 (XEXP (x
, 0), flags
))
7211 flags
|= frv_cond_flags (XEXP (x
, 0));
7214 return frv_registers_conflict_p_1 (x
, flags
);
7218 /* A note_stores callback. DATA points to the regstate_t condition
7219 under which X is modified. Update FRV_PACKET accordingly. */
7222 frv_registers_update_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7226 if (GET_CODE (x
) == REG
)
7227 FOR_EACH_REGNO (regno
, x
)
7228 frv_packet
.regstate
[regno
] |= *(regstate_t
*) data
;
7230 if (GET_CODE (x
) == MEM
)
7232 if (frv_packet
.num_mems
< ARRAY_SIZE (frv_packet
.mems
))
7234 frv_packet
.mems
[frv_packet
.num_mems
].mem
= x
;
7235 frv_packet
.mems
[frv_packet
.num_mems
].cond
= *(regstate_t
*) data
;
7237 frv_packet
.num_mems
++;
7242 /* Update the register state information for an instruction whose
7246 frv_registers_update (rtx x
)
7250 flags
= REGSTATE_MODIFIED
;
7251 if (GET_CODE (x
) == COND_EXEC
)
7253 flags
|= frv_cond_flags (XEXP (x
, 0));
7256 note_stores (x
, frv_registers_update_1
, &flags
);
7260 /* Initialize frv_packet for the start of a new packet. */
7263 frv_start_packet (void)
7265 enum frv_insn_group group
;
7267 memset (frv_packet
.regstate
, 0, sizeof (frv_packet
.regstate
));
7268 frv_packet
.num_mems
= 0;
7269 frv_packet
.num_insns
= 0;
7270 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7271 group
= (enum frv_insn_group
) (group
+ 1))
7272 frv_packet
.groups
[group
].num_insns
= 0;
7276 /* Likewise for the start of a new basic block. */
7279 frv_start_packet_block (void)
7281 state_reset (frv_packet
.dfa_state
);
7282 frv_start_packet ();
7286 /* Finish the current packet, if any, and start a new one. Call
7287 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7290 frv_finish_packet (void (*handle_packet
) (void))
7292 if (frv_packet
.num_insns
> 0)
7295 state_transition (frv_packet
.dfa_state
, 0);
7296 frv_start_packet ();
7301 /* Return true if INSN can be added to the current packet. Update
7302 the DFA state on success. */
7305 frv_pack_insn_p (rtx_insn
*insn
)
7307 /* See if the packet is already as long as it can be. */
7308 if (frv_packet
.num_insns
== frv_packet
.issue_rate
)
7311 /* If the scheduler thought that an instruction should start a packet,
7312 it's usually a good idea to believe it. It knows much more about
7313 the latencies than we do.
7315 There are some exceptions though:
7317 - Conditional instructions are scheduled on the assumption that
7318 they will be executed. This is usually a good thing, since it
7319 tends to avoid unnecessary stalls in the conditional code.
7320 But we want to pack conditional instructions as tightly as
7321 possible, in order to optimize the case where they aren't
7324 - The scheduler will always put branches on their own, even
7325 if there's no real dependency.
7327 - There's no point putting a call in its own packet unless
7329 if (frv_packet
.num_insns
> 0
7330 && NONJUMP_INSN_P (insn
)
7331 && GET_MODE (insn
) == TImode
7332 && GET_CODE (PATTERN (insn
)) != COND_EXEC
)
7335 /* Check for register conflicts. Don't do this for setlo since any
7336 conflict will be with the partnering sethi, with which it can
7338 if (get_attr_type (insn
) != TYPE_SETLO
)
7339 if (frv_registers_conflict_p (PATTERN (insn
)))
7342 return state_transition (frv_packet
.dfa_state
, insn
) < 0;
7346 /* Add instruction INSN to the current packet. */
7349 frv_add_insn_to_packet (rtx_insn
*insn
)
7351 struct frv_packet_group
*packet_group
;
7353 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7354 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7355 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7357 frv_registers_update (PATTERN (insn
));
7361 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7362 packet ends in a branch or call, insert the nop before it, otherwise
7366 frv_insert_nop_in_packet (rtx_insn
*insn
)
7368 struct frv_packet_group
*packet_group
;
7371 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7372 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
7373 if (! NONJUMP_INSN_P (last
))
7375 insn
= emit_insn_before (PATTERN (insn
), last
);
7376 frv_packet
.insns
[frv_packet
.num_insns
- 1] = insn
;
7377 frv_packet
.insns
[frv_packet
.num_insns
++] = last
;
7381 insn
= emit_insn_after (PATTERN (insn
), last
);
7382 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7384 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7388 /* If packing is enabled, divide the instructions into packets and
7389 return true. Call HANDLE_PACKET for each complete packet. */
7392 frv_for_each_packet (void (*handle_packet
) (void))
7394 rtx_insn
*insn
, *next_insn
;
7396 frv_packet
.issue_rate
= frv_issue_rate ();
7398 /* Early exit if we don't want to pack insns. */
7400 || !flag_schedule_insns_after_reload
7401 || !TARGET_VLIW_BRANCH
7402 || frv_packet
.issue_rate
== 1)
7405 /* Set up the initial packing state. */
7407 frv_packet
.dfa_state
= alloca (state_size ());
7409 frv_start_packet_block ();
7410 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
7415 code
= GET_CODE (insn
);
7416 next_insn
= NEXT_INSN (insn
);
7418 if (code
== CODE_LABEL
)
7420 frv_finish_packet (handle_packet
);
7421 frv_start_packet_block ();
7425 switch (GET_CODE (PATTERN (insn
)))
7432 /* Calls mustn't be packed on a TOMCAT. */
7433 if (CALL_P (insn
) && frv_cpu_type
== FRV_CPU_TOMCAT
)
7434 frv_finish_packet (handle_packet
);
7436 /* Since the last instruction in a packet determines the EH
7437 region, any exception-throwing instruction must come at
7438 the end of reordered packet. Insns that issue to a
7439 branch unit are bound to come last; for others it's
7440 too hard to predict. */
7441 eh_insn_p
= (find_reg_note (insn
, REG_EH_REGION
, NULL
) != NULL
);
7442 if (eh_insn_p
&& !frv_issues_to_branch_unit_p (insn
))
7443 frv_finish_packet (handle_packet
);
7445 /* Finish the current packet if we can't add INSN to it.
7446 Simulate cycles until INSN is ready to issue. */
7447 if (!frv_pack_insn_p (insn
))
7449 frv_finish_packet (handle_packet
);
7450 while (!frv_pack_insn_p (insn
))
7451 state_transition (frv_packet
.dfa_state
, 0);
7454 /* Add the instruction to the packet. */
7455 frv_add_insn_to_packet (insn
);
7457 /* Calls and jumps end a packet, as do insns that throw
7459 if (code
== CALL_INSN
|| code
== JUMP_INSN
|| eh_insn_p
)
7460 frv_finish_packet (handle_packet
);
7464 frv_finish_packet (handle_packet
);
7469 /* Subroutine of frv_sort_insn_group. We are trying to sort
7470 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7471 language order. We have already picked a new position for
7472 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7473 These instructions will occupy elements [0, LOWER_SLOT) and
7474 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7475 the DFA state after issuing these instructions.
7477 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7478 of the unused instructions. Return true if one such permutation gives
7479 a valid ordering, leaving the successful permutation in sorted[].
7480 Do not modify sorted[] until a valid permutation is found. */
7483 frv_sort_insn_group_1 (enum frv_insn_group group
,
7484 unsigned int lower_slot
, unsigned int upper_slot
,
7485 unsigned int issued
, unsigned int num_insns
,
7488 struct frv_packet_group
*packet_group
;
7494 /* Early success if we've filled all the slots. */
7495 if (lower_slot
== upper_slot
)
7498 packet_group
= &frv_packet
.groups
[group
];
7499 dfa_size
= state_size ();
7500 test_state
= alloca (dfa_size
);
7502 /* Try issuing each unused instruction. */
7503 for (i
= num_insns
- 1; i
+ 1 != 0; i
--)
7504 if (~issued
& (1 << i
))
7506 insn
= packet_group
->sorted
[i
];
7507 memcpy (test_state
, state
, dfa_size
);
7508 if (state_transition (test_state
, insn
) < 0
7509 && cpu_unit_reservation_p (test_state
,
7510 NTH_UNIT (group
, upper_slot
- 1))
7511 && frv_sort_insn_group_1 (group
, lower_slot
, upper_slot
- 1,
7512 issued
| (1 << i
), num_insns
,
7515 packet_group
->sorted
[upper_slot
- 1] = insn
;
7523 /* Compare two instructions by their frv_insn_unit. */
7526 frv_compare_insns (const void *first
, const void *second
)
7528 rtx_insn
* const *insn1
= (rtx_insn
* const *) first
;
7529 rtx_insn
* const *insn2
= (rtx_insn
* const *) second
;
7530 return frv_insn_unit (*insn1
) - frv_insn_unit (*insn2
);
7533 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7534 and sort it into assembly language order. See frv.md for a description of
7538 frv_sort_insn_group (enum frv_insn_group group
)
7540 struct frv_packet_group
*packet_group
;
7541 unsigned int first
, i
, nop
, max_unit
, num_slots
;
7542 state_t state
, test_state
;
7545 packet_group
= &frv_packet
.groups
[group
];
7547 /* Assume no nop is needed. */
7548 packet_group
->nop
= 0;
7550 if (packet_group
->num_insns
== 0)
7553 /* Copy insns[] to sorted[]. */
7554 memcpy (packet_group
->sorted
, packet_group
->insns
,
7555 sizeof (rtx
) * packet_group
->num_insns
);
7557 /* Sort sorted[] by the unit that each insn tries to take first. */
7558 if (packet_group
->num_insns
> 1)
7559 qsort (packet_group
->sorted
, packet_group
->num_insns
,
7560 sizeof (rtx
), frv_compare_insns
);
7562 /* That's always enough for branch and control insns. */
7563 if (group
== GROUP_B
|| group
== GROUP_C
)
7566 dfa_size
= state_size ();
7567 state
= alloca (dfa_size
);
7568 test_state
= alloca (dfa_size
);
7570 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7571 consecutively and such that the DFA takes unit X when sorted[X]
7572 is added. Set STATE to the new DFA state. */
7573 state_reset (test_state
);
7574 for (first
= 0; first
< packet_group
->num_insns
; first
++)
7576 memcpy (state
, test_state
, dfa_size
);
7577 if (state_transition (test_state
, packet_group
->sorted
[first
]) >= 0
7578 || !cpu_unit_reservation_p (test_state
, NTH_UNIT (group
, first
)))
7582 /* If all the instructions issued in ascending order, we're done. */
7583 if (first
== packet_group
->num_insns
)
7586 /* Add nops to the end of sorted[] and try each permutation until
7587 we find one that works. */
7588 for (nop
= 0; nop
< frv_num_nops
; nop
++)
7590 max_unit
= frv_insn_unit (frv_nops
[nop
]);
7591 if (frv_unit_groups
[max_unit
] == group
)
7593 packet_group
->nop
= frv_nops
[nop
];
7594 num_slots
= UNIT_NUMBER (max_unit
) + 1;
7595 for (i
= packet_group
->num_insns
; i
< num_slots
; i
++)
7596 packet_group
->sorted
[i
] = frv_nops
[nop
];
7597 if (frv_sort_insn_group_1 (group
, first
, num_slots
,
7598 (1 << first
) - 1, num_slots
, state
))
7605 /* Sort the current packet into assembly-language order. Set packing
7606 flags as appropriate. */
7609 frv_reorder_packet (void)
7611 unsigned int cursor
[NUM_GROUPS
];
7612 rtx insns
[ARRAY_SIZE (frv_unit_groups
)];
7613 unsigned int unit
, to
, from
;
7614 enum frv_insn_group group
;
7615 struct frv_packet_group
*packet_group
;
7617 /* First sort each group individually. */
7618 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7619 group
= (enum frv_insn_group
) (group
+ 1))
7622 frv_sort_insn_group (group
);
7625 /* Go through the unit template and try add an instruction from
7626 that unit's group. */
7628 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_groups
); unit
++)
7630 group
= frv_unit_groups
[unit
];
7631 packet_group
= &frv_packet
.groups
[group
];
7632 if (cursor
[group
] < packet_group
->num_insns
)
7634 /* frv_reorg should have added nops for us. */
7635 gcc_assert (packet_group
->sorted
[cursor
[group
]]
7636 != packet_group
->nop
);
7637 insns
[to
++] = packet_group
->sorted
[cursor
[group
]++];
7641 gcc_assert (to
== frv_packet
.num_insns
);
7643 /* Clear the last instruction's packing flag, thus marking the end of
7644 a packet. Reorder the other instructions relative to it. */
7645 CLEAR_PACKING_FLAG (insns
[to
- 1]);
7646 for (from
= 0; from
< to
- 1; from
++)
7648 remove_insn (insns
[from
]);
7649 add_insn_before (insns
[from
], insns
[to
- 1], NULL
);
7650 SET_PACKING_FLAG (insns
[from
]);
7655 /* Divide instructions into packets. Reorder the contents of each
7656 packet so that they are in the correct assembly-language order.
7658 Since this pass can change the raw meaning of the rtl stream, it must
7659 only be called at the last minute, just before the instructions are
7663 frv_pack_insns (void)
7665 if (frv_for_each_packet (frv_reorder_packet
))
7666 frv_insn_packing_flag
= 0;
7668 frv_insn_packing_flag
= -1;
7671 /* See whether we need to add nops to group GROUP in order to
7672 make a valid packet. */
7675 frv_fill_unused_units (enum frv_insn_group group
)
7677 unsigned int non_nops
, nops
, i
;
7678 struct frv_packet_group
*packet_group
;
7680 packet_group
= &frv_packet
.groups
[group
];
7682 /* Sort the instructions into assembly-language order.
7683 Use nops to fill slots that are otherwise unused. */
7684 frv_sort_insn_group (group
);
7686 /* See how many nops are needed before the final useful instruction. */
7688 for (non_nops
= 0; non_nops
< packet_group
->num_insns
; non_nops
++)
7689 while (packet_group
->sorted
[i
++] == packet_group
->nop
)
7692 /* Insert that many nops into the instruction stream. */
7694 frv_insert_nop_in_packet (packet_group
->nop
);
7697 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7700 frv_same_doubleword_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7702 if (io1
->const_address
!= 0 && io2
->const_address
!= 0)
7703 return io1
->const_address
== io2
->const_address
;
7705 if (io1
->var_address
!= 0 && io2
->var_address
!= 0)
7706 return rtx_equal_p (io1
->var_address
, io2
->var_address
);
7711 /* Return true if operations IO1 and IO2 are guaranteed to complete
7715 frv_io_fixed_order_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7717 /* The order of writes is always preserved. */
7718 if (io1
->type
== FRV_IO_WRITE
&& io2
->type
== FRV_IO_WRITE
)
7721 /* The order of reads isn't preserved. */
7722 if (io1
->type
!= FRV_IO_WRITE
&& io2
->type
!= FRV_IO_WRITE
)
7725 /* One operation is a write and the other is (or could be) a read.
7726 The order is only guaranteed if the accesses are to the same
7728 return frv_same_doubleword_p (io1
, io2
);
7731 /* Generalize I/O operation X so that it covers both X and Y. */
7734 frv_io_union (struct frv_io
*x
, const struct frv_io
*y
)
7736 if (x
->type
!= y
->type
)
7737 x
->type
= FRV_IO_UNKNOWN
;
7738 if (!frv_same_doubleword_p (x
, y
))
7740 x
->const_address
= 0;
7745 /* Fill IO with information about the load or store associated with
7746 membar instruction INSN. */
7749 frv_extract_membar (struct frv_io
*io
, rtx_insn
*insn
)
7751 extract_insn (insn
);
7752 io
->type
= (enum frv_io_type
) INTVAL (recog_data
.operand
[2]);
7753 io
->const_address
= INTVAL (recog_data
.operand
[1]);
7754 io
->var_address
= XEXP (recog_data
.operand
[0], 0);
7757 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7758 if X is a register and *DATA depends on X. */
7761 frv_io_check_address (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7763 rtx
*other
= (rtx
*) data
;
7765 if (REG_P (x
) && *other
!= 0 && reg_overlap_mentioned_p (x
, *other
))
7769 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7770 Remove every modified register from the set. */
7773 frv_io_handle_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7775 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7779 FOR_EACH_REGNO (regno
, x
)
7780 CLEAR_HARD_REG_BIT (*set
, regno
);
7783 /* A note_uses callback that adds all registers in *X to hard register
7787 frv_io_handle_use (rtx
*x
, void *data
)
7789 find_all_hard_regs (*x
, (HARD_REG_SET
*) data
);
7792 /* Go through block BB looking for membars to remove. There are two
7793 cases where intra-block analysis is enough:
7795 - a membar is redundant if it occurs between two consecutive I/O
7796 operations and if those operations are guaranteed to complete
7799 - a membar for a __builtin_read is redundant if the result is
7800 used before the next I/O operation is issued.
7802 If the last membar in the block could not be removed, and there
7803 are guaranteed to be no I/O operations between that membar and
7804 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7807 Describe the block's first I/O operation in *NEXT_IO. Describe
7808 an unknown operation if the block doesn't do any I/O. */
7811 frv_optimize_membar_local (basic_block bb
, struct frv_io
*next_io
,
7812 rtx_insn
**last_membar
)
7814 HARD_REG_SET used_regs
;
7815 rtx next_membar
, set
;
7819 /* NEXT_IO is the next I/O operation to be performed after the current
7820 instruction. It starts off as being an unknown operation. */
7821 memset (next_io
, 0, sizeof (*next_io
));
7823 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7824 next_is_end_p
= true;
7826 /* If the current instruction is a __builtin_read or __builtin_write,
7827 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7828 is null if the membar has already been deleted.
7830 Note that the initialization here should only be needed to
7831 suppress warnings. */
7834 /* USED_REGS is the set of registers that are used before the
7835 next I/O instruction. */
7836 CLEAR_HARD_REG_SET (used_regs
);
7838 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
); insn
= PREV_INSN (insn
))
7841 /* We can't predict what a call will do to volatile memory. */
7842 memset (next_io
, 0, sizeof (struct frv_io
));
7843 next_is_end_p
= false;
7844 CLEAR_HARD_REG_SET (used_regs
);
7846 else if (INSN_P (insn
))
7847 switch (recog_memoized (insn
))
7849 case CODE_FOR_optional_membar_qi
:
7850 case CODE_FOR_optional_membar_hi
:
7851 case CODE_FOR_optional_membar_si
:
7852 case CODE_FOR_optional_membar_di
:
7856 /* Local information isn't enough to decide whether this
7857 membar is needed. Stash it away for later. */
7858 *last_membar
= insn
;
7859 frv_extract_membar (next_io
, insn
);
7860 next_is_end_p
= false;
7864 /* Check whether the I/O operation before INSN could be
7865 reordered with one described by NEXT_IO. If it can't,
7866 INSN will not be needed. */
7867 struct frv_io prev_io
;
7869 frv_extract_membar (&prev_io
, insn
);
7870 if (frv_io_fixed_order_p (&prev_io
, next_io
))
7874 ";; [Local] Removing membar %d since order"
7875 " of accesses is guaranteed\n",
7876 INSN_UID (next_membar
));
7878 insn
= NEXT_INSN (insn
);
7879 delete_insn (next_membar
);
7887 /* Invalidate NEXT_IO's address if it depends on something that
7888 is clobbered by INSN. */
7889 if (next_io
->var_address
)
7890 note_stores (PATTERN (insn
), frv_io_check_address
,
7891 &next_io
->var_address
);
7893 /* If the next membar is associated with a __builtin_read,
7894 see if INSN reads from that address. If it does, and if
7895 the destination register is used before the next I/O access,
7896 there is no need for the membar. */
7897 set
= PATTERN (insn
);
7898 if (next_io
->type
== FRV_IO_READ
7899 && next_io
->var_address
!= 0
7901 && GET_CODE (set
) == SET
7902 && GET_CODE (SET_DEST (set
)) == REG
7903 && TEST_HARD_REG_BIT (used_regs
, REGNO (SET_DEST (set
))))
7907 src
= SET_SRC (set
);
7908 if (GET_CODE (src
) == ZERO_EXTEND
)
7909 src
= XEXP (src
, 0);
7911 if (GET_CODE (src
) == MEM
7912 && rtx_equal_p (XEXP (src
, 0), next_io
->var_address
))
7916 ";; [Local] Removing membar %d since the target"
7917 " of %d is used before the I/O operation\n",
7918 INSN_UID (next_membar
), INSN_UID (insn
));
7920 if (next_membar
== *last_membar
)
7923 delete_insn (next_membar
);
7928 /* If INSN has volatile references, forget about any registers
7929 that are used after it. Otherwise forget about uses that
7930 are (or might be) defined by INSN. */
7931 if (volatile_refs_p (PATTERN (insn
)))
7932 CLEAR_HARD_REG_SET (used_regs
);
7934 note_stores (PATTERN (insn
), frv_io_handle_set
, &used_regs
);
7936 note_uses (&PATTERN (insn
), frv_io_handle_use
, &used_regs
);
7941 /* See if MEMBAR, the last membar instruction in BB, can be removed.
7942 FIRST_IO[X] describes the first operation performed by basic block X. */
7945 frv_optimize_membar_global (basic_block bb
, struct frv_io
*first_io
,
7948 struct frv_io this_io
, next_io
;
7952 /* We need to keep the membar if there is an edge to the exit block. */
7953 FOR_EACH_EDGE (succ
, ei
, bb
->succs
)
7954 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
7955 if (succ
->dest
== EXIT_BLOCK_PTR_FOR_FN (cfun
))
7958 /* Work out the union of all successor blocks. */
7959 ei
= ei_start (bb
->succs
);
7960 ei_cond (ei
, &succ
);
7961 /* next_io = first_io[bb->succ->dest->index]; */
7962 next_io
= first_io
[succ
->dest
->index
];
7963 ei
= ei_start (bb
->succs
);
7964 if (ei_cond (ei
, &succ
))
7966 for (ei_next (&ei
); ei_cond (ei
, &succ
); ei_next (&ei
))
7967 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
7968 frv_io_union (&next_io
, &first_io
[succ
->dest
->index
]);
7973 frv_extract_membar (&this_io
, membar
);
7974 if (frv_io_fixed_order_p (&this_io
, &next_io
))
7978 ";; [Global] Removing membar %d since order of accesses"
7979 " is guaranteed\n", INSN_UID (membar
));
7981 delete_insn (membar
);
7985 /* Remove redundant membars from the current function. */
7988 frv_optimize_membar (void)
7991 struct frv_io
*first_io
;
7992 rtx_insn
**last_membar
;
7994 compute_bb_for_insn ();
7995 first_io
= XCNEWVEC (struct frv_io
, last_basic_block_for_fn (cfun
));
7996 last_membar
= XCNEWVEC (rtx_insn
*, last_basic_block_for_fn (cfun
));
7998 FOR_EACH_BB_FN (bb
, cfun
)
7999 frv_optimize_membar_local (bb
, &first_io
[bb
->index
],
8000 &last_membar
[bb
->index
]);
8002 FOR_EACH_BB_FN (bb
, cfun
)
8003 if (last_membar
[bb
->index
] != 0)
8004 frv_optimize_membar_global (bb
, first_io
, last_membar
[bb
->index
]);
8010 /* Used by frv_reorg to keep track of the current packet's address. */
8011 static unsigned int frv_packet_address
;
8013 /* If the current packet falls through to a label, try to pad the packet
8014 with nops in order to fit the label's alignment requirements. */
8017 frv_align_label (void)
8019 unsigned int alignment
, target
, nop
;
8020 rtx_insn
*x
, *last
, *barrier
, *label
;
8022 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8023 maximum alignment of that packet, LABEL to the last label between
8024 the packets, and BARRIER to the last barrier. */
8025 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8026 label
= barrier
= 0;
8028 for (x
= NEXT_INSN (last
); x
!= 0 && !INSN_P (x
); x
= NEXT_INSN (x
))
8032 unsigned int subalign
= 1 << label_to_alignment (x
);
8033 alignment
= MAX (alignment
, subalign
);
8040 /* If -malign-labels, and the packet falls through to an unaligned
8041 label, try introducing a nop to align that label to 8 bytes. */
8042 if (TARGET_ALIGN_LABELS
8045 && frv_packet
.num_insns
< frv_packet
.issue_rate
)
8046 alignment
= MAX (alignment
, 8);
8048 /* Advance the address to the end of the current packet. */
8049 frv_packet_address
+= frv_packet
.num_insns
* 4;
8051 /* Work out the target address, after alignment. */
8052 target
= (frv_packet_address
+ alignment
- 1) & -alignment
;
8054 /* If the packet falls through to the label, try to find an efficient
8055 padding sequence. */
8058 /* First try adding nops to the current packet. */
8059 for (nop
= 0; nop
< frv_num_nops
; nop
++)
8060 while (frv_packet_address
< target
&& frv_pack_insn_p (frv_nops
[nop
]))
8062 frv_insert_nop_in_packet (frv_nops
[nop
]);
8063 frv_packet_address
+= 4;
8066 /* If we still haven't reached the target, add some new packets that
8067 contain only nops. If there are two types of nop, insert an
8068 alternating sequence of frv_nops[0] and frv_nops[1], which will
8069 lead to packets like:
8076 etc. Just emit frv_nops[0] if that's the only nop we have. */
8077 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8079 while (frv_packet_address
< target
)
8081 last
= emit_insn_after (PATTERN (frv_nops
[nop
]), last
);
8082 frv_packet_address
+= 4;
8083 if (frv_num_nops
> 1)
8088 frv_packet_address
= target
;
8091 /* Subroutine of frv_reorg, called after each packet has been constructed
8095 frv_reorg_packet (void)
8097 frv_fill_unused_units (GROUP_I
);
8098 frv_fill_unused_units (GROUP_FM
);
8102 /* Add an instruction with pattern NOP to frv_nops[]. */
8105 frv_register_nop (rtx nop
)
8107 rtx_insn
*nop_insn
= make_insn_raw (nop
);
8108 SET_NEXT_INSN (nop_insn
) = 0;
8109 SET_PREV_INSN (nop_insn
) = 0;
8110 frv_nops
[frv_num_nops
++] = nop_insn
;
8113 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8114 into packets and check whether we need to insert nops in order to
8115 fulfill the processor's issue requirements. Also, if the user has
8116 requested a certain alignment for a label, try to meet that alignment
8117 by inserting nops in the previous packet. */
8122 if (optimize
> 0 && TARGET_OPTIMIZE_MEMBAR
&& cfun
->machine
->has_membar_p
)
8123 frv_optimize_membar ();
8126 frv_register_nop (gen_nop ());
8128 frv_register_nop (gen_mnop ());
8129 if (TARGET_HARD_FLOAT
)
8130 frv_register_nop (gen_fnop ());
8132 /* Estimate the length of each branch. Although this may change after
8133 we've inserted nops, it will only do so in big functions. */
8134 shorten_branches (get_insns ());
8136 frv_packet_address
= 0;
8137 frv_for_each_packet (frv_reorg_packet
);
8140 #define def_builtin(name, type, code) \
8141 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8143 struct builtin_description
8145 enum insn_code icode
;
8147 enum frv_builtins code
;
8148 enum rtx_code comparison
;
8152 /* Media intrinsics that take a single, constant argument. */
8154 static struct builtin_description bdesc_set
[] =
8156 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, UNKNOWN
, 0 }
8159 /* Media intrinsics that take just one argument. */
8161 static struct builtin_description bdesc_1arg
[] =
8163 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, UNKNOWN
, 0 },
8164 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, UNKNOWN
, 0 },
8165 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, UNKNOWN
, 0 },
8166 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, UNKNOWN
, 0},
8167 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, UNKNOWN
, 0 },
8168 { CODE_FOR_scutss
, "__SCUTSS", FRV_BUILTIN_SCUTSS
, UNKNOWN
, 0 }
8171 /* Media intrinsics that take two arguments. */
8173 static struct builtin_description bdesc_2arg
[] =
8175 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, UNKNOWN
, 0},
8176 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, UNKNOWN
, 0},
8177 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, UNKNOWN
, 0},
8178 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, UNKNOWN
, 0},
8179 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, UNKNOWN
, 0},
8180 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, UNKNOWN
, 0},
8181 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, UNKNOWN
, 0},
8182 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, UNKNOWN
, 0},
8183 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, UNKNOWN
, 0},
8184 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, UNKNOWN
, 0},
8185 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, UNKNOWN
, 0},
8186 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, UNKNOWN
, 0},
8187 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, UNKNOWN
, 0},
8188 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, UNKNOWN
, 0},
8189 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, UNKNOWN
, 0},
8190 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, UNKNOWN
, 0},
8191 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, UNKNOWN
, 0},
8192 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, UNKNOWN
, 0},
8193 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, UNKNOWN
, 0},
8194 { CODE_FOR_mqlclrhs
, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS
, UNKNOWN
, 0},
8195 { CODE_FOR_mqlmths
, "__MQLMTHS", FRV_BUILTIN_MQLMTHS
, UNKNOWN
, 0},
8196 { CODE_FOR_smul
, "__SMUL", FRV_BUILTIN_SMUL
, UNKNOWN
, 0},
8197 { CODE_FOR_umul
, "__UMUL", FRV_BUILTIN_UMUL
, UNKNOWN
, 0},
8198 { CODE_FOR_addss
, "__ADDSS", FRV_BUILTIN_ADDSS
, UNKNOWN
, 0},
8199 { CODE_FOR_subss
, "__SUBSS", FRV_BUILTIN_SUBSS
, UNKNOWN
, 0},
8200 { CODE_FOR_slass
, "__SLASS", FRV_BUILTIN_SLASS
, UNKNOWN
, 0},
8201 { CODE_FOR_scan
, "__SCAN", FRV_BUILTIN_SCAN
, UNKNOWN
, 0}
8204 /* Integer intrinsics that take two arguments and have no return value. */
8206 static struct builtin_description bdesc_int_void2arg
[] =
8208 { CODE_FOR_smass
, "__SMASS", FRV_BUILTIN_SMASS
, UNKNOWN
, 0},
8209 { CODE_FOR_smsss
, "__SMSSS", FRV_BUILTIN_SMSSS
, UNKNOWN
, 0},
8210 { CODE_FOR_smu
, "__SMU", FRV_BUILTIN_SMU
, UNKNOWN
, 0}
8213 static struct builtin_description bdesc_prefetches
[] =
8215 { CODE_FOR_frv_prefetch0
, "__data_prefetch0", FRV_BUILTIN_PREFETCH0
, UNKNOWN
,
8217 { CODE_FOR_frv_prefetch
, "__data_prefetch", FRV_BUILTIN_PREFETCH
, UNKNOWN
, 0}
8220 /* Media intrinsics that take two arguments, the first being an ACC number. */
8222 static struct builtin_description bdesc_cut
[] =
8224 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, UNKNOWN
, 0},
8225 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, UNKNOWN
, 0},
8226 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, UNKNOWN
, 0}
8229 /* Two-argument media intrinsics with an immediate second argument. */
8231 static struct builtin_description bdesc_2argimm
[] =
8233 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, UNKNOWN
, 0},
8234 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, UNKNOWN
, 0},
8235 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, UNKNOWN
, 0},
8236 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, UNKNOWN
, 0},
8237 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, UNKNOWN
, 0},
8238 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, UNKNOWN
, 0},
8239 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, UNKNOWN
, 0},
8240 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, UNKNOWN
, 0},
8241 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, UNKNOWN
, 0},
8242 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, UNKNOWN
, 0},
8243 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, UNKNOWN
, 0},
8244 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, UNKNOWN
, 0},
8245 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, UNKNOWN
, 0},
8246 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, UNKNOWN
, 0},
8247 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, UNKNOWN
, 0},
8248 { CODE_FOR_mqsllhi
, "__MQSLLHI", FRV_BUILTIN_MQSLLHI
, UNKNOWN
, 0},
8249 { CODE_FOR_mqsrahi
, "__MQSRAHI", FRV_BUILTIN_MQSRAHI
, UNKNOWN
, 0}
8252 /* Media intrinsics that take two arguments and return void, the first argument
8253 being a pointer to 4 words in memory. */
8255 static struct builtin_description bdesc_void2arg
[] =
8257 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, UNKNOWN
, 0},
8258 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, UNKNOWN
, 0},
8261 /* Media intrinsics that take three arguments, the first being a const_int that
8262 denotes an accumulator, and that return void. */
8264 static struct builtin_description bdesc_void3arg
[] =
8266 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, UNKNOWN
, 0},
8267 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, UNKNOWN
, 0},
8268 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, UNKNOWN
, 0},
8269 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, UNKNOWN
, 0},
8270 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, UNKNOWN
, 0},
8271 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, UNKNOWN
, 0},
8272 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, UNKNOWN
, 0},
8273 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, UNKNOWN
, 0},
8274 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, UNKNOWN
, 0},
8275 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, UNKNOWN
, 0},
8276 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, UNKNOWN
, 0},
8277 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, UNKNOWN
, 0},
8278 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, UNKNOWN
, 0},
8279 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, UNKNOWN
, 0},
8280 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, UNKNOWN
, 0},
8281 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, UNKNOWN
, 0},
8282 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, UNKNOWN
, 0},
8283 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, UNKNOWN
, 0},
8284 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, UNKNOWN
, 0},
8285 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, UNKNOWN
, 0},
8286 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, UNKNOWN
, 0},
8287 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, UNKNOWN
, 0},
8288 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, UNKNOWN
, 0},
8289 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, UNKNOWN
, 0},
8290 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, UNKNOWN
, 0}
8293 /* Media intrinsics that take two accumulator numbers as argument and
8296 static struct builtin_description bdesc_voidacc
[] =
8298 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, UNKNOWN
, 0},
8299 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, UNKNOWN
, 0},
8300 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, UNKNOWN
, 0},
8301 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, UNKNOWN
, 0},
8302 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, UNKNOWN
, 0},
8303 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, UNKNOWN
, 0}
8306 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8307 a normal move and the ICODE is for the membar. */
8309 static struct builtin_description bdesc_loads
[] =
8311 { CODE_FOR_optional_membar_qi
, "__builtin_read8",
8312 FRV_BUILTIN_READ8
, UNKNOWN
, 0},
8313 { CODE_FOR_optional_membar_hi
, "__builtin_read16",
8314 FRV_BUILTIN_READ16
, UNKNOWN
, 0},
8315 { CODE_FOR_optional_membar_si
, "__builtin_read32",
8316 FRV_BUILTIN_READ32
, UNKNOWN
, 0},
8317 { CODE_FOR_optional_membar_di
, "__builtin_read64",
8318 FRV_BUILTIN_READ64
, UNKNOWN
, 0}
8321 /* Likewise stores. */
8323 static struct builtin_description bdesc_stores
[] =
8325 { CODE_FOR_optional_membar_qi
, "__builtin_write8",
8326 FRV_BUILTIN_WRITE8
, UNKNOWN
, 0},
8327 { CODE_FOR_optional_membar_hi
, "__builtin_write16",
8328 FRV_BUILTIN_WRITE16
, UNKNOWN
, 0},
8329 { CODE_FOR_optional_membar_si
, "__builtin_write32",
8330 FRV_BUILTIN_WRITE32
, UNKNOWN
, 0},
8331 { CODE_FOR_optional_membar_di
, "__builtin_write64",
8332 FRV_BUILTIN_WRITE64
, UNKNOWN
, 0},
8335 /* Initialize media builtins. */
8338 frv_init_builtins (void)
8340 tree accumulator
= integer_type_node
;
8341 tree integer
= integer_type_node
;
8342 tree voidt
= void_type_node
;
8343 tree uhalf
= short_unsigned_type_node
;
8344 tree sword1
= long_integer_type_node
;
8345 tree uword1
= long_unsigned_type_node
;
8346 tree sword2
= long_long_integer_type_node
;
8347 tree uword2
= long_long_unsigned_type_node
;
8348 tree uword4
= build_pointer_type (uword1
);
8349 tree vptr
= build_pointer_type (build_type_variant (void_type_node
, 0, 1));
8350 tree ubyte
= unsigned_char_type_node
;
8351 tree iacc
= integer_type_node
;
8353 #define UNARY(RET, T1) \
8354 build_function_type_list (RET, T1, NULL_TREE)
8356 #define BINARY(RET, T1, T2) \
8357 build_function_type_list (RET, T1, T2, NULL_TREE)
8359 #define TRINARY(RET, T1, T2, T3) \
8360 build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8362 #define QUAD(RET, T1, T2, T3, T4) \
8363 build_function_type_list (RET, T1, T2, T3, T4, NULL_TREE)
8365 tree void_ftype_void
= build_function_type_list (voidt
, NULL_TREE
);
8367 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
8368 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
8369 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
8370 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
8371 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
8372 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
8373 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
8374 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
8375 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
8377 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
8378 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
8379 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
8380 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
8381 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
8382 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
8383 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
8384 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
8385 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
8386 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
8387 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
8389 tree sw1_ftype_int
= UNARY (sword1
, integer
);
8390 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
8391 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
8393 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
8394 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
8395 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
8396 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
8397 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
8398 tree uw2_ftype_uh_uh_uh_uh
= QUAD (uword2
, uhalf
, uhalf
, uhalf
, uhalf
);
8400 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
8401 tree sw2_ftype_sw2_int
= BINARY (sword2
, sword2
, integer
);
8402 tree uw2_ftype_uw1_uw1
= BINARY (uword2
, uword1
, uword1
);
8403 tree sw2_ftype_sw1_sw1
= BINARY (sword2
, sword1
, sword1
);
8404 tree void_ftype_sw1_sw1
= BINARY (voidt
, sword1
, sword1
);
8405 tree void_ftype_iacc_sw2
= BINARY (voidt
, iacc
, sword2
);
8406 tree void_ftype_iacc_sw1
= BINARY (voidt
, iacc
, sword1
);
8407 tree sw1_ftype_sw1
= UNARY (sword1
, sword1
);
8408 tree sw2_ftype_iacc
= UNARY (sword2
, iacc
);
8409 tree sw1_ftype_iacc
= UNARY (sword1
, iacc
);
8410 tree void_ftype_ptr
= UNARY (voidt
, const_ptr_type_node
);
8411 tree uw1_ftype_vptr
= UNARY (uword1
, vptr
);
8412 tree uw2_ftype_vptr
= UNARY (uword2
, vptr
);
8413 tree void_ftype_vptr_ub
= BINARY (voidt
, vptr
, ubyte
);
8414 tree void_ftype_vptr_uh
= BINARY (voidt
, vptr
, uhalf
);
8415 tree void_ftype_vptr_uw1
= BINARY (voidt
, vptr
, uword1
);
8416 tree void_ftype_vptr_uw2
= BINARY (voidt
, vptr
, uword2
);
8418 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
8419 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
8420 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
8421 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
8422 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
8423 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
8424 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
8425 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
8426 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
8427 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
8428 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
8429 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
8430 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
8431 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
8432 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
8433 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
8434 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
8435 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
8436 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
8437 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
8438 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
8439 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
8440 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
8441 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
8442 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
8443 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
8444 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
8445 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
8446 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
8447 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
8448 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
8449 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
8450 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
8451 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
8452 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
8453 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
8454 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
8455 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
8456 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
8457 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
8458 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
8459 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
8460 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
8461 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
8462 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
8463 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
8464 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
8465 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
8466 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
8467 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh
, FRV_BUILTIN_MDPACKH
);
8468 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
8469 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
8470 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
8471 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
8472 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
8473 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
8474 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
8475 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
8476 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
8477 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
8478 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
8479 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
8480 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
8481 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
8482 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
8483 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
8484 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
8485 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
8486 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
8487 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
8488 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
8489 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
8490 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
8491 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
8492 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
8493 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
8494 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
8495 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
8496 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
8497 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
8498 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
8499 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
8500 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
8501 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
8502 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLCLRHS
);
8503 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLMTHS
);
8504 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int
, FRV_BUILTIN_MQSLLHI
);
8505 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int
, FRV_BUILTIN_MQSRAHI
);
8506 def_builtin ("__SMUL", sw2_ftype_sw1_sw1
, FRV_BUILTIN_SMUL
);
8507 def_builtin ("__UMUL", uw2_ftype_uw1_uw1
, FRV_BUILTIN_UMUL
);
8508 def_builtin ("__SMASS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMASS
);
8509 def_builtin ("__SMSSS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMSSS
);
8510 def_builtin ("__SMU", void_ftype_sw1_sw1
, FRV_BUILTIN_SMU
);
8511 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_ADDSS
);
8512 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SUBSS
);
8513 def_builtin ("__SLASS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SLASS
);
8514 def_builtin ("__SCAN", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SCAN
);
8515 def_builtin ("__SCUTSS", sw1_ftype_sw1
, FRV_BUILTIN_SCUTSS
);
8516 def_builtin ("__IACCreadll", sw2_ftype_iacc
, FRV_BUILTIN_IACCreadll
);
8517 def_builtin ("__IACCreadl", sw1_ftype_iacc
, FRV_BUILTIN_IACCreadl
);
8518 def_builtin ("__IACCsetll", void_ftype_iacc_sw2
, FRV_BUILTIN_IACCsetll
);
8519 def_builtin ("__IACCsetl", void_ftype_iacc_sw1
, FRV_BUILTIN_IACCsetl
);
8520 def_builtin ("__data_prefetch0", void_ftype_ptr
, FRV_BUILTIN_PREFETCH0
);
8521 def_builtin ("__data_prefetch", void_ftype_ptr
, FRV_BUILTIN_PREFETCH
);
8522 def_builtin ("__builtin_read8", uw1_ftype_vptr
, FRV_BUILTIN_READ8
);
8523 def_builtin ("__builtin_read16", uw1_ftype_vptr
, FRV_BUILTIN_READ16
);
8524 def_builtin ("__builtin_read32", uw1_ftype_vptr
, FRV_BUILTIN_READ32
);
8525 def_builtin ("__builtin_read64", uw2_ftype_vptr
, FRV_BUILTIN_READ64
);
8527 def_builtin ("__builtin_write8", void_ftype_vptr_ub
, FRV_BUILTIN_WRITE8
);
8528 def_builtin ("__builtin_write16", void_ftype_vptr_uh
, FRV_BUILTIN_WRITE16
);
8529 def_builtin ("__builtin_write32", void_ftype_vptr_uw1
, FRV_BUILTIN_WRITE32
);
8530 def_builtin ("__builtin_write64", void_ftype_vptr_uw2
, FRV_BUILTIN_WRITE64
);
8538 /* Set the names for various arithmetic operations according to the
8541 frv_init_libfuncs (void)
8543 set_optab_libfunc (smod_optab
, SImode
, "__modi");
8544 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
8546 set_optab_libfunc (add_optab
, DImode
, "__addll");
8547 set_optab_libfunc (sub_optab
, DImode
, "__subll");
8548 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
8549 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
8550 set_optab_libfunc (smod_optab
, DImode
, "__modll");
8551 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
8552 set_optab_libfunc (and_optab
, DImode
, "__andll");
8553 set_optab_libfunc (ior_optab
, DImode
, "__orll");
8554 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
8555 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
8557 set_optab_libfunc (add_optab
, SFmode
, "__addf");
8558 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
8559 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
8560 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
8562 set_optab_libfunc (add_optab
, DFmode
, "__addd");
8563 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
8564 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
8565 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
8567 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
8568 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
8570 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
8571 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8572 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
8573 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8575 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
8576 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8577 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
8578 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8580 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
8581 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
8582 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
8583 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
8586 /* Convert an integer constant to an accumulator register. ICODE is the
8587 code of the target instruction, OPNUM is the number of the
8588 accumulator operand and OPVAL is the constant integer. Try both
8589 ACC and ACCG registers; only report an error if neither fit the
8593 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
8598 /* ACCs and ACCGs are implicit global registers if media intrinsics
8599 are being used. We set up this lazily to avoid creating lots of
8600 unnecessary call_insn rtl in non-media code. */
8601 for (i
= 0; i
<= ACC_MASK
; i
++)
8602 if ((i
& ACC_MASK
) == i
)
8603 global_regs
[i
+ ACC_FIRST
] = global_regs
[i
+ ACCG_FIRST
] = 1;
8605 if (GET_CODE (opval
) != CONST_INT
)
8607 error ("accumulator is not a constant integer");
8610 if ((INTVAL (opval
) & ~ACC_MASK
) != 0)
8612 error ("accumulator number is out of bounds");
8616 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
8617 ACC_FIRST
+ INTVAL (opval
));
8618 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8619 SET_REGNO (reg
, ACCG_FIRST
+ INTVAL (opval
));
8621 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8623 error ("inappropriate accumulator for %qs", insn_data
[icode
].name
);
8629 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8633 frv_matching_accg_mode (machine_mode mode
)
8651 /* Given that a __builtin_read or __builtin_write function is accessing
8652 address ADDRESS, return the value that should be used as operand 1
8656 frv_io_address_cookie (rtx address
)
8658 return (GET_CODE (address
) == CONST_INT
8659 ? GEN_INT (INTVAL (address
) / 8 * 8)
8663 /* Return the accumulator guard that should be paired with accumulator
8664 register ACC. The mode of the returned register is in the same
8665 class as ACC, but is four times smaller. */
8668 frv_matching_accg_for_acc (rtx acc
)
8670 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
8671 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
8674 /* Read the requested argument from the call EXP given by INDEX.
8675 Return the value as an rtx. */
8678 frv_read_argument (tree exp
, unsigned int index
)
8680 return expand_normal (CALL_EXPR_ARG (exp
, index
));
8683 /* Like frv_read_argument, but interpret the argument as the number
8684 of an IACC register and return a (reg:MODE ...) rtx for it. */
8687 frv_read_iacc_argument (machine_mode mode
, tree call
,
8693 op
= frv_read_argument (call
, index
);
8694 if (GET_CODE (op
) != CONST_INT
8696 || INTVAL (op
) > IACC_LAST
- IACC_FIRST
8697 || ((INTVAL (op
) * 4) & (GET_MODE_SIZE (mode
) - 1)) != 0)
8699 error ("invalid IACC argument");
8703 /* IACCs are implicit global registers. We set up this lazily to
8704 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8706 regno
= INTVAL (op
) + IACC_FIRST
;
8707 for (i
= 0; i
< HARD_REGNO_NREGS (regno
, mode
); i
++)
8708 global_regs
[regno
+ i
] = 1;
8710 return gen_rtx_REG (mode
, regno
);
8713 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8714 The instruction should require a constant operand of some sort. The
8715 function prints an error if OPVAL is not valid. */
8718 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
8720 if (GET_CODE (opval
) != CONST_INT
)
8722 error ("%qs expects a constant argument", insn_data
[icode
].name
);
8725 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
8727 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
8733 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8734 if it's not null, has the right mode, and satisfies operand 0's
8738 frv_legitimize_target (enum insn_code icode
, rtx target
)
8740 machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
8743 || GET_MODE (target
) != mode
8744 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
8745 return gen_reg_rtx (mode
);
8750 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8751 check whether ARG satisfies the operand's constraints. If it doesn't,
8752 copy ARG to a temporary register and return that. Otherwise return ARG
8756 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
8758 machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
8760 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
8763 return copy_to_mode_reg (mode
, arg
);
8766 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8769 frv_volatile_memref (machine_mode mode
, rtx arg
)
8773 mem
= gen_rtx_MEM (mode
, memory_address (mode
, arg
));
8774 MEM_VOLATILE_P (mem
) = 1;
8778 /* Expand builtins that take a single, constant argument. At the moment,
8779 only MHDSETS falls into this category. */
8782 frv_expand_set_builtin (enum insn_code icode
, tree call
, rtx target
)
8785 rtx op0
= frv_read_argument (call
, 0);
8787 if (! frv_check_constant_argument (icode
, 1, op0
))
8790 target
= frv_legitimize_target (icode
, target
);
8791 pat
= GEN_FCN (icode
) (target
, op0
);
8799 /* Expand builtins that take one operand. */
8802 frv_expand_unop_builtin (enum insn_code icode
, tree call
, rtx target
)
8805 rtx op0
= frv_read_argument (call
, 0);
8807 target
= frv_legitimize_target (icode
, target
);
8808 op0
= frv_legitimize_argument (icode
, 1, op0
);
8809 pat
= GEN_FCN (icode
) (target
, op0
);
8817 /* Expand builtins that take two operands. */
8820 frv_expand_binop_builtin (enum insn_code icode
, tree call
, rtx target
)
8823 rtx op0
= frv_read_argument (call
, 0);
8824 rtx op1
= frv_read_argument (call
, 1);
8826 target
= frv_legitimize_target (icode
, target
);
8827 op0
= frv_legitimize_argument (icode
, 1, op0
);
8828 op1
= frv_legitimize_argument (icode
, 2, op1
);
8829 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8837 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8841 frv_expand_cut_builtin (enum insn_code icode
, tree call
, rtx target
)
8844 rtx op0
= frv_read_argument (call
, 0);
8845 rtx op1
= frv_read_argument (call
, 1);
8848 target
= frv_legitimize_target (icode
, target
);
8849 op0
= frv_int_to_acc (icode
, 1, op0
);
8853 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
8855 if (! frv_check_constant_argument (icode
, 2, op1
))
8859 op1
= frv_legitimize_argument (icode
, 2, op1
);
8861 op2
= frv_matching_accg_for_acc (op0
);
8862 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8870 /* Expand builtins that take two operands and the second is immediate. */
8873 frv_expand_binopimm_builtin (enum insn_code icode
, tree call
, rtx target
)
8876 rtx op0
= frv_read_argument (call
, 0);
8877 rtx op1
= frv_read_argument (call
, 1);
8879 if (! frv_check_constant_argument (icode
, 2, op1
))
8882 target
= frv_legitimize_target (icode
, target
);
8883 op0
= frv_legitimize_argument (icode
, 1, op0
);
8884 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8892 /* Expand builtins that take two operands, the first operand being a pointer to
8893 ints and return void. */
8896 frv_expand_voidbinop_builtin (enum insn_code icode
, tree call
)
8899 rtx op0
= frv_read_argument (call
, 0);
8900 rtx op1
= frv_read_argument (call
, 1);
8901 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8904 if (GET_CODE (op0
) != MEM
)
8908 if (! offsettable_address_p (0, mode0
, op0
))
8910 reg
= gen_reg_rtx (Pmode
);
8911 emit_insn (gen_rtx_SET (reg
, op0
));
8914 op0
= gen_rtx_MEM (SImode
, reg
);
8917 addr
= XEXP (op0
, 0);
8918 if (! offsettable_address_p (0, mode0
, addr
))
8919 addr
= copy_to_mode_reg (Pmode
, op0
);
8921 op0
= change_address (op0
, V4SImode
, addr
);
8922 op1
= frv_legitimize_argument (icode
, 1, op1
);
8923 pat
= GEN_FCN (icode
) (op0
, op1
);
8931 /* Expand builtins that take two long operands and return void. */
8934 frv_expand_int_void2arg (enum insn_code icode
, tree call
)
8937 rtx op0
= frv_read_argument (call
, 0);
8938 rtx op1
= frv_read_argument (call
, 1);
8940 op0
= frv_legitimize_argument (icode
, 1, op0
);
8941 op1
= frv_legitimize_argument (icode
, 1, op1
);
8942 pat
= GEN_FCN (icode
) (op0
, op1
);
8950 /* Expand prefetch builtins. These take a single address as argument. */
8953 frv_expand_prefetches (enum insn_code icode
, tree call
)
8956 rtx op0
= frv_read_argument (call
, 0);
8958 pat
= GEN_FCN (icode
) (force_reg (Pmode
, op0
));
8966 /* Expand builtins that take three operands and return void. The first
8967 argument must be a constant that describes a pair or quad accumulators. A
8968 fourth argument is created that is the accumulator guard register that
8969 corresponds to the accumulator. */
8972 frv_expand_voidtriop_builtin (enum insn_code icode
, tree call
)
8975 rtx op0
= frv_read_argument (call
, 0);
8976 rtx op1
= frv_read_argument (call
, 1);
8977 rtx op2
= frv_read_argument (call
, 2);
8980 op0
= frv_int_to_acc (icode
, 0, op0
);
8984 op1
= frv_legitimize_argument (icode
, 1, op1
);
8985 op2
= frv_legitimize_argument (icode
, 2, op2
);
8986 op3
= frv_matching_accg_for_acc (op0
);
8987 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
8995 /* Expand builtins that perform accumulator-to-accumulator operations.
8996 These builtins take two accumulator numbers as argument and return
9000 frv_expand_voidaccop_builtin (enum insn_code icode
, tree call
)
9003 rtx op0
= frv_read_argument (call
, 0);
9004 rtx op1
= frv_read_argument (call
, 1);
9008 op0
= frv_int_to_acc (icode
, 0, op0
);
9012 op1
= frv_int_to_acc (icode
, 1, op1
);
9016 op2
= frv_matching_accg_for_acc (op0
);
9017 op3
= frv_matching_accg_for_acc (op1
);
9018 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9026 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9027 membar and TARGET_MODE is the mode that the loaded value should have. */
9030 frv_expand_load_builtin (enum insn_code icode
, machine_mode target_mode
,
9031 tree call
, rtx target
)
9033 rtx op0
= frv_read_argument (call
, 0);
9034 rtx cookie
= frv_io_address_cookie (op0
);
9036 if (target
== 0 || !REG_P (target
))
9037 target
= gen_reg_rtx (target_mode
);
9038 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9039 convert_move (target
, op0
, 1);
9040 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_READ
)));
9041 cfun
->machine
->has_membar_p
= 1;
9045 /* Likewise __builtin_write* functions. */
9048 frv_expand_store_builtin (enum insn_code icode
, tree call
)
9050 rtx op0
= frv_read_argument (call
, 0);
9051 rtx op1
= frv_read_argument (call
, 1);
9052 rtx cookie
= frv_io_address_cookie (op0
);
9054 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9055 convert_move (op0
, force_reg (insn_data
[icode
].operand
[0].mode
, op1
), 1);
9056 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_WRITE
)));
9057 cfun
->machine
->has_membar_p
= 1;
9061 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9062 each argument forms one word of the two double-word input registers.
9063 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9064 to put the return value. */
9067 frv_expand_mdpackh_builtin (tree call
, rtx target
)
9069 enum insn_code icode
= CODE_FOR_mdpackh
;
9071 rtx arg1
= frv_read_argument (call
, 0);
9072 rtx arg2
= frv_read_argument (call
, 1);
9073 rtx arg3
= frv_read_argument (call
, 2);
9074 rtx arg4
= frv_read_argument (call
, 3);
9076 target
= frv_legitimize_target (icode
, target
);
9077 op0
= gen_reg_rtx (DImode
);
9078 op1
= gen_reg_rtx (DImode
);
9080 /* The high half of each word is not explicitly initialized, so indicate
9081 that the input operands are not live before this point. */
9085 /* Move each argument into the low half of its associated input word. */
9086 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 2), arg1
);
9087 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 6), arg2
);
9088 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 2), arg3
);
9089 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 6), arg4
);
9091 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9099 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9100 number as argument. */
9103 frv_expand_mclracc_builtin (tree call
)
9105 enum insn_code icode
= CODE_FOR_mclracc
;
9107 rtx op0
= frv_read_argument (call
, 0);
9109 op0
= frv_int_to_acc (icode
, 0, op0
);
9113 pat
= GEN_FCN (icode
) (op0
);
9120 /* Expand builtins that take no arguments. */
9123 frv_expand_noargs_builtin (enum insn_code icode
)
9125 rtx pat
= GEN_FCN (icode
) (const0_rtx
);
9132 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9133 number or accumulator guard number as argument and return an SI integer. */
9136 frv_expand_mrdacc_builtin (enum insn_code icode
, tree call
)
9139 rtx target
= gen_reg_rtx (SImode
);
9140 rtx op0
= frv_read_argument (call
, 0);
9142 op0
= frv_int_to_acc (icode
, 1, op0
);
9146 pat
= GEN_FCN (icode
) (target
, op0
);
9154 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9155 accumulator guard as their first argument and an SImode value as their
9159 frv_expand_mwtacc_builtin (enum insn_code icode
, tree call
)
9162 rtx op0
= frv_read_argument (call
, 0);
9163 rtx op1
= frv_read_argument (call
, 1);
9165 op0
= frv_int_to_acc (icode
, 0, op0
);
9169 op1
= frv_legitimize_argument (icode
, 1, op1
);
9170 pat
= GEN_FCN (icode
) (op0
, op1
);
9177 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9178 to move DImode values into and out of IACC0. */
9181 frv_split_iacc_move (rtx dest
, rtx src
)
9186 inner
= GET_MODE (dest
);
9187 for (i
= 0; i
< GET_MODE_SIZE (inner
); i
+= GET_MODE_SIZE (SImode
))
9188 emit_move_insn (simplify_gen_subreg (SImode
, dest
, inner
, i
),
9189 simplify_gen_subreg (SImode
, src
, inner
, i
));
9192 /* Expand builtins. */
9195 frv_expand_builtin (tree exp
,
9197 rtx subtarget ATTRIBUTE_UNUSED
,
9198 machine_mode mode ATTRIBUTE_UNUSED
,
9199 int ignore ATTRIBUTE_UNUSED
)
9201 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9202 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9204 struct builtin_description
*d
;
9206 if (fcode
< FRV_BUILTIN_FIRST_NONMEDIA
&& !TARGET_MEDIA
)
9208 error ("media functions are not available unless -mmedia is used");
9214 case FRV_BUILTIN_MCOP1
:
9215 case FRV_BUILTIN_MCOP2
:
9216 case FRV_BUILTIN_MDUNPACKH
:
9217 case FRV_BUILTIN_MBTOHE
:
9218 if (! TARGET_MEDIA_REV1
)
9220 error ("this media function is only available on the fr500");
9225 case FRV_BUILTIN_MQXMACHS
:
9226 case FRV_BUILTIN_MQXMACXHS
:
9227 case FRV_BUILTIN_MQMACXHS
:
9228 case FRV_BUILTIN_MADDACCS
:
9229 case FRV_BUILTIN_MSUBACCS
:
9230 case FRV_BUILTIN_MASACCS
:
9231 case FRV_BUILTIN_MDADDACCS
:
9232 case FRV_BUILTIN_MDSUBACCS
:
9233 case FRV_BUILTIN_MDASACCS
:
9234 case FRV_BUILTIN_MABSHS
:
9235 case FRV_BUILTIN_MDROTLI
:
9236 case FRV_BUILTIN_MCPLHI
:
9237 case FRV_BUILTIN_MCPLI
:
9238 case FRV_BUILTIN_MDCUTSSI
:
9239 case FRV_BUILTIN_MQSATHS
:
9240 case FRV_BUILTIN_MHSETLOS
:
9241 case FRV_BUILTIN_MHSETLOH
:
9242 case FRV_BUILTIN_MHSETHIS
:
9243 case FRV_BUILTIN_MHSETHIH
:
9244 case FRV_BUILTIN_MHDSETS
:
9245 case FRV_BUILTIN_MHDSETH
:
9246 if (! TARGET_MEDIA_REV2
)
9248 error ("this media function is only available on the fr400"
9254 case FRV_BUILTIN_SMASS
:
9255 case FRV_BUILTIN_SMSSS
:
9256 case FRV_BUILTIN_SMU
:
9257 case FRV_BUILTIN_ADDSS
:
9258 case FRV_BUILTIN_SUBSS
:
9259 case FRV_BUILTIN_SLASS
:
9260 case FRV_BUILTIN_SCUTSS
:
9261 case FRV_BUILTIN_IACCreadll
:
9262 case FRV_BUILTIN_IACCreadl
:
9263 case FRV_BUILTIN_IACCsetll
:
9264 case FRV_BUILTIN_IACCsetl
:
9265 if (!TARGET_FR405_BUILTINS
)
9267 error ("this builtin function is only available"
9268 " on the fr405 and fr450");
9273 case FRV_BUILTIN_PREFETCH
:
9274 if (!TARGET_FR500_FR550_BUILTINS
)
9276 error ("this builtin function is only available on the fr500"
9282 case FRV_BUILTIN_MQLCLRHS
:
9283 case FRV_BUILTIN_MQLMTHS
:
9284 case FRV_BUILTIN_MQSLLHI
:
9285 case FRV_BUILTIN_MQSRAHI
:
9286 if (!TARGET_MEDIA_FR450
)
9288 error ("this builtin function is only available on the fr450");
9297 /* Expand unique builtins. */
9301 case FRV_BUILTIN_MTRAP
:
9302 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9304 case FRV_BUILTIN_MCLRACC
:
9305 return frv_expand_mclracc_builtin (exp
);
9307 case FRV_BUILTIN_MCLRACCA
:
9309 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9311 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9313 case FRV_BUILTIN_MRDACC
:
9314 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, exp
);
9316 case FRV_BUILTIN_MRDACCG
:
9317 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, exp
);
9319 case FRV_BUILTIN_MWTACC
:
9320 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, exp
);
9322 case FRV_BUILTIN_MWTACCG
:
9323 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, exp
);
9325 case FRV_BUILTIN_MDPACKH
:
9326 return frv_expand_mdpackh_builtin (exp
, target
);
9328 case FRV_BUILTIN_IACCreadll
:
9330 rtx src
= frv_read_iacc_argument (DImode
, exp
, 0);
9331 if (target
== 0 || !REG_P (target
))
9332 target
= gen_reg_rtx (DImode
);
9333 frv_split_iacc_move (target
, src
);
9337 case FRV_BUILTIN_IACCreadl
:
9338 return frv_read_iacc_argument (SImode
, exp
, 0);
9340 case FRV_BUILTIN_IACCsetll
:
9342 rtx dest
= frv_read_iacc_argument (DImode
, exp
, 0);
9343 rtx src
= frv_read_argument (exp
, 1);
9344 frv_split_iacc_move (dest
, force_reg (DImode
, src
));
9348 case FRV_BUILTIN_IACCsetl
:
9350 rtx dest
= frv_read_iacc_argument (SImode
, exp
, 0);
9351 rtx src
= frv_read_argument (exp
, 1);
9352 emit_move_insn (dest
, force_reg (SImode
, src
));
9360 /* Expand groups of builtins. */
9362 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9363 if (d
->code
== fcode
)
9364 return frv_expand_set_builtin (d
->icode
, exp
, target
);
9366 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9367 if (d
->code
== fcode
)
9368 return frv_expand_unop_builtin (d
->icode
, exp
, target
);
9370 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9371 if (d
->code
== fcode
)
9372 return frv_expand_binop_builtin (d
->icode
, exp
, target
);
9374 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9375 if (d
->code
== fcode
)
9376 return frv_expand_cut_builtin (d
->icode
, exp
, target
);
9378 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9379 if (d
->code
== fcode
)
9380 return frv_expand_binopimm_builtin (d
->icode
, exp
, target
);
9382 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9383 if (d
->code
== fcode
)
9384 return frv_expand_voidbinop_builtin (d
->icode
, exp
);
9386 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9387 if (d
->code
== fcode
)
9388 return frv_expand_voidtriop_builtin (d
->icode
, exp
);
9390 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9391 if (d
->code
== fcode
)
9392 return frv_expand_voidaccop_builtin (d
->icode
, exp
);
9394 for (i
= 0, d
= bdesc_int_void2arg
;
9395 i
< ARRAY_SIZE (bdesc_int_void2arg
); i
++, d
++)
9396 if (d
->code
== fcode
)
9397 return frv_expand_int_void2arg (d
->icode
, exp
);
9399 for (i
= 0, d
= bdesc_prefetches
;
9400 i
< ARRAY_SIZE (bdesc_prefetches
); i
++, d
++)
9401 if (d
->code
== fcode
)
9402 return frv_expand_prefetches (d
->icode
, exp
);
9404 for (i
= 0, d
= bdesc_loads
; i
< ARRAY_SIZE (bdesc_loads
); i
++, d
++)
9405 if (d
->code
== fcode
)
9406 return frv_expand_load_builtin (d
->icode
, TYPE_MODE (TREE_TYPE (exp
)),
9409 for (i
= 0, d
= bdesc_stores
; i
< ARRAY_SIZE (bdesc_stores
); i
++, d
++)
9410 if (d
->code
== fcode
)
9411 return frv_expand_store_builtin (d
->icode
, exp
);
9417 frv_in_small_data_p (const_tree decl
)
9420 const char *section_name
;
9422 /* Don't apply the -G flag to internal compiler structures. We
9423 should leave such structures in the main data section, partly
9424 for efficiency and partly because the size of some of them
9425 (such as C++ typeinfos) is not known until later. */
9426 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9429 /* If we already know which section the decl should be in, see if
9430 it's a small data section. */
9431 section_name
= DECL_SECTION_NAME (decl
);
9434 if (frv_string_begins_with (section_name
, ".sdata"))
9436 if (frv_string_begins_with (section_name
, ".sbss"))
9441 size
= int_size_in_bytes (TREE_TYPE (decl
));
9442 if (size
> 0 && size
<= g_switch_value
)
9449 frv_rtx_costs (rtx x
,
9452 int opno ATTRIBUTE_UNUSED
,
9454 bool speed ATTRIBUTE_UNUSED
)
9456 int code
= GET_CODE (x
);
9458 if (outer_code
== MEM
)
9460 /* Don't differentiate between memory addresses. All the ones
9461 we accept have equal cost. */
9462 *total
= COSTS_N_INSNS (0);
9469 /* Make 12-bit integers really cheap. */
9470 if (IN_RANGE (INTVAL (x
), -2048, 2047))
9481 *total
= COSTS_N_INSNS (2);
9496 *total
= COSTS_N_INSNS (1);
9497 else if (mode
== DImode
)
9498 *total
= COSTS_N_INSNS (2);
9500 *total
= COSTS_N_INSNS (3);
9505 *total
= COSTS_N_INSNS (2);
9507 *total
= COSTS_N_INSNS (6); /* guess */
9514 *total
= COSTS_N_INSNS (18);
9518 *total
= COSTS_N_INSNS (3);
9527 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9529 switch_to_section (ctors_section
);
9530 assemble_align (POINTER_SIZE
);
9533 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9538 assemble_integer_with_op ("\t.picptr\t", symbol
);
9542 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9544 switch_to_section (dtors_section
);
9545 assemble_align (POINTER_SIZE
);
9548 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9553 assemble_integer_with_op ("\t.picptr\t", symbol
);
9556 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9559 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9560 int incoming ATTRIBUTE_UNUSED
)
9562 return gen_rtx_REG (Pmode
, FRV_STRUCT_VALUE_REGNUM
);
9565 #define TLS_BIAS (2048 - 16)
9567 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9568 We need to emit DTP-relative relocations. */
9571 frv_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9573 gcc_assert (size
== 4);
9574 fputs ("\t.picptr\ttlsmoff(", file
);
9575 /* We want the unbiased TLS offset, so add the bias to the
9576 expression, such that the implicit biasing cancels out. */
9577 output_addr_const (file
, plus_constant (Pmode
, x
, TLS_BIAS
));