1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
47 #include "target-def.h"
50 #define FRV_INLINE inline
53 /* Temporary register allocation support structure. */
54 typedef struct frv_tmp_reg_struct
56 HARD_REG_SET regs
; /* possible registers to allocate */
57 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
61 /* Register state information for VLIW re-packing phase. These values must fit
62 within an unsigned char. */
63 #define REGSTATE_DEAD 0x00 /* register is currently dead */
64 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
65 #define REGSTATE_LIVE 0x08 /* register is live */
66 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
67 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
68 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
69 #define REGSTATE_UNUSED 0x80 /* bit for hire */
70 #define REGSTATE_MASK 0xff /* mask for the bits to set */
72 /* conditional expression used */
73 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
75 /* the following is not sure in the reg_state bytes, so can have a larger value
77 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
79 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
87 /* Information required by frv_frame_access. */
90 /* This field is FRV_LOAD if registers are to be loaded from the stack and
91 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
92 the move is being done by the prologue code while FRV_LOAD implies it
93 is being done by the epilogue. */
96 /* The base register to use when accessing the stack. This may be the
97 frame pointer, stack pointer, or a temporary. The choice of register
98 depends on which part of the frame is being accessed and how big the
102 /* The offset of BASE from the bottom of the current frame, in bytes. */
104 } frv_frame_accessor_t
;
106 /* Define the information needed to generate branch and scc insns. This is
107 stored from the compare operation. */
111 /* Conditional execution support gathered together in one structure */
114 /* Linked list of insns to add if the conditional execution conversion was
115 successful. Each link points to an EXPR_LIST which points to the pattern
116 of the insn to add, and the insn to be inserted before. */
117 rtx added_insns_list
;
119 /* Identify which registers are safe to allocate for if conversions to
120 conditional execution. We keep the last allocated register in the
121 register classes between COND_EXEC statements. This will mean we allocate
122 different registers for each different COND_EXEC group if we can. This
123 might allow the scheduler to intermix two different COND_EXEC sections. */
124 frv_tmp_reg_t tmp_reg
;
126 /* For nested IFs, identify which CC registers are used outside of setting
127 via a compare isnsn, and using via a check insn. This will allow us to
128 know if we can rewrite the register to use a different register that will
129 be paired with the CR register controlling the nested IF-THEN blocks. */
130 HARD_REG_SET nested_cc_ok_rewrite
;
132 /* Temporary registers allocated to hold constants during conditional
134 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
136 /* Current number of temp registers available. */
137 int cur_scratch_regs
;
139 /* Number of nested conditional execution blocks */
140 int num_nested_cond_exec
;
142 /* Map of insns that set up constants in scratch registers. */
143 bitmap scratch_insns_bitmap
;
145 /* Conditional execution test register (CC0..CC7) */
148 /* Conditional execution compare register that is paired with cr_reg, so that
149 nested compares can be done. The csubcc and caddcc instructions don't
150 have enough bits to specify both a CC register to be set and a CR register
151 to do the test on, so the same bit number is used for both. Needless to
152 say, this is rather inconvient for GCC. */
155 /* Extra CR registers used for &&, ||. */
159 /* Previous CR used in nested if, to make sure we are dealing with the same
160 nested if as the previous statement. */
161 rtx last_nested_if_cr
;
165 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
167 /* Map register number to smallest register class. */
168 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
170 /* Map class letter into register class */
171 enum reg_class reg_class_from_letter
[256];
173 /* Cached value of frv_stack_info */
174 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
176 /* -mbranch-cost= support */
177 const char *frv_branch_cost_string
;
178 int frv_branch_cost_int
= DEFAULT_BRANCH_COST
;
181 const char *frv_cpu_string
; /* -mcpu= option */
182 frv_cpu_t frv_cpu_type
= CPU_TYPE
; /* value of -mcpu= */
184 /* -mcond-exec-insns= support */
185 const char *frv_condexec_insns_str
; /* -mcond-exec-insns= option */
186 int frv_condexec_insns
= DEFAULT_CONDEXEC_INSNS
; /* value of -mcond-exec-insns*/
188 /* -mcond-exec-temps= support */
189 const char *frv_condexec_temps_str
; /* -mcond-exec-temps= option */
190 int frv_condexec_temps
= DEFAULT_CONDEXEC_TEMPS
; /* value of -mcond-exec-temps*/
192 /* -msched-lookahead=n */
193 const char *frv_sched_lookahead_str
; /* -msched-lookahead=n */
194 int frv_sched_lookahead
= 4; /* -msched-lookahead=n */
196 /* Forward references */
197 static int frv_default_flags_for_cpu
PARAMS ((void));
198 static int frv_string_begins_with
PARAMS ((tree
, const char *));
199 static FRV_INLINE
int symbol_ref_small_data_p
PARAMS ((rtx
));
200 static FRV_INLINE
int const_small_data_p
PARAMS ((rtx
));
201 static FRV_INLINE
int plus_small_data_p
PARAMS ((rtx
, rtx
));
202 static void frv_print_operand_memory_reference_reg
203 PARAMS ((FILE *, rtx
));
204 static void frv_print_operand_memory_reference
PARAMS ((FILE *, rtx
, int));
205 static int frv_print_operand_jump_hint
PARAMS ((rtx
));
206 static FRV_INLINE
int frv_regno_ok_for_base_p
PARAMS ((int, int));
207 static rtx single_set_pattern
PARAMS ((rtx
));
208 static int frv_function_contains_far_jump
PARAMS ((void));
209 static rtx frv_alloc_temp_reg
PARAMS ((frv_tmp_reg_t
*,
213 static rtx frv_frame_offset_rtx
PARAMS ((int));
214 static rtx frv_frame_mem
PARAMS ((enum machine_mode
,
216 static rtx frv_dwarf_store
PARAMS ((rtx
, int));
217 static void frv_frame_insn
PARAMS ((rtx
, rtx
));
218 static void frv_frame_access
PARAMS ((frv_frame_accessor_t
*,
220 static void frv_frame_access_multi
PARAMS ((frv_frame_accessor_t
*,
221 frv_stack_t
*, int));
222 static void frv_frame_access_standard_regs
PARAMS ((enum frv_stack_op
,
224 static struct machine_function
*frv_init_machine_status
PARAMS ((void));
225 static int frv_legitimate_memory_operand
PARAMS ((rtx
,
228 static rtx frv_int_to_acc
PARAMS ((enum insn_code
,
230 static enum machine_mode frv_matching_accg_mode
PARAMS ((enum machine_mode
));
231 static rtx frv_read_argument
PARAMS ((tree
*));
232 static int frv_check_constant_argument
PARAMS ((enum insn_code
,
234 static rtx frv_legitimize_target
PARAMS ((enum insn_code
, rtx
));
235 static rtx frv_legitimize_argument
PARAMS ((enum insn_code
,
237 static rtx frv_expand_set_builtin
PARAMS ((enum insn_code
,
239 static rtx frv_expand_unop_builtin
PARAMS ((enum insn_code
,
241 static rtx frv_expand_binop_builtin
PARAMS ((enum insn_code
,
243 static rtx frv_expand_cut_builtin
PARAMS ((enum insn_code
,
245 static rtx frv_expand_binopimm_builtin
PARAMS ((enum insn_code
,
247 static rtx frv_expand_voidbinop_builtin
PARAMS ((enum insn_code
,
249 static rtx frv_expand_voidtriop_builtin
PARAMS ((enum insn_code
,
251 static rtx frv_expand_voidaccop_builtin
PARAMS ((enum insn_code
,
253 static rtx frv_expand_mclracc_builtin
PARAMS ((tree
));
254 static rtx frv_expand_mrdacc_builtin
PARAMS ((enum insn_code
,
256 static rtx frv_expand_mwtacc_builtin
PARAMS ((enum insn_code
,
258 static rtx frv_expand_noargs_builtin
PARAMS ((enum insn_code
));
259 static rtx frv_emit_comparison
PARAMS ((enum rtx_code
, rtx
,
261 static int frv_clear_registers_used
PARAMS ((rtx
*, void *));
262 static void frv_ifcvt_add_insn
PARAMS ((rtx
, rtx
, int));
263 static rtx frv_ifcvt_rewrite_mem
PARAMS ((rtx
,
266 static rtx frv_ifcvt_load_value
PARAMS ((rtx
, rtx
));
267 static void frv_registers_update
PARAMS ((rtx
, unsigned char [],
268 int [], int *, int));
269 static int frv_registers_used_p
PARAMS ((rtx
, unsigned char [],
271 static int frv_registers_set_p
PARAMS ((rtx
, unsigned char [],
273 static void frv_pack_insns
PARAMS ((void));
274 static void frv_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
275 static void frv_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
276 static bool frv_assemble_integer
PARAMS ((rtx
, unsigned, int));
277 static const char * frv_strip_name_encoding
PARAMS ((const char *));
278 static void frv_encode_section_info
PARAMS ((tree
, int));
279 static void frv_init_builtins
PARAMS ((void));
280 static rtx frv_expand_builtin
PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
281 static bool frv_in_small_data_p
PARAMS ((tree
));
282 static void frv_asm_output_mi_thunk
283 PARAMS ((FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
));
285 /* Initialize the GCC target structure. */
286 #undef TARGET_ASM_FUNCTION_PROLOGUE
287 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
288 #undef TARGET_ASM_FUNCTION_EPILOGUE
289 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
290 #undef TARGET_ASM_INTEGER
291 #define TARGET_ASM_INTEGER frv_assemble_integer
292 #undef TARGET_STRIP_NAME_ENCODING
293 #define TARGET_STRIP_NAME_ENCODING frv_strip_name_encoding
294 #undef TARGET_ENCODE_SECTION_INFO
295 #define TARGET_ENCODE_SECTION_INFO frv_encode_section_info
296 #undef TARGET_INIT_BUILTINS
297 #define TARGET_INIT_BUILTINS frv_init_builtins
298 #undef TARGET_EXPAND_BUILTIN
299 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
300 #undef TARGET_IN_SMALL_DATA_P
301 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
303 #undef TARGET_ASM_OUTPUT_MI_THUNK
304 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
305 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
306 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
308 struct gcc_target targetm
= TARGET_INITIALIZER
;
310 /* Given a SYMBOL_REF, return true if it points to small data. */
312 static FRV_INLINE
int
313 symbol_ref_small_data_p (x
)
316 return SDATA_NAME_P (XSTR (x
, 0));
319 /* Given a CONST, return true if the symbol_ref points to small data. */
321 static FRV_INLINE
int
322 const_small_data_p (x
)
327 if (GET_CODE (XEXP (x
, 0)) != PLUS
)
330 x0
= XEXP (XEXP (x
, 0), 0);
331 if (GET_CODE (x0
) != SYMBOL_REF
|| !SDATA_NAME_P (XSTR (x0
, 0)))
334 x1
= XEXP (XEXP (x
, 0), 1);
335 if (GET_CODE (x1
) != CONST_INT
336 || !IN_RANGE_P (INTVAL (x1
), -2048, 2047))
342 /* Given a PLUS, return true if this is a small data reference. */
344 static FRV_INLINE
int
345 plus_small_data_p (op0
, op1
)
349 if (GET_MODE (op0
) == SImode
350 && GET_CODE (op0
) == REG
351 && REGNO (op0
) == SDA_BASE_REG
)
353 if (GET_CODE (op1
) == SYMBOL_REF
)
354 return symbol_ref_small_data_p (op1
);
356 if (GET_CODE (op1
) == CONST
)
357 return const_small_data_p (op1
);
365 frv_default_flags_for_cpu ()
367 switch (frv_cpu_type
)
369 case FRV_CPU_GENERIC
:
370 return MASK_DEFAULT_FRV
;
374 return MASK_DEFAULT_FR500
;
377 return MASK_DEFAULT_FR400
;
381 return MASK_DEFAULT_SIMPLE
;
386 /* Sometimes certain combinations of command options do not make
387 sense on a particular target machine. You can define a macro
388 `OVERRIDE_OPTIONS' to take account of this. This macro, if
389 defined, is executed once just after all the command options have
392 Don't use this macro to turn on various extra optimizations for
393 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
396 frv_override_options ()
400 /* Set the cpu type */
403 if (strcmp (frv_cpu_string
, "simple") == 0)
404 frv_cpu_type
= FRV_CPU_SIMPLE
;
406 else if (strcmp (frv_cpu_string
, "tomcat") == 0)
407 frv_cpu_type
= FRV_CPU_TOMCAT
;
409 else if (strncmp (frv_cpu_string
, "fr", sizeof ("fr")-1) != 0)
410 error ("Unknown cpu: -mcpu=%s", frv_cpu_string
);
414 const char *p
= frv_cpu_string
+ sizeof ("fr") - 1;
415 if (strcmp (p
, "500") == 0)
416 frv_cpu_type
= FRV_CPU_FR500
;
418 else if (strcmp (p
, "400") == 0)
419 frv_cpu_type
= FRV_CPU_FR400
;
421 else if (strcmp (p
, "300") == 0)
422 frv_cpu_type
= FRV_CPU_FR300
;
424 else if (strcmp (p
, "v") == 0)
425 frv_cpu_type
= FRV_CPU_GENERIC
;
428 error ("Unknown cpu: -mcpu=%s", frv_cpu_string
);
432 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
434 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
435 linker about linking pic and non-pic code. */
438 if (!flag_pic
) /* -fPIC */
441 if (! g_switch_set
) /* -G0 */
448 /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
450 if (write_symbols
== DWARF_DEBUG
&& flag_pic
)
451 error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");
453 /* Change the branch cost value */
454 if (frv_branch_cost_string
)
455 frv_branch_cost_int
= atoi (frv_branch_cost_string
);
457 /* Change the # of insns to be converted to conditional execution */
458 if (frv_condexec_insns_str
)
459 frv_condexec_insns
= atoi (frv_condexec_insns_str
);
461 /* Change # of temporary registers used to hold integer constants */
462 if (frv_condexec_temps_str
)
463 frv_condexec_temps
= atoi (frv_condexec_temps_str
);
465 /* Change scheduling look ahead. */
466 if (frv_sched_lookahead_str
)
467 frv_sched_lookahead
= atoi (frv_sched_lookahead_str
);
469 /* A C expression whose value is a register class containing hard
470 register REGNO. In general there is more than one such class;
471 choose a class which is "minimal", meaning that no smaller class
472 also contains the register. */
474 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
476 enum reg_class
class;
480 int gpr_reg
= regno
- GPR_FIRST
;
481 if ((gpr_reg
& 3) == 0)
484 else if ((gpr_reg
& 1) == 0)
491 else if (FPR_P (regno
))
493 int fpr_reg
= regno
- GPR_FIRST
;
494 if ((fpr_reg
& 3) == 0)
495 class = QUAD_FPR_REGS
;
497 else if ((fpr_reg
& 1) == 0)
504 else if (regno
== LR_REGNO
)
507 else if (regno
== LCR_REGNO
)
510 else if (ICC_P (regno
))
513 else if (FCC_P (regno
))
516 else if (ICR_P (regno
))
519 else if (FCR_P (regno
))
522 else if (ACC_P (regno
))
524 int r
= regno
- ACC_FIRST
;
526 class = QUAD_ACC_REGS
;
527 else if ((r
& 1) == 0)
528 class = EVEN_ACC_REGS
;
533 else if (ACCG_P (regno
))
539 regno_reg_class
[regno
] = class;
542 /* Check for small data option */
544 g_switch_value
= SDATA_DEFAULT_SIZE
;
546 /* A C expression which defines the machine-dependent operand
547 constraint letters for register classes. If CHAR is such a
548 letter, the value should be the register class corresponding to
549 it. Otherwise, the value should be `NO_REGS'. The register
550 letter `r', corresponding to class `GENERAL_REGS', will not be
551 passed to this macro; you do not need to handle it.
553 The following letters are unavailable, due to being used as
558 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
559 'Q', 'R', 'S', 'T', 'U'
561 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
563 for (i
= 0; i
< 256; i
++)
564 reg_class_from_letter
[i
] = NO_REGS
;
566 reg_class_from_letter
['a'] = ACC_REGS
;
567 reg_class_from_letter
['b'] = EVEN_ACC_REGS
;
568 reg_class_from_letter
['c'] = CC_REGS
;
569 reg_class_from_letter
['d'] = GPR_REGS
;
570 reg_class_from_letter
['e'] = EVEN_REGS
;
571 reg_class_from_letter
['f'] = FPR_REGS
;
572 reg_class_from_letter
['h'] = FEVEN_REGS
;
573 reg_class_from_letter
['l'] = LR_REG
;
574 reg_class_from_letter
['q'] = QUAD_REGS
;
575 reg_class_from_letter
['t'] = ICC_REGS
;
576 reg_class_from_letter
['u'] = FCC_REGS
;
577 reg_class_from_letter
['v'] = ICR_REGS
;
578 reg_class_from_letter
['w'] = FCR_REGS
;
579 reg_class_from_letter
['x'] = QUAD_FPR_REGS
;
580 reg_class_from_letter
['y'] = LCR_REG
;
581 reg_class_from_letter
['z'] = SPR_REGS
;
582 reg_class_from_letter
['A'] = QUAD_ACC_REGS
;
583 reg_class_from_letter
['B'] = ACCG_REGS
;
584 reg_class_from_letter
['C'] = CR_REGS
;
586 /* There is no single unaligned SI op for PIC code. Sometimes we
587 need to use ".4byte" and sometimes we need to use ".picptr".
588 See frv_assemble_integer for details. */
590 targetm
.asm_out
.unaligned_op
.si
= 0;
592 init_machine_status
= frv_init_machine_status
;
596 /* Some machines may desire to change what optimizations are performed for
597 various optimization levels. This macro, if defined, is executed once just
598 after the optimization level is determined and before the remainder of the
599 command options have been parsed. Values set in this macro are used as the
600 default values for the other command line options.
602 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
603 `-O' is specified, and 0 if neither is specified.
605 SIZE is nonzero if `-Os' is specified, 0 otherwise.
607 You should not use this macro to change options that are not
608 machine-specific. These should uniformly selected by the same optimization
609 level on all supported machines. Use this macro to enable machbine-specific
612 *Do not examine `write_symbols' in this macro!* The debugging options are
613 *not supposed to alter the generated code. */
615 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
616 scheduling pass at the current time. */
618 frv_optimization_options (level
, size
)
620 int size ATTRIBUTE_UNUSED
;
624 #ifdef DISABLE_SCHED2
625 flag_schedule_insns_after_reload
= 0;
634 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
637 frv_string_begins_with (name
, prefix
)
641 int prefix_len
= strlen (prefix
);
643 /* Remember: NAME's length includes the null terminator. */
644 return (TREE_STRING_LENGTH (name
) > prefix_len
645 && strncmp (TREE_STRING_POINTER (name
), prefix
, prefix_len
) == 0);
648 /* Encode section information of DECL, which is either a VAR_DECL,
649 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
651 For the FRV we want to record:
653 - whether the object lives in .sdata/.sbss.
654 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
659 frv_encode_section_info (decl
, first
)
665 if (TREE_CODE (decl
) == VAR_DECL
)
667 int size
= int_size_in_bytes (TREE_TYPE (decl
));
668 tree section_name
= DECL_SECTION_NAME (decl
);
671 /* Don't apply the -G flag to internal compiler structures. We
672 should leave such structures in the main data section, partly
673 for efficiency and partly because the size of some of them
674 (such as C++ typeinfos) is not known until later. */
675 if (!DECL_ARTIFICIAL (decl
) && size
> 0 && size
<= g_switch_value
)
678 /* If we already know which section the decl should be in, see if
679 it's a small data section. */
682 if (TREE_CODE (section_name
) == STRING_CST
)
684 if (frv_string_begins_with (section_name
, ".sdata"))
686 if (frv_string_begins_with (section_name
, ".sbss"))
695 rtx sym_ref
= XEXP (DECL_RTL (decl
), 0);
696 char * str
= xmalloc (2 + strlen (XSTR (sym_ref
, 0)));
698 str
[0] = SDATA_FLAG_CHAR
;
699 strcpy (&str
[1], XSTR (sym_ref
, 0));
700 XSTR (sym_ref
, 0) = str
;
706 /* Zero or more C statements that may conditionally modify two variables
707 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
708 been initialized from the two preceding macros.
710 This is necessary in case the fixed or call-clobbered registers depend on
713 You need not define this macro if it has no work to do.
715 If the usage of an entire class of registers depends on the target flags,
716 you may indicate this to GCC by using this macro to modify `fixed_regs' and
717 `call_used_regs' to 1 for each of the registers in the classes which should
718 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
719 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
721 (However, if this class is not included in `GENERAL_REGS' and all of the
722 insn patterns whose constraints permit this class are controlled by target
723 switches, then GCC will automatically avoid using these registers when the
724 target switches are opposed to them.) */
727 frv_conditional_register_usage ()
731 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
732 fixed_regs
[i
] = call_used_regs
[i
] = 1;
734 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
735 fixed_regs
[i
] = call_used_regs
[i
] = 1;
737 for (i
= ACC_FIRST
+ NUM_ACCS
; i
<= ACC_LAST
; i
++)
738 fixed_regs
[i
] = call_used_regs
[i
] = 1;
740 for (i
= ACCG_FIRST
+ NUM_ACCS
; i
<= ACCG_LAST
; i
++)
741 fixed_regs
[i
] = call_used_regs
[i
] = 1;
743 /* Reserve the registers used for conditional execution. At present, we need
744 1 ICC and 1 ICR register. */
745 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
746 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
750 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
751 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
752 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
753 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
757 /* If -fpic, SDA_BASE_REG is the PIC register. */
758 if (g_switch_value
== 0 && !flag_pic
)
759 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
762 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
768 * Compute the stack frame layout
771 * +---------------+-----------------------+-----------------------+
772 * |Register |type |caller-save/callee-save|
773 * +---------------+-----------------------+-----------------------+
774 * |GR0 |Zero register | - |
775 * |GR1 |Stack pointer(SP) | - |
776 * |GR2 |Frame pointer(FP) | - |
777 * |GR3 |Hidden parameter | caller save |
778 * |GR4-GR7 | - | caller save |
779 * |GR8-GR13 |Argument register | caller save |
780 * |GR14-GR15 | - | caller save |
781 * |GR16-GR31 | - | callee save |
782 * |GR32-GR47 | - | caller save |
783 * |GR48-GR63 | - | callee save |
784 * |FR0-FR15 | - | caller save |
785 * |FR16-FR31 | - | callee save |
786 * |FR32-FR47 | - | caller save |
787 * |FR48-FR63 | - | callee save |
788 * +---------------+-----------------------+-----------------------+
792 * SP-> |-----------------------------------|
794 * |-----------------------------------|
795 * | Register save area |
796 * |-----------------------------------|
797 * | Local variable save area |
798 * FP-> |-----------------------------------|
800 * |-----------------------------------|
801 * | Hidden parameter save area |
802 * |-----------------------------------|
803 * | Return address(LR) storage area |
804 * |-----------------------------------|
805 * | Padding for alignment |
806 * |-----------------------------------|
807 * | Register argument area |
808 * OLD SP-> |-----------------------------------|
810 * |-----------------------------------|
813 * Argument area/Parameter area:
815 * When a function is called, this area is used for argument transfer. When
816 * the argument is set up by the caller function, this area is referred to as
817 * the argument area. When the argument is referenced by the callee function,
818 * this area is referred to as the parameter area. The area is allocated when
819 * all arguments cannot be placed on the argument register at the time of
822 * Register save area:
824 * This is a register save area that must be guaranteed for the caller
825 * function. This area is not secured when the register save operation is not
828 * Local variable save area:
830 * This is the area for local variables and temporary variables.
834 * This area stores the FP value of the caller function.
836 * Hidden parameter save area:
838 * This area stores the start address of the return value storage
839 * area for a struct/union return function.
840 * When a struct/union is used as the return value, the caller
841 * function stores the return value storage area start address in
842 * register GR3 and passes it to the caller function.
843 * The callee function interprets the address stored in the GR3
844 * as the return value storage area start address.
845 * When register GR3 needs to be saved into memory, the callee
846 * function saves it in the hidden parameter save area. This
847 * area is not secured when the save operation is not needed.
849 * Return address(LR) storage area:
851 * This area saves the LR. The LR stores the address of a return to the caller
852 * function for the purpose of function calling.
854 * Argument register area:
856 * This area saves the argument register. This area is not secured when the
857 * save operation is not needed.
861 * Arguments, the count of which equals the count of argument registers (6
862 * words), are positioned in registers GR8 to GR13 and delivered to the callee
863 * function. When a struct/union return function is called, the return value
864 * area address is stored in register GR3. Arguments not placed in the
865 * argument registers will be stored in the stack argument area for transfer
866 * purposes. When an 8-byte type argument is to be delivered using registers,
867 * it is divided into two and placed in two registers for transfer. When
868 * argument registers must be saved to memory, the callee function secures an
869 * argument register save area in the stack. In this case, a continuous
870 * argument register save area must be established in the parameter area. The
871 * argument register save area must be allocated as needed to cover the size of
872 * the argument register to be saved. If the function has a variable count of
873 * arguments, it saves all argument registers in the argument register save
876 * Argument Extension Format:
878 * When an argument is to be stored in the stack, its type is converted to an
879 * extended type in accordance with the individual argument type. The argument
880 * is freed by the caller function after the return from the callee function is
883 * +-----------------------+---------------+------------------------+
884 * | Argument Type |Extended Type |Stack Storage Size(byte)|
885 * +-----------------------+---------------+------------------------+
887 * |signed char |int | 4 |
888 * |unsigned char |int | 4 |
889 * |[signed] short int |int | 4 |
890 * |unsigned short int |int | 4 |
891 * |[signed] int |No extension | 4 |
892 * |unsigned int |No extension | 4 |
893 * |[signed] long int |No extension | 4 |
894 * |unsigned long int |No extension | 4 |
895 * |[signed] long long int |No extension | 8 |
896 * |unsigned long long int |No extension | 8 |
897 * |float |double | 8 |
898 * |double |No extension | 8 |
899 * |long double |No extension | 8 |
900 * |pointer |No extension | 4 |
901 * |struct/union |- | 4 (*1) |
902 * +-----------------------+---------------+------------------------+
904 * When a struct/union is to be delivered as an argument, the caller copies it
905 * to the local variable area and delivers the address of that area.
909 * +-------------------------------+----------------------+
910 * |Return Value Type |Return Value Interface|
911 * +-------------------------------+----------------------+
913 * |[signed|unsigned] char |GR8 |
914 * |[signed|unsigned] short int |GR8 |
915 * |[signed|unsigned] int |GR8 |
916 * |[signed|unsigned] long int |GR8 |
918 * |[signed|unsigned] long long int|GR8 & GR9 |
920 * |double |GR8 & GR9 |
921 * |long double |GR8 & GR9 |
922 * |struct/union |(*1) |
923 * +-------------------------------+----------------------+
925 * When a struct/union is used as the return value, the caller function stores
926 * the start address of the return value storage area into GR3 and then passes
927 * it to the callee function. The callee function interprets GR3 as the start
928 * address of the return value storage area. When this address needs to be
929 * saved in memory, the callee function secures the hidden parameter save area
930 * and saves the address in that area.
936 static frv_stack_t info
, zero_info
;
937 frv_stack_t
*info_ptr
= &info
;
938 tree fndecl
= current_function_decl
;
946 /* If we've already calculated the values and reload is complete, just return now */
948 return frv_stack_cache
;
950 /* Zero all fields */
953 /* Set up the register range information */
954 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
955 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
956 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
957 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
959 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
960 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
961 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
962 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
964 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
965 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
966 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
967 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
969 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
970 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
971 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
972 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
974 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
975 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
976 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
978 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
979 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
980 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
981 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
982 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
984 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
985 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= STRUCT_VALUE_REGNUM
;
986 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= STRUCT_VALUE_REGNUM
;
987 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
989 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
990 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
991 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
992 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
994 /* Determine if this is a stdarg function. If so, allocate space to store
1001 /* Find the last argument, and see if it is __builtin_va_alist. */
1002 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
1004 next_arg
= TREE_CHAIN (cur_arg
);
1005 if (next_arg
== (tree
)0)
1007 if (DECL_NAME (cur_arg
)
1008 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1016 /* Iterate over all of the register ranges */
1017 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1019 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1020 int first
= reg_ptr
->first
;
1021 int last
= reg_ptr
->last
;
1023 int size_2words
= 0;
1026 /* Calculate which registers need to be saved & save area size */
1030 for (regno
= first
; regno
<= last
; regno
++)
1032 if ((regs_ever_live
[regno
] && !call_used_regs
[regno
])
1033 || (current_function_calls_eh_return
1034 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1035 || (flag_pic
&& cfun
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1037 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1038 size_1word
+= UNITS_PER_WORD
;
1043 /* Calculate whether we need to create a frame after everything else
1044 has been processed. */
1049 if (regs_ever_live
[LR_REGNO
]
1051 || frame_pointer_needed
1052 || (flag_pic
&& cfun
->uses_pic_offset_table
))
1054 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1055 size_1word
+= UNITS_PER_WORD
;
1059 case STACK_REGS_STDARG
:
1062 /* If this is a stdarg function with an non varardic argument split
1063 between registers and the stack, adjust the saved registers
1065 last
-= (ADDR_ALIGN (cfun
->pretend_args_size
, UNITS_PER_WORD
)
1068 for (regno
= first
; regno
<= last
; regno
++)
1070 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1071 size_1word
+= UNITS_PER_WORD
;
1074 info_ptr
->stdarg_size
= size_1word
;
1078 case STACK_REGS_STRUCT
:
1079 if (cfun
->returns_struct
)
1081 info_ptr
->save_p
[STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1082 size_1word
+= UNITS_PER_WORD
;
1090 /* If this is a field, it only takes one word */
1091 if (reg_ptr
->field_p
)
1092 size_1word
= UNITS_PER_WORD
;
1094 /* Determine which register pairs can be saved together */
1095 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1097 for (regno
= first
; regno
< last
; regno
+= 2)
1099 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1101 size_2words
+= 2 * UNITS_PER_WORD
;
1102 size_1word
-= 2 * UNITS_PER_WORD
;
1103 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1104 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1109 reg_ptr
->size_1word
= size_1word
;
1110 reg_ptr
->size_2words
= size_2words
;
1112 if (! reg_ptr
->special_p
)
1114 info_ptr
->regs_size_1word
+= size_1word
;
1115 info_ptr
->regs_size_2words
+= size_2words
;
1120 /* Set up the sizes of each each field in the frame body, making the sizes
1121 of each be divisible by the size of a dword if dword operations might
1122 be used, or the size of a word otherwise. */
1123 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1125 info_ptr
->parameter_size
= ADDR_ALIGN (cfun
->outgoing_args_size
, alignment
);
1126 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1127 + info_ptr
->regs_size_1word
,
1129 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1131 info_ptr
->pretend_size
= cfun
->pretend_args_size
;
1133 /* Work out the size of the frame, excluding the header. Both the frame
1134 body and register parameter area will be dword-aligned. */
1135 info_ptr
->total_size
1136 = (ADDR_ALIGN (info_ptr
->parameter_size
1137 + info_ptr
->regs_size
1138 + info_ptr
->vars_size
,
1140 + ADDR_ALIGN (info_ptr
->pretend_size
1141 + info_ptr
->stdarg_size
,
1142 2 * UNITS_PER_WORD
));
1144 /* See if we need to create a frame at all, if so add header area. */
1145 if (info_ptr
->total_size
> 0
1146 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1147 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1149 offset
= info_ptr
->parameter_size
;
1150 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1151 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1153 /* Calculate the offsets to save normal register pairs */
1154 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1156 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1157 if (! reg_ptr
->special_p
)
1159 int first
= reg_ptr
->first
;
1160 int last
= reg_ptr
->last
;
1163 for (regno
= first
; regno
<= last
; regno
++)
1164 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1165 && regno
!= FRAME_POINTER_REGNUM
1166 && (regno
< FIRST_ARG_REGNUM
1167 || regno
> LAST_ARG_REGNUM
))
1169 info_ptr
->reg_offset
[regno
] = offset
;
1170 offset
+= 2 * UNITS_PER_WORD
;
1175 /* Calculate the offsets to save normal single registers */
1176 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1178 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1179 if (! reg_ptr
->special_p
)
1181 int first
= reg_ptr
->first
;
1182 int last
= reg_ptr
->last
;
1185 for (regno
= first
; regno
<= last
; regno
++)
1186 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1187 && regno
!= FRAME_POINTER_REGNUM
1188 && (regno
< FIRST_ARG_REGNUM
1189 || regno
> LAST_ARG_REGNUM
))
1191 info_ptr
->reg_offset
[regno
] = offset
;
1192 offset
+= UNITS_PER_WORD
;
1197 /* Calculate the offset to save the local variables at. */
1198 offset
= ADDR_ALIGN (offset
, alignment
);
1199 if (info_ptr
->vars_size
)
1201 info_ptr
->vars_offset
= offset
;
1202 offset
+= info_ptr
->vars_size
;
1205 /* Align header to a dword-boundary. */
1206 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1208 /* Calculate the offsets in the fixed frame. */
1209 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1210 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1211 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1213 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1214 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1215 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1217 if (cfun
->returns_struct
)
1219 info_ptr
->save_p
[STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1220 info_ptr
->reg_offset
[STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1221 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1224 /* Calculate the offsets to store the arguments passed in registers
1225 for stdarg functions. The register pairs are first and the single
1226 register if any is last. The register save area starts on a
1228 if (info_ptr
->stdarg_size
)
1230 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1231 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1234 /* Skip the header. */
1235 offset
+= 4 * UNITS_PER_WORD
;
1236 for (regno
= first
; regno
<= last
; regno
++)
1238 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1240 info_ptr
->reg_offset
[regno
] = offset
;
1241 offset
+= 2 * UNITS_PER_WORD
;
1243 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1245 info_ptr
->reg_offset
[regno
] = offset
;
1246 offset
+= UNITS_PER_WORD
;
1252 if (reload_completed
)
1253 frv_stack_cache
= info_ptr
;
1259 /* Print the information about the frv stack offsets, etc. when debugging. */
1262 frv_debug_stack (info
)
1268 info
= frv_stack_info ();
1270 fprintf (stderr
, "\nStack information for function %s:\n",
1271 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1272 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1275 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1276 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1277 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1278 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1279 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1281 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1282 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1283 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1284 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1286 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1288 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1289 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1291 int first
= regs
->first
;
1292 int last
= regs
->last
;
1295 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1296 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1297 regs
->size_1word
, regs
->size_2words
);
1299 for (regno
= first
; regno
<= last
; regno
++)
1301 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1302 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1303 info
->reg_offset
[regno
]);
1305 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1306 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1307 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1310 fputc ('\n', stderr
);
1320 /* The following variable value is TRUE if the next output insn should
1321 finish cpu cycle. In order words the insn will have packing bit
1322 (which means absence of asm code suffix `.p' on assembler. */
1324 static int frv_insn_packing_flag
;
1326 /* True if the current function contains a far jump. */
1329 frv_function_contains_far_jump ()
1331 rtx insn
= get_insns ();
1333 && !(GET_CODE (insn
) == JUMP_INSN
1334 /* Ignore tablejump patterns. */
1335 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
1336 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
1337 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1338 insn
= NEXT_INSN (insn
);
1339 return (insn
!= NULL
);
1342 /* For the FRV, this function makes sure that a function with far jumps
1343 will return correctly. It also does the VLIW packing. */
1346 frv_function_prologue (file
, size
)
1348 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
1350 /* If no frame was created, check whether the function uses a call
1351 instruction to implement a far jump. If so, save the link in gr3 and
1352 replace all returns to LR with returns to GR3. GR3 is used because it
1353 is call-clobbered, because is not available to the register allocator,
1354 and because all functions that take a hidden argument pointer will have
1356 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1360 /* Just to check that the above comment is true. */
1361 if (regs_ever_live
[GPR_FIRST
+ 3])
1364 /* Generate the instruction that saves the link register. */
1365 fprintf (file
, "\tmovsg lr,gr3\n");
1367 /* Replace the LR with GR3 in *return_internal patterns. The insn
1368 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1369 simply emit a different assembly directive because bralr and jmpl
1370 execute in different units. */
1371 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1372 if (GET_CODE (insn
) == JUMP_INSN
)
1374 rtx pattern
= PATTERN (insn
);
1375 if (GET_CODE (pattern
) == PARALLEL
1376 && XVECLEN (pattern
, 0) >= 2
1377 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1378 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1380 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1381 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1382 REGNO (address
) = GPR_FIRST
+ 3;
1388 frv_insn_packing_flag
= TRUE
;
1392 /* Return the next available temporary register in a given class. */
1395 frv_alloc_temp_reg (info
, class, mode
, mark_as_used
, no_abort
)
1396 frv_tmp_reg_t
*info
; /* which registers are available */
1397 enum reg_class
class; /* register class desired */
1398 enum machine_mode mode
; /* mode to allocate register with */
1399 int mark_as_used
; /* register not available after allocation */
1400 int no_abort
; /* return NULL instead of aborting */
1402 int regno
= info
->next_reg
[ (int)class ];
1403 int orig_regno
= regno
;
1404 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)class ];
1409 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1410 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1413 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1415 if (regno
== orig_regno
)
1424 nr
= HARD_REGNO_NREGS (regno
, mode
);
1425 info
->next_reg
[ (int)class ] = regno
+ nr
;
1428 for (i
= 0; i
< nr
; i
++)
1429 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1431 return gen_rtx_REG (mode
, regno
);
1435 /* Return an rtx with the value OFFSET, which will either be a register or a
1436 signed 12-bit integer. It can be used as the second operand in an "add"
1437 instruction, or as the index in a load or store.
1439 The function returns a constant rtx if OFFSET is small enough, otherwise
1440 it loads the constant into register OFFSET_REGNO and returns that. */
1442 frv_frame_offset_rtx (offset
)
1445 rtx offset_rtx
= GEN_INT (offset
);
1446 if (IN_RANGE_P (offset
, -2048, 2047))
1450 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1451 if (IN_RANGE_P (offset
, -32768, 32767))
1452 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1455 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1456 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1462 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1463 prologue and epilogue uses such expressions to access the stack. */
1465 frv_frame_mem (mode
, base
, offset
)
1466 enum machine_mode mode
;
1470 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1472 frv_frame_offset_rtx (offset
)));
1475 /* Generate a frame-related expression:
1477 (set REG (mem (plus (sp) (const_int OFFSET)))).
1479 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1480 instructions. Marking the expressions as frame-related is superfluous if
1481 the note contains just a single set. But if the note contains a PARALLEL
1482 or SEQUENCE that has several sets, each set must be individually marked
1483 as frame-related. */
1485 frv_dwarf_store (reg
, offset
)
1489 rtx set
= gen_rtx_SET (VOIDmode
,
1490 gen_rtx_MEM (GET_MODE (reg
),
1491 plus_constant (stack_pointer_rtx
,
1494 RTX_FRAME_RELATED_P (set
) = 1;
1498 /* Emit a frame-related instruction whose pattern is PATTERN. The
1499 instruction is the last in a sequence that cumulatively performs the
1500 operation described by DWARF_PATTERN. The instruction is marked as
1501 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1504 frv_frame_insn (pattern
, dwarf_pattern
)
1508 rtx insn
= emit_insn (pattern
);
1509 RTX_FRAME_RELATED_P (insn
) = 1;
1510 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1515 /* Emit instructions that transfer REG to or from the memory location (sp +
1516 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1517 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1518 function to store registers and only the epilogue uses it to load them.
1520 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1521 The generated instruction will use BASE as its base register. BASE may
1522 simply be the stack pointer, but if several accesses are being made to a
1523 region far away from the stack pointer, it may be more efficient to set
1524 up a temporary instead.
1526 Store instructions will be frame-related and will be annotated with the
1527 overall effect of the store. Load instructions will be followed by a
1528 (use) to prevent later optimizations from zapping them.
1530 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1531 as a temporary in such cases. */
1533 frv_frame_access (accessor
, reg
, stack_offset
)
1534 frv_frame_accessor_t
*accessor
;
1538 enum machine_mode mode
= GET_MODE (reg
);
1539 rtx mem
= frv_frame_mem (mode
,
1541 stack_offset
- accessor
->base_offset
);
1543 if (accessor
->op
== FRV_LOAD
)
1545 if (SPR_P (REGNO (reg
)))
1547 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1548 emit_insn (gen_rtx_SET (VOIDmode
, temp
, mem
));
1549 emit_insn (gen_rtx_SET (VOIDmode
, reg
, temp
));
1552 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1553 emit_insn (gen_rtx_USE (VOIDmode
, reg
));
1557 if (SPR_P (REGNO (reg
)))
1559 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1560 emit_insn (gen_rtx_SET (VOIDmode
, temp
, reg
));
1561 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, temp
),
1562 frv_dwarf_store (reg
, stack_offset
));
1564 else if (GET_MODE (reg
) == DImode
)
1566 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1567 with a separate save for each register. */
1568 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1569 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1570 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1571 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1572 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1573 gen_rtx_PARALLEL (VOIDmode
,
1574 gen_rtvec (2, set1
, set2
)));
1577 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1578 frv_dwarf_store (reg
, stack_offset
));
1582 /* A function that uses frv_frame_access to transfer a group of registers to
1583 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1584 is the stack information generated by frv_stack_info, and REG_SET is the
1585 number of the register set to transfer. */
1587 frv_frame_access_multi (accessor
, info
, reg_set
)
1588 frv_frame_accessor_t
*accessor
;
1592 frv_stack_regs_t
*regs_info
;
1595 regs_info
= &info
->regs
[reg_set
];
1596 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1597 if (info
->save_p
[regno
])
1598 frv_frame_access (accessor
,
1599 info
->save_p
[regno
] == REG_SAVE_2WORDS
1600 ? gen_rtx_REG (DImode
, regno
)
1601 : gen_rtx_REG (SImode
, regno
),
1602 info
->reg_offset
[regno
]);
1605 /* Save or restore callee-saved registers that are kept outside the frame
1606 header. The function saves the registers if OP is FRV_STORE and restores
1607 them if OP is FRV_LOAD. INFO is the stack information generated by
1610 frv_frame_access_standard_regs (op
, info
)
1611 enum frv_stack_op op
;
1614 frv_frame_accessor_t accessor
;
1617 accessor
.base
= stack_pointer_rtx
;
1618 accessor
.base_offset
= 0;
1619 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1620 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1621 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1625 /* Called after register allocation to add any instructions needed for the
1626 prologue. Using a prologue insn is favored compared to putting all of the
1627 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1628 to intermix instructions with the saves of the caller saved registers. In
1629 some cases, it might be necessary to emit a barrier instruction as the last
1630 insn to prevent such scheduling.
1632 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1633 so that the debug info generation code can handle them properly. */
1635 frv_expand_prologue ()
1637 frv_stack_t
*info
= frv_stack_info ();
1638 rtx sp
= stack_pointer_rtx
;
1639 rtx fp
= frame_pointer_rtx
;
1640 frv_frame_accessor_t accessor
;
1642 if (TARGET_DEBUG_STACK
)
1643 frv_debug_stack (info
);
1645 if (info
->total_size
== 0)
1648 /* We're interested in three areas of the frame here:
1650 A: the register save area
1652 C: the header after B
1654 If the frame pointer isn't used, we'll have to set up A, B and C
1655 using the stack pointer. If the frame pointer is used, we'll access
1659 B: set up using sp or a temporary (see below)
1662 We set up B using the stack pointer if the frame is small enough.
1663 Otherwise, it's more efficient to copy the old stack pointer into a
1664 temporary and use that.
1666 Note that it's important to make sure the prologue and epilogue use the
1667 same registers to access A and C, since doing otherwise will confuse
1668 the aliasing code. */
1670 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1671 isn't used, the same method will serve for C. */
1672 accessor
.op
= FRV_STORE
;
1673 if (frame_pointer_needed
&& info
->total_size
> 2048)
1677 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1678 accessor
.base_offset
= info
->total_size
;
1679 insn
= emit_insn (gen_movsi (accessor
.base
, sp
));
1683 accessor
.base
= stack_pointer_rtx
;
1684 accessor
.base_offset
= 0;
1687 /* Allocate the stack space. */
1689 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1690 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1692 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1695 gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1698 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1699 and point the new one to that location. */
1700 if (frame_pointer_needed
)
1702 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1704 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1705 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1707 rtx asm_src
= plus_constant (accessor
.base
,
1708 fp_offset
- accessor
.base_offset
);
1709 rtx dwarf_src
= plus_constant (sp
, fp_offset
);
1711 /* Store the old frame pointer at (sp + FP_OFFSET). */
1712 frv_frame_access (&accessor
, fp
, fp_offset
);
1714 /* Set up the new frame pointer. */
1715 frv_frame_insn (gen_rtx_SET (VOIDmode
, fp
, asm_src
),
1716 gen_rtx_SET (VOIDmode
, fp
, dwarf_src
));
1718 /* Access region C from the frame pointer. */
1720 accessor
.base_offset
= fp_offset
;
1723 /* Set up region C. */
1724 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1725 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1726 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1728 /* Set up region A. */
1729 frv_frame_access_standard_regs (FRV_STORE
, info
);
1731 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1732 scheduler from moving loads before the stores saving the registers. */
1733 if (info
->stdarg_size
> 0)
1734 emit_insn (gen_blockage ());
1736 /* Set up pic register/small data register for this function. */
1737 if (flag_pic
&& cfun
->uses_pic_offset_table
)
1738 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1739 gen_rtx_REG (Pmode
, LR_REGNO
),
1740 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1744 /* Under frv, all of the work is done via frv_expand_epilogue, but
1745 this function provides a convient place to do cleanup. */
1748 frv_function_epilogue (file
, size
)
1749 FILE *file ATTRIBUTE_UNUSED
;
1750 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
1752 frv_stack_cache
= (frv_stack_t
*)0;
1754 /* zap last used registers for conditional execution. */
1755 memset ((PTR
) &frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1757 /* release the bitmap of created insns. */
1758 BITMAP_XFREE (frv_ifcvt
.scratch_insns_bitmap
);
1762 /* Called after register allocation to add any instructions needed for the
1763 epilogue. Using an epilogue insn is favored compared to putting all of the
1764 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1765 to intermix instructions with the saves of the caller saved registers. In
1766 some cases, it might be necessary to emit a barrier instruction as the last
1767 insn to prevent such scheduling.
1769 If SIBCALL_P is true, the final branch back to the calling function is
1770 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1771 we must not clobber any arguments used for parameter passing or any stack
1772 slots for arguments passed to the current function. */
1775 frv_expand_epilogue (sibcall_p
)
1778 frv_stack_t
*info
= frv_stack_info ();
1779 rtx fp
= frame_pointer_rtx
;
1780 rtx sp
= stack_pointer_rtx
;
1784 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1786 /* Restore the stack pointer to its original value if alloca or the like
1788 if (! current_function_sp_is_unchanging
)
1789 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1791 /* Restore the callee-saved registers that were used in this function. */
1792 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1794 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1795 no return instruction should be emitted. */
1798 else if (info
->save_p
[LR_REGNO
])
1803 /* Use the same method to access the link register's slot as we did in
1804 the prologue. In other words, use the frame pointer if available,
1805 otherwise use the stack pointer.
1807 LR_OFFSET is the offset of the link register's slot from the start
1808 of the frame and MEM is a memory rtx for it. */
1809 lr_offset
= info
->reg_offset
[LR_REGNO
];
1810 if (frame_pointer_needed
)
1811 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1813 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1815 /* Load the old link register into a GPR. */
1816 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1817 emit_insn (gen_rtx_SET (VOIDmode
, return_addr
, mem
));
1820 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1822 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1823 the load is preserved. */
1824 if (frame_pointer_needed
)
1826 emit_insn (gen_rtx_SET (VOIDmode
, fp
, gen_rtx_MEM (Pmode
, fp
)));
1827 emit_insn (gen_rtx_USE (VOIDmode
, fp
));
1830 /* Deallocate the stack frame. */
1831 if (info
->total_size
!= 0)
1833 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1834 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1837 /* If this function uses eh_return, add the final stack adjustment now. */
1838 if (current_function_calls_eh_return
)
1839 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1842 emit_jump_insn (gen_epilogue_return (return_addr
));
1846 /* A C compound statement that outputs the assembler code for a thunk function,
1847 used to implement C++ virtual function calls with multiple inheritance. The
1848 thunk acts as a wrapper around a virtual function, adjusting the implicit
1849 object parameter before handing control off to the real function.
1851 First, emit code to add the integer DELTA to the location that contains the
1852 incoming first argument. Assume that this argument contains a pointer, and
1853 is the one used to pass the `this' pointer in C++. This is the incoming
1854 argument *before* the function prologue, e.g. `%o0' on a sparc. The
1855 addition must preserve the values of all other incoming arguments.
1857 After the addition, emit code to jump to FUNCTION, which is a
1858 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch
1859 the return address. Hence returning from FUNCTION will return to whoever
1860 called the current `thunk'.
1862 The effect must be as if FUNCTION had been called directly with the adjusted
1863 first argument. This macro is responsible for emitting all of the code for
1864 a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
1867 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been
1868 extracted from it.) It might possibly be useful on some targets, but
1871 If you do not define this macro, the target-independent code in the C++
1872 frontend will generate a less efficient heavyweight thunk that calls
1873 FUNCTION instead of jumping to it. The generic approach does not support
1877 frv_asm_output_mi_thunk (file
, thunk_fndecl
, delta
, vcall_offset
, function
)
1879 tree thunk_fndecl ATTRIBUTE_UNUSED
;
1880 HOST_WIDE_INT delta
;
1881 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
;
1884 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1885 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1886 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1887 const char *parallel
= ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1889 /* Do the add using an addi if possible */
1890 if (IN_RANGE_P (delta
, -2048, 2047))
1891 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1894 const char *name_add
= reg_names
[TEMP_REGNO
];
1895 fprintf (file
, "\tsethi%s #hi(", parallel
);
1896 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, delta
);
1897 fprintf (file
, "),%s\n", name_add
);
1898 fprintf (file
, "\tsetlo #lo(");
1899 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, delta
);
1900 fprintf (file
, "),%s\n", name_add
);
1901 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1906 fprintf (file
, "\tsethi%s #hi(", parallel
);
1907 assemble_name (file
, name_func
);
1908 fprintf (file
, "),%s\n", name_jmp
);
1910 fprintf (file
, "\tsetlo #lo(");
1911 assemble_name (file
, name_func
);
1912 fprintf (file
, "),%s\n", name_jmp
);
1916 /* Use JUMP_REGNO as a temporary PIC register. */
1917 const char *name_lr
= reg_names
[LR_REGNO
];
1918 const char *name_gppic
= name_jmp
;
1919 const char *name_tmp
= reg_names
[TEMP_REGNO
];
1921 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
1922 fprintf (file
, "\tcall 1f\n");
1923 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
1924 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
1925 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
1926 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
1927 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
1929 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
1930 assemble_name (file
, name_func
);
1931 fprintf (file
, "),%s\n", name_tmp
);
1933 fprintf (file
, "\tsetlo #gprello(");
1934 assemble_name (file
, name_func
);
1935 fprintf (file
, "),%s\n", name_tmp
);
1937 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
1940 /* Jump to the function address */
1941 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
1945 /* A C expression which is nonzero if a function must have and use a frame
1946 pointer. This expression is evaluated in the reload pass. If its value is
1947 nonzero the function will have a frame pointer.
1949 The expression can in principle examine the current function and decide
1950 according to the facts, but on most machines the constant 0 or the constant
1951 1 suffices. Use 0 when the machine allows code to be generated with no
1952 frame pointer, and doing so saves some time or space. Use 1 when there is
1953 no possible advantage to avoiding a frame pointer.
1955 In certain cases, the compiler does not know how to produce valid code
1956 without a frame pointer. The compiler recognizes those cases and
1957 automatically gives the function a frame pointer regardless of what
1958 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1960 In a function that does not require a frame pointer, the frame pointer
1961 register can be allocated for ordinary usage, unless you mark it as a fixed
1962 register. See `FIXED_REGISTERS' for more information. */
1964 /* On frv, create a frame whenever we need to create stack */
1967 frv_frame_pointer_required ()
1969 if (! current_function_is_leaf
)
1972 if (get_frame_size () != 0)
1978 if (!current_function_sp_is_unchanging
)
1981 if (flag_pic
&& cfun
->uses_pic_offset_table
)
1987 if (cfun
->machine
->frame_needed
)
1994 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1995 initial difference between the specified pair of registers. This macro must
1996 be defined if `ELIMINABLE_REGS' is defined. */
1998 /* See frv_stack_info for more details on the frv stack frame. */
2001 frv_initial_elimination_offset (from
, to
)
2005 frv_stack_t
*info
= frv_stack_info ();
2008 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2009 ret
= info
->total_size
- info
->pretend_size
;
2011 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2012 ret
= - info
->reg_offset
[FRAME_POINTER_REGNUM
];
2014 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2015 ret
= (info
->total_size
2016 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2017 - info
->pretend_size
);
2022 if (TARGET_DEBUG_STACK
)
2023 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2024 reg_names
[from
], reg_names
[to
], ret
);
2030 /* This macro offers an alternative to using `__builtin_saveregs' and defining
2031 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
2032 arguments into the stack so that all the arguments appear to have been
2033 passed consecutively on the stack. Once this is done, you can use the
2034 standard implementation of varargs that works for machines that pass all
2035 their arguments on the stack.
2037 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
2038 the values that obtain after processing of the named arguments. The
2039 arguments MODE and TYPE describe the last named argument--its machine mode
2040 and its data type as a tree node.
2042 The macro implementation should do two things: first, push onto the stack
2043 all the argument registers *not* used for the named arguments, and second,
2044 store the size of the data thus pushed into the `int'-valued variable whose
2045 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
2046 store here will serve as additional offset for setting up the stack frame.
2048 Because you must generate code to push the anonymous arguments at compile
2049 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
2050 useful on machines that have just a single category of argument register and
2051 use it uniformly for all data types.
2053 If the argument SECOND_TIME is nonzero, it means that the arguments of the
2054 function are being analyzed for the second time. This happens for an inline
2055 function, which is not actually compiled until the end of the source file.
2056 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
2060 frv_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, second_time
)
2061 CUMULATIVE_ARGS
*cum
;
2062 enum machine_mode mode
;
2063 tree type ATTRIBUTE_UNUSED
;
2067 if (TARGET_DEBUG_ARG
)
2069 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2070 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2074 /* If defined, is a C expression that produces the machine-specific code for a
2075 call to `__builtin_saveregs'. This code will be moved to the very beginning
2076 of the function, before any parameter access are made. The return value of
2077 this function should be an RTX that contains the value to use as the return
2078 of `__builtin_saveregs'.
2080 If this macro is not defined, the compiler will output an ordinary call to
2081 the library function `__builtin_saveregs'. */
2084 frv_expand_builtin_saveregs ()
2086 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2088 if (TARGET_DEBUG_ARG
)
2089 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2092 return gen_rtx (PLUS
, Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2096 /* Expand __builtin_va_start to do the va_start macro. */
2099 frv_expand_builtin_va_start (valist
, nextarg
)
2104 int num
= cfun
->args_info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2106 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2107 GEN_INT (UNITS_PER_WORD
* num
));
2109 if (TARGET_DEBUG_ARG
)
2111 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2112 cfun
->args_info
, num
);
2114 debug_rtx (nextarg
);
2117 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2118 make_tree (ptr_type_node
, nextarg
));
2119 TREE_SIDE_EFFECTS (t
) = 1;
2121 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2125 /* Expand __builtin_va_arg to do the va_arg macro. */
2128 frv_expand_builtin_va_arg(valist
, type
)
2136 if (TARGET_DEBUG_ARG
)
2138 fprintf (stderr
, "va_arg:\n");
2142 if (! AGGREGATE_TYPE_P (type
))
2143 return std_expand_builtin_va_arg (valist
, type
);
2145 addr
= std_expand_builtin_va_arg (valist
, ptr_type_node
);
2146 mem
= gen_rtx_MEM (Pmode
, addr
);
2147 reg
= gen_reg_rtx (Pmode
);
2149 set_mem_alias_set (mem
, get_varargs_alias_set ());
2150 emit_move_insn (reg
, mem
);
2156 /* Expand a block move operation, and return 1 if successful. Return 0
2157 if we should let the compiler generate normal code.
2159 operands[0] is the destination
2160 operands[1] is the source
2161 operands[2] is the length
2162 operands[3] is the alignment */
2164 /* Maximum number of loads to do before doing the stores */
2165 #ifndef MAX_MOVE_REG
2166 #define MAX_MOVE_REG 4
2169 /* Maximum number of total loads to do. */
2170 #ifndef TOTAL_MOVE_REG
2171 #define TOTAL_MOVE_REG 8
2175 frv_expand_block_move (operands
)
2178 rtx orig_dest
= operands
[0];
2179 rtx orig_src
= operands
[1];
2180 rtx bytes_rtx
= operands
[2];
2181 rtx align_rtx
= operands
[3];
2182 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2195 rtx stores
[MAX_MOVE_REG
];
2197 enum machine_mode mode
;
2199 /* If this is not a fixed size move, just call memcpy */
2203 /* If this is not a fixed size alignment, abort */
2204 if (GET_CODE (align_rtx
) != CONST_INT
)
2207 align
= INTVAL (align_rtx
);
2209 /* Anything to move? */
2210 bytes
= INTVAL (bytes_rtx
);
2214 /* Don't support real large moves. */
2215 if (bytes
> TOTAL_MOVE_REG
*align
)
2218 /* Move the address into scratch registers. */
2219 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2220 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2222 num_reg
= offset
= 0;
2223 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2225 /* Calculate the correct offset for src/dest */
2229 dest_addr
= dest_reg
;
2233 src_addr
= plus_constant (src_reg
, offset
);
2234 dest_addr
= plus_constant (dest_reg
, offset
);
2237 /* Generate the appropriate load and store, saving the stores
2239 if (bytes
>= 4 && align
>= 4)
2241 else if (bytes
>= 2 && align
>= 2)
2246 move_bytes
= GET_MODE_SIZE (mode
);
2247 tmp_reg
= gen_reg_rtx (mode
);
2248 src_mem
= change_address (orig_src
, mode
, src_addr
);
2249 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2250 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
, src_mem
));
2251 stores
[num_reg
++] = gen_rtx_SET (VOIDmode
, dest_mem
, tmp_reg
);
2253 if (num_reg
>= MAX_MOVE_REG
)
2255 for (i
= 0; i
< num_reg
; i
++)
2256 emit_insn (stores
[i
]);
2261 for (i
= 0; i
< num_reg
; i
++)
2262 emit_insn (stores
[i
]);
2268 /* Expand a block clear operation, and return 1 if successful. Return 0
2269 if we should let the compiler generate normal code.
2271 operands[0] is the destination
2272 operands[1] is the length
2273 operands[2] is the alignment */
2276 frv_expand_block_clear (operands
)
2279 rtx orig_dest
= operands
[0];
2280 rtx bytes_rtx
= operands
[1];
2281 rtx align_rtx
= operands
[2];
2282 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2291 enum machine_mode mode
;
2293 /* If this is not a fixed size move, just call memcpy */
2297 /* If this is not a fixed size alignment, abort */
2298 if (GET_CODE (align_rtx
) != CONST_INT
)
2301 align
= INTVAL (align_rtx
);
2303 /* Anything to move? */
2304 bytes
= INTVAL (bytes_rtx
);
2308 /* Don't support real large clears. */
2309 if (bytes
> TOTAL_MOVE_REG
*align
)
2312 /* Move the address into a scratch register. */
2313 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2315 num_reg
= offset
= 0;
2316 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2318 /* Calculate the correct offset for src/dest */
2319 dest_addr
= ((offset
== 0)
2321 : plus_constant (dest_reg
, offset
));
2323 /* Generate the appropriate store of gr0 */
2324 if (bytes
>= 4 && align
>= 4)
2326 else if (bytes
>= 2 && align
>= 2)
2331 clear_bytes
= GET_MODE_SIZE (mode
);
2332 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2333 emit_insn (gen_rtx_SET (VOIDmode
, dest_mem
, const0_rtx
));
2340 /* The following variable is used to output modifiers of assembler
2341 code of the current output insn.. */
2343 static rtx
*frv_insn_operands
;
2345 /* The following function is used to add assembler insn code suffix .p
2346 if it is necessary. */
2349 frv_asm_output_opcode (f
, ptr
)
2355 if (! PACKING_FLAG_USED_P())
2358 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2361 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2362 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2364 int letter
= *ptr
++;
2367 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2368 while ((c
= *ptr
) >= '0' && c
<= '9')
2375 if (!frv_insn_packing_flag
)
2381 /* The following function sets up the packing bit for the current
2382 output insn. Remember that the function is not called for asm
2386 frv_final_prescan_insn (insn
, opvec
, noperands
)
2389 int noperands ATTRIBUTE_UNUSED
;
2391 if (! PACKING_FLAG_USED_P())
2394 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
2397 frv_insn_operands
= opvec
;
2399 /* Look for the next printable instruction. frv_pack_insns () has set
2400 things up so that any printable instruction will have TImode if it
2401 starts a new packet and VOIDmode if it should be packed with the
2402 previous instruction.
2404 Printable instructions will be asm_operands or match one of the .md
2405 patterns. Since asm instructions cannot be packed -- and will
2406 therefore have TImode -- this loop terminates on any recognisable
2407 instruction, and on any unrecognisable instruction with TImode. */
2408 for (insn
= NEXT_INSN (insn
); insn
; insn
= NEXT_INSN (insn
))
2412 else if (!INSN_P (insn
))
2414 else if (GET_MODE (insn
) == TImode
|| INSN_CODE (insn
) != -1)
2418 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2419 be packed with this one. Set it to TRUE otherwise. If the next
2420 instruction is an asm insntruction, this statement will set the
2421 flag to TRUE, and that value will still hold when the asm operands
2422 themselves are printed. */
2423 frv_insn_packing_flag
= ! (insn
&& INSN_P (insn
)
2424 && GET_MODE (insn
) != TImode
);
2429 /* A C expression whose value is RTL representing the address in a stack frame
2430 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2431 an RTL expression for the address of the stack frame itself.
2433 If you don't define this macro, the default is to return the value of
2434 FRAMEADDR--that is, the stack frame address is also the address of the stack
2435 word that points to the previous frame. */
2437 /* The default is correct, but we need to make sure the frame gets created. */
2439 frv_dynamic_chain_address (frame
)
2442 cfun
->machine
->frame_needed
= 1;
2447 /* A C expression whose value is RTL representing the value of the return
2448 address for the frame COUNT steps up from the current frame, after the
2449 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2450 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2453 The value of the expression must always be the correct address when COUNT is
2454 zero, but may be `NULL_RTX' if there is not way to determine the return
2455 address of other frames. */
2458 frv_return_addr_rtx (count
, frame
)
2459 int count ATTRIBUTE_UNUSED
;
2462 cfun
->machine
->frame_needed
= 1;
2463 return gen_rtx_MEM (Pmode
, plus_constant (frame
, 8));
2466 /* Given a memory reference MEMREF, interpret the referenced memory as
2467 an array of MODE values, and return a reference to the element
2468 specified by INDEX. Assume that any pre-modification implicit in
2469 MEMREF has already happened.
2471 MEMREF must be a legitimate operand for modes larger than SImode.
2472 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2473 this function cannot handle. */
2475 frv_index_memory (memref
, mode
, index
)
2477 enum machine_mode mode
;
2480 rtx base
= XEXP (memref
, 0);
2481 if (GET_CODE (base
) == PRE_MODIFY
)
2482 base
= XEXP (base
, 0);
2483 return change_address (memref
, mode
,
2484 plus_constant (base
, index
* GET_MODE_SIZE (mode
)));
2488 /* Print a memory address as an operand to reference that memory location. */
2490 frv_print_operand_address (stream
, x
)
2494 if (GET_CODE (x
) == MEM
)
2497 switch (GET_CODE (x
))
2500 fputs (reg_names
[ REGNO (x
)], stream
);
2504 fprintf (stream
, "%ld", (long) INTVAL (x
));
2508 assemble_name (stream
, XSTR (x
, 0));
2513 output_addr_const (stream
, x
);
2520 fatal_insn ("Bad insn to frv_print_operand_address:", x
);
2525 frv_print_operand_memory_reference_reg (stream
, x
)
2529 int regno
= true_regnum (x
);
2531 fputs (reg_names
[regno
], stream
);
2533 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x
);
2536 /* Print a memory reference suitable for the ld/st instructions. */
2539 frv_print_operand_memory_reference (stream
, x
, addr_offset
)
2547 switch (GET_CODE (x
))
2554 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2556 x1
= XEXP (XEXP (x
, 1), 1);
2566 if (GET_CODE (x0
) == CONST_INT
)
2574 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2583 else if (GET_CODE (x1
) != CONST_INT
)
2584 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2587 fputs ("@(", stream
);
2589 fputs (reg_names
[GPR_R0
], stream
);
2590 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2591 frv_print_operand_memory_reference_reg (stream
, x0
);
2593 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2595 fputs (",", stream
);
2597 fputs (reg_names
[GPR_R0
], stream
);
2601 switch (GET_CODE (x1
))
2605 frv_print_operand_memory_reference_reg (stream
, x1
);
2609 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2613 if (x0
&& GET_CODE (x0
) == REG
&& REGNO (x0
) == SDA_BASE_REG
2614 && symbol_ref_small_data_p (x1
))
2616 fputs ("#gprel12(", stream
);
2617 assemble_name (stream
, XSTR (x1
, 0));
2618 fputs (")", stream
);
2621 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2625 if (x0
&& GET_CODE (x0
) == REG
&& REGNO (x0
) == SDA_BASE_REG
2626 && const_small_data_p (x1
))
2628 fputs ("#gprel12(", stream
);
2629 assemble_name (stream
, XSTR (XEXP (XEXP (x1
, 0), 0), 0));
2630 fprintf (stream
, "+%d)", INTVAL (XEXP (XEXP (x1
, 0), 1)));
2633 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2637 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2641 fputs (")", stream
);
2645 /* Return 2 for likely branches and 0 for non-likely branches */
2647 #define FRV_JUMP_LIKELY 2
2648 #define FRV_JUMP_NOT_LIKELY 0
2651 frv_print_operand_jump_hint (insn
)
2657 HOST_WIDE_INT prob
= -1;
2658 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2660 if (GET_CODE (insn
) != JUMP_INSN
)
2663 /* Assume any non-conditional jump is likely. */
2664 if (! any_condjump_p (insn
))
2665 ret
= FRV_JUMP_LIKELY
;
2669 labelref
= condjump_label (insn
);
2672 rtx label
= XEXP (labelref
, 0);
2673 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2678 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2680 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2684 prob
= INTVAL (XEXP (note
, 0));
2685 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2687 : FRV_JUMP_NOT_LIKELY
);
2699 case UNKNOWN
: direction
= "unknown jump direction"; break;
2700 case BACKWARD
: direction
= "jump backward"; break;
2701 case FORWARD
: direction
= "jump forward"; break;
2705 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2706 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2707 (long)INSN_UID (insn
), direction
, (long)prob
,
2708 (long)REG_BR_PROB_BASE
, ret
);
2716 /* Print an operand to an assembler instruction.
2718 `%' followed by a letter and a digit says to output an operand in an
2719 alternate fashion. Four letters have standard, built-in meanings described
2720 below. The machine description macro `PRINT_OPERAND' can define additional
2721 letters with nonstandard meanings.
2723 `%cDIGIT' can be used to substitute an operand that is a constant value
2724 without the syntax that normally indicates an immediate operand.
2726 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2729 `%aDIGIT' can be used to substitute an operand as if it were a memory
2730 reference, with the actual operand treated as the address. This may be
2731 useful when outputting a "load address" instruction, because often the
2732 assembler syntax for such an instruction requires you to write the operand
2733 as if it were a memory reference.
2735 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2737 `%=' outputs a number which is unique to each instruction in the entire
2738 compilation. This is useful for making local labels to be referred to more
2739 than once in a single template that generates multiple assembler
2742 `%' followed by a punctuation character specifies a substitution that does
2743 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2744 assembler code. Other nonstandard cases can be defined in the
2745 `PRINT_OPERAND' macro. You must also define which punctuation characters
2746 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2749 frv_print_operand (file
, x
, code
)
2754 HOST_WIDE_INT value
;
2757 if (code
!= 0 && !isalpha (code
))
2760 else if (GET_CODE (x
) == CONST_INT
)
2763 else if (GET_CODE (x
) == CONST_DOUBLE
)
2765 if (GET_MODE (x
) == SFmode
)
2770 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2771 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2775 else if (GET_MODE (x
) == VOIDmode
)
2776 value
= CONST_DOUBLE_LOW (x
);
2779 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x
);
2790 fputs (reg_names
[GPR_R0
], file
);
2794 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2797 case SDATA_FLAG_CHAR
:
2798 /* Output small data area base register (gr16). */
2799 fputs (reg_names
[SDA_BASE_REG
], file
);
2803 /* Output pic register (gr17). */
2804 fputs (reg_names
[PIC_REGNO
], file
);
2808 /* Output the temporary integer CCR register */
2809 fputs (reg_names
[ICR_TEMP
], file
);
2813 /* Output the temporary integer CC register */
2814 fputs (reg_names
[ICC_TEMP
], file
);
2817 /* case 'a': print an address */
2820 /* Print appropriate test for integer branch false operation */
2821 switch (GET_CODE (x
))
2824 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x
);
2826 case EQ
: fputs ("ne", file
); break;
2827 case NE
: fputs ("eq", file
); break;
2828 case LT
: fputs ("ge", file
); break;
2829 case LE
: fputs ("gt", file
); break;
2830 case GT
: fputs ("le", file
); break;
2831 case GE
: fputs ("lt", file
); break;
2832 case LTU
: fputs ("nc", file
); break;
2833 case LEU
: fputs ("hi", file
); break;
2834 case GTU
: fputs ("ls", file
); break;
2835 case GEU
: fputs ("c", file
); break;
2839 /* case 'c': print a constant without the constant prefix. If
2840 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2843 /* Print appropriate test for integer branch true operation */
2844 switch (GET_CODE (x
))
2847 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x
);
2849 case EQ
: fputs ("eq", file
); break;
2850 case NE
: fputs ("ne", file
); break;
2851 case LT
: fputs ("lt", file
); break;
2852 case LE
: fputs ("le", file
); break;
2853 case GT
: fputs ("gt", file
); break;
2854 case GE
: fputs ("ge", file
); break;
2855 case LTU
: fputs ("c", file
); break;
2856 case LEU
: fputs ("ls", file
); break;
2857 case GTU
: fputs ("hi", file
); break;
2858 case GEU
: fputs ("nc", file
); break;
2863 /* Print 1 for a NE and 0 for an EQ to give the final argument
2864 for a conditional instruction. */
2865 if (GET_CODE (x
) == NE
)
2868 else if (GET_CODE (x
) == EQ
)
2872 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x
);
2876 /* Print appropriate test for floating point branch false operation */
2877 switch (GET_CODE (x
))
2880 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x
);
2882 case EQ
: fputs ("ne", file
); break;
2883 case NE
: fputs ("eq", file
); break;
2884 case LT
: fputs ("uge", file
); break;
2885 case LE
: fputs ("ug", file
); break;
2886 case GT
: fputs ("ule", file
); break;
2887 case GE
: fputs ("ul", file
); break;
2892 /* Print appropriate test for floating point branch true operation */
2893 switch (GET_CODE (x
))
2896 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x
);
2898 case EQ
: fputs ("eq", file
); break;
2899 case NE
: fputs ("ne", file
); break;
2900 case LT
: fputs ("lt", file
); break;
2901 case LE
: fputs ("le", file
); break;
2902 case GT
: fputs ("gt", file
); break;
2903 case GE
: fputs ("ge", file
); break;
2908 /* Print 'i' if the operand is a constant, or is a memory reference that
2910 if (GET_CODE (x
) == MEM
)
2911 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2912 ? XEXP (XEXP (x
, 0), 1)
2915 switch (GET_CODE (x
))
2929 /* For jump instructions, print 'i' if the operand is a constant or
2930 is an expression that adds a constant */
2931 if (GET_CODE (x
) == CONST_INT
)
2936 if (GET_CODE (x
) == CONST_INT
2937 || (GET_CODE (x
) == PLUS
2938 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2939 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2945 /* Print the lower register of a double word register pair */
2946 if (GET_CODE (x
) == REG
)
2947 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2949 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x
);
2952 /* case 'l': print a LABEL_REF */
2956 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2957 for the second word of double memory operations. */
2958 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2959 switch (GET_CODE (x
))
2962 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x
);
2965 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2973 frv_print_operand_memory_reference (file
, x
, offset
);
2979 /* Print the opcode of a command. */
2980 switch (GET_CODE (x
))
2983 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x
);
2985 case PLUS
: fputs ("add", file
); break;
2986 case MINUS
: fputs ("sub", file
); break;
2987 case AND
: fputs ("and", file
); break;
2988 case IOR
: fputs ("or", file
); break;
2989 case XOR
: fputs ("xor", file
); break;
2990 case ASHIFT
: fputs ("sll", file
); break;
2991 case ASHIFTRT
: fputs ("sra", file
); break;
2992 case LSHIFTRT
: fputs ("srl", file
); break;
2996 /* case 'n': negate and print a constant int */
2999 /* Print PIC label using operand as the number. */
3000 if (GET_CODE (x
) != CONST_INT
)
3001 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x
);
3003 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
3007 /* Print 'u' if the operand is a update load/store */
3008 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
3013 /* If value is 0, print gr0, otherwise it must be a register */
3014 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
3015 fputs (reg_names
[GPR_R0
], file
);
3017 else if (GET_CODE (x
) == REG
)
3018 fputs (reg_names
[REGNO (x
)], file
);
3021 fatal_insn ("Bad insn in frv_print_operand, z case", x
);
3025 /* Print constant in hex */
3026 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3028 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
3035 if (GET_CODE (x
) == REG
)
3036 fputs (reg_names
[REGNO (x
)], file
);
3038 else if (GET_CODE (x
) == CONST_INT
3039 || GET_CODE (x
) == CONST_DOUBLE
)
3040 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
3042 else if (GET_CODE (x
) == MEM
)
3043 frv_print_operand_address (file
, XEXP (x
, 0));
3045 else if (CONSTANT_ADDRESS_P (x
))
3046 frv_print_operand_address (file
, x
);
3049 fatal_insn ("Bad insn in frv_print_operand, 0 case", x
);
3054 fatal_insn ("frv_print_operand: unknown code", x
);
3062 /* A C statement (sans semicolon) for initializing the variable CUM for the
3063 state at the beginning of the argument list. The variable has type
3064 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3065 of the function which will receive the args, or 0 if the args are to a
3066 compiler support library function. The value of INDIRECT is nonzero when
3067 processing an indirect call, for example a call through a function pointer.
3068 The value of INDIRECT is zero for a call to an explicitly named function, a
3069 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3070 arguments for the function being compiled.
3072 When processing a call to a compiler support library function, LIBNAME
3073 identifies which one. It is a `symbol_ref' rtx which contains the name of
3074 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3075 being processed. Thus, each time this macro is called, either LIBNAME or
3076 FNTYPE is nonzero, but never both of them at once. */
3079 frv_init_cumulative_args (cum
, fntype
, libname
, indirect
, incoming
)
3080 CUMULATIVE_ARGS
*cum
;
3086 *cum
= FIRST_ARG_REGNUM
;
3088 if (TARGET_DEBUG_ARG
)
3090 fprintf (stderr
, "\ninit_cumulative_args:");
3092 fputs (" indirect", stderr
);
3095 fputs (" incoming", stderr
);
3099 tree ret_type
= TREE_TYPE (fntype
);
3100 fprintf (stderr
, " return=%s,",
3101 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
3104 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3105 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3107 if (cfun
->returns_struct
)
3108 fprintf (stderr
, " return-struct");
3110 putc ('\n', stderr
);
3115 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3116 argument with the specified mode and type. If it is not defined,
3117 `PARM_BOUNDARY' is used for all arguments. */
3120 frv_function_arg_boundary (mode
, type
)
3121 enum machine_mode mode ATTRIBUTE_UNUSED
;
3122 tree type ATTRIBUTE_UNUSED
;
3124 return BITS_PER_WORD
;
3128 /* A C expression that controls whether a function argument is passed in a
3129 register, and which register.
3131 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way
3132 defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous
3133 arguments so far passed in registers; MODE, the machine mode of the argument;
3134 TYPE, the data type of the argument as a tree node or 0 if that is not known
3135 (which happens for C support library functions); and NAMED, which is 1 for an
3136 ordinary argument and 0 for nameless arguments that correspond to `...' in the
3137 called function's prototype.
3139 The value of the expression should either be a `reg' RTX for the hard
3140 register in which to pass the argument, or zero to pass the argument on the
3143 For machines like the VAX and 68000, where normally all arguments are
3144 pushed, zero suffices as a definition.
3146 The usual way to make the ANSI library `stdarg.h' work on a machine where
3147 some arguments are usually passed in registers, is to cause nameless
3148 arguments to be passed on the stack instead. This is done by making
3149 `FUNCTION_ARG' return 0 whenever NAMED is 0.
3151 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
3152 this macro to determine if this argument is of a type that must be passed in
3153 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
3154 returns nonzero for such an argument, the compiler will abort. If
3155 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
3156 stack and then loaded into a register. */
3159 frv_function_arg (cum
, mode
, type
, named
, incoming
)
3160 CUMULATIVE_ARGS
*cum
;
3161 enum machine_mode mode
;
3162 tree type ATTRIBUTE_UNUSED
;
3164 int incoming ATTRIBUTE_UNUSED
;
3166 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3171 /* Return a marker for use in the call instruction. */
3172 if (xmode
== VOIDmode
)
3178 else if (arg_num
<= LAST_ARG_REGNUM
)
3180 ret
= gen_rtx (REG
, xmode
, arg_num
);
3181 debstr
= reg_names
[arg_num
];
3190 if (TARGET_DEBUG_ARG
)
3192 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3193 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3199 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3200 advance past an argument in the argument list. The values MODE, TYPE and
3201 NAMED describe that argument. Once this is done, the variable CUM is
3202 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3204 This macro need not do anything if the argument in question was passed on
3205 the stack. The compiler knows how to track the amount of stack space used
3206 for arguments without any special help. */
3209 frv_function_arg_advance (cum
, mode
, type
, named
)
3210 CUMULATIVE_ARGS
*cum
;
3211 enum machine_mode mode
;
3212 tree type ATTRIBUTE_UNUSED
;
3215 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3216 int bytes
= GET_MODE_SIZE (xmode
);
3217 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3220 *cum
= arg_num
+ words
;
3222 if (TARGET_DEBUG_ARG
)
3224 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3225 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3229 /* A C expression for the number of words, at the beginning of an argument,
3230 must be put in registers. The value must be zero for arguments that are
3231 passed entirely in registers or that are entirely pushed on the stack.
3233 On some machines, certain arguments must be passed partially in registers
3234 and partially in memory. On these machines, typically the first N words of
3235 arguments are passed in registers, and the rest on the stack. If a
3236 multi-word argument (a `double' or a structure) crosses that boundary, its
3237 first few words must be passed in registers and the rest must be pushed.
3238 This macro tells the compiler when this occurs, and how many of the words
3239 should go in registers.
3241 `FUNCTION_ARG' for these arguments should return the first register to be
3242 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3243 the called function. */
3246 frv_function_arg_partial_nregs (cum
, mode
, type
, named
)
3247 CUMULATIVE_ARGS
*cum
;
3248 enum machine_mode mode
;
3249 tree type ATTRIBUTE_UNUSED
;
3250 int named ATTRIBUTE_UNUSED
;
3252 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3253 int bytes
= GET_MODE_SIZE (xmode
);
3254 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3258 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3259 ? LAST_ARG_REGNUM
- arg_num
+ 1
3262 if (TARGET_DEBUG_ARG
&& ret
)
3263 fprintf (stderr
, "function_arg_partial_nregs: %d\n", ret
);
3271 /* A C expression that indicates when an argument must be passed by reference.
3272 If nonzero for an argument, a copy of that argument is made in memory and a
3273 pointer to the argument is passed instead of the argument itself. The
3274 pointer is passed in whatever way is appropriate for passing a pointer to
3277 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
3278 definition of this macro might be
3279 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
3280 MUST_PASS_IN_STACK (MODE, TYPE) */
3283 frv_function_arg_pass_by_reference (cum
, mode
, type
, named
)
3284 CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
3285 enum machine_mode mode
;
3287 int named ATTRIBUTE_UNUSED
;
3289 return MUST_PASS_IN_STACK (mode
, type
);
3292 /* If defined, a C expression that indicates when it is the called function's
3293 responsibility to make a copy of arguments passed by invisible reference.
3294 Normally, the caller makes a copy and passes the address of the copy to the
3295 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3296 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3297 the "live" value. The called function must not modify this value. If it
3298 can be determined that the value won't be modified, it need not make a copy;
3299 otherwise a copy must be made. */
3302 frv_function_arg_callee_copies (cum
, mode
, type
, named
)
3303 CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
3304 enum machine_mode mode ATTRIBUTE_UNUSED
;
3305 tree type ATTRIBUTE_UNUSED
;
3306 int named ATTRIBUTE_UNUSED
;
3311 /* If defined, a C expression that indicates when it is more desirable to keep
3312 an argument passed by invisible reference as a reference, rather than
3313 copying it to a pseudo register. */
3316 frv_function_arg_keep_as_reference (cum
, mode
, type
, named
)
3317 CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
3318 enum machine_mode mode ATTRIBUTE_UNUSED
;
3319 tree type ATTRIBUTE_UNUSED
;
3320 int named ATTRIBUTE_UNUSED
;
3326 /* Return true if a register is ok to use as a base or index register. */
3328 static FRV_INLINE
int
3329 frv_regno_ok_for_base_p (regno
, strict_p
)
3337 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3339 if (regno
== ARG_POINTER_REGNUM
)
3342 return (regno
>= FIRST_PSEUDO_REGISTER
);
3346 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3347 RTX) is a legitimate memory address on the target machine for a memory
3348 operand of mode MODE.
3350 It usually pays to define several simpler macros to serve as subroutines for
3351 this one. Otherwise it may be too complicated to understand.
3353 This macro must exist in two variants: a strict variant and a non-strict
3354 one. The strict variant is used in the reload pass. It must be defined so
3355 that any pseudo-register that has not been allocated a hard register is
3356 considered a memory reference. In contexts where some kind of register is
3357 required, a pseudo-register with no hard register must be rejected.
3359 The non-strict variant is used in other passes. It must be defined to
3360 accept all pseudo-registers in every context where some kind of register is
3363 Compiler source files that want to use the strict variant of this macro
3364 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3365 conditional to define the strict variant in that case and the non-strict
3368 Subroutines to check for acceptable registers for various purposes (one for
3369 base registers, one for index registers, and so on) are typically among the
3370 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3371 subroutine macros need have two variants; the higher levels of macros may be
3372 the same whether strict or not.
3374 Normally, constant addresses which are the sum of a `symbol_ref' and an
3375 integer are stored inside a `const' RTX to mark them as constant.
3376 Therefore, there is no need to recognize such sums specifically as
3377 legitimate addresses. Normally you would simply recognize any `const' as
3380 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3381 are not marked with `const'. It assumes that a naked `plus' indicates
3382 indexing. If so, then you *must* reject such naked constant sums as
3383 illegitimate addresses, so that none of them will be given to
3384 `PRINT_OPERAND_ADDRESS'.
3386 On some machines, whether a symbolic address is legitimate depends on the
3387 section that the address refers to. On these machines, define the macro
3388 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3389 then check for it here. When you see a `const', you will have to look
3390 inside it to find the `symbol_ref' in order to determine the section.
3392 The best way to modify the name string is by adding text to the beginning,
3393 with suitable punctuation to prevent any ambiguity. Allocate the new name
3394 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3395 remove and decode the added text and output the name accordingly, and define
3396 `(* targetm.strip_name_encoding)' to access the original name string.
3398 You can check the information stored here into the `symbol_ref' in the
3399 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3400 `PRINT_OPERAND_ADDRESS'. */
3403 frv_legitimate_address_p (mode
, x
, strict_p
, condexec_p
)
3404 enum machine_mode mode
;
3411 HOST_WIDE_INT value
;
3414 switch (GET_CODE (x
))
3421 if (GET_CODE (x
) != REG
)
3427 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3433 if (GET_CODE (x0
) != REG
3434 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3435 || GET_CODE (x1
) != PLUS
3436 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3437 || GET_CODE (XEXP (x1
, 1)) != REG
3438 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3445 /* 12 bit immediate */
3450 ret
= IN_RANGE_P (INTVAL (x
), -2048, 2047);
3452 /* If we can't use load/store double operations, make sure we can
3453 address the second word. */
3454 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3455 ret
= IN_RANGE_P (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3464 if (GET_CODE (x0
) == SUBREG
)
3465 x0
= SUBREG_REG (x0
);
3467 if (GET_CODE (x0
) != REG
)
3470 regno0
= REGNO (x0
);
3471 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3474 switch (GET_CODE (x1
))
3480 x1
= SUBREG_REG (x1
);
3481 if (GET_CODE (x1
) != REG
)
3487 /* Do not allow reg+reg addressing for modes > 1 word if we can't depend
3488 on having move double instructions */
3489 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3492 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3496 /* 12 bit immediate */
3501 value
= INTVAL (x1
);
3502 ret
= IN_RANGE_P (value
, -2048, 2047);
3504 /* If we can't use load/store double operations, make sure we can
3505 address the second word. */
3506 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3507 ret
= IN_RANGE_P (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3513 && regno0
== SDA_BASE_REG
3514 && symbol_ref_small_data_p (x1
))
3519 if (!condexec_p
&& regno0
== SDA_BASE_REG
&& const_small_data_p (x1
))
3527 if (TARGET_DEBUG_ADDR
)
3529 fprintf (stderr
, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3530 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3531 (condexec_p
) ? ", inside conditional code" : "");
3539 /* A C compound statement that attempts to replace X with a valid memory
3540 address for an operand of mode MODE. WIN will be a C statement label
3541 elsewhere in the code; the macro definition may use
3543 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3545 to avoid further processing if the address has become legitimate.
3547 X will always be the result of a call to `break_out_memory_refs', and OLDX
3548 will be the operand that was given to that function to produce X.
3550 The code generated by this macro should not alter the substructure of X. If
3551 it transforms X into a more legitimate form, it should assign X (which will
3552 always be a C variable) a new value.
3554 It is not necessary for this macro to come up with a legitimate address.
3555 The compiler has standard ways of doing so in all cases. In fact, it is
3556 safe for this macro to do nothing. But often a machine-dependent strategy
3557 can generate better code. */
3560 frv_legitimize_address (x
, oldx
, mode
)
3562 rtx oldx ATTRIBUTE_UNUSED
;
3563 enum machine_mode mode ATTRIBUTE_UNUSED
;
3567 /* Don't try to legitimize addresses if we are not optimizing, since the
3568 address we generate is not a general operand, and will horribly mess
3569 things up when force_reg is called to try and put it in a register because
3570 we aren't optimizing. */
3572 && ((GET_CODE (x
) == SYMBOL_REF
&& symbol_ref_small_data_p (x
))
3573 || (GET_CODE (x
) == CONST
&& const_small_data_p (x
))))
3575 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, SDA_BASE_REG
), x
);
3577 cfun
->uses_pic_offset_table
= TRUE
;
3580 if (TARGET_DEBUG_ADDR
&& ret
!= NULL_RTX
)
3582 fprintf (stderr
, "\n========== LEGITIMIZE_ADDRESS, mode = %s, modified address\n",
3583 GET_MODE_NAME (mode
));
3590 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3591 the operand is used by a predicated instruction. */
3594 frv_legitimate_memory_operand (op
, mode
, condexec_p
)
3596 enum machine_mode mode
;
3599 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3600 && GET_CODE (op
) == MEM
3601 && frv_legitimate_address_p (mode
, XEXP (op
, 0),
3602 reload_completed
, condexec_p
));
3606 /* Return 1 is OP is a memory operand, or will be turned into one by
3609 int frv_load_operand (op
, mode
)
3611 enum machine_mode mode
;
3613 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3616 if (reload_in_progress
)
3619 if (GET_CODE (tmp
) == SUBREG
)
3620 tmp
= SUBREG_REG (tmp
);
3621 if (GET_CODE (tmp
) == REG
3622 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
3623 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
3626 return op
&& memory_operand (op
, mode
);
3630 /* Return 1 if operand is a GPR register or a FPR register. */
3632 int gpr_or_fpr_operand (op
, mode
)
3634 enum machine_mode mode
;
3638 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3641 if (GET_CODE (op
) == SUBREG
)
3643 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3644 return register_operand (op
, mode
);
3646 op
= SUBREG_REG (op
);
3649 if (GET_CODE (op
) != REG
)
3653 if (GPR_P (regno
) || FPR_P (regno
) || regno
>= FIRST_PSEUDO_REGISTER
)
3659 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3661 int gpr_or_int12_operand (op
, mode
)
3663 enum machine_mode mode
;
3665 if (GET_CODE (op
) == CONST_INT
)
3666 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3668 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3671 if (GET_CODE (op
) == SUBREG
)
3673 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3674 return register_operand (op
, mode
);
3676 op
= SUBREG_REG (op
);
3679 if (GET_CODE (op
) != REG
)
3682 return GPR_OR_PSEUDO_P (REGNO (op
));
3685 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3686 signed immediate. */
3688 int gpr_fpr_or_int12_operand (op
, mode
)
3690 enum machine_mode mode
;
3694 if (GET_CODE (op
) == CONST_INT
)
3695 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3697 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3700 if (GET_CODE (op
) == SUBREG
)
3702 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3703 return register_operand (op
, mode
);
3705 op
= SUBREG_REG (op
);
3708 if (GET_CODE (op
) != REG
)
3712 if (GPR_P (regno
) || FPR_P (regno
) || regno
>= FIRST_PSEUDO_REGISTER
)
3718 /* Return 1 if operand is a register or 6 bit signed immediate. */
3720 int fpr_or_int6_operand (op
, mode
)
3722 enum machine_mode mode
;
3724 if (GET_CODE (op
) == CONST_INT
)
3725 return IN_RANGE_P (INTVAL (op
), -32, 31);
3727 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3730 if (GET_CODE (op
) == SUBREG
)
3732 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3733 return register_operand (op
, mode
);
3735 op
= SUBREG_REG (op
);
3738 if (GET_CODE (op
) != REG
)
3741 return FPR_OR_PSEUDO_P (REGNO (op
));
3744 /* Return 1 if operand is a register or 10 bit signed immediate. */
3746 int gpr_or_int10_operand (op
, mode
)
3748 enum machine_mode mode
;
3750 if (GET_CODE (op
) == CONST_INT
)
3751 return IN_RANGE_P (INTVAL (op
), -512, 511);
3753 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3756 if (GET_CODE (op
) == SUBREG
)
3758 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3759 return register_operand (op
, mode
);
3761 op
= SUBREG_REG (op
);
3764 if (GET_CODE (op
) != REG
)
3767 return GPR_OR_PSEUDO_P (REGNO (op
));
3770 /* Return 1 if operand is a register or an integer immediate. */
3772 int gpr_or_int_operand (op
, mode
)
3774 enum machine_mode mode
;
3776 if (GET_CODE (op
) == CONST_INT
)
3779 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3782 if (GET_CODE (op
) == SUBREG
)
3784 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3785 return register_operand (op
, mode
);
3787 op
= SUBREG_REG (op
);
3790 if (GET_CODE (op
) != REG
)
3793 return GPR_OR_PSEUDO_P (REGNO (op
));
3796 /* Return 1 if operand is a 12 bit signed immediate. */
3798 int int12_operand (op
, mode
)
3800 enum machine_mode mode ATTRIBUTE_UNUSED
;
3802 if (GET_CODE (op
) != CONST_INT
)
3805 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3808 /* Return 1 if operand is a 6 bit signed immediate. */
3810 int int6_operand (op
, mode
)
3812 enum machine_mode mode ATTRIBUTE_UNUSED
;
3814 if (GET_CODE (op
) != CONST_INT
)
3817 return IN_RANGE_P (INTVAL (op
), -32, 31);
3820 /* Return 1 if operand is a 5 bit signed immediate. */
3822 int int5_operand (op
, mode
)
3824 enum machine_mode mode ATTRIBUTE_UNUSED
;
3826 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), -16, 15);
3829 /* Return 1 if operand is a 5 bit unsigned immediate. */
3831 int uint5_operand (op
, mode
)
3833 enum machine_mode mode ATTRIBUTE_UNUSED
;
3835 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 31);
3838 /* Return 1 if operand is a 4 bit unsigned immediate. */
3840 int uint4_operand (op
, mode
)
3842 enum machine_mode mode ATTRIBUTE_UNUSED
;
3844 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 15);
3847 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3849 int uint1_operand (op
, mode
)
3851 enum machine_mode mode ATTRIBUTE_UNUSED
;
3853 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 1);
3856 /* Return 1 if operand is an integer constant that takes 2 instructions
3857 to load up and can be split into sethi/setlo instructions.. */
3859 int int_2word_operand (op
, mode
)
3861 enum machine_mode mode ATTRIBUTE_UNUSED
;
3863 HOST_WIDE_INT value
;
3867 switch (GET_CODE (op
))
3873 return (flag_pic
== 0);
3876 /* small data references are already 1 word */
3877 return (flag_pic
== 0) && (! const_small_data_p (op
));
3880 /* small data references are already 1 word */
3881 return (flag_pic
== 0) && (! symbol_ref_small_data_p (op
));
3884 return ! IN_RANGE_P (INTVAL (op
), -32768, 32767);
3887 if (GET_MODE (op
) == SFmode
)
3889 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
3890 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
3892 return ! IN_RANGE_P (value
, -32768, 32767);
3894 else if (GET_MODE (op
) == VOIDmode
)
3896 value
= CONST_DOUBLE_LOW (op
);
3897 return ! IN_RANGE_P (value
, -32768, 32767);
3905 /* Return 1 if operand is the pic address register. */
3907 pic_register_operand (op
, mode
)
3909 enum machine_mode mode ATTRIBUTE_UNUSED
;
3914 if (GET_CODE (op
) != REG
)
3917 if (REGNO (op
) != PIC_REGNO
)
3923 /* Return 1 if operand is a symbolic reference when a PIC option is specified
3924 that takes 3 seperate instructions to form. */
3926 int pic_symbolic_operand (op
, mode
)
3928 enum machine_mode mode ATTRIBUTE_UNUSED
;
3933 switch (GET_CODE (op
))
3942 /* small data references are already 1 word */
3943 return ! symbol_ref_small_data_p (op
);
3946 /* small data references are already 1 word */
3947 return ! const_small_data_p (op
);
3953 /* Return 1 if operand is the small data register. */
3955 small_data_register_operand (op
, mode
)
3957 enum machine_mode mode ATTRIBUTE_UNUSED
;
3959 if (GET_CODE (op
) != REG
)
3962 if (REGNO (op
) != SDA_BASE_REG
)
3968 /* Return 1 if operand is a symbolic reference to a small data area static or
3971 int small_data_symbolic_operand (op
, mode
)
3973 enum machine_mode mode ATTRIBUTE_UNUSED
;
3975 switch (GET_CODE (op
))
3981 return const_small_data_p (op
);
3984 return symbol_ref_small_data_p (op
);
3990 /* Return 1 if operand is a 16 bit unsigned immediate */
3992 int uint16_operand (op
, mode
)
3994 enum machine_mode mode ATTRIBUTE_UNUSED
;
3996 if (GET_CODE (op
) != CONST_INT
)
3999 return IN_RANGE_P (INTVAL (op
), 0, 0xffff);
4002 /* Return 1 if operand is an integer constant with the bottom 16 bits clear */
4004 int upper_int16_operand (op
, mode
)
4006 enum machine_mode mode ATTRIBUTE_UNUSED
;
4008 if (GET_CODE (op
) != CONST_INT
)
4011 return ((INTVAL (op
) & 0xffff) == 0);
4014 /* Return true if operand is a GPR register. */
4017 integer_register_operand (op
, mode
)
4019 enum machine_mode mode
;
4021 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4024 if (GET_CODE (op
) == SUBREG
)
4026 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4027 return register_operand (op
, mode
);
4029 op
= SUBREG_REG (op
);
4032 if (GET_CODE (op
) != REG
)
4035 return GPR_OR_PSEUDO_P (REGNO (op
));
4038 /* Return true if operand is a GPR register. Do not allow SUBREG's
4039 here, in order to prevent a combine bug. */
4042 gpr_no_subreg_operand (op
, mode
)
4044 enum machine_mode mode
;
4046 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4049 if (GET_CODE (op
) != REG
)
4052 return GPR_OR_PSEUDO_P (REGNO (op
));
4055 /* Return true if operand is a FPR register. */
4058 fpr_operand (op
, mode
)
4060 enum machine_mode mode
;
4062 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4065 if (GET_CODE (op
) == SUBREG
)
4067 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4068 return register_operand (op
, mode
);
4070 op
= SUBREG_REG (op
);
4073 if (GET_CODE (op
) != REG
)
4076 return FPR_OR_PSEUDO_P (REGNO (op
));
4079 /* Return true if operand is an even GPR or FPR register. */
4082 even_reg_operand (op
, mode
)
4084 enum machine_mode mode
;
4088 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4091 if (GET_CODE (op
) == SUBREG
)
4093 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4094 return register_operand (op
, mode
);
4096 op
= SUBREG_REG (op
);
4099 if (GET_CODE (op
) != REG
)
4103 if (regno
>= FIRST_PSEUDO_REGISTER
)
4107 return (((regno
- GPR_FIRST
) & 1) == 0);
4110 return (((regno
- FPR_FIRST
) & 1) == 0);
4115 /* Return true if operand is an odd GPR register. */
4118 odd_reg_operand (op
, mode
)
4120 enum machine_mode mode
;
4124 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4127 if (GET_CODE (op
) == SUBREG
)
4129 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4130 return register_operand (op
, mode
);
4132 op
= SUBREG_REG (op
);
4135 if (GET_CODE (op
) != REG
)
4139 /* assume that reload will give us an even register */
4140 if (regno
>= FIRST_PSEUDO_REGISTER
)
4144 return (((regno
- GPR_FIRST
) & 1) != 0);
4147 return (((regno
- FPR_FIRST
) & 1) != 0);
4152 /* Return true if operand is an even GPR register. */
4155 even_gpr_operand (op
, mode
)
4157 enum machine_mode mode
;
4161 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4164 if (GET_CODE (op
) == SUBREG
)
4166 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4167 return register_operand (op
, mode
);
4169 op
= SUBREG_REG (op
);
4172 if (GET_CODE (op
) != REG
)
4176 if (regno
>= FIRST_PSEUDO_REGISTER
)
4179 if (! GPR_P (regno
))
4182 return (((regno
- GPR_FIRST
) & 1) == 0);
4185 /* Return true if operand is an odd GPR register. */
4188 odd_gpr_operand (op
, mode
)
4190 enum machine_mode mode
;
4194 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4197 if (GET_CODE (op
) == SUBREG
)
4199 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4200 return register_operand (op
, mode
);
4202 op
= SUBREG_REG (op
);
4205 if (GET_CODE (op
) != REG
)
4209 /* assume that reload will give us an even register */
4210 if (regno
>= FIRST_PSEUDO_REGISTER
)
4213 if (! GPR_P (regno
))
4216 return (((regno
- GPR_FIRST
) & 1) != 0);
4219 /* Return true if operand is a quad aligned FPR register. */
4222 quad_fpr_operand (op
, mode
)
4224 enum machine_mode mode
;
4228 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4231 if (GET_CODE (op
) == SUBREG
)
4233 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4234 return register_operand (op
, mode
);
4236 op
= SUBREG_REG (op
);
4239 if (GET_CODE (op
) != REG
)
4243 if (regno
>= FIRST_PSEUDO_REGISTER
)
4246 if (! FPR_P (regno
))
4249 return (((regno
- FPR_FIRST
) & 3) == 0);
4252 /* Return true if operand is an even FPR register. */
4255 even_fpr_operand (op
, mode
)
4257 enum machine_mode mode
;
4261 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4264 if (GET_CODE (op
) == SUBREG
)
4266 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4267 return register_operand (op
, mode
);
4269 op
= SUBREG_REG (op
);
4272 if (GET_CODE (op
) != REG
)
4276 if (regno
>= FIRST_PSEUDO_REGISTER
)
4279 if (! FPR_P (regno
))
4282 return (((regno
- FPR_FIRST
) & 1) == 0);
4285 /* Return true if operand is an odd FPR register. */
4288 odd_fpr_operand (op
, mode
)
4290 enum machine_mode mode
;
4294 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4297 if (GET_CODE (op
) == SUBREG
)
4299 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4300 return register_operand (op
, mode
);
4302 op
= SUBREG_REG (op
);
4305 if (GET_CODE (op
) != REG
)
4309 /* assume that reload will give us an even register */
4310 if (regno
>= FIRST_PSEUDO_REGISTER
)
4313 if (! FPR_P (regno
))
4316 return (((regno
- FPR_FIRST
) & 1) != 0);
4319 /* Return true if operand is a 2 word memory address that can be loaded in one
4320 instruction to load or store. We assume the stack and frame pointers are
4321 suitably aligned, and variables in the small data area. FIXME -- at some we
4322 should recognize other globals and statics. We can't assume that any old
4323 pointer is aligned, given that arguments could be passed on an odd word on
4324 the stack and the address taken and passed through to another function. */
4327 dbl_memory_one_insn_operand (op
, mode
)
4329 enum machine_mode mode
;
4337 if (GET_CODE (op
) != MEM
)
4340 if (mode
!= VOIDmode
&& GET_MODE_SIZE (mode
) != 2*UNITS_PER_WORD
)
4343 addr
= XEXP (op
, 0);
4344 if (GET_CODE (addr
) == REG
)
4347 else if (GET_CODE (addr
) == PLUS
)
4349 rtx addr0
= XEXP (addr
, 0);
4350 rtx addr1
= XEXP (addr
, 1);
4352 if (GET_CODE (addr0
) != REG
)
4355 if (plus_small_data_p (addr0
, addr1
))
4358 if (GET_CODE (addr1
) != CONST_INT
)
4361 if ((INTVAL (addr1
) & 7) != 0)
4370 if (addr_reg
== frame_pointer_rtx
|| addr_reg
== stack_pointer_rtx
)
4376 /* Return true if operand is a 2 word memory address that needs to
4377 use two instructions to load or store. */
4380 dbl_memory_two_insn_operand (op
, mode
)
4382 enum machine_mode mode
;
4384 if (GET_CODE (op
) != MEM
)
4387 if (mode
!= VOIDmode
&& GET_MODE_SIZE (mode
) != 2*UNITS_PER_WORD
)
4393 return ! dbl_memory_one_insn_operand (op
, mode
);
4396 /* Return true if operand is something that can be an output for a move
4400 move_destination_operand (op
, mode
)
4402 enum machine_mode mode
;
4407 switch (GET_CODE (op
))
4413 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4416 subreg
= SUBREG_REG (op
);
4417 code
= GET_CODE (subreg
);
4419 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4420 reload_completed
, FALSE
);
4422 return (code
== REG
);
4425 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4431 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4434 return frv_legitimate_memory_operand (op
, mode
, FALSE
);
4440 /* Return true if operand is something that can be an input for a move
4444 move_source_operand (op
, mode
)
4446 enum machine_mode mode
;
4451 switch (GET_CODE (op
))
4461 return immediate_operand (op
, mode
);
4464 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4467 subreg
= SUBREG_REG (op
);
4468 code
= GET_CODE (subreg
);
4470 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4471 reload_completed
, FALSE
);
4473 return (code
== REG
);
4476 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4482 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4485 return frv_legitimate_memory_operand (op
, mode
, FALSE
);
4491 /* Return true if operand is something that can be an output for a conditional
4495 condexec_dest_operand (op
, mode
)
4497 enum machine_mode mode
;
4502 switch (GET_CODE (op
))
4508 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4511 subreg
= SUBREG_REG (op
);
4512 code
= GET_CODE (subreg
);
4514 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4515 reload_completed
, TRUE
);
4517 return (code
== REG
);
4520 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4526 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4529 return frv_legitimate_memory_operand (op
, mode
, TRUE
);
4535 /* Return true if operand is something that can be an input for a conditional
4539 condexec_source_operand (op
, mode
)
4541 enum machine_mode mode
;
4546 switch (GET_CODE (op
))
4556 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4559 subreg
= SUBREG_REG (op
);
4560 code
= GET_CODE (subreg
);
4562 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4563 reload_completed
, TRUE
);
4565 return (code
== REG
);
4568 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4574 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4577 return frv_legitimate_memory_operand (op
, mode
, TRUE
);
4583 /* Return true if operand is a register of any flavor or a 0 of the
4584 appropriate type. */
4587 reg_or_0_operand (op
, mode
)
4589 enum machine_mode mode
;
4591 switch (GET_CODE (op
))
4598 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4601 return register_operand (op
, mode
);
4611 /* Return true if operand is the link register */
4614 lr_operand (op
, mode
)
4616 enum machine_mode mode
;
4618 if (GET_CODE (op
) != REG
)
4621 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4624 if (REGNO (op
) != LR_REGNO
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
)
4630 /* Return true if operand is a gpr register or a valid memory operation. */
4633 gpr_or_memory_operand (op
, mode
)
4635 enum machine_mode mode
;
4637 return (integer_register_operand (op
, mode
)
4638 || frv_legitimate_memory_operand (op
, mode
, FALSE
));
4641 /* Return true if operand is a fpr register or a valid memory operation. */
4644 fpr_or_memory_operand (op
, mode
)
4646 enum machine_mode mode
;
4648 return (fpr_operand (op
, mode
)
4649 || frv_legitimate_memory_operand (op
, mode
, FALSE
));
4652 /* Return true if operand is an icc register */
4655 icc_operand (op
, mode
)
4657 enum machine_mode mode
;
4661 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4664 if (GET_CODE (op
) != REG
)
4668 return ICC_OR_PSEUDO_P (regno
);
4671 /* Return true if operand is an fcc register */
4674 fcc_operand (op
, mode
)
4676 enum machine_mode mode
;
4680 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4683 if (GET_CODE (op
) != REG
)
4687 return FCC_OR_PSEUDO_P (regno
);
4690 /* Return true if operand is either an fcc or icc register */
4693 cc_operand (op
, mode
)
4695 enum machine_mode mode
;
4699 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4702 if (GET_CODE (op
) != REG
)
4706 if (CC_OR_PSEUDO_P (regno
))
4712 /* Return true if operand is an integer CCR register */
4715 icr_operand (op
, mode
)
4717 enum machine_mode mode
;
4721 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4724 if (GET_CODE (op
) != REG
)
4728 return ICR_OR_PSEUDO_P (regno
);
4731 /* Return true if operand is an fcc register */
4734 fcr_operand (op
, mode
)
4736 enum machine_mode mode
;
4740 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4743 if (GET_CODE (op
) != REG
)
4747 return FCR_OR_PSEUDO_P (regno
);
4750 /* Return true if operand is either an fcc or icc register */
4753 cr_operand (op
, mode
)
4755 enum machine_mode mode
;
4759 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4762 if (GET_CODE (op
) != REG
)
4766 if (CR_OR_PSEUDO_P (regno
))
4772 /* Return true if operand is a memory reference suitable for a call. */
4775 call_operand (op
, mode
)
4777 enum machine_mode mode
;
4779 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
&& GET_CODE (op
) != CONST_INT
)
4782 if (GET_CODE (op
) == SYMBOL_REF
)
4785 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4786 never occur anyway), but prevents reload from not handling the case
4787 properly of a call through a pointer on a function that calls
4788 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4789 return gpr_or_int12_operand (op
, mode
);
4792 /* Return true if operator is an kind of relational operator */
4795 relational_operator (op
, mode
)
4797 enum machine_mode mode
;
4803 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4806 switch (GET_CODE (op
))
4825 if (op1
!= const0_rtx
)
4829 if (GET_CODE (op0
) != REG
)
4832 regno
= REGNO (op0
);
4833 switch (GET_MODE (op0
))
4840 return ICC_OR_PSEUDO_P (regno
);
4843 return FCC_OR_PSEUDO_P (regno
);
4846 return CR_OR_PSEUDO_P (regno
);
4852 /* Return true if operator is a signed integer relational operator */
4855 signed_relational_operator (op
, mode
)
4857 enum machine_mode mode
;
4863 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4866 switch (GET_CODE (op
))
4881 if (op1
!= const0_rtx
)
4885 if (GET_CODE (op0
) != REG
)
4888 regno
= REGNO (op0
);
4889 if (GET_MODE (op0
) == CCmode
&& ICC_OR_PSEUDO_P (regno
))
4892 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4898 /* Return true if operator is a signed integer relational operator */
4901 unsigned_relational_operator (op
, mode
)
4903 enum machine_mode mode
;
4909 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4912 switch (GET_CODE (op
))
4925 if (op1
!= const0_rtx
)
4929 if (GET_CODE (op0
) != REG
)
4932 regno
= REGNO (op0
);
4933 if (GET_MODE (op0
) == CC_UNSmode
&& ICC_OR_PSEUDO_P (regno
))
4936 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4942 /* Return true if operator is a floating point relational operator */
4945 float_relational_operator (op
, mode
)
4947 enum machine_mode mode
;
4953 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4956 switch (GET_CODE (op
))
4975 if (op1
!= const0_rtx
)
4979 if (GET_CODE (op0
) != REG
)
4982 regno
= REGNO (op0
);
4983 if (GET_MODE (op0
) == CC_FPmode
&& FCC_OR_PSEUDO_P (regno
))
4986 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4992 /* Return true if operator is EQ/NE of a conditional execution register. */
4995 ccr_eqne_operator (op
, mode
)
4997 enum machine_mode mode
;
4999 enum machine_mode op_mode
= GET_MODE (op
);
5004 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5007 switch (GET_CODE (op
))
5018 if (op1
!= const0_rtx
)
5022 if (GET_CODE (op0
) != REG
)
5025 regno
= REGNO (op0
);
5026 if (op_mode
== CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
5032 /* Return true if operator is a minimum or maximum operator (both signed and
5036 minmax_operator (op
, mode
)
5038 enum machine_mode mode
;
5040 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
5043 switch (GET_CODE (op
))
5055 if (! integer_register_operand (XEXP (op
, 0), mode
))
5058 if (! gpr_or_int10_operand (XEXP (op
, 1), mode
))
5064 /* Return true if operator is an integer binary operator that can executed
5065 conditionally and takes 1 cycle. */
5068 condexec_si_binary_operator (op
, mode
)
5070 enum machine_mode mode
;
5072 enum machine_mode op_mode
= GET_MODE (op
);
5074 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5077 switch (GET_CODE (op
))
5094 /* Return true if operator is an integer binary operator that can be
5095 executed conditionally by a media instruction. */
5098 condexec_si_media_operator (op
, mode
)
5100 enum machine_mode mode
;
5102 enum machine_mode op_mode
= GET_MODE (op
);
5104 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5107 switch (GET_CODE (op
))
5119 /* Return true if operator is an integer division operator that can executed
5123 condexec_si_divide_operator (op
, mode
)
5125 enum machine_mode mode
;
5127 enum machine_mode op_mode
= GET_MODE (op
);
5129 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5132 switch (GET_CODE (op
))
5143 /* Return true if operator is an integer unary operator that can executed
5147 condexec_si_unary_operator (op
, mode
)
5149 enum machine_mode mode
;
5151 enum machine_mode op_mode
= GET_MODE (op
);
5153 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5156 switch (GET_CODE (op
))
5167 /* Return true if operator is a conversion-type expression that can be
5168 evaluated conditionally by floating-point instructions. */
5171 condexec_sf_conv_operator (op
, mode
)
5173 enum machine_mode mode
;
5175 enum machine_mode op_mode
= GET_MODE (op
);
5177 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5180 switch (GET_CODE (op
))
5191 /* Return true if operator is an addition or subtraction expression.
5192 Such expressions can be evaluated conditionally by floating-point
5196 condexec_sf_add_operator (op
, mode
)
5198 enum machine_mode mode
;
5200 enum machine_mode op_mode
= GET_MODE (op
);
5202 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5205 switch (GET_CODE (op
))
5216 /* Return true if the memory operand is one that can be conditionally
5220 condexec_memory_operand (op
, mode
)
5222 enum machine_mode mode
;
5224 enum machine_mode op_mode
= GET_MODE (op
);
5227 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5242 if (GET_CODE (op
) != MEM
)
5245 addr
= XEXP (op
, 0);
5246 if (GET_CODE (addr
) == ADDRESSOF
)
5249 return frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
);
5252 /* Return true if operator is an integer binary operator that can be combined
5253 with a setcc operation. Do not allow the arithmetic operations that could
5254 potentially overflow since the FR-V sets the condition code based on the
5255 "true" value of the result, not the result after truncating to a 32-bit
5259 intop_compare_operator (op
, mode
)
5261 enum machine_mode mode
;
5263 enum machine_mode op_mode
= GET_MODE (op
);
5265 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5268 switch (GET_CODE (op
))
5281 if (! integer_register_operand (XEXP (op
, 0), SImode
))
5284 if (! gpr_or_int10_operand (XEXP (op
, 1), SImode
))
5290 /* Return true if operator is an integer binary operator that can be combined
5291 with a setcc operation inside of a conditional execution. */
5294 condexec_intop_cmp_operator (op
, mode
)
5296 enum machine_mode mode
;
5298 enum machine_mode op_mode
= GET_MODE (op
);
5300 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5303 switch (GET_CODE (op
))
5316 if (! integer_register_operand (XEXP (op
, 0), SImode
))
5319 if (! integer_register_operand (XEXP (op
, 1), SImode
))
5325 /* Return 1 if operand is a valid ACC register number */
5328 acc_operand (op
, mode
)
5330 enum machine_mode mode
;
5334 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5337 if (GET_CODE (op
) == SUBREG
)
5339 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5340 return register_operand (op
, mode
);
5342 op
= SUBREG_REG (op
);
5345 if (GET_CODE (op
) != REG
)
5349 return ACC_OR_PSEUDO_P (regno
);
5352 /* Return 1 if operand is a valid even ACC register number */
5355 even_acc_operand (op
, mode
)
5357 enum machine_mode mode
;
5361 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5364 if (GET_CODE (op
) == SUBREG
)
5366 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5367 return register_operand (op
, mode
);
5369 op
= SUBREG_REG (op
);
5372 if (GET_CODE (op
) != REG
)
5376 return (ACC_OR_PSEUDO_P (regno
) && ((regno
- ACC_FIRST
) & 1) == 0);
5379 /* Return 1 if operand is zero or four */
5382 quad_acc_operand (op
, mode
)
5384 enum machine_mode mode
;
5388 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5391 if (GET_CODE (op
) == SUBREG
)
5393 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5394 return register_operand (op
, mode
);
5396 op
= SUBREG_REG (op
);
5399 if (GET_CODE (op
) != REG
)
5403 return (ACC_OR_PSEUDO_P (regno
) && ((regno
- ACC_FIRST
) & 3) == 0);
5406 /* Return 1 if operand is a valid ACCG register number */
5409 accg_operand (op
, mode
)
5411 enum machine_mode mode
;
5413 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5416 if (GET_CODE (op
) == SUBREG
)
5418 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5419 return register_operand (op
, mode
);
5421 op
= SUBREG_REG (op
);
5424 if (GET_CODE (op
) != REG
)
5427 return ACCG_OR_PSEUDO_P (REGNO (op
));
5431 /* Return true if the bare return instruction can be used outside of the
5432 epilog code. For frv, we only do it if there was no stack allocation. */
5439 if (!reload_completed
)
5442 info
= frv_stack_info ();
5443 return (info
->total_size
== 0);
5447 /* Emit code to handle a MOVSI, adding in the small data register or pic
5448 register if needed to load up addresses. Return TRUE if the appropriate
5449 instructions are emitted. */
5452 frv_emit_movsi (dest
, src
)
5456 int base_regno
= -1;
5458 if (!reload_in_progress
5459 && !reload_completed
5460 && !register_operand (dest
, SImode
)
5461 && (!reg_or_0_operand (src
, SImode
)
5462 /* Virtual registers will almost always be replaced by an
5463 add instruction, so expose this to CSE by copying to
5464 an intermediate register */
5465 || (GET_CODE (src
) == REG
5466 && IN_RANGE_P (REGNO (src
),
5467 FIRST_VIRTUAL_REGISTER
,
5468 LAST_VIRTUAL_REGISTER
))))
5470 emit_insn (gen_rtx_SET (VOIDmode
, dest
, copy_to_mode_reg (SImode
, src
)));
5474 /* Explicitly add in the PIC or small data register if needed. */
5475 switch (GET_CODE (src
))
5482 base_regno
= PIC_REGNO
;
5487 if (const_small_data_p (src
))
5488 base_regno
= SDA_BASE_REG
;
5491 base_regno
= PIC_REGNO
;
5496 if (symbol_ref_small_data_p (src
))
5497 base_regno
= SDA_BASE_REG
;
5500 base_regno
= PIC_REGNO
;
5505 if (base_regno
>= 0)
5507 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
5508 gen_rtx_PLUS (Pmode
,
5509 gen_rtx_REG (Pmode
, base_regno
),
5512 if (base_regno
== PIC_REGNO
)
5513 cfun
->uses_pic_offset_table
= TRUE
;
5522 /* Return a string to output a single word move. */
5525 output_move_single (operands
, insn
)
5529 rtx dest
= operands
[0];
5530 rtx src
= operands
[1];
5532 if (GET_CODE (dest
) == REG
)
5534 int dest_regno
= REGNO (dest
);
5535 enum machine_mode mode
= GET_MODE (dest
);
5537 if (GPR_P (dest_regno
))
5539 if (GET_CODE (src
) == REG
)
5541 /* gpr <- some sort of register */
5542 int src_regno
= REGNO (src
);
5544 if (GPR_P (src_regno
))
5545 return "mov %1, %0";
5547 else if (FPR_P (src_regno
))
5548 return "movfg %1, %0";
5550 else if (SPR_P (src_regno
))
5551 return "movsg %1, %0";
5554 else if (GET_CODE (src
) == MEM
)
5563 return "ldsb%I1%U1 %M1,%0";
5566 return "ldsh%I1%U1 %M1,%0";
5570 return "ld%I1%U1 %M1, %0";
5574 else if (GET_CODE (src
) == CONST_INT
5575 || GET_CODE (src
) == CONST_DOUBLE
)
5577 /* gpr <- integer/floating constant */
5578 HOST_WIDE_INT value
;
5580 if (GET_CODE (src
) == CONST_INT
)
5581 value
= INTVAL (src
);
5583 else if (mode
== SFmode
)
5588 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
5589 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
5594 value
= CONST_DOUBLE_LOW (src
);
5596 if (IN_RANGE_P (value
, -32768, 32767))
5597 return "setlos %1, %0";
5602 else if (GET_CODE (src
) == SYMBOL_REF
5603 || GET_CODE (src
) == LABEL_REF
5604 || GET_CODE (src
) == CONST
)
5606 /* Silently fix up instances where the small data pointer is not
5607 used in the address. */
5608 if (small_data_symbolic_operand (src
, GET_MODE (src
)))
5609 return "addi %@, #gprel12(%1), %0";
5615 else if (FPR_P (dest_regno
))
5617 if (GET_CODE (src
) == REG
)
5619 /* fpr <- some sort of register */
5620 int src_regno
= REGNO (src
);
5622 if (GPR_P (src_regno
))
5623 return "movgf %1, %0";
5625 else if (FPR_P (src_regno
))
5627 if (TARGET_HARD_FLOAT
)
5628 return "fmovs %1, %0";
5630 return "mor %1, %1, %0";
5634 else if (GET_CODE (src
) == MEM
)
5643 return "ldbf%I1%U1 %M1,%0";
5646 return "ldhf%I1%U1 %M1,%0";
5650 return "ldf%I1%U1 %M1, %0";
5654 else if (ZERO_P (src
))
5655 return "movgf %., %0";
5658 else if (SPR_P (dest_regno
))
5660 if (GET_CODE (src
) == REG
)
5662 /* spr <- some sort of register */
5663 int src_regno
= REGNO (src
);
5665 if (GPR_P (src_regno
))
5666 return "movgs %1, %0";
5671 else if (GET_CODE (dest
) == MEM
)
5673 if (GET_CODE (src
) == REG
)
5675 int src_regno
= REGNO (src
);
5676 enum machine_mode mode
= GET_MODE (dest
);
5678 if (GPR_P (src_regno
))
5686 return "stb%I0%U0 %1, %M0";
5689 return "sth%I0%U0 %1, %M0";
5693 return "st%I0%U0 %1, %M0";
5697 else if (FPR_P (src_regno
))
5705 return "stbf%I0%U0 %1, %M0";
5708 return "sthf%I0%U0 %1, %M0";
5712 return "stf%I0%U0 %1, %M0";
5717 else if (ZERO_P (src
))
5719 switch (GET_MODE (dest
))
5725 return "stb%I0%U0 %., %M0";
5728 return "sth%I0%U0 %., %M0";
5732 return "st%I0%U0 %., %M0";
5737 fatal_insn ("Bad output_move_single operand", insn
);
5742 /* Return a string to output a double word move. */
5745 output_move_double (operands
, insn
)
5749 rtx dest
= operands
[0];
5750 rtx src
= operands
[1];
5751 enum machine_mode mode
= GET_MODE (dest
);
5753 if (GET_CODE (dest
) == REG
)
5755 int dest_regno
= REGNO (dest
);
5757 if (GPR_P (dest_regno
))
5759 if (GET_CODE (src
) == REG
)
5761 /* gpr <- some sort of register */
5762 int src_regno
= REGNO (src
);
5764 if (GPR_P (src_regno
))
5767 else if (FPR_P (src_regno
))
5769 if (((dest_regno
- GPR_FIRST
) & 1) == 0
5770 && ((src_regno
- FPR_FIRST
) & 1) == 0)
5771 return "movfgd %1, %0";
5777 else if (GET_CODE (src
) == MEM
)
5780 if (dbl_memory_one_insn_operand (src
, mode
))
5781 return "ldd%I1%U1 %M1, %0";
5786 else if (GET_CODE (src
) == CONST_INT
5787 || GET_CODE (src
) == CONST_DOUBLE
)
5791 else if (FPR_P (dest_regno
))
5793 if (GET_CODE (src
) == REG
)
5795 /* fpr <- some sort of register */
5796 int src_regno
= REGNO (src
);
5798 if (GPR_P (src_regno
))
5800 if (((dest_regno
- FPR_FIRST
) & 1) == 0
5801 && ((src_regno
- GPR_FIRST
) & 1) == 0)
5802 return "movgfd %1, %0";
5807 else if (FPR_P (src_regno
))
5810 && ((dest_regno
- FPR_FIRST
) & 1) == 0
5811 && ((src_regno
- FPR_FIRST
) & 1) == 0)
5812 return "fmovd %1, %0";
5818 else if (GET_CODE (src
) == MEM
)
5821 if (dbl_memory_one_insn_operand (src
, mode
))
5822 return "lddf%I1%U1 %M1, %0";
5827 else if (ZERO_P (src
))
5832 else if (GET_CODE (dest
) == MEM
)
5834 if (GET_CODE (src
) == REG
)
5836 int src_regno
= REGNO (src
);
5838 if (GPR_P (src_regno
))
5840 if (((src_regno
- GPR_FIRST
) & 1) == 0
5841 && dbl_memory_one_insn_operand (dest
, mode
))
5842 return "std%I0%U0 %1, %M0";
5847 if (FPR_P (src_regno
))
5849 if (((src_regno
- FPR_FIRST
) & 1) == 0
5850 && dbl_memory_one_insn_operand (dest
, mode
))
5851 return "stdf%I0%U0 %1, %M0";
5857 else if (ZERO_P (src
))
5859 if (dbl_memory_one_insn_operand (dest
, mode
))
5860 return "std%I0%U0 %., %M0";
5866 fatal_insn ("Bad output_move_double operand", insn
);
5871 /* Return a string to output a single word conditional move.
5872 Operand0 -- EQ/NE of ccr register and 0
5873 Operand1 -- CCR register
5874 Operand2 -- destination
5875 Operand3 -- source */
5878 output_condmove_single (operands
, insn
)
5882 rtx dest
= operands
[2];
5883 rtx src
= operands
[3];
5885 if (GET_CODE (dest
) == REG
)
5887 int dest_regno
= REGNO (dest
);
5888 enum machine_mode mode
= GET_MODE (dest
);
5890 if (GPR_P (dest_regno
))
5892 if (GET_CODE (src
) == REG
)
5894 /* gpr <- some sort of register */
5895 int src_regno
= REGNO (src
);
5897 if (GPR_P (src_regno
))
5898 return "cmov %z3, %2, %1, %e0";
5900 else if (FPR_P (src_regno
))
5901 return "cmovfg %3, %2, %1, %e0";
5904 else if (GET_CODE (src
) == MEM
)
5913 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5916 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5920 return "cld%I3%U3 %M3, %2, %1, %e0";
5924 else if (ZERO_P (src
))
5925 return "cmov %., %2, %1, %e0";
5928 else if (FPR_P (dest_regno
))
5930 if (GET_CODE (src
) == REG
)
5932 /* fpr <- some sort of register */
5933 int src_regno
= REGNO (src
);
5935 if (GPR_P (src_regno
))
5936 return "cmovgf %3, %2, %1, %e0";
5938 else if (FPR_P (src_regno
))
5940 if (TARGET_HARD_FLOAT
)
5941 return "cfmovs %3,%2,%1,%e0";
5943 return "cmor %3, %3, %2, %1, %e0";
5947 else if (GET_CODE (src
) == MEM
)
5950 if (mode
== SImode
|| mode
== SFmode
)
5951 return "cldf%I3%U3 %M3, %2, %1, %e0";
5954 else if (ZERO_P (src
))
5955 return "cmovgf %., %2, %1, %e0";
5959 else if (GET_CODE (dest
) == MEM
)
5961 if (GET_CODE (src
) == REG
)
5963 int src_regno
= REGNO (src
);
5964 enum machine_mode mode
= GET_MODE (dest
);
5966 if (GPR_P (src_regno
))
5974 return "cstb%I2%U2 %3, %M2, %1, %e0";
5977 return "csth%I2%U2 %3, %M2, %1, %e0";
5981 return "cst%I2%U2 %3, %M2, %1, %e0";
5985 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
5986 return "cstf%I2%U2 %3, %M2, %1, %e0";
5989 else if (ZERO_P (src
))
5991 enum machine_mode mode
= GET_MODE (dest
);
5998 return "cstb%I2%U2 %., %M2, %1, %e0";
6001 return "csth%I2%U2 %., %M2, %1, %e0";
6005 return "cst%I2%U2 %., %M2, %1, %e0";
6010 fatal_insn ("Bad output_condmove_single operand", insn
);
6015 /* Emit the appropriate code to do a comparison, returning the register the
6016 comparison was done it. */
6019 frv_emit_comparison (test
, op0
, op1
)
6024 enum machine_mode cc_mode
;
6027 /* Floating point doesn't have comparison against a constant */
6028 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
6029 op1
= force_reg (GET_MODE (op0
), op1
);
6031 /* Possibly disable using anything but a fixed register in order to work
6032 around cse moving comparisons past function calls. */
6033 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
6034 cc_reg
= ((TARGET_ALLOC_CC
)
6035 ? gen_reg_rtx (cc_mode
)
6036 : gen_rtx_REG (cc_mode
,
6037 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
6039 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6040 gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
6046 /* Emit code for a conditional branch. The comparison operands were previously
6047 stored in frv_compare_op0 and frv_compare_op1.
6049 XXX: I originally wanted to add a clobber of a CCR register to use in
6050 conditional execution, but that confuses the rest of the compiler. */
6053 frv_emit_cond_branch (test
, label
)
6060 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
6061 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
6063 /* Branches generate:
6065 (if_then_else (<test>, <cc_reg>, (const_int 0))
6066 (label_ref <branch_label>)
6068 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, label
);
6069 test_rtx
= gen_rtx (test
, cc_mode
, cc_reg
, const0_rtx
);
6070 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
6071 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_else
));
6076 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6077 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6080 frv_emit_scc (test
, target
)
6088 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
6090 /* SCC instructions generate:
6091 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6092 (clobber (<ccr_reg>))]) */
6093 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
6094 set
= gen_rtx_SET (VOIDmode
, target
, test_rtx
);
6096 cr_reg
= ((TARGET_ALLOC_CC
)
6097 ? gen_reg_rtx (CC_CCRmode
)
6098 : gen_rtx_REG (CC_CCRmode
,
6099 ((GET_MODE (cc_reg
) == CC_FPmode
)
6103 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
6104 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
6109 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6110 the seperate insns. */
6113 frv_split_scc (dest
, test
, cc_reg
, cr_reg
, value
)
6118 HOST_WIDE_INT value
;
6124 /* Set the appropriate CCR bit. */
6125 emit_insn (gen_rtx_SET (VOIDmode
,
6127 gen_rtx_fmt_ee (GET_CODE (test
),
6132 /* Move the value into the destination. */
6133 emit_move_insn (dest
, GEN_INT (value
));
6135 /* Move 0 into the destination if the test failed */
6136 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6137 gen_rtx_EQ (GET_MODE (cr_reg
),
6140 gen_rtx_SET (VOIDmode
, dest
, const0_rtx
)));
6142 /* Finish up, return sequence. */
6149 /* Emit the code for a conditional move, return TRUE if we could do the
6153 frv_emit_cond_move (dest
, test_rtx
, src1
, src2
)
6164 enum rtx_code test
= GET_CODE (test_rtx
);
6165 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
6166 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
6168 /* Conditional move instructions generate:
6169 (parallel [(set <target>
6170 (if_then_else (<test> <cc_reg> (const_int 0))
6173 (clobber (<ccr_reg>))]) */
6175 /* Handle various cases of conditional move involving two constants. */
6176 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
6178 HOST_WIDE_INT value1
= INTVAL (src1
);
6179 HOST_WIDE_INT value2
= INTVAL (src2
);
6181 /* having 0 as one of the constants can be done by loading the other
6182 constant, and optionally moving in gr0. */
6183 if (value1
== 0 || value2
== 0)
6186 /* If the first value is within an addi range and also the difference
6187 between the two fits in an addi's range, load up the difference, then
6188 conditionally move in 0, and then unconditionally add the first
6190 else if (IN_RANGE_P (value1
, -2048, 2047)
6191 && IN_RANGE_P (value2
- value1
, -2048, 2047))
6194 /* If neither condition holds, just force the constant into a
6198 src1
= force_reg (GET_MODE (dest
), src1
);
6199 src2
= force_reg (GET_MODE (dest
), src2
);
6203 /* If one value is a register, insure the other value is either 0 or a
6207 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
6208 src1
= force_reg (GET_MODE (dest
), src1
);
6210 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
6211 src2
= force_reg (GET_MODE (dest
), src2
);
6214 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
6215 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
6217 set
= gen_rtx_SET (VOIDmode
, dest
, if_rtx
);
6219 cr_reg
= ((TARGET_ALLOC_CC
)
6220 ? gen_reg_rtx (CC_CCRmode
)
6221 : gen_rtx_REG (CC_CCRmode
,
6222 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
6224 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
6225 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
6230 /* Split a conditonal move into constituent parts, returning a SEQUENCE
6231 containing all of the insns. */
6234 frv_split_cond_move (operands
)
6237 rtx dest
= operands
[0];
6238 rtx test
= operands
[1];
6239 rtx cc_reg
= operands
[2];
6240 rtx src1
= operands
[3];
6241 rtx src2
= operands
[4];
6242 rtx cr_reg
= operands
[5];
6244 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
6248 /* Set the appropriate CCR bit. */
6249 emit_insn (gen_rtx_SET (VOIDmode
,
6251 gen_rtx_fmt_ee (GET_CODE (test
),
6256 /* Handle various cases of conditional move involving two constants. */
6257 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
6259 HOST_WIDE_INT value1
= INTVAL (src1
);
6260 HOST_WIDE_INT value2
= INTVAL (src2
);
6262 /* having 0 as one of the constants can be done by loading the other
6263 constant, and optionally moving in gr0. */
6266 emit_move_insn (dest
, src2
);
6267 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6268 gen_rtx_NE (cr_mode
, cr_reg
,
6270 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6273 else if (value2
== 0)
6275 emit_move_insn (dest
, src1
);
6276 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6277 gen_rtx_EQ (cr_mode
, cr_reg
,
6279 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6282 /* If the first value is within an addi range and also the difference
6283 between the two fits in an addi's range, load up the difference, then
6284 conditionally move in 0, and then unconditionally add the first
6286 else if (IN_RANGE_P (value1
, -2048, 2047)
6287 && IN_RANGE_P (value2
- value1
, -2048, 2047))
6289 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
6291 : gen_rtx_SUBREG (SImode
, dest
, 0));
6293 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
6294 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6295 gen_rtx_NE (cr_mode
, cr_reg
,
6297 gen_rtx_SET (VOIDmode
, dest_si
,
6299 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
6307 /* Emit the conditional move for the test being true if needed. */
6308 if (! rtx_equal_p (dest
, src1
))
6309 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6310 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6311 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6313 /* Emit the conditional move for the test being false if needed. */
6314 if (! rtx_equal_p (dest
, src2
))
6315 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6316 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
6317 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6320 /* Finish up, return sequence. */
6327 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6328 memory location that is not known to be dword-aligned. */
6330 frv_split_double_load (dest
, source
)
6334 int regno
= REGNO (dest
);
6335 rtx dest1
= gen_highpart (SImode
, dest
);
6336 rtx dest2
= gen_lowpart (SImode
, dest
);
6337 rtx address
= XEXP (source
, 0);
6339 /* If the address is pre-modified, load the lower-numbered register
6340 first, then load the other register using an integer offset from
6341 the modified base register. This order should always be safe,
6342 since the pre-modification cannot affect the same registers as the
6345 The situation for other loads is more complicated. Loading one
6346 of the registers could affect the value of ADDRESS, so we must
6347 be careful which order we do them in. */
6348 if (GET_CODE (address
) == PRE_MODIFY
6349 || ! refers_to_regno_p (regno
, regno
+ 1, address
, NULL
))
6351 /* It is safe to load the lower-numbered register first. */
6352 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
6353 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
6357 /* ADDRESS is not pre-modified and the address depends on the
6358 lower-numbered register. Load the higher-numbered register
6360 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
6361 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
6365 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6366 and SOURCE is either a double register or the constant zero. */
6368 frv_split_double_store (dest
, source
)
6372 rtx dest1
= change_address (dest
, SImode
, NULL
);
6373 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
6374 if (ZERO_P (source
))
6376 emit_move_insn (dest1
, CONST0_RTX (SImode
));
6377 emit_move_insn (dest2
, CONST0_RTX (SImode
));
6381 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
6382 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
6387 /* Split a min/max operation returning a SEQUENCE containing all of the
6391 frv_split_minmax (operands
)
6394 rtx dest
= operands
[0];
6395 rtx minmax
= operands
[1];
6396 rtx src1
= operands
[2];
6397 rtx src2
= operands
[3];
6398 rtx cc_reg
= operands
[4];
6399 rtx cr_reg
= operands
[5];
6401 enum rtx_code test_code
;
6402 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
6406 /* Figure out which test to use */
6407 switch (GET_CODE (minmax
))
6412 case SMIN
: test_code
= LT
; break;
6413 case SMAX
: test_code
= GT
; break;
6414 case UMIN
: test_code
= LTU
; break;
6415 case UMAX
: test_code
= GTU
; break;
6418 /* Issue the compare instruction. */
6419 emit_insn (gen_rtx_SET (VOIDmode
,
6421 gen_rtx_COMPARE (GET_MODE (cc_reg
),
6424 /* Set the appropriate CCR bit. */
6425 emit_insn (gen_rtx_SET (VOIDmode
,
6427 gen_rtx_fmt_ee (test_code
,
6432 /* If are taking the min/max of a nonzero constant, load that first, and
6433 then do a conditional move of the other value. */
6434 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
6436 if (rtx_equal_p (dest
, src1
))
6439 emit_move_insn (dest
, src2
);
6440 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6441 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6442 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6445 /* Otherwise, do each half of the move. */
6448 /* Emit the conditional move for the test being true if needed. */
6449 if (! rtx_equal_p (dest
, src1
))
6450 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6451 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6452 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6454 /* Emit the conditional move for the test being false if needed. */
6455 if (! rtx_equal_p (dest
, src2
))
6456 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6457 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
6458 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6461 /* Finish up, return sequence. */
6468 /* Split an integer abs operation returning a SEQUENCE containing all of the
6472 frv_split_abs (operands
)
6475 rtx dest
= operands
[0];
6476 rtx src
= operands
[1];
6477 rtx cc_reg
= operands
[2];
6478 rtx cr_reg
= operands
[3];
6483 /* Issue the compare < 0 instruction. */
6484 emit_insn (gen_rtx_SET (VOIDmode
,
6486 gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
6488 /* Set the appropriate CCR bit. */
6489 emit_insn (gen_rtx_SET (VOIDmode
,
6491 gen_rtx_fmt_ee (LT
, CC_CCRmode
, cc_reg
, const0_rtx
)));
6493 /* Emit the conditional negate if the value is negative */
6494 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6495 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
6496 gen_negsi2 (dest
, src
)));
6498 /* Emit the conditional move for the test being false if needed. */
6499 if (! rtx_equal_p (dest
, src
))
6500 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6501 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
6502 gen_rtx_SET (VOIDmode
, dest
, src
)));
6504 /* Finish up, return sequence. */
6511 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6512 register used in an insn. */
6515 frv_clear_registers_used (ptr
, data
)
6519 if (GET_CODE (*ptr
) == REG
)
6521 int regno
= REGNO (*ptr
);
6522 HARD_REG_SET
*p_regs
= (HARD_REG_SET
*)data
;
6524 if (regno
< FIRST_PSEUDO_REGISTER
)
6526 int reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (*ptr
));
6528 while (regno
< reg_max
)
6530 CLEAR_HARD_REG_BIT (*p_regs
, regno
);
6540 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6542 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6543 initialize the static storage. */
6545 frv_ifcvt_init_extra_fields (ce_info
)
6546 ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
;
6548 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6549 frv_ifcvt
.cur_scratch_regs
= 0;
6550 frv_ifcvt
.num_nested_cond_exec
= 0;
6551 frv_ifcvt
.cr_reg
= NULL_RTX
;
6552 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
6553 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
6554 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
6555 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
6559 /* Internal function to add a potenial insn to the list of insns to be inserted
6560 if the conditional execution conversion is successful. */
6563 frv_ifcvt_add_insn (pattern
, insn
, before_p
)
6568 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
6570 link
->jump
= before_p
; /* mark to add this before or after insn */
6571 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
6572 frv_ifcvt
.added_insns_list
);
6574 if (TARGET_DEBUG_COND_EXEC
)
6577 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6578 (before_p
) ? "before" : "after",
6579 (int)INSN_UID (insn
));
6581 debug_rtx (pattern
);
6586 /* A C expression to modify the code described by the conditional if
6587 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6588 FALSE_EXPR for converting if-then and if-then-else code to conditional
6589 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6590 tests cannot be converted. */
6593 frv_ifcvt_modify_tests (ce_info
, p_true
, p_false
)
6594 ce_if_block_t
*ce_info
;
6598 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
6599 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
6600 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
6601 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
6602 rtx true_expr
= *p_true
;
6606 enum machine_mode mode
= GET_MODE (true_expr
);
6610 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
6612 rtx sub_cond_exec_reg
;
6614 enum rtx_code code_true
;
6615 enum rtx_code code_false
;
6616 enum reg_class cc_class
;
6617 enum reg_class cr_class
;
6621 /* Make sure we are only dealing with hard registers. Also honor the
6622 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6624 if (!reload_completed
|| TARGET_NO_COND_EXEC
6625 || (TARGET_NO_NESTED_CE
&& ce_info
->pass
> 1))
6628 /* Figure out which registers we can allocate for our own purposes. Only
6629 consider registers that are not preserved across function calls and are
6630 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6631 if we did not need to use them in reloading other registers. */
6632 memset ((PTR
) &tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
6633 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
6634 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
6635 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
6636 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
6638 /* If this is a nested IF, we need to discover whether the CC registers that
6639 are set/used inside of the block are used anywhere else. If not, we can
6640 change them to be the CC register that is paired with the CR register that
6641 controls the outermost IF block. */
6642 if (ce_info
->pass
> 1)
6644 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
6645 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6646 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6648 if (REGNO_REG_SET_P (then_bb
->global_live_at_start
, j
))
6651 if (else_bb
&& REGNO_REG_SET_P (else_bb
->global_live_at_start
, j
))
6654 if (join_bb
&& REGNO_REG_SET_P (join_bb
->global_live_at_start
, j
))
6657 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
6661 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
6662 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
6664 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6665 frv_ifcvt
.cur_scratch_regs
= 0;
6667 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
6668 * sizeof (basic_block
));
6674 /* Remove anything live at the beginning of the join block from being
6675 available for allocation. */
6676 EXECUTE_IF_SET_IN_REG_SET (join_bb
->global_live_at_start
, 0, regno
,
6678 if (regno
< FIRST_PSEUDO_REGISTER
)
6679 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
6683 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6685 if (ce_info
->num_multiple_test_blocks
)
6687 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
6689 while (multiple_test_bb
!= test_bb
)
6691 bb
[num_bb
++] = multiple_test_bb
;
6692 multiple_test_bb
= multiple_test_bb
->pred
->src
;
6696 /* Add in the THEN and ELSE blocks to be scanned. */
6697 bb
[num_bb
++] = then_bb
;
6699 bb
[num_bb
++] = else_bb
;
6701 sub_cond_exec_reg
= NULL_RTX
;
6702 frv_ifcvt
.num_nested_cond_exec
= 0;
6704 /* Scan all of the blocks for registers that must not be allocated. */
6705 for (j
= 0; j
< num_bb
; j
++)
6707 rtx last_insn
= bb
[j
]->end
;
6708 rtx insn
= bb
[j
]->head
;
6712 fprintf (rtl_dump_file
, "Scanning %s block %d, start %d, end %d\n",
6713 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
6715 (int) INSN_UID (bb
[j
]->head
),
6716 (int) INSN_UID (bb
[j
]->end
));
6718 /* Anything live at the beginning of the block is obviously unavailable
6720 EXECUTE_IF_SET_IN_REG_SET (bb
[j
]->global_live_at_start
, 0, regno
,
6722 if (regno
< FIRST_PSEUDO_REGISTER
)
6723 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
6726 /* loop through the insns in the block. */
6729 /* Mark any new registers that are created as being unavailable for
6730 allocation. Also see if the CC register used in nested IFs can be
6736 int skip_nested_if
= FALSE
;
6738 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
6739 (void *)&tmp_reg
->regs
);
6741 pattern
= PATTERN (insn
);
6742 if (GET_CODE (pattern
) == COND_EXEC
)
6744 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
6746 if (reg
!= sub_cond_exec_reg
)
6748 sub_cond_exec_reg
= reg
;
6749 frv_ifcvt
.num_nested_cond_exec
++;
6753 set
= single_set_pattern (pattern
);
6756 rtx dest
= SET_DEST (set
);
6757 rtx src
= SET_SRC (set
);
6759 if (GET_CODE (dest
) == REG
)
6761 int regno
= REGNO (dest
);
6762 enum rtx_code src_code
= GET_CODE (src
);
6764 if (CC_P (regno
) && src_code
== COMPARE
)
6765 skip_nested_if
= TRUE
;
6767 else if (CR_P (regno
)
6768 && (src_code
== IF_THEN_ELSE
6769 || GET_RTX_CLASS (src_code
) == '<'))
6770 skip_nested_if
= TRUE
;
6774 if (! skip_nested_if
)
6775 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
6776 (void *)&frv_ifcvt
.nested_cc_ok_rewrite
);
6779 if (insn
== last_insn
)
6782 insn
= NEXT_INSN (insn
);
6786 /* If this is a nested if, rewrite the CC registers that are available to
6787 include the ones that can be rewritten, to increase the chance of being
6788 able to allocate a paired CC/CR register combination. */
6789 if (ce_info
->pass
> 1)
6791 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6792 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
6793 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
6795 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
6801 fprintf (rtl_dump_file
, "Available GPRs: ");
6803 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
6804 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6806 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6807 if (++num_gprs
> GPR_TEMP_NUM
+2)
6811 fprintf (rtl_dump_file
, "%s\nAvailable CRs: ",
6812 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
6814 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
6815 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6816 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6818 fputs ("\n", rtl_dump_file
);
6820 if (ce_info
->pass
> 1)
6822 fprintf (rtl_dump_file
, "Modifiable CCs: ");
6823 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6824 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6825 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6827 fprintf (rtl_dump_file
, "\n%d nested COND_EXEC statements\n",
6828 frv_ifcvt
.num_nested_cond_exec
);
6832 /* Allocate the appropriate temporary condition code register. Try to
6833 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6834 that conditional cmp's can be done. */
6835 if (mode
== CCmode
|| mode
== CC_UNSmode
)
6837 cr_class
= ICR_REGS
;
6838 cc_class
= ICC_REGS
;
6839 cc_first
= ICC_FIRST
;
6842 else if (mode
== CC_FPmode
)
6844 cr_class
= FCR_REGS
;
6845 cc_class
= FCC_REGS
;
6846 cc_first
= FCC_FIRST
;
6851 cc_first
= cc_last
= 0;
6852 cr_class
= cc_class
= NO_REGS
;
6855 cc
= XEXP (true_expr
, 0);
6856 nested_cc
= cr
= NULL_RTX
;
6857 if (cc_class
!= NO_REGS
)
6859 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6860 so we can execute a csubcc/caddcc/cfcmps instruction. */
6863 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
6865 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
6867 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
6868 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
6870 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
6871 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
6874 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
6875 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
6885 fprintf (rtl_dump_file
, "Could not allocate a CR temporary register\n");
6891 fprintf (rtl_dump_file
,
6892 "Will use %s for conditional execution, %s for nested comparisons\n",
6893 reg_names
[ REGNO (cr
)],
6894 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
6896 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6897 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6898 bit being true. We don't do this for floating point, because of NaNs. */
6899 code
= GET_CODE (true_expr
);
6900 if (GET_MODE (cc
) != CC_FPmode
)
6902 code
= reverse_condition (code
);
6912 check_insn
= gen_rtx_SET (VOIDmode
, cr
,
6913 gen_rtx_fmt_ee (code
, CC_CCRmode
, cc
, const0_rtx
));
6915 /* Record the check insn to be inserted later. */
6916 frv_ifcvt_add_insn (check_insn
, test_bb
->end
, TRUE
);
6918 /* Update the tests. */
6919 frv_ifcvt
.cr_reg
= cr
;
6920 frv_ifcvt
.nested_cc_reg
= nested_cc
;
6921 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
6922 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
6925 /* Fail, don't do this conditional execution. */
6928 *p_false
= NULL_RTX
;
6930 fprintf (rtl_dump_file
, "Disabling this conditional execution.\n");
6936 /* A C expression to modify the code described by the conditional if
6937 information CE_INFO, for the basic block BB, possibly updating the tests in
6938 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6939 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6940 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6942 /* p_true and p_false are given expressions of the form:
6944 (and (eq:CC_CCR (reg:CC_CCR)
6950 frv_ifcvt_modify_multiple_tests (ce_info
, bb
, p_true
, p_false
)
6951 ce_if_block_t
*ce_info
;
6956 rtx old_true
= XEXP (*p_true
, 0);
6957 rtx old_false
= XEXP (*p_false
, 0);
6958 rtx true_expr
= XEXP (*p_true
, 1);
6959 rtx false_expr
= XEXP (*p_false
, 1);
6962 rtx cr
= XEXP (old_true
, 0);
6964 rtx new_cr
= NULL_RTX
;
6965 rtx
*p_new_cr
= (rtx
*)0;
6969 enum reg_class cr_class
;
6970 enum machine_mode mode
= GET_MODE (true_expr
);
6971 rtx (*logical_func
)(rtx
, rtx
, rtx
);
6973 if (TARGET_DEBUG_COND_EXEC
)
6976 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
6977 ce_info
->and_and_p
? "&&" : "||");
6979 debug_rtx (*p_true
);
6981 fputs ("\nfalse insn:\n", stderr
);
6982 debug_rtx (*p_false
);
6985 if (TARGET_NO_MULTI_CE
)
6988 if (GET_CODE (cr
) != REG
)
6991 if (mode
== CCmode
|| mode
== CC_UNSmode
)
6993 cr_class
= ICR_REGS
;
6994 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
6996 else if (mode
== CC_FPmode
)
6998 cr_class
= FCR_REGS
;
6999 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
7004 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
7005 more &&/|| tests. */
7009 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
7010 CC_CCRmode
, TRUE
, TRUE
);
7015 if (ce_info
->and_and_p
)
7017 old_test
= old_false
;
7018 test_expr
= true_expr
;
7019 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
7020 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
7021 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
7025 old_test
= old_false
;
7026 test_expr
= false_expr
;
7027 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
7028 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
7029 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
7032 /* First add the andcr/andncr/orcr/orncr, which will be added after the
7033 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
7035 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), bb
->end
, TRUE
);
7037 /* Now add the conditional check insn. */
7038 cc
= XEXP (test_expr
, 0);
7039 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
7040 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
7042 check_insn
= gen_rtx_SET (VOIDmode
, new_cr
, if_else
);
7044 /* add the new check insn to the list of check insns that need to be
7046 frv_ifcvt_add_insn (check_insn
, bb
->end
, TRUE
);
7048 if (TARGET_DEBUG_COND_EXEC
)
7050 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
7053 debug_rtx (*p_true
);
7055 fputs ("\nfalse insn:\n", stderr
);
7056 debug_rtx (*p_false
);
7062 *p_true
= *p_false
= NULL_RTX
;
7064 /* If we allocated a CR register, release it. */
7067 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
7068 *p_new_cr
= NULL_RTX
;
7071 if (TARGET_DEBUG_COND_EXEC
)
7072 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
7078 /* Return a register which will be loaded with a value if an IF block is
7079 converted to conditional execution. This is used to rewrite instructions
7080 that use constants to ones that just use registers. */
7083 frv_ifcvt_load_value (value
, insn
)
7085 rtx insn ATTRIBUTE_UNUSED
;
7087 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
7091 /* We know gr0 == 0, so replace any errant uses. */
7092 if (value
== const0_rtx
)
7093 return gen_rtx_REG (SImode
, GPR_FIRST
);
7095 /* First search all registers currently loaded to see if we have an
7096 applicable constant. */
7097 if (CONSTANT_P (value
)
7098 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
7100 for (i
= 0; i
< num_alloc
; i
++)
7102 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
7103 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
7107 /* Have we exhausted the number of registers available? */
7108 if (num_alloc
>= GPR_TEMP_NUM
)
7111 fprintf (rtl_dump_file
, "Too many temporary registers allocated\n");
7116 /* Allocate the new register. */
7117 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
7121 fputs ("Could not find a scratch register\n", rtl_dump_file
);
7126 frv_ifcvt
.cur_scratch_regs
++;
7127 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (VOIDmode
, reg
, value
);
7131 if (GET_CODE (value
) == CONST_INT
)
7132 fprintf (rtl_dump_file
, "Register %s will hold %ld\n",
7133 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
7135 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
7136 fprintf (rtl_dump_file
, "Register %s will hold LR\n",
7137 reg_names
[ REGNO (reg
)]);
7140 fprintf (rtl_dump_file
, "Register %s will hold a saved value\n",
7141 reg_names
[ REGNO (reg
)]);
7148 /* Update a MEM used in conditional code that might contain an offset to put
7149 the offset into a scratch register, so that the conditional load/store
7150 operations can be used. This function returns the original pointer if the
7151 MEM is valid to use in conditional code, NULL if we can't load up the offset
7152 into a temporary register, or the new MEM if we were successful. */
7155 frv_ifcvt_rewrite_mem (mem
, mode
, insn
)
7157 enum machine_mode mode
;
7160 rtx addr
= XEXP (mem
, 0);
7162 if (!frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
))
7164 if (GET_CODE (addr
) == PLUS
)
7166 rtx addr_op0
= XEXP (addr
, 0);
7167 rtx addr_op1
= XEXP (addr
, 1);
7169 if (plus_small_data_p (addr_op0
, addr_op1
))
7170 addr
= frv_ifcvt_load_value (addr
, insn
);
7172 else if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
7174 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
7178 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
7185 else if (CONSTANT_P (addr
))
7186 addr
= frv_ifcvt_load_value (addr
, insn
);
7191 if (addr
== NULL_RTX
)
7194 else if (XEXP (mem
, 0) != addr
)
7195 return change_address (mem
, mode
, addr
);
7202 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7203 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7206 single_set_pattern (pattern
)
7212 if (GET_CODE (pattern
) == COND_EXEC
)
7213 pattern
= COND_EXEC_CODE (pattern
);
7215 if (GET_CODE (pattern
) == SET
)
7218 else if (GET_CODE (pattern
) == PARALLEL
)
7220 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
7222 rtx sub
= XVECEXP (pattern
, 0, i
);
7224 switch (GET_CODE (sub
))
7248 /* A C expression to modify the code described by the conditional if
7249 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7250 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7251 insn cannot be converted to be executed conditionally. */
7254 frv_ifcvt_modify_insn (ce_info
, pattern
, insn
)
7255 ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
;
7259 rtx orig_ce_pattern
= pattern
;
7265 if (GET_CODE (pattern
) != COND_EXEC
)
7268 test
= COND_EXEC_TEST (pattern
);
7269 if (GET_CODE (test
) == AND
)
7271 rtx cr
= frv_ifcvt
.cr_reg
;
7274 op0
= XEXP (test
, 0);
7275 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
7278 op1
= XEXP (test
, 1);
7279 test_reg
= XEXP (op1
, 0);
7280 if (GET_CODE (test_reg
) != REG
)
7283 /* Is this the first nested if block in this sequence? If so, generate
7284 an andcr or andncr. */
7285 if (! frv_ifcvt
.last_nested_if_cr
)
7289 frv_ifcvt
.last_nested_if_cr
= test_reg
;
7290 if (GET_CODE (op0
) == NE
)
7291 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
7293 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
7295 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
7298 /* If this isn't the first statement in the nested if sequence, see if we
7299 are dealing with the same register. */
7300 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
7303 COND_EXEC_TEST (pattern
) = test
= op1
;
7306 /* If this isn't a nested if, reset state variables. */
7309 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
7312 set
= single_set_pattern (pattern
);
7315 rtx dest
= SET_DEST (set
);
7316 rtx src
= SET_SRC (set
);
7317 enum machine_mode mode
= GET_MODE (dest
);
7319 /* Check for normal binary operators */
7321 && (GET_RTX_CLASS (GET_CODE (src
)) == '2'
7322 || GET_RTX_CLASS (GET_CODE (src
)) == 'c'))
7324 op0
= XEXP (src
, 0);
7325 op1
= XEXP (src
, 1);
7327 /* Special case load of small data address which looks like:
7329 if (GET_CODE (src
) == PLUS
&& plus_small_data_p (op0
, op1
))
7331 src
= frv_ifcvt_load_value (src
, insn
);
7333 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
7338 else if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
7340 op1
= frv_ifcvt_load_value (op1
, insn
);
7342 COND_EXEC_CODE (pattern
)
7343 = gen_rtx_SET (VOIDmode
, dest
, gen_rtx_fmt_ee (GET_CODE (src
),
7351 /* For multiply by a constant, we need to handle the sign extending
7352 correctly. Add a USE of the value after the multiply to prevent flow
7353 from cratering because only one register out of the two were used. */
7354 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
7356 op0
= XEXP (src
, 0);
7357 op1
= XEXP (src
, 1);
7358 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
7360 op1
= frv_ifcvt_load_value (op1
, insn
);
7363 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
7364 COND_EXEC_CODE (pattern
)
7365 = gen_rtx_SET (VOIDmode
, dest
,
7366 gen_rtx_MULT (DImode
, op0
, op1
));
7372 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode
, dest
), insn
, FALSE
);
7375 /* If we are just loading a constant created for a nested conditional
7376 execution statement, just load the constant without any conditional
7377 execution, since we know that the constant will not interfere with any
7379 else if (frv_ifcvt
.scratch_insns_bitmap
7380 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
7384 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
7387 int changed_p
= FALSE
;
7389 /* Check for just loading up a constant */
7390 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
7392 src
= frv_ifcvt_load_value (src
, insn
);
7399 /* See if we need to fix up stores */
7400 if (GET_CODE (dest
) == MEM
)
7402 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
7407 else if (new_mem
!= dest
)
7414 /* See if we need to fix up loads */
7415 if (GET_CODE (src
) == MEM
)
7417 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
7422 else if (new_mem
!= src
)
7429 /* If either src or destination changed, redo SET. */
7431 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
7434 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7435 rewriting the CC register to be the same as the paired CC/CR register
7437 else if (mode
== CC_CCRmode
&& GET_RTX_CLASS (GET_CODE (src
)) == '<')
7439 int regno
= REGNO (XEXP (src
, 0));
7442 if (ce_info
->pass
> 1
7443 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
7444 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
7446 src
= gen_rtx_fmt_ee (GET_CODE (src
),
7448 frv_ifcvt
.nested_cc_reg
,
7452 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
7453 pattern
= gen_rtx_SET (VOIDmode
, dest
, if_else
);
7456 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7457 else if (ce_info
->pass
> 1
7458 && GET_CODE (dest
) == REG
7459 && CC_P (REGNO (dest
))
7460 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
7461 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
7463 && GET_CODE (src
) == COMPARE
)
7465 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
7466 COND_EXEC_CODE (pattern
)
7467 = gen_rtx_SET (VOIDmode
, frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
7471 if (TARGET_DEBUG_COND_EXEC
)
7473 rtx orig_pattern
= PATTERN (insn
);
7475 PATTERN (insn
) = pattern
;
7477 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7481 PATTERN (insn
) = orig_pattern
;
7487 if (TARGET_DEBUG_COND_EXEC
)
7489 rtx orig_pattern
= PATTERN (insn
);
7491 PATTERN (insn
) = orig_ce_pattern
;
7493 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7497 PATTERN (insn
) = orig_pattern
;
7504 /* A C expression to perform any final machine dependent modifications in
7505 converting code to conditional execution in the code described by the
7506 conditional if information CE_INFO. */
7509 frv_ifcvt_modify_final (ce_info
)
7510 ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
;
7514 rtx p
= frv_ifcvt
.added_insns_list
;
7517 /* Loop inserting the check insns. The last check insn is the first test,
7518 and is the appropriate place to insert constants. */
7524 rtx check_and_insert_insns
= XEXP (p
, 0);
7527 check_insn
= XEXP (check_and_insert_insns
, 0);
7528 existing_insn
= XEXP (check_and_insert_insns
, 1);
7531 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7532 the existing insn, otherwise it is to be inserted AFTER. */
7533 if (check_and_insert_insns
->jump
)
7535 emit_insn_before (check_insn
, existing_insn
);
7536 check_and_insert_insns
->jump
= 0;
7539 emit_insn_after (check_insn
, existing_insn
);
7541 free_EXPR_LIST_node (check_and_insert_insns
);
7542 free_EXPR_LIST_node (old_p
);
7544 while (p
!= NULL_RTX
);
7546 /* Load up any constants needed into temp gprs */
7547 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
7549 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
7550 if (! frv_ifcvt
.scratch_insns_bitmap
)
7551 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_XMALLOC ();
7552 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
7553 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
7556 frv_ifcvt
.added_insns_list
= NULL_RTX
;
7557 frv_ifcvt
.cur_scratch_regs
= 0;
7561 /* A C expression to cancel any machine dependent modifications in converting
7562 code to conditional execution in the code described by the conditional if
7563 information CE_INFO. */
7566 frv_ifcvt_modify_cancel (ce_info
)
7567 ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
;
7570 rtx p
= frv_ifcvt
.added_insns_list
;
7572 /* Loop freeing up the EXPR_LIST's allocated. */
7573 while (p
!= NULL_RTX
)
7575 rtx check_and_jump
= XEXP (p
, 0);
7579 free_EXPR_LIST_node (check_and_jump
);
7580 free_EXPR_LIST_node (old_p
);
7583 /* Release any temporary gprs allocated. */
7584 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
7585 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
7587 frv_ifcvt
.added_insns_list
= NULL_RTX
;
7588 frv_ifcvt
.cur_scratch_regs
= 0;
7592 /* A C expression for the size in bytes of the trampoline, as an integer.
7596 setlo #0, <static_chain>
7598 sethi #0, <static_chain>
7599 jmpl @(gr0,<jmp_reg>) */
7602 frv_trampoline_size ()
7604 return 5 /* instructions */ * 4 /* instruction size */;
7608 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7609 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7610 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7611 should be passed to the function when it is called.
7616 setlo #0, <static_chain>
7618 sethi #0, <static_chain>
7619 jmpl @(gr0,<jmp_reg>) */
7622 frv_initialize_trampoline (addr
, fnaddr
, static_chain
)
7627 rtx sc_reg
= force_reg (Pmode
, static_chain
);
7629 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
7632 GEN_INT (frv_trampoline_size ()), SImode
,
7638 /* Many machines have some registers that cannot be copied directly to or from
7639 memory or even from other types of registers. An example is the `MQ'
7640 register, which on most machines, can only be copied to or from general
7641 registers, but not memory. Some machines allow copying all registers to and
7642 from memory, but require a scratch register for stores to some memory
7643 locations (e.g., those with symbolic address on the RT, and those with
7644 certain symbolic address on the SPARC when compiling PIC). In some cases,
7645 both an intermediate and a scratch register are required.
7647 You should define these macros to indicate to the reload phase that it may
7648 need to allocate at least one register for a reload in addition to the
7649 register to contain the data. Specifically, if copying X to a register
7650 CLASS in MODE requires an intermediate register, you should define
7651 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7652 whose registers can be used as intermediate registers or scratch registers.
7654 If copying a register CLASS in MODE to X requires an intermediate or scratch
7655 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7656 largest register class required. If the requirements for input and output
7657 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7658 instead of defining both macros identically.
7660 The values returned by these macros are often `GENERAL_REGS'. Return
7661 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7662 to or from a register of CLASS in MODE without requiring a scratch register.
7663 Do not define this macro if it would always return `NO_REGS'.
7665 If a scratch register is required (either with or without an intermediate
7666 register), you should define patterns for `reload_inM' or `reload_outM', as
7667 required.. These patterns, which will normally be implemented with a
7668 `define_expand', should be similar to the `movM' patterns, except that
7669 operand 2 is the scratch register.
7671 Define constraints for the reload register and scratch register that contain
7672 a single register class. If the original reload register (whose class is
7673 CLASS) can meet the constraint given in the pattern, the value returned by
7674 these macros is used for the class of the scratch register. Otherwise, two
7675 additional reload registers are required. Their classes are obtained from
7676 the constraints in the insn pattern.
7678 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7679 either be in a hard register or in memory. Use `true_regnum' to find out;
7680 it will return -1 if the pseudo is in memory and the hard register number if
7681 it is in a register.
7683 These macros should not be used in the case where a particular class of
7684 registers can only be copied to memory and not to another class of
7685 registers. In that case, secondary reload registers are not needed and
7686 would not be helpful. Instead, a stack location must be used to perform the
7687 copy and the `movM' pattern should use memory as an intermediate storage.
7688 This case often occurs between floating-point and general registers. */
7691 frv_secondary_reload_class (class, mode
, x
, in_p
)
7692 enum reg_class
class;
7693 enum machine_mode mode ATTRIBUTE_UNUSED
;
7695 int in_p ATTRIBUTE_UNUSED
;
7705 /* Accumulators/Accumulator guard registers need to go through floating
7711 if (x
&& GET_CODE (x
) == REG
)
7713 int regno
= REGNO (x
);
7715 if (ACC_P (regno
) || ACCG_P (regno
))
7720 /* Nonzero constants should be loaded into an FPR through a GPR. */
7724 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
7730 /* All of these types need gpr registers. */
7742 /* The accumulators need fpr registers */
7755 /* A C expression whose value is nonzero if pseudos that have been assigned to
7756 registers of class CLASS would likely be spilled because registers of CLASS
7757 are needed for spill registers.
7759 The default value of this macro returns 1 if CLASS has exactly one register
7760 and zero otherwise. On most machines, this default should be used. Only
7761 define this macro to some other expression if pseudo allocated by
7762 `local-alloc.c' end up in memory because their hard registers were needed
7763 for spill registers. If this macro returns nonzero for those classes, those
7764 pseudos will only be allocated by `global.c', which knows how to reallocate
7765 the pseudo to another register. If there would not be another register
7766 available for reallocation, you should not change the definition of this
7767 macro since the only effect of such a definition would be to slow down
7768 register allocation. */
7771 frv_class_likely_spilled_p (class)
7772 enum reg_class
class;
7799 /* An expression for the alignment of a structure field FIELD if the
7800 alignment computed in the usual way is COMPUTED. GNU CC uses this
7801 value instead of the value in `BIGGEST_ALIGNMENT' or
7802 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7804 /* The definition type of the bit field data is either char, short, long or
7805 long long. The maximum bit size is the number of bits of its own type.
7807 The bit field data is assigned to a storage unit that has an adequate size
7808 for bit field data retention and is located at the smallest address.
7810 Consecutive bit field data are packed at consecutive bits having the same
7811 storage unit, with regard to the type, beginning with the MSB and continuing
7814 If a field to be assigned lies over a bit field type boundary, its
7815 assignment is completed by aligning it with a boundary suitable for the
7818 When a bit field having a bit length of 0 is declared, it is forcibly
7819 assigned to the next storage unit.
7832 &x 00000000 00000000 00000000 00000000
7835 &x+4 00000000 00000000 00000000 00000000
7838 &x+8 00000000 00000000 00000000 00000000
7841 &x+12 00000000 00000000 00000000 00000000
7847 frv_adjust_field_align (field
, computed
)
7851 /* C++ provides a null DECL_CONTEXT if the bit field is wider than its
7853 if (DECL_BIT_FIELD (field
) && DECL_CONTEXT (field
))
7855 tree parent
= DECL_CONTEXT (field
);
7856 tree prev
= NULL_TREE
;
7859 /* Loop finding the previous field to the current one */
7860 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= TREE_CHAIN (cur
))
7862 if (TREE_CODE (cur
) != FIELD_DECL
)
7871 /* If this isn't a :0 field and if the previous element is a bitfield
7872 also, see if the type is different, if so, we will need to align the
7873 bit-field to the next boundary */
7875 && ! DECL_PACKED (field
)
7876 && ! integer_zerop (DECL_SIZE (field
))
7877 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
7879 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
7880 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
7881 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
7889 /* A C expression that is nonzero if it is permissible to store a value of mode
7890 MODE in hard register number REGNO (or in several registers starting with
7891 that one). For a machine where all registers are equivalent, a suitable
7894 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7896 It is not necessary for this macro to check for the numbers of fixed
7897 registers, because the allocation mechanism considers them to be always
7900 On some machines, double-precision values must be kept in even/odd register
7901 pairs. The way to implement that is to define this macro to reject odd
7902 register numbers for such modes.
7904 The minimum requirement for a mode to be OK in a register is that the
7905 `movMODE' instruction pattern support moves between the register and any
7906 other hard register for which the mode is OK; and that moving a value into
7907 the register and back out not alter it.
7909 Since the same instruction used to move `SImode' will work for all narrower
7910 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7911 to distinguish between these modes, provided you define patterns `movhi',
7912 etc., to take advantage of this. This is useful because of the interaction
7913 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7914 all integer modes to be tieable.
7916 Many machines have special registers for floating point arithmetic. Often
7917 people assume that floating point machine modes are allowed only in floating
7918 point registers. This is not true. Any registers that can hold integers
7919 can safely *hold* a floating point machine mode, whether or not floating
7920 arithmetic can be done on it in those registers. Integer move instructions
7921 can be used to move the values.
7923 On some machines, though, the converse is true: fixed-point machine modes
7924 may not go in floating registers. This is true if the floating registers
7925 normalize any value stored in them, because storing a non-floating value
7926 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7927 fixed-point machine modes in floating registers. But if the floating
7928 registers do not automatically normalize, if you can store any bit pattern
7929 in one and retrieve it unchanged without a trap, then any machine mode may
7930 go in a floating register, so you can define this macro to say so.
7932 The primary significance of special floating registers is rather that they
7933 are the registers acceptable in floating point arithmetic instructions.
7934 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7935 writing the proper constraints for those instructions.
7937 On some machines, the floating registers are especially slow to access, so
7938 that it is better to store a value in a stack frame than in such a register
7939 if floating point arithmetic is not being done. As long as the floating
7940 registers are not in class `GENERAL_REGS', they will not be used unless some
7941 pattern's constraint asks for one. */
7944 frv_hard_regno_mode_ok (regno
, mode
)
7946 enum machine_mode mode
;
7955 return ICC_P (regno
) || GPR_P (regno
);
7958 return CR_P (regno
) || GPR_P (regno
);
7961 return FCC_P (regno
) || GPR_P (regno
);
7967 /* Set BASE to the first register in REGNO's class. Set MASK to the
7968 bits that must be clear in (REGNO - BASE) for the register to be
7970 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
7974 /* ACCGs store one byte. Two-byte quantities must start in
7975 even-numbered registers, four-byte ones in registers whose
7976 numbers are divisible by four, and so on. */
7978 mask
= GET_MODE_SIZE (mode
) - 1;
7982 /* The other registers store one word. */
7986 else if (FPR_P (regno
))
7989 else if (ACC_P (regno
))
7995 /* Anything smaller than an SI is OK in any word-sized register. */
7996 if (GET_MODE_SIZE (mode
) < 4)
7999 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
8001 return (((regno
- base
) & mask
) == 0);
8008 /* A C expression for the number of consecutive hard registers, starting at
8009 register number REGNO, required to hold a value of mode MODE.
8011 On a machine where all registers are exactly one word, a suitable definition
8014 #define HARD_REGNO_NREGS(REGNO, MODE) \
8015 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
8016 / UNITS_PER_WORD)) */
8018 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
8019 that we can build the appropriate instructions to properly reload the
8020 values. Also, make the byte-sized accumulator guards use one guard
8024 frv_hard_regno_nregs (regno
, mode
)
8026 enum machine_mode mode
;
8029 return GET_MODE_SIZE (mode
);
8031 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8035 /* A C expression for the maximum number of consecutive registers of
8036 class CLASS needed to hold a value of mode MODE.
8038 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
8039 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
8040 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
8042 This macro helps control the handling of multiple-word values in
8045 This declaration is required. */
8048 frv_class_max_nregs (class, mode
)
8049 enum reg_class
class;
8050 enum machine_mode mode
;
8052 if (class == ACCG_REGS
)
8053 /* An N-byte value requires N accumulator guards. */
8054 return GET_MODE_SIZE (mode
);
8056 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8060 /* A C expression that is nonzero if X is a legitimate constant for an
8061 immediate operand on the target machine. You can assume that X satisfies
8062 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8063 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8066 frv_legitimate_constant_p (x
)
8069 enum machine_mode mode
= GET_MODE (x
);
8071 /* All of the integer constants are ok */
8072 if (GET_CODE (x
) != CONST_DOUBLE
)
8075 /* double integer constants are ok */
8076 if (mode
== VOIDmode
|| mode
== DImode
)
8079 /* 0 is always ok */
8080 if (x
== CONST0_RTX (mode
))
8083 /* If floating point is just emulated, allow any constant, since it will be
8084 constructed in the GPRs */
8085 if (!TARGET_HAS_FPRS
)
8088 if (mode
== DFmode
&& !TARGET_DOUBLE
)
8091 /* Otherwise store the constant away and do a load. */
8095 /* A C expression for the cost of moving data from a register in class FROM to
8096 one in class TO. The classes are expressed using the enumeration values
8097 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8098 interpreted relative to that.
8100 It is not required that the cost always equal 2 when FROM is the same as TO;
8101 on some machines it is expensive to move between registers if they are not
8104 If reload sees an insn consisting of a single `set' between two hard
8105 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8106 value of 2, reload does not check to ensure that the constraints of the insn
8107 are met. Setting a cost of other than 2 will allow reload to verify that
8108 the constraints are met. You should do this if the `movM' pattern's
8109 constraints do not allow such copying. */
8111 #define HIGH_COST 40
8112 #define MEDIUM_COST 3
8116 frv_register_move_cost (from
, to
)
8117 enum reg_class from
;
8202 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8203 use ".picptr" to generate safe relocations for PIC code. We also
8204 need a fixup entry for aligned (non-debugging) code. */
8207 frv_assemble_integer (value
, size
, aligned_p
)
8212 if (flag_pic
&& size
== UNITS_PER_WORD
)
8214 if (GET_CODE (value
) == CONST
8215 || GET_CODE (value
) == SYMBOL_REF
8216 || GET_CODE (value
) == LABEL_REF
)
8220 static int label_num
= 0;
8224 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
8225 p
= (* targetm
.strip_name_encoding
) (buf
);
8227 fprintf (asm_out_file
, "%s:\n", p
);
8228 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
8229 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
8230 fprintf (asm_out_file
, "\t.previous\n");
8232 assemble_integer_with_op ("\t.picptr\t", value
);
8237 /* We've set the unaligned SI op to NULL, so we always have to
8238 handle the unaligned case here. */
8239 assemble_integer_with_op ("\t.4byte\t", value
);
8243 return default_assemble_integer (value
, size
, aligned_p
);
8246 /* Function to set up the backend function structure. */
8248 static struct machine_function
*
8249 frv_init_machine_status ()
8251 return ggc_alloc_cleared (sizeof (struct machine_function
));
8255 /* Update the register state information, to know about which registers are set
8259 frv_registers_update (x
, reg_state
, modified
, p_num_mod
, flag
)
8261 unsigned char reg_state
[];
8273 switch (GET_CODE (x
))
8278 /* Clobber just modifies a register, it doesn't make it live. */
8280 frv_registers_update (XEXP (x
, 0), reg_state
, modified
, p_num_mod
,
8281 flag
| REGSTATE_MODIFIED
);
8284 /* Pre modify updates the first argument, just references the second. */
8287 frv_registers_update (XEXP (x
, 0), reg_state
, modified
, p_num_mod
,
8288 flag
| REGSTATE_MODIFIED
| REGSTATE_LIVE
);
8289 frv_registers_update (XEXP (x
, 1), reg_state
, modified
, p_num_mod
, flag
);
8292 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8293 statement, but just to be sure, make sure it is the type of cond_exec
8297 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8298 && GET_CODE (XEXP (cond
, 0)) == REG
8299 && CR_P (REGNO (XEXP (cond
, 0)))
8300 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8301 && INTVAL (XEXP (cond
, 1)) == 0
8302 && (flag
& (REGSTATE_MODIFIED
| REGSTATE_IF_EITHER
)) == 0)
8304 frv_registers_update (cond
, reg_state
, modified
, p_num_mod
, flag
);
8305 flag
|= ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
8306 | ((GET_CODE (cond
) == NE
)
8308 : REGSTATE_IF_FALSE
));
8310 frv_registers_update (XEXP (x
, 1), reg_state
, modified
, p_num_mod
,
8315 fatal_insn ("frv_registers_update", x
);
8317 /* MEM resets the modification bits. */
8319 flag
&= ~REGSTATE_MODIFIED
;
8322 /* See if we need to set the modified flag. */
8324 reg
= SUBREG_REG (x
);
8325 if (GET_CODE (reg
) == REG
)
8327 regno
= subreg_regno (x
);
8328 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8335 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8339 if (flag
& REGSTATE_MODIFIED
)
8341 flag
&= REGSTATE_MASK
;
8342 while (regno
< reg_max
)
8344 int rs
= reg_state
[regno
];
8348 if ((rs
& REGSTATE_MODIFIED
) == 0)
8350 modified
[ *p_num_mod
] = regno
;
8354 /* If the previous register state had the register as
8355 modified, possibly in some conditional execution context,
8356 and the current insn modifies in some other context, or
8357 outside of conditional execution, just mark the variable
8360 flag
&= ~(REGSTATE_IF_EITHER
| REGSTATE_CC_MASK
);
8362 reg_state
[regno
] = (rs
| flag
);
8371 length
= GET_RTX_LENGTH (GET_CODE (x
));
8372 format
= GET_RTX_FORMAT (GET_CODE (x
));
8374 for (j
= 0; j
< length
; ++j
)
8379 frv_registers_update (XEXP (x
, j
), reg_state
, modified
, p_num_mod
,
8385 if (XVEC (x
, j
) != 0)
8388 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8389 frv_registers_update (XVECEXP (x
, j
, k
), reg_state
, modified
,
8395 /* Nothing to do. */
8404 /* Return if any registers in a hard register set were used an insn. */
8407 frv_registers_used_p (x
, reg_state
, flag
)
8409 unsigned char reg_state
[];
8421 switch (GET_CODE (x
))
8426 /* Skip clobber, that doesn't use the previous value */
8430 /* For SET, if a conditional jump has occurred in the same insn, only
8431 allow a set of a CR register if that register is not currently live.
8432 This is because on the FR-V, B0/B1 instructions are always last.
8433 Otherwise, don't look at the result, except within a MEM, but do look
8436 dest
= SET_DEST (x
);
8437 if (flag
& REGSTATE_CONDJUMP
8438 && GET_CODE (dest
) == REG
&& CR_P (REGNO (dest
))
8439 && (reg_state
[ REGNO (dest
) ] & REGSTATE_LIVE
) != 0)
8442 if (GET_CODE (dest
) == MEM
)
8444 result
= frv_registers_used_p (XEXP (dest
, 0), reg_state
, flag
);
8449 return frv_registers_used_p (SET_SRC (x
), reg_state
, flag
);
8451 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8452 statement, but just to be sure, make sure it is the type of cond_exec
8456 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8457 && GET_CODE (XEXP (cond
, 0)) == REG
8458 && CR_P (REGNO (XEXP (cond
, 0)))
8459 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8460 && INTVAL (XEXP (cond
, 1)) == 0
8461 && (flag
& (REGSTATE_MODIFIED
| REGSTATE_IF_EITHER
)) == 0)
8463 result
= frv_registers_used_p (cond
, reg_state
, flag
);
8467 flag
|= ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
8468 | ((GET_CODE (cond
) == NE
)
8470 : REGSTATE_IF_FALSE
));
8472 return frv_registers_used_p (XEXP (x
, 1), reg_state
, flag
);
8475 fatal_insn ("frv_registers_used_p", x
);
8477 /* See if a register or subreg was modified in the same VLIW insn. */
8479 reg
= SUBREG_REG (x
);
8480 if (GET_CODE (reg
) == REG
)
8482 regno
= subreg_regno (x
);
8483 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8490 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8494 while (regno
< reg_max
)
8496 int rs
= reg_state
[regno
];
8498 if (rs
& REGSTATE_MODIFIED
)
8500 int rs_if
= rs
& REGSTATE_IF_EITHER
;
8501 int flag_if
= flag
& REGSTATE_IF_EITHER
;
8503 /* Simple modification, no conditional execution */
8504 if ((rs
& REGSTATE_IF_EITHER
) == 0)
8507 /* See if the variable is only modified in a conditional
8508 execution expression opposite to the conditional execution
8509 expression that governs this expression (ie, true vs. false
8510 for the same CC register). If this isn't two halves of the
8511 same conditional expression, consider the register
8513 if (((rs_if
== REGSTATE_IF_TRUE
&& flag_if
== REGSTATE_IF_FALSE
)
8514 || (rs_if
== REGSTATE_IF_FALSE
&& flag_if
== REGSTATE_IF_TRUE
))
8515 && ((rs
& REGSTATE_CC_MASK
) == (flag
& REGSTATE_CC_MASK
)))
8527 length
= GET_RTX_LENGTH (GET_CODE (x
));
8528 format
= GET_RTX_FORMAT (GET_CODE (x
));
8530 for (j
= 0; j
< length
; ++j
)
8535 result
= frv_registers_used_p (XEXP (x
, j
), reg_state
, flag
);
8542 if (XVEC (x
, j
) != 0)
8545 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8547 result
= frv_registers_used_p (XVECEXP (x
, j
, k
), reg_state
,
8556 /* Nothing to do. */
8564 /* Return if any registers in a hard register set were set in an insn. */
8567 frv_registers_set_p (x
, reg_state
, modify_p
)
8569 unsigned char reg_state
[];
8579 switch (GET_CODE (x
))
8585 return frv_registers_set_p (XEXP (x
, 0), reg_state
, TRUE
);
8589 return (frv_registers_set_p (XEXP (x
, 0), reg_state
, TRUE
)
8590 || frv_registers_set_p (XEXP (x
, 1), reg_state
, FALSE
));
8594 /* just to be sure, make sure it is the type of cond_exec we
8596 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8597 && GET_CODE (XEXP (cond
, 0)) == REG
8598 && CR_P (REGNO (XEXP (cond
, 0)))
8599 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8600 && INTVAL (XEXP (cond
, 1)) == 0
8602 return frv_registers_set_p (XEXP (x
, 1), reg_state
, modify_p
);
8604 fatal_insn ("frv_registers_set_p", x
);
8606 /* MEM resets the modification bits. */
8611 /* See if we need to set the modified modify_p. */
8613 reg
= SUBREG_REG (x
);
8614 if (GET_CODE (reg
) == REG
)
8616 regno
= subreg_regno (x
);
8617 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8624 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8629 while (regno
< reg_max
)
8631 int rs
= reg_state
[regno
];
8633 if (rs
& REGSTATE_MODIFIED
)
8641 length
= GET_RTX_LENGTH (GET_CODE (x
));
8642 format
= GET_RTX_FORMAT (GET_CODE (x
));
8644 for (j
= 0; j
< length
; ++j
)
8649 if (frv_registers_set_p (XEXP (x
, j
), reg_state
, modify_p
))
8655 if (XVEC (x
, j
) != 0)
8658 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8659 if (frv_registers_set_p (XVECEXP (x
, j
, k
), reg_state
,
8666 /* Nothing to do. */
8675 /* In rare cases, correct code generation requires extra machine dependent
8676 processing between the second jump optimization pass and delayed branch
8677 scheduling. On those machines, define this macro as a C statement to act on
8678 the code starting at INSN. */
8680 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8681 conditional branches/calls/jumps, etc. with previous insns where it can. It
8682 does not reorder the instructions. We assume the scheduler left the flow
8683 information in a reasonable state. */
8688 state_t frv_state
; /* frv state machine */
8689 int cur_start_vliw_p
; /* current insn starts a VLIW insn */
8690 int next_start_vliw_p
; /* next insn starts a VLIW insn */
8691 int cur_condjump_p
; /* flag if current insn is a cond jump*/
8692 int next_condjump_p
; /* flag if next insn is a cond jump */
8696 int num_mod
= 0; /* # of modified registers */
8697 int modified
[FIRST_PSEUDO_REGISTER
]; /* registers modified in current VLIW */
8698 /* register state information */
8699 unsigned char reg_state
[FIRST_PSEUDO_REGISTER
];
8701 /* If we weren't going to pack the insns, don't bother with this pass. */
8702 if (!optimize
|| !flag_schedule_insns_after_reload
|| TARGET_NO_VLIW_BRANCH
)
8705 switch (frv_cpu_type
)
8708 case FRV_CPU_FR300
: /* FR300/simple are single issue */
8709 case FRV_CPU_SIMPLE
:
8712 case FRV_CPU_GENERIC
: /* FR-V and FR500 are multi-issue */
8715 case FRV_CPU_TOMCAT
:
8719 /* Set up the instruction and register states. */
8721 frv_state
= (state_t
) xmalloc (state_size ());
8722 memset ((PTR
) reg_state
, REGSTATE_DEAD
, sizeof (reg_state
));
8724 /* Go through the insns, and repack the insns. */
8725 state_reset (frv_state
);
8726 cur_start_vliw_p
= FALSE
;
8727 next_start_vliw_p
= TRUE
;
8729 next_condjump_p
= 0;
8731 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
8733 enum rtx_code code
= GET_CODE (insn
);
8734 enum rtx_code pattern_code
;
8736 /* For basic block begin notes redo the live information, and skip other
8740 if (NOTE_LINE_NUMBER (insn
) == (int)NOTE_INSN_BASIC_BLOCK
)
8744 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
8745 reg_state
[j
] &= ~ REGSTATE_LIVE
;
8747 live
= NOTE_BASIC_BLOCK (insn
)->global_live_at_start
;
8748 EXECUTE_IF_SET_IN_REG_SET(live
, 0, j
,
8750 reg_state
[j
] |= REGSTATE_LIVE
;
8757 /* things like labels reset everything. */
8758 if (GET_RTX_CLASS (code
) != 'i')
8760 next_start_vliw_p
= TRUE
;
8764 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8765 set on the USE insn that preceeds the return, and potentially on
8766 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8767 holding the case table labels. */
8768 pattern_code
= GET_CODE (PATTERN (insn
));
8769 if (pattern_code
== USE
|| pattern_code
== CLOBBER
8770 || pattern_code
== ADDR_VEC
|| pattern_code
== ADDR_DIFF_VEC
)
8772 CLEAR_VLIW_START (insn
);
8776 cur_start_vliw_p
= next_start_vliw_p
;
8777 next_start_vliw_p
= FALSE
;
8779 cur_condjump_p
|= next_condjump_p
;
8780 next_condjump_p
= 0;
8782 /* Unconditional branches and calls end the current VLIW insn. */
8783 if (code
== CALL_INSN
)
8785 next_start_vliw_p
= TRUE
;
8787 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8788 if (frv_cpu_type
== FRV_CPU_TOMCAT
)
8789 cur_start_vliw_p
= TRUE
;
8791 else if (code
== JUMP_INSN
)
8793 if (any_condjump_p (insn
))
8794 next_condjump_p
= REGSTATE_CONDJUMP
;
8796 next_start_vliw_p
= TRUE
;
8799 /* Only allow setting a CCR register after a conditional branch. */
8800 else if (((cur_condjump_p
& REGSTATE_CONDJUMP
) != 0)
8801 && get_attr_type (insn
) != TYPE_CCR
)
8802 cur_start_vliw_p
= TRUE
;
8804 /* Determine if we need to start a new VLIW instruction. */
8805 if (cur_start_vliw_p
8806 /* Do not check for register conflicts in a setlo instruction
8807 because any output or true dependencies will be with the
8808 partnering sethi instruction, with which it can be packed.
8810 Although output dependencies are rare they are still
8811 possible. So check output dependencies in VLIW insn. */
8812 || (get_attr_type (insn
) != TYPE_SETLO
8813 && (frv_registers_used_p (PATTERN (insn
),
8816 || frv_registers_set_p (PATTERN (insn
), reg_state
, FALSE
)))
8817 || state_transition (frv_state
, insn
) >= 0)
8819 SET_VLIW_START (insn
);
8820 state_reset (frv_state
);
8821 state_transition (frv_state
, insn
);
8824 /* Update the modified registers. */
8825 for (j
= 0; j
< num_mod
; j
++)
8826 reg_state
[ modified
[j
] ] &= ~(REGSTATE_CC_MASK
8827 | REGSTATE_IF_EITHER
8828 | REGSTATE_MODIFIED
);
8833 CLEAR_VLIW_START (insn
);
8835 /* Record which registers are modified. */
8836 frv_registers_update (PATTERN (insn
), reg_state
, modified
, &num_mod
, 0);
8838 /* Process the death notices */
8839 for (link
= REG_NOTES (insn
);
8841 link
= XEXP (link
, 1))
8843 rtx reg
= XEXP (link
, 0);
8845 if (REG_NOTE_KIND (link
) == REG_DEAD
&& GET_CODE (reg
) == REG
)
8847 int regno
= REGNO (reg
);
8848 int n
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8849 for (; regno
< n
; regno
++)
8850 reg_state
[regno
] &= ~REGSTATE_LIVE
;
8855 free ((PTR
) frv_state
);
8861 #define def_builtin(name, type, code) \
8862 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8864 struct builtin_description
8866 enum insn_code icode
;
8868 enum frv_builtins code
;
8869 enum rtx_code comparison
;
8873 /* Media intrinsics that take a single, constant argument. */
8875 static struct builtin_description bdesc_set
[] =
8877 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, 0, 0 }
8880 /* Media intrinsics that take just one argument. */
8882 static struct builtin_description bdesc_1arg
[] =
8884 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, 0, 0 },
8885 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, 0, 0 },
8886 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, 0, 0 },
8887 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, 0, 0 },
8888 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, 0, 0 }
8891 /* Media intrinsics that take two arguments. */
8893 static struct builtin_description bdesc_2arg
[] =
8895 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, 0, 0 },
8896 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, 0, 0 },
8897 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, 0, 0 },
8898 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, 0, 0 },
8899 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, 0, 0 },
8900 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, 0, 0 },
8901 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, 0, 0 },
8902 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, 0, 0 },
8903 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, 0, 0 },
8904 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, 0, 0 },
8905 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, 0, 0 },
8906 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, 0, 0 },
8907 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, 0, 0 },
8908 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, 0, 0 },
8909 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, 0, 0 },
8910 { CODE_FOR_mdpackh
, "__MDPACKH", FRV_BUILTIN_MDPACKH
, 0, 0 },
8911 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, 0, 0 },
8912 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, 0, 0 },
8913 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, 0, 0 },
8914 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, 0, 0 }
8917 /* Media intrinsics that take two arguments, the first being an ACC number. */
8919 static struct builtin_description bdesc_cut
[] =
8921 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, 0, 0 },
8922 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, 0, 0 },
8923 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, 0, 0 }
8926 /* Two-argument media intrinsics with an immediate second argument. */
8928 static struct builtin_description bdesc_2argimm
[] =
8930 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, 0, 0 },
8931 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, 0, 0 },
8932 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, 0, 0 },
8933 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, 0, 0 },
8934 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, 0, 0 },
8935 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, 0, 0 },
8936 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, 0, 0 },
8937 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, 0, 0 },
8938 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, 0, 0 },
8939 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, 0, 0 },
8940 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, 0, 0 },
8941 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, 0, 0 },
8942 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, 0, 0 },
8943 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, 0, 0 },
8944 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, 0, 0 }
8947 /* Media intrinsics that take two arguments and return void, the first argument
8948 being a pointer to 4 words in memory. */
8950 static struct builtin_description bdesc_void2arg
[] =
8952 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, 0, 0 },
8953 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, 0, 0 },
8956 /* Media intrinsics that take three arguments, the first being a const_int that
8957 denotes an accumulator, and that return void. */
8959 static struct builtin_description bdesc_void3arg
[] =
8961 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, 0, 0 },
8962 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, 0, 0 },
8963 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, 0, 0 },
8964 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, 0, 0 },
8965 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, 0, 0 },
8966 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, 0, 0 },
8967 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, 0, 0 },
8968 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, 0, 0 },
8969 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, 0, 0 },
8970 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, 0, 0 },
8971 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, 0, 0 },
8972 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, 0, 0 },
8973 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, 0, 0 },
8974 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, 0, 0 },
8975 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, 0, 0 },
8976 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, 0, 0 },
8977 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, 0, 0 },
8978 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, 0, 0 },
8979 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, 0, 0 },
8980 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, 0, 0 },
8981 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, 0, 0 },
8982 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, 0, 0 },
8983 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, 0, 0 },
8984 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, 0, 0 },
8985 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, 0, 0 }
8988 /* Media intrinsics that take two accumulator numbers as argument and
8991 static struct builtin_description bdesc_voidacc
[] =
8993 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, 0, 0 },
8994 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, 0, 0 },
8995 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, 0, 0 },
8996 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, 0, 0 },
8997 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, 0, 0 },
8998 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, 0, 0 }
9001 /* Initialize media builtins. */
9004 frv_init_builtins ()
9006 tree endlink
= void_list_node
;
9007 tree accumulator
= integer_type_node
;
9008 tree integer
= integer_type_node
;
9009 tree voidt
= void_type_node
;
9010 tree uhalf
= short_unsigned_type_node
;
9011 tree sword1
= long_integer_type_node
;
9012 tree uword1
= long_unsigned_type_node
;
9013 tree sword2
= long_long_integer_type_node
;
9014 tree uword2
= long_long_unsigned_type_node
;
9015 tree uword4
= build_pointer_type (uword1
);
9017 #define UNARY(RET, T1) \
9018 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9020 #define BINARY(RET, T1, T2) \
9021 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9022 tree_cons (NULL_TREE, T2, endlink)))
9024 #define TRINARY(RET, T1, T2, T3) \
9025 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9026 tree_cons (NULL_TREE, T2, \
9027 tree_cons (NULL_TREE, T3, endlink))))
9029 tree void_ftype_void
= build_function_type (voidt
, endlink
);
9031 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
9032 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
9033 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
9034 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
9035 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
9036 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
9037 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
9038 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
9039 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
9041 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
9042 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
9043 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
9044 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
9045 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
9046 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
9047 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
9048 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
9049 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
9050 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
9051 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
9053 tree sw1_ftype_int
= UNARY (sword1
, integer
);
9054 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
9055 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
9057 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
9058 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
9059 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
9060 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
9061 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
9063 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
9065 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
9066 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
9067 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
9068 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
9069 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
9070 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
9071 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
9072 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
9073 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
9074 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
9075 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
9076 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
9077 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
9078 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
9079 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
9080 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
9081 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
9082 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
9083 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
9084 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
9085 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
9086 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
9087 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
9088 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
9089 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
9090 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
9091 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
9092 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
9093 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
9094 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
9095 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
9096 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
9097 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
9098 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
9099 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
9100 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
9101 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
9102 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
9103 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
9104 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
9105 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
9106 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
9107 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
9108 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
9109 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
9110 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
9111 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
9112 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
9113 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
9114 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MDPACKH
);
9115 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
9116 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
9117 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
9118 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
9119 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
9120 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
9121 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
9122 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
9123 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
9124 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
9125 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
9126 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
9127 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
9128 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
9129 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
9130 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
9131 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
9132 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
9133 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
9134 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
9135 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
9136 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
9137 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
9138 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
9139 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
9140 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
9141 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
9142 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
9143 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
9144 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
9145 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
9146 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
9147 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
9148 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
9155 /* Convert an integer constant to an accumulator register. ICODE is the
9156 code of the target instruction, OPNUM is the number of the
9157 accumulator operand and OPVAL is the constant integer. Try both
9158 ACC and ACCG registers; only report an error if neither fit the
9162 frv_int_to_acc (icode
, opnum
, opval
)
9163 enum insn_code icode
;
9169 if (GET_CODE (opval
) != CONST_INT
)
9171 error ("accumulator is not a constant integer");
9174 if (! IN_RANGE_P (INTVAL (opval
), 0, NUM_ACCS
- 1))
9176 error ("accumulator number is out of bounds");
9180 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
9181 ACC_FIRST
+ INTVAL (opval
));
9182 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
9183 REGNO (reg
) = ACCG_FIRST
+ INTVAL (opval
);
9185 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
9187 error ("inappropriate accumulator for `%s'", insn_data
[icode
].name
);
9193 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9196 static enum machine_mode
9197 frv_matching_accg_mode (mode
)
9198 enum machine_mode mode
;
9216 /* Return the accumulator guard that should be paired with accumulator
9217 register ACC. The mode of the returned register is in the same
9218 class as ACC, but is four times smaller. */
9221 frv_matching_accg_for_acc (acc
)
9224 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
9225 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
9228 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9229 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9233 frv_read_argument (arglistptr
)
9236 tree next
= TREE_VALUE (*arglistptr
);
9237 *arglistptr
= TREE_CHAIN (*arglistptr
);
9238 return expand_expr (next
, NULL_RTX
, VOIDmode
, 0);
9241 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9242 The instruction should require a constant operand of some sort. The
9243 function prints an error if OPVAL is not valid. */
9246 frv_check_constant_argument (icode
, opnum
, opval
)
9247 enum insn_code icode
;
9251 if (GET_CODE (opval
) != CONST_INT
)
9253 error ("`%s' expects a constant argument", insn_data
[icode
].name
);
9256 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
9258 error ("constant argument out of range for `%s'", insn_data
[icode
].name
);
9264 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9265 if it's not null, has the right mode, and satisfies operand 0's
9269 frv_legitimize_target (icode
, target
)
9270 enum insn_code icode
;
9273 enum machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
9276 || GET_MODE (target
) != mode
9277 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
9278 return gen_reg_rtx (mode
);
9283 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9284 check whether ARG satisfies the operand's contraints. If it doesn't,
9285 copy ARG to a temporary register and return that. Otherwise return ARG
9289 frv_legitimize_argument (icode
, opnum
, arg
)
9290 enum insn_code icode
;
9294 enum machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
9296 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
9299 return copy_to_mode_reg (mode
, arg
);
9302 /* Expand builtins that take a single, constant argument. At the moment,
9303 only MHDSETS falls into this category. */
9306 frv_expand_set_builtin (icode
, arglist
, target
)
9307 enum insn_code icode
;
9312 rtx op0
= frv_read_argument (&arglist
);
9314 if (! frv_check_constant_argument (icode
, 1, op0
))
9317 target
= frv_legitimize_target (icode
, target
);
9318 pat
= GEN_FCN (icode
) (target
, op0
);
9326 /* Expand builtins that take one operand. */
9329 frv_expand_unop_builtin (icode
, arglist
, target
)
9330 enum insn_code icode
;
9335 rtx op0
= frv_read_argument (&arglist
);
9337 target
= frv_legitimize_target (icode
, target
);
9338 op0
= frv_legitimize_argument (icode
, 1, op0
);
9339 pat
= GEN_FCN (icode
) (target
, op0
);
9347 /* Expand builtins that take two operands. */
9350 frv_expand_binop_builtin (icode
, arglist
, target
)
9351 enum insn_code icode
;
9356 rtx op0
= frv_read_argument (&arglist
);
9357 rtx op1
= frv_read_argument (&arglist
);
9359 target
= frv_legitimize_target (icode
, target
);
9360 op0
= frv_legitimize_argument (icode
, 1, op0
);
9361 op1
= frv_legitimize_argument (icode
, 2, op1
);
9362 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9370 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9374 frv_expand_cut_builtin (icode
, arglist
, target
)
9375 enum insn_code icode
;
9380 rtx op0
= frv_read_argument (&arglist
);
9381 rtx op1
= frv_read_argument (&arglist
);
9384 target
= frv_legitimize_target (icode
, target
);
9385 op0
= frv_int_to_acc (icode
, 1, op0
);
9389 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
9391 if (! frv_check_constant_argument (icode
, 2, op1
))
9395 op1
= frv_legitimize_argument (icode
, 2, op1
);
9397 op2
= frv_matching_accg_for_acc (op0
);
9398 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
9406 /* Expand builtins that take two operands and the second is immediate. */
9409 frv_expand_binopimm_builtin (icode
, arglist
, target
)
9410 enum insn_code icode
;
9415 rtx op0
= frv_read_argument (&arglist
);
9416 rtx op1
= frv_read_argument (&arglist
);
9418 if (! frv_check_constant_argument (icode
, 2, op1
))
9421 target
= frv_legitimize_target (icode
, target
);
9422 op0
= frv_legitimize_argument (icode
, 1, op0
);
9423 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9431 /* Expand builtins that take two operands, the first operand being a pointer to
9432 ints and return void. */
9435 frv_expand_voidbinop_builtin (icode
, arglist
)
9436 enum insn_code icode
;
9440 rtx op0
= frv_read_argument (&arglist
);
9441 rtx op1
= frv_read_argument (&arglist
);
9442 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
9445 if (GET_CODE (op0
) != MEM
)
9449 if (! offsettable_address_p (0, mode0
, op0
))
9451 reg
= gen_reg_rtx (Pmode
);
9452 emit_insn (gen_rtx_SET (VOIDmode
, reg
, op0
));
9455 op0
= gen_rtx_MEM (SImode
, reg
);
9458 addr
= XEXP (op0
, 0);
9459 if (! offsettable_address_p (0, mode0
, addr
))
9460 addr
= copy_to_mode_reg (Pmode
, op0
);
9462 op0
= change_address (op0
, V4SImode
, addr
);
9463 op1
= frv_legitimize_argument (icode
, 1, op1
);
9464 pat
= GEN_FCN (icode
) (op0
, op1
);
9472 /* Expand builtins that take three operands and return void. The first
9473 argument must be a constant that describes a pair or quad accumulators. A
9474 fourth argument is created that is the accumulator guard register that
9475 corresponds to the accumulator. */
9478 frv_expand_voidtriop_builtin (icode
, arglist
)
9479 enum insn_code icode
;
9483 rtx op0
= frv_read_argument (&arglist
);
9484 rtx op1
= frv_read_argument (&arglist
);
9485 rtx op2
= frv_read_argument (&arglist
);
9488 op0
= frv_int_to_acc (icode
, 0, op0
);
9492 op1
= frv_legitimize_argument (icode
, 1, op1
);
9493 op2
= frv_legitimize_argument (icode
, 2, op2
);
9494 op3
= frv_matching_accg_for_acc (op0
);
9495 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9503 /* Expand builtins that perform accumulator-to-accumulator operations.
9504 These builtins take two accumulator numbers as argument and return
9508 frv_expand_voidaccop_builtin (icode
, arglist
)
9509 enum insn_code icode
;
9513 rtx op0
= frv_read_argument (&arglist
);
9514 rtx op1
= frv_read_argument (&arglist
);
9518 op0
= frv_int_to_acc (icode
, 0, op0
);
9522 op1
= frv_int_to_acc (icode
, 1, op1
);
9526 op2
= frv_matching_accg_for_acc (op0
);
9527 op3
= frv_matching_accg_for_acc (op1
);
9528 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9536 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9537 number as argument. */
9540 frv_expand_mclracc_builtin (arglist
)
9543 enum insn_code icode
= CODE_FOR_mclracc
;
9545 rtx op0
= frv_read_argument (&arglist
);
9547 op0
= frv_int_to_acc (icode
, 0, op0
);
9551 pat
= GEN_FCN (icode
) (op0
);
9558 /* Expand builtins that take no arguments. */
9561 frv_expand_noargs_builtin (icode
)
9562 enum insn_code icode
;
9564 rtx pat
= GEN_FCN (icode
) (GEN_INT (0));
9571 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9572 number or accumulator guard number as argument and return an SI integer. */
9575 frv_expand_mrdacc_builtin (icode
, arglist
)
9576 enum insn_code icode
;
9580 rtx target
= gen_reg_rtx (SImode
);
9581 rtx op0
= frv_read_argument (&arglist
);
9583 op0
= frv_int_to_acc (icode
, 1, op0
);
9587 pat
= GEN_FCN (icode
) (target
, op0
);
9595 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9596 accumulator guard as their first argument and an SImode value as their
9600 frv_expand_mwtacc_builtin (icode
, arglist
)
9601 enum insn_code icode
;
9605 rtx op0
= frv_read_argument (&arglist
);
9606 rtx op1
= frv_read_argument (&arglist
);
9608 op0
= frv_int_to_acc (icode
, 0, op0
);
9612 op1
= frv_legitimize_argument (icode
, 1, op1
);
9613 pat
= GEN_FCN (icode
) (op0
, op1
);
9620 /* Expand builtins. */
9623 frv_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
9626 rtx subtarget ATTRIBUTE_UNUSED
;
9627 enum machine_mode mode ATTRIBUTE_UNUSED
;
9628 int ignore ATTRIBUTE_UNUSED
;
9630 tree arglist
= TREE_OPERAND (exp
, 1);
9631 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
9632 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9634 struct builtin_description
*d
;
9638 error ("media functions are not available unless -mmedia is used");
9644 case FRV_BUILTIN_MCOP1
:
9645 case FRV_BUILTIN_MCOP2
:
9646 case FRV_BUILTIN_MDUNPACKH
:
9647 case FRV_BUILTIN_MBTOHE
:
9648 if (! TARGET_MEDIA_REV1
)
9650 error ("this media function is only available on the fr500");
9655 case FRV_BUILTIN_MQXMACHS
:
9656 case FRV_BUILTIN_MQXMACXHS
:
9657 case FRV_BUILTIN_MQMACXHS
:
9658 case FRV_BUILTIN_MADDACCS
:
9659 case FRV_BUILTIN_MSUBACCS
:
9660 case FRV_BUILTIN_MASACCS
:
9661 case FRV_BUILTIN_MDADDACCS
:
9662 case FRV_BUILTIN_MDSUBACCS
:
9663 case FRV_BUILTIN_MDASACCS
:
9664 case FRV_BUILTIN_MABSHS
:
9665 case FRV_BUILTIN_MDROTLI
:
9666 case FRV_BUILTIN_MCPLHI
:
9667 case FRV_BUILTIN_MCPLI
:
9668 case FRV_BUILTIN_MDCUTSSI
:
9669 case FRV_BUILTIN_MQSATHS
:
9670 case FRV_BUILTIN_MHSETLOS
:
9671 case FRV_BUILTIN_MHSETLOH
:
9672 case FRV_BUILTIN_MHSETHIS
:
9673 case FRV_BUILTIN_MHSETHIH
:
9674 case FRV_BUILTIN_MHDSETS
:
9675 case FRV_BUILTIN_MHDSETH
:
9676 if (! TARGET_MEDIA_REV2
)
9678 error ("this media function is only available on the fr400");
9687 /* Expand unique builtins. */
9691 case FRV_BUILTIN_MTRAP
:
9692 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9694 case FRV_BUILTIN_MCLRACC
:
9695 return frv_expand_mclracc_builtin (arglist
);
9697 case FRV_BUILTIN_MCLRACCA
:
9699 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9701 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9703 case FRV_BUILTIN_MRDACC
:
9704 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, arglist
);
9706 case FRV_BUILTIN_MRDACCG
:
9707 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, arglist
);
9709 case FRV_BUILTIN_MWTACC
:
9710 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, arglist
);
9712 case FRV_BUILTIN_MWTACCG
:
9713 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, arglist
);
9719 /* Expand groups of builtins. */
9721 for (i
= 0, d
= bdesc_set
; i
< sizeof (bdesc_set
) / sizeof *d
; i
++, d
++)
9722 if (d
->code
== fcode
)
9723 return frv_expand_set_builtin (d
->icode
, arglist
, target
);
9725 for (i
= 0, d
= bdesc_1arg
; i
< sizeof (bdesc_1arg
) / sizeof *d
; i
++, d
++)
9726 if (d
->code
== fcode
)
9727 return frv_expand_unop_builtin (d
->icode
, arglist
, target
);
9729 for (i
= 0, d
= bdesc_2arg
; i
< sizeof (bdesc_2arg
) / sizeof *d
; i
++, d
++)
9730 if (d
->code
== fcode
)
9731 return frv_expand_binop_builtin (d
->icode
, arglist
, target
);
9733 for (i
= 0, d
= bdesc_cut
; i
< sizeof (bdesc_cut
) / sizeof *d
; i
++, d
++)
9734 if (d
->code
== fcode
)
9735 return frv_expand_cut_builtin (d
->icode
, arglist
, target
);
9737 for (i
= 0, d
= bdesc_2argimm
;
9738 i
< sizeof (bdesc_2argimm
) / sizeof *d
;
9741 if (d
->code
== fcode
)
9742 return frv_expand_binopimm_builtin (d
->icode
, arglist
, target
);
9745 for (i
= 0, d
= bdesc_void2arg
;
9746 i
< sizeof (bdesc_void2arg
) / sizeof *d
;
9749 if (d
->code
== fcode
)
9750 return frv_expand_voidbinop_builtin (d
->icode
, arglist
);
9753 for (i
= 0, d
= bdesc_void3arg
;
9754 i
< sizeof (bdesc_void3arg
) / sizeof *d
;
9757 if (d
->code
== fcode
)
9758 return frv_expand_voidtriop_builtin (d
->icode
, arglist
);
9761 for (i
= 0, d
= bdesc_voidacc
;
9762 i
< sizeof (bdesc_voidacc
) / sizeof *d
;
9765 if (d
->code
== fcode
)
9766 return frv_expand_voidaccop_builtin (d
->icode
, arglist
);
9772 frv_strip_name_encoding (str
)
9775 while (*str
== '*' || *str
== SDATA_FLAG_CHAR
)
9781 frv_in_small_data_p (decl
)
9784 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
9786 return symbol_ref_small_data_p (XEXP (DECL_RTL (decl
), 0))
9787 && size
> 0 && size
<= g_switch_value
;