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1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "regs.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "output.h"
35 #include "insn-attr.h"
36 #include "flags.h"
37 #include "recog.h"
38 #include "expr.h"
39 #include "function.h"
40 #include "optabs.h"
41 #include "diagnostic-core.h"
42 #include "c-family/c-pragma.h" /* ??? */
43 #include "tm_p.h"
44 #include "tm-constrs.h"
45 #include "ggc.h"
46 #include "target.h"
47 #include "target-def.h"
48 #include "df.h"
49
50 /* Classifies a h8300_src_operand or h8300_dst_operand.
51
52 H8OP_IMMEDIATE
53 A constant operand of some sort.
54
55 H8OP_REGISTER
56 An ordinary register.
57
58 H8OP_MEM_ABSOLUTE
59 A memory reference with a constant address.
60
61 H8OP_MEM_BASE
62 A memory reference with a register as its address.
63
64 H8OP_MEM_COMPLEX
65 Some other kind of memory reference. */
66 enum h8300_operand_class
67 {
68 H8OP_IMMEDIATE,
69 H8OP_REGISTER,
70 H8OP_MEM_ABSOLUTE,
71 H8OP_MEM_BASE,
72 H8OP_MEM_COMPLEX,
73 NUM_H8OPS
74 };
75
76 /* For a general two-operand instruction, element [X][Y] gives
77 the length of the opcode fields when the first operand has class
78 (X + 1) and the second has class Y. */
79 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
80
81 /* Forward declarations. */
82 static const char *byte_reg (rtx, int);
83 static int h8300_interrupt_function_p (tree);
84 static int h8300_saveall_function_p (tree);
85 static int h8300_monitor_function_p (tree);
86 static int h8300_os_task_function_p (tree);
87 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
88 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
89 static unsigned int compute_saved_regs (void);
90 static void push (int);
91 static void pop (int);
92 static const char *cond_string (enum rtx_code);
93 static unsigned int h8300_asm_insn_count (const char *);
94 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
95 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
96 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
97 static void h8300_print_operand_address (FILE *, rtx);
98 static void h8300_print_operand (FILE *, rtx, int);
99 static bool h8300_print_operand_punct_valid_p (unsigned char code);
100 #ifndef OBJECT_FORMAT_ELF
101 static void h8300_asm_named_section (const char *, unsigned int, tree);
102 #endif
103 static int h8300_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
104 static int h8300_and_costs (rtx);
105 static int h8300_shift_costs (rtx);
106 static void h8300_push_pop (int, int, bool, bool);
107 static int h8300_stack_offset_p (rtx, int);
108 static int h8300_ldm_stm_regno (rtx, int, int, int);
109 static void h8300_reorg (void);
110 static unsigned int h8300_constant_length (rtx);
111 static unsigned int h8300_displacement_length (rtx, int);
112 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
113 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
114 static unsigned int h8300_unary_length (rtx);
115 static unsigned int h8300_short_immediate_length (rtx);
116 static unsigned int h8300_bitfield_length (rtx, rtx);
117 static unsigned int h8300_binary_length (rtx, const h8300_length_table *);
118 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
119 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
120 static bool h8300_hard_regno_scratch_ok (unsigned int);
121 static rtx h8300_get_index (rtx, enum machine_mode mode, int *);
122
123 /* CPU_TYPE, says what cpu we're compiling for. */
124 int cpu_type;
125
126 /* True if a #pragma interrupt has been seen for the current function. */
127 static int pragma_interrupt;
128
129 /* True if a #pragma saveall has been seen for the current function. */
130 static int pragma_saveall;
131
132 static const char *const names_big[] =
133 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
134
135 static const char *const names_extended[] =
136 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
137
138 static const char *const names_upper_extended[] =
139 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
140
141 /* Points to one of the above. */
142 /* ??? The above could be put in an array indexed by CPU_TYPE. */
143 const char * const *h8_reg_names;
144
145 /* Various operations needed by the following, indexed by CPU_TYPE. */
146
147 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
148
149 /* Value of MOVE_RATIO. */
150 int h8300_move_ratio;
151 \f
152 /* See below where shifts are handled for explanation of this enum. */
153
154 enum shift_alg
155 {
156 SHIFT_INLINE,
157 SHIFT_ROT_AND,
158 SHIFT_SPECIAL,
159 SHIFT_LOOP
160 };
161
162 /* Symbols of the various shifts which can be used as indices. */
163
164 enum shift_type
165 {
166 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
167 };
168
169 /* Macros to keep the shift algorithm tables small. */
170 #define INL SHIFT_INLINE
171 #define ROT SHIFT_ROT_AND
172 #define LOP SHIFT_LOOP
173 #define SPC SHIFT_SPECIAL
174
175 /* The shift algorithms for each machine, mode, shift type, and shift
176 count are defined below. The three tables below correspond to
177 QImode, HImode, and SImode, respectively. Each table is organized
178 by, in the order of indices, machine, shift type, and shift count. */
179
180 static enum shift_alg shift_alg_qi[3][3][8] = {
181 {
182 /* TARGET_H8300 */
183 /* 0 1 2 3 4 5 6 7 */
184 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
185 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
186 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
187 },
188 {
189 /* TARGET_H8300H */
190 /* 0 1 2 3 4 5 6 7 */
191 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
192 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
193 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
194 },
195 {
196 /* TARGET_H8300S */
197 /* 0 1 2 3 4 5 6 7 */
198 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
199 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
200 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
201 }
202 };
203
204 static enum shift_alg shift_alg_hi[3][3][16] = {
205 {
206 /* TARGET_H8300 */
207 /* 0 1 2 3 4 5 6 7 */
208 /* 8 9 10 11 12 13 14 15 */
209 { INL, INL, INL, INL, INL, INL, INL, SPC,
210 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
211 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
212 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
213 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
214 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
215 },
216 {
217 /* TARGET_H8300H */
218 /* 0 1 2 3 4 5 6 7 */
219 /* 8 9 10 11 12 13 14 15 */
220 { INL, INL, INL, INL, INL, INL, INL, SPC,
221 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
222 { INL, INL, INL, INL, INL, INL, INL, SPC,
223 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
224 { INL, INL, INL, INL, INL, INL, INL, SPC,
225 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
226 },
227 {
228 /* TARGET_H8300S */
229 /* 0 1 2 3 4 5 6 7 */
230 /* 8 9 10 11 12 13 14 15 */
231 { INL, INL, INL, INL, INL, INL, INL, INL,
232 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
233 { INL, INL, INL, INL, INL, INL, INL, INL,
234 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
237 }
238 };
239
240 static enum shift_alg shift_alg_si[3][3][32] = {
241 {
242 /* TARGET_H8300 */
243 /* 0 1 2 3 4 5 6 7 */
244 /* 8 9 10 11 12 13 14 15 */
245 /* 16 17 18 19 20 21 22 23 */
246 /* 24 25 26 27 28 29 30 31 */
247 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
248 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
249 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
250 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
251 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
252 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
253 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
254 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
255 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
256 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
257 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
258 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
259 },
260 {
261 /* TARGET_H8300H */
262 /* 0 1 2 3 4 5 6 7 */
263 /* 8 9 10 11 12 13 14 15 */
264 /* 16 17 18 19 20 21 22 23 */
265 /* 24 25 26 27 28 29 30 31 */
266 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
267 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
268 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
269 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
270 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
271 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
272 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
273 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
274 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
275 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
276 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
277 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
278 },
279 {
280 /* TARGET_H8300S */
281 /* 0 1 2 3 4 5 6 7 */
282 /* 8 9 10 11 12 13 14 15 */
283 /* 16 17 18 19 20 21 22 23 */
284 /* 24 25 26 27 28 29 30 31 */
285 { INL, INL, INL, INL, INL, INL, INL, INL,
286 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
287 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
288 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
289 { INL, INL, INL, INL, INL, INL, INL, INL,
290 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
291 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
292 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
293 { INL, INL, INL, INL, INL, INL, INL, INL,
294 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
295 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
296 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
297 }
298 };
299
300 #undef INL
301 #undef ROT
302 #undef LOP
303 #undef SPC
304
305 enum h8_cpu
306 {
307 H8_300,
308 H8_300H,
309 H8_S
310 };
311
312 /* Initialize various cpu specific globals at start up. */
313
314 static void
315 h8300_option_override (void)
316 {
317 static const char *const h8_push_ops[2] = { "push" , "push.l" };
318 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
319 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
320
321 if (TARGET_H8300)
322 {
323 cpu_type = (int) CPU_H8300;
324 h8_reg_names = names_big;
325 }
326 else
327 {
328 /* For this we treat the H8/300H and H8S the same. */
329 cpu_type = (int) CPU_H8300H;
330 h8_reg_names = names_extended;
331 }
332 h8_push_op = h8_push_ops[cpu_type];
333 h8_pop_op = h8_pop_ops[cpu_type];
334 h8_mov_op = h8_mov_ops[cpu_type];
335
336 if (!TARGET_H8300S && TARGET_MAC)
337 {
338 error ("-ms2600 is used without -ms");
339 target_flags |= MASK_H8300S_1;
340 }
341
342 if (TARGET_H8300 && TARGET_NORMAL_MODE)
343 {
344 error ("-mn is used without -mh or -ms");
345 target_flags ^= MASK_NORMAL_MODE;
346 }
347
348 /* Some of the shifts are optimized for speed by default.
349 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
350 If optimizing for size, change shift_alg for those shift to
351 SHIFT_LOOP. */
352 if (optimize_size)
353 {
354 /* H8/300 */
355 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
356 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
357 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
358 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
359
360 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
361 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
362
363 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
364 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
365
366 /* H8/300H */
367 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
368 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
369
370 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
371 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
372
373 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
374 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
375 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
376 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
377
378 /* H8S */
379 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
380 }
381
382 /* Work out a value for MOVE_RATIO. */
383 if (!TARGET_H8300SX)
384 {
385 /* Memory-memory moves are quite expensive without the
386 h8sx instructions. */
387 h8300_move_ratio = 3;
388 }
389 else if (flag_omit_frame_pointer)
390 {
391 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
392 sometimes be as short as two individual memory-to-memory moves,
393 but since they use all the call-saved registers, it seems better
394 to allow up to three moves here. */
395 h8300_move_ratio = 4;
396 }
397 else if (optimize_size)
398 {
399 /* In this case we don't use movmd sequences since they tend
400 to be longer than calls to memcpy(). Memory-to-memory
401 moves are cheaper than for !TARGET_H8300SX, so it makes
402 sense to have a slightly higher threshold. */
403 h8300_move_ratio = 4;
404 }
405 else
406 {
407 /* We use movmd sequences for some moves since it can be quicker
408 than calling memcpy(). The sequences will need to save and
409 restore er6 though, so bump up the cost. */
410 h8300_move_ratio = 6;
411 }
412
413 /* This target defaults to strict volatile bitfields. */
414 if (flag_strict_volatile_bitfields < 0)
415 flag_strict_volatile_bitfields = 1;
416 }
417
418 /* Return the byte register name for a register rtx X. B should be 0
419 if you want a lower byte register. B should be 1 if you want an
420 upper byte register. */
421
422 static const char *
423 byte_reg (rtx x, int b)
424 {
425 static const char *const names_small[] = {
426 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
427 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
428 };
429
430 gcc_assert (REG_P (x));
431
432 return names_small[REGNO (x) * 2 + b];
433 }
434
435 /* REGNO must be saved/restored across calls if this macro is true. */
436
437 #define WORD_REG_USED(regno) \
438 (regno < SP_REG \
439 /* No need to save registers if this function will not return. */ \
440 && ! TREE_THIS_VOLATILE (current_function_decl) \
441 && (h8300_saveall_function_p (current_function_decl) \
442 /* Save any call saved register that was used. */ \
443 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
444 /* Save the frame pointer if it was used. */ \
445 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
446 /* Save any register used in an interrupt handler. */ \
447 || (h8300_current_function_interrupt_function_p () \
448 && df_regs_ever_live_p (regno)) \
449 /* Save call clobbered registers in non-leaf interrupt \
450 handlers. */ \
451 || (h8300_current_function_interrupt_function_p () \
452 && call_used_regs[regno] \
453 && !current_function_is_leaf)))
454
455 /* We use this to wrap all emitted insns in the prologue. */
456 static rtx
457 F (rtx x, bool set_it)
458 {
459 if (set_it)
460 RTX_FRAME_RELATED_P (x) = 1;
461 return x;
462 }
463
464 /* Mark all the subexpressions of the PARALLEL rtx PAR as
465 frame-related. Return PAR.
466
467 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
468 PARALLEL rtx other than the first if they do not have the
469 FRAME_RELATED flag set on them. */
470 static rtx
471 Fpa (rtx par)
472 {
473 int len = XVECLEN (par, 0);
474 int i;
475
476 for (i = 0; i < len; i++)
477 F (XVECEXP (par, 0, i), true);
478
479 return par;
480 }
481
482 /* Output assembly language to FILE for the operation OP with operand size
483 SIZE to adjust the stack pointer. */
484
485 static void
486 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
487 {
488 /* If the frame size is 0, we don't have anything to do. */
489 if (size == 0)
490 return;
491
492 /* H8/300 cannot add/subtract a large constant with a single
493 instruction. If a temporary register is available, load the
494 constant to it and then do the addition. */
495 if (TARGET_H8300
496 && size > 4
497 && !h8300_current_function_interrupt_function_p ()
498 && !(cfun->static_chain_decl != NULL && sign < 0))
499 {
500 rtx r3 = gen_rtx_REG (Pmode, 3);
501 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
502 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
503 stack_pointer_rtx, r3)), in_prologue);
504 }
505 else
506 {
507 /* The stack adjustment made here is further optimized by the
508 splitter. In case of H8/300, the splitter always splits the
509 addition emitted here to make the adjustment interrupt-safe.
510 FIXME: We don't always tag those, because we don't know what
511 the splitter will do. */
512 if (Pmode == HImode)
513 {
514 rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx,
515 stack_pointer_rtx, GEN_INT (sign * size)));
516 if (size < 4)
517 F (x, in_prologue);
518 }
519 else
520 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
521 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
522 }
523 }
524
525 /* Round up frame size SIZE. */
526
527 static HOST_WIDE_INT
528 round_frame_size (HOST_WIDE_INT size)
529 {
530 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
531 & -STACK_BOUNDARY / BITS_PER_UNIT);
532 }
533
534 /* Compute which registers to push/pop.
535 Return a bit vector of registers. */
536
537 static unsigned int
538 compute_saved_regs (void)
539 {
540 unsigned int saved_regs = 0;
541 int regno;
542
543 /* Construct a bit vector of registers to be pushed/popped. */
544 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
545 {
546 if (WORD_REG_USED (regno))
547 saved_regs |= 1 << regno;
548 }
549
550 /* Don't push/pop the frame pointer as it is treated separately. */
551 if (frame_pointer_needed)
552 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
553
554 return saved_regs;
555 }
556
557 /* Emit an insn to push register RN. */
558
559 static void
560 push (int rn)
561 {
562 rtx reg = gen_rtx_REG (word_mode, rn);
563 rtx x;
564
565 if (TARGET_H8300)
566 x = gen_push_h8300 (reg);
567 else if (!TARGET_NORMAL_MODE)
568 x = gen_push_h8300hs_advanced (reg);
569 else
570 x = gen_push_h8300hs_normal (reg);
571 x = F (emit_insn (x), true);
572 add_reg_note (x, REG_INC, stack_pointer_rtx);
573 }
574
575 /* Emit an insn to pop register RN. */
576
577 static void
578 pop (int rn)
579 {
580 rtx reg = gen_rtx_REG (word_mode, rn);
581 rtx x;
582
583 if (TARGET_H8300)
584 x = gen_pop_h8300 (reg);
585 else if (!TARGET_NORMAL_MODE)
586 x = gen_pop_h8300hs_advanced (reg);
587 else
588 x = gen_pop_h8300hs_normal (reg);
589 x = emit_insn (x);
590 add_reg_note (x, REG_INC, stack_pointer_rtx);
591 }
592
593 /* Emit an instruction to push or pop NREGS consecutive registers
594 starting at register REGNO. POP_P selects a pop rather than a
595 push and RETURN_P is true if the instruction should return.
596
597 It must be possible to do the requested operation in a single
598 instruction. If NREGS == 1 && !RETURN_P, use a normal push
599 or pop insn. Otherwise emit a parallel of the form:
600
601 (parallel
602 [(return) ;; if RETURN_P
603 (save or restore REGNO)
604 (save or restore REGNO + 1)
605 ...
606 (save or restore REGNO + NREGS - 1)
607 (set sp (plus sp (const_int adjust)))] */
608
609 static void
610 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
611 {
612 int i, j;
613 rtvec vec;
614 rtx sp, offset, x;
615
616 /* See whether we can use a simple push or pop. */
617 if (!return_p && nregs == 1)
618 {
619 if (pop_p)
620 pop (regno);
621 else
622 push (regno);
623 return;
624 }
625
626 /* We need one element for the return insn, if present, one for each
627 register, and one for stack adjustment. */
628 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
629 sp = stack_pointer_rtx;
630 i = 0;
631
632 /* Add the return instruction. */
633 if (return_p)
634 {
635 RTVEC_ELT (vec, i) = ret_rtx;
636 i++;
637 }
638
639 /* Add the register moves. */
640 for (j = 0; j < nregs; j++)
641 {
642 rtx lhs, rhs;
643
644 if (pop_p)
645 {
646 /* Register REGNO + NREGS - 1 is popped first. Before the
647 stack adjustment, its slot is at address @sp. */
648 lhs = gen_rtx_REG (SImode, regno + j);
649 rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4));
650 }
651 else
652 {
653 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
654 lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4));
655 rhs = gen_rtx_REG (SImode, regno + j);
656 }
657 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
658 }
659
660 /* Add the stack adjustment. */
661 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
662 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
663 gen_rtx_PLUS (Pmode, sp, offset));
664
665 x = gen_rtx_PARALLEL (VOIDmode, vec);
666 if (!pop_p)
667 x = Fpa (x);
668
669 if (return_p)
670 emit_jump_insn (x);
671 else
672 emit_insn (x);
673 }
674
675 /* Return true if X has the value sp + OFFSET. */
676
677 static int
678 h8300_stack_offset_p (rtx x, int offset)
679 {
680 if (offset == 0)
681 return x == stack_pointer_rtx;
682
683 return (GET_CODE (x) == PLUS
684 && XEXP (x, 0) == stack_pointer_rtx
685 && GET_CODE (XEXP (x, 1)) == CONST_INT
686 && INTVAL (XEXP (x, 1)) == offset);
687 }
688
689 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
690 something that may be an ldm or stm instruction. If it fits
691 the required template, return the register it loads or stores,
692 otherwise return -1.
693
694 LOAD_P is true if X should be a load, false if it should be a store.
695 NREGS is the number of registers that the whole instruction is expected
696 to load or store. INDEX is the index of the register that X should
697 load or store, relative to the lowest-numbered register. */
698
699 static int
700 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
701 {
702 int regindex, memindex, offset;
703
704 if (load_p)
705 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
706 else
707 memindex = 0, regindex = 1, offset = (index + 1) * -4;
708
709 if (GET_CODE (x) == SET
710 && GET_CODE (XEXP (x, regindex)) == REG
711 && GET_CODE (XEXP (x, memindex)) == MEM
712 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
713 return REGNO (XEXP (x, regindex));
714
715 return -1;
716 }
717
718 /* Return true if the elements of VEC starting at FIRST describe an
719 ldm or stm instruction (LOAD_P says which). */
720
721 int
722 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
723 {
724 rtx last;
725 int nregs, i, regno, adjust;
726
727 /* There must be a stack adjustment, a register move, and at least one
728 other operation (a return or another register move). */
729 if (GET_NUM_ELEM (vec) < 3)
730 return false;
731
732 /* Get the range of registers to be pushed or popped. */
733 nregs = GET_NUM_ELEM (vec) - first - 1;
734 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
735
736 /* Check that the call to h8300_ldm_stm_regno succeeded and
737 that we're only dealing with GPRs. */
738 if (regno < 0 || regno + nregs > 8)
739 return false;
740
741 /* 2-register h8s instructions must start with an even-numbered register.
742 3- and 4-register instructions must start with er0 or er4. */
743 if (!TARGET_H8300SX)
744 {
745 if ((regno & 1) != 0)
746 return false;
747 if (nregs > 2 && (regno & 3) != 0)
748 return false;
749 }
750
751 /* Check the other loads or stores. */
752 for (i = 1; i < nregs; i++)
753 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
754 != regno + i)
755 return false;
756
757 /* Check the stack adjustment. */
758 last = RTVEC_ELT (vec, first + nregs);
759 adjust = (load_p ? nregs : -nregs) * 4;
760 return (GET_CODE (last) == SET
761 && SET_DEST (last) == stack_pointer_rtx
762 && h8300_stack_offset_p (SET_SRC (last), adjust));
763 }
764
765 /* This is what the stack looks like after the prolog of
766 a function with a frame has been set up:
767
768 <args>
769 PC
770 FP <- fp
771 <locals>
772 <saved registers> <- sp
773
774 This is what the stack looks like after the prolog of
775 a function which doesn't have a frame:
776
777 <args>
778 PC
779 <locals>
780 <saved registers> <- sp
781 */
782
783 /* Generate RTL code for the function prologue. */
784
785 void
786 h8300_expand_prologue (void)
787 {
788 int regno;
789 int saved_regs;
790 int n_regs;
791
792 /* If the current function has the OS_Task attribute set, then
793 we have a naked prologue. */
794 if (h8300_os_task_function_p (current_function_decl))
795 return;
796
797 if (h8300_monitor_function_p (current_function_decl))
798 /* My understanding of monitor functions is they act just like
799 interrupt functions, except the prologue must mask
800 interrupts. */
801 emit_insn (gen_monitor_prologue ());
802
803 if (frame_pointer_needed)
804 {
805 /* Push fp. */
806 push (HARD_FRAME_POINTER_REGNUM);
807 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
808 }
809
810 /* Push the rest of the registers in ascending order. */
811 saved_regs = compute_saved_regs ();
812 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
813 {
814 n_regs = 1;
815 if (saved_regs & (1 << regno))
816 {
817 if (TARGET_H8300S)
818 {
819 /* See how many registers we can push at the same time. */
820 if ((!TARGET_H8300SX || (regno & 3) == 0)
821 && ((saved_regs >> regno) & 0x0f) == 0x0f)
822 n_regs = 4;
823
824 else if ((!TARGET_H8300SX || (regno & 3) == 0)
825 && ((saved_regs >> regno) & 0x07) == 0x07)
826 n_regs = 3;
827
828 else if ((!TARGET_H8300SX || (regno & 1) == 0)
829 && ((saved_regs >> regno) & 0x03) == 0x03)
830 n_regs = 2;
831 }
832
833 h8300_push_pop (regno, n_regs, false, false);
834 }
835 }
836
837 /* Leave room for locals. */
838 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
839 }
840
841 /* Return nonzero if we can use "rts" for the function currently being
842 compiled. */
843
844 int
845 h8300_can_use_return_insn_p (void)
846 {
847 return (reload_completed
848 && !frame_pointer_needed
849 && get_frame_size () == 0
850 && compute_saved_regs () == 0);
851 }
852
853 /* Generate RTL code for the function epilogue. */
854
855 void
856 h8300_expand_epilogue (void)
857 {
858 int regno;
859 int saved_regs;
860 int n_regs;
861 HOST_WIDE_INT frame_size;
862 bool returned_p;
863
864 if (h8300_os_task_function_p (current_function_decl))
865 /* OS_Task epilogues are nearly naked -- they just have an
866 rts instruction. */
867 return;
868
869 frame_size = round_frame_size (get_frame_size ());
870 returned_p = false;
871
872 /* Deallocate locals. */
873 h8300_emit_stack_adjustment (1, frame_size, false);
874
875 /* Pop the saved registers in descending order. */
876 saved_regs = compute_saved_regs ();
877 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
878 {
879 n_regs = 1;
880 if (saved_regs & (1 << regno))
881 {
882 if (TARGET_H8300S)
883 {
884 /* See how many registers we can pop at the same time. */
885 if ((TARGET_H8300SX || (regno & 3) == 3)
886 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
887 n_regs = 4;
888
889 else if ((TARGET_H8300SX || (regno & 3) == 2)
890 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
891 n_regs = 3;
892
893 else if ((TARGET_H8300SX || (regno & 1) == 1)
894 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
895 n_regs = 2;
896 }
897
898 /* See if this pop would be the last insn before the return.
899 If so, use rte/l or rts/l instead of pop or ldm.l. */
900 if (TARGET_H8300SX
901 && !frame_pointer_needed
902 && frame_size == 0
903 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
904 returned_p = true;
905
906 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
907 }
908 }
909
910 /* Pop frame pointer if we had one. */
911 if (frame_pointer_needed)
912 {
913 if (TARGET_H8300SX)
914 returned_p = true;
915 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
916 }
917
918 if (!returned_p)
919 emit_jump_insn (ret_rtx);
920 }
921
922 /* Return nonzero if the current function is an interrupt
923 function. */
924
925 int
926 h8300_current_function_interrupt_function_p (void)
927 {
928 return (h8300_interrupt_function_p (current_function_decl)
929 || h8300_monitor_function_p (current_function_decl));
930 }
931
932 /* Output assembly code for the start of the file. */
933
934 static void
935 h8300_file_start (void)
936 {
937 default_file_start ();
938
939 if (TARGET_H8300H)
940 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
941 else if (TARGET_H8300SX)
942 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
943 else if (TARGET_H8300S)
944 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
945 }
946
947 /* Output assembly language code for the end of file. */
948
949 static void
950 h8300_file_end (void)
951 {
952 fputs ("\t.end\n", asm_out_file);
953 }
954 \f
955 /* Split an add of a small constant into two adds/subs insns.
956
957 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
958 instead of adds/subs. */
959
960 void
961 split_adds_subs (enum machine_mode mode, rtx *operands)
962 {
963 HOST_WIDE_INT val = INTVAL (operands[1]);
964 rtx reg = operands[0];
965 HOST_WIDE_INT sign = 1;
966 HOST_WIDE_INT amount;
967 rtx (*gen_add) (rtx, rtx, rtx);
968
969 /* Force VAL to be positive so that we do not have to consider the
970 sign. */
971 if (val < 0)
972 {
973 val = -val;
974 sign = -1;
975 }
976
977 switch (mode)
978 {
979 case HImode:
980 gen_add = gen_addhi3;
981 break;
982
983 case SImode:
984 gen_add = gen_addsi3;
985 break;
986
987 default:
988 gcc_unreachable ();
989 }
990
991 /* Try different amounts in descending order. */
992 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
993 amount > 0;
994 amount /= 2)
995 {
996 for (; val >= amount; val -= amount)
997 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
998 }
999
1000 return;
1001 }
1002
1003 /* Handle machine specific pragmas for compatibility with existing
1004 compilers for the H8/300.
1005
1006 pragma saveall generates prologue/epilogue code which saves and
1007 restores all the registers on function entry.
1008
1009 pragma interrupt saves and restores all registers, and exits with
1010 an rte instruction rather than an rts. A pointer to a function
1011 with this attribute may be safely used in an interrupt vector. */
1012
1013 void
1014 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1015 {
1016 pragma_interrupt = 1;
1017 }
1018
1019 void
1020 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1021 {
1022 pragma_saveall = 1;
1023 }
1024
1025 /* If the next function argument with MODE and TYPE is to be passed in
1026 a register, return a reg RTX for the hard register in which to pass
1027 the argument. CUM represents the state after the last argument.
1028 If the argument is to be pushed, NULL_RTX is returned.
1029
1030 On the H8/300 all normal args are pushed, unless -mquickcall in which
1031 case the first 3 arguments are passed in registers. */
1032
1033 static rtx
1034 h8300_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1035 const_tree type, bool named)
1036 {
1037 static const char *const hand_list[] = {
1038 "__main",
1039 "__cmpsi2",
1040 "__divhi3",
1041 "__modhi3",
1042 "__udivhi3",
1043 "__umodhi3",
1044 "__divsi3",
1045 "__modsi3",
1046 "__udivsi3",
1047 "__umodsi3",
1048 "__mulhi3",
1049 "__mulsi3",
1050 "__reg_memcpy",
1051 "__reg_memset",
1052 "__ucmpsi2",
1053 0,
1054 };
1055
1056 rtx result = NULL_RTX;
1057 const char *fname;
1058 int regpass = 0;
1059
1060 /* Never pass unnamed arguments in registers. */
1061 if (!named)
1062 return NULL_RTX;
1063
1064 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1065 if (TARGET_QUICKCALL)
1066 regpass = 3;
1067
1068 /* If calling hand written assembler, use 4 regs of args. */
1069 if (cum->libcall)
1070 {
1071 const char * const *p;
1072
1073 fname = XSTR (cum->libcall, 0);
1074
1075 /* See if this libcall is one of the hand coded ones. */
1076 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1077 ;
1078
1079 if (*p)
1080 regpass = 4;
1081 }
1082
1083 if (regpass)
1084 {
1085 int size;
1086
1087 if (mode == BLKmode)
1088 size = int_size_in_bytes (type);
1089 else
1090 size = GET_MODE_SIZE (mode);
1091
1092 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1093 && cum->nbytes / UNITS_PER_WORD <= 3)
1094 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1095 }
1096
1097 return result;
1098 }
1099
1100 /* Update the data in CUM to advance over an argument
1101 of mode MODE and data type TYPE.
1102 (TYPE is null for libcalls where that information may not be available.) */
1103
1104 static void
1105 h8300_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1106 const_tree type, bool named ATTRIBUTE_UNUSED)
1107 {
1108 cum->nbytes += (mode != BLKmode
1109 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1110 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1111 }
1112
1113 \f
1114 /* Implements TARGET_REGISTER_MOVE_COST.
1115
1116 Any SI register-to-register move may need to be reloaded,
1117 so inmplement h8300_register_move_cost to return > 2 so that reload never
1118 shortcuts. */
1119
1120 static int
1121 h8300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1122 reg_class_t from, reg_class_t to)
1123 {
1124 if (from == MAC_REGS || to == MAC_REG)
1125 return 6;
1126 else
1127 return 3;
1128 }
1129
1130 /* Compute the cost of an and insn. */
1131
1132 static int
1133 h8300_and_costs (rtx x)
1134 {
1135 rtx operands[4];
1136
1137 if (GET_MODE (x) == QImode)
1138 return 1;
1139
1140 if (GET_MODE (x) != HImode
1141 && GET_MODE (x) != SImode)
1142 return 100;
1143
1144 operands[0] = NULL;
1145 operands[1] = XEXP (x, 0);
1146 operands[2] = XEXP (x, 1);
1147 operands[3] = x;
1148 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1149 }
1150
1151 /* Compute the cost of a shift insn. */
1152
1153 static int
1154 h8300_shift_costs (rtx x)
1155 {
1156 rtx operands[4];
1157
1158 if (GET_MODE (x) != QImode
1159 && GET_MODE (x) != HImode
1160 && GET_MODE (x) != SImode)
1161 return 100;
1162
1163 operands[0] = NULL;
1164 operands[1] = NULL;
1165 operands[2] = XEXP (x, 1);
1166 operands[3] = x;
1167 return compute_a_shift_length (NULL, operands) / 2;
1168 }
1169
1170 /* Worker function for TARGET_RTX_COSTS. */
1171
1172 static bool
1173 h8300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
1174 {
1175 if (TARGET_H8300SX && outer_code == MEM)
1176 {
1177 /* Estimate the number of execution states needed to calculate
1178 the address. */
1179 if (register_operand (x, VOIDmode)
1180 || GET_CODE (x) == POST_INC
1181 || GET_CODE (x) == POST_DEC
1182 || CONSTANT_P (x))
1183 *total = 0;
1184 else
1185 *total = COSTS_N_INSNS (1);
1186 return true;
1187 }
1188
1189 switch (code)
1190 {
1191 case CONST_INT:
1192 {
1193 HOST_WIDE_INT n = INTVAL (x);
1194
1195 if (TARGET_H8300SX)
1196 {
1197 /* Constant operands need the same number of processor
1198 states as register operands. Although we could try to
1199 use a size-based cost for !speed, the lack of
1200 of a mode makes the results very unpredictable. */
1201 *total = 0;
1202 return true;
1203 }
1204 if (-4 <= n || n <= 4)
1205 {
1206 switch ((int) n)
1207 {
1208 case 0:
1209 *total = 0;
1210 return true;
1211 case 1:
1212 case 2:
1213 case -1:
1214 case -2:
1215 *total = 0 + (outer_code == SET);
1216 return true;
1217 case 4:
1218 case -4:
1219 if (TARGET_H8300H || TARGET_H8300S)
1220 *total = 0 + (outer_code == SET);
1221 else
1222 *total = 1;
1223 return true;
1224 }
1225 }
1226 *total = 1;
1227 return true;
1228 }
1229
1230 case CONST:
1231 case LABEL_REF:
1232 case SYMBOL_REF:
1233 if (TARGET_H8300SX)
1234 {
1235 /* See comment for CONST_INT. */
1236 *total = 0;
1237 return true;
1238 }
1239 *total = 3;
1240 return true;
1241
1242 case CONST_DOUBLE:
1243 *total = 20;
1244 return true;
1245
1246 case COMPARE:
1247 if (XEXP (x, 1) == const0_rtx)
1248 *total = 0;
1249 return false;
1250
1251 case AND:
1252 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1253 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1254 return false;
1255 *total = COSTS_N_INSNS (h8300_and_costs (x));
1256 return true;
1257
1258 /* We say that MOD and DIV are so expensive because otherwise we'll
1259 generate some really horrible code for division of a power of two. */
1260 case MOD:
1261 case DIV:
1262 case UMOD:
1263 case UDIV:
1264 if (TARGET_H8300SX)
1265 switch (GET_MODE (x))
1266 {
1267 case QImode:
1268 case HImode:
1269 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1270 return false;
1271
1272 case SImode:
1273 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1274 return false;
1275
1276 default:
1277 break;
1278 }
1279 *total = COSTS_N_INSNS (12);
1280 return true;
1281
1282 case MULT:
1283 if (TARGET_H8300SX)
1284 switch (GET_MODE (x))
1285 {
1286 case QImode:
1287 case HImode:
1288 *total = COSTS_N_INSNS (2);
1289 return false;
1290
1291 case SImode:
1292 *total = COSTS_N_INSNS (5);
1293 return false;
1294
1295 default:
1296 break;
1297 }
1298 *total = COSTS_N_INSNS (4);
1299 return true;
1300
1301 case ASHIFT:
1302 case ASHIFTRT:
1303 case LSHIFTRT:
1304 if (h8sx_binary_shift_operator (x, VOIDmode))
1305 {
1306 *total = COSTS_N_INSNS (2);
1307 return false;
1308 }
1309 else if (h8sx_unary_shift_operator (x, VOIDmode))
1310 {
1311 *total = COSTS_N_INSNS (1);
1312 return false;
1313 }
1314 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1315 return true;
1316
1317 case ROTATE:
1318 case ROTATERT:
1319 if (GET_MODE (x) == HImode)
1320 *total = 2;
1321 else
1322 *total = 8;
1323 return true;
1324
1325 default:
1326 *total = COSTS_N_INSNS (1);
1327 return false;
1328 }
1329 }
1330 \f
1331 /* Documentation for the machine specific operand escapes:
1332
1333 'E' like s but negative.
1334 'F' like t but negative.
1335 'G' constant just the negative
1336 'R' print operand as a byte:8 address if appropriate, else fall back to
1337 'X' handling.
1338 'S' print operand as a long word
1339 'T' print operand as a word
1340 'V' find the set bit, and print its number.
1341 'W' find the clear bit, and print its number.
1342 'X' print operand as a byte
1343 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1344 If this operand isn't a register, fall back to 'R' handling.
1345 'Z' print int & 7.
1346 'c' print the opcode corresponding to rtl
1347 'e' first word of 32-bit value - if reg, then least reg. if mem
1348 then least. if const then most sig word
1349 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1350 then +2. if const then least sig word
1351 'j' print operand as condition code.
1352 'k' print operand as reverse condition code.
1353 'm' convert an integer operand to a size suffix (.b, .w or .l)
1354 'o' print an integer without a leading '#'
1355 's' print as low byte of 16-bit value
1356 't' print as high byte of 16-bit value
1357 'w' print as low byte of 32-bit value
1358 'x' print as 2nd byte of 32-bit value
1359 'y' print as 3rd byte of 32-bit value
1360 'z' print as msb of 32-bit value
1361 */
1362
1363 /* Return assembly language string which identifies a comparison type. */
1364
1365 static const char *
1366 cond_string (enum rtx_code code)
1367 {
1368 switch (code)
1369 {
1370 case NE:
1371 return "ne";
1372 case EQ:
1373 return "eq";
1374 case GE:
1375 return "ge";
1376 case GT:
1377 return "gt";
1378 case LE:
1379 return "le";
1380 case LT:
1381 return "lt";
1382 case GEU:
1383 return "hs";
1384 case GTU:
1385 return "hi";
1386 case LEU:
1387 return "ls";
1388 case LTU:
1389 return "lo";
1390 default:
1391 gcc_unreachable ();
1392 }
1393 }
1394
1395 /* Print operand X using operand code CODE to assembly language output file
1396 FILE. */
1397
1398 static void
1399 h8300_print_operand (FILE *file, rtx x, int code)
1400 {
1401 /* This is used for communication between codes V,W,Z and Y. */
1402 static int bitint;
1403
1404 switch (code)
1405 {
1406 case 'E':
1407 switch (GET_CODE (x))
1408 {
1409 case REG:
1410 fprintf (file, "%sl", names_big[REGNO (x)]);
1411 break;
1412 case CONST_INT:
1413 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1414 break;
1415 default:
1416 gcc_unreachable ();
1417 }
1418 break;
1419 case 'F':
1420 switch (GET_CODE (x))
1421 {
1422 case REG:
1423 fprintf (file, "%sh", names_big[REGNO (x)]);
1424 break;
1425 case CONST_INT:
1426 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1427 break;
1428 default:
1429 gcc_unreachable ();
1430 }
1431 break;
1432 case 'G':
1433 gcc_assert (GET_CODE (x) == CONST_INT);
1434 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1435 break;
1436 case 'S':
1437 if (GET_CODE (x) == REG)
1438 fprintf (file, "%s", names_extended[REGNO (x)]);
1439 else
1440 goto def;
1441 break;
1442 case 'T':
1443 if (GET_CODE (x) == REG)
1444 fprintf (file, "%s", names_big[REGNO (x)]);
1445 else
1446 goto def;
1447 break;
1448 case 'V':
1449 bitint = (INTVAL (x) & 0xffff);
1450 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1451 bitint = exact_log2 (bitint & 0xff);
1452 else
1453 bitint = exact_log2 ((bitint >> 8) & 0xff);
1454 gcc_assert (bitint >= 0);
1455 fprintf (file, "#%d", bitint);
1456 break;
1457 case 'W':
1458 bitint = ((~INTVAL (x)) & 0xffff);
1459 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1460 bitint = exact_log2 (bitint & 0xff);
1461 else
1462 bitint = (exact_log2 ((bitint >> 8) & 0xff));
1463 gcc_assert (bitint >= 0);
1464 fprintf (file, "#%d", bitint);
1465 break;
1466 case 'R':
1467 case 'X':
1468 if (GET_CODE (x) == REG)
1469 fprintf (file, "%s", byte_reg (x, 0));
1470 else
1471 goto def;
1472 break;
1473 case 'Y':
1474 gcc_assert (bitint >= 0);
1475 if (GET_CODE (x) == REG)
1476 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1477 else
1478 h8300_print_operand (file, x, 'R');
1479 bitint = -1;
1480 break;
1481 case 'Z':
1482 bitint = INTVAL (x);
1483 fprintf (file, "#%d", bitint & 7);
1484 break;
1485 case 'c':
1486 switch (GET_CODE (x))
1487 {
1488 case IOR:
1489 fprintf (file, "or");
1490 break;
1491 case XOR:
1492 fprintf (file, "xor");
1493 break;
1494 case AND:
1495 fprintf (file, "and");
1496 break;
1497 default:
1498 break;
1499 }
1500 break;
1501 case 'e':
1502 switch (GET_CODE (x))
1503 {
1504 case REG:
1505 if (TARGET_H8300)
1506 fprintf (file, "%s", names_big[REGNO (x)]);
1507 else
1508 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1509 break;
1510 case MEM:
1511 h8300_print_operand (file, x, 0);
1512 break;
1513 case CONST_INT:
1514 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1515 break;
1516 case CONST_DOUBLE:
1517 {
1518 long val;
1519 REAL_VALUE_TYPE rv;
1520 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1521 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1522 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1523 break;
1524 }
1525 default:
1526 gcc_unreachable ();
1527 break;
1528 }
1529 break;
1530 case 'f':
1531 switch (GET_CODE (x))
1532 {
1533 case REG:
1534 if (TARGET_H8300)
1535 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1536 else
1537 fprintf (file, "%s", names_big[REGNO (x)]);
1538 break;
1539 case MEM:
1540 x = adjust_address (x, HImode, 2);
1541 h8300_print_operand (file, x, 0);
1542 break;
1543 case CONST_INT:
1544 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1545 break;
1546 case CONST_DOUBLE:
1547 {
1548 long val;
1549 REAL_VALUE_TYPE rv;
1550 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1551 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1552 fprintf (file, "#%ld", (val & 0xffff));
1553 break;
1554 }
1555 default:
1556 gcc_unreachable ();
1557 }
1558 break;
1559 case 'j':
1560 fputs (cond_string (GET_CODE (x)), file);
1561 break;
1562 case 'k':
1563 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1564 break;
1565 case 'm':
1566 gcc_assert (GET_CODE (x) == CONST_INT);
1567 switch (INTVAL (x))
1568 {
1569 case 1:
1570 fputs (".b", file);
1571 break;
1572
1573 case 2:
1574 fputs (".w", file);
1575 break;
1576
1577 case 4:
1578 fputs (".l", file);
1579 break;
1580
1581 default:
1582 gcc_unreachable ();
1583 }
1584 break;
1585 case 'o':
1586 h8300_print_operand_address (file, x);
1587 break;
1588 case 's':
1589 if (GET_CODE (x) == CONST_INT)
1590 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1591 else
1592 fprintf (file, "%s", byte_reg (x, 0));
1593 break;
1594 case 't':
1595 if (GET_CODE (x) == CONST_INT)
1596 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1597 else
1598 fprintf (file, "%s", byte_reg (x, 1));
1599 break;
1600 case 'w':
1601 if (GET_CODE (x) == CONST_INT)
1602 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1603 else
1604 fprintf (file, "%s",
1605 byte_reg (x, TARGET_H8300 ? 2 : 0));
1606 break;
1607 case 'x':
1608 if (GET_CODE (x) == CONST_INT)
1609 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1610 else
1611 fprintf (file, "%s",
1612 byte_reg (x, TARGET_H8300 ? 3 : 1));
1613 break;
1614 case 'y':
1615 if (GET_CODE (x) == CONST_INT)
1616 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1617 else
1618 fprintf (file, "%s", byte_reg (x, 0));
1619 break;
1620 case 'z':
1621 if (GET_CODE (x) == CONST_INT)
1622 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1623 else
1624 fprintf (file, "%s", byte_reg (x, 1));
1625 break;
1626
1627 default:
1628 def:
1629 switch (GET_CODE (x))
1630 {
1631 case REG:
1632 switch (GET_MODE (x))
1633 {
1634 case QImode:
1635 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1636 fprintf (file, "%s", byte_reg (x, 0));
1637 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1638 fprintf (file, "%s", names_big[REGNO (x)]);
1639 #endif
1640 break;
1641 case HImode:
1642 fprintf (file, "%s", names_big[REGNO (x)]);
1643 break;
1644 case SImode:
1645 case SFmode:
1646 fprintf (file, "%s", names_extended[REGNO (x)]);
1647 break;
1648 default:
1649 gcc_unreachable ();
1650 }
1651 break;
1652
1653 case MEM:
1654 {
1655 rtx addr = XEXP (x, 0);
1656
1657 fprintf (file, "@");
1658 output_address (addr);
1659
1660 /* Add a length suffix to constant addresses. Although this
1661 is often unnecessary, it helps to avoid ambiguity in the
1662 syntax of mova. If we wrote an insn like:
1663
1664 mova/w.l @(1,@foo.b),er0
1665
1666 then .b would be considered part of the symbol name.
1667 Adding a length after foo will avoid this. */
1668 if (CONSTANT_P (addr))
1669 switch (code)
1670 {
1671 case 'R':
1672 /* Used for mov.b and bit operations. */
1673 if (h8300_eightbit_constant_address_p (addr))
1674 {
1675 fprintf (file, ":8");
1676 break;
1677 }
1678
1679 /* Fall through. We should not get here if we are
1680 processing bit operations on H8/300 or H8/300H
1681 because 'U' constraint does not allow bit
1682 operations on the tiny area on these machines. */
1683
1684 case 'X':
1685 case 'T':
1686 case 'S':
1687 if (h8300_constant_length (addr) == 2)
1688 fprintf (file, ":16");
1689 else
1690 fprintf (file, ":32");
1691 break;
1692 default:
1693 break;
1694 }
1695 }
1696 break;
1697
1698 case CONST_INT:
1699 case SYMBOL_REF:
1700 case CONST:
1701 case LABEL_REF:
1702 fprintf (file, "#");
1703 h8300_print_operand_address (file, x);
1704 break;
1705 case CONST_DOUBLE:
1706 {
1707 long val;
1708 REAL_VALUE_TYPE rv;
1709 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1710 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1711 fprintf (file, "#%ld", val);
1712 break;
1713 }
1714 default:
1715 break;
1716 }
1717 }
1718 }
1719
1720 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1721
1722 static bool
1723 h8300_print_operand_punct_valid_p (unsigned char code)
1724 {
1725 return (code == '#');
1726 }
1727
1728 /* Output assembly language output for the address ADDR to FILE. */
1729
1730 static void
1731 h8300_print_operand_address (FILE *file, rtx addr)
1732 {
1733 rtx index;
1734 int size;
1735
1736 switch (GET_CODE (addr))
1737 {
1738 case REG:
1739 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1740 break;
1741
1742 case PRE_DEC:
1743 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1744 break;
1745
1746 case POST_INC:
1747 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1748 break;
1749
1750 case PRE_INC:
1751 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1752 break;
1753
1754 case POST_DEC:
1755 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1756 break;
1757
1758 case PLUS:
1759 fprintf (file, "(");
1760
1761 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1762 if (GET_CODE (index) == REG)
1763 {
1764 /* reg,foo */
1765 h8300_print_operand_address (file, XEXP (addr, 1));
1766 fprintf (file, ",");
1767 switch (size)
1768 {
1769 case 0:
1770 h8300_print_operand_address (file, index);
1771 break;
1772
1773 case 1:
1774 h8300_print_operand (file, index, 'X');
1775 fputs (".b", file);
1776 break;
1777
1778 case 2:
1779 h8300_print_operand (file, index, 'T');
1780 fputs (".w", file);
1781 break;
1782
1783 case 4:
1784 h8300_print_operand (file, index, 'S');
1785 fputs (".l", file);
1786 break;
1787 }
1788 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1789 }
1790 else
1791 {
1792 /* foo+k */
1793 h8300_print_operand_address (file, XEXP (addr, 0));
1794 fprintf (file, "+");
1795 h8300_print_operand_address (file, XEXP (addr, 1));
1796 }
1797 fprintf (file, ")");
1798 break;
1799
1800 case CONST_INT:
1801 {
1802 /* Since the H8/300 only has 16-bit pointers, negative values are also
1803 those >= 32768. This happens for example with pointer minus a
1804 constant. We don't want to turn (char *p - 2) into
1805 (char *p + 65534) because loop unrolling can build upon this
1806 (IE: char *p + 131068). */
1807 int n = INTVAL (addr);
1808 if (TARGET_H8300)
1809 n = (int) (short) n;
1810 fprintf (file, "%d", n);
1811 break;
1812 }
1813
1814 default:
1815 output_addr_const (file, addr);
1816 break;
1817 }
1818 }
1819 \f
1820 /* Output all insn addresses and their sizes into the assembly language
1821 output file. This is helpful for debugging whether the length attributes
1822 in the md file are correct. This is not meant to be a user selectable
1823 option. */
1824
1825 void
1826 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1827 int num_operands ATTRIBUTE_UNUSED)
1828 {
1829 /* This holds the last insn address. */
1830 static int last_insn_address = 0;
1831
1832 const int uid = INSN_UID (insn);
1833
1834 if (TARGET_ADDRESSES)
1835 {
1836 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1837 INSN_ADDRESSES (uid) - last_insn_address);
1838 last_insn_address = INSN_ADDRESSES (uid);
1839 }
1840 }
1841
1842 /* Prepare for an SI sized move. */
1843
1844 int
1845 h8300_expand_movsi (rtx operands[])
1846 {
1847 rtx src = operands[1];
1848 rtx dst = operands[0];
1849 if (!reload_in_progress && !reload_completed)
1850 {
1851 if (!register_operand (dst, GET_MODE (dst)))
1852 {
1853 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1854 emit_move_insn (tmp, src);
1855 operands[1] = tmp;
1856 }
1857 }
1858 return 0;
1859 }
1860
1861 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1862 Frame pointer elimination is automatically handled.
1863
1864 For the h8300, if frame pointer elimination is being done, we would like to
1865 convert ap and rp into sp, not fp.
1866
1867 All other eliminations are valid. */
1868
1869 static bool
1870 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1871 {
1872 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1873 }
1874
1875 /* Conditionally modify register usage based on target flags. */
1876
1877 static void
1878 h8300_conditional_register_usage (void)
1879 {
1880 if (!TARGET_MAC)
1881 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1882 }
1883
1884 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1885 Define the offset between two registers, one to be eliminated, and
1886 the other its replacement, at the start of a routine. */
1887
1888 int
1889 h8300_initial_elimination_offset (int from, int to)
1890 {
1891 /* The number of bytes that the return address takes on the stack. */
1892 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1893
1894 /* The number of bytes that the saved frame pointer takes on the stack. */
1895 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1896
1897 /* The number of bytes that the saved registers, excluding the frame
1898 pointer, take on the stack. */
1899 int saved_regs_size = 0;
1900
1901 /* The number of bytes that the locals takes on the stack. */
1902 int frame_size = round_frame_size (get_frame_size ());
1903
1904 int regno;
1905
1906 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1907 if (WORD_REG_USED (regno))
1908 saved_regs_size += UNITS_PER_WORD;
1909
1910 /* Adjust saved_regs_size because the above loop took the frame
1911 pointer int account. */
1912 saved_regs_size -= fp_size;
1913
1914 switch (to)
1915 {
1916 case HARD_FRAME_POINTER_REGNUM:
1917 switch (from)
1918 {
1919 case ARG_POINTER_REGNUM:
1920 return pc_size + fp_size;
1921 case RETURN_ADDRESS_POINTER_REGNUM:
1922 return fp_size;
1923 case FRAME_POINTER_REGNUM:
1924 return -saved_regs_size;
1925 default:
1926 gcc_unreachable ();
1927 }
1928 break;
1929 case STACK_POINTER_REGNUM:
1930 switch (from)
1931 {
1932 case ARG_POINTER_REGNUM:
1933 return pc_size + saved_regs_size + frame_size;
1934 case RETURN_ADDRESS_POINTER_REGNUM:
1935 return saved_regs_size + frame_size;
1936 case FRAME_POINTER_REGNUM:
1937 return frame_size;
1938 default:
1939 gcc_unreachable ();
1940 }
1941 break;
1942 default:
1943 gcc_unreachable ();
1944 }
1945 gcc_unreachable ();
1946 }
1947
1948 /* Worker function for RETURN_ADDR_RTX. */
1949
1950 rtx
1951 h8300_return_addr_rtx (int count, rtx frame)
1952 {
1953 rtx ret;
1954
1955 if (count == 0)
1956 ret = gen_rtx_MEM (Pmode,
1957 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1958 else if (flag_omit_frame_pointer)
1959 return (rtx) 0;
1960 else
1961 ret = gen_rtx_MEM (Pmode,
1962 memory_address (Pmode,
1963 plus_constant (frame, UNITS_PER_WORD)));
1964 set_mem_alias_set (ret, get_frame_alias_set ());
1965 return ret;
1966 }
1967
1968 /* Update the condition code from the insn. */
1969
1970 void
1971 notice_update_cc (rtx body, rtx insn)
1972 {
1973 rtx set;
1974
1975 switch (get_attr_cc (insn))
1976 {
1977 case CC_NONE:
1978 /* Insn does not affect CC at all. */
1979 break;
1980
1981 case CC_NONE_0HIT:
1982 /* Insn does not change CC, but the 0'th operand has been changed. */
1983 if (cc_status.value1 != 0
1984 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1985 cc_status.value1 = 0;
1986 if (cc_status.value2 != 0
1987 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1988 cc_status.value2 = 0;
1989 break;
1990
1991 case CC_SET_ZN:
1992 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1993 The V flag is unusable. The C flag may or may not be known but
1994 that's ok because alter_cond will change tests to use EQ/NE. */
1995 CC_STATUS_INIT;
1996 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1997 set = single_set (insn);
1998 cc_status.value1 = SET_SRC (set);
1999 if (SET_DEST (set) != cc0_rtx)
2000 cc_status.value2 = SET_DEST (set);
2001 break;
2002
2003 case CC_SET_ZNV:
2004 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2005 The C flag may or may not be known but that's ok because
2006 alter_cond will change tests to use EQ/NE. */
2007 CC_STATUS_INIT;
2008 cc_status.flags |= CC_NO_CARRY;
2009 set = single_set (insn);
2010 cc_status.value1 = SET_SRC (set);
2011 if (SET_DEST (set) != cc0_rtx)
2012 {
2013 /* If the destination is STRICT_LOW_PART, strip off
2014 STRICT_LOW_PART. */
2015 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2016 cc_status.value2 = XEXP (SET_DEST (set), 0);
2017 else
2018 cc_status.value2 = SET_DEST (set);
2019 }
2020 break;
2021
2022 case CC_COMPARE:
2023 /* The insn is a compare instruction. */
2024 CC_STATUS_INIT;
2025 cc_status.value1 = SET_SRC (body);
2026 break;
2027
2028 case CC_CLOBBER:
2029 /* Insn doesn't leave CC in a usable state. */
2030 CC_STATUS_INIT;
2031 break;
2032 }
2033 }
2034 \f
2035 /* Given that X occurs in an address of the form (plus X constant),
2036 return the part of X that is expected to be a register. There are
2037 four kinds of addressing mode to recognize:
2038
2039 @(dd,Rn)
2040 @(dd,RnL.b)
2041 @(dd,Rn.w)
2042 @(dd,ERn.l)
2043
2044 If SIZE is nonnull, and the address is one of the last three forms,
2045 set *SIZE to the index multiplication factor. Set it to 0 for
2046 plain @(dd,Rn) addresses.
2047
2048 MODE is the mode of the value being accessed. It can be VOIDmode
2049 if the address is known to be valid, but its mode is unknown. */
2050
2051 static rtx
2052 h8300_get_index (rtx x, enum machine_mode mode, int *size)
2053 {
2054 int dummy, factor;
2055
2056 if (size == 0)
2057 size = &dummy;
2058
2059 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2060 if (TARGET_H8300SX
2061 && factor <= 4
2062 && (mode == VOIDmode
2063 || GET_MODE_CLASS (mode) == MODE_INT
2064 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2065 {
2066 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2067 {
2068 /* When accessing byte-sized values, the index can be
2069 a zero-extended QImode or HImode register. */
2070 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2071 return XEXP (x, 0);
2072 }
2073 else
2074 {
2075 /* We're looking for addresses of the form:
2076
2077 (mult X I)
2078 or (mult (zero_extend X) I)
2079
2080 where I is the size of the operand being accessed.
2081 The canonical form of the second expression is:
2082
2083 (and (mult (subreg X) I) J)
2084
2085 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2086 rtx index;
2087
2088 if (GET_CODE (x) == AND
2089 && GET_CODE (XEXP (x, 1)) == CONST_INT
2090 && (factor == 0
2091 || INTVAL (XEXP (x, 1)) == 0xff * factor
2092 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2093 {
2094 index = XEXP (x, 0);
2095 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2096 }
2097 else
2098 {
2099 index = x;
2100 *size = 4;
2101 }
2102
2103 if (GET_CODE (index) == MULT
2104 && GET_CODE (XEXP (index, 1)) == CONST_INT
2105 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2106 return XEXP (index, 0);
2107 }
2108 }
2109 *size = 0;
2110 return x;
2111 }
2112 \f
2113 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2114
2115 On the H8/300, the predecrement and postincrement address depend thus
2116 (the amount of decrement or increment being the length of the operand). */
2117
2118 static bool
2119 h8300_mode_dependent_address_p (const_rtx addr)
2120 {
2121 if (GET_CODE (addr) == PLUS
2122 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2123 return true;
2124
2125 return false;
2126 }
2127 \f
2128 static const h8300_length_table addb_length_table =
2129 {
2130 /* #xx Rs @aa @Rs @xx */
2131 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2132 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2133 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2134 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2135 };
2136
2137 static const h8300_length_table addw_length_table =
2138 {
2139 /* #xx Rs @aa @Rs @xx */
2140 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2141 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2142 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2143 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2144 };
2145
2146 static const h8300_length_table addl_length_table =
2147 {
2148 /* #xx Rs @aa @Rs @xx */
2149 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2150 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2151 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2152 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2153 };
2154
2155 #define logicb_length_table addb_length_table
2156 #define logicw_length_table addw_length_table
2157
2158 static const h8300_length_table logicl_length_table =
2159 {
2160 /* #xx Rs @aa @Rs @xx */
2161 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2162 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2163 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2164 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2165 };
2166
2167 static const h8300_length_table movb_length_table =
2168 {
2169 /* #xx Rs @aa @Rs @xx */
2170 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2171 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2172 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2173 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2174 };
2175
2176 #define movw_length_table movb_length_table
2177
2178 static const h8300_length_table movl_length_table =
2179 {
2180 /* #xx Rs @aa @Rs @xx */
2181 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2182 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2183 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2184 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2185 };
2186
2187 /* Return the size of the given address or displacement constant. */
2188
2189 static unsigned int
2190 h8300_constant_length (rtx constant)
2191 {
2192 /* Check for (@d:16,Reg). */
2193 if (GET_CODE (constant) == CONST_INT
2194 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2195 return 2;
2196
2197 /* Check for (@d:16,Reg) in cases where the displacement is
2198 an absolute address. */
2199 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2200 return 2;
2201
2202 return 4;
2203 }
2204
2205 /* Return the size of a displacement field in address ADDR, which should
2206 have the form (plus X constant). SIZE is the number of bytes being
2207 accessed. */
2208
2209 static unsigned int
2210 h8300_displacement_length (rtx addr, int size)
2211 {
2212 rtx offset;
2213
2214 offset = XEXP (addr, 1);
2215
2216 /* Check for @(d:2,Reg). */
2217 if (register_operand (XEXP (addr, 0), VOIDmode)
2218 && GET_CODE (offset) == CONST_INT
2219 && (INTVAL (offset) == size
2220 || INTVAL (offset) == size * 2
2221 || INTVAL (offset) == size * 3))
2222 return 0;
2223
2224 return h8300_constant_length (offset);
2225 }
2226
2227 /* Store the class of operand OP in *OPCLASS and return the length of any
2228 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2229 can be null if only the length is needed. */
2230
2231 static unsigned int
2232 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2233 {
2234 enum h8300_operand_class dummy;
2235
2236 if (opclass == 0)
2237 opclass = &dummy;
2238
2239 if (CONSTANT_P (op))
2240 {
2241 *opclass = H8OP_IMMEDIATE;
2242
2243 /* Byte-sized immediates are stored in the opcode fields. */
2244 if (size == 1)
2245 return 0;
2246
2247 /* If this is a 32-bit instruction, see whether the constant
2248 will fit into a 16-bit immediate field. */
2249 if (TARGET_H8300SX
2250 && size == 4
2251 && GET_CODE (op) == CONST_INT
2252 && IN_RANGE (INTVAL (op), 0, 0xffff))
2253 return 2;
2254
2255 return size;
2256 }
2257 else if (GET_CODE (op) == MEM)
2258 {
2259 op = XEXP (op, 0);
2260 if (CONSTANT_P (op))
2261 {
2262 *opclass = H8OP_MEM_ABSOLUTE;
2263 return h8300_constant_length (op);
2264 }
2265 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2266 {
2267 *opclass = H8OP_MEM_COMPLEX;
2268 return h8300_displacement_length (op, size);
2269 }
2270 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2271 {
2272 *opclass = H8OP_MEM_COMPLEX;
2273 return 0;
2274 }
2275 else if (register_operand (op, VOIDmode))
2276 {
2277 *opclass = H8OP_MEM_BASE;
2278 return 0;
2279 }
2280 }
2281 gcc_assert (register_operand (op, VOIDmode));
2282 *opclass = H8OP_REGISTER;
2283 return 0;
2284 }
2285
2286 /* Return the length of the instruction described by TABLE given that
2287 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2288 and OP2 must be an h8300_src_operand. */
2289
2290 static unsigned int
2291 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2292 {
2293 enum h8300_operand_class op1_class, op2_class;
2294 unsigned int size, immediate_length;
2295
2296 size = GET_MODE_SIZE (GET_MODE (op1));
2297 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2298 + h8300_classify_operand (op2, size, &op2_class));
2299 return immediate_length + (*table)[op1_class - 1][op2_class];
2300 }
2301
2302 /* Return the length of a unary instruction such as neg or not given that
2303 its operand is OP. */
2304
2305 unsigned int
2306 h8300_unary_length (rtx op)
2307 {
2308 enum h8300_operand_class opclass;
2309 unsigned int size, operand_length;
2310
2311 size = GET_MODE_SIZE (GET_MODE (op));
2312 operand_length = h8300_classify_operand (op, size, &opclass);
2313 switch (opclass)
2314 {
2315 case H8OP_REGISTER:
2316 return 2;
2317
2318 case H8OP_MEM_BASE:
2319 return (size == 4 ? 6 : 4);
2320
2321 case H8OP_MEM_ABSOLUTE:
2322 return operand_length + (size == 4 ? 6 : 4);
2323
2324 case H8OP_MEM_COMPLEX:
2325 return operand_length + 6;
2326
2327 default:
2328 gcc_unreachable ();
2329 }
2330 }
2331
2332 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2333
2334 static unsigned int
2335 h8300_short_immediate_length (rtx op)
2336 {
2337 enum h8300_operand_class opclass;
2338 unsigned int size, operand_length;
2339
2340 size = GET_MODE_SIZE (GET_MODE (op));
2341 operand_length = h8300_classify_operand (op, size, &opclass);
2342
2343 switch (opclass)
2344 {
2345 case H8OP_REGISTER:
2346 return 2;
2347
2348 case H8OP_MEM_BASE:
2349 case H8OP_MEM_ABSOLUTE:
2350 case H8OP_MEM_COMPLEX:
2351 return 4 + operand_length;
2352
2353 default:
2354 gcc_unreachable ();
2355 }
2356 }
2357
2358 /* Likewise bitfield load and store instructions. */
2359
2360 static unsigned int
2361 h8300_bitfield_length (rtx op, rtx op2)
2362 {
2363 enum h8300_operand_class opclass;
2364 unsigned int size, operand_length;
2365
2366 if (GET_CODE (op) == REG)
2367 op = op2;
2368 gcc_assert (GET_CODE (op) != REG);
2369
2370 size = GET_MODE_SIZE (GET_MODE (op));
2371 operand_length = h8300_classify_operand (op, size, &opclass);
2372
2373 switch (opclass)
2374 {
2375 case H8OP_MEM_BASE:
2376 case H8OP_MEM_ABSOLUTE:
2377 case H8OP_MEM_COMPLEX:
2378 return 4 + operand_length;
2379
2380 default:
2381 gcc_unreachable ();
2382 }
2383 }
2384
2385 /* Calculate the length of general binary instruction INSN using TABLE. */
2386
2387 static unsigned int
2388 h8300_binary_length (rtx insn, const h8300_length_table *table)
2389 {
2390 rtx set;
2391
2392 set = single_set (insn);
2393 gcc_assert (set);
2394
2395 if (BINARY_P (SET_SRC (set)))
2396 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2397 XEXP (SET_SRC (set), 1), table);
2398 else
2399 {
2400 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2401 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2402 XEXP (XEXP (SET_SRC (set), 1), 1),
2403 table);
2404 }
2405 }
2406
2407 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2408 memory reference and either (1) it has the form @(d:16,Rn) or
2409 (2) its address has the code given by INC_CODE. */
2410
2411 static bool
2412 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2413 {
2414 rtx addr;
2415 unsigned int size;
2416
2417 if (GET_CODE (op) != MEM)
2418 return false;
2419
2420 addr = XEXP (op, 0);
2421 size = GET_MODE_SIZE (GET_MODE (op));
2422 if (size != 1 && size != 2)
2423 return false;
2424
2425 return (GET_CODE (addr) == inc_code
2426 || (GET_CODE (addr) == PLUS
2427 && GET_CODE (XEXP (addr, 0)) == REG
2428 && h8300_displacement_length (addr, size) == 2));
2429 }
2430
2431 /* Calculate the length of move instruction INSN using the given length
2432 table. Although the tables are correct for most cases, there is some
2433 irregularity in the length of mov.b and mov.w. The following forms:
2434
2435 mov @ERs+, Rd
2436 mov @(d:16,ERs), Rd
2437 mov Rs, @-ERd
2438 mov Rs, @(d:16,ERd)
2439
2440 are two bytes shorter than most other "mov Rs, @complex" or
2441 "mov @complex,Rd" combinations. */
2442
2443 static unsigned int
2444 h8300_move_length (rtx *operands, const h8300_length_table *table)
2445 {
2446 unsigned int size;
2447
2448 size = h8300_length_from_table (operands[0], operands[1], table);
2449 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2450 size -= 2;
2451 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2452 size -= 2;
2453 return size;
2454 }
2455
2456 /* Return the length of a mova instruction with the given operands.
2457 DEST is the register destination, SRC is the source address and
2458 OFFSET is the 16-bit or 32-bit displacement. */
2459
2460 static unsigned int
2461 h8300_mova_length (rtx dest, rtx src, rtx offset)
2462 {
2463 unsigned int size;
2464
2465 size = (2
2466 + h8300_constant_length (offset)
2467 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2468 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2469 size += 2;
2470 return size;
2471 }
2472
2473 /* Compute the length of INSN based on its length_table attribute.
2474 OPERANDS is the array of its operands. */
2475
2476 unsigned int
2477 h8300_insn_length_from_table (rtx insn, rtx * operands)
2478 {
2479 switch (get_attr_length_table (insn))
2480 {
2481 case LENGTH_TABLE_NONE:
2482 gcc_unreachable ();
2483
2484 case LENGTH_TABLE_ADDB:
2485 return h8300_binary_length (insn, &addb_length_table);
2486
2487 case LENGTH_TABLE_ADDW:
2488 return h8300_binary_length (insn, &addw_length_table);
2489
2490 case LENGTH_TABLE_ADDL:
2491 return h8300_binary_length (insn, &addl_length_table);
2492
2493 case LENGTH_TABLE_LOGICB:
2494 return h8300_binary_length (insn, &logicb_length_table);
2495
2496 case LENGTH_TABLE_MOVB:
2497 return h8300_move_length (operands, &movb_length_table);
2498
2499 case LENGTH_TABLE_MOVW:
2500 return h8300_move_length (operands, &movw_length_table);
2501
2502 case LENGTH_TABLE_MOVL:
2503 return h8300_move_length (operands, &movl_length_table);
2504
2505 case LENGTH_TABLE_MOVA:
2506 return h8300_mova_length (operands[0], operands[1], operands[2]);
2507
2508 case LENGTH_TABLE_MOVA_ZERO:
2509 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2510
2511 case LENGTH_TABLE_UNARY:
2512 return h8300_unary_length (operands[0]);
2513
2514 case LENGTH_TABLE_MOV_IMM4:
2515 return 2 + h8300_classify_operand (operands[0], 0, 0);
2516
2517 case LENGTH_TABLE_SHORT_IMMEDIATE:
2518 return h8300_short_immediate_length (operands[0]);
2519
2520 case LENGTH_TABLE_BITFIELD:
2521 return h8300_bitfield_length (operands[0], operands[1]);
2522
2523 case LENGTH_TABLE_BITBRANCH:
2524 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2525
2526 default:
2527 gcc_unreachable ();
2528 }
2529 }
2530
2531 /* Return true if LHS and RHS are memory references that can be mapped
2532 to the same h8sx assembly operand. LHS appears as the destination of
2533 an instruction and RHS appears as a source.
2534
2535 Three cases are allowed:
2536
2537 - RHS is @+Rn or @-Rn, LHS is @Rn
2538 - RHS is @Rn, LHS is @Rn+ or @Rn-
2539 - RHS and LHS have the same address and neither has side effects. */
2540
2541 bool
2542 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2543 {
2544 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2545 {
2546 rhs = XEXP (rhs, 0);
2547 lhs = XEXP (lhs, 0);
2548
2549 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2550 return rtx_equal_p (XEXP (rhs, 0), lhs);
2551
2552 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2553 return rtx_equal_p (rhs, XEXP (lhs, 0));
2554
2555 if (rtx_equal_p (rhs, lhs))
2556 return true;
2557 }
2558 return false;
2559 }
2560
2561 /* Return true if OPERANDS[1] can be mapped to the same assembly
2562 operand as OPERANDS[0]. */
2563
2564 bool
2565 h8300_operands_match_p (rtx *operands)
2566 {
2567 if (register_operand (operands[0], VOIDmode)
2568 && register_operand (operands[1], VOIDmode))
2569 return true;
2570
2571 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2572 return true;
2573
2574 return false;
2575 }
2576 \f
2577 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2578 region DEST. The two regions do not overlap and have the common
2579 alignment given by ALIGNMENT. Return true on success.
2580
2581 Using movmd for variable-length moves seems to involve some
2582 complex trade-offs. For instance:
2583
2584 - Preparing for a movmd instruction is similar to preparing
2585 for a memcpy. The main difference is that the arguments
2586 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2587
2588 - Since movmd clobbers the frame pointer, we need to save
2589 and restore it somehow when frame_pointer_needed. This can
2590 sometimes make movmd sequences longer than calls to memcpy().
2591
2592 - The counter register is 16 bits, so the instruction is only
2593 suitable for variable-length moves when sizeof (size_t) == 2.
2594 That's only true in normal mode.
2595
2596 - We will often lack static alignment information. Falling back
2597 on movmd.b would likely be slower than calling memcpy(), at least
2598 for big moves.
2599
2600 This function therefore only uses movmd when the length is a
2601 known constant, and only then if -fomit-frame-pointer is in
2602 effect or if we're not optimizing for size.
2603
2604 At the moment the function uses movmd for all in-range constants,
2605 but it might be better to fall back on memcpy() for large moves
2606 if ALIGNMENT == 1. */
2607
2608 bool
2609 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2610 HOST_WIDE_INT alignment)
2611 {
2612 if (!flag_omit_frame_pointer && optimize_size)
2613 return false;
2614
2615 if (GET_CODE (length) == CONST_INT)
2616 {
2617 rtx dest_reg, src_reg, first_dest, first_src;
2618 HOST_WIDE_INT n;
2619 int factor;
2620
2621 /* Use movmd.l if the alignment allows it, otherwise fall back
2622 on movmd.b. */
2623 factor = (alignment >= 2 ? 4 : 1);
2624
2625 /* Make sure the length is within range. We can handle counter
2626 values up to 65536, although HImode truncation will make
2627 the count appear negative in rtl dumps. */
2628 n = INTVAL (length);
2629 if (n <= 0 || n / factor > 65536)
2630 return false;
2631
2632 /* Create temporary registers for the source and destination
2633 pointers. Initialize them to the start of each region. */
2634 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2635 src_reg = copy_addr_to_reg (XEXP (src, 0));
2636
2637 /* Create references to the movmd source and destination blocks. */
2638 first_dest = replace_equiv_address (dest, dest_reg);
2639 first_src = replace_equiv_address (src, src_reg);
2640
2641 set_mem_size (first_dest, GEN_INT (n & -factor));
2642 set_mem_size (first_src, GEN_INT (n & -factor));
2643
2644 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2645 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2646
2647 if ((n & -factor) != n)
2648 {
2649 /* Move SRC and DEST past the region we just copied.
2650 This is done to update the memory attributes. */
2651 dest = adjust_address (dest, BLKmode, n & -factor);
2652 src = adjust_address (src, BLKmode, n & -factor);
2653
2654 /* Replace the addresses with the source and destination
2655 registers, which movmd has left with the right values. */
2656 dest = replace_equiv_address (dest, dest_reg);
2657 src = replace_equiv_address (src, src_reg);
2658
2659 /* Mop up the left-over bytes. */
2660 if (n & 2)
2661 emit_move_insn (adjust_address (dest, HImode, 0),
2662 adjust_address (src, HImode, 0));
2663 if (n & 1)
2664 emit_move_insn (adjust_address (dest, QImode, n & 2),
2665 adjust_address (src, QImode, n & 2));
2666 }
2667 return true;
2668 }
2669 return false;
2670 }
2671
2672 /* Move ADDR into er6 after pushing its old value onto the stack. */
2673
2674 void
2675 h8300_swap_into_er6 (rtx addr)
2676 {
2677 push (HARD_FRAME_POINTER_REGNUM);
2678 emit_move_insn (hard_frame_pointer_rtx, addr);
2679 if (REGNO (addr) == SP_REG)
2680 emit_move_insn (hard_frame_pointer_rtx,
2681 plus_constant (hard_frame_pointer_rtx,
2682 GET_MODE_SIZE (word_mode)));
2683 }
2684
2685 /* Move the current value of er6 into ADDR and pop its old value
2686 from the stack. */
2687
2688 void
2689 h8300_swap_out_of_er6 (rtx addr)
2690 {
2691 if (REGNO (addr) != SP_REG)
2692 emit_move_insn (addr, hard_frame_pointer_rtx);
2693 pop (HARD_FRAME_POINTER_REGNUM);
2694 }
2695 \f
2696 /* Return the length of mov instruction. */
2697
2698 unsigned int
2699 compute_mov_length (rtx *operands)
2700 {
2701 /* If the mov instruction involves a memory operand, we compute the
2702 length, assuming the largest addressing mode is used, and then
2703 adjust later in the function. Otherwise, we compute and return
2704 the exact length in one step. */
2705 enum machine_mode mode = GET_MODE (operands[0]);
2706 rtx dest = operands[0];
2707 rtx src = operands[1];
2708 rtx addr;
2709
2710 if (GET_CODE (src) == MEM)
2711 addr = XEXP (src, 0);
2712 else if (GET_CODE (dest) == MEM)
2713 addr = XEXP (dest, 0);
2714 else
2715 addr = NULL_RTX;
2716
2717 if (TARGET_H8300)
2718 {
2719 unsigned int base_length;
2720
2721 switch (mode)
2722 {
2723 case QImode:
2724 if (addr == NULL_RTX)
2725 return 2;
2726
2727 /* The eightbit addressing is available only in QImode, so
2728 go ahead and take care of it. */
2729 if (h8300_eightbit_constant_address_p (addr))
2730 return 2;
2731
2732 base_length = 4;
2733 break;
2734
2735 case HImode:
2736 if (addr == NULL_RTX)
2737 {
2738 if (REG_P (src))
2739 return 2;
2740
2741 if (src == const0_rtx)
2742 return 2;
2743
2744 return 4;
2745 }
2746
2747 base_length = 4;
2748 break;
2749
2750 case SImode:
2751 if (addr == NULL_RTX)
2752 {
2753 if (REG_P (src))
2754 return 4;
2755
2756 if (GET_CODE (src) == CONST_INT)
2757 {
2758 if (src == const0_rtx)
2759 return 4;
2760
2761 if ((INTVAL (src) & 0xffff) == 0)
2762 return 6;
2763
2764 if ((INTVAL (src) & 0xffff) == 0)
2765 return 6;
2766
2767 if ((INTVAL (src) & 0xffff)
2768 == ((INTVAL (src) >> 16) & 0xffff))
2769 return 6;
2770 }
2771 return 8;
2772 }
2773
2774 base_length = 8;
2775 break;
2776
2777 case SFmode:
2778 if (addr == NULL_RTX)
2779 {
2780 if (REG_P (src))
2781 return 4;
2782
2783 if (satisfies_constraint_G (src))
2784 return 4;
2785
2786 return 8;
2787 }
2788
2789 base_length = 8;
2790 break;
2791
2792 default:
2793 gcc_unreachable ();
2794 }
2795
2796 /* Adjust the length based on the addressing mode used.
2797 Specifically, we subtract the difference between the actual
2798 length and the longest one, which is @(d:16,Rs). For SImode
2799 and SFmode, we double the adjustment because two mov.w are
2800 used to do the job. */
2801
2802 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2803 if (GET_CODE (addr) == PRE_DEC
2804 || GET_CODE (addr) == POST_INC)
2805 {
2806 if (mode == QImode || mode == HImode)
2807 return base_length - 2;
2808 else
2809 /* In SImode and SFmode, we use two mov.w instructions, so
2810 double the adjustment. */
2811 return base_length - 4;
2812 }
2813
2814 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2815 in SImode and SFmode, the second mov.w involves an address
2816 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2817 only 2 bytes. */
2818 if (GET_CODE (addr) == REG)
2819 return base_length - 2;
2820
2821 return base_length;
2822 }
2823 else
2824 {
2825 unsigned int base_length;
2826
2827 switch (mode)
2828 {
2829 case QImode:
2830 if (addr == NULL_RTX)
2831 return 2;
2832
2833 /* The eightbit addressing is available only in QImode, so
2834 go ahead and take care of it. */
2835 if (h8300_eightbit_constant_address_p (addr))
2836 return 2;
2837
2838 base_length = 8;
2839 break;
2840
2841 case HImode:
2842 if (addr == NULL_RTX)
2843 {
2844 if (REG_P (src))
2845 return 2;
2846
2847 if (src == const0_rtx)
2848 return 2;
2849
2850 return 4;
2851 }
2852
2853 base_length = 8;
2854 break;
2855
2856 case SImode:
2857 if (addr == NULL_RTX)
2858 {
2859 if (REG_P (src))
2860 {
2861 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2862 return 4;
2863 else
2864 return 2;
2865 }
2866
2867 if (GET_CODE (src) == CONST_INT)
2868 {
2869 int val = INTVAL (src);
2870
2871 if (val == 0)
2872 return 2;
2873
2874 if (val == (val & 0x00ff) || val == (val & 0xff00))
2875 return 4;
2876
2877 switch (val & 0xffffffff)
2878 {
2879 case 0xffffffff:
2880 case 0xfffffffe:
2881 case 0xfffffffc:
2882 case 0x0000ffff:
2883 case 0x0000fffe:
2884 case 0xffff0000:
2885 case 0xfffe0000:
2886 case 0x00010000:
2887 case 0x00020000:
2888 return 4;
2889 }
2890 }
2891 return 6;
2892 }
2893
2894 base_length = 10;
2895 break;
2896
2897 case SFmode:
2898 if (addr == NULL_RTX)
2899 {
2900 if (REG_P (src))
2901 return 2;
2902
2903 if (satisfies_constraint_G (src))
2904 return 2;
2905
2906 return 6;
2907 }
2908
2909 base_length = 10;
2910 break;
2911
2912 default:
2913 gcc_unreachable ();
2914 }
2915
2916 /* Adjust the length based on the addressing mode used.
2917 Specifically, we subtract the difference between the actual
2918 length and the longest one, which is @(d:24,ERs). */
2919
2920 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2921 if (GET_CODE (addr) == PRE_DEC
2922 || GET_CODE (addr) == POST_INC)
2923 return base_length - 6;
2924
2925 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2926 if (GET_CODE (addr) == REG)
2927 return base_length - 6;
2928
2929 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2930 longest. */
2931 if (GET_CODE (addr) == PLUS
2932 && GET_CODE (XEXP (addr, 0)) == REG
2933 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2934 && INTVAL (XEXP (addr, 1)) > -32768
2935 && INTVAL (XEXP (addr, 1)) < 32767)
2936 return base_length - 4;
2937
2938 /* @aa:16 is 4 bytes shorter than the longest. */
2939 if (h8300_tiny_constant_address_p (addr))
2940 return base_length - 4;
2941
2942 /* @aa:24 is 2 bytes shorter than the longest. */
2943 if (CONSTANT_P (addr))
2944 return base_length - 2;
2945
2946 return base_length;
2947 }
2948 }
2949 \f
2950 /* Output an addition insn. */
2951
2952 const char *
2953 output_plussi (rtx *operands)
2954 {
2955 enum machine_mode mode = GET_MODE (operands[0]);
2956
2957 gcc_assert (mode == SImode);
2958
2959 if (TARGET_H8300)
2960 {
2961 if (GET_CODE (operands[2]) == REG)
2962 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2963
2964 if (GET_CODE (operands[2]) == CONST_INT)
2965 {
2966 HOST_WIDE_INT n = INTVAL (operands[2]);
2967
2968 if ((n & 0xffffff) == 0)
2969 return "add\t%z2,%z0";
2970 if ((n & 0xffff) == 0)
2971 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2972 if ((n & 0xff) == 0)
2973 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2974 }
2975
2976 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2977 }
2978 else
2979 {
2980 if (GET_CODE (operands[2]) == CONST_INT
2981 && register_operand (operands[1], VOIDmode))
2982 {
2983 HOST_WIDE_INT intval = INTVAL (operands[2]);
2984
2985 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
2986 return "add.l\t%S2,%S0";
2987 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
2988 return "sub.l\t%G2,%S0";
2989
2990 /* See if we can finish with 2 bytes. */
2991
2992 switch ((unsigned int) intval & 0xffffffff)
2993 {
2994 case 0x00000001:
2995 case 0x00000002:
2996 case 0x00000004:
2997 return "adds\t%2,%S0";
2998
2999 case 0xffffffff:
3000 case 0xfffffffe:
3001 case 0xfffffffc:
3002 return "subs\t%G2,%S0";
3003
3004 case 0x00010000:
3005 case 0x00020000:
3006 operands[2] = GEN_INT (intval >> 16);
3007 return "inc.w\t%2,%e0";
3008
3009 case 0xffff0000:
3010 case 0xfffe0000:
3011 operands[2] = GEN_INT (intval >> 16);
3012 return "dec.w\t%G2,%e0";
3013 }
3014
3015 /* See if we can finish with 4 bytes. */
3016 if ((intval & 0xffff) == 0)
3017 {
3018 operands[2] = GEN_INT (intval >> 16);
3019 return "add.w\t%2,%e0";
3020 }
3021 }
3022
3023 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3024 {
3025 operands[2] = GEN_INT (-INTVAL (operands[2]));
3026 return "sub.l\t%S2,%S0";
3027 }
3028 return "add.l\t%S2,%S0";
3029 }
3030 }
3031
3032 /* ??? It would be much easier to add the h8sx stuff if a single function
3033 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3034 /* Compute the length of an addition insn. */
3035
3036 unsigned int
3037 compute_plussi_length (rtx *operands)
3038 {
3039 enum machine_mode mode = GET_MODE (operands[0]);
3040
3041 gcc_assert (mode == SImode);
3042
3043 if (TARGET_H8300)
3044 {
3045 if (GET_CODE (operands[2]) == REG)
3046 return 6;
3047
3048 if (GET_CODE (operands[2]) == CONST_INT)
3049 {
3050 HOST_WIDE_INT n = INTVAL (operands[2]);
3051
3052 if ((n & 0xffffff) == 0)
3053 return 2;
3054 if ((n & 0xffff) == 0)
3055 return 4;
3056 if ((n & 0xff) == 0)
3057 return 6;
3058 }
3059
3060 return 8;
3061 }
3062 else
3063 {
3064 if (GET_CODE (operands[2]) == CONST_INT
3065 && register_operand (operands[1], VOIDmode))
3066 {
3067 HOST_WIDE_INT intval = INTVAL (operands[2]);
3068
3069 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3070 return 2;
3071 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3072 return 2;
3073
3074 /* See if we can finish with 2 bytes. */
3075
3076 switch ((unsigned int) intval & 0xffffffff)
3077 {
3078 case 0x00000001:
3079 case 0x00000002:
3080 case 0x00000004:
3081 return 2;
3082
3083 case 0xffffffff:
3084 case 0xfffffffe:
3085 case 0xfffffffc:
3086 return 2;
3087
3088 case 0x00010000:
3089 case 0x00020000:
3090 return 2;
3091
3092 case 0xffff0000:
3093 case 0xfffe0000:
3094 return 2;
3095 }
3096
3097 /* See if we can finish with 4 bytes. */
3098 if ((intval & 0xffff) == 0)
3099 return 4;
3100 }
3101
3102 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3103 return h8300_length_from_table (operands[0],
3104 GEN_INT (-INTVAL (operands[2])),
3105 &addl_length_table);
3106 else
3107 return h8300_length_from_table (operands[0], operands[2],
3108 &addl_length_table);
3109 return 6;
3110 }
3111 }
3112
3113 /* Compute which flag bits are valid after an addition insn. */
3114
3115 enum attr_cc
3116 compute_plussi_cc (rtx *operands)
3117 {
3118 enum machine_mode mode = GET_MODE (operands[0]);
3119
3120 gcc_assert (mode == SImode);
3121
3122 if (TARGET_H8300)
3123 {
3124 return CC_CLOBBER;
3125 }
3126 else
3127 {
3128 if (GET_CODE (operands[2]) == CONST_INT
3129 && register_operand (operands[1], VOIDmode))
3130 {
3131 HOST_WIDE_INT intval = INTVAL (operands[2]);
3132
3133 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3134 return CC_SET_ZN;
3135 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3136 return CC_SET_ZN;
3137
3138 /* See if we can finish with 2 bytes. */
3139
3140 switch ((unsigned int) intval & 0xffffffff)
3141 {
3142 case 0x00000001:
3143 case 0x00000002:
3144 case 0x00000004:
3145 return CC_NONE_0HIT;
3146
3147 case 0xffffffff:
3148 case 0xfffffffe:
3149 case 0xfffffffc:
3150 return CC_NONE_0HIT;
3151
3152 case 0x00010000:
3153 case 0x00020000:
3154 return CC_CLOBBER;
3155
3156 case 0xffff0000:
3157 case 0xfffe0000:
3158 return CC_CLOBBER;
3159 }
3160
3161 /* See if we can finish with 4 bytes. */
3162 if ((intval & 0xffff) == 0)
3163 return CC_CLOBBER;
3164 }
3165
3166 return CC_SET_ZN;
3167 }
3168 }
3169 \f
3170 /* Output a logical insn. */
3171
3172 const char *
3173 output_logical_op (enum machine_mode mode, rtx *operands)
3174 {
3175 /* Figure out the logical op that we need to perform. */
3176 enum rtx_code code = GET_CODE (operands[3]);
3177 /* Pretend that every byte is affected if both operands are registers. */
3178 const unsigned HOST_WIDE_INT intval =
3179 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3180 /* Always use the full instruction if the
3181 first operand is in memory. It is better
3182 to use define_splits to generate the shorter
3183 sequence where valid. */
3184 && register_operand (operands[1], VOIDmode)
3185 ? INTVAL (operands[2]) : 0x55555555);
3186 /* The determinant of the algorithm. If we perform an AND, 0
3187 affects a bit. Otherwise, 1 affects a bit. */
3188 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3189 /* Break up DET into pieces. */
3190 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3191 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3192 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3193 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3194 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3195 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3196 int lower_half_easy_p = 0;
3197 int upper_half_easy_p = 0;
3198 /* The name of an insn. */
3199 const char *opname;
3200 char insn_buf[100];
3201
3202 switch (code)
3203 {
3204 case AND:
3205 opname = "and";
3206 break;
3207 case IOR:
3208 opname = "or";
3209 break;
3210 case XOR:
3211 opname = "xor";
3212 break;
3213 default:
3214 gcc_unreachable ();
3215 }
3216
3217 switch (mode)
3218 {
3219 case HImode:
3220 /* First, see if we can finish with one insn. */
3221 if ((TARGET_H8300H || TARGET_H8300S)
3222 && b0 != 0
3223 && b1 != 0)
3224 {
3225 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3226 output_asm_insn (insn_buf, operands);
3227 }
3228 else
3229 {
3230 /* Take care of the lower byte. */
3231 if (b0 != 0)
3232 {
3233 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3234 output_asm_insn (insn_buf, operands);
3235 }
3236 /* Take care of the upper byte. */
3237 if (b1 != 0)
3238 {
3239 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3240 output_asm_insn (insn_buf, operands);
3241 }
3242 }
3243 break;
3244 case SImode:
3245 if (TARGET_H8300H || TARGET_H8300S)
3246 {
3247 /* Determine if the lower half can be taken care of in no more
3248 than two bytes. */
3249 lower_half_easy_p = (b0 == 0
3250 || b1 == 0
3251 || (code != IOR && w0 == 0xffff));
3252
3253 /* Determine if the upper half can be taken care of in no more
3254 than two bytes. */
3255 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3256 || (code == AND && w1 == 0xff00));
3257 }
3258
3259 /* Check if doing everything with one insn is no worse than
3260 using multiple insns. */
3261 if ((TARGET_H8300H || TARGET_H8300S)
3262 && w0 != 0 && w1 != 0
3263 && !(lower_half_easy_p && upper_half_easy_p)
3264 && !(code == IOR && w1 == 0xffff
3265 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3266 {
3267 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3268 output_asm_insn (insn_buf, operands);
3269 }
3270 else
3271 {
3272 /* Take care of the lower and upper words individually. For
3273 each word, we try different methods in the order of
3274
3275 1) the special insn (in case of AND or XOR),
3276 2) the word-wise insn, and
3277 3) The byte-wise insn. */
3278 if (w0 == 0xffff
3279 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3280 output_asm_insn ((code == AND)
3281 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3282 operands);
3283 else if ((TARGET_H8300H || TARGET_H8300S)
3284 && (b0 != 0)
3285 && (b1 != 0))
3286 {
3287 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3288 output_asm_insn (insn_buf, operands);
3289 }
3290 else
3291 {
3292 if (b0 != 0)
3293 {
3294 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3295 output_asm_insn (insn_buf, operands);
3296 }
3297 if (b1 != 0)
3298 {
3299 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3300 output_asm_insn (insn_buf, operands);
3301 }
3302 }
3303
3304 if ((w1 == 0xffff)
3305 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3306 output_asm_insn ((code == AND)
3307 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3308 operands);
3309 else if ((TARGET_H8300H || TARGET_H8300S)
3310 && code == IOR
3311 && w1 == 0xffff
3312 && (w0 & 0x8000) != 0)
3313 {
3314 output_asm_insn ("exts.l\t%S0", operands);
3315 }
3316 else if ((TARGET_H8300H || TARGET_H8300S)
3317 && code == AND
3318 && w1 == 0xff00)
3319 {
3320 output_asm_insn ("extu.w\t%e0", operands);
3321 }
3322 else if (TARGET_H8300H || TARGET_H8300S)
3323 {
3324 if (w1 != 0)
3325 {
3326 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3327 output_asm_insn (insn_buf, operands);
3328 }
3329 }
3330 else
3331 {
3332 if (b2 != 0)
3333 {
3334 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3335 output_asm_insn (insn_buf, operands);
3336 }
3337 if (b3 != 0)
3338 {
3339 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3340 output_asm_insn (insn_buf, operands);
3341 }
3342 }
3343 }
3344 break;
3345 default:
3346 gcc_unreachable ();
3347 }
3348 return "";
3349 }
3350
3351 /* Compute the length of a logical insn. */
3352
3353 unsigned int
3354 compute_logical_op_length (enum machine_mode mode, rtx *operands)
3355 {
3356 /* Figure out the logical op that we need to perform. */
3357 enum rtx_code code = GET_CODE (operands[3]);
3358 /* Pretend that every byte is affected if both operands are registers. */
3359 const unsigned HOST_WIDE_INT intval =
3360 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3361 /* Always use the full instruction if the
3362 first operand is in memory. It is better
3363 to use define_splits to generate the shorter
3364 sequence where valid. */
3365 && register_operand (operands[1], VOIDmode)
3366 ? INTVAL (operands[2]) : 0x55555555);
3367 /* The determinant of the algorithm. If we perform an AND, 0
3368 affects a bit. Otherwise, 1 affects a bit. */
3369 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3370 /* Break up DET into pieces. */
3371 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3372 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3373 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3374 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3375 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3376 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3377 int lower_half_easy_p = 0;
3378 int upper_half_easy_p = 0;
3379 /* Insn length. */
3380 unsigned int length = 0;
3381
3382 switch (mode)
3383 {
3384 case HImode:
3385 /* First, see if we can finish with one insn. */
3386 if ((TARGET_H8300H || TARGET_H8300S)
3387 && b0 != 0
3388 && b1 != 0)
3389 {
3390 length = h8300_length_from_table (operands[1], operands[2],
3391 &logicw_length_table);
3392 }
3393 else
3394 {
3395 /* Take care of the lower byte. */
3396 if (b0 != 0)
3397 length += 2;
3398
3399 /* Take care of the upper byte. */
3400 if (b1 != 0)
3401 length += 2;
3402 }
3403 break;
3404 case SImode:
3405 if (TARGET_H8300H || TARGET_H8300S)
3406 {
3407 /* Determine if the lower half can be taken care of in no more
3408 than two bytes. */
3409 lower_half_easy_p = (b0 == 0
3410 || b1 == 0
3411 || (code != IOR && w0 == 0xffff));
3412
3413 /* Determine if the upper half can be taken care of in no more
3414 than two bytes. */
3415 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3416 || (code == AND && w1 == 0xff00));
3417 }
3418
3419 /* Check if doing everything with one insn is no worse than
3420 using multiple insns. */
3421 if ((TARGET_H8300H || TARGET_H8300S)
3422 && w0 != 0 && w1 != 0
3423 && !(lower_half_easy_p && upper_half_easy_p)
3424 && !(code == IOR && w1 == 0xffff
3425 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3426 {
3427 length = h8300_length_from_table (operands[1], operands[2],
3428 &logicl_length_table);
3429 }
3430 else
3431 {
3432 /* Take care of the lower and upper words individually. For
3433 each word, we try different methods in the order of
3434
3435 1) the special insn (in case of AND or XOR),
3436 2) the word-wise insn, and
3437 3) The byte-wise insn. */
3438 if (w0 == 0xffff
3439 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3440 {
3441 length += 2;
3442 }
3443 else if ((TARGET_H8300H || TARGET_H8300S)
3444 && (b0 != 0)
3445 && (b1 != 0))
3446 {
3447 length += 4;
3448 }
3449 else
3450 {
3451 if (b0 != 0)
3452 length += 2;
3453
3454 if (b1 != 0)
3455 length += 2;
3456 }
3457
3458 if (w1 == 0xffff
3459 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3460 {
3461 length += 2;
3462 }
3463 else if ((TARGET_H8300H || TARGET_H8300S)
3464 && code == IOR
3465 && w1 == 0xffff
3466 && (w0 & 0x8000) != 0)
3467 {
3468 length += 2;
3469 }
3470 else if ((TARGET_H8300H || TARGET_H8300S)
3471 && code == AND
3472 && w1 == 0xff00)
3473 {
3474 length += 2;
3475 }
3476 else if (TARGET_H8300H || TARGET_H8300S)
3477 {
3478 if (w1 != 0)
3479 length += 4;
3480 }
3481 else
3482 {
3483 if (b2 != 0)
3484 length += 2;
3485
3486 if (b3 != 0)
3487 length += 2;
3488 }
3489 }
3490 break;
3491 default:
3492 gcc_unreachable ();
3493 }
3494 return length;
3495 }
3496
3497 /* Compute which flag bits are valid after a logical insn. */
3498
3499 enum attr_cc
3500 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
3501 {
3502 /* Figure out the logical op that we need to perform. */
3503 enum rtx_code code = GET_CODE (operands[3]);
3504 /* Pretend that every byte is affected if both operands are registers. */
3505 const unsigned HOST_WIDE_INT intval =
3506 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3507 /* Always use the full instruction if the
3508 first operand is in memory. It is better
3509 to use define_splits to generate the shorter
3510 sequence where valid. */
3511 && register_operand (operands[1], VOIDmode)
3512 ? INTVAL (operands[2]) : 0x55555555);
3513 /* The determinant of the algorithm. If we perform an AND, 0
3514 affects a bit. Otherwise, 1 affects a bit. */
3515 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3516 /* Break up DET into pieces. */
3517 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3518 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3519 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3520 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3521 int lower_half_easy_p = 0;
3522 int upper_half_easy_p = 0;
3523 /* Condition code. */
3524 enum attr_cc cc = CC_CLOBBER;
3525
3526 switch (mode)
3527 {
3528 case HImode:
3529 /* First, see if we can finish with one insn. */
3530 if ((TARGET_H8300H || TARGET_H8300S)
3531 && b0 != 0
3532 && b1 != 0)
3533 {
3534 cc = CC_SET_ZNV;
3535 }
3536 break;
3537 case SImode:
3538 if (TARGET_H8300H || TARGET_H8300S)
3539 {
3540 /* Determine if the lower half can be taken care of in no more
3541 than two bytes. */
3542 lower_half_easy_p = (b0 == 0
3543 || b1 == 0
3544 || (code != IOR && w0 == 0xffff));
3545
3546 /* Determine if the upper half can be taken care of in no more
3547 than two bytes. */
3548 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3549 || (code == AND && w1 == 0xff00));
3550 }
3551
3552 /* Check if doing everything with one insn is no worse than
3553 using multiple insns. */
3554 if ((TARGET_H8300H || TARGET_H8300S)
3555 && w0 != 0 && w1 != 0
3556 && !(lower_half_easy_p && upper_half_easy_p)
3557 && !(code == IOR && w1 == 0xffff
3558 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3559 {
3560 cc = CC_SET_ZNV;
3561 }
3562 else
3563 {
3564 if ((TARGET_H8300H || TARGET_H8300S)
3565 && code == IOR
3566 && w1 == 0xffff
3567 && (w0 & 0x8000) != 0)
3568 {
3569 cc = CC_SET_ZNV;
3570 }
3571 }
3572 break;
3573 default:
3574 gcc_unreachable ();
3575 }
3576 return cc;
3577 }
3578 \f
3579 /* Expand a conditional branch. */
3580
3581 void
3582 h8300_expand_branch (rtx operands[])
3583 {
3584 enum rtx_code code = GET_CODE (operands[0]);
3585 rtx op0 = operands[1];
3586 rtx op1 = operands[2];
3587 rtx label = operands[3];
3588 rtx tmp;
3589
3590 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3591 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3592
3593 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3594 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3595 gen_rtx_LABEL_REF (VOIDmode, label),
3596 pc_rtx);
3597 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3598 }
3599
3600
3601 /* Expand a conditional store. */
3602
3603 void
3604 h8300_expand_store (rtx operands[])
3605 {
3606 rtx dest = operands[0];
3607 enum rtx_code code = GET_CODE (operands[1]);
3608 rtx op0 = operands[2];
3609 rtx op1 = operands[3];
3610 rtx tmp;
3611
3612 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3613 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3614
3615 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3616 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3617 }
3618 \f
3619 /* Shifts.
3620
3621 We devote a fair bit of code to getting efficient shifts since we
3622 can only shift one bit at a time on the H8/300 and H8/300H and only
3623 one or two bits at a time on the H8S.
3624
3625 All shift code falls into one of the following ways of
3626 implementation:
3627
3628 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3629 when a straight line shift is about the same size or smaller than
3630 a loop.
3631
3632 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3633 off the bits we don't need. This is used when only a few of the
3634 bits in the original value will survive in the shifted value.
3635
3636 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3637 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3638 shifts can be added if the shift count is slightly more than 8 or
3639 16. This case also includes other oddballs that are not worth
3640 explaining here.
3641
3642 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3643
3644 For each shift count, we try to use code that has no trade-off
3645 between code size and speed whenever possible.
3646
3647 If the trade-off is unavoidable, we try to be reasonable.
3648 Specifically, the fastest version is one instruction longer than
3649 the shortest version, we take the fastest version. We also provide
3650 the use a way to switch back to the shortest version with -Os.
3651
3652 For the details of the shift algorithms for various shift counts,
3653 refer to shift_alg_[qhs]i. */
3654
3655 /* Classify a shift with the given mode and code. OP is the shift amount. */
3656
3657 enum h8sx_shift_type
3658 h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3659 {
3660 if (!TARGET_H8300SX)
3661 return H8SX_SHIFT_NONE;
3662
3663 switch (code)
3664 {
3665 case ASHIFT:
3666 case LSHIFTRT:
3667 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3668 if (GET_CODE (op) != CONST_INT)
3669 return H8SX_SHIFT_BINARY;
3670
3671 /* Reject out-of-range shift amounts. */
3672 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3673 return H8SX_SHIFT_NONE;
3674
3675 /* Power-of-2 shifts are effectively unary operations. */
3676 if (exact_log2 (INTVAL (op)) >= 0)
3677 return H8SX_SHIFT_UNARY;
3678
3679 return H8SX_SHIFT_BINARY;
3680
3681 case ASHIFTRT:
3682 if (op == const1_rtx || op == const2_rtx)
3683 return H8SX_SHIFT_UNARY;
3684 return H8SX_SHIFT_NONE;
3685
3686 case ROTATE:
3687 if (GET_CODE (op) == CONST_INT
3688 && (INTVAL (op) == 1
3689 || INTVAL (op) == 2
3690 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3691 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3692 return H8SX_SHIFT_UNARY;
3693 return H8SX_SHIFT_NONE;
3694
3695 default:
3696 return H8SX_SHIFT_NONE;
3697 }
3698 }
3699
3700 /* Return the asm template for a single h8sx shift instruction.
3701 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3702 is the source and OPERANDS[3] is the shift. SUFFIX is the
3703 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3704 prefix for the destination operand. */
3705
3706 const char *
3707 output_h8sx_shift (rtx *operands, int suffix, int optype)
3708 {
3709 static char buffer[16];
3710 const char *stem;
3711
3712 switch (GET_CODE (operands[3]))
3713 {
3714 case ASHIFT:
3715 stem = "shll";
3716 break;
3717
3718 case ASHIFTRT:
3719 stem = "shar";
3720 break;
3721
3722 case LSHIFTRT:
3723 stem = "shlr";
3724 break;
3725
3726 case ROTATE:
3727 stem = "rotl";
3728 if (INTVAL (operands[2]) > 2)
3729 {
3730 /* This is really a right rotate. */
3731 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3732 - INTVAL (operands[2]));
3733 stem = "rotr";
3734 }
3735 break;
3736
3737 default:
3738 gcc_unreachable ();
3739 }
3740 if (operands[2] == const1_rtx)
3741 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3742 else
3743 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3744 return buffer;
3745 }
3746
3747 /* Emit code to do shifts. */
3748
3749 bool
3750 expand_a_shift (enum machine_mode mode, enum rtx_code code, rtx operands[])
3751 {
3752 switch (h8sx_classify_shift (mode, code, operands[2]))
3753 {
3754 case H8SX_SHIFT_BINARY:
3755 operands[1] = force_reg (mode, operands[1]);
3756 return false;
3757
3758 case H8SX_SHIFT_UNARY:
3759 return false;
3760
3761 case H8SX_SHIFT_NONE:
3762 break;
3763 }
3764
3765 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3766
3767 /* Need a loop to get all the bits we want - we generate the
3768 code at emit time, but need to allocate a scratch reg now. */
3769
3770 emit_insn (gen_rtx_PARALLEL
3771 (VOIDmode,
3772 gen_rtvec (2,
3773 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
3774 gen_rtx_fmt_ee (code, mode,
3775 copy_rtx (operands[0]), operands[2])),
3776 gen_rtx_CLOBBER (VOIDmode,
3777 gen_rtx_SCRATCH (QImode)))));
3778 return true;
3779 }
3780
3781 /* Symbols of the various modes which can be used as indices. */
3782
3783 enum shift_mode
3784 {
3785 QIshift, HIshift, SIshift
3786 };
3787
3788 /* For single bit shift insns, record assembler and what bits of the
3789 condition code are valid afterwards (represented as various CC_FOO
3790 bits, 0 means CC isn't left in a usable state). */
3791
3792 struct shift_insn
3793 {
3794 const char *const assembler;
3795 const enum attr_cc cc_valid;
3796 };
3797
3798 /* Assembler instruction shift table.
3799
3800 These tables are used to look up the basic shifts.
3801 They are indexed by cpu, shift_type, and mode. */
3802
3803 static const struct shift_insn shift_one[2][3][3] =
3804 {
3805 /* H8/300 */
3806 {
3807 /* SHIFT_ASHIFT */
3808 {
3809 { "shll\t%X0", CC_SET_ZNV },
3810 { "add.w\t%T0,%T0", CC_SET_ZN },
3811 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3812 },
3813 /* SHIFT_LSHIFTRT */
3814 {
3815 { "shlr\t%X0", CC_SET_ZNV },
3816 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3817 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3818 },
3819 /* SHIFT_ASHIFTRT */
3820 {
3821 { "shar\t%X0", CC_SET_ZNV },
3822 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3823 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3824 }
3825 },
3826 /* H8/300H */
3827 {
3828 /* SHIFT_ASHIFT */
3829 {
3830 { "shll.b\t%X0", CC_SET_ZNV },
3831 { "shll.w\t%T0", CC_SET_ZNV },
3832 { "shll.l\t%S0", CC_SET_ZNV }
3833 },
3834 /* SHIFT_LSHIFTRT */
3835 {
3836 { "shlr.b\t%X0", CC_SET_ZNV },
3837 { "shlr.w\t%T0", CC_SET_ZNV },
3838 { "shlr.l\t%S0", CC_SET_ZNV }
3839 },
3840 /* SHIFT_ASHIFTRT */
3841 {
3842 { "shar.b\t%X0", CC_SET_ZNV },
3843 { "shar.w\t%T0", CC_SET_ZNV },
3844 { "shar.l\t%S0", CC_SET_ZNV }
3845 }
3846 }
3847 };
3848
3849 static const struct shift_insn shift_two[3][3] =
3850 {
3851 /* SHIFT_ASHIFT */
3852 {
3853 { "shll.b\t#2,%X0", CC_SET_ZNV },
3854 { "shll.w\t#2,%T0", CC_SET_ZNV },
3855 { "shll.l\t#2,%S0", CC_SET_ZNV }
3856 },
3857 /* SHIFT_LSHIFTRT */
3858 {
3859 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3860 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3861 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3862 },
3863 /* SHIFT_ASHIFTRT */
3864 {
3865 { "shar.b\t#2,%X0", CC_SET_ZNV },
3866 { "shar.w\t#2,%T0", CC_SET_ZNV },
3867 { "shar.l\t#2,%S0", CC_SET_ZNV }
3868 }
3869 };
3870
3871 /* Rotates are organized by which shift they'll be used in implementing.
3872 There's no need to record whether the cc is valid afterwards because
3873 it is the AND insn that will decide this. */
3874
3875 static const char *const rotate_one[2][3][3] =
3876 {
3877 /* H8/300 */
3878 {
3879 /* SHIFT_ASHIFT */
3880 {
3881 "rotr\t%X0",
3882 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3883 0
3884 },
3885 /* SHIFT_LSHIFTRT */
3886 {
3887 "rotl\t%X0",
3888 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3889 0
3890 },
3891 /* SHIFT_ASHIFTRT */
3892 {
3893 "rotl\t%X0",
3894 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3895 0
3896 }
3897 },
3898 /* H8/300H */
3899 {
3900 /* SHIFT_ASHIFT */
3901 {
3902 "rotr.b\t%X0",
3903 "rotr.w\t%T0",
3904 "rotr.l\t%S0"
3905 },
3906 /* SHIFT_LSHIFTRT */
3907 {
3908 "rotl.b\t%X0",
3909 "rotl.w\t%T0",
3910 "rotl.l\t%S0"
3911 },
3912 /* SHIFT_ASHIFTRT */
3913 {
3914 "rotl.b\t%X0",
3915 "rotl.w\t%T0",
3916 "rotl.l\t%S0"
3917 }
3918 }
3919 };
3920
3921 static const char *const rotate_two[3][3] =
3922 {
3923 /* SHIFT_ASHIFT */
3924 {
3925 "rotr.b\t#2,%X0",
3926 "rotr.w\t#2,%T0",
3927 "rotr.l\t#2,%S0"
3928 },
3929 /* SHIFT_LSHIFTRT */
3930 {
3931 "rotl.b\t#2,%X0",
3932 "rotl.w\t#2,%T0",
3933 "rotl.l\t#2,%S0"
3934 },
3935 /* SHIFT_ASHIFTRT */
3936 {
3937 "rotl.b\t#2,%X0",
3938 "rotl.w\t#2,%T0",
3939 "rotl.l\t#2,%S0"
3940 }
3941 };
3942
3943 struct shift_info {
3944 /* Shift algorithm. */
3945 enum shift_alg alg;
3946
3947 /* The number of bits to be shifted by shift1 and shift2. Valid
3948 when ALG is SHIFT_SPECIAL. */
3949 unsigned int remainder;
3950
3951 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3952 const char *special;
3953
3954 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3955 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3956 const char *shift1;
3957
3958 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3959 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3960 const char *shift2;
3961
3962 /* CC status for SHIFT_INLINE. */
3963 enum attr_cc cc_inline;
3964
3965 /* CC status for SHIFT_SPECIAL. */
3966 enum attr_cc cc_special;
3967 };
3968
3969 static void get_shift_alg (enum shift_type,
3970 enum shift_mode, unsigned int,
3971 struct shift_info *);
3972
3973 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3974 best algorithm for doing the shift. The assembler code is stored
3975 in the pointers in INFO. We achieve the maximum efficiency in most
3976 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3977 SImode in particular have a lot of room to optimize.
3978
3979 We first determine the strategy of the shift algorithm by a table
3980 lookup. If that tells us to use a hand crafted assembly code, we
3981 go into the big switch statement to find what that is. Otherwise,
3982 we resort to a generic way, such as inlining. In either case, the
3983 result is returned through INFO. */
3984
3985 static void
3986 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
3987 unsigned int count, struct shift_info *info)
3988 {
3989 enum h8_cpu cpu;
3990
3991 /* Find the target CPU. */
3992 if (TARGET_H8300)
3993 cpu = H8_300;
3994 else if (TARGET_H8300H)
3995 cpu = H8_300H;
3996 else
3997 cpu = H8_S;
3998
3999 /* Find the shift algorithm. */
4000 info->alg = SHIFT_LOOP;
4001 switch (shift_mode)
4002 {
4003 case QIshift:
4004 if (count < GET_MODE_BITSIZE (QImode))
4005 info->alg = shift_alg_qi[cpu][shift_type][count];
4006 break;
4007
4008 case HIshift:
4009 if (count < GET_MODE_BITSIZE (HImode))
4010 info->alg = shift_alg_hi[cpu][shift_type][count];
4011 break;
4012
4013 case SIshift:
4014 if (count < GET_MODE_BITSIZE (SImode))
4015 info->alg = shift_alg_si[cpu][shift_type][count];
4016 break;
4017
4018 default:
4019 gcc_unreachable ();
4020 }
4021
4022 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4023 switch (info->alg)
4024 {
4025 case SHIFT_INLINE:
4026 info->remainder = count;
4027 /* Fall through. */
4028
4029 case SHIFT_LOOP:
4030 /* It is up to the caller to know that looping clobbers cc. */
4031 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4032 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4033 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4034 goto end;
4035
4036 case SHIFT_ROT_AND:
4037 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4038 info->shift2 = rotate_two[shift_type][shift_mode];
4039 info->cc_inline = CC_CLOBBER;
4040 goto end;
4041
4042 case SHIFT_SPECIAL:
4043 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4044 info->remainder = 0;
4045 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4046 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4047 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4048 info->cc_special = CC_CLOBBER;
4049 break;
4050 }
4051
4052 /* Here we only deal with SHIFT_SPECIAL. */
4053 switch (shift_mode)
4054 {
4055 case QIshift:
4056 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4057 through the entire value. */
4058 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4059 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4060 goto end;
4061
4062 case HIshift:
4063 if (count == 7)
4064 {
4065 switch (shift_type)
4066 {
4067 case SHIFT_ASHIFT:
4068 if (TARGET_H8300)
4069 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4070 else
4071 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4072 goto end;
4073 case SHIFT_LSHIFTRT:
4074 if (TARGET_H8300)
4075 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4076 else
4077 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4078 goto end;
4079 case SHIFT_ASHIFTRT:
4080 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4081 goto end;
4082 }
4083 }
4084 else if ((8 <= count && count <= 13)
4085 || (TARGET_H8300S && count == 14))
4086 {
4087 info->remainder = count - 8;
4088
4089 switch (shift_type)
4090 {
4091 case SHIFT_ASHIFT:
4092 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4093 goto end;
4094 case SHIFT_LSHIFTRT:
4095 if (TARGET_H8300)
4096 {
4097 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4098 info->shift1 = "shlr.b\t%s0";
4099 info->cc_inline = CC_SET_ZNV;
4100 }
4101 else
4102 {
4103 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4104 info->cc_special = CC_SET_ZNV;
4105 }
4106 goto end;
4107 case SHIFT_ASHIFTRT:
4108 if (TARGET_H8300)
4109 {
4110 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4111 info->shift1 = "shar.b\t%s0";
4112 }
4113 else
4114 {
4115 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4116 info->cc_special = CC_SET_ZNV;
4117 }
4118 goto end;
4119 }
4120 }
4121 else if (count == 14)
4122 {
4123 switch (shift_type)
4124 {
4125 case SHIFT_ASHIFT:
4126 if (TARGET_H8300)
4127 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4128 goto end;
4129 case SHIFT_LSHIFTRT:
4130 if (TARGET_H8300)
4131 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4132 goto end;
4133 case SHIFT_ASHIFTRT:
4134 if (TARGET_H8300)
4135 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4136 else if (TARGET_H8300H)
4137 {
4138 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4139 info->cc_special = CC_SET_ZNV;
4140 }
4141 else /* TARGET_H8300S */
4142 gcc_unreachable ();
4143 goto end;
4144 }
4145 }
4146 else if (count == 15)
4147 {
4148 switch (shift_type)
4149 {
4150 case SHIFT_ASHIFT:
4151 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4152 goto end;
4153 case SHIFT_LSHIFTRT:
4154 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4155 goto end;
4156 case SHIFT_ASHIFTRT:
4157 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4158 goto end;
4159 }
4160 }
4161 gcc_unreachable ();
4162
4163 case SIshift:
4164 if (TARGET_H8300 && 8 <= count && count <= 9)
4165 {
4166 info->remainder = count - 8;
4167
4168 switch (shift_type)
4169 {
4170 case SHIFT_ASHIFT:
4171 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4172 goto end;
4173 case SHIFT_LSHIFTRT:
4174 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4175 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4176 goto end;
4177 case SHIFT_ASHIFTRT:
4178 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4179 goto end;
4180 }
4181 }
4182 else if (count == 8 && !TARGET_H8300)
4183 {
4184 switch (shift_type)
4185 {
4186 case SHIFT_ASHIFT:
4187 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4188 goto end;
4189 case SHIFT_LSHIFTRT:
4190 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4191 goto end;
4192 case SHIFT_ASHIFTRT:
4193 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4194 goto end;
4195 }
4196 }
4197 else if (count == 15 && TARGET_H8300)
4198 {
4199 switch (shift_type)
4200 {
4201 case SHIFT_ASHIFT:
4202 gcc_unreachable ();
4203 case SHIFT_LSHIFTRT:
4204 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4205 goto end;
4206 case SHIFT_ASHIFTRT:
4207 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4208 goto end;
4209 }
4210 }
4211 else if (count == 15 && !TARGET_H8300)
4212 {
4213 switch (shift_type)
4214 {
4215 case SHIFT_ASHIFT:
4216 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4217 info->cc_special = CC_SET_ZNV;
4218 goto end;
4219 case SHIFT_LSHIFTRT:
4220 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4221 info->cc_special = CC_SET_ZNV;
4222 goto end;
4223 case SHIFT_ASHIFTRT:
4224 gcc_unreachable ();
4225 }
4226 }
4227 else if ((TARGET_H8300 && 16 <= count && count <= 20)
4228 || (TARGET_H8300H && 16 <= count && count <= 19)
4229 || (TARGET_H8300S && 16 <= count && count <= 21))
4230 {
4231 info->remainder = count - 16;
4232
4233 switch (shift_type)
4234 {
4235 case SHIFT_ASHIFT:
4236 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4237 if (TARGET_H8300)
4238 info->shift1 = "add.w\t%e0,%e0";
4239 goto end;
4240 case SHIFT_LSHIFTRT:
4241 if (TARGET_H8300)
4242 {
4243 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4244 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4245 }
4246 else
4247 {
4248 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4249 info->cc_special = CC_SET_ZNV;
4250 }
4251 goto end;
4252 case SHIFT_ASHIFTRT:
4253 if (TARGET_H8300)
4254 {
4255 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4256 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4257 }
4258 else
4259 {
4260 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4261 info->cc_special = CC_SET_ZNV;
4262 }
4263 goto end;
4264 }
4265 }
4266 else if (TARGET_H8300 && 24 <= count && count <= 28)
4267 {
4268 info->remainder = count - 24;
4269
4270 switch (shift_type)
4271 {
4272 case SHIFT_ASHIFT:
4273 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4274 info->shift1 = "shll.b\t%z0";
4275 info->cc_inline = CC_SET_ZNV;
4276 goto end;
4277 case SHIFT_LSHIFTRT:
4278 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4279 info->shift1 = "shlr.b\t%w0";
4280 info->cc_inline = CC_SET_ZNV;
4281 goto end;
4282 case SHIFT_ASHIFTRT:
4283 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4284 info->shift1 = "shar.b\t%w0";
4285 info->cc_inline = CC_SET_ZNV;
4286 goto end;
4287 }
4288 }
4289 else if ((TARGET_H8300H && count == 24)
4290 || (TARGET_H8300S && 24 <= count && count <= 25))
4291 {
4292 info->remainder = count - 24;
4293
4294 switch (shift_type)
4295 {
4296 case SHIFT_ASHIFT:
4297 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4298 goto end;
4299 case SHIFT_LSHIFTRT:
4300 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4301 info->cc_special = CC_SET_ZNV;
4302 goto end;
4303 case SHIFT_ASHIFTRT:
4304 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4305 info->cc_special = CC_SET_ZNV;
4306 goto end;
4307 }
4308 }
4309 else if (!TARGET_H8300 && count == 28)
4310 {
4311 switch (shift_type)
4312 {
4313 case SHIFT_ASHIFT:
4314 if (TARGET_H8300H)
4315 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4316 else
4317 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4318 goto end;
4319 case SHIFT_LSHIFTRT:
4320 if (TARGET_H8300H)
4321 {
4322 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4323 info->cc_special = CC_SET_ZNV;
4324 }
4325 else
4326 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4327 goto end;
4328 case SHIFT_ASHIFTRT:
4329 gcc_unreachable ();
4330 }
4331 }
4332 else if (!TARGET_H8300 && count == 29)
4333 {
4334 switch (shift_type)
4335 {
4336 case SHIFT_ASHIFT:
4337 if (TARGET_H8300H)
4338 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4339 else
4340 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4341 goto end;
4342 case SHIFT_LSHIFTRT:
4343 if (TARGET_H8300H)
4344 {
4345 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4346 info->cc_special = CC_SET_ZNV;
4347 }
4348 else
4349 {
4350 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4351 info->cc_special = CC_SET_ZNV;
4352 }
4353 goto end;
4354 case SHIFT_ASHIFTRT:
4355 gcc_unreachable ();
4356 }
4357 }
4358 else if (!TARGET_H8300 && count == 30)
4359 {
4360 switch (shift_type)
4361 {
4362 case SHIFT_ASHIFT:
4363 if (TARGET_H8300H)
4364 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4365 else
4366 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4367 goto end;
4368 case SHIFT_LSHIFTRT:
4369 if (TARGET_H8300H)
4370 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4371 else
4372 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4373 goto end;
4374 case SHIFT_ASHIFTRT:
4375 gcc_unreachable ();
4376 }
4377 }
4378 else if (count == 31)
4379 {
4380 if (TARGET_H8300)
4381 {
4382 switch (shift_type)
4383 {
4384 case SHIFT_ASHIFT:
4385 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4386 goto end;
4387 case SHIFT_LSHIFTRT:
4388 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4389 goto end;
4390 case SHIFT_ASHIFTRT:
4391 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4392 goto end;
4393 }
4394 }
4395 else
4396 {
4397 switch (shift_type)
4398 {
4399 case SHIFT_ASHIFT:
4400 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4401 info->cc_special = CC_SET_ZNV;
4402 goto end;
4403 case SHIFT_LSHIFTRT:
4404 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4405 info->cc_special = CC_SET_ZNV;
4406 goto end;
4407 case SHIFT_ASHIFTRT:
4408 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4409 info->cc_special = CC_SET_ZNV;
4410 goto end;
4411 }
4412 }
4413 }
4414 gcc_unreachable ();
4415
4416 default:
4417 gcc_unreachable ();
4418 }
4419
4420 end:
4421 if (!TARGET_H8300S)
4422 info->shift2 = NULL;
4423 }
4424
4425 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4426 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4427
4428 int
4429 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
4430 {
4431 enum h8_cpu cpu;
4432 int a, lr, ar;
4433
4434 if (GET_MODE_BITSIZE (mode) <= count)
4435 return 1;
4436
4437 /* Find out the target CPU. */
4438 if (TARGET_H8300)
4439 cpu = H8_300;
4440 else if (TARGET_H8300H)
4441 cpu = H8_300H;
4442 else
4443 cpu = H8_S;
4444
4445 /* Find the shift algorithm. */
4446 switch (mode)
4447 {
4448 case QImode:
4449 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4450 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4451 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4452 break;
4453
4454 case HImode:
4455 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4456 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4457 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4458 break;
4459
4460 case SImode:
4461 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4462 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4463 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4464 break;
4465
4466 default:
4467 gcc_unreachable ();
4468 }
4469
4470 /* On H8/300H, count == 8 uses a scratch register. */
4471 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4472 || (TARGET_H8300H && mode == SImode && count == 8));
4473 }
4474
4475 /* Output the assembler code for doing shifts. */
4476
4477 const char *
4478 output_a_shift (rtx *operands)
4479 {
4480 static int loopend_lab;
4481 rtx shift = operands[3];
4482 enum machine_mode mode = GET_MODE (shift);
4483 enum rtx_code code = GET_CODE (shift);
4484 enum shift_type shift_type;
4485 enum shift_mode shift_mode;
4486 struct shift_info info;
4487 int n;
4488
4489 loopend_lab++;
4490
4491 switch (mode)
4492 {
4493 case QImode:
4494 shift_mode = QIshift;
4495 break;
4496 case HImode:
4497 shift_mode = HIshift;
4498 break;
4499 case SImode:
4500 shift_mode = SIshift;
4501 break;
4502 default:
4503 gcc_unreachable ();
4504 }
4505
4506 switch (code)
4507 {
4508 case ASHIFTRT:
4509 shift_type = SHIFT_ASHIFTRT;
4510 break;
4511 case LSHIFTRT:
4512 shift_type = SHIFT_LSHIFTRT;
4513 break;
4514 case ASHIFT:
4515 shift_type = SHIFT_ASHIFT;
4516 break;
4517 default:
4518 gcc_unreachable ();
4519 }
4520
4521 /* This case must be taken care of by one of the two splitters
4522 that convert a variable shift into a loop. */
4523 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4524
4525 n = INTVAL (operands[2]);
4526
4527 /* If the count is negative, make it 0. */
4528 if (n < 0)
4529 n = 0;
4530 /* If the count is too big, truncate it.
4531 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4532 do the intuitive thing. */
4533 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4534 n = GET_MODE_BITSIZE (mode);
4535
4536 get_shift_alg (shift_type, shift_mode, n, &info);
4537
4538 switch (info.alg)
4539 {
4540 case SHIFT_SPECIAL:
4541 output_asm_insn (info.special, operands);
4542 /* Fall through. */
4543
4544 case SHIFT_INLINE:
4545 n = info.remainder;
4546
4547 /* Emit two bit shifts first. */
4548 if (info.shift2 != NULL)
4549 {
4550 for (; n > 1; n -= 2)
4551 output_asm_insn (info.shift2, operands);
4552 }
4553
4554 /* Now emit one bit shifts for any residual. */
4555 for (; n > 0; n--)
4556 output_asm_insn (info.shift1, operands);
4557 return "";
4558
4559 case SHIFT_ROT_AND:
4560 {
4561 int m = GET_MODE_BITSIZE (mode) - n;
4562 const int mask = (shift_type == SHIFT_ASHIFT
4563 ? ((1 << m) - 1) << n
4564 : (1 << m) - 1);
4565 char insn_buf[200];
4566
4567 /* Not all possibilities of rotate are supported. They shouldn't
4568 be generated, but let's watch for 'em. */
4569 gcc_assert (info.shift1);
4570
4571 /* Emit two bit rotates first. */
4572 if (info.shift2 != NULL)
4573 {
4574 for (; m > 1; m -= 2)
4575 output_asm_insn (info.shift2, operands);
4576 }
4577
4578 /* Now single bit rotates for any residual. */
4579 for (; m > 0; m--)
4580 output_asm_insn (info.shift1, operands);
4581
4582 /* Now mask off the high bits. */
4583 switch (mode)
4584 {
4585 case QImode:
4586 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4587 break;
4588
4589 case HImode:
4590 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4591 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4592 break;
4593
4594 default:
4595 gcc_unreachable ();
4596 }
4597
4598 output_asm_insn (insn_buf, operands);
4599 return "";
4600 }
4601
4602 case SHIFT_LOOP:
4603 /* A loop to shift by a "large" constant value.
4604 If we have shift-by-2 insns, use them. */
4605 if (info.shift2 != NULL)
4606 {
4607 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4608 names_big[REGNO (operands[4])]);
4609 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4610 output_asm_insn (info.shift2, operands);
4611 output_asm_insn ("add #0xff,%X4", operands);
4612 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4613 if (n % 2)
4614 output_asm_insn (info.shift1, operands);
4615 }
4616 else
4617 {
4618 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4619 names_big[REGNO (operands[4])]);
4620 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4621 output_asm_insn (info.shift1, operands);
4622 output_asm_insn ("add #0xff,%X4", operands);
4623 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4624 }
4625 return "";
4626
4627 default:
4628 gcc_unreachable ();
4629 }
4630 }
4631
4632 /* Count the number of assembly instructions in a string TEMPL. */
4633
4634 static unsigned int
4635 h8300_asm_insn_count (const char *templ)
4636 {
4637 unsigned int count = 1;
4638
4639 for (; *templ; templ++)
4640 if (*templ == '\n')
4641 count++;
4642
4643 return count;
4644 }
4645
4646 /* Compute the length of a shift insn. */
4647
4648 unsigned int
4649 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4650 {
4651 rtx shift = operands[3];
4652 enum machine_mode mode = GET_MODE (shift);
4653 enum rtx_code code = GET_CODE (shift);
4654 enum shift_type shift_type;
4655 enum shift_mode shift_mode;
4656 struct shift_info info;
4657 unsigned int wlength = 0;
4658
4659 switch (mode)
4660 {
4661 case QImode:
4662 shift_mode = QIshift;
4663 break;
4664 case HImode:
4665 shift_mode = HIshift;
4666 break;
4667 case SImode:
4668 shift_mode = SIshift;
4669 break;
4670 default:
4671 gcc_unreachable ();
4672 }
4673
4674 switch (code)
4675 {
4676 case ASHIFTRT:
4677 shift_type = SHIFT_ASHIFTRT;
4678 break;
4679 case LSHIFTRT:
4680 shift_type = SHIFT_LSHIFTRT;
4681 break;
4682 case ASHIFT:
4683 shift_type = SHIFT_ASHIFT;
4684 break;
4685 default:
4686 gcc_unreachable ();
4687 }
4688
4689 if (GET_CODE (operands[2]) != CONST_INT)
4690 {
4691 /* Get the assembler code to do one shift. */
4692 get_shift_alg (shift_type, shift_mode, 1, &info);
4693
4694 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4695 }
4696 else
4697 {
4698 int n = INTVAL (operands[2]);
4699
4700 /* If the count is negative, make it 0. */
4701 if (n < 0)
4702 n = 0;
4703 /* If the count is too big, truncate it.
4704 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4705 do the intuitive thing. */
4706 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4707 n = GET_MODE_BITSIZE (mode);
4708
4709 get_shift_alg (shift_type, shift_mode, n, &info);
4710
4711 switch (info.alg)
4712 {
4713 case SHIFT_SPECIAL:
4714 wlength += h8300_asm_insn_count (info.special);
4715
4716 /* Every assembly instruction used in SHIFT_SPECIAL case
4717 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4718 see xor.l, we just pretend that xor.l counts as two insns
4719 so that the insn length will be computed correctly. */
4720 if (strstr (info.special, "xor.l") != NULL)
4721 wlength++;
4722
4723 /* Fall through. */
4724
4725 case SHIFT_INLINE:
4726 n = info.remainder;
4727
4728 if (info.shift2 != NULL)
4729 {
4730 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4731 n = n % 2;
4732 }
4733
4734 wlength += h8300_asm_insn_count (info.shift1) * n;
4735
4736 return 2 * wlength;
4737
4738 case SHIFT_ROT_AND:
4739 {
4740 int m = GET_MODE_BITSIZE (mode) - n;
4741
4742 /* Not all possibilities of rotate are supported. They shouldn't
4743 be generated, but let's watch for 'em. */
4744 gcc_assert (info.shift1);
4745
4746 if (info.shift2 != NULL)
4747 {
4748 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4749 m = m % 2;
4750 }
4751
4752 wlength += h8300_asm_insn_count (info.shift1) * m;
4753
4754 /* Now mask off the high bits. */
4755 switch (mode)
4756 {
4757 case QImode:
4758 wlength += 1;
4759 break;
4760 case HImode:
4761 wlength += 2;
4762 break;
4763 case SImode:
4764 gcc_assert (!TARGET_H8300);
4765 wlength += 3;
4766 break;
4767 default:
4768 gcc_unreachable ();
4769 }
4770 return 2 * wlength;
4771 }
4772
4773 case SHIFT_LOOP:
4774 /* A loop to shift by a "large" constant value.
4775 If we have shift-by-2 insns, use them. */
4776 if (info.shift2 != NULL)
4777 {
4778 wlength += 3 + h8300_asm_insn_count (info.shift2);
4779 if (n % 2)
4780 wlength += h8300_asm_insn_count (info.shift1);
4781 }
4782 else
4783 {
4784 wlength += 3 + h8300_asm_insn_count (info.shift1);
4785 }
4786 return 2 * wlength;
4787
4788 default:
4789 gcc_unreachable ();
4790 }
4791 }
4792 }
4793
4794 /* Compute which flag bits are valid after a shift insn. */
4795
4796 enum attr_cc
4797 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4798 {
4799 rtx shift = operands[3];
4800 enum machine_mode mode = GET_MODE (shift);
4801 enum rtx_code code = GET_CODE (shift);
4802 enum shift_type shift_type;
4803 enum shift_mode shift_mode;
4804 struct shift_info info;
4805 int n;
4806
4807 switch (mode)
4808 {
4809 case QImode:
4810 shift_mode = QIshift;
4811 break;
4812 case HImode:
4813 shift_mode = HIshift;
4814 break;
4815 case SImode:
4816 shift_mode = SIshift;
4817 break;
4818 default:
4819 gcc_unreachable ();
4820 }
4821
4822 switch (code)
4823 {
4824 case ASHIFTRT:
4825 shift_type = SHIFT_ASHIFTRT;
4826 break;
4827 case LSHIFTRT:
4828 shift_type = SHIFT_LSHIFTRT;
4829 break;
4830 case ASHIFT:
4831 shift_type = SHIFT_ASHIFT;
4832 break;
4833 default:
4834 gcc_unreachable ();
4835 }
4836
4837 /* This case must be taken care of by one of the two splitters
4838 that convert a variable shift into a loop. */
4839 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4840
4841 n = INTVAL (operands[2]);
4842
4843 /* If the count is negative, make it 0. */
4844 if (n < 0)
4845 n = 0;
4846 /* If the count is too big, truncate it.
4847 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4848 do the intuitive thing. */
4849 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4850 n = GET_MODE_BITSIZE (mode);
4851
4852 get_shift_alg (shift_type, shift_mode, n, &info);
4853
4854 switch (info.alg)
4855 {
4856 case SHIFT_SPECIAL:
4857 if (info.remainder == 0)
4858 return info.cc_special;
4859
4860 /* Fall through. */
4861
4862 case SHIFT_INLINE:
4863 return info.cc_inline;
4864
4865 case SHIFT_ROT_AND:
4866 /* This case always ends with an and instruction. */
4867 return CC_SET_ZNV;
4868
4869 case SHIFT_LOOP:
4870 /* A loop to shift by a "large" constant value.
4871 If we have shift-by-2 insns, use them. */
4872 if (info.shift2 != NULL)
4873 {
4874 if (n % 2)
4875 return info.cc_inline;
4876 }
4877 return CC_CLOBBER;
4878
4879 default:
4880 gcc_unreachable ();
4881 }
4882 }
4883 \f
4884 /* A rotation by a non-constant will cause a loop to be generated, in
4885 which a rotation by one bit is used. A rotation by a constant,
4886 including the one in the loop, will be taken care of by
4887 output_a_rotate () at the insn emit time. */
4888
4889 int
4890 expand_a_rotate (rtx operands[])
4891 {
4892 rtx dst = operands[0];
4893 rtx src = operands[1];
4894 rtx rotate_amount = operands[2];
4895 enum machine_mode mode = GET_MODE (dst);
4896
4897 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4898 return false;
4899
4900 /* We rotate in place. */
4901 emit_move_insn (dst, src);
4902
4903 if (GET_CODE (rotate_amount) != CONST_INT)
4904 {
4905 rtx counter = gen_reg_rtx (QImode);
4906 rtx start_label = gen_label_rtx ();
4907 rtx end_label = gen_label_rtx ();
4908
4909 /* If the rotate amount is less than or equal to 0,
4910 we go out of the loop. */
4911 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4912 QImode, 0, end_label);
4913
4914 /* Initialize the loop counter. */
4915 emit_move_insn (counter, rotate_amount);
4916
4917 emit_label (start_label);
4918
4919 /* Rotate by one bit. */
4920 switch (mode)
4921 {
4922 case QImode:
4923 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4924 break;
4925 case HImode:
4926 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4927 break;
4928 case SImode:
4929 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
4930 break;
4931 default:
4932 gcc_unreachable ();
4933 }
4934
4935 /* Decrement the counter by 1. */
4936 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
4937
4938 /* If the loop counter is nonzero, we go back to the beginning
4939 of the loop. */
4940 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
4941 start_label);
4942
4943 emit_label (end_label);
4944 }
4945 else
4946 {
4947 /* Rotate by AMOUNT bits. */
4948 switch (mode)
4949 {
4950 case QImode:
4951 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
4952 break;
4953 case HImode:
4954 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
4955 break;
4956 case SImode:
4957 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
4958 break;
4959 default:
4960 gcc_unreachable ();
4961 }
4962 }
4963
4964 return 1;
4965 }
4966
4967 /* Output a rotate insn. */
4968
4969 const char *
4970 output_a_rotate (enum rtx_code code, rtx *operands)
4971 {
4972 rtx dst = operands[0];
4973 rtx rotate_amount = operands[2];
4974 enum shift_mode rotate_mode;
4975 enum shift_type rotate_type;
4976 const char *insn_buf;
4977 int bits;
4978 int amount;
4979 enum machine_mode mode = GET_MODE (dst);
4980
4981 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
4982
4983 switch (mode)
4984 {
4985 case QImode:
4986 rotate_mode = QIshift;
4987 break;
4988 case HImode:
4989 rotate_mode = HIshift;
4990 break;
4991 case SImode:
4992 rotate_mode = SIshift;
4993 break;
4994 default:
4995 gcc_unreachable ();
4996 }
4997
4998 switch (code)
4999 {
5000 case ROTATERT:
5001 rotate_type = SHIFT_ASHIFT;
5002 break;
5003 case ROTATE:
5004 rotate_type = SHIFT_LSHIFTRT;
5005 break;
5006 default:
5007 gcc_unreachable ();
5008 }
5009
5010 amount = INTVAL (rotate_amount);
5011
5012 /* Clean up AMOUNT. */
5013 if (amount < 0)
5014 amount = 0;
5015 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5016 amount = GET_MODE_BITSIZE (mode);
5017
5018 /* Determine the faster direction. After this phase, amount will be
5019 at most a half of GET_MODE_BITSIZE (mode). */
5020 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5021 {
5022 /* Flip the direction. */
5023 amount = GET_MODE_BITSIZE (mode) - amount;
5024 rotate_type =
5025 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5026 }
5027
5028 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5029 boost up the rotation. */
5030 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5031 || (mode == HImode && TARGET_H8300H && amount >= 6)
5032 || (mode == HImode && TARGET_H8300S && amount == 8)
5033 || (mode == SImode && TARGET_H8300H && amount >= 10)
5034 || (mode == SImode && TARGET_H8300S && amount >= 13))
5035 {
5036 switch (mode)
5037 {
5038 case HImode:
5039 /* This code works on any family. */
5040 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5041 output_asm_insn (insn_buf, operands);
5042 break;
5043
5044 case SImode:
5045 /* This code works on the H8/300H and H8S. */
5046 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5047 output_asm_insn (insn_buf, operands);
5048 break;
5049
5050 default:
5051 gcc_unreachable ();
5052 }
5053
5054 /* Adjust AMOUNT and flip the direction. */
5055 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5056 rotate_type =
5057 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5058 }
5059
5060 /* Output rotate insns. */
5061 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5062 {
5063 if (bits == 2)
5064 insn_buf = rotate_two[rotate_type][rotate_mode];
5065 else
5066 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5067
5068 for (; amount >= bits; amount -= bits)
5069 output_asm_insn (insn_buf, operands);
5070 }
5071
5072 return "";
5073 }
5074
5075 /* Compute the length of a rotate insn. */
5076
5077 unsigned int
5078 compute_a_rotate_length (rtx *operands)
5079 {
5080 rtx src = operands[1];
5081 rtx amount_rtx = operands[2];
5082 enum machine_mode mode = GET_MODE (src);
5083 int amount;
5084 unsigned int length = 0;
5085
5086 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5087
5088 amount = INTVAL (amount_rtx);
5089
5090 /* Clean up AMOUNT. */
5091 if (amount < 0)
5092 amount = 0;
5093 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5094 amount = GET_MODE_BITSIZE (mode);
5095
5096 /* Determine the faster direction. After this phase, amount
5097 will be at most a half of GET_MODE_BITSIZE (mode). */
5098 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5099 /* Flip the direction. */
5100 amount = GET_MODE_BITSIZE (mode) - amount;
5101
5102 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5103 boost up the rotation. */
5104 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5105 || (mode == HImode && TARGET_H8300H && amount >= 6)
5106 || (mode == HImode && TARGET_H8300S && amount == 8)
5107 || (mode == SImode && TARGET_H8300H && amount >= 10)
5108 || (mode == SImode && TARGET_H8300S && amount >= 13))
5109 {
5110 /* Adjust AMOUNT and flip the direction. */
5111 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5112 length += 6;
5113 }
5114
5115 /* We use 2-bit rotations on the H8S. */
5116 if (TARGET_H8300S)
5117 amount = amount / 2 + amount % 2;
5118
5119 /* The H8/300 uses three insns to rotate one bit, taking 6
5120 length. */
5121 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5122
5123 return length;
5124 }
5125 \f
5126 /* Fix the operands of a gen_xxx so that it could become a bit
5127 operating insn. */
5128
5129 int
5130 fix_bit_operand (rtx *operands, enum rtx_code code)
5131 {
5132 /* The bit_operand predicate accepts any memory during RTL generation, but
5133 only 'U' memory afterwards, so if this is a MEM operand, we must force
5134 it to be valid for 'U' by reloading the address. */
5135
5136 if (code == AND
5137 ? single_zero_operand (operands[2], QImode)
5138 : single_one_operand (operands[2], QImode))
5139 {
5140 /* OK to have a memory dest. */
5141 if (GET_CODE (operands[0]) == MEM
5142 && !satisfies_constraint_U (operands[0]))
5143 {
5144 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5145 copy_to_mode_reg (Pmode,
5146 XEXP (operands[0], 0)));
5147 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5148 operands[0] = mem;
5149 }
5150
5151 if (GET_CODE (operands[1]) == MEM
5152 && !satisfies_constraint_U (operands[1]))
5153 {
5154 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5155 copy_to_mode_reg (Pmode,
5156 XEXP (operands[1], 0)));
5157 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5158 operands[1] = mem;
5159 }
5160 return 0;
5161 }
5162
5163 /* Dest and src op must be register. */
5164
5165 operands[1] = force_reg (QImode, operands[1]);
5166 {
5167 rtx res = gen_reg_rtx (QImode);
5168 switch (code)
5169 {
5170 case AND:
5171 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5172 break;
5173 case IOR:
5174 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5175 break;
5176 case XOR:
5177 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5178 break;
5179 default:
5180 gcc_unreachable ();
5181 }
5182 emit_insn (gen_movqi (operands[0], res));
5183 }
5184 return 1;
5185 }
5186
5187 /* Return nonzero if FUNC is an interrupt function as specified
5188 by the "interrupt" attribute. */
5189
5190 static int
5191 h8300_interrupt_function_p (tree func)
5192 {
5193 tree a;
5194
5195 if (TREE_CODE (func) != FUNCTION_DECL)
5196 return 0;
5197
5198 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5199 return a != NULL_TREE;
5200 }
5201
5202 /* Return nonzero if FUNC is a saveall function as specified by the
5203 "saveall" attribute. */
5204
5205 static int
5206 h8300_saveall_function_p (tree func)
5207 {
5208 tree a;
5209
5210 if (TREE_CODE (func) != FUNCTION_DECL)
5211 return 0;
5212
5213 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5214 return a != NULL_TREE;
5215 }
5216
5217 /* Return nonzero if FUNC is an OS_Task function as specified
5218 by the "OS_Task" attribute. */
5219
5220 static int
5221 h8300_os_task_function_p (tree func)
5222 {
5223 tree a;
5224
5225 if (TREE_CODE (func) != FUNCTION_DECL)
5226 return 0;
5227
5228 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5229 return a != NULL_TREE;
5230 }
5231
5232 /* Return nonzero if FUNC is a monitor function as specified
5233 by the "monitor" attribute. */
5234
5235 static int
5236 h8300_monitor_function_p (tree func)
5237 {
5238 tree a;
5239
5240 if (TREE_CODE (func) != FUNCTION_DECL)
5241 return 0;
5242
5243 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5244 return a != NULL_TREE;
5245 }
5246
5247 /* Return nonzero if FUNC is a function that should be called
5248 through the function vector. */
5249
5250 int
5251 h8300_funcvec_function_p (tree func)
5252 {
5253 tree a;
5254
5255 if (TREE_CODE (func) != FUNCTION_DECL)
5256 return 0;
5257
5258 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5259 return a != NULL_TREE;
5260 }
5261
5262 /* Return nonzero if DECL is a variable that's in the eight bit
5263 data area. */
5264
5265 int
5266 h8300_eightbit_data_p (tree decl)
5267 {
5268 tree a;
5269
5270 if (TREE_CODE (decl) != VAR_DECL)
5271 return 0;
5272
5273 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5274 return a != NULL_TREE;
5275 }
5276
5277 /* Return nonzero if DECL is a variable that's in the tiny
5278 data area. */
5279
5280 int
5281 h8300_tiny_data_p (tree decl)
5282 {
5283 tree a;
5284
5285 if (TREE_CODE (decl) != VAR_DECL)
5286 return 0;
5287
5288 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5289 return a != NULL_TREE;
5290 }
5291
5292 /* Generate an 'interrupt_handler' attribute for decls. We convert
5293 all the pragmas to corresponding attributes. */
5294
5295 static void
5296 h8300_insert_attributes (tree node, tree *attributes)
5297 {
5298 if (TREE_CODE (node) == FUNCTION_DECL)
5299 {
5300 if (pragma_interrupt)
5301 {
5302 pragma_interrupt = 0;
5303
5304 /* Add an 'interrupt_handler' attribute. */
5305 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5306 NULL, *attributes);
5307 }
5308
5309 if (pragma_saveall)
5310 {
5311 pragma_saveall = 0;
5312
5313 /* Add an 'saveall' attribute. */
5314 *attributes = tree_cons (get_identifier ("saveall"),
5315 NULL, *attributes);
5316 }
5317 }
5318 }
5319
5320 /* Supported attributes:
5321
5322 interrupt_handler: output a prologue and epilogue suitable for an
5323 interrupt handler.
5324
5325 saveall: output a prologue and epilogue that saves and restores
5326 all registers except the stack pointer.
5327
5328 function_vector: This function should be called through the
5329 function vector.
5330
5331 eightbit_data: This variable lives in the 8-bit data area and can
5332 be referenced with 8-bit absolute memory addresses.
5333
5334 tiny_data: This variable lives in the tiny data area and can be
5335 referenced with 16-bit absolute memory references. */
5336
5337 static const struct attribute_spec h8300_attribute_table[] =
5338 {
5339 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5340 affects_type_identity } */
5341 { "interrupt_handler", 0, 0, true, false, false,
5342 h8300_handle_fndecl_attribute, false },
5343 { "saveall", 0, 0, true, false, false,
5344 h8300_handle_fndecl_attribute, false },
5345 { "OS_Task", 0, 0, true, false, false,
5346 h8300_handle_fndecl_attribute, false },
5347 { "monitor", 0, 0, true, false, false,
5348 h8300_handle_fndecl_attribute, false },
5349 { "function_vector", 0, 0, true, false, false,
5350 h8300_handle_fndecl_attribute, false },
5351 { "eightbit_data", 0, 0, true, false, false,
5352 h8300_handle_eightbit_data_attribute, false },
5353 { "tiny_data", 0, 0, true, false, false,
5354 h8300_handle_tiny_data_attribute, false },
5355 { NULL, 0, 0, false, false, false, NULL, false }
5356 };
5357
5358
5359 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5360 struct attribute_spec.handler. */
5361 static tree
5362 h8300_handle_fndecl_attribute (tree *node, tree name,
5363 tree args ATTRIBUTE_UNUSED,
5364 int flags ATTRIBUTE_UNUSED,
5365 bool *no_add_attrs)
5366 {
5367 if (TREE_CODE (*node) != FUNCTION_DECL)
5368 {
5369 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5370 name);
5371 *no_add_attrs = true;
5372 }
5373
5374 return NULL_TREE;
5375 }
5376
5377 /* Handle an "eightbit_data" attribute; arguments as in
5378 struct attribute_spec.handler. */
5379 static tree
5380 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5381 tree args ATTRIBUTE_UNUSED,
5382 int flags ATTRIBUTE_UNUSED,
5383 bool *no_add_attrs)
5384 {
5385 tree decl = *node;
5386
5387 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5388 {
5389 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
5390 }
5391 else
5392 {
5393 warning (OPT_Wattributes, "%qE attribute ignored",
5394 name);
5395 *no_add_attrs = true;
5396 }
5397
5398 return NULL_TREE;
5399 }
5400
5401 /* Handle an "tiny_data" attribute; arguments as in
5402 struct attribute_spec.handler. */
5403 static tree
5404 h8300_handle_tiny_data_attribute (tree *node, tree name,
5405 tree args ATTRIBUTE_UNUSED,
5406 int flags ATTRIBUTE_UNUSED,
5407 bool *no_add_attrs)
5408 {
5409 tree decl = *node;
5410
5411 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5412 {
5413 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
5414 }
5415 else
5416 {
5417 warning (OPT_Wattributes, "%qE attribute ignored",
5418 name);
5419 *no_add_attrs = true;
5420 }
5421
5422 return NULL_TREE;
5423 }
5424
5425 /* Mark function vectors, and various small data objects. */
5426
5427 static void
5428 h8300_encode_section_info (tree decl, rtx rtl, int first)
5429 {
5430 int extra_flags = 0;
5431
5432 default_encode_section_info (decl, rtl, first);
5433
5434 if (TREE_CODE (decl) == FUNCTION_DECL
5435 && h8300_funcvec_function_p (decl))
5436 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5437 else if (TREE_CODE (decl) == VAR_DECL
5438 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5439 {
5440 if (h8300_eightbit_data_p (decl))
5441 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5442 else if (first && h8300_tiny_data_p (decl))
5443 extra_flags = SYMBOL_FLAG_TINY_DATA;
5444 }
5445
5446 if (extra_flags)
5447 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5448 }
5449
5450 /* Output a single-bit extraction. */
5451
5452 const char *
5453 output_simode_bld (int bild, rtx operands[])
5454 {
5455 if (TARGET_H8300)
5456 {
5457 /* Clear the destination register. */
5458 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5459
5460 /* Now output the bit load or bit inverse load, and store it in
5461 the destination. */
5462 if (bild)
5463 output_asm_insn ("bild\t%Z2,%Y1", operands);
5464 else
5465 output_asm_insn ("bld\t%Z2,%Y1", operands);
5466
5467 output_asm_insn ("bst\t#0,%w0", operands);
5468 }
5469 else
5470 {
5471 /* Determine if we can clear the destination first. */
5472 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5473 && REGNO (operands[0]) != REGNO (operands[1]));
5474
5475 if (clear_first)
5476 output_asm_insn ("sub.l\t%S0,%S0", operands);
5477
5478 /* Output the bit load or bit inverse load. */
5479 if (bild)
5480 output_asm_insn ("bild\t%Z2,%Y1", operands);
5481 else
5482 output_asm_insn ("bld\t%Z2,%Y1", operands);
5483
5484 if (!clear_first)
5485 output_asm_insn ("xor.l\t%S0,%S0", operands);
5486
5487 /* Perform the bit store. */
5488 output_asm_insn ("rotxl.l\t%S0", operands);
5489 }
5490
5491 /* All done. */
5492 return "";
5493 }
5494
5495 /* Delayed-branch scheduling is more effective if we have some idea
5496 how long each instruction will be. Use a shorten_branches pass
5497 to get an initial estimate. */
5498
5499 static void
5500 h8300_reorg (void)
5501 {
5502 if (flag_delayed_branch)
5503 shorten_branches (get_insns ());
5504 }
5505
5506 #ifndef OBJECT_FORMAT_ELF
5507 static void
5508 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5509 tree decl)
5510 {
5511 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5512 fprintf (asm_out_file, "\t.section %s\n", name);
5513 }
5514 #endif /* ! OBJECT_FORMAT_ELF */
5515
5516 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5517 which is a special case of the 'R' operand. */
5518
5519 int
5520 h8300_eightbit_constant_address_p (rtx x)
5521 {
5522 /* The ranges of the 8-bit area. */
5523 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5524 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5525 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5526 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5527 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5528 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5529
5530 unsigned HOST_WIDE_INT addr;
5531
5532 /* We accept symbols declared with eightbit_data. */
5533 if (GET_CODE (x) == SYMBOL_REF)
5534 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5535
5536 if (GET_CODE (x) != CONST_INT)
5537 return 0;
5538
5539 addr = INTVAL (x);
5540
5541 return (0
5542 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5543 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5544 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5545 }
5546
5547 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5548 on H8/300H and H8S. */
5549
5550 int
5551 h8300_tiny_constant_address_p (rtx x)
5552 {
5553 /* The ranges of the 16-bit area. */
5554 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5555 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5556 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5557 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5558 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5559 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5560 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5561 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5562
5563 unsigned HOST_WIDE_INT addr;
5564
5565 switch (GET_CODE (x))
5566 {
5567 case SYMBOL_REF:
5568 /* In the normal mode, any symbol fits in the 16-bit absolute
5569 address range. We also accept symbols declared with
5570 tiny_data. */
5571 return (TARGET_NORMAL_MODE
5572 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5573
5574 case CONST_INT:
5575 addr = INTVAL (x);
5576 return (TARGET_NORMAL_MODE
5577 || (TARGET_H8300H
5578 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5579 || (TARGET_H8300S
5580 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5581
5582 case CONST:
5583 return TARGET_NORMAL_MODE;
5584
5585 default:
5586 return 0;
5587 }
5588
5589 }
5590
5591 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5592 locations that can be accessed as a 16-bit word. */
5593
5594 int
5595 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5596 {
5597 HOST_WIDE_INT offset1, offset2;
5598 rtx reg1, reg2;
5599
5600 if (REG_P (addr1))
5601 {
5602 reg1 = addr1;
5603 offset1 = 0;
5604 }
5605 else if (GET_CODE (addr1) == PLUS
5606 && REG_P (XEXP (addr1, 0))
5607 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5608 {
5609 reg1 = XEXP (addr1, 0);
5610 offset1 = INTVAL (XEXP (addr1, 1));
5611 }
5612 else
5613 return 0;
5614
5615 if (REG_P (addr2))
5616 {
5617 reg2 = addr2;
5618 offset2 = 0;
5619 }
5620 else if (GET_CODE (addr2) == PLUS
5621 && REG_P (XEXP (addr2, 0))
5622 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5623 {
5624 reg2 = XEXP (addr2, 0);
5625 offset2 = INTVAL (XEXP (addr2, 1));
5626 }
5627 else
5628 return 0;
5629
5630 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5631 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5632 && offset1 % 2 == 0
5633 && offset1 + 1 == offset2)
5634 return 1;
5635
5636 return 0;
5637 }
5638
5639 /* Return nonzero if we have the same comparison insn as I3 two insns
5640 before I3. I3 is assumed to be a comparison insn. */
5641
5642 int
5643 same_cmp_preceding_p (rtx i3)
5644 {
5645 rtx i1, i2;
5646
5647 /* Make sure we have a sequence of three insns. */
5648 i2 = prev_nonnote_insn (i3);
5649 if (i2 == NULL_RTX)
5650 return 0;
5651 i1 = prev_nonnote_insn (i2);
5652 if (i1 == NULL_RTX)
5653 return 0;
5654
5655 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5656 && any_condjump_p (i2) && onlyjump_p (i2));
5657 }
5658
5659 /* Return nonzero if we have the same comparison insn as I1 two insns
5660 after I1. I1 is assumed to be a comparison insn. */
5661
5662 int
5663 same_cmp_following_p (rtx i1)
5664 {
5665 rtx i2, i3;
5666
5667 /* Make sure we have a sequence of three insns. */
5668 i2 = next_nonnote_insn (i1);
5669 if (i2 == NULL_RTX)
5670 return 0;
5671 i3 = next_nonnote_insn (i2);
5672 if (i3 == NULL_RTX)
5673 return 0;
5674
5675 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5676 && any_condjump_p (i2) && onlyjump_p (i2));
5677 }
5678
5679 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5680 (or pops) N registers. OPERANDS are assumed to be an array of
5681 registers. */
5682
5683 int
5684 h8300_regs_ok_for_stm (int n, rtx operands[])
5685 {
5686 switch (n)
5687 {
5688 case 2:
5689 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5690 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5691 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5692 case 3:
5693 return ((REGNO (operands[0]) == 0
5694 && REGNO (operands[1]) == 1
5695 && REGNO (operands[2]) == 2)
5696 || (REGNO (operands[0]) == 4
5697 && REGNO (operands[1]) == 5
5698 && REGNO (operands[2]) == 6));
5699
5700 case 4:
5701 return (REGNO (operands[0]) == 0
5702 && REGNO (operands[1]) == 1
5703 && REGNO (operands[2]) == 2
5704 && REGNO (operands[3]) == 3);
5705 default:
5706 gcc_unreachable ();
5707 }
5708 }
5709
5710 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5711
5712 int
5713 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5714 unsigned int new_reg)
5715 {
5716 /* Interrupt functions can only use registers that have already been
5717 saved by the prologue, even if they would normally be
5718 call-clobbered. */
5719
5720 if (h8300_current_function_interrupt_function_p ()
5721 && !df_regs_ever_live_p (new_reg))
5722 return 0;
5723
5724 return 1;
5725 }
5726
5727 /* Returns true if register REGNO is safe to be allocated as a scratch
5728 register in the current function. */
5729
5730 static bool
5731 h8300_hard_regno_scratch_ok (unsigned int regno)
5732 {
5733 if (h8300_current_function_interrupt_function_p ()
5734 && ! WORD_REG_USED (regno))
5735 return false;
5736
5737 return true;
5738 }
5739
5740
5741 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5742
5743 static int
5744 h8300_rtx_ok_for_base_p (rtx x, int strict)
5745 {
5746 /* Strip off SUBREG if any. */
5747 if (GET_CODE (x) == SUBREG)
5748 x = SUBREG_REG (x);
5749
5750 return (REG_P (x)
5751 && (strict
5752 ? REG_OK_FOR_BASE_STRICT_P (x)
5753 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5754 }
5755
5756 /* Return nozero if X is a legitimate address. On the H8/300, a
5757 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5758 CONSTANT_ADDRESS. */
5759
5760 static bool
5761 h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
5762 {
5763 /* The register indirect addresses like @er0 is always valid. */
5764 if (h8300_rtx_ok_for_base_p (x, strict))
5765 return 1;
5766
5767 if (CONSTANT_ADDRESS_P (x))
5768 return 1;
5769
5770 if (TARGET_H8300SX
5771 && ( GET_CODE (x) == PRE_INC
5772 || GET_CODE (x) == PRE_DEC
5773 || GET_CODE (x) == POST_INC
5774 || GET_CODE (x) == POST_DEC)
5775 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5776 return 1;
5777
5778 if (GET_CODE (x) == PLUS
5779 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5780 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5781 mode, 0), strict))
5782 return 1;
5783
5784 return 0;
5785 }
5786
5787 /* Worker function for HARD_REGNO_NREGS.
5788
5789 We pretend the MAC register is 32bits -- we don't have any data
5790 types on the H8 series to handle more than 32bits. */
5791
5792 int
5793 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5794 {
5795 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5796 }
5797
5798 /* Worker function for HARD_REGNO_MODE_OK. */
5799
5800 int
5801 h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5802 {
5803 if (TARGET_H8300)
5804 /* If an even reg, then anything goes. Otherwise the mode must be
5805 QI or HI. */
5806 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5807 else
5808 /* MAC register can only be of SImode. Otherwise, anything
5809 goes. */
5810 return regno == MAC_REG ? mode == SImode : 1;
5811 }
5812 \f
5813 /* Perform target dependent optabs initialization. */
5814 static void
5815 h8300_init_libfuncs (void)
5816 {
5817 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5818 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5819 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5820 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5821 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5822 }
5823 \f
5824 /* Worker function for TARGET_FUNCTION_VALUE.
5825
5826 On the H8 the return value is in R0/R1. */
5827
5828 static rtx
5829 h8300_function_value (const_tree ret_type,
5830 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5831 bool outgoing ATTRIBUTE_UNUSED)
5832 {
5833 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5834 }
5835
5836 /* Worker function for TARGET_LIBCALL_VALUE.
5837
5838 On the H8 the return value is in R0/R1. */
5839
5840 static rtx
5841 h8300_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5842 {
5843 return gen_rtx_REG (mode, R0_REG);
5844 }
5845
5846 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5847
5848 On the H8, R0 is the only register thus used. */
5849
5850 static bool
5851 h8300_function_value_regno_p (const unsigned int regno)
5852 {
5853 return (regno == R0_REG);
5854 }
5855
5856 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5857
5858 static bool
5859 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5860 {
5861 return (TYPE_MODE (type) == BLKmode
5862 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5863 }
5864 \f
5865 /* We emit the entire trampoline here. Depending on the pointer size,
5866 we use a different trampoline.
5867
5868 Pmode == HImode
5869 vvvv context
5870 1 0000 7903xxxx mov.w #0x1234,r3
5871 2 0004 5A00xxxx jmp @0x1234
5872 ^^^^ function
5873
5874 Pmode == SImode
5875 vvvvvvvv context
5876 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5877 3 0006 5Axxxxxx jmp @0x123456
5878 ^^^^^^ function
5879 */
5880
5881 static void
5882 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5883 {
5884 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5885 rtx mem;
5886
5887 if (Pmode == HImode)
5888 {
5889 mem = adjust_address (m_tramp, HImode, 0);
5890 emit_move_insn (mem, GEN_INT (0x7903));
5891 mem = adjust_address (m_tramp, Pmode, 2);
5892 emit_move_insn (mem, cxt);
5893 mem = adjust_address (m_tramp, HImode, 4);
5894 emit_move_insn (mem, GEN_INT (0x5a00));
5895 mem = adjust_address (m_tramp, Pmode, 6);
5896 emit_move_insn (mem, fnaddr);
5897 }
5898 else
5899 {
5900 rtx tem;
5901
5902 mem = adjust_address (m_tramp, HImode, 0);
5903 emit_move_insn (mem, GEN_INT (0x7a03));
5904 mem = adjust_address (m_tramp, Pmode, 2);
5905 emit_move_insn (mem, cxt);
5906
5907 tem = copy_to_reg (fnaddr);
5908 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
5909 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
5910 mem = adjust_address (m_tramp, SImode, 6);
5911 emit_move_insn (mem, tem);
5912 }
5913 }
5914 \f
5915 /* Initialize the GCC target structure. */
5916 #undef TARGET_ATTRIBUTE_TABLE
5917 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5918
5919 #undef TARGET_ASM_ALIGNED_HI_OP
5920 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5921
5922 #undef TARGET_ASM_FILE_START
5923 #define TARGET_ASM_FILE_START h8300_file_start
5924 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5925 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5926
5927 #undef TARGET_ASM_FILE_END
5928 #define TARGET_ASM_FILE_END h8300_file_end
5929
5930 #undef TARGET_PRINT_OPERAND
5931 #define TARGET_PRINT_OPERAND h8300_print_operand
5932 #undef TARGET_PRINT_OPERAND_ADDRESS
5933 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
5934 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
5935 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
5936
5937 #undef TARGET_ENCODE_SECTION_INFO
5938 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5939
5940 #undef TARGET_INSERT_ATTRIBUTES
5941 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5942
5943 #undef TARGET_REGISTER_MOVE_COST
5944 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
5945
5946 #undef TARGET_RTX_COSTS
5947 #define TARGET_RTX_COSTS h8300_rtx_costs
5948
5949 #undef TARGET_INIT_LIBFUNCS
5950 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5951
5952 #undef TARGET_FUNCTION_VALUE
5953 #define TARGET_FUNCTION_VALUE h8300_function_value
5954
5955 #undef TARGET_LIBCALL_VALUE
5956 #define TARGET_LIBCALL_VALUE h8300_libcall_value
5957
5958 #undef TARGET_FUNCTION_VALUE_REGNO_P
5959 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
5960
5961 #undef TARGET_RETURN_IN_MEMORY
5962 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5963
5964 #undef TARGET_FUNCTION_ARG
5965 #define TARGET_FUNCTION_ARG h8300_function_arg
5966
5967 #undef TARGET_FUNCTION_ARG_ADVANCE
5968 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
5969
5970 #undef TARGET_MACHINE_DEPENDENT_REORG
5971 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5972
5973 #undef TARGET_HARD_REGNO_SCRATCH_OK
5974 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5975
5976 #undef TARGET_LEGITIMATE_ADDRESS_P
5977 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5978
5979 #undef TARGET_CAN_ELIMINATE
5980 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
5981
5982 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5983 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
5984
5985 #undef TARGET_TRAMPOLINE_INIT
5986 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
5987
5988 #undef TARGET_OPTION_OVERRIDE
5989 #define TARGET_OPTION_OVERRIDE h8300_option_override
5990
5991 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
5992 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
5993
5994 struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git