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[thirdparty/gcc.git] / gcc / config / h8300 / peepholes.md
1 ;; -----------------------------------------------------------------
2 ;; PEEPHOLE PATTERNS
3 ;; -----------------------------------------------------------------
4
5 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
6
7 (define_peephole2
8 [(parallel [(set (match_operand:HI 0 "register_operand" "")
9 (lshiftrt:HI (match_dup 0)
10 (match_operand:HI 1 "const_int_operand" "")))
11 (clobber (match_operand:HI 2 "" ""))])
12 (set (match_dup 0)
13 (and:HI (match_dup 0)
14 (match_operand:HI 3 "const_int_operand" "")))]
15 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
16 [(set (match_dup 0)
17 (and:HI (match_dup 0)
18 (const_int 255)))
19 (parallel [(set (match_dup 0)
20 (lshiftrt:HI (match_dup 0) (match_dup 1)))
21 (clobber (match_dup 2))])]
22 "")
23
24 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
25
26 (define_peephole2
27 [(parallel [(set (match_operand:HI 0 "register_operand" "")
28 (ashift:HI (match_dup 0)
29 (match_operand:HI 1 "const_int_operand" "")))
30 (clobber (match_operand:HI 2 "" ""))])
31 (set (match_dup 0)
32 (and:HI (match_dup 0)
33 (match_operand:HI 3 "const_int_operand" "")))]
34 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
35 [(set (match_dup 0)
36 (and:HI (match_dup 0)
37 (const_int 255)))
38 (parallel [(set (match_dup 0)
39 (ashift:HI (match_dup 0) (match_dup 1)))
40 (clobber (match_dup 2))])]
41 "")
42
43 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
44
45 (define_peephole2
46 [(parallel [(set (match_operand:SI 0 "register_operand" "")
47 (lshiftrt:SI (match_dup 0)
48 (match_operand:SI 1 "const_int_operand" "")))
49 (clobber (match_operand:SI 2 "" ""))])
50 (set (match_dup 0)
51 (and:SI (match_dup 0)
52 (match_operand:SI 3 "const_int_operand" "")))]
53 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
54 [(set (match_dup 0)
55 (and:SI (match_dup 0)
56 (const_int 255)))
57 (parallel [(set (match_dup 0)
58 (lshiftrt:SI (match_dup 0) (match_dup 1)))
59 (clobber (match_dup 2))])]
60 "")
61
62 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
63
64 (define_peephole2
65 [(parallel [(set (match_operand:SI 0 "register_operand" "")
66 (ashift:SI (match_dup 0)
67 (match_operand:SI 1 "const_int_operand" "")))
68 (clobber (match_operand:SI 2 "" ""))])
69 (set (match_dup 0)
70 (and:SI (match_dup 0)
71 (match_operand:SI 3 "const_int_operand" "")))]
72 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
73 [(set (match_dup 0)
74 (and:SI (match_dup 0)
75 (const_int 255)))
76 (parallel [(set (match_dup 0)
77 (ashift:SI (match_dup 0) (match_dup 1)))
78 (clobber (match_dup 2))])]
79 "")
80
81 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
82
83 (define_peephole2
84 [(parallel [(set (match_operand:SI 0 "register_operand" "")
85 (lshiftrt:SI (match_dup 0)
86 (match_operand:SI 1 "const_int_operand" "")))
87 (clobber (match_operand:SI 2 "" ""))])
88 (set (match_dup 0)
89 (and:SI (match_dup 0)
90 (match_operand:SI 3 "const_int_operand" "")))]
91 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
92 [(set (match_dup 0)
93 (and:SI (match_dup 0)
94 (const_int 65535)))
95 (parallel [(set (match_dup 0)
96 (lshiftrt:SI (match_dup 0) (match_dup 1)))
97 (clobber (match_dup 2))])]
98 "")
99
100 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
101
102 (define_peephole2
103 [(parallel [(set (match_operand:SI 0 "register_operand" "")
104 (ashift:SI (match_dup 0)
105 (match_operand:SI 1 "const_int_operand" "")))
106 (clobber (match_operand:SI 2 "" ""))])
107 (set (match_dup 0)
108 (and:SI (match_dup 0)
109 (match_operand:SI 3 "const_int_operand" "")))]
110 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
111 [(set (match_dup 0)
112 (and:SI (match_dup 0)
113 (const_int 65535)))
114 (parallel [(set (match_dup 0)
115 (ashift:SI (match_dup 0) (match_dup 1)))
116 (clobber (match_dup 2))])]
117 "")
118
119 ;; Cram four pushes into stm.l.
120
121 (define_peephole2
122 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
123 (match_operand:SI 0 "register_operand" ""))
124 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
125 (match_operand:SI 1 "register_operand" ""))
126 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
127 (match_operand:SI 2 "register_operand" ""))
128 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
129 (match_operand:SI 3 "register_operand" ""))]
130 "TARGET_H8300S && !TARGET_NORMAL_MODE
131 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
132 && REGNO (operands[1]) == REGNO (operands[0]) + 1
133 && REGNO (operands[2]) == REGNO (operands[0]) + 2
134 && REGNO (operands[3]) == REGNO (operands[0]) + 3
135 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
136 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
137 (match_dup 0))
138 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
139 (match_dup 1))
140 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
141 (match_dup 2))
142 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
143 (match_dup 3))
144 (set (reg:SI SP_REG)
145 (plus:SI (reg:SI SP_REG)
146 (const_int -16)))])]
147 "")
148
149 (define_peephole2
150 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
151 (match_operand:SI 0 "register_operand" ""))
152 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
153 (match_operand:SI 1 "register_operand" ""))
154 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
155 (match_operand:SI 2 "register_operand" ""))
156 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
157 (match_operand:SI 3 "register_operand" ""))]
158 "TARGET_H8300S && TARGET_NORMAL_MODE
159 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
160 && REGNO (operands[1]) == REGNO (operands[0]) + 1
161 && REGNO (operands[2]) == REGNO (operands[0]) + 2
162 && REGNO (operands[3]) == REGNO (operands[0]) + 3
163 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
164 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
165 (match_dup 0))
166 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
167 (match_dup 1))
168 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
169 (match_dup 2))
170 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
171 (match_dup 3))
172 (set (reg:HI SP_REG)
173 (plus:HI (reg:HI SP_REG)
174 (const_int -16)))])]
175 "")
176
177 ;; Cram three pushes into stm.l.
178
179 (define_peephole2
180 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
181 (match_operand:SI 0 "register_operand" ""))
182 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
183 (match_operand:SI 1 "register_operand" ""))
184 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
185 (match_operand:SI 2 "register_operand" ""))]
186 "TARGET_H8300S && !TARGET_NORMAL_MODE
187 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
188 && REGNO (operands[1]) == REGNO (operands[0]) + 1
189 && REGNO (operands[2]) == REGNO (operands[0]) + 2
190 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
191 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
192 (match_dup 0))
193 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
194 (match_dup 1))
195 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
196 (match_dup 2))
197 (set (reg:SI SP_REG)
198 (plus:SI (reg:SI SP_REG)
199 (const_int -12)))])]
200 "")
201
202 (define_peephole2
203 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
204 (match_operand:SI 0 "register_operand" ""))
205 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
206 (match_operand:SI 1 "register_operand" ""))
207 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
208 (match_operand:SI 2 "register_operand" ""))]
209 "TARGET_H8300S && TARGET_NORMAL_MODE
210 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
211 && REGNO (operands[1]) == REGNO (operands[0]) + 1
212 && REGNO (operands[2]) == REGNO (operands[0]) + 2
213 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
214 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
215 (match_dup 0))
216 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
217 (match_dup 1))
218 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
219 (match_dup 2))
220 (set (reg:HI SP_REG)
221 (plus:HI (reg:HI SP_REG)
222 (const_int -12)))])]
223 "")
224
225 ;; Cram two pushes into stm.l.
226
227 (define_peephole2
228 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
229 (match_operand:SI 0 "register_operand" ""))
230 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
231 (match_operand:SI 1 "register_operand" ""))]
232 "TARGET_H8300S && !TARGET_NORMAL_MODE
233 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
234 && REGNO (operands[1]) == REGNO (operands[0]) + 1
235 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
236 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
237 (match_dup 0))
238 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
239 (match_dup 1))
240 (set (reg:SI SP_REG)
241 (plus:SI (reg:SI SP_REG)
242 (const_int -8)))])]
243 "")
244
245 (define_peephole2
246 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
247 (match_operand:SI 0 "register_operand" ""))
248 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
249 (match_operand:SI 1 "register_operand" ""))]
250 "TARGET_H8300S && TARGET_NORMAL_MODE
251 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
252 && REGNO (operands[1]) == REGNO (operands[0]) + 1
253 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
254 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
255 (match_dup 0))
256 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
257 (match_dup 1))
258 (set (reg:HI SP_REG)
259 (plus:HI (reg:HI SP_REG)
260 (const_int -8)))])]
261 "")
262
263 ;; Turn
264 ;;
265 ;; mov.w #2,r0
266 ;; add.w r7,r0 (6 bytes)
267 ;;
268 ;; into
269 ;;
270 ;; mov.w r7,r0
271 ;; adds #2,r0 (4 bytes)
272
273 (define_peephole2
274 [(set (match_operand:HI 0 "register_operand" "")
275 (match_operand:HI 1 "const_int_operand" ""))
276 (set (match_dup 0)
277 (plus:HI (match_dup 0)
278 (match_operand:HI 2 "register_operand" "")))]
279 "REG_P (operands[0]) && REG_P (operands[2])
280 && REGNO (operands[0]) != REGNO (operands[2])
281 && (satisfies_constraint_J (operands[1])
282 || satisfies_constraint_L (operands[1])
283 || satisfies_constraint_N (operands[1]))"
284 [(set (match_dup 0)
285 (match_dup 2))
286 (set (match_dup 0)
287 (plus:HI (match_dup 0)
288 (match_dup 1)))]
289 "")
290
291 ;; Turn
292 ;;
293 ;; sub.l er0,er0
294 ;; add.b #4,r0l
295 ;; add.l er7,er0 (6 bytes)
296 ;;
297 ;; into
298 ;;
299 ;; mov.l er7,er0
300 ;; adds #4,er0 (4 bytes)
301
302 (define_peephole2
303 [(set (match_operand:SI 0 "register_operand" "")
304 (match_operand:SI 1 "const_int_operand" ""))
305 (set (match_dup 0)
306 (plus:SI (match_dup 0)
307 (match_operand:SI 2 "register_operand" "")))]
308 "REG_P (operands[0]) && REG_P (operands[2])
309 && REGNO (operands[0]) != REGNO (operands[2])
310 && (satisfies_constraint_L (operands[1])
311 || satisfies_constraint_N (operands[1]))"
312 [(set (match_dup 0)
313 (match_dup 2))
314 (set (match_dup 0)
315 (plus:SI (match_dup 0)
316 (match_dup 1)))]
317 "")
318
319 ;; Turn
320 ;;
321 ;; mov.l er7,er0
322 ;; add.l #10,er0 (takes 8 bytes)
323 ;;
324 ;; into
325 ;;
326 ;; sub.l er0,er0
327 ;; add.b #10,r0l
328 ;; add.l er7,er0 (takes 6 bytes)
329
330 (define_peephole2
331 [(set (match_operand:SI 0 "register_operand" "")
332 (match_operand:SI 1 "register_operand" ""))
333 (set (match_dup 0)
334 (plus:SI (match_dup 0)
335 (match_operand:SI 2 "const_int_operand" "")))]
336 "operands[0] != stack_pointer_rtx
337 && REG_P (operands[0]) && REG_P (operands[1])
338 && REGNO (operands[0]) != REGNO (operands[1])
339 && !satisfies_constraint_L (operands[2])
340 && !satisfies_constraint_N (operands[2])
341 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
342 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
343 || INTVAL (operands[2]) == 0xffff
344 || INTVAL (operands[2]) == 0xfffe)"
345 [(set (match_dup 0)
346 (match_dup 2))
347 (set (match_dup 0)
348 (plus:SI (match_dup 0)
349 (match_dup 1)))]
350 "")
351
352 ;; Turn
353 ;;
354 ;; subs #1,er4
355 ;; mov.w r4,r4
356 ;; bne .L2028
357 ;;
358 ;; into
359 ;;
360 ;; dec.w #1,r4
361 ;; bne .L2028
362
363 (define_peephole2
364 [(set (match_operand:HI 0 "register_operand" "")
365 (plus:HI (match_dup 0)
366 (match_operand 1 "incdec_operand" "")))
367 (set (cc0) (compare (match_dup 0)
368 (const_int 0)))
369 (set (pc)
370 (if_then_else (match_operator 3 "eqne_operator"
371 [(cc0) (const_int 0)])
372 (label_ref (match_operand 2 "" ""))
373 (pc)))]
374 ""
375 [(set (match_operand:HI 0 "register_operand" "")
376 (unspec:HI [(match_dup 0)
377 (match_dup 1)]
378 UNSPEC_INCDEC))
379 (set (cc0) (compare (match_dup 0)
380 (const_int 0)))
381 (set (pc)
382 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
383 (label_ref (match_dup 2))
384 (pc)))]
385 "")
386
387 ;; The SImode version of the previous pattern.
388
389 (define_peephole2
390 [(set (match_operand:SI 0 "register_operand" "")
391 (plus:SI (match_dup 0)
392 (match_operand 1 "incdec_operand" "")))
393 (set (cc0) (compare (match_dup 0)
394 (const_int 0)))
395 (set (pc)
396 (if_then_else (match_operator 3 "eqne_operator"
397 [(cc0) (const_int 0)])
398 (label_ref (match_operand 2 "" ""))
399 (pc)))]
400 ""
401 [(set (match_operand:SI 0 "register_operand" "")
402 (unspec:SI [(match_dup 0)
403 (match_dup 1)]
404 UNSPEC_INCDEC))
405 (set (cc0) (compare (match_dup 0)
406 (const_int 0)))
407 (set (pc)
408 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
409 (label_ref (match_dup 2))
410 (pc)))]
411 "")
412
413 (define_peephole2
414 [(parallel [(set (cc0)
415 (compare (zero_extract:SI (match_operand:QI 0 "register_operand" "")
416 (const_int 1)
417 (const_int 7))
418 (const_int 0)))
419 (clobber (scratch:QI))])
420 (set (pc)
421 (if_then_else (match_operator 1 "eqne_operator"
422 [(cc0) (const_int 0)])
423 (label_ref (match_operand 2 "" ""))
424 (pc)))]
425 ""
426 [(set (cc0) (compare (match_dup 0)
427 (const_int 0)))
428 (set (pc)
429 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
430 (label_ref (match_dup 2))
431 (pc)))]
432 {
433 operands[3] = ((GET_CODE (operands[1]) == EQ)
434 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
435 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));
436 })
437
438 ;; The next three peephole2's will try to transform
439 ;;
440 ;; mov.b A,r0l (or mov.l A,er0)
441 ;; and.l #CST,er0
442 ;;
443 ;; into
444 ;;
445 ;; sub.l er0
446 ;; mov.b A,r0l
447 ;; and.b #CST,r0l (if CST is not 255)
448
449 (define_peephole2
450 [(set (match_operand:QI 0 "register_operand" "")
451 (match_operand:QI 1 "general_operand" ""))
452 (set (match_operand:SI 2 "register_operand" "")
453 (and:SI (match_dup 2)
454 (const_int 255)))]
455 "!reg_overlap_mentioned_p (operands[2], operands[1])
456 && REGNO (operands[0]) == REGNO (operands[2])"
457 [(set (match_dup 2)
458 (const_int 0))
459 (set (strict_low_part (match_dup 0))
460 (match_dup 1))]
461 "")
462
463 (define_peephole2
464 [(set (match_operand:SI 0 "register_operand" "")
465 (match_operand:SI 1 "nonimmediate_operand" ""))
466 (set (match_dup 0)
467 (and:SI (match_dup 0)
468 (const_int 255)))]
469 "!reg_overlap_mentioned_p (operands[0], operands[1])
470 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
471 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
472 [(set (match_dup 0)
473 (const_int 0))
474 (set (strict_low_part (match_dup 2))
475 (match_dup 3))]
476 {
477 operands[2] = gen_lowpart (QImode, operands[0]);
478 operands[3] = gen_lowpart (QImode, operands[1]);
479 })
480
481 (define_peephole2
482 [(set (match_operand 0 "register_operand" "")
483 (match_operand 1 "nonimmediate_operand" ""))
484 (set (match_operand:SI 2 "register_operand" "")
485 (and:SI (match_dup 2)
486 (match_operand:SI 3 "const_int_qi_operand" "")))]
487 "(GET_MODE (operands[0]) == QImode
488 || GET_MODE (operands[0]) == HImode
489 || GET_MODE (operands[0]) == SImode)
490 && GET_MODE (operands[0]) == GET_MODE (operands[1])
491 && REGNO (operands[0]) == REGNO (operands[2])
492 && !reg_overlap_mentioned_p (operands[2], operands[1])
493 && !(GET_MODE (operands[1]) != QImode
494 && GET_CODE (operands[1]) == MEM
495 && !offsettable_memref_p (operands[1]))
496 && !(GET_MODE (operands[1]) != QImode
497 && GET_CODE (operands[1]) == MEM
498 && MEM_VOLATILE_P (operands[1]))"
499 [(set (match_dup 2)
500 (const_int 0))
501 (set (strict_low_part (match_dup 4))
502 (match_dup 5))
503 (set (match_dup 2)
504 (and:SI (match_dup 2)
505 (match_dup 6)))]
506 {
507 operands[4] = gen_lowpart (QImode, operands[0]);
508 operands[5] = gen_lowpart (QImode, operands[1]);
509 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));
510 })
511
512 (define_peephole2
513 [(set (match_operand:SI 0 "register_operand" "")
514 (match_operand:SI 1 "register_operand" ""))
515 (set (match_dup 0)
516 (and:SI (match_dup 0)
517 (const_int 65280)))]
518 "!reg_overlap_mentioned_p (operands[0], operands[1])"
519 [(set (match_dup 0)
520 (const_int 0))
521 (set (zero_extract:SI (match_dup 0)
522 (const_int 8)
523 (const_int 8))
524 (lshiftrt:SI (match_dup 1)
525 (const_int 8)))]
526 "")
527
528 ;; If a load of mem:SI is followed by an AND that turns off the upper
529 ;; half, then we can load mem:HI instead.
530
531 (define_peephole2
532 [(set (match_operand:SI 0 "register_operand" "")
533 (match_operand:SI 1 "memory_operand" ""))
534 (set (match_dup 0)
535 (and:SI (match_dup 0)
536 (match_operand:SI 2 "const_int_operand" "")))]
537 "!MEM_VOLATILE_P (operands[1])
538 && offsettable_memref_p (operands[1])
539 && (INTVAL (operands[2]) & ~0xffff) == 0
540 && INTVAL (operands[2]) != 255"
541 [(set (match_dup 3)
542 (match_dup 4))
543 (set (match_dup 0)
544 (and:SI (match_dup 0)
545 (match_dup 2)))]
546 {
547 operands[3] = gen_lowpart (HImode, operands[0]);
548 operands[4] = gen_lowpart (HImode, operands[1]);
549 })
550
551 ;; Convert a memory comparison to a move if there is a scratch register.
552
553 (define_peephole2
554 [(match_scratch:QHSI 1 "r")
555 (set (cc0)
556 (compare (match_operand:QHSI 0 "memory_operand" "")
557 (const_int 0)))]
558 ""
559 [(set (match_dup 1)
560 (match_dup 0))
561 (set (cc0) (compare (match_dup 1)
562 (const_int 0)))]
563 "")
564
565 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
566 ;; the equivalent with shorter sequences. Here is the summary. Cases
567 ;; are grouped for each define_peephole2.
568 ;;
569 ;; reg const_int use insn
570 ;; --------------------------------------------------------
571 ;; dead -2 eq/ne inc.l
572 ;; dead -1 eq/ne inc.l
573 ;; dead 1 eq/ne dec.l
574 ;; dead 2 eq/ne dec.l
575 ;;
576 ;; dead 1 ge/lt shar.l
577 ;; dead 3 (H8S) ge/lt shar.l
578 ;;
579 ;; dead 1 geu/ltu shar.l
580 ;; dead 3 (H8S) geu/ltu shar.l
581 ;;
582 ;; ---- 255 ge/lt mov.b
583 ;;
584 ;; ---- 255 geu/ltu mov.b
585
586 ;; Transform
587 ;;
588 ;; cmp.w #1,r0
589 ;; bne .L1
590 ;;
591 ;; into
592 ;;
593 ;; dec.w #1,r0
594 ;; bne .L1
595
596 (define_peephole2
597 [(set (cc0)
598 (compare (match_operand:HI 0 "register_operand" "")
599 (match_operand:HI 1 "incdec_operand" "")))
600 (set (pc)
601 (if_then_else (match_operator 3 "eqne_operator"
602 [(cc0) (const_int 0)])
603 (label_ref (match_operand 2 "" ""))
604 (pc)))]
605 "INTVAL (operands[1]) != 0 && peep2_reg_dead_p (1, operands[0])"
606 [(set (match_dup 0)
607 (unspec:HI [(match_dup 0)
608 (match_dup 4)]
609 UNSPEC_INCDEC))
610 (set (cc0) (compare (match_dup 0)
611 (const_int 0)))
612 (set (pc)
613 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
614 (label_ref (match_dup 2))
615 (pc)))]
616 {
617 operands[4] = GEN_INT (- INTVAL (operands[1]));
618 })
619
620 ;; Transform
621 ;;
622 ;; cmp.w #1,r0
623 ;; bgt .L1
624 ;;
625 ;; into
626 ;;
627 ;; shar.w r0
628 ;; bgt .L1
629
630 (define_peephole2
631 [(set (cc0)
632 (compare (match_operand:HI 0 "register_operand" "")
633 (match_operand:HI 1 "const_int_operand" "")))
634 (set (pc)
635 (if_then_else (match_operator 2 "gtle_operator"
636 [(cc0) (const_int 0)])
637 (label_ref (match_operand 3 "" ""))
638 (pc)))]
639 "peep2_reg_dead_p (1, operands[0])
640 && (INTVAL (operands[1]) == 1
641 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
642 [(parallel [(set (match_dup 0)
643 (ashiftrt:HI (match_dup 0)
644 (match_dup 4)))
645 (clobber (scratch:QI))])
646 (set (cc0) (compare (match_dup 0)
647 (const_int 0)))
648 (set (pc)
649 (if_then_else (match_dup 2)
650 (label_ref (match_dup 3))
651 (pc)))]
652 {
653 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
654 })
655
656 ;; Transform
657 ;;
658 ;; cmp.w #1,r0
659 ;; bhi .L1
660 ;;
661 ;; into
662 ;;
663 ;; shar.w r0
664 ;; bne .L1
665
666 (define_peephole2
667 [(set (cc0)
668 (compare (match_operand:HI 0 "register_operand" "")
669 (match_operand:HI 1 "const_int_operand" "")))
670 (set (pc)
671 (if_then_else (match_operator 2 "gtuleu_operator"
672 [(cc0) (const_int 0)])
673 (label_ref (match_operand 3 "" ""))
674 (pc)))]
675 "peep2_reg_dead_p (1, operands[0])
676 && (INTVAL (operands[1]) == 1
677 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
678 [(parallel [(set (match_dup 0)
679 (ashiftrt:HI (match_dup 0)
680 (match_dup 4)))
681 (clobber (scratch:QI))])
682 (set (cc0) (compare (match_dup 0)
683 (const_int 0)))
684 (set (pc)
685 (if_then_else (match_dup 5)
686 (label_ref (match_dup 3))
687 (pc)))]
688 {
689 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
690 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
691 VOIDmode, cc0_rtx, const0_rtx);
692 })
693
694 ;; Transform
695 ;;
696 ;; cmp.w #255,r0
697 ;; bgt .L1
698 ;;
699 ;; into
700 ;;
701 ;; mov.b r0h,r0h
702 ;; bgt .L1
703
704 (define_peephole2
705 [(set (cc0)
706 (compare (match_operand:HI 0 "register_operand" "")
707 (const_int 255)))
708 (set (pc)
709 (if_then_else (match_operator 1 "gtle_operator"
710 [(cc0) (const_int 0)])
711 (label_ref (match_operand 2 "" ""))
712 (pc)))]
713 ""
714 [(set (cc0) (compare (and:HI (match_dup 0)
715 (const_int -256))
716 (const_int 0)))
717 (set (pc)
718 (if_then_else (match_dup 1)
719 (label_ref (match_dup 2))
720 (pc)))]
721 "")
722
723 ;; Transform
724 ;;
725 ;; cmp.w #255,r0
726 ;; bhi .L1
727 ;;
728 ;; into
729 ;;
730 ;; mov.b r0h,r0h
731 ;; bne .L1
732
733 (define_peephole2
734 [(set (cc0)
735 (compare (match_operand:HI 0 "register_operand" "")
736 (const_int 255)))
737 (set (pc)
738 (if_then_else (match_operator 1 "gtuleu_operator"
739 [(cc0) (const_int 0)])
740 (label_ref (match_operand 2 "" ""))
741 (pc)))]
742 ""
743 [(set (cc0) (compare (and:HI (match_dup 0)
744 (const_int -256))
745 (const_int 0)))
746 (set (pc)
747 (if_then_else (match_dup 3)
748 (label_ref (match_dup 2))
749 (pc)))]
750 {
751 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
752 VOIDmode, cc0_rtx, const0_rtx);
753 })
754
755 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
756 ;; the equivalent with shorter sequences. Here is the summary. Cases
757 ;; are grouped for each define_peephole2.
758 ;;
759 ;; reg const_int use insn
760 ;; --------------------------------------------------------
761 ;; live -2 eq/ne copy and inc.l
762 ;; live -1 eq/ne copy and inc.l
763 ;; live 1 eq/ne copy and dec.l
764 ;; live 2 eq/ne copy and dec.l
765 ;;
766 ;; dead -2 eq/ne inc.l
767 ;; dead -1 eq/ne inc.l
768 ;; dead 1 eq/ne dec.l
769 ;; dead 2 eq/ne dec.l
770 ;;
771 ;; dead -131072 eq/ne inc.w and test
772 ;; dead -65536 eq/ne inc.w and test
773 ;; dead 65536 eq/ne dec.w and test
774 ;; dead 131072 eq/ne dec.w and test
775 ;;
776 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
777 ;; dead 0x0000??00 eq/ne xor.b and test
778 ;; dead 0x0000ffff eq/ne not.w and test
779 ;;
780 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
781 ;; dead 0xffff??ff eq/ne xor.b and not.l
782 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
783 ;; dead 0x80000000 eq/ne rotl.l and dec.l
784 ;;
785 ;; live 1 ge/lt copy and shar.l
786 ;; live 3 (H8S) ge/lt copy and shar.l
787 ;;
788 ;; live 1 geu/ltu copy and shar.l
789 ;; live 3 (H8S) geu/ltu copy and shar.l
790 ;;
791 ;; dead 1 ge/lt shar.l
792 ;; dead 3 (H8S) ge/lt shar.l
793 ;;
794 ;; dead 1 geu/ltu shar.l
795 ;; dead 3 (H8S) geu/ltu shar.l
796 ;;
797 ;; dead 3 (H8/300H) ge/lt and.b and test
798 ;; dead 7 ge/lt and.b and test
799 ;; dead 15 ge/lt and.b and test
800 ;; dead 31 ge/lt and.b and test
801 ;; dead 63 ge/lt and.b and test
802 ;; dead 127 ge/lt and.b and test
803 ;; dead 255 ge/lt and.b and test
804 ;;
805 ;; dead 3 (H8/300H) geu/ltu and.b and test
806 ;; dead 7 geu/ltu and.b and test
807 ;; dead 15 geu/ltu and.b and test
808 ;; dead 31 geu/ltu and.b and test
809 ;; dead 63 geu/ltu and.b and test
810 ;; dead 127 geu/ltu and.b and test
811 ;; dead 255 geu/ltu and.b and test
812 ;;
813 ;; ---- 65535 ge/lt mov.w
814 ;;
815 ;; ---- 65535 geu/ltu mov.w
816
817 ;; Transform
818 ;;
819 ;; cmp.l #1,er0
820 ;; beq .L1
821 ;;
822 ;; into
823 ;;
824 ;; dec.l #1,er0
825 ;; beq .L1
826
827 (define_peephole2
828 [(set (cc0)
829 (compare (match_operand:SI 0 "register_operand" "")
830 (match_operand:SI 1 "incdec_operand" "")))
831 (set (pc)
832 (if_then_else (match_operator 3 "eqne_operator"
833 [(cc0) (const_int 0)])
834 (label_ref (match_operand 2 "" ""))
835 (pc)))]
836 "INTVAL (operands[1]) != 0 && peep2_reg_dead_p (1, operands[0])"
837 [(set (match_dup 0)
838 (unspec:SI [(match_dup 0)
839 (match_dup 4)]
840 UNSPEC_INCDEC))
841 (set (cc0) (compare (match_dup 0)
842 (const_int 0)))
843 (set (pc)
844 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
845 (label_ref (match_dup 2))
846 (pc)))]
847 {
848 operands[4] = GEN_INT (- INTVAL (operands[1]));
849 })
850
851 ;; Transform
852 ;;
853 ;; cmp.l #65536,er0
854 ;; beq .L1
855 ;;
856 ;; into
857 ;;
858 ;; dec.l #1,e0
859 ;; beq .L1
860
861 (define_peephole2
862 [(set (cc0)
863 (compare (match_operand:SI 0 "register_operand" "")
864 (match_operand:SI 1 "const_int_operand" "")))
865 (set (pc)
866 (if_then_else (match_operator 3 "eqne_operator"
867 [(cc0) (const_int 0)])
868 (label_ref (match_operand 2 "" ""))
869 (pc)))]
870 "peep2_reg_dead_p (1, operands[0])
871 && (INTVAL (operands[1]) == -131072
872 || INTVAL (operands[1]) == -65536
873 || INTVAL (operands[1]) == 65536
874 || INTVAL (operands[1]) == 131072)"
875 [(set (match_dup 0)
876 (plus:SI (match_dup 0)
877 (match_dup 4)))
878 (set (cc0) (compare (match_dup 0)
879 (const_int 0)))
880 (set (pc)
881 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
882 (label_ref (match_dup 2))
883 (pc)))]
884 {
885 operands[4] = GEN_INT (- INTVAL (operands[1]));
886 })
887
888 ;; Transform
889 ;;
890 ;; cmp.l #100,er0
891 ;; beq .L1
892 ;;
893 ;; into
894 ;;
895 ;; xor.b #100,er0
896 ;; mov.l er0,er0
897 ;; beq .L1
898
899 (define_peephole2
900 [(set (cc0)
901 (compare (match_operand:SI 0 "register_operand" "")
902 (match_operand:SI 1 "const_int_operand" "")))
903 (set (pc)
904 (if_then_else (match_operator 3 "eqne_operator"
905 [(cc0) (const_int 0)])
906 (label_ref (match_operand 2 "" ""))
907 (pc)))]
908 "peep2_reg_dead_p (1, operands[0])
909 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
910 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
911 || INTVAL (operands[1]) == 0x0000ffff)
912 && INTVAL (operands[1]) != 0
913 && INTVAL (operands[1]) != 1
914 && INTVAL (operands[1]) != 2"
915 [(set (match_dup 0)
916 (xor:SI (match_dup 0)
917 (match_dup 1)))
918 (set (cc0) (compare (match_dup 0)
919 (const_int 0)))
920 (set (pc)
921 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
922 (label_ref (match_dup 2))
923 (pc)))]
924 "")
925
926 ;; Transform
927 ;;
928 ;; cmp.l #-100,er0
929 ;; beq .L1
930 ;;
931 ;; into
932 ;;
933 ;; xor.b #99,er0
934 ;; not.l er0
935 ;; beq .L1
936
937 (define_peephole2
938 [(set (cc0)
939 (compare (match_operand:SI 0 "register_operand" "")
940 (match_operand:SI 1 "const_int_operand" "")))
941 (set (pc)
942 (if_then_else (match_operator 3 "eqne_operator"
943 [(cc0) (const_int 0)])
944 (label_ref (match_operand 2 "" ""))
945 (pc)))]
946 "peep2_reg_dead_p (1, operands[0])
947 && ((INTVAL (operands[1]) | 0x00ff) == -1
948 || (INTVAL (operands[1]) | 0xff00) == -1)
949 && INTVAL (operands[1]) != -1
950 && INTVAL (operands[1]) != -2"
951 [(set (match_dup 0)
952 (xor:SI (match_dup 0)
953 (match_dup 4)))
954 (set (match_dup 0)
955 (not:SI (match_dup 0)))
956 (set (cc0) (compare (match_dup 0)
957 (const_int 0)))
958 (set (pc)
959 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
960 (label_ref (match_dup 2))
961 (pc)))]
962 {
963 operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);
964 })
965
966 ;; Transform
967 ;;
968 ;; cmp.l #-2147483648,er0
969 ;; beq .L1
970 ;;
971 ;; into
972 ;;
973 ;; rotl.l er0
974 ;; dec.l #1,er0
975 ;; beq .L1
976
977 (define_peephole2
978 [(set (cc0)
979 (compare (match_operand:SI 0 "register_operand" "")
980 (match_operand:SI 1 "const_int_operand" "")))
981 (set (pc)
982 (if_then_else (match_operator 3 "eqne_operator"
983 [(cc0) (const_int 0)])
984 (label_ref (match_operand 2 "" ""))
985 (pc)))]
986 "peep2_reg_dead_p (1, operands[0])
987 && (INTVAL (operands[1]) == -2147483647 - 1
988 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
989 [(set (match_dup 0)
990 (rotate:SI (match_dup 0)
991 (match_dup 4)))
992 (set (match_dup 0)
993 (unspec:SI [(match_dup 0)
994 (const_int -1)]
995 UNSPEC_INCDEC))
996 (set (cc0) (compare (match_dup 0)
997 (const_int 0)))
998 (set (pc)
999 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
1000 (label_ref (match_dup 2))
1001 (pc)))]
1002 {
1003 operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);
1004 })
1005
1006 ;; Transform
1007 ;;
1008 ;; cmp.l #1,er0
1009 ;; bgt .L1
1010 ;;
1011 ;; into
1012 ;;
1013 ;; mov.l er0,er1
1014 ;; shar.l er1
1015 ;; bgt .L1
1016
1017 ;; We avoid this transformation if we see more than one copy of the
1018 ;; same compare insn immediately before this one.
1019
1020 (define_peephole2
1021 [(match_scratch:SI 4 "r")
1022 (set (cc0)
1023 (compare (match_operand:SI 0 "register_operand" "")
1024 (match_operand:SI 1 "const_int_operand" "")))
1025 (set (pc)
1026 (if_then_else (match_operator 2 "gtle_operator"
1027 [(cc0) (const_int 0)])
1028 (label_ref (match_operand 3 "" ""))
1029 (pc)))]
1030 "!peep2_reg_dead_p (1, operands[0])
1031 && (INTVAL (operands[1]) == 1
1032 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
1033 && !same_cmp_preceding_p (insn)"
1034 [(set (match_dup 4)
1035 (match_dup 0))
1036 (parallel [(set (match_dup 4)
1037 (ashiftrt:SI (match_dup 4)
1038 (match_dup 5)))
1039 (clobber (scratch:QI))])
1040 (set (cc0) (compare (match_dup 4)
1041 (const_int 0)))
1042 (set (pc)
1043 (if_then_else (match_dup 2)
1044 (label_ref (match_dup 3))
1045 (pc)))]
1046 {
1047 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
1048 })
1049
1050 ;; Transform
1051 ;;
1052 ;; cmp.l #1,er0
1053 ;; bhi .L1
1054 ;;
1055 ;; into
1056 ;;
1057 ;; mov.l er0,er1
1058 ;; shar.l er1
1059 ;; bne .L1
1060
1061 ;; We avoid this transformation if we see more than one copy of the
1062 ;; same compare insn immediately before this one.
1063
1064 (define_peephole2
1065 [(match_scratch:SI 4 "r")
1066 (set (cc0)
1067 (compare (match_operand:SI 0 "register_operand" "")
1068 (match_operand:SI 1 "const_int_operand" "")))
1069 (set (pc)
1070 (if_then_else (match_operator 2 "gtuleu_operator"
1071 [(cc0) (const_int 0)])
1072 (label_ref (match_operand 3 "" ""))
1073 (pc)))]
1074 "!peep2_reg_dead_p (1, operands[0])
1075 && (INTVAL (operands[1]) == 1
1076 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
1077 && !same_cmp_preceding_p (insn)"
1078 [(set (match_dup 4)
1079 (match_dup 0))
1080 (parallel [(set (match_dup 4)
1081 (ashiftrt:SI (match_dup 4)
1082 (match_dup 5)))
1083 (clobber (scratch:QI))])
1084 (set (cc0) (compare (match_dup 4)
1085 (const_int 0)))
1086 (set (pc)
1087 (if_then_else (match_dup 6)
1088 (label_ref (match_dup 3))
1089 (pc)))]
1090 {
1091 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
1092 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
1093 VOIDmode, cc0_rtx, const0_rtx);
1094 })
1095
1096 ;; Transform
1097 ;;
1098 ;; cmp.l #1,er0
1099 ;; bgt .L1
1100 ;;
1101 ;; into
1102 ;;
1103 ;; shar.l er0
1104 ;; bgt .L1
1105
1106 (define_peephole2
1107 [(set (cc0)
1108 (compare (match_operand:SI 0 "register_operand" "")
1109 (match_operand:SI 1 "const_int_operand" "")))
1110 (set (pc)
1111 (if_then_else (match_operator 2 "gtle_operator"
1112 [(cc0) (const_int 0)])
1113 (label_ref (match_operand 3 "" ""))
1114 (pc)))]
1115 "peep2_reg_dead_p (1, operands[0])
1116 && (INTVAL (operands[1]) == 1
1117 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
1118 [(parallel [(set (match_dup 0)
1119 (ashiftrt:SI (match_dup 0)
1120 (match_dup 4)))
1121 (clobber (scratch:QI))])
1122 (set (cc0) (compare (match_dup 0)
1123 (const_int 0)))
1124 (set (pc)
1125 (if_then_else (match_dup 2)
1126 (label_ref (match_dup 3))
1127 (pc)))]
1128 {
1129 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
1130 })
1131
1132 ;; Transform
1133 ;;
1134 ;; cmp.l #1,er0
1135 ;; bhi .L1
1136 ;;
1137 ;; into
1138 ;;
1139 ;; shar.l er0
1140 ;; bne .L1
1141
1142 (define_peephole2
1143 [(set (cc0)
1144 (compare (match_operand:SI 0 "register_operand" "")
1145 (match_operand:SI 1 "const_int_operand" "")))
1146 (set (pc)
1147 (if_then_else (match_operator 2 "gtuleu_operator"
1148 [(cc0) (const_int 0)])
1149 (label_ref (match_operand 3 "" ""))
1150 (pc)))]
1151 "peep2_reg_dead_p (1, operands[0])
1152 && (INTVAL (operands[1]) == 1
1153 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
1154 [(parallel [(set (match_dup 0)
1155 (ashiftrt:SI (match_dup 0)
1156 (match_dup 4)))
1157 (clobber (scratch:QI))])
1158 (set (cc0) (compare (match_dup 0)
1159 (const_int 0)))
1160 (set (pc)
1161 (if_then_else (match_dup 5)
1162 (label_ref (match_dup 3))
1163 (pc)))]
1164 {
1165 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
1166 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
1167 VOIDmode, cc0_rtx, const0_rtx);
1168 })
1169
1170 ;; Transform
1171 ;;
1172 ;; cmp.l #15,er0
1173 ;; bgt .L1
1174 ;;
1175 ;; into
1176 ;;
1177 ;; and #240,r0l
1178 ;; mov.l er0,er0
1179 ;; bgt .L1
1180
1181 (define_peephole2
1182 [(set (cc0)
1183 (compare (match_operand:SI 0 "register_operand" "")
1184 (match_operand:SI 1 "const_int_operand" "")))
1185 (set (pc)
1186 (if_then_else (match_operator 2 "gtle_operator"
1187 [(cc0) (const_int 0)])
1188 (label_ref (match_operand 3 "" ""))
1189 (pc)))]
1190 "peep2_reg_dead_p (1, operands[0])
1191 && (INTVAL (operands[1]) == 3
1192 || INTVAL (operands[1]) == 7
1193 || INTVAL (operands[1]) == 15
1194 || INTVAL (operands[1]) == 31
1195 || INTVAL (operands[1]) == 63
1196 || INTVAL (operands[1]) == 127
1197 || INTVAL (operands[1]) == 255)"
1198 [(set (match_dup 0)
1199 (and:SI (match_dup 0)
1200 (match_dup 4)))
1201 (set (cc0) (compare (match_dup 0)
1202 (const_int 0)))
1203 (set (pc)
1204 (if_then_else (match_dup 2)
1205 (label_ref (match_dup 3))
1206 (pc)))]
1207 {
1208 operands[4] = GEN_INT (~INTVAL (operands[1]));
1209 })
1210
1211 ;; Transform
1212 ;;
1213 ;; cmp.l #15,er0
1214 ;; bhi .L1
1215 ;;
1216 ;; into
1217 ;;
1218 ;; and #240,r0l
1219 ;; mov.l er0,er0
1220 ;; bne .L1
1221
1222 (define_peephole2
1223 [(set (cc0)
1224 (compare (match_operand:SI 0 "register_operand" "")
1225 (match_operand:SI 1 "const_int_operand" "")))
1226 (set (pc)
1227 (if_then_else (match_operator 2 "gtuleu_operator"
1228 [(cc0) (const_int 0)])
1229 (label_ref (match_operand 3 "" ""))
1230 (pc)))]
1231 "peep2_reg_dead_p (1, operands[0])
1232 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
1233 || INTVAL (operands[1]) == 7
1234 || INTVAL (operands[1]) == 15
1235 || INTVAL (operands[1]) == 31
1236 || INTVAL (operands[1]) == 63
1237 || INTVAL (operands[1]) == 127
1238 || INTVAL (operands[1]) == 255)"
1239 [(set (match_dup 0)
1240 (and:SI (match_dup 0)
1241 (match_dup 4)))
1242 (set (cc0) (compare (match_dup 0)
1243 (const_int 0)))
1244 (set (pc)
1245 (if_then_else (match_dup 5)
1246 (label_ref (match_dup 3))
1247 (pc)))]
1248 {
1249 operands[4] = GEN_INT (~INTVAL (operands[1]));
1250 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
1251 VOIDmode, cc0_rtx, const0_rtx);
1252 })
1253
1254 ;; Transform
1255 ;;
1256 ;; cmp.l #65535,er0
1257 ;; bgt .L1
1258 ;;
1259 ;; into
1260 ;;
1261 ;; mov.l e0,e0
1262 ;; bgt .L1
1263
1264 (define_peephole2
1265 [(set (cc0)
1266 (compare (match_operand:SI 0 "register_operand" "")
1267 (const_int 65535)))
1268 (set (pc)
1269 (if_then_else (match_operator 1 "gtle_operator"
1270 [(cc0) (const_int 0)])
1271 (label_ref (match_operand 2 "" ""))
1272 (pc)))]
1273 ""
1274 [(set (cc0) (compare (and:SI (match_dup 0)
1275 (const_int -65536))
1276 (const_int 0)))
1277 (set (pc)
1278 (if_then_else (match_dup 1)
1279 (label_ref (match_dup 2))
1280 (pc)))]
1281 "")
1282
1283 ;; Transform
1284 ;;
1285 ;; cmp.l #65535,er0
1286 ;; bhi .L1
1287 ;;
1288 ;; into
1289 ;;
1290 ;; mov.l e0,e0
1291 ;; bne .L1
1292
1293 (define_peephole2
1294 [(set (cc0)
1295 (compare (match_operand:SI 0 "register_operand" "")
1296 (const_int 65535)))
1297 (set (pc)
1298 (if_then_else (match_operator 1 "gtuleu_operator"
1299 [(cc0) (const_int 0)])
1300 (label_ref (match_operand 2 "" ""))
1301 (pc)))]
1302 ""
1303 [(set (cc0) (compare (and:SI (match_dup 0)
1304 (const_int -65536))
1305 (const_int 0)))
1306 (set (pc)
1307 (if_then_else (match_dup 3)
1308 (label_ref (match_dup 2))
1309 (pc)))]
1310 {
1311 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
1312 VOIDmode, cc0_rtx, const0_rtx);
1313 })
1314
1315 ;; Transform
1316 ;;
1317 ;; cmp.l #1,er0
1318 ;; beq .L1
1319 ;;
1320 ;; into
1321 ;;
1322 ;; mov.l er0,er1
1323 ;; dec.l #1,er1
1324 ;; beq .L1
1325
1326 ;; We avoid this transformation if we see more than one copy of the
1327 ;; same compare insn.
1328
1329 (define_peephole2
1330 [(match_scratch:SI 4 "r")
1331 (set (cc0)
1332 (compare (match_operand:SI 0 "register_operand" "")
1333 (match_operand:SI 1 "incdec_operand" "")))
1334 (set (pc)
1335 (if_then_else (match_operator 3 "eqne_operator"
1336 [(cc0) (const_int 0)])
1337 (label_ref (match_operand 2 "" ""))
1338 (pc)))]
1339 "INTVAL (operands[1]) != 0
1340 && !peep2_reg_dead_p (1, operands[0])
1341 && !same_cmp_following_p (insn)"
1342 [(set (match_dup 4)
1343 (match_dup 0))
1344 (set (match_dup 4)
1345 (unspec:SI [(match_dup 4)
1346 (match_dup 5)]
1347 UNSPEC_INCDEC))
1348 (set (cc0) (compare (match_dup 4)
1349 (const_int 0)))
1350 (set (pc)
1351 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
1352 (label_ref (match_dup 2))
1353 (pc)))]
1354 {
1355 operands[5] = GEN_INT (- INTVAL (operands[1]));
1356 })
1357
1358 ;; Narrow the mode of testing if possible.
1359
1360 (define_peephole2
1361 [(set (match_operand:HSI 0 "register_operand" "")
1362 (and:HSI (match_dup 0)
1363 (match_operand:HSI 1 "const_int_operand" "")))
1364 (set (cc0) (compare (match_dup 0)
1365 (const_int 0)))
1366 (set (pc)
1367 (if_then_else (match_operator 3 "eqne_operator"
1368 [(cc0) (const_int 0)])
1369 (label_ref (match_operand 2 "" ""))
1370 (pc)))]
1371 "((const_int_qi_operand (operands[1], QImode)
1372 || (GET_MODE (operands[0]) == SImode
1373 && const_int_hi_operand (operands[1], HImode)))
1374 && peep2_reg_dead_p (2, operands[0]))"
1375 [(set (match_dup 4) (match_dup 6))
1376 (set (cc0) (compare (match_dup 4)
1377 (const_int 0)))
1378 (set (pc)
1379 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
1380 (label_ref (match_dup 2))
1381 (pc)))]
1382 {
1383 enum machine_mode mode;
1384
1385 mode = const_int_qi_operand (operands[1], QImode) ? QImode : HImode;
1386 operands[4] = gen_rtx_REG (mode, REGNO (operands[0]));
1387 operands[5] = gen_int_mode (INTVAL (operands[1]), mode);
1388 operands[6] = gen_rtx_AND (mode, operands[4], operands[5]);
1389 })
1390
1391 ;; These triggers right at the end of allocation of locals in the
1392 ;; prologue (and possibly at other places).
1393
1394 ;; stack adjustment of -4, generate one push
1395 ;;
1396 ;; before : 6 bytes
1397 ;; after : 4 bytes
1398
1399 (define_peephole2
1400 [(set (reg:SI SP_REG)
1401 (plus:SI (reg:SI SP_REG)
1402 (const_int -4)))
1403 (set (mem:SFI (reg:SI SP_REG))
1404 (match_operand:SFI 0 "register_operand" ""))]
1405 "!TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
1406 [(set (mem:SFI (pre_dec:SI (reg:SI SP_REG)))
1407 (match_dup 0))])
1408
1409 ;; stack adjustment of -8, generate one push
1410 ;;
1411 ;; before : 8 bytes
1412 ;; after : 6 bytes
1413
1414 (define_peephole2
1415 [(set (reg:SI SP_REG)
1416 (plus:SI (reg:SI SP_REG)
1417 (const_int -8)))
1418 (set (mem:SFI (reg:SI SP_REG))
1419 (match_operand:SFI 0 "register_operand" ""))]
1420 "!TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
1421 [(set (reg:SI SP_REG)
1422 (plus:SI (reg:SI SP_REG)
1423 (const_int -4)))
1424 (set (mem:SFI (pre_dec:SI (reg:SI SP_REG)))
1425 (match_dup 0))])
1426
1427 ;; stack adjustment of -12, generate one push
1428 ;;
1429 ;; before : 10 bytes
1430 ;; after : 8 bytes
1431
1432 (define_peephole2
1433 [(set (reg:SI SP_REG)
1434 (plus:SI (reg:SI SP_REG)
1435 (const_int -12)))
1436 (set (mem:SFI (reg:SI SP_REG))
1437 (match_operand:SFI 0 "register_operand" ""))]
1438 "!TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
1439 [(set (reg:SI SP_REG)
1440 (plus:SI (reg:SI SP_REG)
1441 (const_int -4)))
1442 (set (reg:SI SP_REG)
1443 (plus:SI (reg:SI SP_REG)
1444 (const_int -4)))
1445 (set (mem:SFI (pre_dec:SI (reg:SI SP_REG)))
1446 (match_dup 0))])
1447
1448 ;; Transform
1449 ;;
1450 ;; mov dst,reg
1451 ;; op reg
1452 ;; mov reg,dst
1453 ;;
1454 ;; into
1455 ;;
1456 ;; op dst
1457 ;;
1458 ;; if "reg" dies at the end of the sequence.
1459
1460 (define_peephole2
1461 [(set (match_operand 0 "register_operand" "")
1462 (match_operand 1 "memory_operand" ""))
1463 (set (match_dup 0)
1464 (match_operator 2 "h8sx_unary_memory_operator"
1465 [(match_dup 0)]))
1466 (set (match_operand 3 "memory_operand" "")
1467 (match_dup 0))]
1468 "TARGET_H8300SX
1469 && peep2_reg_dead_p (3, operands[0])
1470 && !reg_overlap_mentioned_p (operands[0], operands[3])
1471 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
1472 [(set (match_dup 3)
1473 (match_dup 4))]
1474 {
1475 operands[4] = shallow_copy_rtx (operands[2]);
1476 XEXP (operands[4], 0) = operands[1];
1477 })
1478
1479 ;; Transform
1480 ;;
1481 ;; mov src1,reg
1482 ;; cmp reg,src2
1483 ;;
1484 ;; into
1485 ;;
1486 ;; cmp src1,src2
1487 ;;
1488 ;; if "reg" dies in the comparison.
1489
1490 (define_peephole2
1491 [(set (match_operand 0 "register_operand" "")
1492 (match_operand 1 "h8300_dst_operand" ""))
1493 (set (cc0)
1494 (compare (match_dup 0)
1495 (match_operand 2 "h8300_src_operand" "")))]
1496 "TARGET_H8300SX
1497 && peep2_reg_dead_p (2, operands[0])
1498 && !reg_overlap_mentioned_p (operands[0], operands[2])
1499 && operands[2] != const0_rtx"
1500 [(set (cc0)
1501 (compare (match_dup 1)
1502 (match_dup 2)))])
1503
1504 ;; Likewise for the second operand.
1505
1506 (define_peephole2
1507 [(set (match_operand 0 "register_operand" "")
1508 (match_operand 1 "h8300_src_operand" ""))
1509 (set (cc0)
1510 (compare (match_operand 2 "h8300_dst_operand" "")
1511 (match_dup 0)))]
1512 "TARGET_H8300SX
1513 && peep2_reg_dead_p (2, operands[0])
1514 && !reg_overlap_mentioned_p (operands[0], operands[2])"
1515 [(set (cc0)
1516 (compare (match_dup 2)
1517 (match_dup 1)))])
1518
1519 ;; Combine two moves.
1520
1521 (define_peephole2
1522 [(set (match_operand 0 "register_operand" "")
1523 (match_operand 1 "h8300_src_operand" ""))
1524 (set (match_operand 2 "h8300_dst_operand" "")
1525 (match_dup 0))]
1526 "TARGET_H8300SX
1527 && peep2_reg_dead_p (2, operands[0])
1528 && !reg_overlap_mentioned_p (operands[0], operands[2])"
1529 [(set (match_dup 2)
1530 (match_dup 1))])
1531
1532
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