1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999
3 Free Software Foundation, Inc.
4 Contributed by Steven McGeady, Intel Corp.
5 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
6 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
38 #include "insn-codes.h"
45 /* Save the operands last given to a compare for use when we
46 generate a scc or bcc insn. */
48 rtx i960_compare_op0
, i960_compare_op1
;
50 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
53 static int i960_maxbitalignment
;
54 static int i960_last_maxbitalignment
;
56 /* Used to implement switching between MEM and ALU insn types, for better
57 C series performance. */
59 enum insn_types i960_last_insn_type
;
61 /* The leaf-procedure return register. Set only if this is a leaf routine. */
63 static int i960_leaf_ret_reg
;
65 /* True if replacing tail calls with jumps is OK. */
67 static int tail_call_ok
;
69 /* A string containing a list of insns to emit in the epilogue so as to
70 restore all registers saved by the prologue. Created by the prologue
71 code as it saves registers away. */
73 char epilogue_string
[1000];
75 /* A unique number (per function) for return labels. */
77 static int ret_label
= 0;
79 /* This is true if FNDECL is either a varargs or a stdarg function.
80 This is used to help identify functions that use an argument block. */
82 #define VARARGS_STDARG_FUNCTION(FNDECL) \
83 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
84 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
85 || current_function_varargs)
87 /* Handle pragmas for compatibility with Intel's compilers. */
89 /* ??? This is incomplete, since it does not handle all pragmas that the
90 intel compilers understand. */
93 process_pragma (p_getc
, p_ungetc
, pname
)
94 int (* p_getc
) PROTO ((void));
95 void (* p_ungetc
) PROTO ((int));
104 /* Should be pragma 'far' or equivalent for callx/balx here. */
105 if (strcmp (pname
, "align") != 0)
112 while (c
== ' ' || c
== '\t');
117 while (c
>= '0' && c
<= '9')
119 if (s
< buf
+ sizeof buf
- 1)
126 /* We had to read a non-numerical character to get out of the
127 while loop---often a newline. So, we have to put it back to
128 make sure we continue to parse everything properly. */
137 /* Return to last alignment. */
138 align
= i960_last_maxbitalignment
/ 8;
145 i960_last_maxbitalignment
= i960_maxbitalignment
;
146 i960_maxbitalignment
= align
* 8;
150 /* Silently ignore bad values. */
154 /* NOTE: ic960 R3.0 pragma align definition:
156 #pragma align [(size)] | (identifier=size[,...])
157 #pragma noalign [(identifier)[,...]]
159 (all parens are optional)
161 - size is [1,2,4,8,16]
162 - noalign means size==1
163 - applies only to component elements of a struct (and union?)
164 - identifier applies to structure tag (only)
165 - missing identifier means next struct
167 - alignment rules for bitfields need more investigation */
172 /* Initialize variables before compiling any files. */
177 if (TARGET_IC_COMPAT2_0
)
179 i960_maxbitalignment
= 8;
180 i960_last_maxbitalignment
= 128;
184 i960_maxbitalignment
= 128;
185 i960_last_maxbitalignment
= 8;
189 /* Return true if OP can be used as the source of an fp move insn. */
192 fpmove_src_operand (op
, mode
)
194 enum machine_mode mode
;
196 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
200 /* Return true if OP is a register or zero. */
203 reg_or_zero_operand (op
, mode
)
205 enum machine_mode mode
;
207 return register_operand (op
, mode
) || op
== const0_rtx
;
211 /* Return truth value of whether OP can be used as an operands in a three
212 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
215 arith_operand (op
, mode
)
217 enum machine_mode mode
;
219 return (register_operand (op
, mode
) || literal (op
, mode
));
222 /* Return truth value of whether OP can be used as an operands in a three
223 address logic insn, possibly complementing OP, of mode MODE. */
226 logic_operand (op
, mode
)
228 enum machine_mode mode
;
230 return (register_operand (op
, mode
)
231 || (GET_CODE (op
) == CONST_INT
232 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
235 /* Return true if OP is a register or a valid floating point literal. */
238 fp_arith_operand (op
, mode
)
240 enum machine_mode mode
;
242 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
245 /* Return true is OP is a register or a valid signed integer literal. */
248 signed_arith_operand (op
, mode
)
250 enum machine_mode mode
;
252 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
255 /* Return truth value of whether OP is a integer which fits the
256 range constraining immediate operands in three-address insns. */
261 enum machine_mode mode
;
263 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
266 /* Return true if OP is a float constant of 1. */
269 fp_literal_one (op
, mode
)
271 enum machine_mode mode
;
273 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
276 /* Return true if OP is a float constant of 0. */
279 fp_literal_zero (op
, mode
)
281 enum machine_mode mode
;
283 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
286 /* Return true if OP is a valid floating point literal. */
291 enum machine_mode mode
;
293 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
296 /* Return true if OP is a valid signed immediate constant. */
299 signed_literal(op
, mode
)
301 enum machine_mode mode
;
303 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
306 /* Return truth value of statement that OP is a symbolic memory
307 operand of mode MODE. */
310 symbolic_memory_operand (op
, mode
)
312 enum machine_mode mode
;
314 if (GET_CODE (op
) == SUBREG
)
315 op
= SUBREG_REG (op
);
316 if (GET_CODE (op
) != MEM
)
319 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
320 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
323 /* Return truth value of whether OP is EQ or NE. */
328 enum machine_mode mode
;
330 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
333 /* OP is an integer register or a constant. */
336 arith32_operand (op
, mode
)
338 enum machine_mode mode
;
340 if (register_operand (op
, mode
))
342 return (CONSTANT_P (op
));
345 /* Return true if OP is an integer constant which is a power of 2. */
348 power2_operand (op
,mode
)
350 enum machine_mode mode
;
352 if (GET_CODE (op
) != CONST_INT
)
355 return exact_log2 (INTVAL (op
)) >= 0;
358 /* Return true if OP is an integer constant which is the complement of a
362 cmplpower2_operand (op
, mode
)
364 enum machine_mode mode
;
366 if (GET_CODE (op
) != CONST_INT
)
369 return exact_log2 (~ INTVAL (op
)) >= 0;
372 /* If VAL has only one bit set, return the index of that bit. Otherwise
381 for (i
= 0; val
!= 0; i
++, val
>>= 1)
393 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
394 The return value indicates how many consecutive non-zero bits exist
395 if this is a mask. This is the same as the next function, except that
396 it does not indicate what the start and stop bit positions are. */
402 register int start
, end
, i
;
405 for (i
= 0; val
!= 0; val
>>= 1, i
++)
415 /* Still looking for the first bit. */
419 /* We've seen the start of a bit sequence, and now a zero. There
420 must be more one bits, otherwise we would have exited the loop.
421 Therefore, it is not a mask. */
426 /* The bit string has ones from START to END bit positions only. */
427 return end
- start
+ 1;
430 /* If VAL is a mask, then return nonzero, with S set to the starting bit
431 position and E set to the ending bit position of the mask. The return
432 value indicates how many consecutive bits exist in the mask. This is
433 the same as the previous function, except that it also indicates the
434 start and end bit positions of the mask. */
441 register int start
, end
, i
;
445 for (i
= 0; val
!= 0; val
>>= 1, i
++)
456 /* Still looking for the first bit. */
460 /* We've seen the start of a bit sequence, and now a zero. There
461 must be more one bits, otherwise we would have exited the loop.
462 Therefor, it is not a mask. */
471 /* The bit string has ones from START to END bit positions only. */
474 return ((start
< 0) ? 0 : end
- start
+ 1);
477 /* Return the machine mode to use for a comparison. */
480 select_cc_mode (op
, x
)
484 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
489 /* X and Y are two things to compare using CODE. Emit the compare insn and
490 return the rtx for register 36 in the proper mode. */
493 gen_compare_reg (code
, x
, y
)
498 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
499 enum machine_mode mode
500 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
504 if (! arith_operand (x
, mode
))
505 x
= force_reg (SImode
, x
);
506 if (! arith_operand (y
, mode
))
507 y
= force_reg (SImode
, y
);
510 cc_reg
= gen_rtx (REG
, ccmode
, 36);
511 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
512 gen_rtx (COMPARE
, ccmode
, x
, y
)));
517 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
518 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
519 are 4. Indexed addresses are cost 6. */
521 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
524 i960_address_cost (x
)
528 /* Handled before calling here. */
529 if (GET_CODE (x
) == REG
)
532 /* This is a MEMA operand -- it's free. */
533 if (GET_CODE (x
) == CONST_INT
535 && INTVAL (x
) < 4096)
538 if (GET_CODE (x
) == PLUS
)
540 rtx base
= XEXP (x
, 0);
541 rtx offset
= XEXP (x
, 1);
543 if (GET_CODE (base
) == SUBREG
)
544 base
= SUBREG_REG (base
);
545 if (GET_CODE (offset
) == SUBREG
)
546 offset
= SUBREG_REG (offset
);
548 if (GET_CODE (base
) == REG
)
550 if (GET_CODE (offset
) == REG
)
552 if (GET_CODE (offset
) == CONST_INT
)
554 if ((unsigned)INTVAL (offset
) < 2047)
558 if (CONSTANT_P (offset
))
561 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
564 /* This is an invalid address. The return value doesn't matter, but
565 for convenience we make this more expensive than anything else. */
568 if (GET_CODE (x
) == MULT
)
571 /* Symbol_refs and other unrecognized addresses are cost 4. */
575 /* Emit insns to move operands[1] into operands[0].
577 Return 1 if we have written out everything that needs to be done to
578 do the move. Otherwise, return 0 and the caller will emit the move
582 emit_move_sequence (operands
, mode
)
584 enum machine_mode mode
;
586 /* We can only store registers to memory. */
588 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
589 && (operands
[1] != const0_rtx
|| current_function_args_size
590 || current_function_varargs
|| current_function_stdarg
591 || rtx_equal_function_value_matters
))
592 /* Here we use the same test as movsi+1 pattern -- see i960.md. */
593 operands
[1] = force_reg (mode
, operands
[1]);
595 /* Storing multi-word values in unaligned hard registers to memory may
596 require a scratch since we have to store them a register at a time and
597 adding 4 to the memory address may not yield a valid insn. */
598 /* ??? We don't always need the scratch, but that would complicate things.
600 /* ??? We must also handle stores to pseudos here, because the pseudo may be
601 replaced with a MEM later. This would be cleaner if we didn't have
602 a separate pattern for unaligned DImode/TImode stores. */
603 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
604 && (GET_CODE (operands
[0]) == MEM
605 || (GET_CODE (operands
[0]) == REG
606 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
607 && GET_CODE (operands
[1]) == REG
608 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
609 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
611 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
613 gen_rtx (SET
, VOIDmode
,
614 operands
[0], operands
[1]),
615 gen_rtx (CLOBBER
, VOIDmode
,
616 gen_rtx (SCRATCH
, Pmode
)))));
623 /* Output assembler to move a double word value. */
626 i960_output_move_double (dst
, src
)
631 if (GET_CODE (dst
) == REG
632 && GET_CODE (src
) == REG
)
634 if ((REGNO (src
) & 1)
635 || (REGNO (dst
) & 1))
637 /* We normally copy the low-numbered register first. However, if
638 the second source register is the same as the first destination
639 register, we must copy in the opposite order. */
640 if (REGNO (src
) + 1 == REGNO (dst
))
641 return "mov %D1,%D0\n\tmov %1,%0";
643 return "mov %1,%0\n\tmov %D1,%D0";
648 else if (GET_CODE (dst
) == REG
649 && GET_CODE (src
) == CONST_INT
650 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
653 return "mov %1,%0\n\tmov 0,%D0";
657 else if (GET_CODE (dst
) == REG
658 && GET_CODE (src
) == MEM
)
662 /* One can optimize a few cases here, but you have to be
663 careful of clobbering registers used in the address and
667 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 1);
668 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
669 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
670 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
676 else if (GET_CODE (dst
) == MEM
677 && GET_CODE (src
) == REG
)
682 operands
[1] = adj_offsettable_operand (dst
, UNITS_PER_WORD
);
683 if (! memory_address_p (word_mode
, XEXP (operands
[1], 0)))
686 output_asm_insn ("st %2,%0\n\tst %D2,%1", operands
);
695 /* Output assembler to move a double word zero. */
698 i960_output_move_double_zero (dst
)
705 operands
[1] = adj_offsettable_operand (dst
, 4);
706 output_asm_insn ("st g14,%0\n\tst g14,%1", operands
);
711 /* Output assembler to move a quad word value. */
714 i960_output_move_quad (dst
, src
)
719 if (GET_CODE (dst
) == REG
720 && GET_CODE (src
) == REG
)
722 if ((REGNO (src
) & 3)
723 || (REGNO (dst
) & 3))
725 /* We normally copy starting with the low numbered register.
726 However, if there is an overlap such that the first dest reg
727 is <= the last source reg but not < the first source reg, we
728 must copy in the opposite order. */
729 if (REGNO (dst
) <= REGNO (src
) + 3
730 && REGNO (dst
) >= REGNO (src
))
731 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
733 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
738 else if (GET_CODE (dst
) == REG
739 && GET_CODE (src
) == CONST_INT
740 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
743 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
747 else if (GET_CODE (dst
) == REG
748 && GET_CODE (src
) == MEM
)
752 /* One can optimize a few cases here, but you have to be
753 careful of clobbering registers used in the address and
757 operands
[2] = gen_rtx (REG
, Pmode
, REGNO (dst
) + 3);
758 operands
[3] = gen_rtx (MEM
, word_mode
, operands
[2]);
759 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
760 operands
[5] = adj_offsettable_operand (operands
[4], UNITS_PER_WORD
);
761 operands
[6] = adj_offsettable_operand (operands
[5], UNITS_PER_WORD
);
762 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
768 else if (GET_CODE (dst
) == MEM
769 && GET_CODE (src
) == REG
)
774 operands
[1] = adj_offsettable_operand (dst
, UNITS_PER_WORD
);
775 operands
[2] = adj_offsettable_operand (dst
, 2*UNITS_PER_WORD
);
776 operands
[3] = adj_offsettable_operand (dst
, 3*UNITS_PER_WORD
);
777 if (! memory_address_p (word_mode
, XEXP (operands
[3], 0)))
780 output_asm_insn ("st %4,%0\n\tst %D4,%1\n\tst %E4,%2\n\tst %F4,%3", operands
);
789 /* Output assembler to move a quad word zero. */
792 i960_output_move_quad_zero (dst
)
799 operands
[1] = adj_offsettable_operand (dst
, 4);
800 operands
[2] = adj_offsettable_operand (dst
, 8);
801 operands
[3] = adj_offsettable_operand (dst
, 12);
802 output_asm_insn ("st g14,%0\n\tst g14,%1\n\tst g14,%2\n\tst g14,%3", operands
);
808 /* Emit insns to load a constant to non-floating point registers.
809 Uses several strategies to try to use as few insns as possible. */
812 i960_output_ldconst (dst
, src
)
813 register rtx dst
, src
;
816 register unsigned rsrc2
;
817 enum machine_mode mode
= GET_MODE (dst
);
820 operands
[0] = operands
[2] = dst
;
821 operands
[1] = operands
[3] = src
;
823 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
824 must be a ldconst insn. */
826 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
828 output_asm_insn ("ldconst %1,%0", operands
);
831 else if (mode
== XFmode
)
837 if (fp_literal_zero (src
, XFmode
))
840 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
841 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
843 output_asm_insn ("# ldconst %1,%0",operands
);
845 for (i
= 0; i
< 3; i
++)
847 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + i
);
848 operands
[1] = GEN_INT (value_long
[i
]);
849 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
855 else if (mode
== DFmode
)
859 if (fp_literal_zero (src
, DFmode
))
862 split_double (src
, &first
, &second
);
864 output_asm_insn ("# ldconst %1,%0",operands
);
866 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
868 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
870 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
871 operands
[1] = second
;
872 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
876 else if (mode
== SFmode
)
881 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
882 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
884 output_asm_insn ("# ldconst %1,%0",operands
);
885 operands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
));
886 operands
[1] = GEN_INT (value
);
887 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
891 else if (mode
== TImode
)
893 /* ??? This is currently not handled at all. */
896 /* Note: lowest order word goes in lowest numbered reg. */
897 rsrc1
= INTVAL (src
);
898 if (rsrc1
>= 0 && rsrc1
< 32)
901 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
902 /* Go pick up the low-order word. */
904 else if (mode
== DImode
)
906 rtx upperhalf
, lowerhalf
, xoperands
[2];
908 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
909 split_double (src
, &lowerhalf
, &upperhalf
);
914 /* Note: lowest order word goes in lowest numbered reg. */
915 /* Numbers from 0 to 31 can be handled with a single insn. */
916 rsrc1
= INTVAL (lowerhalf
);
917 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
920 /* Output the upper half with a recursive call. */
921 xoperands
[0] = gen_rtx (REG
, SImode
, REGNO (dst
) + 1);
922 xoperands
[1] = upperhalf
;
923 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
925 /* The lower word is emitted as normally. */
929 rsrc1
= INTVAL (src
);
935 else if (mode
== HImode
)
944 /* ldconst 0..31,X -> mov 0..31,X */
947 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
952 /* ldconst 32..63,X -> add 31,nn,X */
955 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
957 operands
[1] = GEN_INT (rsrc1
- 31);
958 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
964 /* ldconst -1..-31 -> sub 0,0..31,X */
967 /* return 'sub -(%1),0,%0' */
968 operands
[1] = GEN_INT (- rsrc1
);
969 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
973 /* ldconst -32 -> not 31,X */
976 operands
[1] = GEN_INT (~rsrc1
);
977 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
982 /* If const is a single bit. */
983 if (bitpos (rsrc1
) >= 0)
985 operands
[1] = GEN_INT (bitpos (rsrc1
));
986 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
990 /* If const is a bit string of less than 6 bits (1..31 shifted). */
995 if (bitstr (rsrc1
, &s
, &e
) < 6)
997 rsrc2
= ((unsigned int) rsrc1
) >> s
;
998 operands
[1] = GEN_INT (rsrc2
);
999 operands
[2] = GEN_INT (s
);
1000 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
1005 /* Unimplemented cases:
1006 const is in range 0..31 but rotated around end of word:
1007 ror 31,3,g0 -> ldconst 0xe0000003,g0
1009 and any 2 instruction cases that might be worthwhile */
1011 output_asm_insn ("ldconst %1,%0", operands
);
1015 /* Determine if there is an opportunity for a bypass optimization.
1016 Bypass succeeds on the 960K* if the destination of the previous
1017 instruction is the second operand of the current instruction.
1018 Bypass always succeeds on the C*.
1020 Return 1 if the pattern should interchange the operands.
1022 CMPBR_FLAG is true if this is for a compare-and-branch insn.
1023 OP1 and OP2 are the two source operands of a 3 operand insn. */
1026 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
1027 register rtx insn
, op1
, op2
;
1030 register rtx prev_insn
, prev_dest
;
1032 if (TARGET_C_SERIES
)
1035 /* Can't do this if op1 isn't a register. */
1039 /* Can't do this for a compare-and-branch if both ops aren't regs. */
1040 if (cmpbr_flag
&& ! REG_P (op2
))
1043 prev_insn
= prev_real_insn (insn
);
1045 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
1046 && GET_CODE (PATTERN (prev_insn
)) == SET
)
1048 prev_dest
= SET_DEST (PATTERN (prev_insn
));
1049 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
1050 || (GET_CODE (prev_dest
) == SUBREG
1051 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
1052 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
1058 /* Output the code which declares the function name. This also handles
1059 leaf routines, which have special requirements, and initializes some
1060 global variables. */
1063 i960_function_name_declare (file
, name
, fndecl
)
1072 /* Increment global return label. */
1076 /* Compute whether tail calls and leaf routine optimizations can be performed
1077 for this function. */
1079 if (TARGET_TAILCALL
)
1084 if (TARGET_LEAFPROC
)
1089 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1090 argblock, because argblock uses g14 implicitly. */
1092 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1098 /* See if caller passes in an address to return value. */
1100 if (aggregate_value_p (DECL_RESULT (fndecl
)))
1106 /* Can not use tail calls or make this a leaf routine if there is a non
1109 if (get_frame_size () != 0)
1112 /* I don't understand this condition, and do not think that it is correct.
1113 Apparently this is just checking whether the frame pointer is used, and
1114 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1117 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1118 if (GET_CODE (insn
) == INSN
1119 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1125 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1128 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1129 if (GET_CODE (insn
) == CALL_INSN
)
1135 /* Can not be a leaf routine if any non-call clobbered registers are
1136 used in this function. */
1139 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1140 if (regs_ever_live
[i
]
1141 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1143 /* Global registers. */
1144 if (i
< 16 && i
> 7 && i
!= 13)
1146 /* Local registers. */
1151 /* Now choose a leaf return register, if we can find one, and if it is
1152 OK for this to be a leaf routine. */
1154 i960_leaf_ret_reg
= -1;
1156 if (optimize
&& leaf_proc_ok
)
1158 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1159 if (regs_ever_live
[i
] == 0)
1161 i960_leaf_ret_reg
= i
;
1162 regs_ever_live
[i
] = 1;
1167 /* Do this after choosing the leaf return register, so it will be listed
1168 if one was chosen. */
1170 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1171 fprintf (file
, "\t# Registers used: ");
1173 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1175 if (regs_ever_live
[i
])
1177 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1179 if (i
> 15 && j
== 0)
1181 fprintf (file
,"\n\t#\t\t ");
1187 fprintf (file
, "\n");
1189 if (i960_leaf_ret_reg
>= 0)
1191 /* Make it a leaf procedure. */
1193 if (TREE_PUBLIC (fndecl
))
1194 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1196 fprintf (file
, "\t.leafproc\t");
1197 assemble_name (file
, name
);
1198 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1199 ASM_OUTPUT_LABEL (file
, name
);
1200 fprintf (file
, "\tlda Li960R%d,g14\n", ret_label
);
1201 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1202 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1204 if (TARGET_C_SERIES
)
1206 fprintf (file
, "\tlda 0,g14\n");
1207 i960_last_insn_type
= I_TYPE_MEM
;
1211 fprintf (file
, "\tmov 0,g14\n");
1212 i960_last_insn_type
= I_TYPE_REG
;
1217 ASM_OUTPUT_LABEL (file
, name
);
1218 i960_last_insn_type
= I_TYPE_CTRL
;
1222 /* Compute and return the frame size. */
1225 compute_frame_size (size
)
1229 int outgoing_args_size
= current_function_outgoing_args_size
;
1231 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1232 as size is concerned. */
1233 actual_fsize
= (size
+ 15) & -16;
1234 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1236 return actual_fsize
;
1239 /* Here register group is range of registers which can be moved by
1240 one i960 instruction. */
1248 /* The following functions forms the biggest as possible register
1249 groups with registers in STATE. REGS contain states of the
1250 registers in range [start, finish_reg). The function returns the
1251 number of groups formed. */
1253 i960_form_reg_groups (start_reg
, finish_reg
, regs
, state
, reg_groups
)
1258 struct reg_group
*reg_groups
;
1263 for (i
= start_reg
; i
< finish_reg
; )
1265 if (regs
[i
] != state
)
1270 else if (i
% 2 != 0 || regs
[i
+ 1] != state
)
1271 reg_groups
[nw
].length
= 1;
1272 else if (i
% 4 != 0 || regs
[i
+ 2] != state
)
1273 reg_groups
[nw
].length
= 2;
1274 else if (regs
[i
+ 3] != state
)
1275 reg_groups
[nw
].length
= 3;
1277 reg_groups
[nw
].length
= 4;
1278 reg_groups
[nw
].start_reg
= i
;
1279 i
+= reg_groups
[nw
].length
;
1285 /* We sort register winodws in descending order by length. */
1287 i960_reg_group_compare (group1
, group2
)
1291 struct reg_group
*w1
= group1
;
1292 struct reg_group
*w2
= group2
;
1294 if (w1
->length
> w2
->length
)
1296 else if (w1
->length
< w2
->length
)
1302 /* Split the first register group in REG_GROUPS on subgroups one of
1303 which will contain SUBGROUP_LENGTH registers. The function
1304 returns new number of winodws. */
1306 i960_split_reg_group (reg_groups
, nw
, subgroup_length
)
1307 struct reg_group
*reg_groups
;
1309 int subgroup_length
;
1311 if (subgroup_length
< reg_groups
->length
- subgroup_length
)
1312 /* This guarantees correct alignments of the two subgroups for
1313 i960 (see spliting for the group length 2, 3, 4). More
1314 generalized algorithm would require splitting the group more
1316 subgroup_length
= reg_groups
->length
- subgroup_length
;
1317 /* More generalized algorithm would require to try merging
1318 subgroups here. But in case i960 it always results in failure
1319 because of register group alignment. */
1320 reg_groups
[nw
].length
= reg_groups
->length
- subgroup_length
;
1321 reg_groups
[nw
].start_reg
= reg_groups
->start_reg
+ subgroup_length
;
1323 reg_groups
->length
= subgroup_length
;
1324 qsort (reg_groups
, nw
, sizeof (struct reg_group
), i960_reg_group_compare
);
1328 /* Output code for the function prologue. */
1331 i960_function_prologue (file
, size
)
1335 register int i
, j
, nr
;
1338 int actual_fsize
, offset
;
1340 struct reg_group
*g
, *l
;
1342 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1344 int regs
[FIRST_PSEUDO_REGISTER
];
1345 /* All global registers (which must be saved) divided by groups. */
1346 struct reg_group global_reg_groups
[16];
1347 /* All local registers (which are available) divided by groups. */
1348 struct reg_group local_reg_groups
[16];
1351 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1352 if (regs_ever_live
[i
]
1353 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12))
1354 /* No need to save the static chain pointer. */
1355 && ! (i
== STATIC_CHAIN_REGNUM
&& current_function_needs_context
))
1358 /* Count global registers that need saving. */
1365 epilogue_string
[0] = '\0';
1367 if (profile_flag
|| profile_block_flag
)
1369 /* When profiling, we may use registers 20 to 27 to save arguments, so
1370 they can't be used here for saving globals. J is the number of
1371 argument registers the mcount call will save. */
1372 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1375 for (i
= 20; i
<= j
+ 20; i
++)
1379 gnw
= i960_form_reg_groups (0, 16, regs
, -1, global_reg_groups
);
1380 lnw
= i960_form_reg_groups (19, 32, regs
, 0, local_reg_groups
);
1381 qsort (global_reg_groups
, gnw
, sizeof (struct reg_group
),
1382 i960_reg_group_compare
);
1383 qsort (local_reg_groups
, lnw
, sizeof (struct reg_group
),
1384 i960_reg_group_compare
);
1385 for (g
= global_reg_groups
, l
= local_reg_groups
; lnw
!= 0 && gnw
!= 0;)
1387 if (g
->length
== l
->length
)
1389 fprintf (file
, "\tmov%s %s,%s\n",
1390 ((g
->length
== 4) ? "q" :
1391 (g
->length
== 3) ? "t" :
1392 (g
->length
== 2) ? "l" : ""),
1393 reg_names
[g
->start_reg
], reg_names
[l
->start_reg
]);
1394 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1395 ((g
->length
== 4) ? "q" :
1396 (g
->length
== 3) ? "t" :
1397 (g
->length
== 2) ? "l" : ""),
1398 reg_names
[l
->start_reg
], reg_names
[g
->start_reg
]);
1399 strcat (epilogue_string
, tmpstr
);
1400 n_iregs
-= g
->length
;
1401 for (i
= 0; i
< g
->length
; i
++)
1403 regs
[i
+ g
->start_reg
] = 1;
1404 regs
[i
+ l
->start_reg
] = -1;
1405 regs_ever_live
[i
+ l
->start_reg
] = 1;
1412 else if (g
->length
> l
->length
)
1413 gnw
= i960_split_reg_group (g
, gnw
, l
->length
);
1415 lnw
= i960_split_reg_group (l
, lnw
, g
->length
);
1418 /* N_iregs is now the number of global registers that haven't been saved
1421 rsize
= (n_iregs
* 4);
1422 actual_fsize
= compute_frame_size (size
) + rsize
;
1424 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1425 size up to the nearest multiple of 16. I don't know whether this is
1426 necessary, or even desirable.
1428 The frame pointer must be aligned, but the call instruction takes care of
1429 that. If we leave the stack pointer unaligned, we may save a little on
1430 dynamic stack allocation. And we don't lose, at least according to the
1432 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1435 /* Allocate space for register save and locals. */
1436 if (actual_fsize
> 0)
1438 if (actual_fsize
< 32)
1439 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1441 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1444 /* Take hardware register save area created by the call instruction
1445 into account, but store them before the argument block area. */
1446 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1447 /* Save registers on stack if needed. */
1448 /* ??? Is it worth to use the same algorithm as one for saving
1449 global registers in local registers? */
1450 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1457 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1460 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1464 if (nr
== 3 && regs
[i
+3] == -1)
1467 fprintf (file
,"\tst%s %s,%d(fp)\n",
1470 (nr
== 2) ? "l" : ""),
1471 reg_names
[i
], offset
);
1472 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1475 (nr
== 2) ? "l" : ""),
1476 offset
, reg_names
[i
]);
1477 strcat (epilogue_string
, tmpstr
);
1483 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1486 fprintf (file
, "\t#Prologue stats:\n");
1487 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1490 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1492 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1494 fprintf (file
, "\t#End Prologue#\n");
1497 /* Output code for the function profiler. */
1500 output_function_profiler (file
, labelno
)
1504 /* The last used parameter register. */
1506 int i
, j
, increment
;
1507 int varargs_stdarg_function
1508 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1510 /* Figure out the last used parameter register. The proper thing to do
1511 is to walk incoming args of the function. A function might have live
1512 parameter registers even if it has no incoming args. Note that we
1513 don't have to save parameter registers g8 to g11 because they are
1516 /* See also output_function_prologue, which tries to use local registers
1517 for preserved call-saved global registers. */
1519 for (last_parm_reg
= 7;
1520 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1524 /* Save parameter registers in regs r4 (20) to r11 (27). */
1526 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1528 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1530 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1532 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1537 fprintf (file
, "\tmov%s g%d,r%d\n",
1538 (increment
== 4 ? "q" : increment
== 3 ? "t"
1539 : increment
== 2 ? "l": ""), i
, j
);
1542 /* If this function uses the arg pointer, then save it in r3 and then
1545 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1546 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1548 /* Load location address into g0 and call mcount. */
1550 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1552 /* If this function uses the arg pointer, restore it. */
1554 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1555 fprintf (file
, "\tmov r3,g14\n");
1557 /* Restore parameter registers. */
1559 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1561 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1563 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1565 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1570 fprintf (file
, "\tmov%s r%d,g%d\n",
1571 (increment
== 4 ? "q" : increment
== 3 ? "t"
1572 : increment
== 2 ? "l": ""), j
, i
);
1576 /* Output code for the function epilogue. */
1579 i960_function_epilogue (file
, size
)
1583 if (i960_leaf_ret_reg
>= 0)
1585 fprintf (file
, "Li960R%d: ret\n", ret_label
);
1589 if (*epilogue_string
== 0)
1593 /* Emit a return insn, but only if control can fall through to here. */
1595 tmp
= get_last_insn ();
1598 if (GET_CODE (tmp
) == BARRIER
)
1600 if (GET_CODE (tmp
) == CODE_LABEL
)
1602 if (GET_CODE (tmp
) == JUMP_INSN
)
1604 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1608 if (GET_CODE (tmp
) == NOTE
)
1610 tmp
= PREV_INSN (tmp
);
1615 fprintf (file
, "Li960R%d: ret\n", ret_label
);
1619 fprintf (file
, "Li960R%d:\n", ret_label
);
1621 fprintf (file
, "\t#EPILOGUE#\n");
1623 /* Output the string created by the prologue which will restore all
1624 registers saved by the prologue. */
1626 if (epilogue_string
[0] != '\0')
1627 fprintf (file
, "%s", epilogue_string
);
1629 /* Must clear g14 on return if this function set it.
1630 Only varargs/stdarg functions modify g14. */
1632 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1633 fprintf (file
, "\tmov 0,g14\n");
1635 fprintf (file
, "\tret\n");
1636 fprintf (file
, "\t#End Epilogue#\n");
1639 /* Output code for a call insn. */
1642 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1643 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1645 int argsize
= INTVAL (argsize_rtx
);
1646 rtx nexti
= next_real_insn (insn
);
1648 int varargs_stdarg_function
1649 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1651 operands
[0] = target
;
1652 operands
[1] = arg_pointer
;
1654 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1655 output_asm_insn ("mov g14,r3", operands
);
1658 output_asm_insn ("lda %a1,g14", operands
);
1659 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1660 output_asm_insn ("mov 0,g14", operands
);
1662 /* The code used to assume that calls to SYMBOL_REFs could not be more
1663 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1664 feature is now implemented by relaxing in the GNU linker. It can convert
1665 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1667 /* Nexti could be zero if the called routine is volatile. */
1668 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1669 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1671 /* Delete following return insn. */
1672 if (nexti
&& no_labels_between_p (insn
, nexti
))
1673 delete_insn (nexti
);
1674 output_asm_insn ("bx %0", operands
);
1675 return "# notreached";
1678 output_asm_insn ("callx %0", operands
);
1680 /* If the caller sets g14 to the address of the argblock, then the caller
1681 must clear it after the return. */
1683 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1684 output_asm_insn ("mov r3,g14", operands
);
1685 else if (argsize
> 48)
1686 output_asm_insn ("mov 0,g14", operands
);
1691 /* Output code for a return insn. */
1694 i960_output_ret_insn (insn
)
1697 static char lbuf
[20];
1699 if (*epilogue_string
!= 0)
1701 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1704 sprintf (lbuf
, "b Li960R%d", ret_label
);
1708 /* Must clear g14 on return if this function set it.
1709 Only varargs/stdarg functions modify g14. */
1711 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1712 output_asm_insn ("mov 0,g14", 0);
1714 if (i960_leaf_ret_reg
>= 0)
1716 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1723 /* Return a character string representing the branch prediction
1724 opcode to be tacked on an instruction. This must at least
1725 return a null string. */
1728 i960_br_predict_opcode (lab_ref
, insn
)
1731 if (TARGET_BRANCH_PREDICT
)
1733 unsigned long label_uid
;
1735 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1736 label_uid
= INSN_UID (lab_ref
);
1737 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1738 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1742 /* If not optimizing, then the insn_addresses array will not be
1743 valid. In this case, always return ".t" since most branches
1744 are taken. If optimizing, return .t for backward branches
1745 and .f for forward branches. */
1747 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1756 /* Print the operand represented by rtx X formatted by code CODE. */
1759 i960_print_operand (file
, x
, code
)
1764 enum rtx_code rtxcode
= GET_CODE (x
);
1771 /* Second reg of a double or quad. */
1772 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1776 /* Third reg of a quad. */
1777 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1781 /* Fourth reg of a quad. */
1782 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1786 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1794 else if (rtxcode
== MEM
)
1796 output_address (XEXP (x
, 0));
1799 else if (rtxcode
== CONST_INT
)
1801 HOST_WIDE_INT val
= INTVAL (x
);
1804 if (val
> 9999 || val
< -999)
1805 fprintf (file
, "0x%x", val
);
1807 fprintf (file
, "%d", val
);
1810 else if (rtxcode
== CONST_DOUBLE
)
1815 if (x
== CONST0_RTX (GET_MODE (x
)))
1817 fprintf (file
, "0f0.0");
1820 else if (x
== CONST1_RTX (GET_MODE (x
)))
1822 fprintf (file
, "0f1.0");
1826 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1827 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1828 fprintf (file
, "0f%s", dstr
);
1835 /* Branch or jump, depending on assembler. */
1836 if (TARGET_ASM_COMPAT
)
1843 /* Sign of condition. */
1844 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1845 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1847 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1848 || (rtxcode
== GE
) || (rtxcode
== LE
))
1855 /* Inverted condition. */
1856 rtxcode
= reverse_condition (rtxcode
);
1860 /* Inverted condition w/ reversed operands. */
1861 rtxcode
= reverse_condition (rtxcode
);
1865 /* Reversed operand condition. */
1866 rtxcode
= swap_condition (rtxcode
);
1870 /* Normal condition. */
1872 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1873 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1874 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1875 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1876 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1877 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1878 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1879 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1880 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1881 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1886 output_addr_const (file
, x
);
1896 /* Print a memory address as an operand to reference that memory location.
1898 This is exactly the same as legitimate_address_p, except that it the prints
1899 addresses instead of recognizing them. */
1902 i960_print_operand_addr (file
, addr
)
1914 if (GET_CODE (addr
) == REG
)
1916 else if (CONSTANT_P (addr
))
1918 else if (GET_CODE (addr
) == PLUS
)
1922 op0
= XEXP (addr
, 0);
1923 op1
= XEXP (addr
, 1);
1925 if (GET_CODE (op0
) == REG
)
1928 if (GET_CODE (op1
) == REG
)
1930 else if (CONSTANT_P (op1
))
1935 else if (GET_CODE (op0
) == PLUS
)
1937 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1939 ireg
= XEXP (XEXP (op0
, 0), 0);
1940 scale
= XEXP (XEXP (op0
, 0), 1);
1941 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1943 breg
= XEXP (op0
, 1);
1949 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1951 breg
= XEXP (op0
, 0);
1952 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1954 ireg
= XEXP (op0
, 1);
1963 else if (GET_CODE (op0
) == MULT
)
1965 ireg
= XEXP (op0
, 0);
1966 scale
= XEXP (op0
, 1);
1967 if (GET_CODE (op1
) == REG
)
1969 else if (CONSTANT_P (op1
))
1977 else if (GET_CODE (addr
) == MULT
)
1979 ireg
= XEXP (addr
, 0);
1980 scale
= XEXP (addr
, 1);
1986 output_addr_const (file
, offset
);
1988 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1990 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1993 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1994 that is a valid memory address for an instruction.
1995 The MODE argument is the machine mode for the MEM expression
1996 that wants to use this address.
1998 On 80960, legitimate addresses are:
2000 disp (12 or 32 bit) ld foo,r0
2001 base + index ld (g0)[g1*1],r0
2002 base + displ ld 0xf00(g0),r0
2003 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
2004 index*scale + base ld (g0)[g1*4],r0
2005 index*scale + displ ld 0xf00[g1*4],r0
2006 index*scale ld [g1*4],r0
2007 index + base + displ ld 0xf00(g0)[g1*1],r0
2009 In each case, scale can be 1, 2, 4, 8, or 16. */
2011 /* This is exactly the same as i960_print_operand_addr, except that
2012 it recognizes addresses instead of printing them.
2014 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2015 convert common non-canonical forms to canonical form so that they will
2018 /* These two macros allow us to accept either a REG or a SUBREG anyplace
2019 where a register is valid. */
2021 #define RTX_OK_FOR_BASE_P(X, STRICT) \
2022 ((GET_CODE (X) == REG \
2023 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
2024 || (GET_CODE (X) == SUBREG \
2025 && GET_CODE (SUBREG_REG (X)) == REG \
2026 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
2027 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
2029 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
2030 ((GET_CODE (X) == REG \
2031 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
2032 || (GET_CODE (X) == SUBREG \
2033 && GET_CODE (SUBREG_REG (X)) == REG \
2034 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
2035 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
2038 legitimate_address_p (mode
, addr
, strict
)
2039 enum machine_mode mode
;
2043 if (RTX_OK_FOR_BASE_P (addr
, strict
))
2045 else if (CONSTANT_P (addr
))
2047 else if (GET_CODE (addr
) == PLUS
)
2051 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2054 op0
= XEXP (addr
, 0);
2055 op1
= XEXP (addr
, 1);
2057 if (RTX_OK_FOR_BASE_P (op0
, strict
))
2059 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
2061 else if (CONSTANT_P (op1
))
2066 else if (GET_CODE (op0
) == PLUS
)
2068 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
2070 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
2071 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
2074 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
2075 && CONSTANT_P (op1
))
2080 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
2082 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
2083 && CONSTANT_P (op1
))
2091 else if (GET_CODE (op0
) == MULT
)
2093 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
2094 && SCALE_TERM_P (XEXP (op0
, 1))))
2097 if (RTX_OK_FOR_BASE_P (op1
, strict
))
2099 else if (CONSTANT_P (op1
))
2107 else if (GET_CODE (addr
) == MULT
)
2109 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2112 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
2113 && SCALE_TERM_P (XEXP (addr
, 1)));
2119 /* Try machine-dependent ways of modifying an illegitimate address
2120 to be legitimate. If we find one, return the new, valid address.
2121 This macro is used in only one place: `memory_address' in explow.c.
2123 This converts some non-canonical addresses to canonical form so they
2124 can be recognized. */
2127 legitimize_address (x
, oldx
, mode
)
2130 enum machine_mode mode
;
2132 if (GET_CODE (x
) == SYMBOL_REF
)
2135 x
= copy_to_reg (x
);
2138 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2141 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2142 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2143 created by virtual register instantiation, register elimination, and
2144 similar optimizations. */
2145 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
2146 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2147 x
= gen_rtx (PLUS
, Pmode
,
2148 gen_rtx (PLUS
, Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2149 XEXP (XEXP (x
, 1), 1));
2151 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2152 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2153 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2154 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2155 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2156 && CONSTANT_P (XEXP (x
, 1)))
2158 rtx constant
, other
;
2160 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2162 constant
= XEXP (x
, 1);
2163 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2165 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2167 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2168 other
= XEXP (x
, 1);
2174 x
= gen_rtx (PLUS
, Pmode
,
2175 gen_rtx (PLUS
, Pmode
, XEXP (XEXP (x
, 0), 0),
2176 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2177 plus_constant (other
, INTVAL (constant
)));
2184 /* Return the most stringent alignment that we are willing to consider
2185 objects of size SIZE and known alignment ALIGN as having. */
2188 i960_alignment (size
, align
)
2194 if (! TARGET_STRICT_ALIGN
)
2195 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2197 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2208 hard_regno_mode_ok (regno
, mode
)
2210 enum machine_mode mode
;
2216 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2219 case DImode
: case DFmode
:
2220 return (regno
& 1) == 0;
2222 case TImode
: case XFmode
:
2223 return (regno
& 3) == 0;
2229 else if (regno
>= 32 && regno
< 36)
2233 case SFmode
: case DFmode
: case XFmode
:
2234 case SCmode
: case DCmode
:
2241 else if (regno
== 36)
2245 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2252 else if (regno
== 37)
2259 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2260 advantage of machine specific facts, such as knowing that the frame pointer
2261 is always 16 byte aligned. */
2264 i960_expr_alignment (x
, size
)
2273 switch (GET_CODE(x
))
2278 if ((align
& 0xf) == 0)
2280 else if ((align
& 0x7) == 0)
2282 else if ((align
& 0x3) == 0)
2284 else if ((align
& 0x1) == 0)
2291 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2292 i960_expr_alignment (XEXP (x
, 1), size
));
2296 /* If this is a valid program, objects are guaranteed to be
2297 correctly aligned for whatever size the reference actually is. */
2298 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2302 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2307 align
= i960_expr_alignment (XEXP (x
, 0));
2309 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2311 align
= align
<< INTVAL (XEXP (x
, 1));
2312 align
= MIN (align
, 16);
2317 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2318 i960_expr_alignment (XEXP (x
, 1), size
));
2320 align
= MIN (align
, 16);
2327 /* Return true if it is possible to reference both BASE and OFFSET, which
2328 have alignment at least as great as 4 byte, as if they had alignment valid
2329 for an object of size SIZE. */
2332 i960_improve_align (base
, offset
, size
)
2339 /* We have at least a word reference to the object, so we know it has to
2340 be aligned at least to 4 bytes. */
2342 i
= MIN (i960_expr_alignment (base
, 4),
2343 i960_expr_alignment (offset
, 4));
2347 /* We know the size of the request. If strict align is not enabled, we
2348 can guess that the alignment is OK for the requested size. */
2350 if (! TARGET_STRICT_ALIGN
)
2351 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2357 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2358 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2361 i960_si_ti (base
, offset
)
2365 return i960_improve_align (base
, offset
, 16);
2368 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2369 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2372 i960_si_di (base
, offset
)
2376 return i960_improve_align (base
, offset
, 8);
2379 /* Return raw values of size and alignment (in words) for the data
2380 type being accessed. These values will be rounded by the caller. */
2383 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2384 enum machine_mode mode
;
2391 /* Use formal alignment requirements of type being passed, except make
2392 it at least a word. If we don't have a type, this is a library call,
2393 and the parm has to be of scalar type. In this case, consider its
2394 formal alignment requirement to be its size in words. */
2396 if (mode
== BLKmode
)
2397 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2398 else if (mode
== VOIDmode
)
2400 /* End of parm list. */
2401 if (type
== 0 || TYPE_MODE (type
) != VOIDmode
)
2406 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2410 /* ??? This is a hack to properly correct the alignment of XFmode
2411 values without affecting anything else. */
2417 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2418 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2426 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2427 Any arg that is bigger than 4 words is placed on the stack and all
2428 subsequent arguments are placed on the stack.
2430 Additionally, parameters with an alignment requirement stronger than
2431 a word must be aligned appropriately. Note that this means that a
2432 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2433 passed in an odd/even register pair. */
2435 /* Update CUM to advance past an argument described by MODE and TYPE. */
2438 i960_function_arg_advance (cum
, mode
, type
, named
)
2439 CUMULATIVE_ARGS
*cum
;
2440 enum machine_mode mode
;
2446 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2448 if (size
> 4 || cum
->ca_nstackparms
!= 0
2449 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2450 || MUST_PASS_IN_STACK (mode
, type
))
2452 /* Indicate that all the registers are in use, even if all are not,
2453 so va_start will compute the right value. */
2454 cum
->ca_nregparms
= NPARM_REGS
;
2455 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2458 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2461 /* Return the register that the argument described by MODE and TYPE is
2462 passed in, or else return 0 if it is passed on the stack. */
2465 i960_function_arg (cum
, mode
, type
, named
)
2466 CUMULATIVE_ARGS
*cum
;
2467 enum machine_mode mode
;
2474 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2476 if (size
> 4 || cum
->ca_nstackparms
!= 0
2477 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2478 || MUST_PASS_IN_STACK (mode
, type
))
2480 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2485 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2486 ret
= gen_rtx (REG
, mode
, cum
->ca_nregparms
);
2492 /* Floating-point support. */
2495 i960_output_long_double (file
, value
)
2497 REAL_VALUE_TYPE value
;
2502 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2503 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2506 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2507 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2508 fprintf (file
, "\t.word\t0x0\n");
2512 i960_output_double (file
, value
)
2514 REAL_VALUE_TYPE value
;
2519 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2520 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2522 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2523 value_long
[0], dstr
, value_long
[1]);
2527 i960_output_float (file
, value
)
2529 REAL_VALUE_TYPE value
;
2534 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2535 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2537 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2540 /* Return the number of bits that an object of size N bytes is aligned to. */
2543 i960_object_bytes_bitalign (n
)
2547 else if (n
> 4) n
= 64;
2548 else if (n
> 2) n
= 32;
2549 else if (n
> 1) n
= 16;
2555 /* Compute the alignment for an aggregate type TSIZE.
2556 Alignment is MAX (greatest member alignment,
2557 MIN (pragma align, structure size alignment)). */
2560 i960_round_align (align
, tsize
)
2566 if (TREE_CODE (tsize
) != INTEGER_CST
)
2569 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2571 /* Handle #pragma align. */
2572 if (new_align
> i960_maxbitalignment
)
2573 new_align
= i960_maxbitalignment
;
2575 if (align
< new_align
)
2581 /* Do any needed setup for a varargs function. For the i960, we must
2582 create a register parameter block if one doesn't exist, and then copy
2583 all register parameters to memory. */
2586 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2587 CUMULATIVE_ARGS
*cum
;
2588 enum machine_mode mode
;
2593 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2594 int first_reg
= cum
->ca_nregparms
;
2596 /* Copy only unnamed register arguments to memory. If there are
2597 any stack parms, there are no unnamed arguments in registers, and
2598 an argument block was already allocated by the caller.
2599 Remember that any arg bigger than 4 words is passed on the stack as
2600 are all subsequent args.
2602 If there are no stack arguments but there are exactly NPARM_REGS
2603 registers, either there were no extra arguments or the caller
2604 allocated an argument block. */
2606 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2608 rtx label
= gen_label_rtx ();
2611 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2612 and we need to allocate a chunk to save the registers (if any
2613 arguments were passed on the stack the caller would allocate the
2614 48 bytes as well). We must allocate all 48 bytes (12*4) because
2615 va_start assumes it. */
2616 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2617 emit_jump_insn (gen_bne (label
));
2618 emit_insn (gen_rtx (SET
, VOIDmode
, arg_pointer_rtx
,
2619 stack_pointer_rtx
));
2620 emit_insn (gen_rtx (SET
, VOIDmode
, stack_pointer_rtx
,
2621 memory_address (SImode
,
2622 plus_constant (stack_pointer_rtx
,
2626 /* ??? Note that we unnecessarily store one extra register for stdarg
2627 fns. We could optimize this, but it's kept as-is for now. */
2628 regblock
= gen_rtx (MEM
, BLKmode
,
2629 plus_constant (arg_pointer_rtx
,
2631 MEM_ALIAS_SET (regblock
) = get_varargs_alias_set ();
2632 move_block_from_reg (first_reg
, regblock
,
2633 NPARM_REGS
- first_reg
,
2634 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2638 /* Define the `__builtin_va_list' type for the ABI. */
2641 i960_build_va_list ()
2643 return build_array_type (unsigned_type_node
,
2644 build_index_type (size_one_node
));
2647 /* Implement `va_start' for varargs and stdarg. */
2650 i960_va_start (stdarg_p
, valist
, nextarg
)
2651 int stdarg_p ATTRIBUTE_UNUSED
;
2653 rtx nextarg ATTRIBUTE_UNUSED
;
2657 s
= make_tree (unsigned_type_node
, arg_pointer_rtx
);
2658 d
= build (ARRAY_REF
, unsigned_type_node
, valist
, size_zero_node
);
2659 t
= build (MODIFY_EXPR
, unsigned_type_node
, d
, s
);
2660 TREE_SIDE_EFFECTS (t
) = 1;
2661 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2663 s
= build_int_2 ((current_function_args_info
.ca_nregparms
2664 + current_function_args_info
.ca_nstackparms
) * 4, 0);
2665 d
= build (ARRAY_REF
, unsigned_type_node
, valist
, size_one_node
);
2666 t
= build (MODIFY_EXPR
, unsigned_type_node
, d
, s
);
2667 TREE_SIDE_EFFECTS (t
) = 1;
2668 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2671 /* Implement `va_arg'. */
2674 i960_va_arg (valist
, type
)
2677 HOST_WIDE_INT siz
, ali
;
2678 tree base
, num
, pad
, next
, this, t1
, t2
, int48
;
2681 base
= build (ARRAY_REF
, unsigned_type_node
, valist
, size_zero_node
);
2682 num
= build (ARRAY_REF
, unsigned_type_node
, valist
, size_one_node
);
2684 /* Round up sizeof(type) to a word. */
2685 siz
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
2687 /* Round up alignment to a word. */
2688 ali
= TYPE_ALIGN (type
);
2689 if (ali
< BITS_PER_WORD
)
2690 ali
= BITS_PER_WORD
;
2691 ali
/= BITS_PER_UNIT
;
2693 /* Align NUM appropriate for the argument. */
2694 pad
= fold (build (PLUS_EXPR
, unsigned_type_node
, num
,
2695 build_int_2 (ali
- 1, 0)));
2696 pad
= fold (build (BIT_AND_EXPR
, unsigned_type_node
, pad
,
2697 build_int_2 (-ali
, -1)));
2698 pad
= save_expr (pad
);
2700 /* Increment VPAD past this argument. */
2701 next
= fold (build (PLUS_EXPR
, unsigned_type_node
, pad
,
2702 build_int_2 (siz
, 0)));
2703 next
= save_expr (next
);
2705 /* Find the offset for the current argument. Mind peculiar overflow
2706 from registers to stack. */
2707 int48
= build_int_2 (48, 0);
2709 t2
= integer_one_node
;
2711 t2
= fold (build (GT_EXPR
, integer_type_node
, next
, int48
));
2712 t1
= fold (build (LE_EXPR
, integer_type_node
, num
, int48
));
2713 t1
= fold (build (TRUTH_AND_EXPR
, integer_type_node
, t1
, t2
));
2714 this = fold (build (COND_EXPR
, unsigned_type_node
, t1
, int48
, pad
));
2716 /* Find the address for the current argument. */
2717 t1
= fold (build (PLUS_EXPR
, unsigned_type_node
, base
, this));
2718 t1
= build1 (NOP_EXPR
, ptr_type_node
, t1
);
2719 addr_rtx
= expand_expr (t1
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
2721 /* Increment NUM. */
2722 t1
= build (MODIFY_EXPR
, unsigned_type_node
, num
, next
);
2723 TREE_SIDE_EFFECTS (t1
) = 1;
2724 expand_expr (t1
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2729 /* Calculate the final size of the reg parm stack space for the current
2730 function, based on how many bytes would be allocated on the stack. */
2733 i960_final_reg_parm_stack_space (const_size
, var_size
)
2737 if (var_size
|| const_size
> 48)
2743 /* Calculate the size of the reg parm stack space. This is a bit complicated
2747 i960_reg_parm_stack_space (fndecl
)
2750 /* In this case, we are called from emit_library_call, and we don't need
2751 to pretend we have more space for parameters than what's apparent. */
2755 /* In this case, we are called from locate_and_pad_parms when we're
2756 not IN_REGS, so we have an arg block. */
2757 if (fndecl
!= current_function_decl
)
2760 /* Otherwise, we have an arg block if the current function has more than
2761 48 bytes of parameters. */
2762 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2768 /* Return the register class of a scratch register needed to copy IN into
2769 or out of a register in CLASS in MODE. If it can be done directly,
2770 NO_REGS is returned. */
2773 secondary_reload_class (class, mode
, in
)
2774 enum reg_class
class;
2775 enum machine_mode mode
;
2780 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2781 regno
= true_regnum (in
);
2783 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2784 LOCAL_OR_GLOBAL_REGS into anything. */
2785 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2786 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2789 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2790 if (class == FP_REGS
2791 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2792 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2795 return LOCAL_OR_GLOBAL_REGS
;
2798 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2799 function unit it executed on. */
2801 /* ??? This would make more sense as an attribute. */
2804 i960_scan_opcode (p
)
2816 /* Ret is not actually of type REG, but it won't matter, because no
2817 insn will ever follow it. */
2820 i960_last_insn_type
= I_TYPE_REG
;
2824 if (p
[1] == 'x' || p
[3] == 'x')
2825 i960_last_insn_type
= I_TYPE_MEM
;
2826 i960_last_insn_type
= I_TYPE_CTRL
;
2831 i960_last_insn_type
= I_TYPE_CTRL
;
2838 i960_last_insn_type
= I_TYPE_MEM
;
2840 i960_last_insn_type
= I_TYPE_CTRL
;
2842 else if (p
[1] == 'm')
2845 i960_last_insn_type
= I_TYPE_REG
;
2846 else if (p
[4] == 'b' || p
[4] == 'j')
2847 i960_last_insn_type
= I_TYPE_CTRL
;
2849 i960_last_insn_type
= I_TYPE_REG
;
2852 i960_last_insn_type
= I_TYPE_REG
;
2856 i960_last_insn_type
= I_TYPE_MEM
;
2861 i960_last_insn_type
= I_TYPE_MEM
;
2863 i960_last_insn_type
= I_TYPE_REG
;