1 ;;- Machine description for Intel 80960 chip for GNU C compiler
2 ;; Copyright (C) 1992, 1995, 1998 Free Software Foundation, Inc.
3 ;; Contributed by Steven McGeady, Intel Corp.
4 ;; Additional work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 ;; Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;; There are very few (4) 'f' registers, they can't be loaded/stored from/to
27 ;; memory, and some instructions explicitly require them, so we get better
28 ;; code by discouraging pseudo-registers from being allocated to them.
29 ;; However, we do want to allow all patterns which can store to them to
30 ;; include them in their constraints, so we always use '*f' in a destination
31 ;; constraint except when 'f' is the only alternative.
33 ;; Insn attributes which describe the i960.
35 ;; Modscan is not used, since the compiler never emits any of these insns.
37 "move,arith,alu2,mult,div,modscan,load,store,branch,call,address,compare,fpload,fpstore,fpmove,fpcvt,fpcc,fpadd,fpmul,fpdiv,multi,misc"
38 (const_string "arith"))
40 ;; Length (in # of insns).
41 (define_attr "length" ""
42 (cond [(eq_attr "type" "load,fpload")
43 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
46 (eq_attr "type" "store,fpstore")
47 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
50 (eq_attr "type" "address")
54 (define_asm_attributes
55 [(set_attr "length" "1")
56 (set_attr "type" "multi")])
58 ;; (define_function_unit {name} {num-units} {n-users} {test}
59 ;; {ready-delay} {issue-delay} [{conflict-list}])
62 (define_function_unit "alu" 2 0 (eq_attr "type" "arith,compare,move,address") 1 0)
63 (define_function_unit "alu" 2 0 (eq_attr "type" "alu2") 2 0)
64 (define_function_unit "alu" 2 0 (eq_attr "type" "mult") 5 0)
65 (define_function_unit "alu" 2 0 (eq_attr "type" "div") 35 0)
66 (define_function_unit "alu" 2 0 (eq_attr "type" "modscan") 3 0)
68 ;; Memory with load-delay of 1 (i.e., 2 cycle load).
69 (define_function_unit "memory" 1 0 (eq_attr "type" "load,fpload") 2 0)
71 ;; Floating point operations.
72 (define_function_unit "fp" 1 2 (eq_attr "type" "fpmove") 5 0)
73 (define_function_unit "fp" 1 2 (eq_attr "type" "fpcvt") 35 0)
74 (define_function_unit "fp" 1 2 (eq_attr "type" "fpcc") 10 0)
75 (define_function_unit "fp" 1 2 (eq_attr "type" "fpadd") 10 0)
76 (define_function_unit "fp" 1 2 (eq_attr "type" "fpmul") 20 0)
77 (define_function_unit "fp" 1 2 (eq_attr "type" "fpdiv") 35 0)
79 ;; Compare instructions.
80 ;; This controls RTL generation and register allocation.
82 ;; We generate RTL for comparisons and branches by having the cmpxx
83 ;; patterns store away the operands. Then, the scc and bcc patterns
84 ;; emit RTL for both the compare and the branch.
86 ;; We start with the DEFINE_EXPANDs, then DEFINE_INSNs to match
87 ;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc
88 ;; insns that actually require more than one machine instruction.
90 ;; Put cmpsi first because it is expected to be the most common.
92 (define_expand "cmpsi"
94 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "")
95 (match_operand:SI 1 "general_operand" "")))]
99 i960_compare_op0 = operands[0];
100 i960_compare_op1 = operands[1];
104 (define_expand "cmpdf"
106 (compare:CC (match_operand:DF 0 "register_operand" "r")
107 (match_operand:DF 1 "nonmemory_operand" "rGH")))]
111 i960_compare_op0 = operands[0];
112 i960_compare_op1 = operands[1];
116 (define_expand "cmpsf"
118 (compare:CC (match_operand:SF 0 "register_operand" "r")
119 (match_operand:SF 1 "nonmemory_operand" "rGH")))]
123 i960_compare_op0 = operands[0];
124 i960_compare_op1 = operands[1];
128 ;; Now the DEFINE_INSNs for the compare and scc cases. First the compares.
132 (compare:CC (match_operand:SI 0 "register_operand" "d")
133 (match_operand:SI 1 "arith_operand" "dI")))]
136 [(set_attr "type" "compare")])
139 [(set (reg:CC_UNS 36)
140 (compare:CC_UNS (match_operand:SI 0 "register_operand" "d")
141 (match_operand:SI 1 "arith_operand" "dI")))]
144 [(set_attr "type" "compare")])
148 (compare:CC (match_operand:DF 0 "register_operand" "r")
149 (match_operand:DF 1 "nonmemory_operand" "rGH")))]
152 [(set_attr "type" "fpcc")])
156 (compare:CC (match_operand:SF 0 "register_operand" "r")
157 (match_operand:SF 1 "nonmemory_operand" "rGH")))]
160 [(set_attr "type" "fpcc")])
162 ;; Instruction definitions for branch-on-bit-set and clear insns.
167 (ne (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
169 (match_operand:SI 2 "arith_operand" "dI"))
171 (label_ref (match_operand 3 "" ""))
175 [(set_attr "type" "branch")])
180 (eq (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
182 (match_operand:SI 2 "arith_operand" "dI"))
184 (label_ref (match_operand 3 "" ""))
188 [(set_attr "type" "branch")])
193 (ne (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
195 (match_operand:SI 2 "arith_operand" "dI"))
197 (label_ref (match_operand 3 "" ""))
201 [(set_attr "type" "branch")])
206 (eq (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
208 (match_operand:SI 2 "arith_operand" "dI"))
210 (label_ref (match_operand 3 "" ""))
214 [(set_attr "type" "branch")])
216 ;; ??? These will never match. The LOG_LINKs necessary to make these match
217 ;; are not created by flow. These remain as a reminder to make this work
222 (compare (match_operand:SI 0 "arith_operand" "d")
223 (match_operand:SI 1 "arith_operand" "d")))
224 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))]
227 [(set_attr "type" "compare")])
230 [(set (reg:CC_UNS 36)
231 (compare (match_operand:SI 0 "arith_operand" "d")
232 (match_operand:SI 1 "arith_operand" "d")))
233 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))]
236 [(set_attr "type" "compare")])
240 (compare (match_operand:SI 0 "arith_operand" "d")
241 (match_operand:SI 1 "arith_operand" "d")))
242 (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))]
245 [(set_attr "type" "compare")])
248 [(set (reg:CC_UNS 36)
249 (compare (match_operand:SI 0 "arith_operand" "d")
250 (match_operand:SI 1 "arith_operand" "d")))
251 (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))]
254 [(set_attr "type" "compare")])
256 ;; Templates to store result of condition.
257 ;; '1' is stored if condition is true.
258 ;; '0' is stored if condition is false.
259 ;; These should use predicate "general_operand", since
260 ;; gcc seems to be creating mem references which use these
264 [(set (match_operand:SI 0 "general_operand" "=d")
265 (eq:SI (match_dup 1) (const_int 0)))]
269 operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1);
273 [(set (match_operand:SI 0 "general_operand" "=d")
274 (ne:SI (match_dup 1) (const_int 0)))]
278 operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1);
282 [(set (match_operand:SI 0 "general_operand" "=d")
283 (gt:SI (match_dup 1) (const_int 0)))]
287 operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1);
290 (define_expand "sgtu"
291 [(set (match_operand:SI 0 "general_operand" "=d")
292 (gtu:SI (match_dup 1) (const_int 0)))]
296 operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1);
300 [(set (match_operand:SI 0 "general_operand" "=d")
301 (lt:SI (match_dup 1) (const_int 0)))]
305 operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1);
308 (define_expand "sltu"
309 [(set (match_operand:SI 0 "general_operand" "=d")
310 (ltu:SI (match_dup 1) (const_int 0)))]
314 operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1);
318 [(set (match_operand:SI 0 "general_operand" "=d")
319 (ge:SI (match_dup 1) (const_int 0)))]
323 operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1);
326 (define_expand "sgeu"
327 [(set (match_operand:SI 0 "general_operand" "=d")
328 (geu:SI (match_dup 1) (const_int 0)))]
332 operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1);
336 [(set (match_operand:SI 0 "general_operand" "=d")
337 (le:SI (match_dup 1) (const_int 0)))]
341 operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1);
344 (define_expand "sleu"
345 [(set (match_operand:SI 0 "general_operand" "=d")
346 (leu:SI (match_dup 1) (const_int 0)))]
350 operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1);
354 [(set (match_operand:SI 0 "general_operand" "=d")
355 (eq:SI (match_operand:SI 1 "register_operand" "d") (const_int 0)))]
358 [(set_attr "type" "alu2")])
361 [(set (match_operand:SI 0 "general_operand" "=d")
362 (match_operator:SI 1 "comparison_operator" [(reg:CC 36) (const_int 0)]))]
365 [(set_attr "type" "compare")])
368 [(set (match_operand:SI 0 "general_operand" "=d")
369 (match_operator:SI 1 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]))]
372 [(set_attr "type" "compare")])
374 ;; These control RTL generation for conditional jump insns
375 ;; and match them for register allocation.
379 (if_then_else (eq (match_dup 1)
381 (label_ref (match_operand 0 "" ""))
385 { operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); }")
389 (if_then_else (ne (match_dup 1)
391 (label_ref (match_operand 0 "" ""))
395 { operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); }")
399 (if_then_else (gt (match_dup 1)
401 (label_ref (match_operand 0 "" ""))
405 { operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); }")
407 (define_expand "bgtu"
409 (if_then_else (gtu (match_dup 1)
411 (label_ref (match_operand 0 "" ""))
415 { operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); }")
419 (if_then_else (lt (match_dup 1)
421 (label_ref (match_operand 0 "" ""))
425 { operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); }")
427 (define_expand "bltu"
429 (if_then_else (ltu (match_dup 1)
431 (label_ref (match_operand 0 "" ""))
435 { operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); }")
439 (if_then_else (ge (match_dup 1)
441 (label_ref (match_operand 0 "" ""))
445 { operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); }")
447 (define_expand "bgeu"
449 (if_then_else (geu (match_dup 1)
451 (label_ref (match_operand 0 "" ""))
455 { operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); }")
459 (if_then_else (le (match_dup 1)
461 (label_ref (match_operand 0 "" ""))
465 { operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); }")
467 (define_expand "bleu"
469 (if_then_else (leu (match_dup 1)
471 (label_ref (match_operand 0 "" ""))
475 { operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); }")
477 ;; Now the normal branch insns (forward and reverse).
481 (if_then_else (match_operator 0 "comparison_operator"
482 [(reg:CC 36) (const_int 0)])
483 (label_ref (match_operand 1 "" ""))
487 [(set_attr "type" "branch")])
491 (if_then_else (match_operator 0 "comparison_operator"
492 [(reg:CC 36) (const_int 0)])
494 (label_ref (match_operand 1 "" ""))))]
497 [(set_attr "type" "branch")])
501 (if_then_else (match_operator 0 "comparison_operator"
502 [(reg:CC_UNS 36) (const_int 0)])
503 (label_ref (match_operand 1 "" ""))
507 [(set_attr "type" "branch")])
511 (if_then_else (match_operator 0 "comparison_operator"
512 [(reg:CC_UNS 36) (const_int 0)])
514 (label_ref (match_operand 1 "" ""))))]
517 [(set_attr "type" "branch")])
522 (match_operator 0 "comparison_operator"
523 [(match_operand:SI 1 "arith_operand" "d")
524 (match_operand:SI 2 "arith_operand" "dI")])
525 (label_ref (match_operand 3 "" ""))
528 "cmp%S0%B0%R0 %2,%1,%l3"
529 [(set_attr "type" "branch")])
534 (match_operator 0 "comparison_operator"
535 [(match_operand:SI 1 "arith_operand" "d")
536 (match_operand:SI 2 "arith_operand" "dI")])
538 (label_ref (match_operand 3 "" ""))))]
540 "cmp%S0%B0%X0 %2,%1,%l3"
541 [(set_attr "type" "branch")])
543 ;; Normal move instructions.
544 ;; This code is based on the sparc machine description.
546 (define_expand "movsi"
547 [(set (match_operand:SI 0 "general_operand" "")
548 (match_operand:SI 1 "general_operand" ""))]
552 if (emit_move_sequence (operands, SImode))
556 ;; The store case can not be separate, because reload may convert a register
557 ;; to register move insn to a store (or load) insn without rerecognizing
560 ;; The i960 does not have any store constant to memory instruction. However,
561 ;; the calling convention is defined so that the arg pointer when it is not
562 ;; overwise being used is zero. Thus, we can handle store zero to memory
563 ;; by storing an unused arg pointer. The arg pointer will be unused if
564 ;; current_function_args_size is zero and this is not a stdarg/varargs
565 ;; function. This value of the former variable is not valid until after
566 ;; all rtl generation is complete, including function inlining (because a
567 ;; function that doesn't need an arg pointer may be inlined into a function
568 ;; that does need an arg pointer), so we must also check that
569 ;; rtx_equal_function_value_matters is zero.
572 [(set (match_operand:SI 0 "general_operand" "=d,d,d,m")
573 (match_operand:SI 1 "general_operand" "dI,i,m,dJ"))]
574 "(current_function_args_size == 0
575 && current_function_varargs == 0
576 && current_function_stdarg == 0
577 && rtx_equal_function_value_matters == 0)
578 && (register_operand (operands[0], SImode)
579 || register_operand (operands[1], SImode)
580 || operands[1] == const0_rtx)"
583 switch (which_alternative)
586 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
588 if (GET_CODE (operands[1]) == REG)
589 return \"lda (%1),%0\";
591 return \"lda %1,%0\";
593 return \"mov %1,%0\";
595 return i960_output_ldconst (operands[0], operands[1]);
599 if (operands[1] == const0_rtx)
600 return \"st g14,%0\";
604 [(set_attr "type" "move,address,load,store")
605 (set_attr "length" "*,3,*,*")])
608 [(set (match_operand:SI 0 "general_operand" "=d,d,d,m")
609 (match_operand:SI 1 "general_operand" "dI,i,m,d"))]
610 "(current_function_args_size != 0
611 || current_function_varargs != 0
612 || current_function_stdarg != 0
613 || rtx_equal_function_value_matters != 0)
614 && (register_operand (operands[0], SImode)
615 || register_operand (operands[1], SImode))"
618 switch (which_alternative)
621 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
623 if (GET_CODE (operands[1]) == REG)
624 return \"lda (%1),%0\";
626 return \"lda %1,%0\";
628 return \"mov %1,%0\";
630 return i960_output_ldconst (operands[0], operands[1]);
637 [(set_attr "type" "move,address,load,store")
638 (set_attr "length" "*,3,*,*")])
640 (define_expand "movhi"
641 [(set (match_operand:HI 0 "general_operand" "")
642 (match_operand:HI 1 "general_operand" ""))]
646 if (emit_move_sequence (operands, HImode))
650 ;; Special pattern for zero stores to memory for functions which don't use
653 ;; The store case can not be separate. See above.
655 [(set (match_operand:HI 0 "general_operand" "=d,d,d,m")
656 (match_operand:HI 1 "general_operand" "dI,i,m,dJ"))]
657 "(current_function_args_size == 0
658 && current_function_varargs == 0
659 && current_function_stdarg == 0
660 && rtx_equal_function_value_matters == 0)
661 && (register_operand (operands[0], HImode)
662 || register_operand (operands[1], HImode)
663 || operands[1] == const0_rtx)"
666 switch (which_alternative)
669 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
671 if (GET_CODE (operands[1]) == REG)
672 return \"lda (%1),%0\";
674 return \"lda %1,%0\";
676 return \"mov %1,%0\";
678 return i960_output_ldconst (operands[0], operands[1]);
680 return \"ldos %1,%0\";
682 if (operands[1] == const0_rtx)
683 return \"stos g14,%0\";
684 return \"stos %1,%0\";
687 [(set_attr "type" "move,misc,load,store")
688 (set_attr "length" "*,3,*,*")])
690 ;; The store case can not be separate. See above.
692 [(set (match_operand:HI 0 "general_operand" "=d,d,d,m")
693 (match_operand:HI 1 "general_operand" "dI,i,m,d"))]
694 "(current_function_args_size != 0
695 || current_function_varargs != 0
696 || current_function_stdarg != 0
697 || rtx_equal_function_value_matters != 0)
698 && (register_operand (operands[0], HImode)
699 || register_operand (operands[1], HImode))"
702 switch (which_alternative)
705 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
707 if (GET_CODE (operands[1]) == REG)
708 return \"lda (%1),%0\";
710 return \"lda %1,%0\";
712 return \"mov %1,%0\";
714 return i960_output_ldconst (operands[0], operands[1]);
716 return \"ldos %1,%0\";
718 return \"stos %1,%0\";
721 [(set_attr "type" "move,misc,load,store")
722 (set_attr "length" "*,3,*,*")])
724 (define_expand "movqi"
725 [(set (match_operand:QI 0 "general_operand" "")
726 (match_operand:QI 1 "general_operand" ""))]
730 if (emit_move_sequence (operands, QImode))
734 ;; The store case can not be separate. See comment above.
736 [(set (match_operand:QI 0 "general_operand" "=d,d,d,m")
737 (match_operand:QI 1 "general_operand" "dI,i,m,dJ"))]
738 "(current_function_args_size == 0
739 && current_function_varargs == 0
740 && current_function_stdarg == 0
741 && rtx_equal_function_value_matters == 0)
742 && (register_operand (operands[0], QImode)
743 || register_operand (operands[1], QImode)
744 || operands[1] == const0_rtx)"
747 switch (which_alternative)
750 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
752 if (GET_CODE (operands[1]) == REG)
753 return \"lda (%1),%0\";
755 return \"lda %1,%0\";
757 return \"mov %1,%0\";
759 return i960_output_ldconst (operands[0], operands[1]);
761 return \"ldob %1,%0\";
763 if (operands[1] == const0_rtx)
764 return \"stob g14,%0\";
765 return \"stob %1,%0\";
768 [(set_attr "type" "move,misc,load,store")
769 (set_attr "length" "*,3,*,*")])
771 ;; The store case can not be separate. See comment above.
773 [(set (match_operand:QI 0 "general_operand" "=d,d,d,m")
774 (match_operand:QI 1 "general_operand" "dI,i,m,d"))]
775 "(current_function_args_size != 0
776 || current_function_varargs != 0
777 || current_function_stdarg != 0
778 || rtx_equal_function_value_matters != 0)
779 && (register_operand (operands[0], QImode)
780 || register_operand (operands[1], QImode))"
783 switch (which_alternative)
786 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
788 if (GET_CODE (operands[1]) == REG)
789 return \"lda (%1),%0\";
791 return \"lda %1,%0\";
793 return \"mov %1,%0\";
795 return i960_output_ldconst (operands[0], operands[1]);
797 return \"ldob %1,%0\";
799 return \"stob %1,%0\";
802 [(set_attr "type" "move,misc,load,store")
803 (set_attr "length" "*,3,*,*")])
805 (define_expand "movdi"
806 [(set (match_operand:DI 0 "general_operand" "")
807 (match_operand:DI 1 "general_operand" ""))]
811 if (emit_move_sequence (operands, DImode))
815 ;; The store case can not be separate. See comment above.
817 [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,m,o")
818 (match_operand:DI 1 "general_operand" "d,I,i,m,d,J"))]
819 "(current_function_args_size == 0
820 && current_function_varargs == 0
821 && current_function_stdarg == 0
822 && rtx_equal_function_value_matters == 0)
823 && (register_operand (operands[0], DImode)
824 || register_operand (operands[1], DImode)
825 || operands[1] == const0_rtx)"
828 switch (which_alternative)
834 return i960_output_move_double (operands[0], operands[1]);
836 return i960_output_ldconst (operands[0], operands[1]);
838 return i960_output_move_double_zero (operands[0]);
841 [(set_attr "type" "move,move,load,load,store,store")])
843 ;; The store case can not be separate. See comment above.
845 [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,m")
846 (match_operand:DI 1 "general_operand" "d,I,i,m,d"))]
847 "(current_function_args_size != 0
848 || current_function_varargs != 0
849 || current_function_stdarg != 0
850 || rtx_equal_function_value_matters != 0)
851 && (register_operand (operands[0], DImode)
852 || register_operand (operands[1], DImode))"
855 switch (which_alternative)
861 return i960_output_move_double (operands[0], operands[1]);
863 return i960_output_ldconst (operands[0], operands[1]);
866 [(set_attr "type" "move,move,load,load,store")])
868 (define_insn "*store_unaligned_di_reg"
869 [(set (match_operand:DI 0 "general_operand" "=d,m")
870 (match_operand:DI 1 "register_operand" "d,d"))
871 (clobber (match_scratch:SI 2 "=X,&d"))]
875 if (which_alternative == 0)
876 return i960_output_move_double (operands[0], operands[1]);
878 operands[3] = gen_rtx (MEM, word_mode, operands[2]);
879 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
880 return \"lda %0,%2\;st %1,%3\;st %D1,%4\";
882 [(set_attr "type" "move,store")])
884 (define_expand "movti"
885 [(set (match_operand:TI 0 "general_operand" "")
886 (match_operand:TI 1 "general_operand" ""))]
890 if (emit_move_sequence (operands, TImode))
894 ;; The store case can not be separate. See comment above.
896 [(set (match_operand:TI 0 "general_operand" "=d,d,d,d,m,o")
897 (match_operand:TI 1 "general_operand" "d,I,i,m,d,J"))]
898 "(current_function_args_size == 0
899 && current_function_varargs == 0
900 && current_function_stdarg == 0
901 && rtx_equal_function_value_matters == 0)
902 && (register_operand (operands[0], TImode)
903 || register_operand (operands[1], TImode)
904 || operands[1] == const0_rtx)"
907 switch (which_alternative)
913 return i960_output_move_quad (operands[0], operands[1]);
915 return i960_output_ldconst (operands[0], operands[1]);
917 return i960_output_move_quad_zero (operands[0]);
920 [(set_attr "type" "move,move,load,load,store,store")])
922 ;; The store case can not be separate. See comment above.
924 [(set (match_operand:TI 0 "general_operand" "=d,d,d,d,m")
925 (match_operand:TI 1 "general_operand" "d,I,i,m,d"))]
926 "(current_function_args_size != 0
927 || current_function_varargs != 0
928 || current_function_stdarg != 0
929 || rtx_equal_function_value_matters != 0)
930 && (register_operand (operands[0], TImode)
931 || register_operand (operands[1], TImode))"
934 switch (which_alternative)
940 return i960_output_move_quad (operands[0], operands[1]);
942 return i960_output_ldconst (operands[0], operands[1]);
945 [(set_attr "type" "move,move,load,load,store")])
947 (define_insn "*store_unaligned_ti_reg"
948 [(set (match_operand:TI 0 "general_operand" "=d,m")
949 (match_operand:TI 1 "register_operand" "d,d"))
950 (clobber (match_scratch:SI 2 "=X,&d"))]
954 if (which_alternative == 0)
955 return i960_output_move_quad (operands[0], operands[1]);
957 operands[3] = gen_rtx (MEM, word_mode, operands[2]);
958 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
959 operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD);
960 operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD);
961 return \"lda %0,%2\;st %1,%3\;st %D1,%4\;st %E1,%5\;st %F1,%6\";
963 [(set_attr "type" "move,store")])
965 (define_expand "store_multiple"
966 [(set (match_operand:SI 0 "" "") ;;- dest
967 (match_operand:SI 1 "" "")) ;;- src
968 (use (match_operand:SI 2 "" ""))] ;;- nregs
976 if (GET_CODE (operands[0]) != MEM
977 || GET_CODE (operands[1]) != REG
978 || GET_CODE (operands[2]) != CONST_INT)
981 count = INTVAL (operands[2]);
985 regno = REGNO (operands[1]);
986 from = memory_address (SImode, XEXP (operands[0], 0));
987 while (count >= 4 && ((regno & 3) == 0))
989 emit_move_insn (change_address (operands[0], TImode, from),
990 gen_rtx_REG (TImode, regno));
993 from = memory_address (TImode, plus_constant (from, 16));
995 while (count >= 2 && ((regno & 1) == 0))
997 emit_move_insn (change_address (operands[0], DImode, from),
998 gen_rtx_REG (DImode, regno));
1001 from = memory_address (DImode, plus_constant (from, 8));
1005 emit_move_insn (change_address (operands[0], SImode, from),
1006 gen_rtx_REG (SImode, regno));
1009 from = memory_address (SImode, plus_constant (from, 4));
1014 ;; Floating point move insns
1016 (define_expand "movdf"
1017 [(set (match_operand:DF 0 "general_operand" "")
1018 (match_operand:DF 1 "fpmove_src_operand" ""))]
1022 if (emit_move_sequence (operands, DFmode))
1027 [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m,o")
1028 (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))]
1029 "(current_function_args_size == 0
1030 && current_function_varargs == 0
1031 && current_function_stdarg == 0
1032 && rtx_equal_function_value_matters == 0)
1033 && (register_operand (operands[0], DFmode)
1034 || register_operand (operands[1], DFmode)
1035 || operands[1] == CONST0_RTX (DFmode))"
1038 switch (which_alternative)
1041 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1042 return \"movrl %1,%0\";
1044 return \"movl %1,%0\";
1046 return \"movrl %1,%0\";
1048 return i960_output_ldconst (operands[0], operands[1]);
1050 return \"ldl %1,%0\";
1052 return \"stl %1,%0\";
1054 operands[1] = adj_offsettable_operand (operands[0], 4);
1055 return \"st g14,%0\;st g14,%1\";
1058 [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")])
1061 [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m")
1062 (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
1063 "(current_function_args_size != 0
1064 || current_function_varargs != 0
1065 || current_function_stdarg != 0
1066 || rtx_equal_function_value_matters != 0)
1067 && (register_operand (operands[0], DFmode)
1068 || register_operand (operands[1], DFmode))"
1071 switch (which_alternative)
1074 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1075 return \"movrl %1,%0\";
1077 return \"movl %1,%0\";
1079 return \"movrl %1,%0\";
1081 return i960_output_ldconst (operands[0], operands[1]);
1083 return \"ldl %1,%0\";
1085 return \"stl %1,%0\";
1088 [(set_attr "type" "move,move,load,fpload,fpstore")])
1090 (define_expand "movsf"
1091 [(set (match_operand:SF 0 "general_operand" "")
1092 (match_operand:SF 1 "fpmove_src_operand" ""))]
1096 if (emit_move_sequence (operands, SFmode))
1101 [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m")
1102 (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,dG"))]
1103 "(current_function_args_size == 0
1104 && current_function_varargs == 0
1105 && current_function_stdarg == 0
1106 && rtx_equal_function_value_matters == 0)
1107 && (register_operand (operands[0], SFmode)
1108 || register_operand (operands[1], SFmode)
1109 || operands[1] == CONST0_RTX (SFmode))"
1112 switch (which_alternative)
1115 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1116 return \"movr %1,%0\";
1118 return \"mov %1,%0\";
1120 return \"movr %1,%0\";
1122 return i960_output_ldconst (operands[0], operands[1]);
1124 return \"ld %1,%0\";
1126 if (operands[1] == CONST0_RTX (SFmode))
1127 return \"st g14,%0\";
1128 return \"st %1,%0\";
1131 [(set_attr "type" "move,move,load,fpload,fpstore")])
1134 [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m")
1135 (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
1136 "(current_function_args_size != 0
1137 || current_function_varargs != 0
1138 || current_function_stdarg != 0
1139 || rtx_equal_function_value_matters != 0)
1140 && (register_operand (operands[0], SFmode)
1141 || register_operand (operands[1], SFmode))"
1144 switch (which_alternative)
1147 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1148 return \"movr %1,%0\";
1150 return \"mov %1,%0\";
1152 return \"movr %1,%0\";
1154 return i960_output_ldconst (operands[0], operands[1]);
1156 return \"ld %1,%0\";
1158 return \"st %1,%0\";
1161 [(set_attr "type" "move,move,load,fpload,fpstore")])
1163 ;; Mixed-mode moves with sign and zero-extension.
1165 ;; Note that the one starting from HImode comes before those for QImode
1166 ;; so that a constant operand will match HImode, not QImode.
1168 (define_expand "extendhisi2"
1169 [(set (match_operand:SI 0 "register_operand" "")
1171 (match_operand:HI 1 "nonimmediate_operand" "")))]
1175 if (GET_CODE (operand1) == REG
1176 || (GET_CODE (operand1) == SUBREG
1177 && GET_CODE (XEXP (operand1, 0)) == REG))
1179 rtx temp = gen_reg_rtx (SImode);
1180 rtx shift_16 = GEN_INT (16);
1181 int op1_subreg_word = 0;
1183 if (GET_CODE (operand1) == SUBREG)
1185 op1_subreg_word = SUBREG_WORD (operand1);
1186 operand1 = SUBREG_REG (operand1);
1188 if (GET_MODE (operand1) != SImode)
1189 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1191 emit_insn (gen_ashlsi3 (temp, operand1, shift_16));
1192 emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
1198 [(set (match_operand:SI 0 "register_operand" "=d")
1199 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
1202 [(set_attr "type" "load")])
1204 (define_expand "extendqisi2"
1205 [(set (match_operand:SI 0 "register_operand" "")
1206 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1210 if (GET_CODE (operand1) == REG
1211 || (GET_CODE (operand1) == SUBREG
1212 && GET_CODE (XEXP (operand1, 0)) == REG))
1214 rtx temp = gen_reg_rtx (SImode);
1215 rtx shift_24 = GEN_INT (24);
1216 int op1_subreg_word = 0;
1218 if (GET_CODE (operand1) == SUBREG)
1220 op1_subreg_word = SUBREG_WORD (operand1);
1221 operand1 = SUBREG_REG (operand1);
1223 if (GET_MODE (operand1) != SImode)
1224 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1226 emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1227 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
1233 [(set (match_operand:SI 0 "register_operand" "=d")
1234 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
1237 [(set_attr "type" "load")])
1239 (define_expand "extendqihi2"
1240 [(set (match_operand:HI 0 "register_operand" "")
1242 (match_operand:QI 1 "nonimmediate_operand" "")))]
1246 if (GET_CODE (operand1) == REG
1247 || (GET_CODE (operand1) == SUBREG
1248 && GET_CODE (XEXP (operand1, 0)) == REG))
1250 rtx temp = gen_reg_rtx (SImode);
1251 rtx shift_24 = GEN_INT (24);
1252 int op0_subreg_word = 0;
1253 int op1_subreg_word = 0;
1255 if (GET_CODE (operand1) == SUBREG)
1257 op1_subreg_word = SUBREG_WORD (operand1);
1258 operand1 = SUBREG_REG (operand1);
1260 if (GET_MODE (operand1) != SImode)
1261 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1263 if (GET_CODE (operand0) == SUBREG)
1265 op0_subreg_word = SUBREG_WORD (operand0);
1266 operand0 = SUBREG_REG (operand0);
1268 if (GET_MODE (operand0) != SImode)
1269 operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word);
1271 emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1272 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
1278 [(set (match_operand:HI 0 "register_operand" "=d")
1279 (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
1282 [(set_attr "type" "load")])
1284 (define_expand "zero_extendhisi2"
1285 [(set (match_operand:SI 0 "register_operand" "")
1287 (match_operand:HI 1 "nonimmediate_operand" "")))]
1291 if (GET_CODE (operand1) == REG
1292 || (GET_CODE (operand1) == SUBREG
1293 && GET_CODE (XEXP (operand1, 0)) == REG))
1295 rtx temp = gen_reg_rtx (SImode);
1296 rtx shift_16 = GEN_INT (16);
1297 int op1_subreg_word = 0;
1299 if (GET_CODE (operand1) == SUBREG)
1301 op1_subreg_word = SUBREG_WORD (operand1);
1302 operand1 = SUBREG_REG (operand1);
1304 if (GET_MODE (operand1) != SImode)
1305 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1307 emit_insn (gen_ashlsi3 (temp, operand1, shift_16));
1308 emit_insn (gen_lshrsi3 (operand0, temp, shift_16));
1314 [(set (match_operand:SI 0 "register_operand" "=d")
1315 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
1318 [(set_attr "type" "load")])
1320 ;; Using shifts here generates much better code than doing an `and 255'.
1321 ;; This is mainly because the `and' requires loading the constant separately,
1322 ;; the constant is likely to get optimized, and then the compiler can't
1323 ;; optimize the `and' because it doesn't know that one operand is a constant.
1325 (define_expand "zero_extendqisi2"
1326 [(set (match_operand:SI 0 "register_operand" "")
1327 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1331 if (GET_CODE (operand1) == REG
1332 || (GET_CODE (operand1) == SUBREG
1333 && GET_CODE (XEXP (operand1, 0)) == REG))
1335 rtx temp = gen_reg_rtx (SImode);
1336 rtx shift_24 = GEN_INT (24);
1337 int op1_subreg_word = 0;
1339 if (GET_CODE (operand1) == SUBREG)
1341 op1_subreg_word = SUBREG_WORD (operand1);
1342 operand1 = SUBREG_REG (operand1);
1344 if (GET_MODE (operand1) != SImode)
1345 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1347 emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1348 emit_insn (gen_lshrsi3 (operand0, temp, shift_24));
1354 [(set (match_operand:SI 0 "register_operand" "=d")
1355 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
1358 [(set_attr "type" "load")])
1360 (define_expand "zero_extendqihi2"
1361 [(set (match_operand:HI 0 "register_operand" "")
1363 (match_operand:QI 1 "nonimmediate_operand" "")))]
1367 if (GET_CODE (operand1) == REG
1368 || (GET_CODE (operand1) == SUBREG
1369 && GET_CODE (XEXP (operand1, 0)) == REG))
1371 rtx temp = gen_reg_rtx (SImode);
1372 rtx shift_24 = GEN_INT (24);
1373 int op0_subreg_word = 0;
1374 int op1_subreg_word = 0;
1376 if (GET_CODE (operand1) == SUBREG)
1378 op1_subreg_word = SUBREG_WORD (operand1);
1379 operand1 = SUBREG_REG (operand1);
1381 if (GET_MODE (operand1) != SImode)
1382 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1384 if (GET_CODE (operand0) == SUBREG)
1386 op0_subreg_word = SUBREG_WORD (operand0);
1387 operand0 = SUBREG_REG (operand0);
1389 if (GET_MODE (operand0) != SImode)
1390 operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word);
1392 emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1393 emit_insn (gen_lshrsi3 (operand0, temp, shift_24));
1399 [(set (match_operand:HI 0 "register_operand" "=d")
1400 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
1403 [(set_attr "type" "load")])
1405 ;; Conversions between float and double.
1407 (define_insn "extendsfdf2"
1408 [(set (match_operand:DF 0 "register_operand" "=*f,d")
1409 (float_extend:DF (match_operand:SF 1 "fp_arith_operand" "dGH,fGH")))]
1414 [(set_attr "type" "fpmove")])
1416 (define_insn "truncdfsf2"
1417 [(set (match_operand:SF 0 "register_operand" "=d")
1419 (match_operand:DF 1 "fp_arith_operand" "fGH")))]
1422 [(set_attr "type" "fpmove")])
1424 ;; Conversion between fixed point and floating point.
1426 (define_insn "floatsidf2"
1427 [(set (match_operand:DF 0 "register_operand" "=f")
1428 (float:DF (match_operand:SI 1 "register_operand" "d")))]
1431 [(set_attr "type" "fpcvt")])
1433 (define_insn "floatsisf2"
1434 [(set (match_operand:SF 0 "register_operand" "=d*f")
1435 (float:SF (match_operand:SI 1 "register_operand" "d")))]
1438 [(set_attr "type" "fpcvt")])
1440 ;; Convert a float to an actual integer.
1441 ;; Truncation is performed as part of the conversion.
1442 ;; The i960 requires conversion from DFmode to DImode to make
1443 ;; unsigned conversions work properly.
1445 (define_insn "fixuns_truncdfdi2"
1446 [(set (match_operand:DI 0 "register_operand" "=d")
1447 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))]
1450 [(set_attr "type" "fpcvt")])
1452 (define_insn "fixuns_truncsfdi2"
1453 [(set (match_operand:DI 0 "register_operand" "=d")
1454 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "fp_arith_operand" "fGH"))))]
1457 [(set_attr "type" "fpcvt")])
1459 (define_insn "fix_truncdfsi2"
1460 [(set (match_operand:SI 0 "register_operand" "=d")
1461 (fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))]
1464 [(set_attr "type" "fpcvt")])
1466 (define_expand "fixuns_truncdfsi2"
1467 [(set (match_operand:SI 0 "register_operand" "")
1468 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" ""))))]
1472 rtx temp = gen_reg_rtx (DImode);
1473 emit_insn (gen_rtx (SET, VOIDmode, temp,
1474 gen_rtx (UNSIGNED_FIX, DImode,
1475 gen_rtx (FIX, DFmode, operands[1]))));
1476 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1477 gen_rtx (SUBREG, SImode, temp, 0)));
1481 (define_insn "fix_truncsfsi2"
1482 [(set (match_operand:SI 0 "register_operand" "=d")
1483 (fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" "dfGH"))))]
1486 [(set_attr "type" "fpcvt")])
1488 (define_expand "fixuns_truncsfsi2"
1489 [(set (match_operand:SI 0 "register_operand" "")
1490 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" ""))))]
1494 rtx temp = gen_reg_rtx (DImode);
1495 emit_insn (gen_rtx (SET, VOIDmode, temp,
1496 gen_rtx (UNSIGNED_FIX, DImode,
1497 gen_rtx (FIX, SFmode, operands[1]))));
1498 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1499 gen_rtx (SUBREG, SImode, temp, 0)));
1503 ;; Arithmetic instructions.
1505 (define_insn "subsi3"
1506 [(set (match_operand:SI 0 "register_operand" "=d")
1507 (minus:SI (match_operand:SI 1 "arith_operand" "dI")
1508 (match_operand:SI 2 "arith_operand" "dI")))]
1512 ;; Try to generate an lda instruction when it would be faster than an
1514 ;; Some assemblers apparently won't accept two addresses added together.
1516 ;; ??? The condition should be improved to reject the case of two
1517 ;; symbolic constants.
1520 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
1521 (plus:SI (match_operand:SI 1 "arith32_operand" "%dn,i,dn")
1522 (match_operand:SI 2 "arith32_operand" "dn,dn,i")))]
1523 "(TARGET_C_SERIES) && (CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))"
1526 if (GET_CODE (operands[1]) == CONST_INT)
1528 rtx tmp = operands[1];
1529 operands[1] = operands[2];
1532 if (GET_CODE (operands[2]) == CONST_INT
1533 && GET_CODE (operands[1]) == REG
1534 && i960_last_insn_type != I_TYPE_REG)
1536 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32)
1537 return \"subo %n2,%1,%0\";
1538 else if (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)
1539 return \"addo %1,%2,%0\";
1541 /* Non-canonical results (op1 == const, op2 != const) have been seen
1542 in reload output when both operands were symbols before reload, so
1543 we deal with it here. This may be a fault of the constraints above. */
1544 if (CONSTANT_P (operands[1]))
1546 if (CONSTANT_P (operands[2]))
1547 return \"lda %1+%2,%0\";
1549 return \"lda %1(%2),%0\";
1551 return \"lda %2(%1),%0\";
1554 (define_insn "addsi3"
1555 [(set (match_operand:SI 0 "register_operand" "=d")
1556 (plus:SI (match_operand:SI 1 "signed_arith_operand" "%dI")
1557 (match_operand:SI 2 "signed_arith_operand" "dIK")))]
1561 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1562 return \"subo %n2,%1,%0\";
1563 if (i960_bypass (insn, operands[1], operands[2], 0))
1564 return \"addo %2,%1,%0\";
1565 return \"addo %1,%2,%0\";
1568 (define_insn "mulsi3"
1569 [(set (match_operand:SI 0 "register_operand" "=d")
1570 (mult:SI (match_operand:SI 1 "arith_operand" "%dI")
1571 (match_operand:SI 2 "arith_operand" "dI")))]
1575 if (i960_bypass (insn, operands[1], operands[2], 0))
1576 return \"mulo %2,%1,%0\";
1577 return \"mulo %1,%2,%0\";
1579 [(set_attr "type" "mult")])
1581 (define_insn "umulsidi3"
1582 [(set (match_operand:DI 0 "register_operand" "=d")
1583 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
1584 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1588 if (i960_bypass (insn, operands[1], operands[2], 0))
1589 return \"emul %2,%1,%0\";
1590 return \"emul %1,%2,%0\";
1592 [(set_attr "type" "mult")])
1595 [(set (match_operand:DI 0 "register_operand" "=d")
1596 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%d"))
1597 (match_operand:SI 2 "literal" "I")))]
1601 if (i960_bypass (insn, operands[1], operands[2], 0))
1602 return \"emul %2,%1,%0\";
1603 return \"emul %1,%2,%0\";
1605 [(set_attr "type" "mult")])
1607 ;; This goes after the move/add/sub/mul instructions
1608 ;; because those instructions are better when they apply.
1611 [(set (match_operand:SI 0 "register_operand" "=d")
1612 (match_operand:SI 1 "address_operand" "p"))]
1615 [(set_attr "type" "load")])
1617 ;; This will never be selected because of an "optimization" that GCC does.
1618 ;; It always converts divides by a power of 2 into a sequence of instructions
1619 ;; that does a right shift, and then corrects the result if it was negative.
1622 ;; [(set (match_operand:SI 0 "register_operand" "=d")
1623 ;; (div:SI (match_operand:SI 1 "arith_operand" "dI")
1624 ;; (match_operand:SI 2 "power2_operand" "nI")))]
1627 ;; operands[2] = GEN_INT (bitpos (INTVAL (operands[2])));
1628 ;; return \"shrdi %2,%1,%0\";
1631 (define_insn "divsi3"
1632 [(set (match_operand:SI 0 "register_operand" "=d")
1633 (div:SI (match_operand:SI 1 "arith_operand" "dI")
1634 (match_operand:SI 2 "arith_operand" "dI")))]
1637 [(set_attr "type" "div")])
1639 (define_insn "udivsi3"
1640 [(set (match_operand:SI 0 "register_operand" "=d")
1641 (udiv:SI (match_operand:SI 1 "arith_operand" "dI")
1642 (match_operand:SI 2 "arith_operand" "dI")))]
1645 [(set_attr "type" "div")])
1647 ;; We must use `remi' not `modi' here, to ensure that `%' has the effects
1648 ;; specified by the ANSI C standard.
1650 (define_insn "modsi3"
1651 [(set (match_operand:SI 0 "register_operand" "=d")
1652 (mod:SI (match_operand:SI 1 "arith_operand" "dI")
1653 (match_operand:SI 2 "arith_operand" "dI")))]
1656 [(set_attr "type" "div")])
1658 (define_insn "umodsi3"
1659 [(set (match_operand:SI 0 "register_operand" "=d")
1660 (umod:SI (match_operand:SI 1 "arith_operand" "dI")
1661 (match_operand:SI 2 "arith_operand" "dI")))]
1664 [(set_attr "type" "div")])
1666 ;; And instructions (with complement also).
1668 (define_insn "andsi3"
1669 [(set (match_operand:SI 0 "register_operand" "=d")
1670 (and:SI (match_operand:SI 1 "register_operand" "%d")
1671 (match_operand:SI 2 "logic_operand" "dIM")))]
1675 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1676 return \"andnot %C2,%1,%0\";
1677 if (i960_bypass (insn, operands[1], operands[2], 0))
1678 return \"and %2,%1,%0\";
1679 return \"and %1,%2,%0\";
1683 [(set (match_operand:SI 0 "register_operand" "=d")
1684 (and:SI (match_operand:SI 1 "arith_operand" "dI")
1685 (match_operand:SI 2 "cmplpower2_operand" "n")))]
1689 operands[2] = GEN_INT (bitpos (~INTVAL (operands[2])));
1690 return \"clrbit %2,%1,%0\";
1694 [(set (match_operand:SI 0 "register_operand" "=d")
1695 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
1696 (match_operand:SI 2 "logic_operand" "dIM")))]
1700 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1701 return \"nor %C2,%1,%0\";
1702 if (i960_bypass (insn, operands[1], operands[2], 0))
1703 return \"notand %2,%1,%0\";
1704 return \"andnot %1,%2,%0\";
1708 [(set (match_operand:SI 0 "register_operand" "=d")
1709 (ior:SI (not:SI (match_operand:SI 1 "register_operand" "%d"))
1710 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
1714 if (i960_bypass (insn, operands[1], operands[2], 0))
1715 return \"nand %2,%1,%0\";
1716 return \"nand %1,%2,%0\";
1719 (define_insn "iorsi3"
1720 [(set (match_operand:SI 0 "register_operand" "=d")
1721 (ior:SI (match_operand:SI 1 "register_operand" "%d")
1722 (match_operand:SI 2 "logic_operand" "dIM")))]
1726 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1727 return \"ornot %C2,%1,%0\";
1728 if (i960_bypass (insn, operands[1], operands[2], 0))
1729 return \"or %2,%1,%0\";
1730 return \"or %1,%2,%0\";
1734 [(set (match_operand:SI 0 "register_operand" "=d")
1735 (ior:SI (match_operand:SI 1 "register_operand" "d")
1736 (match_operand:SI 2 "power2_operand" "n")))]
1740 operands[2] = GEN_INT (bitpos (INTVAL (operands[2])));
1741 return \"setbit %2,%1,%0\";
1745 [(set (match_operand:SI 0 "register_operand" "=d")
1746 (ior:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
1747 (match_operand:SI 2 "logic_operand" "dIM")))]
1751 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1752 return \"nand %C2,%1,%0\";
1753 if (i960_bypass (insn, operands[1], operands[2], 0))
1754 return \"notor %2,%1,%0\";
1755 return \"ornot %1,%2,%0\";
1759 [(set (match_operand:SI 0 "register_operand" "=d")
1760 (and:SI (not:SI (match_operand:SI 1 "register_operand" "%d"))
1761 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
1765 if (i960_bypass (insn, operands[1], operands[2], 0))
1766 return \"nor %2,%1,%0\";
1767 return \"nor %1,%2,%0\";
1770 (define_insn "xorsi3"
1771 [(set (match_operand:SI 0 "register_operand" "=d")
1772 (xor:SI (match_operand:SI 1 "register_operand" "%d")
1773 (match_operand:SI 2 "logic_operand" "dIM")))]
1777 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1778 return \"xnor %C2,%1,%0\";
1779 if (i960_bypass (insn, operands[1], operands[2], 0))
1780 return \"xor %2,%1,%0\";
1781 return \"xor %1,%2,%0\";
1785 [(set (match_operand:SI 0 "register_operand" "=d")
1786 (xor:SI (match_operand:SI 1 "arith_operand" "dI")
1787 (match_operand:SI 2 "power2_operand" "n")))]
1791 operands[2] = GEN_INT (bitpos (INTVAL (operands[2])));
1792 return \"notbit %2,%1,%0\";
1796 [(set (match_operand:SI 0 "register_operand" "=d")
1797 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%d")
1798 (match_operand:SI 2 "register_operand" "d"))))]
1802 if (i960_bypass (insn, operands[1], operands[2], 0))
1803 return \"xnor %2,%1,%0\";
1804 return \"xnor %2,%1,%0\";
1808 [(set (match_operand:SI 0 "register_operand" "=d")
1809 (ior:SI (ashift:SI (const_int 1)
1810 (match_operand:SI 1 "register_operand" "d"))
1811 (match_operand:SI 2 "arith_operand" "dI")))]
1815 ;; (not (ashift 1 reg)) canonicalizes to (rotate -2 reg)
1817 [(set (match_operand:SI 0 "register_operand" "=d")
1818 (and:SI (rotate:SI (const_int -2)
1819 (match_operand:SI 1 "register_operand" "d"))
1820 (match_operand:SI 2 "register_operand" "d")))]
1824 ;; The above pattern canonicalizes to this when both the input and output
1825 ;; are the same pseudo-register.
1827 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "=d")
1829 (match_operand:SI 1 "register_operand" "d"))
1835 [(set (match_operand:SI 0 "register_operand" "=d")
1836 (xor:SI (ashift:SI (const_int 1)
1837 (match_operand:SI 1 "register_operand" "d"))
1838 (match_operand:SI 2 "arith_operand" "dI")))]
1842 (define_insn "negsi2"
1843 [(set (match_operand:SI 0 "register_operand" "=d")
1844 (neg:SI (match_operand:SI 1 "arith_operand" "dI")))]
1847 [(set_attr "length" "1")])
1849 (define_insn "one_cmplsi2"
1850 [(set (match_operand:SI 0 "register_operand" "=d")
1851 (not:SI (match_operand:SI 1 "arith_operand" "dI")))]
1854 [(set_attr "length" "1")])
1856 ;; Floating point arithmetic instructions.
1858 (define_insn "adddf3"
1859 [(set (match_operand:DF 0 "register_operand" "=d*f")
1860 (plus:DF (match_operand:DF 1 "fp_arith_operand" "%rGH")
1861 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1864 [(set_attr "type" "fpadd")])
1866 (define_insn "addsf3"
1867 [(set (match_operand:SF 0 "register_operand" "=d*f")
1868 (plus:SF (match_operand:SF 1 "fp_arith_operand" "%rGH")
1869 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1872 [(set_attr "type" "fpadd")])
1875 (define_insn "subdf3"
1876 [(set (match_operand:DF 0 "register_operand" "=d*f")
1877 (minus:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
1878 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1881 [(set_attr "type" "fpadd")])
1883 (define_insn "subsf3"
1884 [(set (match_operand:SF 0 "register_operand" "=d*f")
1885 (minus:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
1886 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1889 [(set_attr "type" "fpadd")])
1892 (define_insn "muldf3"
1893 [(set (match_operand:DF 0 "register_operand" "=d*f")
1894 (mult:DF (match_operand:DF 1 "fp_arith_operand" "%rGH")
1895 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1898 [(set_attr "type" "fpmul")])
1900 (define_insn "mulsf3"
1901 [(set (match_operand:SF 0 "register_operand" "=d*f")
1902 (mult:SF (match_operand:SF 1 "fp_arith_operand" "%rGH")
1903 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1906 [(set_attr "type" "fpmul")])
1909 (define_insn "divdf3"
1910 [(set (match_operand:DF 0 "register_operand" "=d*f")
1911 (div:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
1912 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1915 [(set_attr "type" "fpdiv")])
1917 (define_insn "divsf3"
1918 [(set (match_operand:SF 0 "register_operand" "=d*f")
1919 (div:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
1920 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1923 [(set_attr "type" "fpdiv")])
1925 (define_insn "negdf2"
1926 [(set (match_operand:DF 0 "register_operand" "=d,d*f")
1927 (neg:DF (match_operand:DF 1 "register_operand" "d,r")))]
1931 if (which_alternative == 0)
1933 if (REGNO (operands[0]) == REGNO (operands[1]))
1934 return \"notbit 31,%D1,%D0\";
1935 return \"mov %1,%0\;notbit 31,%D1,%D0\";
1937 return \"subrl %1,0f0.0,%0\";
1939 [(set_attr "type" "fpadd")])
1941 (define_insn "negsf2"
1942 [(set (match_operand:SF 0 "register_operand" "=d,d*f")
1943 (neg:SF (match_operand:SF 1 "register_operand" "d,r")))]
1948 [(set_attr "type" "fpadd")])
1950 ;;; The abs patterns also work even if the target machine doesn't have
1951 ;;; floating point, because in that case dstreg and srcreg will always be
1954 (define_insn "absdf2"
1955 [(set (match_operand:DF 0 "register_operand" "=d*f")
1956 (abs:DF (match_operand:DF 1 "register_operand" "df")))]
1960 int dstreg = REGNO (operands[0]);
1961 int srcreg = REGNO (operands[1]);
1967 if (dstreg != srcreg)
1968 output_asm_insn (\"mov %1,%0\", operands);
1969 return \"clrbit 31,%D1,%D0\";
1971 /* Src is an fp reg. */
1972 return \"movrl %1,%0\;clrbit 31,%D1,%D0\";
1975 return \"cpysre %1,0f0.0,%0\";
1976 return \"movrl %1,%0\;cpysre %0,0f0.0,%0\";
1978 [(set_attr "type" "multi")])
1980 (define_insn "abssf2"
1981 [(set (match_operand:SF 0 "register_operand" "=d*f")
1982 (abs:SF (match_operand:SF 1 "register_operand" "df")))]
1986 int dstreg = REGNO (operands[0]);
1987 int srcreg = REGNO (operands[1]);
1989 if (dstreg < 32 && srcreg < 32)
1990 return \"clrbit 31,%1,%0\";
1992 if (dstreg >= 32 && srcreg >= 32)
1993 return \"cpysre %1,0f0.0,%0\";
1996 return \"movr %1,%0\;clrbit 31,%0,%0\";
1998 return \"movr %1,%0\;cpysre %0,0f0.0,%0\";
2000 [(set_attr "type" "multi")])
2002 ;; Tetra (16 byte) float support.
2004 (define_expand "cmpxf"
2006 (compare:CC (match_operand:XF 0 "register_operand" "")
2007 (match_operand:XF 1 "nonmemory_operand" "")))]
2011 i960_compare_op0 = operands[0];
2012 i960_compare_op1 = operands[1];
2018 (compare:CC (match_operand:XF 0 "register_operand" "f")
2019 (match_operand:XF 1 "nonmemory_operand" "fGH")))]
2022 [(set_attr "type" "fpcc")])
2024 (define_expand "movxf"
2025 [(set (match_operand:XF 0 "general_operand" "")
2026 (match_operand:XF 1 "fpmove_src_operand" ""))]
2030 if (emit_move_sequence (operands, XFmode))
2035 [(set (match_operand:XF 0 "general_operand" "=r,f,d,d,m")
2036 (match_operand:XF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
2037 "register_operand (operands[0], XFmode)
2038 || register_operand (operands[1], XFmode)"
2041 switch (which_alternative)
2044 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
2045 return \"movre %1,%0\";
2047 return \"movq %1,%0\";
2049 return \"movre %1,%0\";
2051 return i960_output_ldconst (operands[0], operands[1]);
2053 return \"ldt %1,%0\";
2055 return \"stt %1,%0\";
2058 [(set_attr "type" "move,move,load,fpload,fpstore")])
2060 (define_insn "extendsfxf2"
2061 [(set (match_operand:XF 0 "register_operand" "=f,d")
2063 (match_operand:SF 1 "register_operand" "d,f")))]
2068 [(set_attr "type" "fpmove")])
2070 (define_insn "extenddfxf2"
2071 [(set (match_operand:XF 0 "register_operand" "=f,d")
2073 (match_operand:DF 1 "register_operand" "d,f")))]
2078 [(set_attr "type" "fpmove")])
2080 (define_insn "truncxfdf2"
2081 [(set (match_operand:DF 0 "register_operand" "=d")
2083 (match_operand:XF 1 "register_operand" "f")))]
2086 [(set_attr "type" "fpmove")])
2088 (define_insn "truncxfsf2"
2089 [(set (match_operand:SF 0 "register_operand" "=d")
2091 (match_operand:XF 1 "register_operand" "f")))]
2094 [(set_attr "type" "fpmove")])
2096 (define_insn "floatsixf2"
2097 [(set (match_operand:XF 0 "register_operand" "=f")
2098 (float:XF (match_operand:SI 1 "register_operand" "d")))]
2101 [(set_attr "type" "fpcvt")])
2103 (define_insn "fix_truncxfsi2"
2104 [(set (match_operand:SI 0 "register_operand" "=d")
2105 (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
2108 [(set_attr "type" "fpcvt")])
2110 (define_insn "fixuns_truncxfsi2"
2111 [(set (match_operand:SI 0 "register_operand" "=d")
2112 (unsigned_fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
2115 [(set_attr "type" "fpcvt")])
2117 (define_insn "addxf3"
2118 [(set (match_operand:XF 0 "register_operand" "=f")
2119 (plus:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
2120 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
2123 [(set_attr "type" "fpadd")])
2125 (define_insn "subxf3"
2126 [(set (match_operand:XF 0 "register_operand" "=f")
2127 (minus:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
2128 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
2131 [(set_attr "type" "fpadd")])
2133 (define_insn "mulxf3"
2134 [(set (match_operand:XF 0 "register_operand" "=f")
2135 (mult:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
2136 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
2139 [(set_attr "type" "fpmul")])
2141 (define_insn "divxf3"
2142 [(set (match_operand:XF 0 "register_operand" "=f")
2143 (div:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
2144 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
2147 [(set_attr "type" "fpdiv")])
2149 (define_insn "negxf2"
2150 [(set (match_operand:XF 0 "register_operand" "=f")
2151 (neg:XF (match_operand:XF 1 "register_operand" "f")))]
2154 [(set_attr "type" "fpadd")])
2156 (define_insn "absxf2"
2157 [(set (match_operand:XF 0 "register_operand" "=f")
2158 (abs:XF (match_operand:XF 1 "register_operand" "f")))]
2160 "cpysre %1,0f0.0,%0"
2161 [(set_attr "type" "fpmove")])
2163 ;; Arithmetic shift instructions.
2165 ;; The shli instruction generates an overflow fault if the sign changes.
2166 ;; In the case of overflow, it does not give the natural result, it instead
2167 ;; gives the last shift value before the overflow. We can not use this
2168 ;; instruction because gcc thinks that arithmetic left shift and logical
2169 ;; left shift are identical, and sometimes canonicalizes the logical left
2170 ;; shift to an arithmetic left shift. Therefore we must always use the
2171 ;; logical left shift instruction.
2173 (define_insn "ashlsi3"
2174 [(set (match_operand:SI 0 "register_operand" "=d")
2175 (ashift:SI (match_operand:SI 1 "arith_operand" "dI")
2176 (match_operand:SI 2 "arith_operand" "dI")))]
2179 [(set_attr "type" "alu2")])
2181 (define_insn "ashrsi3"
2182 [(set (match_operand:SI 0 "register_operand" "=d")
2183 (ashiftrt:SI (match_operand:SI 1 "arith_operand" "dI")
2184 (match_operand:SI 2 "arith_operand" "dI")))]
2187 [(set_attr "type" "alu2")])
2189 (define_insn "lshrsi3"
2190 [(set (match_operand:SI 0 "register_operand" "=d")
2191 (lshiftrt:SI (match_operand:SI 1 "arith_operand" "dI")
2192 (match_operand:SI 2 "arith_operand" "dI")))]
2195 [(set_attr "type" "alu2")])
2197 ;; Unconditional and other jump instructions.
2201 (label_ref (match_operand 0 "" "")))]
2204 [(set_attr "type" "branch")])
2206 (define_insn "indirect_jump"
2207 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
2210 [(set_attr "type" "branch")])
2212 (define_insn "tablejump"
2213 [(set (pc) (match_operand:SI 0 "register_operand" "d"))
2214 (use (label_ref (match_operand 1 "" "")))]
2219 return \"bx %l1(%0)\";
2223 [(set_attr "type" "branch")])
2225 ;;- jump to subroutine
2227 (define_expand "call"
2228 [(call (match_operand:SI 0 "memory_operand" "m")
2229 (match_operand:SI 1 "immediate_operand" "i"))]
2233 emit_insn (gen_call_internal (operands[0], operands[1],
2234 virtual_outgoing_args_rtx));
2238 ;; We need a call saved register allocated for the match_scratch, so we use
2239 ;; 'l' because all local registers are call saved.
2241 ;; ??? I would prefer to use a match_scratch here, but match_scratch allocated
2242 ;; registers can't be used for spills. In a function with lots of calls,
2243 ;; local-alloc may allocate all local registers to a match_scratch, leaving
2244 ;; no local registers available for spills.
2246 (define_insn "call_internal"
2247 [(call (match_operand:SI 0 "memory_operand" "m")
2248 (match_operand:SI 1 "immediate_operand" "i"))
2249 (use (match_operand:SI 2 "address_operand" "p"))
2250 (clobber (reg:SI 19))]
2252 "* return i960_output_call_insn (operands[0], operands[1], operands[2],
2254 [(set_attr "type" "call")])
2256 (define_expand "call_value"
2257 [(set (match_operand 0 "register_operand" "=d")
2258 (call (match_operand:SI 1 "memory_operand" "m")
2259 (match_operand:SI 2 "immediate_operand" "i")))]
2263 emit_insn (gen_call_value_internal (operands[0], operands[1], operands[2],
2264 virtual_outgoing_args_rtx));
2268 ;; We need a call saved register allocated for the match_scratch, so we use
2269 ;; 'l' because all local registers are call saved.
2271 (define_insn "call_value_internal"
2272 [(set (match_operand 0 "register_operand" "=d")
2273 (call (match_operand:SI 1 "memory_operand" "m")
2274 (match_operand:SI 2 "immediate_operand" "i")))
2275 (use (match_operand:SI 3 "address_operand" "p"))
2276 (clobber (reg:SI 19))]
2278 "* return i960_output_call_insn (operands[1], operands[2], operands[3],
2280 [(set_attr "type" "call")])
2282 (define_insn "return"
2285 "* return i960_output_ret_insn (insn);"
2286 [(set_attr "type" "branch")])
2288 ;; A return instruction. Used only by nonlocal_goto to change the
2289 ;; stack pointer, frame pointer, previous frame pointer and the return
2290 ;; instruction pointer.
2293 (unspec_volatile [(const_int 0)] 3)]
2296 [(set_attr "type" "branch")
2297 (set_attr "length" "1")])
2299 (define_expand "nonlocal_goto"
2300 [(match_operand:SI 0 "" "")
2301 (match_operand:SI 1 "general_operand" "")
2302 (match_operand:SI 2 "general_operand" "")
2303 (match_operand:SI 3 "general_operand" "")]
2307 rtx chain = operands[0];
2308 rtx handler = operands[1];
2309 rtx stack = operands[2];
2310 rtx label = operands[3];
2312 /* We must restore the stack pointer, frame pointer, previous frame
2313 pointer and the return instruction pointer. Since the ret
2314 instruction does all this for us with one instruction, we arrange
2315 everything so that ret will do everything we need done. */
2317 /* First, we must flush the register windows, so that we can modify
2318 the saved local registers on the stack directly and because we
2319 are going to change the previous frame pointer. */
2321 emit_insn (gen_flush_register_windows ());
2323 /* Load the static chain value for the containing fn into fp. This is needed
2324 because STACK refers to fp. */
2325 emit_move_insn (hard_frame_pointer_rtx, chain);
2327 /* Now move the adjusted value into the pfp register for the following return
2329 emit_move_insn (gen_rtx (REG, SImode, 16),
2330 plus_constant (hard_frame_pointer_rtx, -64));
2332 /* Next, we put the address that we want to transfer to, into the
2333 saved $rip value in the frame. Once we ret below, that value
2334 will be loaded into the pc (IP). */
2336 emit_move_insn (gen_rtx (MEM, SImode,
2337 plus_constant (hard_frame_pointer_rtx, -56)),
2338 replace_rtx (copy_rtx (handler), virtual_stack_vars_rtx,
2339 hard_frame_pointer_rtx));
2341 /* Next, we put stack into the saved $sp value in the frame. */
2342 emit_move_insn (gen_rtx (MEM, SImode,
2343 plus_constant (hard_frame_pointer_rtx, -60)),
2344 replace_rtx (copy_rtx (stack), virtual_stack_vars_rtx,
2345 hard_frame_pointer_rtx));
2347 /* And finally, we can now just ret to get all the values saved
2348 above into all the right registers, and also, all the local
2349 register that were in use in the function, are restored from
2350 their saved values (from the call instruction) on the stack
2351 because we are very careful to ret from the exact save area in
2352 use during the original call. */
2354 emit_insn (gen_ret ());
2359 ;; Special insn to flush register windows.
2360 (define_insn "flush_register_windows"
2361 [(unspec_volatile [(const_int 0)] 1)]
2364 [(set_attr "type" "misc")
2365 (set_attr "length" "1")])
2372 ;; Various peephole optimizations for multiple-word moves, loads, and stores.
2373 ;; Multiple register moves.
2377 [(set (match_operand:SI 0 "register_operand" "=r")
2378 (match_operand:SI 1 "register_operand" "r"))
2379 (set (match_operand:SI 2 "register_operand" "=r")
2380 (match_operand:SI 3 "register_operand" "r"))
2381 (set (match_operand:SI 4 "register_operand" "=r")
2382 (match_operand:SI 5 "register_operand" "r"))
2383 (set (match_operand:SI 6 "register_operand" "=r")
2384 (match_operand:SI 7 "register_operand" "r"))]
2385 "((REGNO (operands[0]) & 3) == 0)
2386 && ((REGNO (operands[1]) & 3) == 0)
2387 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2388 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2389 && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2390 && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
2391 && (REGNO (operands[0]) + 3 == REGNO (operands[6]))
2392 && (REGNO (operands[1]) + 3 == REGNO (operands[7]))"
2397 [(set (match_operand:DI 0 "register_operand" "=r")
2398 (match_operand:DI 1 "register_operand" "r"))
2399 (set (match_operand:DI 2 "register_operand" "=r")
2400 (match_operand:DI 3 "register_operand" "r"))]
2401 "((REGNO (operands[0]) & 3) == 0)
2402 && ((REGNO (operands[1]) & 3) == 0)
2403 && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
2404 && (REGNO (operands[1]) + 2 == REGNO (operands[3]))"
2409 [(set (match_operand:DI 0 "register_operand" "=r")
2410 (match_operand:DI 1 "register_operand" "r"))
2411 (set (match_operand:SI 2 "register_operand" "=r")
2412 (match_operand:SI 3 "register_operand" "r"))
2413 (set (match_operand:SI 4 "register_operand" "=r")
2414 (match_operand:SI 5 "register_operand" "r"))]
2415 "((REGNO (operands[0]) & 3) == 0)
2416 && ((REGNO (operands[1]) & 3) == 0)
2417 && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
2418 && (REGNO (operands[1]) + 2 == REGNO (operands[3]))
2419 && (REGNO (operands[0]) + 3 == REGNO (operands[4]))
2420 && (REGNO (operands[1]) + 3 == REGNO (operands[5]))"
2425 [(set (match_operand:SI 0 "register_operand" "=r")
2426 (match_operand:SI 1 "register_operand" "r"))
2427 (set (match_operand:SI 2 "register_operand" "=r")
2428 (match_operand:SI 3 "register_operand" "r"))
2429 (set (match_operand:DI 4 "register_operand" "=r")
2430 (match_operand:DI 5 "register_operand" "r"))]
2431 "((REGNO (operands[0]) & 3) == 0)
2432 && ((REGNO (operands[1]) & 3) == 0)
2433 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2434 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2435 && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2436 && (REGNO (operands[1]) + 2 == REGNO (operands[5]))"
2441 [(set (match_operand:DI 0 "register_operand" "=r")
2442 (match_operand:DI 1 "register_operand" "r"))
2443 (set (match_operand:SI 2 "register_operand" "=r")
2444 (match_operand:SI 3 "register_operand" "r"))]
2445 "((REGNO (operands[0]) & 3) == 0)
2446 && ((REGNO (operands[1]) & 3) == 0)
2447 && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
2448 && (REGNO (operands[1]) + 2 == REGNO (operands[3]))"
2453 [(set (match_operand:SI 0 "register_operand" "=r")
2454 (match_operand:SI 1 "register_operand" "r"))
2455 (set (match_operand:SI 2 "register_operand" "=r")
2456 (match_operand:SI 3 "register_operand" "r"))
2457 (set (match_operand:SI 4 "register_operand" "=r")
2458 (match_operand:SI 5 "register_operand" "r"))]
2459 "((REGNO (operands[0]) & 3) == 0)
2460 && ((REGNO (operands[1]) & 3) == 0)
2461 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2462 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2463 && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2464 && (REGNO (operands[1]) + 2 == REGNO (operands[5]))"
2469 [(set (match_operand:SI 0 "register_operand" "=r")
2470 (match_operand:SI 1 "register_operand" "r"))
2471 (set (match_operand:SI 2 "register_operand" "=r")
2472 (match_operand:SI 3 "register_operand" "r"))]
2473 "((REGNO (operands[0]) & 1) == 0)
2474 && ((REGNO (operands[1]) & 1) == 0)
2475 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2476 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))"
2479 ; Multiple register loads.
2483 [(set (match_operand:SI 0 "register_operand" "=r")
2484 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
2485 (match_operand:SI 2 "immediate_operand" "n"))))
2486 (set (match_operand:SI 3 "register_operand" "=r")
2487 (mem:SI (plus:SI (match_dup 1)
2488 (match_operand:SI 4 "immediate_operand" "n"))))
2489 (set (match_operand:SI 5 "register_operand" "=r")
2490 (mem:SI (plus:SI (match_dup 1)
2491 (match_operand:SI 6 "immediate_operand" "n"))))
2492 (set (match_operand:SI 7 "register_operand" "=r")
2493 (mem:SI (plus:SI (match_dup 1)
2494 (match_operand:SI 8 "immediate_operand" "n"))))]
2495 "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2496 && (REGNO (operands[1]) != REGNO (operands[0]))
2497 && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
2498 && (REGNO (operands[1]) != REGNO (operands[3]))
2499 && (REGNO (operands[0]) + 2 == REGNO (operands[5]))
2500 && (REGNO (operands[1]) != REGNO (operands[5]))
2501 && (REGNO (operands[0]) + 3 == REGNO (operands[7]))
2502 && (INTVAL (operands[2]) + 4 == INTVAL (operands[4]))
2503 && (INTVAL (operands[2]) + 8 == INTVAL (operands[6]))
2504 && (INTVAL (operands[2]) + 12 == INTVAL (operands[8])))"
2509 [(set (match_operand:DF 0 "register_operand" "=d")
2510 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
2511 (match_operand:SI 2 "immediate_operand" "n"))))
2512 (set (match_operand:DF 3 "register_operand" "=d")
2513 (mem:DF (plus:SI (match_dup 1)
2514 (match_operand:SI 4 "immediate_operand" "n"))))]
2515 "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2516 && (REGNO (operands[1]) != REGNO (operands[0]))
2517 && (REGNO (operands[0]) + 2 == REGNO (operands[3]))
2518 && (REGNO (operands[1]) != REGNO (operands[3]))
2519 && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))"
2524 [(set (match_operand:DI 0 "register_operand" "=d")
2525 (mem:DI (plus:SI (match_operand:SI 1 "register_operand" "d")
2526 (match_operand:SI 2 "immediate_operand" "n"))))
2527 (set (match_operand:DI 3 "register_operand" "=d")
2528 (mem:DI (plus:SI (match_dup 1)
2529 (match_operand:SI 4 "immediate_operand" "n"))))]
2530 "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2531 && (REGNO (operands[1]) != REGNO (operands[0]))
2532 && (REGNO (operands[0]) + 2 == REGNO (operands[3]))
2533 && (REGNO (operands[1]) != REGNO (operands[3]))
2534 && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))"
2539 [(set (match_operand:SI 0 "register_operand" "=d")
2540 (mem:SI (match_operand:SI 1 "register_operand" "d")))
2541 (set (match_operand:SI 2 "register_operand" "=d")
2542 (mem:SI (plus:SI (match_dup 1)
2543 (match_operand:SI 3 "immediate_operand" "n"))))
2544 (set (match_operand:SI 4 "register_operand" "=d")
2545 (mem:SI (plus:SI (match_dup 1)
2546 (match_operand:SI 5 "immediate_operand" "n"))))
2547 (set (match_operand:SI 6 "register_operand" "=d")
2548 (mem:SI (plus:SI (match_dup 1)
2549 (match_operand:SI 7 "immediate_operand" "n"))))]
2550 "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0)
2551 && (REGNO (operands[1]) != REGNO (operands[0]))
2552 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2553 && (REGNO (operands[1]) != REGNO (operands[2]))
2554 && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2555 && (REGNO (operands[1]) != REGNO (operands[4]))
2556 && (REGNO (operands[0]) + 3 == REGNO (operands[6]))
2557 && (INTVAL (operands[3]) == 4)
2558 && (INTVAL (operands[5]) == 8)
2559 && (INTVAL (operands[7]) == 12))"
2564 [(set (match_operand:SI 0 "register_operand" "=d")
2565 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
2566 (match_operand:SI 2 "immediate_operand" "n"))))
2567 (set (match_operand:SI 3 "register_operand" "=d")
2568 (mem:SI (plus:SI (match_dup 1)
2569 (match_operand:SI 4 "immediate_operand" "n"))))
2570 (set (match_operand:SI 5 "register_operand" "=d")
2571 (mem:SI (plus:SI (match_dup 1)
2572 (match_operand:SI 6 "immediate_operand" "n"))))]
2573 "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2574 && (REGNO (operands[1]) != REGNO (operands[0]))
2575 && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
2576 && (REGNO (operands[1]) != REGNO (operands[3]))
2577 && (REGNO (operands[0]) + 2 == REGNO (operands[5]))
2578 && (INTVAL (operands[2]) + 4 == INTVAL (operands[4]))
2579 && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])))"
2584 [(set (match_operand:SI 0 "register_operand" "=d")
2585 (mem:SI (match_operand:SI 1 "register_operand" "d")))
2586 (set (match_operand:SI 2 "register_operand" "=d")
2587 (mem:SI (plus:SI (match_dup 1)
2588 (match_operand:SI 3 "immediate_operand" "n"))))
2589 (set (match_operand:SI 4 "register_operand" "=d")
2590 (mem:SI (plus:SI (match_dup 1)
2591 (match_operand:SI 5 "immediate_operand" "n"))))]
2592 "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0)
2593 && (REGNO (operands[1]) != REGNO (operands[0]))
2594 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2595 && (REGNO (operands[1]) != REGNO (operands[2]))
2596 && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2597 && (INTVAL (operands[3]) == 4)
2598 && (INTVAL (operands[5]) == 8))"
2603 [(set (match_operand:SI 0 "register_operand" "=d")
2604 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
2605 (match_operand:SI 2 "immediate_operand" "n"))))
2606 (set (match_operand:SI 3 "register_operand" "=d")
2607 (mem:SI (plus:SI (match_dup 1)
2608 (match_operand:SI 4 "immediate_operand" "n"))))]
2609 "(i960_si_di (operands[1], operands[2]) && ((REGNO (operands[0]) & 1) == 0)
2610 && (REGNO (operands[1]) != REGNO (operands[0]))
2611 && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
2612 && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])))"
2617 [(set (match_operand:SI 0 "register_operand" "=d")
2618 (mem:SI (match_operand:SI 1 "register_operand" "d")))
2619 (set (match_operand:SI 2 "register_operand" "=d")
2620 (mem:SI (plus:SI (match_dup 1)
2621 (match_operand:SI 3 "immediate_operand" "n"))))]
2622 "(i960_si_di (operands[1], 0) && ((REGNO (operands[0]) & 1) == 0)
2623 && (REGNO (operands[1]) != REGNO (operands[0]))
2624 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2625 && (INTVAL (operands[3]) == 4))"
2628 ; Multiple register stores.
2632 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
2633 (match_operand:SI 1 "immediate_operand" "n")))
2634 (match_operand:SI 2 "register_operand" "d"))
2635 (set (mem:SI (plus:SI (match_dup 0)
2636 (match_operand:SI 3 "immediate_operand" "n")))
2637 (match_operand:SI 4 "register_operand" "d"))
2638 (set (mem:SI (plus:SI (match_dup 0)
2639 (match_operand:SI 5 "immediate_operand" "n")))
2640 (match_operand:SI 6 "register_operand" "d"))
2641 (set (mem:SI (plus:SI (match_dup 0)
2642 (match_operand:SI 7 "immediate_operand" "n")))
2643 (match_operand:SI 8 "register_operand" "d"))]
2644 "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2645 && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
2646 && (REGNO (operands[2]) + 2 == REGNO (operands[6]))
2647 && (REGNO (operands[2]) + 3 == REGNO (operands[8]))
2648 && (INTVAL (operands[1]) + 4 == INTVAL (operands[3]))
2649 && (INTVAL (operands[1]) + 8 == INTVAL (operands[5]))
2650 && (INTVAL (operands[1]) + 12 == INTVAL (operands[7])))"
2655 [(set (mem:DF (plus:SI (match_operand:SI 0 "register_operand" "d")
2656 (match_operand:SI 1 "immediate_operand" "n")))
2657 (match_operand:DF 2 "register_operand" "d"))
2658 (set (mem:DF (plus:SI (match_dup 0)
2659 (match_operand:SI 3 "immediate_operand" "n")))
2660 (match_operand:DF 4 "register_operand" "d"))]
2661 "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2662 && (REGNO (operands[2]) + 2 == REGNO (operands[4]))
2663 && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))"
2668 [(set (mem:DI (plus:SI (match_operand:SI 0 "register_operand" "d")
2669 (match_operand:SI 1 "immediate_operand" "n")))
2670 (match_operand:DI 2 "register_operand" "d"))
2671 (set (mem:DI (plus:SI (match_dup 0)
2672 (match_operand:SI 3 "immediate_operand" "n")))
2673 (match_operand:DI 4 "register_operand" "d"))]
2674 "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2675 && (REGNO (operands[2]) + 2 == REGNO (operands[4]))
2676 && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))"
2681 [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
2682 (match_operand:SI 1 "register_operand" "d"))
2683 (set (mem:SI (plus:SI (match_dup 0)
2684 (match_operand:SI 2 "immediate_operand" "n")))
2685 (match_operand:SI 3 "register_operand" "d"))
2686 (set (mem:SI (plus:SI (match_dup 0)
2687 (match_operand:SI 4 "immediate_operand" "n")))
2688 (match_operand:SI 5 "register_operand" "d"))
2689 (set (mem:SI (plus:SI (match_dup 0)
2690 (match_operand:SI 6 "immediate_operand" "n")))
2691 (match_operand:SI 7 "register_operand" "d"))]
2692 "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0)
2693 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2694 && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
2695 && (REGNO (operands[1]) + 3 == REGNO (operands[7]))
2696 && (INTVAL (operands[2]) == 4)
2697 && (INTVAL (operands[4]) == 8)
2698 && (INTVAL (operands[6]) == 12))"
2703 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
2704 (match_operand:SI 1 "immediate_operand" "n")))
2705 (match_operand:SI 2 "register_operand" "d"))
2706 (set (mem:SI (plus:SI (match_dup 0)
2707 (match_operand:SI 3 "immediate_operand" "n")))
2708 (match_operand:SI 4 "register_operand" "d"))
2709 (set (mem:SI (plus:SI (match_dup 0)
2710 (match_operand:SI 5 "immediate_operand" "n")))
2711 (match_operand:SI 6 "register_operand" "d"))]
2712 "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2713 && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
2714 && (REGNO (operands[2]) + 2 == REGNO (operands[6]))
2715 && (INTVAL (operands[1]) + 4 == INTVAL (operands[3]))
2716 && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])))"
2721 [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
2722 (match_operand:SI 1 "register_operand" "d"))
2723 (set (mem:SI (plus:SI (match_dup 0)
2724 (match_operand:SI 2 "immediate_operand" "n")))
2725 (match_operand:SI 3 "register_operand" "d"))
2726 (set (mem:SI (plus:SI (match_dup 0)
2727 (match_operand:SI 4 "immediate_operand" "n")))
2728 (match_operand:SI 5 "register_operand" "d"))]
2729 "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0)
2730 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2731 && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
2732 && (INTVAL (operands[2]) == 4)
2733 && (INTVAL (operands[4]) == 8))"
2738 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
2739 (match_operand:SI 1 "immediate_operand" "n")))
2740 (match_operand:SI 2 "register_operand" "d"))
2741 (set (mem:SI (plus:SI (match_dup 0)
2742 (match_operand:SI 3 "immediate_operand" "n")))
2743 (match_operand:SI 4 "register_operand" "d"))]
2744 "(i960_si_di (operands[0], operands[1]) && ((REGNO (operands[2]) & 1) == 0)
2745 && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
2746 && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])))"
2751 [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
2752 (match_operand:SI 1 "register_operand" "d"))
2753 (set (mem:SI (plus:SI (match_dup 0)
2754 (match_operand:SI 2 "immediate_operand" "n")))
2755 (match_operand:SI 3 "register_operand" "d"))]
2756 "(i960_si_di (operands[0], 0) && ((REGNO (operands[1]) & 1) == 0)
2757 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2758 && (INTVAL (operands[2]) == 4))"