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1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999-2014 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "stringpool.h"
29 #include "stor-layout.h"
30 #include "calls.h"
31 #include "varasm.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "recog.h"
40 #include "expr.h"
41 #include "optabs.h"
42 #include "except.h"
43 #include "function.h"
44 #include "ggc.h"
45 #include "basic-block.h"
46 #include "libfuncs.h"
47 #include "diagnostic-core.h"
48 #include "sched-int.h"
49 #include "timevar.h"
50 #include "target.h"
51 #include "target-def.h"
52 #include "common/common-target.h"
53 #include "tm_p.h"
54 #include "hash-table.h"
55 #include "langhooks.h"
56 #include "vec.h"
57 #include "basic-block.h"
58 #include "tree-ssa-alias.h"
59 #include "internal-fn.h"
60 #include "gimple-fold.h"
61 #include "tree-eh.h"
62 #include "gimple-expr.h"
63 #include "is-a.h"
64 #include "gimple.h"
65 #include "gimplify.h"
66 #include "intl.h"
67 #include "df.h"
68 #include "debug.h"
69 #include "params.h"
70 #include "dbgcnt.h"
71 #include "tm-constrs.h"
72 #include "sel-sched.h"
73 #include "reload.h"
74 #include "opts.h"
75 #include "dumpfile.h"
76 #include "builtins.h"
77
78 /* This is used for communication between ASM_OUTPUT_LABEL and
79 ASM_OUTPUT_LABELREF. */
80 int ia64_asm_output_label = 0;
81
82 /* Register names for ia64_expand_prologue. */
83 static const char * const ia64_reg_numbers[96] =
84 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
85 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
86 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
87 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
88 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
89 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
90 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
91 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
92 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
93 "r104","r105","r106","r107","r108","r109","r110","r111",
94 "r112","r113","r114","r115","r116","r117","r118","r119",
95 "r120","r121","r122","r123","r124","r125","r126","r127"};
96
97 /* ??? These strings could be shared with REGISTER_NAMES. */
98 static const char * const ia64_input_reg_names[8] =
99 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
100
101 /* ??? These strings could be shared with REGISTER_NAMES. */
102 static const char * const ia64_local_reg_names[80] =
103 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
104 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
105 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
106 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
107 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
108 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
109 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
110 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
111 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
112 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
113
114 /* ??? These strings could be shared with REGISTER_NAMES. */
115 static const char * const ia64_output_reg_names[8] =
116 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
117
118 /* Variables which are this size or smaller are put in the sdata/sbss
119 sections. */
120
121 unsigned int ia64_section_threshold;
122
123 /* The following variable is used by the DFA insn scheduler. The value is
124 TRUE if we do insn bundling instead of insn scheduling. */
125 int bundling_p = 0;
126
127 enum ia64_frame_regs
128 {
129 reg_fp,
130 reg_save_b0,
131 reg_save_pr,
132 reg_save_ar_pfs,
133 reg_save_ar_unat,
134 reg_save_ar_lc,
135 reg_save_gp,
136 number_of_ia64_frame_regs
137 };
138
139 /* Structure to be filled in by ia64_compute_frame_size with register
140 save masks and offsets for the current function. */
141
142 struct ia64_frame_info
143 {
144 HOST_WIDE_INT total_size; /* size of the stack frame, not including
145 the caller's scratch area. */
146 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
147 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
148 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
149 HARD_REG_SET mask; /* mask of saved registers. */
150 unsigned int gr_used_mask; /* mask of registers in use as gr spill
151 registers or long-term scratches. */
152 int n_spilled; /* number of spilled registers. */
153 int r[number_of_ia64_frame_regs]; /* Frame related registers. */
154 int n_input_regs; /* number of input registers used. */
155 int n_local_regs; /* number of local registers used. */
156 int n_output_regs; /* number of output registers used. */
157 int n_rotate_regs; /* number of rotating registers used. */
158
159 char need_regstk; /* true if a .regstk directive needed. */
160 char initialized; /* true if the data is finalized. */
161 };
162
163 /* Current frame information calculated by ia64_compute_frame_size. */
164 static struct ia64_frame_info current_frame_info;
165 /* The actual registers that are emitted. */
166 static int emitted_frame_related_regs[number_of_ia64_frame_regs];
167 \f
168 static int ia64_first_cycle_multipass_dfa_lookahead (void);
169 static void ia64_dependencies_evaluation_hook (rtx_insn *, rtx_insn *);
170 static void ia64_init_dfa_pre_cycle_insn (void);
171 static rtx ia64_dfa_pre_cycle_insn (void);
172 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx_insn *, int);
173 static int ia64_dfa_new_cycle (FILE *, int, rtx_insn *, int, int, int *);
174 static void ia64_h_i_d_extended (void);
175 static void * ia64_alloc_sched_context (void);
176 static void ia64_init_sched_context (void *, bool);
177 static void ia64_set_sched_context (void *);
178 static void ia64_clear_sched_context (void *);
179 static void ia64_free_sched_context (void *);
180 static int ia64_mode_to_int (enum machine_mode);
181 static void ia64_set_sched_flags (spec_info_t);
182 static ds_t ia64_get_insn_spec_ds (rtx_insn *);
183 static ds_t ia64_get_insn_checked_ds (rtx_insn *);
184 static bool ia64_skip_rtx_p (const_rtx);
185 static int ia64_speculate_insn (rtx_insn *, ds_t, rtx *);
186 static bool ia64_needs_block_p (ds_t);
187 static rtx ia64_gen_spec_check (rtx_insn *, rtx_insn *, ds_t);
188 static int ia64_spec_check_p (rtx);
189 static int ia64_spec_check_src_p (rtx);
190 static rtx gen_tls_get_addr (void);
191 static rtx gen_thread_pointer (void);
192 static int find_gr_spill (enum ia64_frame_regs, int);
193 static int next_scratch_gr_reg (void);
194 static void mark_reg_gr_used_mask (rtx, void *);
195 static void ia64_compute_frame_size (HOST_WIDE_INT);
196 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
197 static void finish_spill_pointers (void);
198 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
199 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
200 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
201 static rtx gen_movdi_x (rtx, rtx, rtx);
202 static rtx gen_fr_spill_x (rtx, rtx, rtx);
203 static rtx gen_fr_restore_x (rtx, rtx, rtx);
204
205 static void ia64_option_override (void);
206 static bool ia64_can_eliminate (const int, const int);
207 static enum machine_mode hfa_element_mode (const_tree, bool);
208 static void ia64_setup_incoming_varargs (cumulative_args_t, enum machine_mode,
209 tree, int *, int);
210 static int ia64_arg_partial_bytes (cumulative_args_t, enum machine_mode,
211 tree, bool);
212 static rtx ia64_function_arg_1 (cumulative_args_t, enum machine_mode,
213 const_tree, bool, bool);
214 static rtx ia64_function_arg (cumulative_args_t, enum machine_mode,
215 const_tree, bool);
216 static rtx ia64_function_incoming_arg (cumulative_args_t,
217 enum machine_mode, const_tree, bool);
218 static void ia64_function_arg_advance (cumulative_args_t, enum machine_mode,
219 const_tree, bool);
220 static unsigned int ia64_function_arg_boundary (enum machine_mode,
221 const_tree);
222 static bool ia64_function_ok_for_sibcall (tree, tree);
223 static bool ia64_return_in_memory (const_tree, const_tree);
224 static rtx ia64_function_value (const_tree, const_tree, bool);
225 static rtx ia64_libcall_value (enum machine_mode, const_rtx);
226 static bool ia64_function_value_regno_p (const unsigned int);
227 static int ia64_register_move_cost (enum machine_mode, reg_class_t,
228 reg_class_t);
229 static int ia64_memory_move_cost (enum machine_mode mode, reg_class_t,
230 bool);
231 static bool ia64_rtx_costs (rtx, int, int, int, int *, bool);
232 static int ia64_unspec_may_trap_p (const_rtx, unsigned);
233 static void fix_range (const char *);
234 static struct machine_function * ia64_init_machine_status (void);
235 static void emit_insn_group_barriers (FILE *);
236 static void emit_all_insn_group_barriers (FILE *);
237 static void final_emit_insn_group_barriers (FILE *);
238 static void emit_predicate_relation_info (void);
239 static void ia64_reorg (void);
240 static bool ia64_in_small_data_p (const_tree);
241 static void process_epilogue (FILE *, rtx, bool, bool);
242
243 static bool ia64_assemble_integer (rtx, unsigned int, int);
244 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
245 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
246 static void ia64_output_function_end_prologue (FILE *);
247
248 static void ia64_print_operand (FILE *, rtx, int);
249 static void ia64_print_operand_address (FILE *, rtx);
250 static bool ia64_print_operand_punct_valid_p (unsigned char code);
251
252 static int ia64_issue_rate (void);
253 static int ia64_adjust_cost_2 (rtx_insn *, int, rtx_insn *, int, dw_t);
254 static void ia64_sched_init (FILE *, int, int);
255 static void ia64_sched_init_global (FILE *, int, int);
256 static void ia64_sched_finish_global (FILE *, int);
257 static void ia64_sched_finish (FILE *, int);
258 static int ia64_dfa_sched_reorder (FILE *, int, rtx_insn **, int *, int, int);
259 static int ia64_sched_reorder (FILE *, int, rtx_insn **, int *, int);
260 static int ia64_sched_reorder2 (FILE *, int, rtx_insn **, int *, int);
261 static int ia64_variable_issue (FILE *, int, rtx_insn *, int);
262
263 static void ia64_asm_unwind_emit (FILE *, rtx_insn *);
264 static void ia64_asm_emit_except_personality (rtx);
265 static void ia64_asm_init_sections (void);
266
267 static enum unwind_info_type ia64_debug_unwind_info (void);
268
269 static struct bundle_state *get_free_bundle_state (void);
270 static void free_bundle_state (struct bundle_state *);
271 static void initiate_bundle_states (void);
272 static void finish_bundle_states (void);
273 static int insert_bundle_state (struct bundle_state *);
274 static void initiate_bundle_state_table (void);
275 static void finish_bundle_state_table (void);
276 static int try_issue_nops (struct bundle_state *, int);
277 static int try_issue_insn (struct bundle_state *, rtx);
278 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
279 static int get_max_pos (state_t);
280 static int get_template (state_t, int);
281
282 static rtx get_next_important_insn (rtx, rtx);
283 static bool important_for_bundling_p (rtx);
284 static bool unknown_for_bundling_p (rtx);
285 static void bundling (FILE *, int, rtx, rtx);
286
287 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
288 HOST_WIDE_INT, tree);
289 static void ia64_file_start (void);
290 static void ia64_globalize_decl_name (FILE *, tree);
291
292 static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
293 static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
294 static section *ia64_select_rtx_section (enum machine_mode, rtx,
295 unsigned HOST_WIDE_INT);
296 static void ia64_output_dwarf_dtprel (FILE *, int, rtx)
297 ATTRIBUTE_UNUSED;
298 static unsigned int ia64_section_type_flags (tree, const char *, int);
299 static void ia64_init_libfuncs (void)
300 ATTRIBUTE_UNUSED;
301 static void ia64_hpux_init_libfuncs (void)
302 ATTRIBUTE_UNUSED;
303 static void ia64_sysv4_init_libfuncs (void)
304 ATTRIBUTE_UNUSED;
305 static void ia64_vms_init_libfuncs (void)
306 ATTRIBUTE_UNUSED;
307 static void ia64_soft_fp_init_libfuncs (void)
308 ATTRIBUTE_UNUSED;
309 static bool ia64_vms_valid_pointer_mode (enum machine_mode mode)
310 ATTRIBUTE_UNUSED;
311 static tree ia64_vms_common_object_attribute (tree *, tree, tree, int, bool *)
312 ATTRIBUTE_UNUSED;
313
314 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
315 static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *);
316 static void ia64_encode_section_info (tree, rtx, int);
317 static rtx ia64_struct_value_rtx (tree, int);
318 static tree ia64_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
319 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
320 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
321 static bool ia64_legitimate_constant_p (enum machine_mode, rtx);
322 static bool ia64_legitimate_address_p (enum machine_mode, rtx, bool);
323 static bool ia64_cannot_force_const_mem (enum machine_mode, rtx);
324 static const char *ia64_mangle_type (const_tree);
325 static const char *ia64_invalid_conversion (const_tree, const_tree);
326 static const char *ia64_invalid_unary_op (int, const_tree);
327 static const char *ia64_invalid_binary_op (int, const_tree, const_tree);
328 static enum machine_mode ia64_c_mode_for_suffix (char);
329 static void ia64_trampoline_init (rtx, tree, rtx);
330 static void ia64_override_options_after_change (void);
331 static bool ia64_member_type_forces_blk (const_tree, enum machine_mode);
332
333 static tree ia64_builtin_decl (unsigned, bool);
334
335 static reg_class_t ia64_preferred_reload_class (rtx, reg_class_t);
336 static enum machine_mode ia64_get_reg_raw_mode (int regno);
337 static section * ia64_hpux_function_section (tree, enum node_frequency,
338 bool, bool);
339
340 static bool ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
341 const unsigned char *sel);
342
343 #define MAX_VECT_LEN 8
344
345 struct expand_vec_perm_d
346 {
347 rtx target, op0, op1;
348 unsigned char perm[MAX_VECT_LEN];
349 enum machine_mode vmode;
350 unsigned char nelt;
351 bool one_operand_p;
352 bool testing_p;
353 };
354
355 static bool ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d);
356
357 \f
358 /* Table of valid machine attributes. */
359 static const struct attribute_spec ia64_attribute_table[] =
360 {
361 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
362 affects_type_identity } */
363 { "syscall_linkage", 0, 0, false, true, true, NULL, false },
364 { "model", 1, 1, true, false, false, ia64_handle_model_attribute,
365 false },
366 #if TARGET_ABI_OPEN_VMS
367 { "common_object", 1, 1, true, false, false,
368 ia64_vms_common_object_attribute, false },
369 #endif
370 { "version_id", 1, 1, true, false, false,
371 ia64_handle_version_id_attribute, false },
372 { NULL, 0, 0, false, false, false, NULL, false }
373 };
374
375 /* Initialize the GCC target structure. */
376 #undef TARGET_ATTRIBUTE_TABLE
377 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
378
379 #undef TARGET_INIT_BUILTINS
380 #define TARGET_INIT_BUILTINS ia64_init_builtins
381
382 #undef TARGET_EXPAND_BUILTIN
383 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
384
385 #undef TARGET_BUILTIN_DECL
386 #define TARGET_BUILTIN_DECL ia64_builtin_decl
387
388 #undef TARGET_ASM_BYTE_OP
389 #define TARGET_ASM_BYTE_OP "\tdata1\t"
390 #undef TARGET_ASM_ALIGNED_HI_OP
391 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
392 #undef TARGET_ASM_ALIGNED_SI_OP
393 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
394 #undef TARGET_ASM_ALIGNED_DI_OP
395 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
396 #undef TARGET_ASM_UNALIGNED_HI_OP
397 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
398 #undef TARGET_ASM_UNALIGNED_SI_OP
399 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
400 #undef TARGET_ASM_UNALIGNED_DI_OP
401 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
402 #undef TARGET_ASM_INTEGER
403 #define TARGET_ASM_INTEGER ia64_assemble_integer
404
405 #undef TARGET_OPTION_OVERRIDE
406 #define TARGET_OPTION_OVERRIDE ia64_option_override
407
408 #undef TARGET_ASM_FUNCTION_PROLOGUE
409 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
410 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
411 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
412 #undef TARGET_ASM_FUNCTION_EPILOGUE
413 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
414
415 #undef TARGET_PRINT_OPERAND
416 #define TARGET_PRINT_OPERAND ia64_print_operand
417 #undef TARGET_PRINT_OPERAND_ADDRESS
418 #define TARGET_PRINT_OPERAND_ADDRESS ia64_print_operand_address
419 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
420 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ia64_print_operand_punct_valid_p
421
422 #undef TARGET_IN_SMALL_DATA_P
423 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
424
425 #undef TARGET_SCHED_ADJUST_COST_2
426 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
427 #undef TARGET_SCHED_ISSUE_RATE
428 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
429 #undef TARGET_SCHED_VARIABLE_ISSUE
430 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
431 #undef TARGET_SCHED_INIT
432 #define TARGET_SCHED_INIT ia64_sched_init
433 #undef TARGET_SCHED_FINISH
434 #define TARGET_SCHED_FINISH ia64_sched_finish
435 #undef TARGET_SCHED_INIT_GLOBAL
436 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
437 #undef TARGET_SCHED_FINISH_GLOBAL
438 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
439 #undef TARGET_SCHED_REORDER
440 #define TARGET_SCHED_REORDER ia64_sched_reorder
441 #undef TARGET_SCHED_REORDER2
442 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
443
444 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
445 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
446
447 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
448 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
449
450 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
451 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
452 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
453 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
454
455 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
456 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
457 ia64_first_cycle_multipass_dfa_lookahead_guard
458
459 #undef TARGET_SCHED_DFA_NEW_CYCLE
460 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
461
462 #undef TARGET_SCHED_H_I_D_EXTENDED
463 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
464
465 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
466 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context
467
468 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
469 #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context
470
471 #undef TARGET_SCHED_SET_SCHED_CONTEXT
472 #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context
473
474 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
475 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context
476
477 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
478 #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context
479
480 #undef TARGET_SCHED_SET_SCHED_FLAGS
481 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
482
483 #undef TARGET_SCHED_GET_INSN_SPEC_DS
484 #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds
485
486 #undef TARGET_SCHED_GET_INSN_CHECKED_DS
487 #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds
488
489 #undef TARGET_SCHED_SPECULATE_INSN
490 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
491
492 #undef TARGET_SCHED_NEEDS_BLOCK_P
493 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
494
495 #undef TARGET_SCHED_GEN_SPEC_CHECK
496 #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
497
498 #undef TARGET_SCHED_SKIP_RTX_P
499 #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
500
501 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
502 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
503 #undef TARGET_ARG_PARTIAL_BYTES
504 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
505 #undef TARGET_FUNCTION_ARG
506 #define TARGET_FUNCTION_ARG ia64_function_arg
507 #undef TARGET_FUNCTION_INCOMING_ARG
508 #define TARGET_FUNCTION_INCOMING_ARG ia64_function_incoming_arg
509 #undef TARGET_FUNCTION_ARG_ADVANCE
510 #define TARGET_FUNCTION_ARG_ADVANCE ia64_function_arg_advance
511 #undef TARGET_FUNCTION_ARG_BOUNDARY
512 #define TARGET_FUNCTION_ARG_BOUNDARY ia64_function_arg_boundary
513
514 #undef TARGET_ASM_OUTPUT_MI_THUNK
515 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
516 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
517 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
518
519 #undef TARGET_ASM_FILE_START
520 #define TARGET_ASM_FILE_START ia64_file_start
521
522 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
523 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
524
525 #undef TARGET_REGISTER_MOVE_COST
526 #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost
527 #undef TARGET_MEMORY_MOVE_COST
528 #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost
529 #undef TARGET_RTX_COSTS
530 #define TARGET_RTX_COSTS ia64_rtx_costs
531 #undef TARGET_ADDRESS_COST
532 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
533
534 #undef TARGET_UNSPEC_MAY_TRAP_P
535 #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
536
537 #undef TARGET_MACHINE_DEPENDENT_REORG
538 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
539
540 #undef TARGET_ENCODE_SECTION_INFO
541 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
542
543 #undef TARGET_SECTION_TYPE_FLAGS
544 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
545
546 #ifdef HAVE_AS_TLS
547 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
548 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
549 #endif
550
551 /* ??? Investigate. */
552 #if 0
553 #undef TARGET_PROMOTE_PROTOTYPES
554 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
555 #endif
556
557 #undef TARGET_FUNCTION_VALUE
558 #define TARGET_FUNCTION_VALUE ia64_function_value
559 #undef TARGET_LIBCALL_VALUE
560 #define TARGET_LIBCALL_VALUE ia64_libcall_value
561 #undef TARGET_FUNCTION_VALUE_REGNO_P
562 #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p
563
564 #undef TARGET_STRUCT_VALUE_RTX
565 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
566 #undef TARGET_RETURN_IN_MEMORY
567 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
568 #undef TARGET_SETUP_INCOMING_VARARGS
569 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
570 #undef TARGET_STRICT_ARGUMENT_NAMING
571 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
572 #undef TARGET_MUST_PASS_IN_STACK
573 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
574 #undef TARGET_GET_RAW_RESULT_MODE
575 #define TARGET_GET_RAW_RESULT_MODE ia64_get_reg_raw_mode
576 #undef TARGET_GET_RAW_ARG_MODE
577 #define TARGET_GET_RAW_ARG_MODE ia64_get_reg_raw_mode
578
579 #undef TARGET_MEMBER_TYPE_FORCES_BLK
580 #define TARGET_MEMBER_TYPE_FORCES_BLK ia64_member_type_forces_blk
581
582 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
583 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
584
585 #undef TARGET_ASM_UNWIND_EMIT
586 #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit
587 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
588 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality
589 #undef TARGET_ASM_INIT_SECTIONS
590 #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections
591
592 #undef TARGET_DEBUG_UNWIND_INFO
593 #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info
594
595 #undef TARGET_SCALAR_MODE_SUPPORTED_P
596 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
597 #undef TARGET_VECTOR_MODE_SUPPORTED_P
598 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
599
600 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
601 in an order different from the specified program order. */
602 #undef TARGET_RELAXED_ORDERING
603 #define TARGET_RELAXED_ORDERING true
604
605 #undef TARGET_LEGITIMATE_CONSTANT_P
606 #define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p
607 #undef TARGET_LEGITIMATE_ADDRESS_P
608 #define TARGET_LEGITIMATE_ADDRESS_P ia64_legitimate_address_p
609
610 #undef TARGET_CANNOT_FORCE_CONST_MEM
611 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
612
613 #undef TARGET_MANGLE_TYPE
614 #define TARGET_MANGLE_TYPE ia64_mangle_type
615
616 #undef TARGET_INVALID_CONVERSION
617 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
618 #undef TARGET_INVALID_UNARY_OP
619 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
620 #undef TARGET_INVALID_BINARY_OP
621 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
622
623 #undef TARGET_C_MODE_FOR_SUFFIX
624 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
625
626 #undef TARGET_CAN_ELIMINATE
627 #define TARGET_CAN_ELIMINATE ia64_can_eliminate
628
629 #undef TARGET_TRAMPOLINE_INIT
630 #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init
631
632 #undef TARGET_CAN_USE_DOLOOP_P
633 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
634 #undef TARGET_INVALID_WITHIN_DOLOOP
635 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
636
637 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
638 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change
639
640 #undef TARGET_PREFERRED_RELOAD_CLASS
641 #define TARGET_PREFERRED_RELOAD_CLASS ia64_preferred_reload_class
642
643 #undef TARGET_DELAY_SCHED2
644 #define TARGET_DELAY_SCHED2 true
645
646 /* Variable tracking should be run after all optimizations which
647 change order of insns. It also needs a valid CFG. */
648 #undef TARGET_DELAY_VARTRACK
649 #define TARGET_DELAY_VARTRACK true
650
651 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
652 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK ia64_vectorize_vec_perm_const_ok
653
654 struct gcc_target targetm = TARGET_INITIALIZER;
655 \f
656 typedef enum
657 {
658 ADDR_AREA_NORMAL, /* normal address area */
659 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
660 }
661 ia64_addr_area;
662
663 static GTY(()) tree small_ident1;
664 static GTY(()) tree small_ident2;
665
666 static void
667 init_idents (void)
668 {
669 if (small_ident1 == 0)
670 {
671 small_ident1 = get_identifier ("small");
672 small_ident2 = get_identifier ("__small__");
673 }
674 }
675
676 /* Retrieve the address area that has been chosen for the given decl. */
677
678 static ia64_addr_area
679 ia64_get_addr_area (tree decl)
680 {
681 tree model_attr;
682
683 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
684 if (model_attr)
685 {
686 tree id;
687
688 init_idents ();
689 id = TREE_VALUE (TREE_VALUE (model_attr));
690 if (id == small_ident1 || id == small_ident2)
691 return ADDR_AREA_SMALL;
692 }
693 return ADDR_AREA_NORMAL;
694 }
695
696 static tree
697 ia64_handle_model_attribute (tree *node, tree name, tree args,
698 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
699 {
700 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
701 ia64_addr_area area;
702 tree arg, decl = *node;
703
704 init_idents ();
705 arg = TREE_VALUE (args);
706 if (arg == small_ident1 || arg == small_ident2)
707 {
708 addr_area = ADDR_AREA_SMALL;
709 }
710 else
711 {
712 warning (OPT_Wattributes, "invalid argument of %qE attribute",
713 name);
714 *no_add_attrs = true;
715 }
716
717 switch (TREE_CODE (decl))
718 {
719 case VAR_DECL:
720 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
721 == FUNCTION_DECL)
722 && !TREE_STATIC (decl))
723 {
724 error_at (DECL_SOURCE_LOCATION (decl),
725 "an address area attribute cannot be specified for "
726 "local variables");
727 *no_add_attrs = true;
728 }
729 area = ia64_get_addr_area (decl);
730 if (area != ADDR_AREA_NORMAL && addr_area != area)
731 {
732 error ("address area of %q+D conflicts with previous "
733 "declaration", decl);
734 *no_add_attrs = true;
735 }
736 break;
737
738 case FUNCTION_DECL:
739 error_at (DECL_SOURCE_LOCATION (decl),
740 "address area attribute cannot be specified for "
741 "functions");
742 *no_add_attrs = true;
743 break;
744
745 default:
746 warning (OPT_Wattributes, "%qE attribute ignored",
747 name);
748 *no_add_attrs = true;
749 break;
750 }
751
752 return NULL_TREE;
753 }
754
755 /* Part of the low level implementation of DEC Ada pragma Common_Object which
756 enables the shared use of variables stored in overlaid linker areas
757 corresponding to the use of Fortran COMMON. */
758
759 static tree
760 ia64_vms_common_object_attribute (tree *node, tree name, tree args,
761 int flags ATTRIBUTE_UNUSED,
762 bool *no_add_attrs)
763 {
764 tree decl = *node;
765 tree id;
766
767 gcc_assert (DECL_P (decl));
768
769 DECL_COMMON (decl) = 1;
770 id = TREE_VALUE (args);
771 if (TREE_CODE (id) != IDENTIFIER_NODE && TREE_CODE (id) != STRING_CST)
772 {
773 error ("%qE attribute requires a string constant argument", name);
774 *no_add_attrs = true;
775 return NULL_TREE;
776 }
777 return NULL_TREE;
778 }
779
780 /* Part of the low level implementation of DEC Ada pragma Common_Object. */
781
782 void
783 ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name,
784 unsigned HOST_WIDE_INT size,
785 unsigned int align)
786 {
787 tree attr = DECL_ATTRIBUTES (decl);
788
789 if (attr)
790 attr = lookup_attribute ("common_object", attr);
791 if (attr)
792 {
793 tree id = TREE_VALUE (TREE_VALUE (attr));
794 const char *name;
795
796 if (TREE_CODE (id) == IDENTIFIER_NODE)
797 name = IDENTIFIER_POINTER (id);
798 else if (TREE_CODE (id) == STRING_CST)
799 name = TREE_STRING_POINTER (id);
800 else
801 abort ();
802
803 fprintf (file, "\t.vms_common\t\"%s\",", name);
804 }
805 else
806 fprintf (file, "%s", COMMON_ASM_OP);
807
808 /* Code from elfos.h. */
809 assemble_name (file, name);
810 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u",
811 size, align / BITS_PER_UNIT);
812
813 fputc ('\n', file);
814 }
815
816 static void
817 ia64_encode_addr_area (tree decl, rtx symbol)
818 {
819 int flags;
820
821 flags = SYMBOL_REF_FLAGS (symbol);
822 switch (ia64_get_addr_area (decl))
823 {
824 case ADDR_AREA_NORMAL: break;
825 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
826 default: gcc_unreachable ();
827 }
828 SYMBOL_REF_FLAGS (symbol) = flags;
829 }
830
831 static void
832 ia64_encode_section_info (tree decl, rtx rtl, int first)
833 {
834 default_encode_section_info (decl, rtl, first);
835
836 /* Careful not to prod global register variables. */
837 if (TREE_CODE (decl) == VAR_DECL
838 && GET_CODE (DECL_RTL (decl)) == MEM
839 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
840 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
841 ia64_encode_addr_area (decl, XEXP (rtl, 0));
842 }
843 \f
844 /* Return 1 if the operands of a move are ok. */
845
846 int
847 ia64_move_ok (rtx dst, rtx src)
848 {
849 /* If we're under init_recog_no_volatile, we'll not be able to use
850 memory_operand. So check the code directly and don't worry about
851 the validity of the underlying address, which should have been
852 checked elsewhere anyway. */
853 if (GET_CODE (dst) != MEM)
854 return 1;
855 if (GET_CODE (src) == MEM)
856 return 0;
857 if (register_operand (src, VOIDmode))
858 return 1;
859
860 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
861 if (INTEGRAL_MODE_P (GET_MODE (dst)))
862 return src == const0_rtx;
863 else
864 return satisfies_constraint_G (src);
865 }
866
867 /* Return 1 if the operands are ok for a floating point load pair. */
868
869 int
870 ia64_load_pair_ok (rtx dst, rtx src)
871 {
872 /* ??? There is a thinko in the implementation of the "x" constraint and the
873 FP_REGS class. The constraint will also reject (reg f30:TI) so we must
874 also return false for it. */
875 if (GET_CODE (dst) != REG
876 || !(FP_REGNO_P (REGNO (dst)) && FP_REGNO_P (REGNO (dst) + 1)))
877 return 0;
878 if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
879 return 0;
880 switch (GET_CODE (XEXP (src, 0)))
881 {
882 case REG:
883 case POST_INC:
884 break;
885 case POST_DEC:
886 return 0;
887 case POST_MODIFY:
888 {
889 rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
890
891 if (GET_CODE (adjust) != CONST_INT
892 || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
893 return 0;
894 }
895 break;
896 default:
897 abort ();
898 }
899 return 1;
900 }
901
902 int
903 addp4_optimize_ok (rtx op1, rtx op2)
904 {
905 return (basereg_operand (op1, GET_MODE(op1)) !=
906 basereg_operand (op2, GET_MODE(op2)));
907 }
908
909 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
910 Return the length of the field, or <= 0 on failure. */
911
912 int
913 ia64_depz_field_mask (rtx rop, rtx rshift)
914 {
915 unsigned HOST_WIDE_INT op = INTVAL (rop);
916 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
917
918 /* Get rid of the zero bits we're shifting in. */
919 op >>= shift;
920
921 /* We must now have a solid block of 1's at bit 0. */
922 return exact_log2 (op + 1);
923 }
924
925 /* Return the TLS model to use for ADDR. */
926
927 static enum tls_model
928 tls_symbolic_operand_type (rtx addr)
929 {
930 enum tls_model tls_kind = TLS_MODEL_NONE;
931
932 if (GET_CODE (addr) == CONST)
933 {
934 if (GET_CODE (XEXP (addr, 0)) == PLUS
935 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
936 tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
937 }
938 else if (GET_CODE (addr) == SYMBOL_REF)
939 tls_kind = SYMBOL_REF_TLS_MODEL (addr);
940
941 return tls_kind;
942 }
943
944 /* Returns true if REG (assumed to be a `reg' RTX) is valid for use
945 as a base register. */
946
947 static inline bool
948 ia64_reg_ok_for_base_p (const_rtx reg, bool strict)
949 {
950 if (strict
951 && REGNO_OK_FOR_BASE_P (REGNO (reg)))
952 return true;
953 else if (!strict
954 && (GENERAL_REGNO_P (REGNO (reg))
955 || !HARD_REGISTER_P (reg)))
956 return true;
957 else
958 return false;
959 }
960
961 static bool
962 ia64_legitimate_address_reg (const_rtx reg, bool strict)
963 {
964 if ((REG_P (reg) && ia64_reg_ok_for_base_p (reg, strict))
965 || (GET_CODE (reg) == SUBREG && REG_P (XEXP (reg, 0))
966 && ia64_reg_ok_for_base_p (XEXP (reg, 0), strict)))
967 return true;
968
969 return false;
970 }
971
972 static bool
973 ia64_legitimate_address_disp (const_rtx reg, const_rtx disp, bool strict)
974 {
975 if (GET_CODE (disp) == PLUS
976 && rtx_equal_p (reg, XEXP (disp, 0))
977 && (ia64_legitimate_address_reg (XEXP (disp, 1), strict)
978 || (CONST_INT_P (XEXP (disp, 1))
979 && IN_RANGE (INTVAL (XEXP (disp, 1)), -256, 255))))
980 return true;
981
982 return false;
983 }
984
985 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
986
987 static bool
988 ia64_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
989 rtx x, bool strict)
990 {
991 if (ia64_legitimate_address_reg (x, strict))
992 return true;
993 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC)
994 && ia64_legitimate_address_reg (XEXP (x, 0), strict)
995 && XEXP (x, 0) != arg_pointer_rtx)
996 return true;
997 else if (GET_CODE (x) == POST_MODIFY
998 && ia64_legitimate_address_reg (XEXP (x, 0), strict)
999 && XEXP (x, 0) != arg_pointer_rtx
1000 && ia64_legitimate_address_disp (XEXP (x, 0), XEXP (x, 1), strict))
1001 return true;
1002 else
1003 return false;
1004 }
1005
1006 /* Return true if X is a constant that is valid for some immediate
1007 field in an instruction. */
1008
1009 static bool
1010 ia64_legitimate_constant_p (enum machine_mode mode, rtx x)
1011 {
1012 switch (GET_CODE (x))
1013 {
1014 case CONST_INT:
1015 case LABEL_REF:
1016 return true;
1017
1018 case CONST_DOUBLE:
1019 if (GET_MODE (x) == VOIDmode || mode == SFmode || mode == DFmode)
1020 return true;
1021 return satisfies_constraint_G (x);
1022
1023 case CONST:
1024 case SYMBOL_REF:
1025 /* ??? Short term workaround for PR 28490. We must make the code here
1026 match the code in ia64_expand_move and move_operand, even though they
1027 are both technically wrong. */
1028 if (tls_symbolic_operand_type (x) == 0)
1029 {
1030 HOST_WIDE_INT addend = 0;
1031 rtx op = x;
1032
1033 if (GET_CODE (op) == CONST
1034 && GET_CODE (XEXP (op, 0)) == PLUS
1035 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
1036 {
1037 addend = INTVAL (XEXP (XEXP (op, 0), 1));
1038 op = XEXP (XEXP (op, 0), 0);
1039 }
1040
1041 if (any_offset_symbol_operand (op, mode)
1042 || function_operand (op, mode))
1043 return true;
1044 if (aligned_offset_symbol_operand (op, mode))
1045 return (addend & 0x3fff) == 0;
1046 return false;
1047 }
1048 return false;
1049
1050 case CONST_VECTOR:
1051 if (mode == V2SFmode)
1052 return satisfies_constraint_Y (x);
1053
1054 return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
1055 && GET_MODE_SIZE (mode) <= 8);
1056
1057 default:
1058 return false;
1059 }
1060 }
1061
1062 /* Don't allow TLS addresses to get spilled to memory. */
1063
1064 static bool
1065 ia64_cannot_force_const_mem (enum machine_mode mode, rtx x)
1066 {
1067 if (mode == RFmode)
1068 return true;
1069 return tls_symbolic_operand_type (x) != 0;
1070 }
1071
1072 /* Expand a symbolic constant load. */
1073
1074 bool
1075 ia64_expand_load_address (rtx dest, rtx src)
1076 {
1077 gcc_assert (GET_CODE (dest) == REG);
1078
1079 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1080 having to pointer-extend the value afterward. Other forms of address
1081 computation below are also more natural to compute as 64-bit quantities.
1082 If we've been given an SImode destination register, change it. */
1083 if (GET_MODE (dest) != Pmode)
1084 dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest),
1085 byte_lowpart_offset (Pmode, GET_MODE (dest)));
1086
1087 if (TARGET_NO_PIC)
1088 return false;
1089 if (small_addr_symbolic_operand (src, VOIDmode))
1090 return false;
1091
1092 if (TARGET_AUTO_PIC)
1093 emit_insn (gen_load_gprel64 (dest, src));
1094 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
1095 emit_insn (gen_load_fptr (dest, src));
1096 else if (sdata_symbolic_operand (src, VOIDmode))
1097 emit_insn (gen_load_gprel (dest, src));
1098 else
1099 {
1100 HOST_WIDE_INT addend = 0;
1101 rtx tmp;
1102
1103 /* We did split constant offsets in ia64_expand_move, and we did try
1104 to keep them split in move_operand, but we also allowed reload to
1105 rematerialize arbitrary constants rather than spill the value to
1106 the stack and reload it. So we have to be prepared here to split
1107 them apart again. */
1108 if (GET_CODE (src) == CONST)
1109 {
1110 HOST_WIDE_INT hi, lo;
1111
1112 hi = INTVAL (XEXP (XEXP (src, 0), 1));
1113 lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000;
1114 hi = hi - lo;
1115
1116 if (lo != 0)
1117 {
1118 addend = lo;
1119 src = plus_constant (Pmode, XEXP (XEXP (src, 0), 0), hi);
1120 }
1121 }
1122
1123 tmp = gen_rtx_HIGH (Pmode, src);
1124 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
1125 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1126
1127 tmp = gen_rtx_LO_SUM (Pmode, gen_const_mem (Pmode, dest), src);
1128 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1129
1130 if (addend)
1131 {
1132 tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend));
1133 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1134 }
1135 }
1136
1137 return true;
1138 }
1139
1140 static GTY(()) rtx gen_tls_tga;
1141 static rtx
1142 gen_tls_get_addr (void)
1143 {
1144 if (!gen_tls_tga)
1145 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
1146 return gen_tls_tga;
1147 }
1148
1149 static GTY(()) rtx thread_pointer_rtx;
1150 static rtx
1151 gen_thread_pointer (void)
1152 {
1153 if (!thread_pointer_rtx)
1154 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
1155 return thread_pointer_rtx;
1156 }
1157
1158 static rtx
1159 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1,
1160 rtx orig_op1, HOST_WIDE_INT addend)
1161 {
1162 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp;
1163 rtx_insn *insns;
1164 rtx orig_op0 = op0;
1165 HOST_WIDE_INT addend_lo, addend_hi;
1166
1167 switch (tls_kind)
1168 {
1169 case TLS_MODEL_GLOBAL_DYNAMIC:
1170 start_sequence ();
1171
1172 tga_op1 = gen_reg_rtx (Pmode);
1173 emit_insn (gen_load_dtpmod (tga_op1, op1));
1174
1175 tga_op2 = gen_reg_rtx (Pmode);
1176 emit_insn (gen_load_dtprel (tga_op2, op1));
1177
1178 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1179 LCT_CONST, Pmode, 2, tga_op1,
1180 Pmode, tga_op2, Pmode);
1181
1182 insns = get_insns ();
1183 end_sequence ();
1184
1185 if (GET_MODE (op0) != Pmode)
1186 op0 = tga_ret;
1187 emit_libcall_block (insns, op0, tga_ret, op1);
1188 break;
1189
1190 case TLS_MODEL_LOCAL_DYNAMIC:
1191 /* ??? This isn't the completely proper way to do local-dynamic
1192 If the call to __tls_get_addr is used only by a single symbol,
1193 then we should (somehow) move the dtprel to the second arg
1194 to avoid the extra add. */
1195 start_sequence ();
1196
1197 tga_op1 = gen_reg_rtx (Pmode);
1198 emit_insn (gen_load_dtpmod (tga_op1, op1));
1199
1200 tga_op2 = const0_rtx;
1201
1202 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1203 LCT_CONST, Pmode, 2, tga_op1,
1204 Pmode, tga_op2, Pmode);
1205
1206 insns = get_insns ();
1207 end_sequence ();
1208
1209 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1210 UNSPEC_LD_BASE);
1211 tmp = gen_reg_rtx (Pmode);
1212 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1213
1214 if (!register_operand (op0, Pmode))
1215 op0 = gen_reg_rtx (Pmode);
1216 if (TARGET_TLS64)
1217 {
1218 emit_insn (gen_load_dtprel (op0, op1));
1219 emit_insn (gen_adddi3 (op0, tmp, op0));
1220 }
1221 else
1222 emit_insn (gen_add_dtprel (op0, op1, tmp));
1223 break;
1224
1225 case TLS_MODEL_INITIAL_EXEC:
1226 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1227 addend_hi = addend - addend_lo;
1228
1229 op1 = plus_constant (Pmode, op1, addend_hi);
1230 addend = addend_lo;
1231
1232 tmp = gen_reg_rtx (Pmode);
1233 emit_insn (gen_load_tprel (tmp, op1));
1234
1235 if (!register_operand (op0, Pmode))
1236 op0 = gen_reg_rtx (Pmode);
1237 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
1238 break;
1239
1240 case TLS_MODEL_LOCAL_EXEC:
1241 if (!register_operand (op0, Pmode))
1242 op0 = gen_reg_rtx (Pmode);
1243
1244 op1 = orig_op1;
1245 addend = 0;
1246 if (TARGET_TLS64)
1247 {
1248 emit_insn (gen_load_tprel (op0, op1));
1249 emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ()));
1250 }
1251 else
1252 emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ()));
1253 break;
1254
1255 default:
1256 gcc_unreachable ();
1257 }
1258
1259 if (addend)
1260 op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend),
1261 orig_op0, 1, OPTAB_DIRECT);
1262 if (orig_op0 == op0)
1263 return NULL_RTX;
1264 if (GET_MODE (orig_op0) == Pmode)
1265 return op0;
1266 return gen_lowpart (GET_MODE (orig_op0), op0);
1267 }
1268
1269 rtx
1270 ia64_expand_move (rtx op0, rtx op1)
1271 {
1272 enum machine_mode mode = GET_MODE (op0);
1273
1274 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1275 op1 = force_reg (mode, op1);
1276
1277 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1278 {
1279 HOST_WIDE_INT addend = 0;
1280 enum tls_model tls_kind;
1281 rtx sym = op1;
1282
1283 if (GET_CODE (op1) == CONST
1284 && GET_CODE (XEXP (op1, 0)) == PLUS
1285 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
1286 {
1287 addend = INTVAL (XEXP (XEXP (op1, 0), 1));
1288 sym = XEXP (XEXP (op1, 0), 0);
1289 }
1290
1291 tls_kind = tls_symbolic_operand_type (sym);
1292 if (tls_kind)
1293 return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend);
1294
1295 if (any_offset_symbol_operand (sym, mode))
1296 addend = 0;
1297 else if (aligned_offset_symbol_operand (sym, mode))
1298 {
1299 HOST_WIDE_INT addend_lo, addend_hi;
1300
1301 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1302 addend_hi = addend - addend_lo;
1303
1304 if (addend_lo != 0)
1305 {
1306 op1 = plus_constant (mode, sym, addend_hi);
1307 addend = addend_lo;
1308 }
1309 else
1310 addend = 0;
1311 }
1312 else
1313 op1 = sym;
1314
1315 if (reload_completed)
1316 {
1317 /* We really should have taken care of this offset earlier. */
1318 gcc_assert (addend == 0);
1319 if (ia64_expand_load_address (op0, op1))
1320 return NULL_RTX;
1321 }
1322
1323 if (addend)
1324 {
1325 rtx subtarget = !can_create_pseudo_p () ? op0 : gen_reg_rtx (mode);
1326
1327 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1));
1328
1329 op1 = expand_simple_binop (mode, PLUS, subtarget,
1330 GEN_INT (addend), op0, 1, OPTAB_DIRECT);
1331 if (op0 == op1)
1332 return NULL_RTX;
1333 }
1334 }
1335
1336 return op1;
1337 }
1338
1339 /* Split a move from OP1 to OP0 conditional on COND. */
1340
1341 void
1342 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1343 {
1344 rtx_insn *insn, *first = get_last_insn ();
1345
1346 emit_move_insn (op0, op1);
1347
1348 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1349 if (INSN_P (insn))
1350 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1351 PATTERN (insn));
1352 }
1353
1354 /* Split a post-reload TImode or TFmode reference into two DImode
1355 components. This is made extra difficult by the fact that we do
1356 not get any scratch registers to work with, because reload cannot
1357 be prevented from giving us a scratch that overlaps the register
1358 pair involved. So instead, when addressing memory, we tweak the
1359 pointer register up and back down with POST_INCs. Or up and not
1360 back down when we can get away with it.
1361
1362 REVERSED is true when the loads must be done in reversed order
1363 (high word first) for correctness. DEAD is true when the pointer
1364 dies with the second insn we generate and therefore the second
1365 address must not carry a postmodify.
1366
1367 May return an insn which is to be emitted after the moves. */
1368
1369 static rtx
1370 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1371 {
1372 rtx fixup = 0;
1373
1374 switch (GET_CODE (in))
1375 {
1376 case REG:
1377 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1378 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1379 break;
1380
1381 case CONST_INT:
1382 case CONST_DOUBLE:
1383 /* Cannot occur reversed. */
1384 gcc_assert (!reversed);
1385
1386 if (GET_MODE (in) != TFmode)
1387 split_double (in, &out[0], &out[1]);
1388 else
1389 /* split_double does not understand how to split a TFmode
1390 quantity into a pair of DImode constants. */
1391 {
1392 REAL_VALUE_TYPE r;
1393 unsigned HOST_WIDE_INT p[2];
1394 long l[4]; /* TFmode is 128 bits */
1395
1396 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1397 real_to_target (l, &r, TFmode);
1398
1399 if (FLOAT_WORDS_BIG_ENDIAN)
1400 {
1401 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1402 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1403 }
1404 else
1405 {
1406 p[0] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1407 p[1] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1408 }
1409 out[0] = GEN_INT (p[0]);
1410 out[1] = GEN_INT (p[1]);
1411 }
1412 break;
1413
1414 case MEM:
1415 {
1416 rtx base = XEXP (in, 0);
1417 rtx offset;
1418
1419 switch (GET_CODE (base))
1420 {
1421 case REG:
1422 if (!reversed)
1423 {
1424 out[0] = adjust_automodify_address
1425 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1426 out[1] = adjust_automodify_address
1427 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1428 }
1429 else
1430 {
1431 /* Reversal requires a pre-increment, which can only
1432 be done as a separate insn. */
1433 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1434 out[0] = adjust_automodify_address
1435 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1436 out[1] = adjust_address (in, DImode, 0);
1437 }
1438 break;
1439
1440 case POST_INC:
1441 gcc_assert (!reversed && !dead);
1442
1443 /* Just do the increment in two steps. */
1444 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1445 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1446 break;
1447
1448 case POST_DEC:
1449 gcc_assert (!reversed && !dead);
1450
1451 /* Add 8, subtract 24. */
1452 base = XEXP (base, 0);
1453 out[0] = adjust_automodify_address
1454 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1455 out[1] = adjust_automodify_address
1456 (in, DImode,
1457 gen_rtx_POST_MODIFY (Pmode, base,
1458 plus_constant (Pmode, base, -24)),
1459 8);
1460 break;
1461
1462 case POST_MODIFY:
1463 gcc_assert (!reversed && !dead);
1464
1465 /* Extract and adjust the modification. This case is
1466 trickier than the others, because we might have an
1467 index register, or we might have a combined offset that
1468 doesn't fit a signed 9-bit displacement field. We can
1469 assume the incoming expression is already legitimate. */
1470 offset = XEXP (base, 1);
1471 base = XEXP (base, 0);
1472
1473 out[0] = adjust_automodify_address
1474 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1475
1476 if (GET_CODE (XEXP (offset, 1)) == REG)
1477 {
1478 /* Can't adjust the postmodify to match. Emit the
1479 original, then a separate addition insn. */
1480 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1481 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1482 }
1483 else
1484 {
1485 gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
1486 if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1487 {
1488 /* Again the postmodify cannot be made to match,
1489 but in this case it's more efficient to get rid
1490 of the postmodify entirely and fix up with an
1491 add insn. */
1492 out[1] = adjust_automodify_address (in, DImode, base, 8);
1493 fixup = gen_adddi3
1494 (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1495 }
1496 else
1497 {
1498 /* Combined offset still fits in the displacement field.
1499 (We cannot overflow it at the high end.) */
1500 out[1] = adjust_automodify_address
1501 (in, DImode, gen_rtx_POST_MODIFY
1502 (Pmode, base, gen_rtx_PLUS
1503 (Pmode, base,
1504 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1505 8);
1506 }
1507 }
1508 break;
1509
1510 default:
1511 gcc_unreachable ();
1512 }
1513 break;
1514 }
1515
1516 default:
1517 gcc_unreachable ();
1518 }
1519
1520 return fixup;
1521 }
1522
1523 /* Split a TImode or TFmode move instruction after reload.
1524 This is used by *movtf_internal and *movti_internal. */
1525 void
1526 ia64_split_tmode_move (rtx operands[])
1527 {
1528 rtx in[2], out[2], insn;
1529 rtx fixup[2];
1530 bool dead = false;
1531 bool reversed = false;
1532
1533 /* It is possible for reload to decide to overwrite a pointer with
1534 the value it points to. In that case we have to do the loads in
1535 the appropriate order so that the pointer is not destroyed too
1536 early. Also we must not generate a postmodify for that second
1537 load, or rws_access_regno will die. And we must not generate a
1538 postmodify for the second load if the destination register
1539 overlaps with the base register. */
1540 if (GET_CODE (operands[1]) == MEM
1541 && reg_overlap_mentioned_p (operands[0], operands[1]))
1542 {
1543 rtx base = XEXP (operands[1], 0);
1544 while (GET_CODE (base) != REG)
1545 base = XEXP (base, 0);
1546
1547 if (REGNO (base) == REGNO (operands[0]))
1548 reversed = true;
1549
1550 if (refers_to_regno_p (REGNO (operands[0]),
1551 REGNO (operands[0])+2,
1552 base, 0))
1553 dead = true;
1554 }
1555 /* Another reason to do the moves in reversed order is if the first
1556 element of the target register pair is also the second element of
1557 the source register pair. */
1558 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1559 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1560 reversed = true;
1561
1562 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1563 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1564
1565 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1566 if (GET_CODE (EXP) == MEM \
1567 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1568 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1569 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1570 add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0))
1571
1572 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1573 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1574 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1575
1576 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1577 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1578 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1579
1580 if (fixup[0])
1581 emit_insn (fixup[0]);
1582 if (fixup[1])
1583 emit_insn (fixup[1]);
1584
1585 #undef MAYBE_ADD_REG_INC_NOTE
1586 }
1587
1588 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1589 through memory plus an extra GR scratch register. Except that you can
1590 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1591 SECONDARY_RELOAD_CLASS, but not both.
1592
1593 We got into problems in the first place by allowing a construct like
1594 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1595 This solution attempts to prevent this situation from occurring. When
1596 we see something like the above, we spill the inner register to memory. */
1597
1598 static rtx
1599 spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode)
1600 {
1601 if (GET_CODE (in) == SUBREG
1602 && GET_MODE (SUBREG_REG (in)) == TImode
1603 && GET_CODE (SUBREG_REG (in)) == REG)
1604 {
1605 rtx memt = assign_stack_temp (TImode, 16);
1606 emit_move_insn (memt, SUBREG_REG (in));
1607 return adjust_address (memt, mode, 0);
1608 }
1609 else if (force && GET_CODE (in) == REG)
1610 {
1611 rtx memx = assign_stack_temp (mode, 16);
1612 emit_move_insn (memx, in);
1613 return memx;
1614 }
1615 else
1616 return in;
1617 }
1618
1619 /* Expand the movxf or movrf pattern (MODE says which) with the given
1620 OPERANDS, returning true if the pattern should then invoke
1621 DONE. */
1622
1623 bool
1624 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1625 {
1626 rtx op0 = operands[0];
1627
1628 if (GET_CODE (op0) == SUBREG)
1629 op0 = SUBREG_REG (op0);
1630
1631 /* We must support XFmode loads into general registers for stdarg/vararg,
1632 unprototyped calls, and a rare case where a long double is passed as
1633 an argument after a float HFA fills the FP registers. We split them into
1634 DImode loads for convenience. We also need to support XFmode stores
1635 for the last case. This case does not happen for stdarg/vararg routines,
1636 because we do a block store to memory of unnamed arguments. */
1637
1638 if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
1639 {
1640 rtx out[2];
1641
1642 /* We're hoping to transform everything that deals with XFmode
1643 quantities and GR registers early in the compiler. */
1644 gcc_assert (can_create_pseudo_p ());
1645
1646 /* Struct to register can just use TImode instead. */
1647 if ((GET_CODE (operands[1]) == SUBREG
1648 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1649 || (GET_CODE (operands[1]) == REG
1650 && GR_REGNO_P (REGNO (operands[1]))))
1651 {
1652 rtx op1 = operands[1];
1653
1654 if (GET_CODE (op1) == SUBREG)
1655 op1 = SUBREG_REG (op1);
1656 else
1657 op1 = gen_rtx_REG (TImode, REGNO (op1));
1658
1659 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
1660 return true;
1661 }
1662
1663 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1664 {
1665 /* Don't word-swap when reading in the constant. */
1666 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1667 operand_subword (operands[1], WORDS_BIG_ENDIAN,
1668 0, mode));
1669 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1670 operand_subword (operands[1], !WORDS_BIG_ENDIAN,
1671 0, mode));
1672 return true;
1673 }
1674
1675 /* If the quantity is in a register not known to be GR, spill it. */
1676 if (register_operand (operands[1], mode))
1677 operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1678
1679 gcc_assert (GET_CODE (operands[1]) == MEM);
1680
1681 /* Don't word-swap when reading in the value. */
1682 out[0] = gen_rtx_REG (DImode, REGNO (op0));
1683 out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1684
1685 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1686 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1687 return true;
1688 }
1689
1690 if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
1691 {
1692 /* We're hoping to transform everything that deals with XFmode
1693 quantities and GR registers early in the compiler. */
1694 gcc_assert (can_create_pseudo_p ());
1695
1696 /* Op0 can't be a GR_REG here, as that case is handled above.
1697 If op0 is a register, then we spill op1, so that we now have a
1698 MEM operand. This requires creating an XFmode subreg of a TImode reg
1699 to force the spill. */
1700 if (register_operand (operands[0], mode))
1701 {
1702 rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
1703 op1 = gen_rtx_SUBREG (mode, op1, 0);
1704 operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1705 }
1706
1707 else
1708 {
1709 rtx in[2];
1710
1711 gcc_assert (GET_CODE (operands[0]) == MEM);
1712
1713 /* Don't word-swap when writing out the value. */
1714 in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1715 in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1716
1717 emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1718 emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1719 return true;
1720 }
1721 }
1722
1723 if (!reload_in_progress && !reload_completed)
1724 {
1725 operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1726
1727 if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
1728 {
1729 rtx memt, memx, in = operands[1];
1730 if (CONSTANT_P (in))
1731 in = validize_mem (force_const_mem (mode, in));
1732 if (GET_CODE (in) == MEM)
1733 memt = adjust_address (in, TImode, 0);
1734 else
1735 {
1736 memt = assign_stack_temp (TImode, 16);
1737 memx = adjust_address (memt, mode, 0);
1738 emit_move_insn (memx, in);
1739 }
1740 emit_move_insn (op0, memt);
1741 return true;
1742 }
1743
1744 if (!ia64_move_ok (operands[0], operands[1]))
1745 operands[1] = force_reg (mode, operands[1]);
1746 }
1747
1748 return false;
1749 }
1750
1751 /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
1752 with the expression that holds the compare result (in VOIDmode). */
1753
1754 static GTY(()) rtx cmptf_libfunc;
1755
1756 void
1757 ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1)
1758 {
1759 enum rtx_code code = GET_CODE (*expr);
1760 rtx cmp;
1761
1762 /* If we have a BImode input, then we already have a compare result, and
1763 do not need to emit another comparison. */
1764 if (GET_MODE (*op0) == BImode)
1765 {
1766 gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx);
1767 cmp = *op0;
1768 }
1769 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1770 magic number as its third argument, that indicates what to do.
1771 The return value is an integer to be compared against zero. */
1772 else if (TARGET_HPUX && GET_MODE (*op0) == TFmode)
1773 {
1774 enum qfcmp_magic {
1775 QCMP_INV = 1, /* Raise FP_INVALID on NaNs as a side effect. */
1776 QCMP_UNORD = 2,
1777 QCMP_EQ = 4,
1778 QCMP_LT = 8,
1779 QCMP_GT = 16
1780 };
1781 int magic;
1782 enum rtx_code ncode;
1783 rtx ret, insns;
1784
1785 gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode);
1786 switch (code)
1787 {
1788 /* 1 = equal, 0 = not equal. Equality operators do
1789 not raise FP_INVALID when given a NaN operand. */
1790 case EQ: magic = QCMP_EQ; ncode = NE; break;
1791 case NE: magic = QCMP_EQ; ncode = EQ; break;
1792 /* isunordered() from C99. */
1793 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1794 case ORDERED: magic = QCMP_UNORD; ncode = EQ; break;
1795 /* Relational operators raise FP_INVALID when given
1796 a NaN operand. */
1797 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1798 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1799 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1800 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1801 /* Unordered relational operators do not raise FP_INVALID
1802 when given a NaN operand. */
1803 case UNLT: magic = QCMP_LT |QCMP_UNORD; ncode = NE; break;
1804 case UNLE: magic = QCMP_LT|QCMP_EQ|QCMP_UNORD; ncode = NE; break;
1805 case UNGT: magic = QCMP_GT |QCMP_UNORD; ncode = NE; break;
1806 case UNGE: magic = QCMP_GT|QCMP_EQ|QCMP_UNORD; ncode = NE; break;
1807 /* Not supported. */
1808 case UNEQ:
1809 case LTGT:
1810 default: gcc_unreachable ();
1811 }
1812
1813 start_sequence ();
1814
1815 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1816 *op0, TFmode, *op1, TFmode,
1817 GEN_INT (magic), DImode);
1818 cmp = gen_reg_rtx (BImode);
1819 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1820 gen_rtx_fmt_ee (ncode, BImode,
1821 ret, const0_rtx)));
1822
1823 insns = get_insns ();
1824 end_sequence ();
1825
1826 emit_libcall_block (insns, cmp, cmp,
1827 gen_rtx_fmt_ee (code, BImode, *op0, *op1));
1828 code = NE;
1829 }
1830 else
1831 {
1832 cmp = gen_reg_rtx (BImode);
1833 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1834 gen_rtx_fmt_ee (code, BImode, *op0, *op1)));
1835 code = NE;
1836 }
1837
1838 *expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx);
1839 *op0 = cmp;
1840 *op1 = const0_rtx;
1841 }
1842
1843 /* Generate an integral vector comparison. Return true if the condition has
1844 been reversed, and so the sense of the comparison should be inverted. */
1845
1846 static bool
1847 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1848 rtx dest, rtx op0, rtx op1)
1849 {
1850 bool negate = false;
1851 rtx x;
1852
1853 /* Canonicalize the comparison to EQ, GT, GTU. */
1854 switch (code)
1855 {
1856 case EQ:
1857 case GT:
1858 case GTU:
1859 break;
1860
1861 case NE:
1862 case LE:
1863 case LEU:
1864 code = reverse_condition (code);
1865 negate = true;
1866 break;
1867
1868 case GE:
1869 case GEU:
1870 code = reverse_condition (code);
1871 negate = true;
1872 /* FALLTHRU */
1873
1874 case LT:
1875 case LTU:
1876 code = swap_condition (code);
1877 x = op0, op0 = op1, op1 = x;
1878 break;
1879
1880 default:
1881 gcc_unreachable ();
1882 }
1883
1884 /* Unsigned parallel compare is not supported by the hardware. Play some
1885 tricks to turn this into a signed comparison against 0. */
1886 if (code == GTU)
1887 {
1888 switch (mode)
1889 {
1890 case V2SImode:
1891 {
1892 rtx t1, t2, mask;
1893
1894 /* Subtract (-(INT MAX) - 1) from both operands to make
1895 them signed. */
1896 mask = GEN_INT (0x80000000);
1897 mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
1898 mask = force_reg (mode, mask);
1899 t1 = gen_reg_rtx (mode);
1900 emit_insn (gen_subv2si3 (t1, op0, mask));
1901 t2 = gen_reg_rtx (mode);
1902 emit_insn (gen_subv2si3 (t2, op1, mask));
1903 op0 = t1;
1904 op1 = t2;
1905 code = GT;
1906 }
1907 break;
1908
1909 case V8QImode:
1910 case V4HImode:
1911 /* Perform a parallel unsigned saturating subtraction. */
1912 x = gen_reg_rtx (mode);
1913 emit_insn (gen_rtx_SET (VOIDmode, x,
1914 gen_rtx_US_MINUS (mode, op0, op1)));
1915
1916 code = EQ;
1917 op0 = x;
1918 op1 = CONST0_RTX (mode);
1919 negate = !negate;
1920 break;
1921
1922 default:
1923 gcc_unreachable ();
1924 }
1925 }
1926
1927 x = gen_rtx_fmt_ee (code, mode, op0, op1);
1928 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1929
1930 return negate;
1931 }
1932
1933 /* Emit an integral vector conditional move. */
1934
1935 void
1936 ia64_expand_vecint_cmov (rtx operands[])
1937 {
1938 enum machine_mode mode = GET_MODE (operands[0]);
1939 enum rtx_code code = GET_CODE (operands[3]);
1940 bool negate;
1941 rtx cmp, x, ot, of;
1942
1943 cmp = gen_reg_rtx (mode);
1944 negate = ia64_expand_vecint_compare (code, mode, cmp,
1945 operands[4], operands[5]);
1946
1947 ot = operands[1+negate];
1948 of = operands[2-negate];
1949
1950 if (ot == CONST0_RTX (mode))
1951 {
1952 if (of == CONST0_RTX (mode))
1953 {
1954 emit_move_insn (operands[0], ot);
1955 return;
1956 }
1957
1958 x = gen_rtx_NOT (mode, cmp);
1959 x = gen_rtx_AND (mode, x, of);
1960 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1961 }
1962 else if (of == CONST0_RTX (mode))
1963 {
1964 x = gen_rtx_AND (mode, cmp, ot);
1965 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1966 }
1967 else
1968 {
1969 rtx t, f;
1970
1971 t = gen_reg_rtx (mode);
1972 x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1973 emit_insn (gen_rtx_SET (VOIDmode, t, x));
1974
1975 f = gen_reg_rtx (mode);
1976 x = gen_rtx_NOT (mode, cmp);
1977 x = gen_rtx_AND (mode, x, operands[2-negate]);
1978 emit_insn (gen_rtx_SET (VOIDmode, f, x));
1979
1980 x = gen_rtx_IOR (mode, t, f);
1981 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1982 }
1983 }
1984
1985 /* Emit an integral vector min or max operation. Return true if all done. */
1986
1987 bool
1988 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1989 rtx operands[])
1990 {
1991 rtx xops[6];
1992
1993 /* These four combinations are supported directly. */
1994 if (mode == V8QImode && (code == UMIN || code == UMAX))
1995 return false;
1996 if (mode == V4HImode && (code == SMIN || code == SMAX))
1997 return false;
1998
1999 /* This combination can be implemented with only saturating subtraction. */
2000 if (mode == V4HImode && code == UMAX)
2001 {
2002 rtx x, tmp = gen_reg_rtx (mode);
2003
2004 x = gen_rtx_US_MINUS (mode, operands[1], operands[2]);
2005 emit_insn (gen_rtx_SET (VOIDmode, tmp, x));
2006
2007 emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2]));
2008 return true;
2009 }
2010
2011 /* Everything else implemented via vector comparisons. */
2012 xops[0] = operands[0];
2013 xops[4] = xops[1] = operands[1];
2014 xops[5] = xops[2] = operands[2];
2015
2016 switch (code)
2017 {
2018 case UMIN:
2019 code = LTU;
2020 break;
2021 case UMAX:
2022 code = GTU;
2023 break;
2024 case SMIN:
2025 code = LT;
2026 break;
2027 case SMAX:
2028 code = GT;
2029 break;
2030 default:
2031 gcc_unreachable ();
2032 }
2033 xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
2034
2035 ia64_expand_vecint_cmov (xops);
2036 return true;
2037 }
2038
2039 /* The vectors LO and HI each contain N halves of a double-wide vector.
2040 Reassemble either the first N/2 or the second N/2 elements. */
2041
2042 void
2043 ia64_unpack_assemble (rtx out, rtx lo, rtx hi, bool highp)
2044 {
2045 enum machine_mode vmode = GET_MODE (lo);
2046 unsigned int i, high, nelt = GET_MODE_NUNITS (vmode);
2047 struct expand_vec_perm_d d;
2048 bool ok;
2049
2050 d.target = gen_lowpart (vmode, out);
2051 d.op0 = (TARGET_BIG_ENDIAN ? hi : lo);
2052 d.op1 = (TARGET_BIG_ENDIAN ? lo : hi);
2053 d.vmode = vmode;
2054 d.nelt = nelt;
2055 d.one_operand_p = false;
2056 d.testing_p = false;
2057
2058 high = (highp ? nelt / 2 : 0);
2059 for (i = 0; i < nelt / 2; ++i)
2060 {
2061 d.perm[i * 2] = i + high;
2062 d.perm[i * 2 + 1] = i + high + nelt;
2063 }
2064
2065 ok = ia64_expand_vec_perm_const_1 (&d);
2066 gcc_assert (ok);
2067 }
2068
2069 /* Return a vector of the sign-extension of VEC. */
2070
2071 static rtx
2072 ia64_unpack_sign (rtx vec, bool unsignedp)
2073 {
2074 enum machine_mode mode = GET_MODE (vec);
2075 rtx zero = CONST0_RTX (mode);
2076
2077 if (unsignedp)
2078 return zero;
2079 else
2080 {
2081 rtx sign = gen_reg_rtx (mode);
2082 bool neg;
2083
2084 neg = ia64_expand_vecint_compare (LT, mode, sign, vec, zero);
2085 gcc_assert (!neg);
2086
2087 return sign;
2088 }
2089 }
2090
2091 /* Emit an integral vector unpack operation. */
2092
2093 void
2094 ia64_expand_unpack (rtx operands[3], bool unsignedp, bool highp)
2095 {
2096 rtx sign = ia64_unpack_sign (operands[1], unsignedp);
2097 ia64_unpack_assemble (operands[0], operands[1], sign, highp);
2098 }
2099
2100 /* Emit an integral vector widening sum operations. */
2101
2102 void
2103 ia64_expand_widen_sum (rtx operands[3], bool unsignedp)
2104 {
2105 enum machine_mode wmode;
2106 rtx l, h, t, sign;
2107
2108 sign = ia64_unpack_sign (operands[1], unsignedp);
2109
2110 wmode = GET_MODE (operands[0]);
2111 l = gen_reg_rtx (wmode);
2112 h = gen_reg_rtx (wmode);
2113
2114 ia64_unpack_assemble (l, operands[1], sign, false);
2115 ia64_unpack_assemble (h, operands[1], sign, true);
2116
2117 t = expand_binop (wmode, add_optab, l, operands[2], NULL, 0, OPTAB_DIRECT);
2118 t = expand_binop (wmode, add_optab, h, t, operands[0], 0, OPTAB_DIRECT);
2119 if (t != operands[0])
2120 emit_move_insn (operands[0], t);
2121 }
2122
2123 /* Emit the appropriate sequence for a call. */
2124
2125 void
2126 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
2127 int sibcall_p)
2128 {
2129 rtx insn, b0;
2130
2131 addr = XEXP (addr, 0);
2132 addr = convert_memory_address (DImode, addr);
2133 b0 = gen_rtx_REG (DImode, R_BR (0));
2134
2135 /* ??? Should do this for functions known to bind local too. */
2136 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
2137 {
2138 if (sibcall_p)
2139 insn = gen_sibcall_nogp (addr);
2140 else if (! retval)
2141 insn = gen_call_nogp (addr, b0);
2142 else
2143 insn = gen_call_value_nogp (retval, addr, b0);
2144 insn = emit_call_insn (insn);
2145 }
2146 else
2147 {
2148 if (sibcall_p)
2149 insn = gen_sibcall_gp (addr);
2150 else if (! retval)
2151 insn = gen_call_gp (addr, b0);
2152 else
2153 insn = gen_call_value_gp (retval, addr, b0);
2154 insn = emit_call_insn (insn);
2155
2156 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2157 }
2158
2159 if (sibcall_p)
2160 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
2161
2162 if (TARGET_ABI_OPEN_VMS)
2163 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2164 gen_rtx_REG (DImode, GR_REG (25)));
2165 }
2166
2167 static void
2168 reg_emitted (enum ia64_frame_regs r)
2169 {
2170 if (emitted_frame_related_regs[r] == 0)
2171 emitted_frame_related_regs[r] = current_frame_info.r[r];
2172 else
2173 gcc_assert (emitted_frame_related_regs[r] == current_frame_info.r[r]);
2174 }
2175
2176 static int
2177 get_reg (enum ia64_frame_regs r)
2178 {
2179 reg_emitted (r);
2180 return current_frame_info.r[r];
2181 }
2182
2183 static bool
2184 is_emitted (int regno)
2185 {
2186 unsigned int r;
2187
2188 for (r = reg_fp; r < number_of_ia64_frame_regs; r++)
2189 if (emitted_frame_related_regs[r] == regno)
2190 return true;
2191 return false;
2192 }
2193
2194 void
2195 ia64_reload_gp (void)
2196 {
2197 rtx tmp;
2198
2199 if (current_frame_info.r[reg_save_gp])
2200 {
2201 tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp));
2202 }
2203 else
2204 {
2205 HOST_WIDE_INT offset;
2206 rtx offset_r;
2207
2208 offset = (current_frame_info.spill_cfa_off
2209 + current_frame_info.spill_size);
2210 if (frame_pointer_needed)
2211 {
2212 tmp = hard_frame_pointer_rtx;
2213 offset = -offset;
2214 }
2215 else
2216 {
2217 tmp = stack_pointer_rtx;
2218 offset = current_frame_info.total_size - offset;
2219 }
2220
2221 offset_r = GEN_INT (offset);
2222 if (satisfies_constraint_I (offset_r))
2223 emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r));
2224 else
2225 {
2226 emit_move_insn (pic_offset_table_rtx, offset_r);
2227 emit_insn (gen_adddi3 (pic_offset_table_rtx,
2228 pic_offset_table_rtx, tmp));
2229 }
2230
2231 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
2232 }
2233
2234 emit_move_insn (pic_offset_table_rtx, tmp);
2235 }
2236
2237 void
2238 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
2239 rtx scratch_b, int noreturn_p, int sibcall_p)
2240 {
2241 rtx insn;
2242 bool is_desc = false;
2243
2244 /* If we find we're calling through a register, then we're actually
2245 calling through a descriptor, so load up the values. */
2246 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
2247 {
2248 rtx tmp;
2249 bool addr_dead_p;
2250
2251 /* ??? We are currently constrained to *not* use peep2, because
2252 we can legitimately change the global lifetime of the GP
2253 (in the form of killing where previously live). This is
2254 because a call through a descriptor doesn't use the previous
2255 value of the GP, while a direct call does, and we do not
2256 commit to either form until the split here.
2257
2258 That said, this means that we lack precise life info for
2259 whether ADDR is dead after this call. This is not terribly
2260 important, since we can fix things up essentially for free
2261 with the POST_DEC below, but it's nice to not use it when we
2262 can immediately tell it's not necessary. */
2263 addr_dead_p = ((noreturn_p || sibcall_p
2264 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
2265 REGNO (addr)))
2266 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
2267
2268 /* Load the code address into scratch_b. */
2269 tmp = gen_rtx_POST_INC (Pmode, addr);
2270 tmp = gen_rtx_MEM (Pmode, tmp);
2271 emit_move_insn (scratch_r, tmp);
2272 emit_move_insn (scratch_b, scratch_r);
2273
2274 /* Load the GP address. If ADDR is not dead here, then we must
2275 revert the change made above via the POST_INCREMENT. */
2276 if (!addr_dead_p)
2277 tmp = gen_rtx_POST_DEC (Pmode, addr);
2278 else
2279 tmp = addr;
2280 tmp = gen_rtx_MEM (Pmode, tmp);
2281 emit_move_insn (pic_offset_table_rtx, tmp);
2282
2283 is_desc = true;
2284 addr = scratch_b;
2285 }
2286
2287 if (sibcall_p)
2288 insn = gen_sibcall_nogp (addr);
2289 else if (retval)
2290 insn = gen_call_value_nogp (retval, addr, retaddr);
2291 else
2292 insn = gen_call_nogp (addr, retaddr);
2293 emit_call_insn (insn);
2294
2295 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
2296 ia64_reload_gp ();
2297 }
2298
2299 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2300
2301 This differs from the generic code in that we know about the zero-extending
2302 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2303 also know that ld.acq+cmpxchg.rel equals a full barrier.
2304
2305 The loop we want to generate looks like
2306
2307 cmp_reg = mem;
2308 label:
2309 old_reg = cmp_reg;
2310 new_reg = cmp_reg op val;
2311 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2312 if (cmp_reg != old_reg)
2313 goto label;
2314
2315 Note that we only do the plain load from memory once. Subsequent
2316 iterations use the value loaded by the compare-and-swap pattern. */
2317
2318 void
2319 ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
2320 rtx old_dst, rtx new_dst, enum memmodel model)
2321 {
2322 enum machine_mode mode = GET_MODE (mem);
2323 rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
2324 enum insn_code icode;
2325
2326 /* Special case for using fetchadd. */
2327 if ((mode == SImode || mode == DImode)
2328 && (code == PLUS || code == MINUS)
2329 && fetchadd_operand (val, mode))
2330 {
2331 if (code == MINUS)
2332 val = GEN_INT (-INTVAL (val));
2333
2334 if (!old_dst)
2335 old_dst = gen_reg_rtx (mode);
2336
2337 switch (model)
2338 {
2339 case MEMMODEL_ACQ_REL:
2340 case MEMMODEL_SEQ_CST:
2341 emit_insn (gen_memory_barrier ());
2342 /* FALLTHRU */
2343 case MEMMODEL_RELAXED:
2344 case MEMMODEL_ACQUIRE:
2345 case MEMMODEL_CONSUME:
2346 if (mode == SImode)
2347 icode = CODE_FOR_fetchadd_acq_si;
2348 else
2349 icode = CODE_FOR_fetchadd_acq_di;
2350 break;
2351 case MEMMODEL_RELEASE:
2352 if (mode == SImode)
2353 icode = CODE_FOR_fetchadd_rel_si;
2354 else
2355 icode = CODE_FOR_fetchadd_rel_di;
2356 break;
2357
2358 default:
2359 gcc_unreachable ();
2360 }
2361
2362 emit_insn (GEN_FCN (icode) (old_dst, mem, val));
2363
2364 if (new_dst)
2365 {
2366 new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
2367 true, OPTAB_WIDEN);
2368 if (new_reg != new_dst)
2369 emit_move_insn (new_dst, new_reg);
2370 }
2371 return;
2372 }
2373
2374 /* Because of the volatile mem read, we get an ld.acq, which is the
2375 front half of the full barrier. The end half is the cmpxchg.rel.
2376 For relaxed and release memory models, we don't need this. But we
2377 also don't bother trying to prevent it either. */
2378 gcc_assert (model == MEMMODEL_RELAXED
2379 || model == MEMMODEL_RELEASE
2380 || MEM_VOLATILE_P (mem));
2381
2382 old_reg = gen_reg_rtx (DImode);
2383 cmp_reg = gen_reg_rtx (DImode);
2384 label = gen_label_rtx ();
2385
2386 if (mode != DImode)
2387 {
2388 val = simplify_gen_subreg (DImode, val, mode, 0);
2389 emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2390 }
2391 else
2392 emit_move_insn (cmp_reg, mem);
2393
2394 emit_label (label);
2395
2396 ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
2397 emit_move_insn (old_reg, cmp_reg);
2398 emit_move_insn (ar_ccv, cmp_reg);
2399
2400 if (old_dst)
2401 emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
2402
2403 new_reg = cmp_reg;
2404 if (code == NOT)
2405 {
2406 new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX,
2407 true, OPTAB_DIRECT);
2408 new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true);
2409 }
2410 else
2411 new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
2412 true, OPTAB_DIRECT);
2413
2414 if (mode != DImode)
2415 new_reg = gen_lowpart (mode, new_reg);
2416 if (new_dst)
2417 emit_move_insn (new_dst, new_reg);
2418
2419 switch (model)
2420 {
2421 case MEMMODEL_RELAXED:
2422 case MEMMODEL_ACQUIRE:
2423 case MEMMODEL_CONSUME:
2424 switch (mode)
2425 {
2426 case QImode: icode = CODE_FOR_cmpxchg_acq_qi; break;
2427 case HImode: icode = CODE_FOR_cmpxchg_acq_hi; break;
2428 case SImode: icode = CODE_FOR_cmpxchg_acq_si; break;
2429 case DImode: icode = CODE_FOR_cmpxchg_acq_di; break;
2430 default:
2431 gcc_unreachable ();
2432 }
2433 break;
2434
2435 case MEMMODEL_RELEASE:
2436 case MEMMODEL_ACQ_REL:
2437 case MEMMODEL_SEQ_CST:
2438 switch (mode)
2439 {
2440 case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
2441 case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
2442 case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
2443 case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
2444 default:
2445 gcc_unreachable ();
2446 }
2447 break;
2448
2449 default:
2450 gcc_unreachable ();
2451 }
2452
2453 emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
2454
2455 emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
2456 }
2457 \f
2458 /* Begin the assembly file. */
2459
2460 static void
2461 ia64_file_start (void)
2462 {
2463 default_file_start ();
2464 emit_safe_across_calls ();
2465 }
2466
2467 void
2468 emit_safe_across_calls (void)
2469 {
2470 unsigned int rs, re;
2471 int out_state;
2472
2473 rs = 1;
2474 out_state = 0;
2475 while (1)
2476 {
2477 while (rs < 64 && call_used_regs[PR_REG (rs)])
2478 rs++;
2479 if (rs >= 64)
2480 break;
2481 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
2482 continue;
2483 if (out_state == 0)
2484 {
2485 fputs ("\t.pred.safe_across_calls ", asm_out_file);
2486 out_state = 1;
2487 }
2488 else
2489 fputc (',', asm_out_file);
2490 if (re == rs + 1)
2491 fprintf (asm_out_file, "p%u", rs);
2492 else
2493 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
2494 rs = re + 1;
2495 }
2496 if (out_state)
2497 fputc ('\n', asm_out_file);
2498 }
2499
2500 /* Globalize a declaration. */
2501
2502 static void
2503 ia64_globalize_decl_name (FILE * stream, tree decl)
2504 {
2505 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2506 tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl));
2507 if (version_attr)
2508 {
2509 tree v = TREE_VALUE (TREE_VALUE (version_attr));
2510 const char *p = TREE_STRING_POINTER (v);
2511 fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p);
2512 }
2513 targetm.asm_out.globalize_label (stream, name);
2514 if (TREE_CODE (decl) == FUNCTION_DECL)
2515 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function");
2516 }
2517
2518 /* Helper function for ia64_compute_frame_size: find an appropriate general
2519 register to spill some special register to. SPECIAL_SPILL_MASK contains
2520 bits in GR0 to GR31 that have already been allocated by this routine.
2521 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2522
2523 static int
2524 find_gr_spill (enum ia64_frame_regs r, int try_locals)
2525 {
2526 int regno;
2527
2528 if (emitted_frame_related_regs[r] != 0)
2529 {
2530 regno = emitted_frame_related_regs[r];
2531 if (regno >= LOC_REG (0) && regno < LOC_REG (80 - frame_pointer_needed)
2532 && current_frame_info.n_local_regs < regno - LOC_REG (0) + 1)
2533 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2534 else if (crtl->is_leaf
2535 && regno >= GR_REG (1) && regno <= GR_REG (31))
2536 current_frame_info.gr_used_mask |= 1 << regno;
2537
2538 return regno;
2539 }
2540
2541 /* If this is a leaf function, first try an otherwise unused
2542 call-clobbered register. */
2543 if (crtl->is_leaf)
2544 {
2545 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2546 if (! df_regs_ever_live_p (regno)
2547 && call_used_regs[regno]
2548 && ! fixed_regs[regno]
2549 && ! global_regs[regno]
2550 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0
2551 && ! is_emitted (regno))
2552 {
2553 current_frame_info.gr_used_mask |= 1 << regno;
2554 return regno;
2555 }
2556 }
2557
2558 if (try_locals)
2559 {
2560 regno = current_frame_info.n_local_regs;
2561 /* If there is a frame pointer, then we can't use loc79, because
2562 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2563 reg_name switching code in ia64_expand_prologue. */
2564 while (regno < (80 - frame_pointer_needed))
2565 if (! is_emitted (LOC_REG (regno++)))
2566 {
2567 current_frame_info.n_local_regs = regno;
2568 return LOC_REG (regno - 1);
2569 }
2570 }
2571
2572 /* Failed to find a general register to spill to. Must use stack. */
2573 return 0;
2574 }
2575
2576 /* In order to make for nice schedules, we try to allocate every temporary
2577 to a different register. We must of course stay away from call-saved,
2578 fixed, and global registers. We must also stay away from registers
2579 allocated in current_frame_info.gr_used_mask, since those include regs
2580 used all through the prologue.
2581
2582 Any register allocated here must be used immediately. The idea is to
2583 aid scheduling, not to solve data flow problems. */
2584
2585 static int last_scratch_gr_reg;
2586
2587 static int
2588 next_scratch_gr_reg (void)
2589 {
2590 int i, regno;
2591
2592 for (i = 0; i < 32; ++i)
2593 {
2594 regno = (last_scratch_gr_reg + i + 1) & 31;
2595 if (call_used_regs[regno]
2596 && ! fixed_regs[regno]
2597 && ! global_regs[regno]
2598 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2599 {
2600 last_scratch_gr_reg = regno;
2601 return regno;
2602 }
2603 }
2604
2605 /* There must be _something_ available. */
2606 gcc_unreachable ();
2607 }
2608
2609 /* Helper function for ia64_compute_frame_size, called through
2610 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2611
2612 static void
2613 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2614 {
2615 unsigned int regno = REGNO (reg);
2616 if (regno < 32)
2617 {
2618 unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)];
2619 for (i = 0; i < n; ++i)
2620 current_frame_info.gr_used_mask |= 1 << (regno + i);
2621 }
2622 }
2623
2624
2625 /* Returns the number of bytes offset between the frame pointer and the stack
2626 pointer for the current function. SIZE is the number of bytes of space
2627 needed for local variables. */
2628
2629 static void
2630 ia64_compute_frame_size (HOST_WIDE_INT size)
2631 {
2632 HOST_WIDE_INT total_size;
2633 HOST_WIDE_INT spill_size = 0;
2634 HOST_WIDE_INT extra_spill_size = 0;
2635 HOST_WIDE_INT pretend_args_size;
2636 HARD_REG_SET mask;
2637 int n_spilled = 0;
2638 int spilled_gr_p = 0;
2639 int spilled_fr_p = 0;
2640 unsigned int regno;
2641 int min_regno;
2642 int max_regno;
2643 int i;
2644
2645 if (current_frame_info.initialized)
2646 return;
2647
2648 memset (&current_frame_info, 0, sizeof current_frame_info);
2649 CLEAR_HARD_REG_SET (mask);
2650
2651 /* Don't allocate scratches to the return register. */
2652 diddle_return_value (mark_reg_gr_used_mask, NULL);
2653
2654 /* Don't allocate scratches to the EH scratch registers. */
2655 if (cfun->machine->ia64_eh_epilogue_sp)
2656 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2657 if (cfun->machine->ia64_eh_epilogue_bsp)
2658 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2659
2660 /* Static stack checking uses r2 and r3. */
2661 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
2662 current_frame_info.gr_used_mask |= 0xc;
2663
2664 /* Find the size of the register stack frame. We have only 80 local
2665 registers, because we reserve 8 for the inputs and 8 for the
2666 outputs. */
2667
2668 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2669 since we'll be adjusting that down later. */
2670 regno = LOC_REG (78) + ! frame_pointer_needed;
2671 for (; regno >= LOC_REG (0); regno--)
2672 if (df_regs_ever_live_p (regno) && !is_emitted (regno))
2673 break;
2674 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2675
2676 /* For functions marked with the syscall_linkage attribute, we must mark
2677 all eight input registers as in use, so that locals aren't visible to
2678 the caller. */
2679
2680 if (cfun->machine->n_varargs > 0
2681 || lookup_attribute ("syscall_linkage",
2682 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2683 current_frame_info.n_input_regs = 8;
2684 else
2685 {
2686 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2687 if (df_regs_ever_live_p (regno))
2688 break;
2689 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2690 }
2691
2692 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2693 if (df_regs_ever_live_p (regno))
2694 break;
2695 i = regno - OUT_REG (0) + 1;
2696
2697 #ifndef PROFILE_HOOK
2698 /* When -p profiling, we need one output register for the mcount argument.
2699 Likewise for -a profiling for the bb_init_func argument. For -ax
2700 profiling, we need two output registers for the two bb_init_trace_func
2701 arguments. */
2702 if (crtl->profile)
2703 i = MAX (i, 1);
2704 #endif
2705 current_frame_info.n_output_regs = i;
2706
2707 /* ??? No rotating register support yet. */
2708 current_frame_info.n_rotate_regs = 0;
2709
2710 /* Discover which registers need spilling, and how much room that
2711 will take. Begin with floating point and general registers,
2712 which will always wind up on the stack. */
2713
2714 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2715 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2716 {
2717 SET_HARD_REG_BIT (mask, regno);
2718 spill_size += 16;
2719 n_spilled += 1;
2720 spilled_fr_p = 1;
2721 }
2722
2723 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2724 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2725 {
2726 SET_HARD_REG_BIT (mask, regno);
2727 spill_size += 8;
2728 n_spilled += 1;
2729 spilled_gr_p = 1;
2730 }
2731
2732 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2733 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2734 {
2735 SET_HARD_REG_BIT (mask, regno);
2736 spill_size += 8;
2737 n_spilled += 1;
2738 }
2739
2740 /* Now come all special registers that might get saved in other
2741 general registers. */
2742
2743 if (frame_pointer_needed)
2744 {
2745 current_frame_info.r[reg_fp] = find_gr_spill (reg_fp, 1);
2746 /* If we did not get a register, then we take LOC79. This is guaranteed
2747 to be free, even if regs_ever_live is already set, because this is
2748 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2749 as we don't count loc79 above. */
2750 if (current_frame_info.r[reg_fp] == 0)
2751 {
2752 current_frame_info.r[reg_fp] = LOC_REG (79);
2753 current_frame_info.n_local_regs = LOC_REG (79) - LOC_REG (0) + 1;
2754 }
2755 }
2756
2757 if (! crtl->is_leaf)
2758 {
2759 /* Emit a save of BR0 if we call other functions. Do this even
2760 if this function doesn't return, as EH depends on this to be
2761 able to unwind the stack. */
2762 SET_HARD_REG_BIT (mask, BR_REG (0));
2763
2764 current_frame_info.r[reg_save_b0] = find_gr_spill (reg_save_b0, 1);
2765 if (current_frame_info.r[reg_save_b0] == 0)
2766 {
2767 extra_spill_size += 8;
2768 n_spilled += 1;
2769 }
2770
2771 /* Similarly for ar.pfs. */
2772 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2773 current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1);
2774 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2775 {
2776 extra_spill_size += 8;
2777 n_spilled += 1;
2778 }
2779
2780 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2781 registers are clobbered, so we fall back to the stack. */
2782 current_frame_info.r[reg_save_gp]
2783 = (cfun->calls_setjmp ? 0 : find_gr_spill (reg_save_gp, 1));
2784 if (current_frame_info.r[reg_save_gp] == 0)
2785 {
2786 SET_HARD_REG_BIT (mask, GR_REG (1));
2787 spill_size += 8;
2788 n_spilled += 1;
2789 }
2790 }
2791 else
2792 {
2793 if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs[BR_REG (0)])
2794 {
2795 SET_HARD_REG_BIT (mask, BR_REG (0));
2796 extra_spill_size += 8;
2797 n_spilled += 1;
2798 }
2799
2800 if (df_regs_ever_live_p (AR_PFS_REGNUM))
2801 {
2802 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2803 current_frame_info.r[reg_save_ar_pfs]
2804 = find_gr_spill (reg_save_ar_pfs, 1);
2805 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2806 {
2807 extra_spill_size += 8;
2808 n_spilled += 1;
2809 }
2810 }
2811 }
2812
2813 /* Unwind descriptor hackery: things are most efficient if we allocate
2814 consecutive GR save registers for RP, PFS, FP in that order. However,
2815 it is absolutely critical that FP get the only hard register that's
2816 guaranteed to be free, so we allocated it first. If all three did
2817 happen to be allocated hard regs, and are consecutive, rearrange them
2818 into the preferred order now.
2819
2820 If we have already emitted code for any of those registers,
2821 then it's already too late to change. */
2822 min_regno = MIN (current_frame_info.r[reg_fp],
2823 MIN (current_frame_info.r[reg_save_b0],
2824 current_frame_info.r[reg_save_ar_pfs]));
2825 max_regno = MAX (current_frame_info.r[reg_fp],
2826 MAX (current_frame_info.r[reg_save_b0],
2827 current_frame_info.r[reg_save_ar_pfs]));
2828 if (min_regno > 0
2829 && min_regno + 2 == max_regno
2830 && (current_frame_info.r[reg_fp] == min_regno + 1
2831 || current_frame_info.r[reg_save_b0] == min_regno + 1
2832 || current_frame_info.r[reg_save_ar_pfs] == min_regno + 1)
2833 && (emitted_frame_related_regs[reg_save_b0] == 0
2834 || emitted_frame_related_regs[reg_save_b0] == min_regno)
2835 && (emitted_frame_related_regs[reg_save_ar_pfs] == 0
2836 || emitted_frame_related_regs[reg_save_ar_pfs] == min_regno + 1)
2837 && (emitted_frame_related_regs[reg_fp] == 0
2838 || emitted_frame_related_regs[reg_fp] == min_regno + 2))
2839 {
2840 current_frame_info.r[reg_save_b0] = min_regno;
2841 current_frame_info.r[reg_save_ar_pfs] = min_regno + 1;
2842 current_frame_info.r[reg_fp] = min_regno + 2;
2843 }
2844
2845 /* See if we need to store the predicate register block. */
2846 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2847 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2848 break;
2849 if (regno <= PR_REG (63))
2850 {
2851 SET_HARD_REG_BIT (mask, PR_REG (0));
2852 current_frame_info.r[reg_save_pr] = find_gr_spill (reg_save_pr, 1);
2853 if (current_frame_info.r[reg_save_pr] == 0)
2854 {
2855 extra_spill_size += 8;
2856 n_spilled += 1;
2857 }
2858
2859 /* ??? Mark them all as used so that register renaming and such
2860 are free to use them. */
2861 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2862 df_set_regs_ever_live (regno, true);
2863 }
2864
2865 /* If we're forced to use st8.spill, we're forced to save and restore
2866 ar.unat as well. The check for existing liveness allows inline asm
2867 to touch ar.unat. */
2868 if (spilled_gr_p || cfun->machine->n_varargs
2869 || df_regs_ever_live_p (AR_UNAT_REGNUM))
2870 {
2871 df_set_regs_ever_live (AR_UNAT_REGNUM, true);
2872 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2873 current_frame_info.r[reg_save_ar_unat]
2874 = find_gr_spill (reg_save_ar_unat, spill_size == 0);
2875 if (current_frame_info.r[reg_save_ar_unat] == 0)
2876 {
2877 extra_spill_size += 8;
2878 n_spilled += 1;
2879 }
2880 }
2881
2882 if (df_regs_ever_live_p (AR_LC_REGNUM))
2883 {
2884 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2885 current_frame_info.r[reg_save_ar_lc]
2886 = find_gr_spill (reg_save_ar_lc, spill_size == 0);
2887 if (current_frame_info.r[reg_save_ar_lc] == 0)
2888 {
2889 extra_spill_size += 8;
2890 n_spilled += 1;
2891 }
2892 }
2893
2894 /* If we have an odd number of words of pretend arguments written to
2895 the stack, then the FR save area will be unaligned. We round the
2896 size of this area up to keep things 16 byte aligned. */
2897 if (spilled_fr_p)
2898 pretend_args_size = IA64_STACK_ALIGN (crtl->args.pretend_args_size);
2899 else
2900 pretend_args_size = crtl->args.pretend_args_size;
2901
2902 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2903 + crtl->outgoing_args_size);
2904 total_size = IA64_STACK_ALIGN (total_size);
2905
2906 /* We always use the 16-byte scratch area provided by the caller, but
2907 if we are a leaf function, there's no one to which we need to provide
2908 a scratch area. However, if the function allocates dynamic stack space,
2909 the dynamic offset is computed early and contains STACK_POINTER_OFFSET,
2910 so we need to cope. */
2911 if (crtl->is_leaf && !cfun->calls_alloca)
2912 total_size = MAX (0, total_size - 16);
2913
2914 current_frame_info.total_size = total_size;
2915 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2916 current_frame_info.spill_size = spill_size;
2917 current_frame_info.extra_spill_size = extra_spill_size;
2918 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2919 current_frame_info.n_spilled = n_spilled;
2920 current_frame_info.initialized = reload_completed;
2921 }
2922
2923 /* Worker function for TARGET_CAN_ELIMINATE. */
2924
2925 bool
2926 ia64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
2927 {
2928 return (to == BR_REG (0) ? crtl->is_leaf : true);
2929 }
2930
2931 /* Compute the initial difference between the specified pair of registers. */
2932
2933 HOST_WIDE_INT
2934 ia64_initial_elimination_offset (int from, int to)
2935 {
2936 HOST_WIDE_INT offset;
2937
2938 ia64_compute_frame_size (get_frame_size ());
2939 switch (from)
2940 {
2941 case FRAME_POINTER_REGNUM:
2942 switch (to)
2943 {
2944 case HARD_FRAME_POINTER_REGNUM:
2945 offset = -current_frame_info.total_size;
2946 if (!crtl->is_leaf || cfun->calls_alloca)
2947 offset += 16 + crtl->outgoing_args_size;
2948 break;
2949
2950 case STACK_POINTER_REGNUM:
2951 offset = 0;
2952 if (!crtl->is_leaf || cfun->calls_alloca)
2953 offset += 16 + crtl->outgoing_args_size;
2954 break;
2955
2956 default:
2957 gcc_unreachable ();
2958 }
2959 break;
2960
2961 case ARG_POINTER_REGNUM:
2962 /* Arguments start above the 16 byte save area, unless stdarg
2963 in which case we store through the 16 byte save area. */
2964 switch (to)
2965 {
2966 case HARD_FRAME_POINTER_REGNUM:
2967 offset = 16 - crtl->args.pretend_args_size;
2968 break;
2969
2970 case STACK_POINTER_REGNUM:
2971 offset = (current_frame_info.total_size
2972 + 16 - crtl->args.pretend_args_size);
2973 break;
2974
2975 default:
2976 gcc_unreachable ();
2977 }
2978 break;
2979
2980 default:
2981 gcc_unreachable ();
2982 }
2983
2984 return offset;
2985 }
2986
2987 /* If there are more than a trivial number of register spills, we use
2988 two interleaved iterators so that we can get two memory references
2989 per insn group.
2990
2991 In order to simplify things in the prologue and epilogue expanders,
2992 we use helper functions to fix up the memory references after the
2993 fact with the appropriate offsets to a POST_MODIFY memory mode.
2994 The following data structure tracks the state of the two iterators
2995 while insns are being emitted. */
2996
2997 struct spill_fill_data
2998 {
2999 rtx_insn *init_after; /* point at which to emit initializations */
3000 rtx init_reg[2]; /* initial base register */
3001 rtx iter_reg[2]; /* the iterator registers */
3002 rtx *prev_addr[2]; /* address of last memory use */
3003 rtx_insn *prev_insn[2]; /* the insn corresponding to prev_addr */
3004 HOST_WIDE_INT prev_off[2]; /* last offset */
3005 int n_iter; /* number of iterators in use */
3006 int next_iter; /* next iterator to use */
3007 unsigned int save_gr_used_mask;
3008 };
3009
3010 static struct spill_fill_data spill_fill_data;
3011
3012 static void
3013 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
3014 {
3015 int i;
3016
3017 spill_fill_data.init_after = get_last_insn ();
3018 spill_fill_data.init_reg[0] = init_reg;
3019 spill_fill_data.init_reg[1] = init_reg;
3020 spill_fill_data.prev_addr[0] = NULL;
3021 spill_fill_data.prev_addr[1] = NULL;
3022 spill_fill_data.prev_insn[0] = NULL;
3023 spill_fill_data.prev_insn[1] = NULL;
3024 spill_fill_data.prev_off[0] = cfa_off;
3025 spill_fill_data.prev_off[1] = cfa_off;
3026 spill_fill_data.next_iter = 0;
3027 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
3028
3029 spill_fill_data.n_iter = 1 + (n_spills > 2);
3030 for (i = 0; i < spill_fill_data.n_iter; ++i)
3031 {
3032 int regno = next_scratch_gr_reg ();
3033 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
3034 current_frame_info.gr_used_mask |= 1 << regno;
3035 }
3036 }
3037
3038 static void
3039 finish_spill_pointers (void)
3040 {
3041 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
3042 }
3043
3044 static rtx
3045 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
3046 {
3047 int iter = spill_fill_data.next_iter;
3048 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
3049 rtx disp_rtx = GEN_INT (disp);
3050 rtx mem;
3051
3052 if (spill_fill_data.prev_addr[iter])
3053 {
3054 if (satisfies_constraint_N (disp_rtx))
3055 {
3056 *spill_fill_data.prev_addr[iter]
3057 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
3058 gen_rtx_PLUS (DImode,
3059 spill_fill_data.iter_reg[iter],
3060 disp_rtx));
3061 add_reg_note (spill_fill_data.prev_insn[iter],
3062 REG_INC, spill_fill_data.iter_reg[iter]);
3063 }
3064 else
3065 {
3066 /* ??? Could use register post_modify for loads. */
3067 if (!satisfies_constraint_I (disp_rtx))
3068 {
3069 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3070 emit_move_insn (tmp, disp_rtx);
3071 disp_rtx = tmp;
3072 }
3073 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
3074 spill_fill_data.iter_reg[iter], disp_rtx));
3075 }
3076 }
3077 /* Micro-optimization: if we've created a frame pointer, it's at
3078 CFA 0, which may allow the real iterator to be initialized lower,
3079 slightly increasing parallelism. Also, if there are few saves
3080 it may eliminate the iterator entirely. */
3081 else if (disp == 0
3082 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
3083 && frame_pointer_needed)
3084 {
3085 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
3086 set_mem_alias_set (mem, get_varargs_alias_set ());
3087 return mem;
3088 }
3089 else
3090 {
3091 rtx seq;
3092 rtx_insn *insn;
3093
3094 if (disp == 0)
3095 seq = gen_movdi (spill_fill_data.iter_reg[iter],
3096 spill_fill_data.init_reg[iter]);
3097 else
3098 {
3099 start_sequence ();
3100
3101 if (!satisfies_constraint_I (disp_rtx))
3102 {
3103 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3104 emit_move_insn (tmp, disp_rtx);
3105 disp_rtx = tmp;
3106 }
3107
3108 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
3109 spill_fill_data.init_reg[iter],
3110 disp_rtx));
3111
3112 seq = get_insns ();
3113 end_sequence ();
3114 }
3115
3116 /* Careful for being the first insn in a sequence. */
3117 if (spill_fill_data.init_after)
3118 insn = emit_insn_after (seq, spill_fill_data.init_after);
3119 else
3120 {
3121 rtx_insn *first = get_insns ();
3122 if (first)
3123 insn = emit_insn_before (seq, first);
3124 else
3125 insn = emit_insn (seq);
3126 }
3127 spill_fill_data.init_after = insn;
3128 }
3129
3130 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
3131
3132 /* ??? Not all of the spills are for varargs, but some of them are.
3133 The rest of the spills belong in an alias set of their own. But
3134 it doesn't actually hurt to include them here. */
3135 set_mem_alias_set (mem, get_varargs_alias_set ());
3136
3137 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
3138 spill_fill_data.prev_off[iter] = cfa_off;
3139
3140 if (++iter >= spill_fill_data.n_iter)
3141 iter = 0;
3142 spill_fill_data.next_iter = iter;
3143
3144 return mem;
3145 }
3146
3147 static void
3148 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
3149 rtx frame_reg)
3150 {
3151 int iter = spill_fill_data.next_iter;
3152 rtx mem;
3153 rtx_insn *insn;
3154
3155 mem = spill_restore_mem (reg, cfa_off);
3156 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
3157 spill_fill_data.prev_insn[iter] = insn;
3158
3159 if (frame_reg)
3160 {
3161 rtx base;
3162 HOST_WIDE_INT off;
3163
3164 RTX_FRAME_RELATED_P (insn) = 1;
3165
3166 /* Don't even pretend that the unwind code can intuit its way
3167 through a pair of interleaved post_modify iterators. Just
3168 provide the correct answer. */
3169
3170 if (frame_pointer_needed)
3171 {
3172 base = hard_frame_pointer_rtx;
3173 off = - cfa_off;
3174 }
3175 else
3176 {
3177 base = stack_pointer_rtx;
3178 off = current_frame_info.total_size - cfa_off;
3179 }
3180
3181 add_reg_note (insn, REG_CFA_OFFSET,
3182 gen_rtx_SET (VOIDmode,
3183 gen_rtx_MEM (GET_MODE (reg),
3184 plus_constant (Pmode,
3185 base, off)),
3186 frame_reg));
3187 }
3188 }
3189
3190 static void
3191 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
3192 {
3193 int iter = spill_fill_data.next_iter;
3194 rtx_insn *insn;
3195
3196 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
3197 GEN_INT (cfa_off)));
3198 spill_fill_data.prev_insn[iter] = insn;
3199 }
3200
3201 /* Wrapper functions that discards the CONST_INT spill offset. These
3202 exist so that we can give gr_spill/gr_fill the offset they need and
3203 use a consistent function interface. */
3204
3205 static rtx
3206 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3207 {
3208 return gen_movdi (dest, src);
3209 }
3210
3211 static rtx
3212 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3213 {
3214 return gen_fr_spill (dest, src);
3215 }
3216
3217 static rtx
3218 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3219 {
3220 return gen_fr_restore (dest, src);
3221 }
3222
3223 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
3224
3225 /* See Table 6.2 of the IA-64 Software Developer Manual, Volume 2. */
3226 #define BACKING_STORE_SIZE(N) ((N) > 0 ? ((N) + (N)/63 + 1) * 8 : 0)
3227
3228 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
3229 inclusive. These are offsets from the current stack pointer. BS_SIZE
3230 is the size of the backing store. ??? This clobbers r2 and r3. */
3231
3232 static void
3233 ia64_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size,
3234 int bs_size)
3235 {
3236 rtx r2 = gen_rtx_REG (Pmode, GR_REG (2));
3237 rtx r3 = gen_rtx_REG (Pmode, GR_REG (3));
3238 rtx p6 = gen_rtx_REG (BImode, PR_REG (6));
3239
3240 /* On the IA-64 there is a second stack in memory, namely the Backing Store
3241 of the Register Stack Engine. We also need to probe it after checking
3242 that the 2 stacks don't overlap. */
3243 emit_insn (gen_bsp_value (r3));
3244 emit_move_insn (r2, GEN_INT (-(first + size)));
3245
3246 /* Compare current value of BSP and SP registers. */
3247 emit_insn (gen_rtx_SET (VOIDmode, p6,
3248 gen_rtx_fmt_ee (LTU, BImode,
3249 r3, stack_pointer_rtx)));
3250
3251 /* Compute the address of the probe for the Backing Store (which grows
3252 towards higher addresses). We probe only at the first offset of
3253 the next page because some OS (eg Linux/ia64) only extend the
3254 backing store when this specific address is hit (but generate a SEGV
3255 on other address). Page size is the worst case (4KB). The reserve
3256 size is at least 4096 - (96 + 2) * 8 = 3312 bytes, which is enough.
3257 Also compute the address of the last probe for the memory stack
3258 (which grows towards lower addresses). */
3259 emit_insn (gen_rtx_SET (VOIDmode, r3, plus_constant (Pmode, r3, 4095)));
3260 emit_insn (gen_rtx_SET (VOIDmode, r2,
3261 gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2)));
3262
3263 /* Compare them and raise SEGV if the former has topped the latter. */
3264 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
3265 gen_rtx_fmt_ee (NE, VOIDmode, p6, const0_rtx),
3266 gen_rtx_SET (VOIDmode, p6,
3267 gen_rtx_fmt_ee (GEU, BImode,
3268 r3, r2))));
3269 emit_insn (gen_rtx_SET (VOIDmode,
3270 gen_rtx_ZERO_EXTRACT (DImode, r3, GEN_INT (12),
3271 const0_rtx),
3272 const0_rtx));
3273 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
3274 gen_rtx_fmt_ee (NE, VOIDmode, p6, const0_rtx),
3275 gen_rtx_TRAP_IF (VOIDmode, const1_rtx,
3276 GEN_INT (11))));
3277
3278 /* Probe the Backing Store if necessary. */
3279 if (bs_size > 0)
3280 emit_stack_probe (r3);
3281
3282 /* Probe the memory stack if necessary. */
3283 if (size == 0)
3284 ;
3285
3286 /* See if we have a constant small number of probes to generate. If so,
3287 that's the easy case. */
3288 else if (size <= PROBE_INTERVAL)
3289 emit_stack_probe (r2);
3290
3291 /* The run-time loop is made up of 8 insns in the generic case while this
3292 compile-time loop is made up of 5+2*(n-2) insns for n # of intervals. */
3293 else if (size <= 4 * PROBE_INTERVAL)
3294 {
3295 HOST_WIDE_INT i;
3296
3297 emit_move_insn (r2, GEN_INT (-(first + PROBE_INTERVAL)));
3298 emit_insn (gen_rtx_SET (VOIDmode, r2,
3299 gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2)));
3300 emit_stack_probe (r2);
3301
3302 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
3303 it exceeds SIZE. If only two probes are needed, this will not
3304 generate any code. Then probe at FIRST + SIZE. */
3305 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
3306 {
3307 emit_insn (gen_rtx_SET (VOIDmode, r2,
3308 plus_constant (Pmode, r2, -PROBE_INTERVAL)));
3309 emit_stack_probe (r2);
3310 }
3311
3312 emit_insn (gen_rtx_SET (VOIDmode, r2,
3313 plus_constant (Pmode, r2,
3314 (i - PROBE_INTERVAL) - size)));
3315 emit_stack_probe (r2);
3316 }
3317
3318 /* Otherwise, do the same as above, but in a loop. Note that we must be
3319 extra careful with variables wrapping around because we might be at
3320 the very top (or the very bottom) of the address space and we have
3321 to be able to handle this case properly; in particular, we use an
3322 equality test for the loop condition. */
3323 else
3324 {
3325 HOST_WIDE_INT rounded_size;
3326
3327 emit_move_insn (r2, GEN_INT (-first));
3328
3329
3330 /* Step 1: round SIZE to the previous multiple of the interval. */
3331
3332 rounded_size = size & -PROBE_INTERVAL;
3333
3334
3335 /* Step 2: compute initial and final value of the loop counter. */
3336
3337 /* TEST_ADDR = SP + FIRST. */
3338 emit_insn (gen_rtx_SET (VOIDmode, r2,
3339 gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2)));
3340
3341 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
3342 if (rounded_size > (1 << 21))
3343 {
3344 emit_move_insn (r3, GEN_INT (-rounded_size));
3345 emit_insn (gen_rtx_SET (VOIDmode, r3, gen_rtx_PLUS (Pmode, r2, r3)));
3346 }
3347 else
3348 emit_insn (gen_rtx_SET (VOIDmode, r3,
3349 gen_rtx_PLUS (Pmode, r2,
3350 GEN_INT (-rounded_size))));
3351
3352
3353 /* Step 3: the loop
3354
3355 while (TEST_ADDR != LAST_ADDR)
3356 {
3357 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
3358 probe at TEST_ADDR
3359 }
3360
3361 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
3362 until it is equal to ROUNDED_SIZE. */
3363
3364 emit_insn (gen_probe_stack_range (r2, r2, r3));
3365
3366
3367 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
3368 that SIZE is equal to ROUNDED_SIZE. */
3369
3370 /* TEMP = SIZE - ROUNDED_SIZE. */
3371 if (size != rounded_size)
3372 {
3373 emit_insn (gen_rtx_SET (VOIDmode, r2,
3374 plus_constant (Pmode, r2,
3375 rounded_size - size)));
3376 emit_stack_probe (r2);
3377 }
3378 }
3379
3380 /* Make sure nothing is scheduled before we are done. */
3381 emit_insn (gen_blockage ());
3382 }
3383
3384 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
3385 absolute addresses. */
3386
3387 const char *
3388 output_probe_stack_range (rtx reg1, rtx reg2)
3389 {
3390 static int labelno = 0;
3391 char loop_lab[32], end_lab[32];
3392 rtx xops[3];
3393
3394 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
3395 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
3396
3397 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
3398
3399 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
3400 xops[0] = reg1;
3401 xops[1] = reg2;
3402 xops[2] = gen_rtx_REG (BImode, PR_REG (6));
3403 output_asm_insn ("cmp.eq %2, %I2 = %0, %1", xops);
3404 fprintf (asm_out_file, "\t(%s) br.cond.dpnt ", reg_names [REGNO (xops[2])]);
3405 assemble_name_raw (asm_out_file, end_lab);
3406 fputc ('\n', asm_out_file);
3407
3408 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
3409 xops[1] = GEN_INT (-PROBE_INTERVAL);
3410 output_asm_insn ("addl %0 = %1, %0", xops);
3411 fputs ("\t;;\n", asm_out_file);
3412
3413 /* Probe at TEST_ADDR and branch. */
3414 output_asm_insn ("probe.w.fault %0, 0", xops);
3415 fprintf (asm_out_file, "\tbr ");
3416 assemble_name_raw (asm_out_file, loop_lab);
3417 fputc ('\n', asm_out_file);
3418
3419 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
3420
3421 return "";
3422 }
3423
3424 /* Called after register allocation to add any instructions needed for the
3425 prologue. Using a prologue insn is favored compared to putting all of the
3426 instructions in output_function_prologue(), since it allows the scheduler
3427 to intermix instructions with the saves of the caller saved registers. In
3428 some cases, it might be necessary to emit a barrier instruction as the last
3429 insn to prevent such scheduling.
3430
3431 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
3432 so that the debug info generation code can handle them properly.
3433
3434 The register save area is laid out like so:
3435 cfa+16
3436 [ varargs spill area ]
3437 [ fr register spill area ]
3438 [ br register spill area ]
3439 [ ar register spill area ]
3440 [ pr register spill area ]
3441 [ gr register spill area ] */
3442
3443 /* ??? Get inefficient code when the frame size is larger than can fit in an
3444 adds instruction. */
3445
3446 void
3447 ia64_expand_prologue (void)
3448 {
3449 rtx_insn *insn;
3450 rtx ar_pfs_save_reg, ar_unat_save_reg;
3451 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
3452 rtx reg, alt_reg;
3453
3454 ia64_compute_frame_size (get_frame_size ());
3455 last_scratch_gr_reg = 15;
3456
3457 if (flag_stack_usage_info)
3458 current_function_static_stack_size = current_frame_info.total_size;
3459
3460 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
3461 {
3462 HOST_WIDE_INT size = current_frame_info.total_size;
3463 int bs_size = BACKING_STORE_SIZE (current_frame_info.n_input_regs
3464 + current_frame_info.n_local_regs);
3465
3466 if (crtl->is_leaf && !cfun->calls_alloca)
3467 {
3468 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
3469 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT,
3470 size - STACK_CHECK_PROTECT,
3471 bs_size);
3472 else if (size + bs_size > STACK_CHECK_PROTECT)
3473 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT, 0, bs_size);
3474 }
3475 else if (size + bs_size > 0)
3476 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT, size, bs_size);
3477 }
3478
3479 if (dump_file)
3480 {
3481 fprintf (dump_file, "ia64 frame related registers "
3482 "recorded in current_frame_info.r[]:\n");
3483 #define PRINTREG(a) if (current_frame_info.r[a]) \
3484 fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a])
3485 PRINTREG(reg_fp);
3486 PRINTREG(reg_save_b0);
3487 PRINTREG(reg_save_pr);
3488 PRINTREG(reg_save_ar_pfs);
3489 PRINTREG(reg_save_ar_unat);
3490 PRINTREG(reg_save_ar_lc);
3491 PRINTREG(reg_save_gp);
3492 #undef PRINTREG
3493 }
3494
3495 /* If there is no epilogue, then we don't need some prologue insns.
3496 We need to avoid emitting the dead prologue insns, because flow
3497 will complain about them. */
3498 if (optimize)
3499 {
3500 edge e;
3501 edge_iterator ei;
3502
3503 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds)
3504 if ((e->flags & EDGE_FAKE) == 0
3505 && (e->flags & EDGE_FALLTHRU) != 0)
3506 break;
3507 epilogue_p = (e != NULL);
3508 }
3509 else
3510 epilogue_p = 1;
3511
3512 /* Set the local, input, and output register names. We need to do this
3513 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3514 half. If we use in/loc/out register names, then we get assembler errors
3515 in crtn.S because there is no alloc insn or regstk directive in there. */
3516 if (! TARGET_REG_NAMES)
3517 {
3518 int inputs = current_frame_info.n_input_regs;
3519 int locals = current_frame_info.n_local_regs;
3520 int outputs = current_frame_info.n_output_regs;
3521
3522 for (i = 0; i < inputs; i++)
3523 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
3524 for (i = 0; i < locals; i++)
3525 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
3526 for (i = 0; i < outputs; i++)
3527 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
3528 }
3529
3530 /* Set the frame pointer register name. The regnum is logically loc79,
3531 but of course we'll not have allocated that many locals. Rather than
3532 worrying about renumbering the existing rtxs, we adjust the name. */
3533 /* ??? This code means that we can never use one local register when
3534 there is a frame pointer. loc79 gets wasted in this case, as it is
3535 renamed to a register that will never be used. See also the try_locals
3536 code in find_gr_spill. */
3537 if (current_frame_info.r[reg_fp])
3538 {
3539 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3540 reg_names[HARD_FRAME_POINTER_REGNUM]
3541 = reg_names[current_frame_info.r[reg_fp]];
3542 reg_names[current_frame_info.r[reg_fp]] = tmp;
3543 }
3544
3545 /* We don't need an alloc instruction if we've used no outputs or locals. */
3546 if (current_frame_info.n_local_regs == 0
3547 && current_frame_info.n_output_regs == 0
3548 && current_frame_info.n_input_regs <= crtl->args.info.int_regs
3549 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3550 {
3551 /* If there is no alloc, but there are input registers used, then we
3552 need a .regstk directive. */
3553 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
3554 ar_pfs_save_reg = NULL_RTX;
3555 }
3556 else
3557 {
3558 current_frame_info.need_regstk = 0;
3559
3560 if (current_frame_info.r[reg_save_ar_pfs])
3561 {
3562 regno = current_frame_info.r[reg_save_ar_pfs];
3563 reg_emitted (reg_save_ar_pfs);
3564 }
3565 else
3566 regno = next_scratch_gr_reg ();
3567 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
3568
3569 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
3570 GEN_INT (current_frame_info.n_input_regs),
3571 GEN_INT (current_frame_info.n_local_regs),
3572 GEN_INT (current_frame_info.n_output_regs),
3573 GEN_INT (current_frame_info.n_rotate_regs)));
3574 if (current_frame_info.r[reg_save_ar_pfs])
3575 {
3576 RTX_FRAME_RELATED_P (insn) = 1;
3577 add_reg_note (insn, REG_CFA_REGISTER,
3578 gen_rtx_SET (VOIDmode,
3579 ar_pfs_save_reg,
3580 gen_rtx_REG (DImode, AR_PFS_REGNUM)));
3581 }
3582 }
3583
3584 /* Set up frame pointer, stack pointer, and spill iterators. */
3585
3586 n_varargs = cfun->machine->n_varargs;
3587 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
3588 stack_pointer_rtx, 0);
3589
3590 if (frame_pointer_needed)
3591 {
3592 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3593 RTX_FRAME_RELATED_P (insn) = 1;
3594
3595 /* Force the unwind info to recognize this as defining a new CFA,
3596 rather than some temp register setup. */
3597 add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL_RTX);
3598 }
3599
3600 if (current_frame_info.total_size != 0)
3601 {
3602 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
3603 rtx offset;
3604
3605 if (satisfies_constraint_I (frame_size_rtx))
3606 offset = frame_size_rtx;
3607 else
3608 {
3609 regno = next_scratch_gr_reg ();
3610 offset = gen_rtx_REG (DImode, regno);
3611 emit_move_insn (offset, frame_size_rtx);
3612 }
3613
3614 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
3615 stack_pointer_rtx, offset));
3616
3617 if (! frame_pointer_needed)
3618 {
3619 RTX_FRAME_RELATED_P (insn) = 1;
3620 add_reg_note (insn, REG_CFA_ADJUST_CFA,
3621 gen_rtx_SET (VOIDmode,
3622 stack_pointer_rtx,
3623 gen_rtx_PLUS (DImode,
3624 stack_pointer_rtx,
3625 frame_size_rtx)));
3626 }
3627
3628 /* ??? At this point we must generate a magic insn that appears to
3629 modify the stack pointer, the frame pointer, and all spill
3630 iterators. This would allow the most scheduling freedom. For
3631 now, just hard stop. */
3632 emit_insn (gen_blockage ());
3633 }
3634
3635 /* Must copy out ar.unat before doing any integer spills. */
3636 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3637 {
3638 if (current_frame_info.r[reg_save_ar_unat])
3639 {
3640 ar_unat_save_reg
3641 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3642 reg_emitted (reg_save_ar_unat);
3643 }
3644 else
3645 {
3646 alt_regno = next_scratch_gr_reg ();
3647 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3648 current_frame_info.gr_used_mask |= 1 << alt_regno;
3649 }
3650
3651 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3652 insn = emit_move_insn (ar_unat_save_reg, reg);
3653 if (current_frame_info.r[reg_save_ar_unat])
3654 {
3655 RTX_FRAME_RELATED_P (insn) = 1;
3656 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3657 }
3658
3659 /* Even if we're not going to generate an epilogue, we still
3660 need to save the register so that EH works. */
3661 if (! epilogue_p && current_frame_info.r[reg_save_ar_unat])
3662 emit_insn (gen_prologue_use (ar_unat_save_reg));
3663 }
3664 else
3665 ar_unat_save_reg = NULL_RTX;
3666
3667 /* Spill all varargs registers. Do this before spilling any GR registers,
3668 since we want the UNAT bits for the GR registers to override the UNAT
3669 bits from varargs, which we don't care about. */
3670
3671 cfa_off = -16;
3672 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
3673 {
3674 reg = gen_rtx_REG (DImode, regno);
3675 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
3676 }
3677
3678 /* Locate the bottom of the register save area. */
3679 cfa_off = (current_frame_info.spill_cfa_off
3680 + current_frame_info.spill_size
3681 + current_frame_info.extra_spill_size);
3682
3683 /* Save the predicate register block either in a register or in memory. */
3684 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3685 {
3686 reg = gen_rtx_REG (DImode, PR_REG (0));
3687 if (current_frame_info.r[reg_save_pr] != 0)
3688 {
3689 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3690 reg_emitted (reg_save_pr);
3691 insn = emit_move_insn (alt_reg, reg);
3692
3693 /* ??? Denote pr spill/fill by a DImode move that modifies all
3694 64 hard registers. */
3695 RTX_FRAME_RELATED_P (insn) = 1;
3696 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3697
3698 /* Even if we're not going to generate an epilogue, we still
3699 need to save the register so that EH works. */
3700 if (! epilogue_p)
3701 emit_insn (gen_prologue_use (alt_reg));
3702 }
3703 else
3704 {
3705 alt_regno = next_scratch_gr_reg ();
3706 alt_reg = gen_rtx_REG (DImode, alt_regno);
3707 insn = emit_move_insn (alt_reg, reg);
3708 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3709 cfa_off -= 8;
3710 }
3711 }
3712
3713 /* Handle AR regs in numerical order. All of them get special handling. */
3714 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
3715 && current_frame_info.r[reg_save_ar_unat] == 0)
3716 {
3717 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3718 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
3719 cfa_off -= 8;
3720 }
3721
3722 /* The alloc insn already copied ar.pfs into a general register. The
3723 only thing we have to do now is copy that register to a stack slot
3724 if we'd not allocated a local register for the job. */
3725 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
3726 && current_frame_info.r[reg_save_ar_pfs] == 0)
3727 {
3728 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3729 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
3730 cfa_off -= 8;
3731 }
3732
3733 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3734 {
3735 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3736 if (current_frame_info.r[reg_save_ar_lc] != 0)
3737 {
3738 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3739 reg_emitted (reg_save_ar_lc);
3740 insn = emit_move_insn (alt_reg, reg);
3741 RTX_FRAME_RELATED_P (insn) = 1;
3742 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3743
3744 /* Even if we're not going to generate an epilogue, we still
3745 need to save the register so that EH works. */
3746 if (! epilogue_p)
3747 emit_insn (gen_prologue_use (alt_reg));
3748 }
3749 else
3750 {
3751 alt_regno = next_scratch_gr_reg ();
3752 alt_reg = gen_rtx_REG (DImode, alt_regno);
3753 emit_move_insn (alt_reg, reg);
3754 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3755 cfa_off -= 8;
3756 }
3757 }
3758
3759 /* Save the return pointer. */
3760 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3761 {
3762 reg = gen_rtx_REG (DImode, BR_REG (0));
3763 if (current_frame_info.r[reg_save_b0] != 0)
3764 {
3765 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3766 reg_emitted (reg_save_b0);
3767 insn = emit_move_insn (alt_reg, reg);
3768 RTX_FRAME_RELATED_P (insn) = 1;
3769 add_reg_note (insn, REG_CFA_REGISTER,
3770 gen_rtx_SET (VOIDmode, alt_reg, pc_rtx));
3771
3772 /* Even if we're not going to generate an epilogue, we still
3773 need to save the register so that EH works. */
3774 if (! epilogue_p)
3775 emit_insn (gen_prologue_use (alt_reg));
3776 }
3777 else
3778 {
3779 alt_regno = next_scratch_gr_reg ();
3780 alt_reg = gen_rtx_REG (DImode, alt_regno);
3781 emit_move_insn (alt_reg, reg);
3782 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3783 cfa_off -= 8;
3784 }
3785 }
3786
3787 if (current_frame_info.r[reg_save_gp])
3788 {
3789 reg_emitted (reg_save_gp);
3790 insn = emit_move_insn (gen_rtx_REG (DImode,
3791 current_frame_info.r[reg_save_gp]),
3792 pic_offset_table_rtx);
3793 }
3794
3795 /* We should now be at the base of the gr/br/fr spill area. */
3796 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3797 + current_frame_info.spill_size));
3798
3799 /* Spill all general registers. */
3800 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3801 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3802 {
3803 reg = gen_rtx_REG (DImode, regno);
3804 do_spill (gen_gr_spill, reg, cfa_off, reg);
3805 cfa_off -= 8;
3806 }
3807
3808 /* Spill the rest of the BR registers. */
3809 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3810 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3811 {
3812 alt_regno = next_scratch_gr_reg ();
3813 alt_reg = gen_rtx_REG (DImode, alt_regno);
3814 reg = gen_rtx_REG (DImode, regno);
3815 emit_move_insn (alt_reg, reg);
3816 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3817 cfa_off -= 8;
3818 }
3819
3820 /* Align the frame and spill all FR registers. */
3821 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3822 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3823 {
3824 gcc_assert (!(cfa_off & 15));
3825 reg = gen_rtx_REG (XFmode, regno);
3826 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
3827 cfa_off -= 16;
3828 }
3829
3830 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3831
3832 finish_spill_pointers ();
3833 }
3834
3835 /* Output the textual info surrounding the prologue. */
3836
3837 void
3838 ia64_start_function (FILE *file, const char *fnname,
3839 tree decl ATTRIBUTE_UNUSED)
3840 {
3841 #if TARGET_ABI_OPEN_VMS
3842 vms_start_function (fnname);
3843 #endif
3844
3845 fputs ("\t.proc ", file);
3846 assemble_name (file, fnname);
3847 fputc ('\n', file);
3848 ASM_OUTPUT_LABEL (file, fnname);
3849 }
3850
3851 /* Called after register allocation to add any instructions needed for the
3852 epilogue. Using an epilogue insn is favored compared to putting all of the
3853 instructions in output_function_prologue(), since it allows the scheduler
3854 to intermix instructions with the saves of the caller saved registers. In
3855 some cases, it might be necessary to emit a barrier instruction as the last
3856 insn to prevent such scheduling. */
3857
3858 void
3859 ia64_expand_epilogue (int sibcall_p)
3860 {
3861 rtx_insn *insn;
3862 rtx reg, alt_reg, ar_unat_save_reg;
3863 int regno, alt_regno, cfa_off;
3864
3865 ia64_compute_frame_size (get_frame_size ());
3866
3867 /* If there is a frame pointer, then we use it instead of the stack
3868 pointer, so that the stack pointer does not need to be valid when
3869 the epilogue starts. See EXIT_IGNORE_STACK. */
3870 if (frame_pointer_needed)
3871 setup_spill_pointers (current_frame_info.n_spilled,
3872 hard_frame_pointer_rtx, 0);
3873 else
3874 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
3875 current_frame_info.total_size);
3876
3877 if (current_frame_info.total_size != 0)
3878 {
3879 /* ??? At this point we must generate a magic insn that appears to
3880 modify the spill iterators and the frame pointer. This would
3881 allow the most scheduling freedom. For now, just hard stop. */
3882 emit_insn (gen_blockage ());
3883 }
3884
3885 /* Locate the bottom of the register save area. */
3886 cfa_off = (current_frame_info.spill_cfa_off
3887 + current_frame_info.spill_size
3888 + current_frame_info.extra_spill_size);
3889
3890 /* Restore the predicate registers. */
3891 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3892 {
3893 if (current_frame_info.r[reg_save_pr] != 0)
3894 {
3895 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3896 reg_emitted (reg_save_pr);
3897 }
3898 else
3899 {
3900 alt_regno = next_scratch_gr_reg ();
3901 alt_reg = gen_rtx_REG (DImode, alt_regno);
3902 do_restore (gen_movdi_x, alt_reg, cfa_off);
3903 cfa_off -= 8;
3904 }
3905 reg = gen_rtx_REG (DImode, PR_REG (0));
3906 emit_move_insn (reg, alt_reg);
3907 }
3908
3909 /* Restore the application registers. */
3910
3911 /* Load the saved unat from the stack, but do not restore it until
3912 after the GRs have been restored. */
3913 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3914 {
3915 if (current_frame_info.r[reg_save_ar_unat] != 0)
3916 {
3917 ar_unat_save_reg
3918 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3919 reg_emitted (reg_save_ar_unat);
3920 }
3921 else
3922 {
3923 alt_regno = next_scratch_gr_reg ();
3924 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3925 current_frame_info.gr_used_mask |= 1 << alt_regno;
3926 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3927 cfa_off -= 8;
3928 }
3929 }
3930 else
3931 ar_unat_save_reg = NULL_RTX;
3932
3933 if (current_frame_info.r[reg_save_ar_pfs] != 0)
3934 {
3935 reg_emitted (reg_save_ar_pfs);
3936 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]);
3937 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3938 emit_move_insn (reg, alt_reg);
3939 }
3940 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3941 {
3942 alt_regno = next_scratch_gr_reg ();
3943 alt_reg = gen_rtx_REG (DImode, alt_regno);
3944 do_restore (gen_movdi_x, alt_reg, cfa_off);
3945 cfa_off -= 8;
3946 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3947 emit_move_insn (reg, alt_reg);
3948 }
3949
3950 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3951 {
3952 if (current_frame_info.r[reg_save_ar_lc] != 0)
3953 {
3954 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3955 reg_emitted (reg_save_ar_lc);
3956 }
3957 else
3958 {
3959 alt_regno = next_scratch_gr_reg ();
3960 alt_reg = gen_rtx_REG (DImode, alt_regno);
3961 do_restore (gen_movdi_x, alt_reg, cfa_off);
3962 cfa_off -= 8;
3963 }
3964 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3965 emit_move_insn (reg, alt_reg);
3966 }
3967
3968 /* Restore the return pointer. */
3969 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3970 {
3971 if (current_frame_info.r[reg_save_b0] != 0)
3972 {
3973 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3974 reg_emitted (reg_save_b0);
3975 }
3976 else
3977 {
3978 alt_regno = next_scratch_gr_reg ();
3979 alt_reg = gen_rtx_REG (DImode, alt_regno);
3980 do_restore (gen_movdi_x, alt_reg, cfa_off);
3981 cfa_off -= 8;
3982 }
3983 reg = gen_rtx_REG (DImode, BR_REG (0));
3984 emit_move_insn (reg, alt_reg);
3985 }
3986
3987 /* We should now be at the base of the gr/br/fr spill area. */
3988 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3989 + current_frame_info.spill_size));
3990
3991 /* The GP may be stored on the stack in the prologue, but it's
3992 never restored in the epilogue. Skip the stack slot. */
3993 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3994 cfa_off -= 8;
3995
3996 /* Restore all general registers. */
3997 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3998 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3999 {
4000 reg = gen_rtx_REG (DImode, regno);
4001 do_restore (gen_gr_restore, reg, cfa_off);
4002 cfa_off -= 8;
4003 }
4004
4005 /* Restore the branch registers. */
4006 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
4007 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
4008 {
4009 alt_regno = next_scratch_gr_reg ();
4010 alt_reg = gen_rtx_REG (DImode, alt_regno);
4011 do_restore (gen_movdi_x, alt_reg, cfa_off);
4012 cfa_off -= 8;
4013 reg = gen_rtx_REG (DImode, regno);
4014 emit_move_insn (reg, alt_reg);
4015 }
4016
4017 /* Restore floating point registers. */
4018 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
4019 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
4020 {
4021 gcc_assert (!(cfa_off & 15));
4022 reg = gen_rtx_REG (XFmode, regno);
4023 do_restore (gen_fr_restore_x, reg, cfa_off);
4024 cfa_off -= 16;
4025 }
4026
4027 /* Restore ar.unat for real. */
4028 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
4029 {
4030 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
4031 emit_move_insn (reg, ar_unat_save_reg);
4032 }
4033
4034 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
4035
4036 finish_spill_pointers ();
4037
4038 if (current_frame_info.total_size
4039 || cfun->machine->ia64_eh_epilogue_sp
4040 || frame_pointer_needed)
4041 {
4042 /* ??? At this point we must generate a magic insn that appears to
4043 modify the spill iterators, the stack pointer, and the frame
4044 pointer. This would allow the most scheduling freedom. For now,
4045 just hard stop. */
4046 emit_insn (gen_blockage ());
4047 }
4048
4049 if (cfun->machine->ia64_eh_epilogue_sp)
4050 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
4051 else if (frame_pointer_needed)
4052 {
4053 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
4054 RTX_FRAME_RELATED_P (insn) = 1;
4055 add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL);
4056 }
4057 else if (current_frame_info.total_size)
4058 {
4059 rtx offset, frame_size_rtx;
4060
4061 frame_size_rtx = GEN_INT (current_frame_info.total_size);
4062 if (satisfies_constraint_I (frame_size_rtx))
4063 offset = frame_size_rtx;
4064 else
4065 {
4066 regno = next_scratch_gr_reg ();
4067 offset = gen_rtx_REG (DImode, regno);
4068 emit_move_insn (offset, frame_size_rtx);
4069 }
4070
4071 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
4072 offset));
4073
4074 RTX_FRAME_RELATED_P (insn) = 1;
4075 add_reg_note (insn, REG_CFA_ADJUST_CFA,
4076 gen_rtx_SET (VOIDmode,
4077 stack_pointer_rtx,
4078 gen_rtx_PLUS (DImode,
4079 stack_pointer_rtx,
4080 frame_size_rtx)));
4081 }
4082
4083 if (cfun->machine->ia64_eh_epilogue_bsp)
4084 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
4085
4086 if (! sibcall_p)
4087 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
4088 else
4089 {
4090 int fp = GR_REG (2);
4091 /* We need a throw away register here, r0 and r1 are reserved,
4092 so r2 is the first available call clobbered register. If
4093 there was a frame_pointer register, we may have swapped the
4094 names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make
4095 sure we're using the string "r2" when emitting the register
4096 name for the assembler. */
4097 if (current_frame_info.r[reg_fp]
4098 && current_frame_info.r[reg_fp] == GR_REG (2))
4099 fp = HARD_FRAME_POINTER_REGNUM;
4100
4101 /* We must emit an alloc to force the input registers to become output
4102 registers. Otherwise, if the callee tries to pass its parameters
4103 through to another call without an intervening alloc, then these
4104 values get lost. */
4105 /* ??? We don't need to preserve all input registers. We only need to
4106 preserve those input registers used as arguments to the sibling call.
4107 It is unclear how to compute that number here. */
4108 if (current_frame_info.n_input_regs != 0)
4109 {
4110 rtx n_inputs = GEN_INT (current_frame_info.n_input_regs);
4111
4112 insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
4113 const0_rtx, const0_rtx,
4114 n_inputs, const0_rtx));
4115 RTX_FRAME_RELATED_P (insn) = 1;
4116
4117 /* ??? We need to mark the alloc as frame-related so that it gets
4118 passed into ia64_asm_unwind_emit for ia64-specific unwinding.
4119 But there's nothing dwarf2 related to be done wrt the register
4120 windows. If we do nothing, dwarf2out will abort on the UNSPEC;
4121 the empty parallel means dwarf2out will not see anything. */
4122 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4123 gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (0)));
4124 }
4125 }
4126 }
4127
4128 /* Return 1 if br.ret can do all the work required to return from a
4129 function. */
4130
4131 int
4132 ia64_direct_return (void)
4133 {
4134 if (reload_completed && ! frame_pointer_needed)
4135 {
4136 ia64_compute_frame_size (get_frame_size ());
4137
4138 return (current_frame_info.total_size == 0
4139 && current_frame_info.n_spilled == 0
4140 && current_frame_info.r[reg_save_b0] == 0
4141 && current_frame_info.r[reg_save_pr] == 0
4142 && current_frame_info.r[reg_save_ar_pfs] == 0
4143 && current_frame_info.r[reg_save_ar_unat] == 0
4144 && current_frame_info.r[reg_save_ar_lc] == 0);
4145 }
4146 return 0;
4147 }
4148
4149 /* Return the magic cookie that we use to hold the return address
4150 during early compilation. */
4151
4152 rtx
4153 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
4154 {
4155 if (count != 0)
4156 return NULL;
4157 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
4158 }
4159
4160 /* Split this value after reload, now that we know where the return
4161 address is saved. */
4162
4163 void
4164 ia64_split_return_addr_rtx (rtx dest)
4165 {
4166 rtx src;
4167
4168 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
4169 {
4170 if (current_frame_info.r[reg_save_b0] != 0)
4171 {
4172 src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
4173 reg_emitted (reg_save_b0);
4174 }
4175 else
4176 {
4177 HOST_WIDE_INT off;
4178 unsigned int regno;
4179 rtx off_r;
4180
4181 /* Compute offset from CFA for BR0. */
4182 /* ??? Must be kept in sync with ia64_expand_prologue. */
4183 off = (current_frame_info.spill_cfa_off
4184 + current_frame_info.spill_size);
4185 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
4186 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
4187 off -= 8;
4188
4189 /* Convert CFA offset to a register based offset. */
4190 if (frame_pointer_needed)
4191 src = hard_frame_pointer_rtx;
4192 else
4193 {
4194 src = stack_pointer_rtx;
4195 off += current_frame_info.total_size;
4196 }
4197
4198 /* Load address into scratch register. */
4199 off_r = GEN_INT (off);
4200 if (satisfies_constraint_I (off_r))
4201 emit_insn (gen_adddi3 (dest, src, off_r));
4202 else
4203 {
4204 emit_move_insn (dest, off_r);
4205 emit_insn (gen_adddi3 (dest, src, dest));
4206 }
4207
4208 src = gen_rtx_MEM (Pmode, dest);
4209 }
4210 }
4211 else
4212 src = gen_rtx_REG (DImode, BR_REG (0));
4213
4214 emit_move_insn (dest, src);
4215 }
4216
4217 int
4218 ia64_hard_regno_rename_ok (int from, int to)
4219 {
4220 /* Don't clobber any of the registers we reserved for the prologue. */
4221 unsigned int r;
4222
4223 for (r = reg_fp; r <= reg_save_ar_lc; r++)
4224 if (to == current_frame_info.r[r]
4225 || from == current_frame_info.r[r]
4226 || to == emitted_frame_related_regs[r]
4227 || from == emitted_frame_related_regs[r])
4228 return 0;
4229
4230 /* Don't use output registers outside the register frame. */
4231 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
4232 return 0;
4233
4234 /* Retain even/oddness on predicate register pairs. */
4235 if (PR_REGNO_P (from) && PR_REGNO_P (to))
4236 return (from & 1) == (to & 1);
4237
4238 return 1;
4239 }
4240
4241 /* Target hook for assembling integer objects. Handle word-sized
4242 aligned objects and detect the cases when @fptr is needed. */
4243
4244 static bool
4245 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
4246 {
4247 if (size == POINTER_SIZE / BITS_PER_UNIT
4248 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
4249 && GET_CODE (x) == SYMBOL_REF
4250 && SYMBOL_REF_FUNCTION_P (x))
4251 {
4252 static const char * const directive[2][2] = {
4253 /* 64-bit pointer */ /* 32-bit pointer */
4254 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
4255 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
4256 };
4257 fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file);
4258 output_addr_const (asm_out_file, x);
4259 fputs (")\n", asm_out_file);
4260 return true;
4261 }
4262 return default_assemble_integer (x, size, aligned_p);
4263 }
4264
4265 /* Emit the function prologue. */
4266
4267 static void
4268 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4269 {
4270 int mask, grsave, grsave_prev;
4271
4272 if (current_frame_info.need_regstk)
4273 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
4274 current_frame_info.n_input_regs,
4275 current_frame_info.n_local_regs,
4276 current_frame_info.n_output_regs,
4277 current_frame_info.n_rotate_regs);
4278
4279 if (ia64_except_unwind_info (&global_options) != UI_TARGET)
4280 return;
4281
4282 /* Emit the .prologue directive. */
4283
4284 mask = 0;
4285 grsave = grsave_prev = 0;
4286 if (current_frame_info.r[reg_save_b0] != 0)
4287 {
4288 mask |= 8;
4289 grsave = grsave_prev = current_frame_info.r[reg_save_b0];
4290 }
4291 if (current_frame_info.r[reg_save_ar_pfs] != 0
4292 && (grsave_prev == 0
4293 || current_frame_info.r[reg_save_ar_pfs] == grsave_prev + 1))
4294 {
4295 mask |= 4;
4296 if (grsave_prev == 0)
4297 grsave = current_frame_info.r[reg_save_ar_pfs];
4298 grsave_prev = current_frame_info.r[reg_save_ar_pfs];
4299 }
4300 if (current_frame_info.r[reg_fp] != 0
4301 && (grsave_prev == 0
4302 || current_frame_info.r[reg_fp] == grsave_prev + 1))
4303 {
4304 mask |= 2;
4305 if (grsave_prev == 0)
4306 grsave = HARD_FRAME_POINTER_REGNUM;
4307 grsave_prev = current_frame_info.r[reg_fp];
4308 }
4309 if (current_frame_info.r[reg_save_pr] != 0
4310 && (grsave_prev == 0
4311 || current_frame_info.r[reg_save_pr] == grsave_prev + 1))
4312 {
4313 mask |= 1;
4314 if (grsave_prev == 0)
4315 grsave = current_frame_info.r[reg_save_pr];
4316 }
4317
4318 if (mask && TARGET_GNU_AS)
4319 fprintf (file, "\t.prologue %d, %d\n", mask,
4320 ia64_dbx_register_number (grsave));
4321 else
4322 fputs ("\t.prologue\n", file);
4323
4324 /* Emit a .spill directive, if necessary, to relocate the base of
4325 the register spill area. */
4326 if (current_frame_info.spill_cfa_off != -16)
4327 fprintf (file, "\t.spill %ld\n",
4328 (long) (current_frame_info.spill_cfa_off
4329 + current_frame_info.spill_size));
4330 }
4331
4332 /* Emit the .body directive at the scheduled end of the prologue. */
4333
4334 static void
4335 ia64_output_function_end_prologue (FILE *file)
4336 {
4337 if (ia64_except_unwind_info (&global_options) != UI_TARGET)
4338 return;
4339
4340 fputs ("\t.body\n", file);
4341 }
4342
4343 /* Emit the function epilogue. */
4344
4345 static void
4346 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
4347 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4348 {
4349 int i;
4350
4351 if (current_frame_info.r[reg_fp])
4352 {
4353 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
4354 reg_names[HARD_FRAME_POINTER_REGNUM]
4355 = reg_names[current_frame_info.r[reg_fp]];
4356 reg_names[current_frame_info.r[reg_fp]] = tmp;
4357 reg_emitted (reg_fp);
4358 }
4359 if (! TARGET_REG_NAMES)
4360 {
4361 for (i = 0; i < current_frame_info.n_input_regs; i++)
4362 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
4363 for (i = 0; i < current_frame_info.n_local_regs; i++)
4364 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
4365 for (i = 0; i < current_frame_info.n_output_regs; i++)
4366 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
4367 }
4368
4369 current_frame_info.initialized = 0;
4370 }
4371
4372 int
4373 ia64_dbx_register_number (int regno)
4374 {
4375 /* In ia64_expand_prologue we quite literally renamed the frame pointer
4376 from its home at loc79 to something inside the register frame. We
4377 must perform the same renumbering here for the debug info. */
4378 if (current_frame_info.r[reg_fp])
4379 {
4380 if (regno == HARD_FRAME_POINTER_REGNUM)
4381 regno = current_frame_info.r[reg_fp];
4382 else if (regno == current_frame_info.r[reg_fp])
4383 regno = HARD_FRAME_POINTER_REGNUM;
4384 }
4385
4386 if (IN_REGNO_P (regno))
4387 return 32 + regno - IN_REG (0);
4388 else if (LOC_REGNO_P (regno))
4389 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
4390 else if (OUT_REGNO_P (regno))
4391 return (32 + current_frame_info.n_input_regs
4392 + current_frame_info.n_local_regs + regno - OUT_REG (0));
4393 else
4394 return regno;
4395 }
4396
4397 /* Implement TARGET_TRAMPOLINE_INIT.
4398
4399 The trampoline should set the static chain pointer to value placed
4400 into the trampoline and should branch to the specified routine.
4401 To make the normal indirect-subroutine calling convention work,
4402 the trampoline must look like a function descriptor; the first
4403 word being the target address and the second being the target's
4404 global pointer.
4405
4406 We abuse the concept of a global pointer by arranging for it
4407 to point to the data we need to load. The complete trampoline
4408 has the following form:
4409
4410 +-------------------+ \
4411 TRAMP: | __ia64_trampoline | |
4412 +-------------------+ > fake function descriptor
4413 | TRAMP+16 | |
4414 +-------------------+ /
4415 | target descriptor |
4416 +-------------------+
4417 | static link |
4418 +-------------------+
4419 */
4420
4421 static void
4422 ia64_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
4423 {
4424 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
4425 rtx addr, addr_reg, tramp, eight = GEN_INT (8);
4426
4427 /* The Intel assembler requires that the global __ia64_trampoline symbol
4428 be declared explicitly */
4429 if (!TARGET_GNU_AS)
4430 {
4431 static bool declared_ia64_trampoline = false;
4432
4433 if (!declared_ia64_trampoline)
4434 {
4435 declared_ia64_trampoline = true;
4436 (*targetm.asm_out.globalize_label) (asm_out_file,
4437 "__ia64_trampoline");
4438 }
4439 }
4440
4441 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
4442 addr = convert_memory_address (Pmode, XEXP (m_tramp, 0));
4443 fnaddr = convert_memory_address (Pmode, fnaddr);
4444 static_chain = convert_memory_address (Pmode, static_chain);
4445
4446 /* Load up our iterator. */
4447 addr_reg = copy_to_reg (addr);
4448 m_tramp = adjust_automodify_address (m_tramp, Pmode, addr_reg, 0);
4449
4450 /* The first two words are the fake descriptor:
4451 __ia64_trampoline, ADDR+16. */
4452 tramp = gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline");
4453 if (TARGET_ABI_OPEN_VMS)
4454 {
4455 /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity
4456 in the Macro-32 compiler) and changed the semantics of the LTOFF22
4457 relocation against function symbols to make it identical to the
4458 LTOFF_FPTR22 relocation. Emit the latter directly to stay within
4459 strict ELF and dereference to get the bare code address. */
4460 rtx reg = gen_reg_rtx (Pmode);
4461 SYMBOL_REF_FLAGS (tramp) |= SYMBOL_FLAG_FUNCTION;
4462 emit_move_insn (reg, tramp);
4463 emit_move_insn (reg, gen_rtx_MEM (Pmode, reg));
4464 tramp = reg;
4465 }
4466 emit_move_insn (m_tramp, tramp);
4467 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4468 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4469
4470 emit_move_insn (m_tramp, force_reg (Pmode, plus_constant (Pmode, addr, 16)));
4471 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4472 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4473
4474 /* The third word is the target descriptor. */
4475 emit_move_insn (m_tramp, force_reg (Pmode, fnaddr));
4476 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4477 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4478
4479 /* The fourth word is the static chain. */
4480 emit_move_insn (m_tramp, static_chain);
4481 }
4482 \f
4483 /* Do any needed setup for a variadic function. CUM has not been updated
4484 for the last named argument which has type TYPE and mode MODE.
4485
4486 We generate the actual spill instructions during prologue generation. */
4487
4488 static void
4489 ia64_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
4490 tree type, int * pretend_size,
4491 int second_time ATTRIBUTE_UNUSED)
4492 {
4493 CUMULATIVE_ARGS next_cum = *get_cumulative_args (cum);
4494
4495 /* Skip the current argument. */
4496 ia64_function_arg_advance (pack_cumulative_args (&next_cum), mode, type, 1);
4497
4498 if (next_cum.words < MAX_ARGUMENT_SLOTS)
4499 {
4500 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
4501 *pretend_size = n * UNITS_PER_WORD;
4502 cfun->machine->n_varargs = n;
4503 }
4504 }
4505
4506 /* Check whether TYPE is a homogeneous floating point aggregate. If
4507 it is, return the mode of the floating point type that appears
4508 in all leafs. If it is not, return VOIDmode.
4509
4510 An aggregate is a homogeneous floating point aggregate is if all
4511 fields/elements in it have the same floating point type (e.g,
4512 SFmode). 128-bit quad-precision floats are excluded.
4513
4514 Variable sized aggregates should never arrive here, since we should
4515 have already decided to pass them by reference. Top-level zero-sized
4516 aggregates are excluded because our parallels crash the middle-end. */
4517
4518 static enum machine_mode
4519 hfa_element_mode (const_tree type, bool nested)
4520 {
4521 enum machine_mode element_mode = VOIDmode;
4522 enum machine_mode mode;
4523 enum tree_code code = TREE_CODE (type);
4524 int know_element_mode = 0;
4525 tree t;
4526
4527 if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type))))
4528 return VOIDmode;
4529
4530 switch (code)
4531 {
4532 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
4533 case BOOLEAN_TYPE: case POINTER_TYPE:
4534 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
4535 case LANG_TYPE: case FUNCTION_TYPE:
4536 return VOIDmode;
4537
4538 /* Fortran complex types are supposed to be HFAs, so we need to handle
4539 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
4540 types though. */
4541 case COMPLEX_TYPE:
4542 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
4543 && TYPE_MODE (type) != TCmode)
4544 return GET_MODE_INNER (TYPE_MODE (type));
4545 else
4546 return VOIDmode;
4547
4548 case REAL_TYPE:
4549 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
4550 mode if this is contained within an aggregate. */
4551 if (nested && TYPE_MODE (type) != TFmode)
4552 return TYPE_MODE (type);
4553 else
4554 return VOIDmode;
4555
4556 case ARRAY_TYPE:
4557 return hfa_element_mode (TREE_TYPE (type), 1);
4558
4559 case RECORD_TYPE:
4560 case UNION_TYPE:
4561 case QUAL_UNION_TYPE:
4562 for (t = TYPE_FIELDS (type); t; t = DECL_CHAIN (t))
4563 {
4564 if (TREE_CODE (t) != FIELD_DECL)
4565 continue;
4566
4567 mode = hfa_element_mode (TREE_TYPE (t), 1);
4568 if (know_element_mode)
4569 {
4570 if (mode != element_mode)
4571 return VOIDmode;
4572 }
4573 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
4574 return VOIDmode;
4575 else
4576 {
4577 know_element_mode = 1;
4578 element_mode = mode;
4579 }
4580 }
4581 return element_mode;
4582
4583 default:
4584 /* If we reach here, we probably have some front-end specific type
4585 that the backend doesn't know about. This can happen via the
4586 aggregate_value_p call in init_function_start. All we can do is
4587 ignore unknown tree types. */
4588 return VOIDmode;
4589 }
4590
4591 return VOIDmode;
4592 }
4593
4594 /* Return the number of words required to hold a quantity of TYPE and MODE
4595 when passed as an argument. */
4596 static int
4597 ia64_function_arg_words (const_tree type, enum machine_mode mode)
4598 {
4599 int words;
4600
4601 if (mode == BLKmode)
4602 words = int_size_in_bytes (type);
4603 else
4604 words = GET_MODE_SIZE (mode);
4605
4606 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
4607 }
4608
4609 /* Return the number of registers that should be skipped so the current
4610 argument (described by TYPE and WORDS) will be properly aligned.
4611
4612 Integer and float arguments larger than 8 bytes start at the next
4613 even boundary. Aggregates larger than 8 bytes start at the next
4614 even boundary if the aggregate has 16 byte alignment. Note that
4615 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
4616 but are still to be aligned in registers.
4617
4618 ??? The ABI does not specify how to handle aggregates with
4619 alignment from 9 to 15 bytes, or greater than 16. We handle them
4620 all as if they had 16 byte alignment. Such aggregates can occur
4621 only if gcc extensions are used. */
4622 static int
4623 ia64_function_arg_offset (const CUMULATIVE_ARGS *cum,
4624 const_tree type, int words)
4625 {
4626 /* No registers are skipped on VMS. */
4627 if (TARGET_ABI_OPEN_VMS || (cum->words & 1) == 0)
4628 return 0;
4629
4630 if (type
4631 && TREE_CODE (type) != INTEGER_TYPE
4632 && TREE_CODE (type) != REAL_TYPE)
4633 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
4634 else
4635 return words > 1;
4636 }
4637
4638 /* Return rtx for register where argument is passed, or zero if it is passed
4639 on the stack. */
4640 /* ??? 128-bit quad-precision floats are always passed in general
4641 registers. */
4642
4643 static rtx
4644 ia64_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode,
4645 const_tree type, bool named, bool incoming)
4646 {
4647 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4648
4649 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
4650 int words = ia64_function_arg_words (type, mode);
4651 int offset = ia64_function_arg_offset (cum, type, words);
4652 enum machine_mode hfa_mode = VOIDmode;
4653
4654 /* For OPEN VMS, emit the instruction setting up the argument register here,
4655 when we know this will be together with the other arguments setup related
4656 insns. This is not the conceptually best place to do this, but this is
4657 the easiest as we have convenient access to cumulative args info. */
4658
4659 if (TARGET_ABI_OPEN_VMS && mode == VOIDmode && type == void_type_node
4660 && named == 1)
4661 {
4662 unsigned HOST_WIDE_INT regval = cum->words;
4663 int i;
4664
4665 for (i = 0; i < 8; i++)
4666 regval |= ((int) cum->atypes[i]) << (i * 3 + 8);
4667
4668 emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)),
4669 GEN_INT (regval));
4670 }
4671
4672 /* If all argument slots are used, then it must go on the stack. */
4673 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4674 return 0;
4675
4676 /* On OpenVMS argument is either in Rn or Fn. */
4677 if (TARGET_ABI_OPEN_VMS)
4678 {
4679 if (FLOAT_MODE_P (mode))
4680 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->words);
4681 else
4682 return gen_rtx_REG (mode, basereg + cum->words);
4683 }
4684
4685 /* Check for and handle homogeneous FP aggregates. */
4686 if (type)
4687 hfa_mode = hfa_element_mode (type, 0);
4688
4689 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4690 and unprototyped hfas are passed specially. */
4691 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4692 {
4693 rtx loc[16];
4694 int i = 0;
4695 int fp_regs = cum->fp_regs;
4696 int int_regs = cum->words + offset;
4697 int hfa_size = GET_MODE_SIZE (hfa_mode);
4698 int byte_size;
4699 int args_byte_size;
4700
4701 /* If prototyped, pass it in FR regs then GR regs.
4702 If not prototyped, pass it in both FR and GR regs.
4703
4704 If this is an SFmode aggregate, then it is possible to run out of
4705 FR regs while GR regs are still left. In that case, we pass the
4706 remaining part in the GR regs. */
4707
4708 /* Fill the FP regs. We do this always. We stop if we reach the end
4709 of the argument, the last FP register, or the last argument slot. */
4710
4711 byte_size = ((mode == BLKmode)
4712 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4713 args_byte_size = int_regs * UNITS_PER_WORD;
4714 offset = 0;
4715 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4716 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
4717 {
4718 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4719 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
4720 + fp_regs)),
4721 GEN_INT (offset));
4722 offset += hfa_size;
4723 args_byte_size += hfa_size;
4724 fp_regs++;
4725 }
4726
4727 /* If no prototype, then the whole thing must go in GR regs. */
4728 if (! cum->prototype)
4729 offset = 0;
4730 /* If this is an SFmode aggregate, then we might have some left over
4731 that needs to go in GR regs. */
4732 else if (byte_size != offset)
4733 int_regs += offset / UNITS_PER_WORD;
4734
4735 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4736
4737 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
4738 {
4739 enum machine_mode gr_mode = DImode;
4740 unsigned int gr_size;
4741
4742 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4743 then this goes in a GR reg left adjusted/little endian, right
4744 adjusted/big endian. */
4745 /* ??? Currently this is handled wrong, because 4-byte hunks are
4746 always right adjusted/little endian. */
4747 if (offset & 0x4)
4748 gr_mode = SImode;
4749 /* If we have an even 4 byte hunk because the aggregate is a
4750 multiple of 4 bytes in size, then this goes in a GR reg right
4751 adjusted/little endian. */
4752 else if (byte_size - offset == 4)
4753 gr_mode = SImode;
4754
4755 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4756 gen_rtx_REG (gr_mode, (basereg
4757 + int_regs)),
4758 GEN_INT (offset));
4759
4760 gr_size = GET_MODE_SIZE (gr_mode);
4761 offset += gr_size;
4762 if (gr_size == UNITS_PER_WORD
4763 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
4764 int_regs++;
4765 else if (gr_size > UNITS_PER_WORD)
4766 int_regs += gr_size / UNITS_PER_WORD;
4767 }
4768 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4769 }
4770
4771 /* Integral and aggregates go in general registers. If we have run out of
4772 FR registers, then FP values must also go in general registers. This can
4773 happen when we have a SFmode HFA. */
4774 else if (mode == TFmode || mode == TCmode
4775 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4776 {
4777 int byte_size = ((mode == BLKmode)
4778 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4779 if (BYTES_BIG_ENDIAN
4780 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
4781 && byte_size < UNITS_PER_WORD
4782 && byte_size > 0)
4783 {
4784 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4785 gen_rtx_REG (DImode,
4786 (basereg + cum->words
4787 + offset)),
4788 const0_rtx);
4789 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
4790 }
4791 else
4792 return gen_rtx_REG (mode, basereg + cum->words + offset);
4793
4794 }
4795
4796 /* If there is a prototype, then FP values go in a FR register when
4797 named, and in a GR register when unnamed. */
4798 else if (cum->prototype)
4799 {
4800 if (named)
4801 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
4802 /* In big-endian mode, an anonymous SFmode value must be represented
4803 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4804 the value into the high half of the general register. */
4805 else if (BYTES_BIG_ENDIAN && mode == SFmode)
4806 return gen_rtx_PARALLEL (mode,
4807 gen_rtvec (1,
4808 gen_rtx_EXPR_LIST (VOIDmode,
4809 gen_rtx_REG (DImode, basereg + cum->words + offset),
4810 const0_rtx)));
4811 else
4812 return gen_rtx_REG (mode, basereg + cum->words + offset);
4813 }
4814 /* If there is no prototype, then FP values go in both FR and GR
4815 registers. */
4816 else
4817 {
4818 /* See comment above. */
4819 enum machine_mode inner_mode =
4820 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
4821
4822 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
4823 gen_rtx_REG (mode, (FR_ARG_FIRST
4824 + cum->fp_regs)),
4825 const0_rtx);
4826 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4827 gen_rtx_REG (inner_mode,
4828 (basereg + cum->words
4829 + offset)),
4830 const0_rtx);
4831
4832 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
4833 }
4834 }
4835
4836 /* Implement TARGET_FUNCION_ARG target hook. */
4837
4838 static rtx
4839 ia64_function_arg (cumulative_args_t cum, enum machine_mode mode,
4840 const_tree type, bool named)
4841 {
4842 return ia64_function_arg_1 (cum, mode, type, named, false);
4843 }
4844
4845 /* Implement TARGET_FUNCION_INCOMING_ARG target hook. */
4846
4847 static rtx
4848 ia64_function_incoming_arg (cumulative_args_t cum,
4849 enum machine_mode mode,
4850 const_tree type, bool named)
4851 {
4852 return ia64_function_arg_1 (cum, mode, type, named, true);
4853 }
4854
4855 /* Return number of bytes, at the beginning of the argument, that must be
4856 put in registers. 0 is the argument is entirely in registers or entirely
4857 in memory. */
4858
4859 static int
4860 ia64_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
4861 tree type, bool named ATTRIBUTE_UNUSED)
4862 {
4863 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4864
4865 int words = ia64_function_arg_words (type, mode);
4866 int offset = ia64_function_arg_offset (cum, type, words);
4867
4868 /* If all argument slots are used, then it must go on the stack. */
4869 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4870 return 0;
4871
4872 /* It doesn't matter whether the argument goes in FR or GR regs. If
4873 it fits within the 8 argument slots, then it goes entirely in
4874 registers. If it extends past the last argument slot, then the rest
4875 goes on the stack. */
4876
4877 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
4878 return 0;
4879
4880 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
4881 }
4882
4883 /* Return ivms_arg_type based on machine_mode. */
4884
4885 static enum ivms_arg_type
4886 ia64_arg_type (enum machine_mode mode)
4887 {
4888 switch (mode)
4889 {
4890 case SFmode:
4891 return FS;
4892 case DFmode:
4893 return FT;
4894 default:
4895 return I64;
4896 }
4897 }
4898
4899 /* Update CUM to point after this argument. This is patterned after
4900 ia64_function_arg. */
4901
4902 static void
4903 ia64_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
4904 const_tree type, bool named)
4905 {
4906 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4907 int words = ia64_function_arg_words (type, mode);
4908 int offset = ia64_function_arg_offset (cum, type, words);
4909 enum machine_mode hfa_mode = VOIDmode;
4910
4911 /* If all arg slots are already full, then there is nothing to do. */
4912 if (cum->words >= MAX_ARGUMENT_SLOTS)
4913 {
4914 cum->words += words + offset;
4915 return;
4916 }
4917
4918 cum->atypes[cum->words] = ia64_arg_type (mode);
4919 cum->words += words + offset;
4920
4921 /* On OpenVMS argument is either in Rn or Fn. */
4922 if (TARGET_ABI_OPEN_VMS)
4923 {
4924 cum->int_regs = cum->words;
4925 cum->fp_regs = cum->words;
4926 return;
4927 }
4928
4929 /* Check for and handle homogeneous FP aggregates. */
4930 if (type)
4931 hfa_mode = hfa_element_mode (type, 0);
4932
4933 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4934 and unprototyped hfas are passed specially. */
4935 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4936 {
4937 int fp_regs = cum->fp_regs;
4938 /* This is the original value of cum->words + offset. */
4939 int int_regs = cum->words - words;
4940 int hfa_size = GET_MODE_SIZE (hfa_mode);
4941 int byte_size;
4942 int args_byte_size;
4943
4944 /* If prototyped, pass it in FR regs then GR regs.
4945 If not prototyped, pass it in both FR and GR regs.
4946
4947 If this is an SFmode aggregate, then it is possible to run out of
4948 FR regs while GR regs are still left. In that case, we pass the
4949 remaining part in the GR regs. */
4950
4951 /* Fill the FP regs. We do this always. We stop if we reach the end
4952 of the argument, the last FP register, or the last argument slot. */
4953
4954 byte_size = ((mode == BLKmode)
4955 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4956 args_byte_size = int_regs * UNITS_PER_WORD;
4957 offset = 0;
4958 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4959 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
4960 {
4961 offset += hfa_size;
4962 args_byte_size += hfa_size;
4963 fp_regs++;
4964 }
4965
4966 cum->fp_regs = fp_regs;
4967 }
4968
4969 /* Integral and aggregates go in general registers. So do TFmode FP values.
4970 If we have run out of FR registers, then other FP values must also go in
4971 general registers. This can happen when we have a SFmode HFA. */
4972 else if (mode == TFmode || mode == TCmode
4973 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4974 cum->int_regs = cum->words;
4975
4976 /* If there is a prototype, then FP values go in a FR register when
4977 named, and in a GR register when unnamed. */
4978 else if (cum->prototype)
4979 {
4980 if (! named)
4981 cum->int_regs = cum->words;
4982 else
4983 /* ??? Complex types should not reach here. */
4984 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4985 }
4986 /* If there is no prototype, then FP values go in both FR and GR
4987 registers. */
4988 else
4989 {
4990 /* ??? Complex types should not reach here. */
4991 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4992 cum->int_regs = cum->words;
4993 }
4994 }
4995
4996 /* Arguments with alignment larger than 8 bytes start at the next even
4997 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4998 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4999
5000 static unsigned int
5001 ia64_function_arg_boundary (enum machine_mode mode, const_tree type)
5002 {
5003 if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
5004 return PARM_BOUNDARY * 2;
5005
5006 if (type)
5007 {
5008 if (TYPE_ALIGN (type) > PARM_BOUNDARY)
5009 return PARM_BOUNDARY * 2;
5010 else
5011 return PARM_BOUNDARY;
5012 }
5013
5014 if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
5015 return PARM_BOUNDARY * 2;
5016 else
5017 return PARM_BOUNDARY;
5018 }
5019
5020 /* True if it is OK to do sibling call optimization for the specified
5021 call expression EXP. DECL will be the called function, or NULL if
5022 this is an indirect call. */
5023 static bool
5024 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5025 {
5026 /* We can't perform a sibcall if the current function has the syscall_linkage
5027 attribute. */
5028 if (lookup_attribute ("syscall_linkage",
5029 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
5030 return false;
5031
5032 /* We must always return with our current GP. This means we can
5033 only sibcall to functions defined in the current module unless
5034 TARGET_CONST_GP is set to true. */
5035 return (decl && (*targetm.binds_local_p) (decl)) || TARGET_CONST_GP;
5036 }
5037 \f
5038
5039 /* Implement va_arg. */
5040
5041 static tree
5042 ia64_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
5043 gimple_seq *post_p)
5044 {
5045 /* Variable sized types are passed by reference. */
5046 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5047 {
5048 tree ptrtype = build_pointer_type (type);
5049 tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p);
5050 return build_va_arg_indirect_ref (addr);
5051 }
5052
5053 /* Aggregate arguments with alignment larger than 8 bytes start at
5054 the next even boundary. Integer and floating point arguments
5055 do so if they are larger than 8 bytes, whether or not they are
5056 also aligned larger than 8 bytes. */
5057 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
5058 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
5059 {
5060 tree t = fold_build_pointer_plus_hwi (valist, 2 * UNITS_PER_WORD - 1);
5061 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5062 build_int_cst (TREE_TYPE (t), -2 * UNITS_PER_WORD));
5063 gimplify_assign (unshare_expr (valist), t, pre_p);
5064 }
5065
5066 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5067 }
5068 \f
5069 /* Return 1 if function return value returned in memory. Return 0 if it is
5070 in a register. */
5071
5072 static bool
5073 ia64_return_in_memory (const_tree valtype, const_tree fntype ATTRIBUTE_UNUSED)
5074 {
5075 enum machine_mode mode;
5076 enum machine_mode hfa_mode;
5077 HOST_WIDE_INT byte_size;
5078
5079 mode = TYPE_MODE (valtype);
5080 byte_size = GET_MODE_SIZE (mode);
5081 if (mode == BLKmode)
5082 {
5083 byte_size = int_size_in_bytes (valtype);
5084 if (byte_size < 0)
5085 return true;
5086 }
5087
5088 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
5089
5090 hfa_mode = hfa_element_mode (valtype, 0);
5091 if (hfa_mode != VOIDmode)
5092 {
5093 int hfa_size = GET_MODE_SIZE (hfa_mode);
5094
5095 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
5096 return true;
5097 else
5098 return false;
5099 }
5100 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
5101 return true;
5102 else
5103 return false;
5104 }
5105
5106 /* Return rtx for register that holds the function return value. */
5107
5108 static rtx
5109 ia64_function_value (const_tree valtype,
5110 const_tree fn_decl_or_type,
5111 bool outgoing ATTRIBUTE_UNUSED)
5112 {
5113 enum machine_mode mode;
5114 enum machine_mode hfa_mode;
5115 int unsignedp;
5116 const_tree func = fn_decl_or_type;
5117
5118 if (fn_decl_or_type
5119 && !DECL_P (fn_decl_or_type))
5120 func = NULL;
5121
5122 mode = TYPE_MODE (valtype);
5123 hfa_mode = hfa_element_mode (valtype, 0);
5124
5125 if (hfa_mode != VOIDmode)
5126 {
5127 rtx loc[8];
5128 int i;
5129 int hfa_size;
5130 int byte_size;
5131 int offset;
5132
5133 hfa_size = GET_MODE_SIZE (hfa_mode);
5134 byte_size = ((mode == BLKmode)
5135 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
5136 offset = 0;
5137 for (i = 0; offset < byte_size; i++)
5138 {
5139 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
5140 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
5141 GEN_INT (offset));
5142 offset += hfa_size;
5143 }
5144 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
5145 }
5146 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
5147 return gen_rtx_REG (mode, FR_ARG_FIRST);
5148 else
5149 {
5150 bool need_parallel = false;
5151
5152 /* In big-endian mode, we need to manage the layout of aggregates
5153 in the registers so that we get the bits properly aligned in
5154 the highpart of the registers. */
5155 if (BYTES_BIG_ENDIAN
5156 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
5157 need_parallel = true;
5158
5159 /* Something like struct S { long double x; char a[0] } is not an
5160 HFA structure, and therefore doesn't go in fp registers. But
5161 the middle-end will give it XFmode anyway, and XFmode values
5162 don't normally fit in integer registers. So we need to smuggle
5163 the value inside a parallel. */
5164 else if (mode == XFmode || mode == XCmode || mode == RFmode)
5165 need_parallel = true;
5166
5167 if (need_parallel)
5168 {
5169 rtx loc[8];
5170 int offset;
5171 int bytesize;
5172 int i;
5173
5174 offset = 0;
5175 bytesize = int_size_in_bytes (valtype);
5176 /* An empty PARALLEL is invalid here, but the return value
5177 doesn't matter for empty structs. */
5178 if (bytesize == 0)
5179 return gen_rtx_REG (mode, GR_RET_FIRST);
5180 for (i = 0; offset < bytesize; i++)
5181 {
5182 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
5183 gen_rtx_REG (DImode,
5184 GR_RET_FIRST + i),
5185 GEN_INT (offset));
5186 offset += UNITS_PER_WORD;
5187 }
5188 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
5189 }
5190
5191 mode = promote_function_mode (valtype, mode, &unsignedp,
5192 func ? TREE_TYPE (func) : NULL_TREE,
5193 true);
5194
5195 return gen_rtx_REG (mode, GR_RET_FIRST);
5196 }
5197 }
5198
5199 /* Worker function for TARGET_LIBCALL_VALUE. */
5200
5201 static rtx
5202 ia64_libcall_value (enum machine_mode mode,
5203 const_rtx fun ATTRIBUTE_UNUSED)
5204 {
5205 return gen_rtx_REG (mode,
5206 (((GET_MODE_CLASS (mode) == MODE_FLOAT
5207 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5208 && (mode) != TFmode)
5209 ? FR_RET_FIRST : GR_RET_FIRST));
5210 }
5211
5212 /* Worker function for FUNCTION_VALUE_REGNO_P. */
5213
5214 static bool
5215 ia64_function_value_regno_p (const unsigned int regno)
5216 {
5217 return ((regno >= GR_RET_FIRST && regno <= GR_RET_LAST)
5218 || (regno >= FR_RET_FIRST && regno <= FR_RET_LAST));
5219 }
5220
5221 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5222 We need to emit DTP-relative relocations. */
5223
5224 static void
5225 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
5226 {
5227 gcc_assert (size == 4 || size == 8);
5228 if (size == 4)
5229 fputs ("\tdata4.ua\t@dtprel(", file);
5230 else
5231 fputs ("\tdata8.ua\t@dtprel(", file);
5232 output_addr_const (file, x);
5233 fputs (")", file);
5234 }
5235
5236 /* Print a memory address as an operand to reference that memory location. */
5237
5238 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
5239 also call this from ia64_print_operand for memory addresses. */
5240
5241 static void
5242 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
5243 rtx address ATTRIBUTE_UNUSED)
5244 {
5245 }
5246
5247 /* Print an operand to an assembler instruction.
5248 C Swap and print a comparison operator.
5249 D Print an FP comparison operator.
5250 E Print 32 - constant, for SImode shifts as extract.
5251 e Print 64 - constant, for DImode rotates.
5252 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
5253 a floating point register emitted normally.
5254 G A floating point constant.
5255 I Invert a predicate register by adding 1.
5256 J Select the proper predicate register for a condition.
5257 j Select the inverse predicate register for a condition.
5258 O Append .acq for volatile load.
5259 P Postincrement of a MEM.
5260 Q Append .rel for volatile store.
5261 R Print .s .d or nothing for a single, double or no truncation.
5262 S Shift amount for shladd instruction.
5263 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
5264 for Intel assembler.
5265 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
5266 for Intel assembler.
5267 X A pair of floating point registers.
5268 r Print register name, or constant 0 as r0. HP compatibility for
5269 Linux kernel.
5270 v Print vector constant value as an 8-byte integer value. */
5271
5272 static void
5273 ia64_print_operand (FILE * file, rtx x, int code)
5274 {
5275 const char *str;
5276
5277 switch (code)
5278 {
5279 case 0:
5280 /* Handled below. */
5281 break;
5282
5283 case 'C':
5284 {
5285 enum rtx_code c = swap_condition (GET_CODE (x));
5286 fputs (GET_RTX_NAME (c), file);
5287 return;
5288 }
5289
5290 case 'D':
5291 switch (GET_CODE (x))
5292 {
5293 case NE:
5294 str = "neq";
5295 break;
5296 case UNORDERED:
5297 str = "unord";
5298 break;
5299 case ORDERED:
5300 str = "ord";
5301 break;
5302 case UNLT:
5303 str = "nge";
5304 break;
5305 case UNLE:
5306 str = "ngt";
5307 break;
5308 case UNGT:
5309 str = "nle";
5310 break;
5311 case UNGE:
5312 str = "nlt";
5313 break;
5314 case UNEQ:
5315 case LTGT:
5316 gcc_unreachable ();
5317 default:
5318 str = GET_RTX_NAME (GET_CODE (x));
5319 break;
5320 }
5321 fputs (str, file);
5322 return;
5323
5324 case 'E':
5325 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
5326 return;
5327
5328 case 'e':
5329 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
5330 return;
5331
5332 case 'F':
5333 if (x == CONST0_RTX (GET_MODE (x)))
5334 str = reg_names [FR_REG (0)];
5335 else if (x == CONST1_RTX (GET_MODE (x)))
5336 str = reg_names [FR_REG (1)];
5337 else
5338 {
5339 gcc_assert (GET_CODE (x) == REG);
5340 str = reg_names [REGNO (x)];
5341 }
5342 fputs (str, file);
5343 return;
5344
5345 case 'G':
5346 {
5347 long val[4];
5348 REAL_VALUE_TYPE rv;
5349 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
5350 real_to_target (val, &rv, GET_MODE (x));
5351 if (GET_MODE (x) == SFmode)
5352 fprintf (file, "0x%08lx", val[0] & 0xffffffff);
5353 else if (GET_MODE (x) == DFmode)
5354 fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1])
5355 & 0xffffffff,
5356 (WORDS_BIG_ENDIAN ? val[1] : val[0])
5357 & 0xffffffff);
5358 else
5359 output_operand_lossage ("invalid %%G mode");
5360 }
5361 return;
5362
5363 case 'I':
5364 fputs (reg_names [REGNO (x) + 1], file);
5365 return;
5366
5367 case 'J':
5368 case 'j':
5369 {
5370 unsigned int regno = REGNO (XEXP (x, 0));
5371 if (GET_CODE (x) == EQ)
5372 regno += 1;
5373 if (code == 'j')
5374 regno ^= 1;
5375 fputs (reg_names [regno], file);
5376 }
5377 return;
5378
5379 case 'O':
5380 if (MEM_VOLATILE_P (x))
5381 fputs(".acq", file);
5382 return;
5383
5384 case 'P':
5385 {
5386 HOST_WIDE_INT value;
5387
5388 switch (GET_CODE (XEXP (x, 0)))
5389 {
5390 default:
5391 return;
5392
5393 case POST_MODIFY:
5394 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
5395 if (GET_CODE (x) == CONST_INT)
5396 value = INTVAL (x);
5397 else
5398 {
5399 gcc_assert (GET_CODE (x) == REG);
5400 fprintf (file, ", %s", reg_names[REGNO (x)]);
5401 return;
5402 }
5403 break;
5404
5405 case POST_INC:
5406 value = GET_MODE_SIZE (GET_MODE (x));
5407 break;
5408
5409 case POST_DEC:
5410 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
5411 break;
5412 }
5413
5414 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
5415 return;
5416 }
5417
5418 case 'Q':
5419 if (MEM_VOLATILE_P (x))
5420 fputs(".rel", file);
5421 return;
5422
5423 case 'R':
5424 if (x == CONST0_RTX (GET_MODE (x)))
5425 fputs(".s", file);
5426 else if (x == CONST1_RTX (GET_MODE (x)))
5427 fputs(".d", file);
5428 else if (x == CONST2_RTX (GET_MODE (x)))
5429 ;
5430 else
5431 output_operand_lossage ("invalid %%R value");
5432 return;
5433
5434 case 'S':
5435 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5436 return;
5437
5438 case 'T':
5439 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
5440 {
5441 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
5442 return;
5443 }
5444 break;
5445
5446 case 'U':
5447 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
5448 {
5449 const char *prefix = "0x";
5450 if (INTVAL (x) & 0x80000000)
5451 {
5452 fprintf (file, "0xffffffff");
5453 prefix = "";
5454 }
5455 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
5456 return;
5457 }
5458 break;
5459
5460 case 'X':
5461 {
5462 unsigned int regno = REGNO (x);
5463 fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]);
5464 }
5465 return;
5466
5467 case 'r':
5468 /* If this operand is the constant zero, write it as register zero.
5469 Any register, zero, or CONST_INT value is OK here. */
5470 if (GET_CODE (x) == REG)
5471 fputs (reg_names[REGNO (x)], file);
5472 else if (x == CONST0_RTX (GET_MODE (x)))
5473 fputs ("r0", file);
5474 else if (GET_CODE (x) == CONST_INT)
5475 output_addr_const (file, x);
5476 else
5477 output_operand_lossage ("invalid %%r value");
5478 return;
5479
5480 case 'v':
5481 gcc_assert (GET_CODE (x) == CONST_VECTOR);
5482 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
5483 break;
5484
5485 case '+':
5486 {
5487 const char *which;
5488
5489 /* For conditional branches, returns or calls, substitute
5490 sptk, dptk, dpnt, or spnt for %s. */
5491 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
5492 if (x)
5493 {
5494 int pred_val = XINT (x, 0);
5495
5496 /* Guess top and bottom 10% statically predicted. */
5497 if (pred_val < REG_BR_PROB_BASE / 50
5498 && br_prob_note_reliable_p (x))
5499 which = ".spnt";
5500 else if (pred_val < REG_BR_PROB_BASE / 2)
5501 which = ".dpnt";
5502 else if (pred_val < REG_BR_PROB_BASE / 100 * 98
5503 || !br_prob_note_reliable_p (x))
5504 which = ".dptk";
5505 else
5506 which = ".sptk";
5507 }
5508 else if (CALL_P (current_output_insn))
5509 which = ".sptk";
5510 else
5511 which = ".dptk";
5512
5513 fputs (which, file);
5514 return;
5515 }
5516
5517 case ',':
5518 x = current_insn_predicate;
5519 if (x)
5520 {
5521 unsigned int regno = REGNO (XEXP (x, 0));
5522 if (GET_CODE (x) == EQ)
5523 regno += 1;
5524 fprintf (file, "(%s) ", reg_names [regno]);
5525 }
5526 return;
5527
5528 default:
5529 output_operand_lossage ("ia64_print_operand: unknown code");
5530 return;
5531 }
5532
5533 switch (GET_CODE (x))
5534 {
5535 /* This happens for the spill/restore instructions. */
5536 case POST_INC:
5537 case POST_DEC:
5538 case POST_MODIFY:
5539 x = XEXP (x, 0);
5540 /* ... fall through ... */
5541
5542 case REG:
5543 fputs (reg_names [REGNO (x)], file);
5544 break;
5545
5546 case MEM:
5547 {
5548 rtx addr = XEXP (x, 0);
5549 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
5550 addr = XEXP (addr, 0);
5551 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
5552 break;
5553 }
5554
5555 default:
5556 output_addr_const (file, x);
5557 break;
5558 }
5559
5560 return;
5561 }
5562
5563 /* Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
5564
5565 static bool
5566 ia64_print_operand_punct_valid_p (unsigned char code)
5567 {
5568 return (code == '+' || code == ',');
5569 }
5570 \f
5571 /* Compute a (partial) cost for rtx X. Return true if the complete
5572 cost has been computed, and false if subexpressions should be
5573 scanned. In either case, *TOTAL contains the cost result. */
5574 /* ??? This is incomplete. */
5575
5576 static bool
5577 ia64_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
5578 int *total, bool speed ATTRIBUTE_UNUSED)
5579 {
5580 switch (code)
5581 {
5582 case CONST_INT:
5583 switch (outer_code)
5584 {
5585 case SET:
5586 *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1);
5587 return true;
5588 case PLUS:
5589 if (satisfies_constraint_I (x))
5590 *total = 0;
5591 else if (satisfies_constraint_J (x))
5592 *total = 1;
5593 else
5594 *total = COSTS_N_INSNS (1);
5595 return true;
5596 default:
5597 if (satisfies_constraint_K (x) || satisfies_constraint_L (x))
5598 *total = 0;
5599 else
5600 *total = COSTS_N_INSNS (1);
5601 return true;
5602 }
5603
5604 case CONST_DOUBLE:
5605 *total = COSTS_N_INSNS (1);
5606 return true;
5607
5608 case CONST:
5609 case SYMBOL_REF:
5610 case LABEL_REF:
5611 *total = COSTS_N_INSNS (3);
5612 return true;
5613
5614 case FMA:
5615 *total = COSTS_N_INSNS (4);
5616 return true;
5617
5618 case MULT:
5619 /* For multiplies wider than HImode, we have to go to the FPU,
5620 which normally involves copies. Plus there's the latency
5621 of the multiply itself, and the latency of the instructions to
5622 transfer integer regs to FP regs. */
5623 if (FLOAT_MODE_P (GET_MODE (x)))
5624 *total = COSTS_N_INSNS (4);
5625 else if (GET_MODE_SIZE (GET_MODE (x)) > 2)
5626 *total = COSTS_N_INSNS (10);
5627 else
5628 *total = COSTS_N_INSNS (2);
5629 return true;
5630
5631 case PLUS:
5632 case MINUS:
5633 if (FLOAT_MODE_P (GET_MODE (x)))
5634 {
5635 *total = COSTS_N_INSNS (4);
5636 return true;
5637 }
5638 /* FALLTHRU */
5639
5640 case ASHIFT:
5641 case ASHIFTRT:
5642 case LSHIFTRT:
5643 *total = COSTS_N_INSNS (1);
5644 return true;
5645
5646 case DIV:
5647 case UDIV:
5648 case MOD:
5649 case UMOD:
5650 /* We make divide expensive, so that divide-by-constant will be
5651 optimized to a multiply. */
5652 *total = COSTS_N_INSNS (60);
5653 return true;
5654
5655 default:
5656 return false;
5657 }
5658 }
5659
5660 /* Calculate the cost of moving data from a register in class FROM to
5661 one in class TO, using MODE. */
5662
5663 static int
5664 ia64_register_move_cost (enum machine_mode mode, reg_class_t from,
5665 reg_class_t to)
5666 {
5667 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
5668 if (to == ADDL_REGS)
5669 to = GR_REGS;
5670 if (from == ADDL_REGS)
5671 from = GR_REGS;
5672
5673 /* All costs are symmetric, so reduce cases by putting the
5674 lower number class as the destination. */
5675 if (from < to)
5676 {
5677 reg_class_t tmp = to;
5678 to = from, from = tmp;
5679 }
5680
5681 /* Moving from FR<->GR in XFmode must be more expensive than 2,
5682 so that we get secondary memory reloads. Between FR_REGS,
5683 we have to make this at least as expensive as memory_move_cost
5684 to avoid spectacularly poor register class preferencing. */
5685 if (mode == XFmode || mode == RFmode)
5686 {
5687 if (to != GR_REGS || from != GR_REGS)
5688 return memory_move_cost (mode, to, false);
5689 else
5690 return 3;
5691 }
5692
5693 switch (to)
5694 {
5695 case PR_REGS:
5696 /* Moving between PR registers takes two insns. */
5697 if (from == PR_REGS)
5698 return 3;
5699 /* Moving between PR and anything but GR is impossible. */
5700 if (from != GR_REGS)
5701 return memory_move_cost (mode, to, false);
5702 break;
5703
5704 case BR_REGS:
5705 /* Moving between BR and anything but GR is impossible. */
5706 if (from != GR_REGS && from != GR_AND_BR_REGS)
5707 return memory_move_cost (mode, to, false);
5708 break;
5709
5710 case AR_I_REGS:
5711 case AR_M_REGS:
5712 /* Moving between AR and anything but GR is impossible. */
5713 if (from != GR_REGS)
5714 return memory_move_cost (mode, to, false);
5715 break;
5716
5717 case GR_REGS:
5718 case FR_REGS:
5719 case FP_REGS:
5720 case GR_AND_FR_REGS:
5721 case GR_AND_BR_REGS:
5722 case ALL_REGS:
5723 break;
5724
5725 default:
5726 gcc_unreachable ();
5727 }
5728
5729 return 2;
5730 }
5731
5732 /* Calculate the cost of moving data of MODE from a register to or from
5733 memory. */
5734
5735 static int
5736 ia64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
5737 reg_class_t rclass,
5738 bool in ATTRIBUTE_UNUSED)
5739 {
5740 if (rclass == GENERAL_REGS
5741 || rclass == FR_REGS
5742 || rclass == FP_REGS
5743 || rclass == GR_AND_FR_REGS)
5744 return 4;
5745 else
5746 return 10;
5747 }
5748
5749 /* Implement TARGET_PREFERRED_RELOAD_CLASS. Place additional restrictions
5750 on RCLASS to use when copying X into that class. */
5751
5752 static reg_class_t
5753 ia64_preferred_reload_class (rtx x, reg_class_t rclass)
5754 {
5755 switch (rclass)
5756 {
5757 case FR_REGS:
5758 case FP_REGS:
5759 /* Don't allow volatile mem reloads into floating point registers.
5760 This is defined to force reload to choose the r/m case instead
5761 of the f/f case when reloading (set (reg fX) (mem/v)). */
5762 if (MEM_P (x) && MEM_VOLATILE_P (x))
5763 return NO_REGS;
5764
5765 /* Force all unrecognized constants into the constant pool. */
5766 if (CONSTANT_P (x))
5767 return NO_REGS;
5768 break;
5769
5770 case AR_M_REGS:
5771 case AR_I_REGS:
5772 if (!OBJECT_P (x))
5773 return NO_REGS;
5774 break;
5775
5776 default:
5777 break;
5778 }
5779
5780 return rclass;
5781 }
5782
5783 /* This function returns the register class required for a secondary
5784 register when copying between one of the registers in RCLASS, and X,
5785 using MODE. A return value of NO_REGS means that no secondary register
5786 is required. */
5787
5788 enum reg_class
5789 ia64_secondary_reload_class (enum reg_class rclass,
5790 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
5791 {
5792 int regno = -1;
5793
5794 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
5795 regno = true_regnum (x);
5796
5797 switch (rclass)
5798 {
5799 case BR_REGS:
5800 case AR_M_REGS:
5801 case AR_I_REGS:
5802 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
5803 interaction. We end up with two pseudos with overlapping lifetimes
5804 both of which are equiv to the same constant, and both which need
5805 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
5806 changes depending on the path length, which means the qty_first_reg
5807 check in make_regs_eqv can give different answers at different times.
5808 At some point I'll probably need a reload_indi pattern to handle
5809 this.
5810
5811 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
5812 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
5813 non-general registers for good measure. */
5814 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
5815 return GR_REGS;
5816
5817 /* This is needed if a pseudo used as a call_operand gets spilled to a
5818 stack slot. */
5819 if (GET_CODE (x) == MEM)
5820 return GR_REGS;
5821 break;
5822
5823 case FR_REGS:
5824 case FP_REGS:
5825 /* Need to go through general registers to get to other class regs. */
5826 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
5827 return GR_REGS;
5828
5829 /* This can happen when a paradoxical subreg is an operand to the
5830 muldi3 pattern. */
5831 /* ??? This shouldn't be necessary after instruction scheduling is
5832 enabled, because paradoxical subregs are not accepted by
5833 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5834 stop the paradoxical subreg stupidity in the *_operand functions
5835 in recog.c. */
5836 if (GET_CODE (x) == MEM
5837 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
5838 || GET_MODE (x) == QImode))
5839 return GR_REGS;
5840
5841 /* This can happen because of the ior/and/etc patterns that accept FP
5842 registers as operands. If the third operand is a constant, then it
5843 needs to be reloaded into a FP register. */
5844 if (GET_CODE (x) == CONST_INT)
5845 return GR_REGS;
5846
5847 /* This can happen because of register elimination in a muldi3 insn.
5848 E.g. `26107 * (unsigned long)&u'. */
5849 if (GET_CODE (x) == PLUS)
5850 return GR_REGS;
5851 break;
5852
5853 case PR_REGS:
5854 /* ??? This happens if we cse/gcse a BImode value across a call,
5855 and the function has a nonlocal goto. This is because global
5856 does not allocate call crossing pseudos to hard registers when
5857 crtl->has_nonlocal_goto is true. This is relatively
5858 common for C++ programs that use exceptions. To reproduce,
5859 return NO_REGS and compile libstdc++. */
5860 if (GET_CODE (x) == MEM)
5861 return GR_REGS;
5862
5863 /* This can happen when we take a BImode subreg of a DImode value,
5864 and that DImode value winds up in some non-GR register. */
5865 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
5866 return GR_REGS;
5867 break;
5868
5869 default:
5870 break;
5871 }
5872
5873 return NO_REGS;
5874 }
5875
5876 \f
5877 /* Implement targetm.unspec_may_trap_p hook. */
5878 static int
5879 ia64_unspec_may_trap_p (const_rtx x, unsigned flags)
5880 {
5881 switch (XINT (x, 1))
5882 {
5883 case UNSPEC_LDA:
5884 case UNSPEC_LDS:
5885 case UNSPEC_LDSA:
5886 case UNSPEC_LDCCLR:
5887 case UNSPEC_CHKACLR:
5888 case UNSPEC_CHKS:
5889 /* These unspecs are just wrappers. */
5890 return may_trap_p_1 (XVECEXP (x, 0, 0), flags);
5891 }
5892
5893 return default_unspec_may_trap_p (x, flags);
5894 }
5895
5896 \f
5897 /* Parse the -mfixed-range= option string. */
5898
5899 static void
5900 fix_range (const char *const_str)
5901 {
5902 int i, first, last;
5903 char *str, *dash, *comma;
5904
5905 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5906 REG2 are either register names or register numbers. The effect
5907 of this option is to mark the registers in the range from REG1 to
5908 REG2 as ``fixed'' so they won't be used by the compiler. This is
5909 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5910
5911 i = strlen (const_str);
5912 str = (char *) alloca (i + 1);
5913 memcpy (str, const_str, i + 1);
5914
5915 while (1)
5916 {
5917 dash = strchr (str, '-');
5918 if (!dash)
5919 {
5920 warning (0, "value of -mfixed-range must have form REG1-REG2");
5921 return;
5922 }
5923 *dash = '\0';
5924
5925 comma = strchr (dash + 1, ',');
5926 if (comma)
5927 *comma = '\0';
5928
5929 first = decode_reg_name (str);
5930 if (first < 0)
5931 {
5932 warning (0, "unknown register name: %s", str);
5933 return;
5934 }
5935
5936 last = decode_reg_name (dash + 1);
5937 if (last < 0)
5938 {
5939 warning (0, "unknown register name: %s", dash + 1);
5940 return;
5941 }
5942
5943 *dash = '-';
5944
5945 if (first > last)
5946 {
5947 warning (0, "%s-%s is an empty range", str, dash + 1);
5948 return;
5949 }
5950
5951 for (i = first; i <= last; ++i)
5952 fixed_regs[i] = call_used_regs[i] = 1;
5953
5954 if (!comma)
5955 break;
5956
5957 *comma = ',';
5958 str = comma + 1;
5959 }
5960 }
5961
5962 /* Implement TARGET_OPTION_OVERRIDE. */
5963
5964 static void
5965 ia64_option_override (void)
5966 {
5967 unsigned int i;
5968 cl_deferred_option *opt;
5969 vec<cl_deferred_option> *v
5970 = (vec<cl_deferred_option> *) ia64_deferred_options;
5971
5972 if (v)
5973 FOR_EACH_VEC_ELT (*v, i, opt)
5974 {
5975 switch (opt->opt_index)
5976 {
5977 case OPT_mfixed_range_:
5978 fix_range (opt->arg);
5979 break;
5980
5981 default:
5982 gcc_unreachable ();
5983 }
5984 }
5985
5986 if (TARGET_AUTO_PIC)
5987 target_flags |= MASK_CONST_GP;
5988
5989 /* Numerous experiment shows that IRA based loop pressure
5990 calculation works better for RTL loop invariant motion on targets
5991 with enough (>= 32) registers. It is an expensive optimization.
5992 So it is on only for peak performance. */
5993 if (optimize >= 3)
5994 flag_ira_loop_pressure = 1;
5995
5996
5997 ia64_section_threshold = (global_options_set.x_g_switch_value
5998 ? g_switch_value
5999 : IA64_DEFAULT_GVALUE);
6000
6001 init_machine_status = ia64_init_machine_status;
6002
6003 if (align_functions <= 0)
6004 align_functions = 64;
6005 if (align_loops <= 0)
6006 align_loops = 32;
6007 if (TARGET_ABI_OPEN_VMS)
6008 flag_no_common = 1;
6009
6010 ia64_override_options_after_change();
6011 }
6012
6013 /* Implement targetm.override_options_after_change. */
6014
6015 static void
6016 ia64_override_options_after_change (void)
6017 {
6018 if (optimize >= 3
6019 && !global_options_set.x_flag_selective_scheduling
6020 && !global_options_set.x_flag_selective_scheduling2)
6021 {
6022 flag_selective_scheduling2 = 1;
6023 flag_sel_sched_pipelining = 1;
6024 }
6025 if (mflag_sched_control_spec == 2)
6026 {
6027 /* Control speculation is on by default for the selective scheduler,
6028 but not for the Haifa scheduler. */
6029 mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0;
6030 }
6031 if (flag_sel_sched_pipelining && flag_auto_inc_dec)
6032 {
6033 /* FIXME: remove this when we'd implement breaking autoinsns as
6034 a transformation. */
6035 flag_auto_inc_dec = 0;
6036 }
6037 }
6038
6039 /* Initialize the record of emitted frame related registers. */
6040
6041 void ia64_init_expanders (void)
6042 {
6043 memset (&emitted_frame_related_regs, 0, sizeof (emitted_frame_related_regs));
6044 }
6045
6046 static struct machine_function *
6047 ia64_init_machine_status (void)
6048 {
6049 return ggc_cleared_alloc<machine_function> ();
6050 }
6051 \f
6052 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
6053 static enum attr_type ia64_safe_type (rtx);
6054
6055 static enum attr_itanium_class
6056 ia64_safe_itanium_class (rtx insn)
6057 {
6058 if (recog_memoized (insn) >= 0)
6059 return get_attr_itanium_class (insn);
6060 else if (DEBUG_INSN_P (insn))
6061 return ITANIUM_CLASS_IGNORE;
6062 else
6063 return ITANIUM_CLASS_UNKNOWN;
6064 }
6065
6066 static enum attr_type
6067 ia64_safe_type (rtx insn)
6068 {
6069 if (recog_memoized (insn) >= 0)
6070 return get_attr_type (insn);
6071 else
6072 return TYPE_UNKNOWN;
6073 }
6074 \f
6075 /* The following collection of routines emit instruction group stop bits as
6076 necessary to avoid dependencies. */
6077
6078 /* Need to track some additional registers as far as serialization is
6079 concerned so we can properly handle br.call and br.ret. We could
6080 make these registers visible to gcc, but since these registers are
6081 never explicitly used in gcc generated code, it seems wasteful to
6082 do so (plus it would make the call and return patterns needlessly
6083 complex). */
6084 #define REG_RP (BR_REG (0))
6085 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
6086 /* This is used for volatile asms which may require a stop bit immediately
6087 before and after them. */
6088 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
6089 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
6090 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
6091
6092 /* For each register, we keep track of how it has been written in the
6093 current instruction group.
6094
6095 If a register is written unconditionally (no qualifying predicate),
6096 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
6097
6098 If a register is written if its qualifying predicate P is true, we
6099 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
6100 may be written again by the complement of P (P^1) and when this happens,
6101 WRITE_COUNT gets set to 2.
6102
6103 The result of this is that whenever an insn attempts to write a register
6104 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
6105
6106 If a predicate register is written by a floating-point insn, we set
6107 WRITTEN_BY_FP to true.
6108
6109 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
6110 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
6111
6112 #if GCC_VERSION >= 4000
6113 #define RWS_FIELD_TYPE __extension__ unsigned short
6114 #else
6115 #define RWS_FIELD_TYPE unsigned int
6116 #endif
6117 struct reg_write_state
6118 {
6119 RWS_FIELD_TYPE write_count : 2;
6120 RWS_FIELD_TYPE first_pred : 10;
6121 RWS_FIELD_TYPE written_by_fp : 1;
6122 RWS_FIELD_TYPE written_by_and : 1;
6123 RWS_FIELD_TYPE written_by_or : 1;
6124 };
6125
6126 /* Cumulative info for the current instruction group. */
6127 struct reg_write_state rws_sum[NUM_REGS];
6128 #ifdef ENABLE_CHECKING
6129 /* Bitmap whether a register has been written in the current insn. */
6130 HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1)
6131 / HOST_BITS_PER_WIDEST_FAST_INT];
6132
6133 static inline void
6134 rws_insn_set (int regno)
6135 {
6136 gcc_assert (!TEST_HARD_REG_BIT (rws_insn, regno));
6137 SET_HARD_REG_BIT (rws_insn, regno);
6138 }
6139
6140 static inline int
6141 rws_insn_test (int regno)
6142 {
6143 return TEST_HARD_REG_BIT (rws_insn, regno);
6144 }
6145 #else
6146 /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */
6147 unsigned char rws_insn[2];
6148
6149 static inline void
6150 rws_insn_set (int regno)
6151 {
6152 if (regno == REG_AR_CFM)
6153 rws_insn[0] = 1;
6154 else if (regno == REG_VOLATILE)
6155 rws_insn[1] = 1;
6156 }
6157
6158 static inline int
6159 rws_insn_test (int regno)
6160 {
6161 if (regno == REG_AR_CFM)
6162 return rws_insn[0];
6163 if (regno == REG_VOLATILE)
6164 return rws_insn[1];
6165 return 0;
6166 }
6167 #endif
6168
6169 /* Indicates whether this is the first instruction after a stop bit,
6170 in which case we don't need another stop bit. Without this,
6171 ia64_variable_issue will die when scheduling an alloc. */
6172 static int first_instruction;
6173
6174 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
6175 RTL for one instruction. */
6176 struct reg_flags
6177 {
6178 unsigned int is_write : 1; /* Is register being written? */
6179 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
6180 unsigned int is_branch : 1; /* Is register used as part of a branch? */
6181 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
6182 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
6183 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
6184 };
6185
6186 static void rws_update (int, struct reg_flags, int);
6187 static int rws_access_regno (int, struct reg_flags, int);
6188 static int rws_access_reg (rtx, struct reg_flags, int);
6189 static void update_set_flags (rtx, struct reg_flags *);
6190 static int set_src_needs_barrier (rtx, struct reg_flags, int);
6191 static int rtx_needs_barrier (rtx, struct reg_flags, int);
6192 static void init_insn_group_barriers (void);
6193 static int group_barrier_needed (rtx);
6194 static int safe_group_barrier_needed (rtx);
6195 static int in_safe_group_barrier;
6196
6197 /* Update *RWS for REGNO, which is being written by the current instruction,
6198 with predicate PRED, and associated register flags in FLAGS. */
6199
6200 static void
6201 rws_update (int regno, struct reg_flags flags, int pred)
6202 {
6203 if (pred)
6204 rws_sum[regno].write_count++;
6205 else
6206 rws_sum[regno].write_count = 2;
6207 rws_sum[regno].written_by_fp |= flags.is_fp;
6208 /* ??? Not tracking and/or across differing predicates. */
6209 rws_sum[regno].written_by_and = flags.is_and;
6210 rws_sum[regno].written_by_or = flags.is_or;
6211 rws_sum[regno].first_pred = pred;
6212 }
6213
6214 /* Handle an access to register REGNO of type FLAGS using predicate register
6215 PRED. Update rws_sum array. Return 1 if this access creates
6216 a dependency with an earlier instruction in the same group. */
6217
6218 static int
6219 rws_access_regno (int regno, struct reg_flags flags, int pred)
6220 {
6221 int need_barrier = 0;
6222
6223 gcc_assert (regno < NUM_REGS);
6224
6225 if (! PR_REGNO_P (regno))
6226 flags.is_and = flags.is_or = 0;
6227
6228 if (flags.is_write)
6229 {
6230 int write_count;
6231
6232 rws_insn_set (regno);
6233 write_count = rws_sum[regno].write_count;
6234
6235 switch (write_count)
6236 {
6237 case 0:
6238 /* The register has not been written yet. */
6239 if (!in_safe_group_barrier)
6240 rws_update (regno, flags, pred);
6241 break;
6242
6243 case 1:
6244 /* The register has been written via a predicate. Treat
6245 it like a unconditional write and do not try to check
6246 for complementary pred reg in earlier write. */
6247 if (flags.is_and && rws_sum[regno].written_by_and)
6248 ;
6249 else if (flags.is_or && rws_sum[regno].written_by_or)
6250 ;
6251 else
6252 need_barrier = 1;
6253 if (!in_safe_group_barrier)
6254 rws_update (regno, flags, pred);
6255 break;
6256
6257 case 2:
6258 /* The register has been unconditionally written already. We
6259 need a barrier. */
6260 if (flags.is_and && rws_sum[regno].written_by_and)
6261 ;
6262 else if (flags.is_or && rws_sum[regno].written_by_or)
6263 ;
6264 else
6265 need_barrier = 1;
6266 if (!in_safe_group_barrier)
6267 {
6268 rws_sum[regno].written_by_and = flags.is_and;
6269 rws_sum[regno].written_by_or = flags.is_or;
6270 }
6271 break;
6272
6273 default:
6274 gcc_unreachable ();
6275 }
6276 }
6277 else
6278 {
6279 if (flags.is_branch)
6280 {
6281 /* Branches have several RAW exceptions that allow to avoid
6282 barriers. */
6283
6284 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
6285 /* RAW dependencies on branch regs are permissible as long
6286 as the writer is a non-branch instruction. Since we
6287 never generate code that uses a branch register written
6288 by a branch instruction, handling this case is
6289 easy. */
6290 return 0;
6291
6292 if (REGNO_REG_CLASS (regno) == PR_REGS
6293 && ! rws_sum[regno].written_by_fp)
6294 /* The predicates of a branch are available within the
6295 same insn group as long as the predicate was written by
6296 something other than a floating-point instruction. */
6297 return 0;
6298 }
6299
6300 if (flags.is_and && rws_sum[regno].written_by_and)
6301 return 0;
6302 if (flags.is_or && rws_sum[regno].written_by_or)
6303 return 0;
6304
6305 switch (rws_sum[regno].write_count)
6306 {
6307 case 0:
6308 /* The register has not been written yet. */
6309 break;
6310
6311 case 1:
6312 /* The register has been written via a predicate, assume we
6313 need a barrier (don't check for complementary regs). */
6314 need_barrier = 1;
6315 break;
6316
6317 case 2:
6318 /* The register has been unconditionally written already. We
6319 need a barrier. */
6320 need_barrier = 1;
6321 break;
6322
6323 default:
6324 gcc_unreachable ();
6325 }
6326 }
6327
6328 return need_barrier;
6329 }
6330
6331 static int
6332 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
6333 {
6334 int regno = REGNO (reg);
6335 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
6336
6337 if (n == 1)
6338 return rws_access_regno (regno, flags, pred);
6339 else
6340 {
6341 int need_barrier = 0;
6342 while (--n >= 0)
6343 need_barrier |= rws_access_regno (regno + n, flags, pred);
6344 return need_barrier;
6345 }
6346 }
6347
6348 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
6349 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
6350
6351 static void
6352 update_set_flags (rtx x, struct reg_flags *pflags)
6353 {
6354 rtx src = SET_SRC (x);
6355
6356 switch (GET_CODE (src))
6357 {
6358 case CALL:
6359 return;
6360
6361 case IF_THEN_ELSE:
6362 /* There are four cases here:
6363 (1) The destination is (pc), in which case this is a branch,
6364 nothing here applies.
6365 (2) The destination is ar.lc, in which case this is a
6366 doloop_end_internal,
6367 (3) The destination is an fp register, in which case this is
6368 an fselect instruction.
6369 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
6370 this is a check load.
6371 In all cases, nothing we do in this function applies. */
6372 return;
6373
6374 default:
6375 if (COMPARISON_P (src)
6376 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0))))
6377 /* Set pflags->is_fp to 1 so that we know we're dealing
6378 with a floating point comparison when processing the
6379 destination of the SET. */
6380 pflags->is_fp = 1;
6381
6382 /* Discover if this is a parallel comparison. We only handle
6383 and.orcm and or.andcm at present, since we must retain a
6384 strict inverse on the predicate pair. */
6385 else if (GET_CODE (src) == AND)
6386 pflags->is_and = 1;
6387 else if (GET_CODE (src) == IOR)
6388 pflags->is_or = 1;
6389
6390 break;
6391 }
6392 }
6393
6394 /* Subroutine of rtx_needs_barrier; this function determines whether the
6395 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
6396 are as in rtx_needs_barrier. COND is an rtx that holds the condition
6397 for this insn. */
6398
6399 static int
6400 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred)
6401 {
6402 int need_barrier = 0;
6403 rtx dst;
6404 rtx src = SET_SRC (x);
6405
6406 if (GET_CODE (src) == CALL)
6407 /* We don't need to worry about the result registers that
6408 get written by subroutine call. */
6409 return rtx_needs_barrier (src, flags, pred);
6410 else if (SET_DEST (x) == pc_rtx)
6411 {
6412 /* X is a conditional branch. */
6413 /* ??? This seems redundant, as the caller sets this bit for
6414 all JUMP_INSNs. */
6415 if (!ia64_spec_check_src_p (src))
6416 flags.is_branch = 1;
6417 return rtx_needs_barrier (src, flags, pred);
6418 }
6419
6420 if (ia64_spec_check_src_p (src))
6421 /* Avoid checking one register twice (in condition
6422 and in 'then' section) for ldc pattern. */
6423 {
6424 gcc_assert (REG_P (XEXP (src, 2)));
6425 need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred);
6426
6427 /* We process MEM below. */
6428 src = XEXP (src, 1);
6429 }
6430
6431 need_barrier |= rtx_needs_barrier (src, flags, pred);
6432
6433 dst = SET_DEST (x);
6434 if (GET_CODE (dst) == ZERO_EXTRACT)
6435 {
6436 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
6437 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
6438 }
6439 return need_barrier;
6440 }
6441
6442 /* Handle an access to rtx X of type FLAGS using predicate register
6443 PRED. Return 1 if this access creates a dependency with an earlier
6444 instruction in the same group. */
6445
6446 static int
6447 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
6448 {
6449 int i, j;
6450 int is_complemented = 0;
6451 int need_barrier = 0;
6452 const char *format_ptr;
6453 struct reg_flags new_flags;
6454 rtx cond;
6455
6456 if (! x)
6457 return 0;
6458
6459 new_flags = flags;
6460
6461 switch (GET_CODE (x))
6462 {
6463 case SET:
6464 update_set_flags (x, &new_flags);
6465 need_barrier = set_src_needs_barrier (x, new_flags, pred);
6466 if (GET_CODE (SET_SRC (x)) != CALL)
6467 {
6468 new_flags.is_write = 1;
6469 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
6470 }
6471 break;
6472
6473 case CALL:
6474 new_flags.is_write = 0;
6475 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6476
6477 /* Avoid multiple register writes, in case this is a pattern with
6478 multiple CALL rtx. This avoids a failure in rws_access_reg. */
6479 if (! flags.is_sibcall && ! rws_insn_test (REG_AR_CFM))
6480 {
6481 new_flags.is_write = 1;
6482 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
6483 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
6484 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6485 }
6486 break;
6487
6488 case COND_EXEC:
6489 /* X is a predicated instruction. */
6490
6491 cond = COND_EXEC_TEST (x);
6492 gcc_assert (!pred);
6493 need_barrier = rtx_needs_barrier (cond, flags, 0);
6494
6495 if (GET_CODE (cond) == EQ)
6496 is_complemented = 1;
6497 cond = XEXP (cond, 0);
6498 gcc_assert (GET_CODE (cond) == REG
6499 && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
6500 pred = REGNO (cond);
6501 if (is_complemented)
6502 ++pred;
6503
6504 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
6505 return need_barrier;
6506
6507 case CLOBBER:
6508 case USE:
6509 /* Clobber & use are for earlier compiler-phases only. */
6510 break;
6511
6512 case ASM_OPERANDS:
6513 case ASM_INPUT:
6514 /* We always emit stop bits for traditional asms. We emit stop bits
6515 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
6516 if (GET_CODE (x) != ASM_OPERANDS
6517 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
6518 {
6519 /* Avoid writing the register multiple times if we have multiple
6520 asm outputs. This avoids a failure in rws_access_reg. */
6521 if (! rws_insn_test (REG_VOLATILE))
6522 {
6523 new_flags.is_write = 1;
6524 rws_access_regno (REG_VOLATILE, new_flags, pred);
6525 }
6526 return 1;
6527 }
6528
6529 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
6530 We cannot just fall through here since then we would be confused
6531 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
6532 traditional asms unlike their normal usage. */
6533
6534 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
6535 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
6536 need_barrier = 1;
6537 break;
6538
6539 case PARALLEL:
6540 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6541 {
6542 rtx pat = XVECEXP (x, 0, i);
6543 switch (GET_CODE (pat))
6544 {
6545 case SET:
6546 update_set_flags (pat, &new_flags);
6547 need_barrier |= set_src_needs_barrier (pat, new_flags, pred);
6548 break;
6549
6550 case USE:
6551 case CALL:
6552 case ASM_OPERANDS:
6553 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6554 break;
6555
6556 case CLOBBER:
6557 if (REG_P (XEXP (pat, 0))
6558 && extract_asm_operands (x) != NULL_RTX
6559 && REGNO (XEXP (pat, 0)) != AR_UNAT_REGNUM)
6560 {
6561 new_flags.is_write = 1;
6562 need_barrier |= rtx_needs_barrier (XEXP (pat, 0),
6563 new_flags, pred);
6564 new_flags = flags;
6565 }
6566 break;
6567
6568 case RETURN:
6569 break;
6570
6571 default:
6572 gcc_unreachable ();
6573 }
6574 }
6575 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6576 {
6577 rtx pat = XVECEXP (x, 0, i);
6578 if (GET_CODE (pat) == SET)
6579 {
6580 if (GET_CODE (SET_SRC (pat)) != CALL)
6581 {
6582 new_flags.is_write = 1;
6583 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
6584 pred);
6585 }
6586 }
6587 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
6588 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6589 }
6590 break;
6591
6592 case SUBREG:
6593 need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred);
6594 break;
6595 case REG:
6596 if (REGNO (x) == AR_UNAT_REGNUM)
6597 {
6598 for (i = 0; i < 64; ++i)
6599 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
6600 }
6601 else
6602 need_barrier = rws_access_reg (x, flags, pred);
6603 break;
6604
6605 case MEM:
6606 /* Find the regs used in memory address computation. */
6607 new_flags.is_write = 0;
6608 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6609 break;
6610
6611 case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR:
6612 case SYMBOL_REF: case LABEL_REF: case CONST:
6613 break;
6614
6615 /* Operators with side-effects. */
6616 case POST_INC: case POST_DEC:
6617 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6618
6619 new_flags.is_write = 0;
6620 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6621 new_flags.is_write = 1;
6622 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6623 break;
6624
6625 case POST_MODIFY:
6626 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6627
6628 new_flags.is_write = 0;
6629 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6630 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6631 new_flags.is_write = 1;
6632 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6633 break;
6634
6635 /* Handle common unary and binary ops for efficiency. */
6636 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
6637 case MOD: case UDIV: case UMOD: case AND: case IOR:
6638 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
6639 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
6640 case NE: case EQ: case GE: case GT: case LE:
6641 case LT: case GEU: case GTU: case LEU: case LTU:
6642 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6643 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6644 break;
6645
6646 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
6647 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
6648 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
6649 case SQRT: case FFS: case POPCOUNT:
6650 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6651 break;
6652
6653 case VEC_SELECT:
6654 /* VEC_SELECT's second argument is a PARALLEL with integers that
6655 describe the elements selected. On ia64, those integers are
6656 always constants. Avoid walking the PARALLEL so that we don't
6657 get confused with "normal" parallels and then die. */
6658 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6659 break;
6660
6661 case UNSPEC:
6662 switch (XINT (x, 1))
6663 {
6664 case UNSPEC_LTOFF_DTPMOD:
6665 case UNSPEC_LTOFF_DTPREL:
6666 case UNSPEC_DTPREL:
6667 case UNSPEC_LTOFF_TPREL:
6668 case UNSPEC_TPREL:
6669 case UNSPEC_PRED_REL_MUTEX:
6670 case UNSPEC_PIC_CALL:
6671 case UNSPEC_MF:
6672 case UNSPEC_FETCHADD_ACQ:
6673 case UNSPEC_FETCHADD_REL:
6674 case UNSPEC_BSP_VALUE:
6675 case UNSPEC_FLUSHRS:
6676 case UNSPEC_BUNDLE_SELECTOR:
6677 break;
6678
6679 case UNSPEC_GR_SPILL:
6680 case UNSPEC_GR_RESTORE:
6681 {
6682 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
6683 HOST_WIDE_INT bit = (offset >> 3) & 63;
6684
6685 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6686 new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL);
6687 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
6688 new_flags, pred);
6689 break;
6690 }
6691
6692 case UNSPEC_FR_SPILL:
6693 case UNSPEC_FR_RESTORE:
6694 case UNSPEC_GETF_EXP:
6695 case UNSPEC_SETF_EXP:
6696 case UNSPEC_ADDP4:
6697 case UNSPEC_FR_SQRT_RECIP_APPROX:
6698 case UNSPEC_FR_SQRT_RECIP_APPROX_RES:
6699 case UNSPEC_LDA:
6700 case UNSPEC_LDS:
6701 case UNSPEC_LDS_A:
6702 case UNSPEC_LDSA:
6703 case UNSPEC_CHKACLR:
6704 case UNSPEC_CHKS:
6705 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6706 break;
6707
6708 case UNSPEC_FR_RECIP_APPROX:
6709 case UNSPEC_SHRP:
6710 case UNSPEC_COPYSIGN:
6711 case UNSPEC_FR_RECIP_APPROX_RES:
6712 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6713 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6714 break;
6715
6716 case UNSPEC_CMPXCHG_ACQ:
6717 case UNSPEC_CMPXCHG_REL:
6718 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6719 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
6720 break;
6721
6722 default:
6723 gcc_unreachable ();
6724 }
6725 break;
6726
6727 case UNSPEC_VOLATILE:
6728 switch (XINT (x, 1))
6729 {
6730 case UNSPECV_ALLOC:
6731 /* Alloc must always be the first instruction of a group.
6732 We force this by always returning true. */
6733 /* ??? We might get better scheduling if we explicitly check for
6734 input/local/output register dependencies, and modify the
6735 scheduler so that alloc is always reordered to the start of
6736 the current group. We could then eliminate all of the
6737 first_instruction code. */
6738 rws_access_regno (AR_PFS_REGNUM, flags, pred);
6739
6740 new_flags.is_write = 1;
6741 rws_access_regno (REG_AR_CFM, new_flags, pred);
6742 return 1;
6743
6744 case UNSPECV_SET_BSP:
6745 case UNSPECV_PROBE_STACK_RANGE:
6746 need_barrier = 1;
6747 break;
6748
6749 case UNSPECV_BLOCKAGE:
6750 case UNSPECV_INSN_GROUP_BARRIER:
6751 case UNSPECV_BREAK:
6752 case UNSPECV_PSAC_ALL:
6753 case UNSPECV_PSAC_NORMAL:
6754 return 0;
6755
6756 case UNSPECV_PROBE_STACK_ADDRESS:
6757 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6758 break;
6759
6760 default:
6761 gcc_unreachable ();
6762 }
6763 break;
6764
6765 case RETURN:
6766 new_flags.is_write = 0;
6767 need_barrier = rws_access_regno (REG_RP, flags, pred);
6768 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
6769
6770 new_flags.is_write = 1;
6771 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6772 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6773 break;
6774
6775 default:
6776 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
6777 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6778 switch (format_ptr[i])
6779 {
6780 case '0': /* unused field */
6781 case 'i': /* integer */
6782 case 'n': /* note */
6783 case 'w': /* wide integer */
6784 case 's': /* pointer to string */
6785 case 'S': /* optional pointer to string */
6786 break;
6787
6788 case 'e':
6789 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
6790 need_barrier = 1;
6791 break;
6792
6793 case 'E':
6794 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
6795 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
6796 need_barrier = 1;
6797 break;
6798
6799 default:
6800 gcc_unreachable ();
6801 }
6802 break;
6803 }
6804 return need_barrier;
6805 }
6806
6807 /* Clear out the state for group_barrier_needed at the start of a
6808 sequence of insns. */
6809
6810 static void
6811 init_insn_group_barriers (void)
6812 {
6813 memset (rws_sum, 0, sizeof (rws_sum));
6814 first_instruction = 1;
6815 }
6816
6817 /* Given the current state, determine whether a group barrier (a stop bit) is
6818 necessary before INSN. Return nonzero if so. This modifies the state to
6819 include the effects of INSN as a side-effect. */
6820
6821 static int
6822 group_barrier_needed (rtx insn)
6823 {
6824 rtx pat;
6825 int need_barrier = 0;
6826 struct reg_flags flags;
6827
6828 memset (&flags, 0, sizeof (flags));
6829 switch (GET_CODE (insn))
6830 {
6831 case NOTE:
6832 case DEBUG_INSN:
6833 break;
6834
6835 case BARRIER:
6836 /* A barrier doesn't imply an instruction group boundary. */
6837 break;
6838
6839 case CODE_LABEL:
6840 memset (rws_insn, 0, sizeof (rws_insn));
6841 return 1;
6842
6843 case CALL_INSN:
6844 flags.is_branch = 1;
6845 flags.is_sibcall = SIBLING_CALL_P (insn);
6846 memset (rws_insn, 0, sizeof (rws_insn));
6847
6848 /* Don't bundle a call following another call. */
6849 if ((pat = prev_active_insn (insn)) && CALL_P (pat))
6850 {
6851 need_barrier = 1;
6852 break;
6853 }
6854
6855 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
6856 break;
6857
6858 case JUMP_INSN:
6859 if (!ia64_spec_check_p (insn))
6860 flags.is_branch = 1;
6861
6862 /* Don't bundle a jump following a call. */
6863 if ((pat = prev_active_insn (insn)) && CALL_P (pat))
6864 {
6865 need_barrier = 1;
6866 break;
6867 }
6868 /* FALLTHRU */
6869
6870 case INSN:
6871 if (GET_CODE (PATTERN (insn)) == USE
6872 || GET_CODE (PATTERN (insn)) == CLOBBER)
6873 /* Don't care about USE and CLOBBER "insns"---those are used to
6874 indicate to the optimizer that it shouldn't get rid of
6875 certain operations. */
6876 break;
6877
6878 pat = PATTERN (insn);
6879
6880 /* Ug. Hack hacks hacked elsewhere. */
6881 switch (recog_memoized (insn))
6882 {
6883 /* We play dependency tricks with the epilogue in order
6884 to get proper schedules. Undo this for dv analysis. */
6885 case CODE_FOR_epilogue_deallocate_stack:
6886 case CODE_FOR_prologue_allocate_stack:
6887 pat = XVECEXP (pat, 0, 0);
6888 break;
6889
6890 /* The pattern we use for br.cloop confuses the code above.
6891 The second element of the vector is representative. */
6892 case CODE_FOR_doloop_end_internal:
6893 pat = XVECEXP (pat, 0, 1);
6894 break;
6895
6896 /* Doesn't generate code. */
6897 case CODE_FOR_pred_rel_mutex:
6898 case CODE_FOR_prologue_use:
6899 return 0;
6900
6901 default:
6902 break;
6903 }
6904
6905 memset (rws_insn, 0, sizeof (rws_insn));
6906 need_barrier = rtx_needs_barrier (pat, flags, 0);
6907
6908 /* Check to see if the previous instruction was a volatile
6909 asm. */
6910 if (! need_barrier)
6911 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
6912
6913 break;
6914
6915 default:
6916 gcc_unreachable ();
6917 }
6918
6919 if (first_instruction && important_for_bundling_p (insn))
6920 {
6921 need_barrier = 0;
6922 first_instruction = 0;
6923 }
6924
6925 return need_barrier;
6926 }
6927
6928 /* Like group_barrier_needed, but do not clobber the current state. */
6929
6930 static int
6931 safe_group_barrier_needed (rtx insn)
6932 {
6933 int saved_first_instruction;
6934 int t;
6935
6936 saved_first_instruction = first_instruction;
6937 in_safe_group_barrier = 1;
6938
6939 t = group_barrier_needed (insn);
6940
6941 first_instruction = saved_first_instruction;
6942 in_safe_group_barrier = 0;
6943
6944 return t;
6945 }
6946
6947 /* Scan the current function and insert stop bits as necessary to
6948 eliminate dependencies. This function assumes that a final
6949 instruction scheduling pass has been run which has already
6950 inserted most of the necessary stop bits. This function only
6951 inserts new ones at basic block boundaries, since these are
6952 invisible to the scheduler. */
6953
6954 static void
6955 emit_insn_group_barriers (FILE *dump)
6956 {
6957 rtx_insn *insn;
6958 rtx_insn *last_label = 0;
6959 int insns_since_last_label = 0;
6960
6961 init_insn_group_barriers ();
6962
6963 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6964 {
6965 if (LABEL_P (insn))
6966 {
6967 if (insns_since_last_label)
6968 last_label = insn;
6969 insns_since_last_label = 0;
6970 }
6971 else if (NOTE_P (insn)
6972 && NOTE_KIND (insn) == NOTE_INSN_BASIC_BLOCK)
6973 {
6974 if (insns_since_last_label)
6975 last_label = insn;
6976 insns_since_last_label = 0;
6977 }
6978 else if (NONJUMP_INSN_P (insn)
6979 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
6980 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
6981 {
6982 init_insn_group_barriers ();
6983 last_label = 0;
6984 }
6985 else if (NONDEBUG_INSN_P (insn))
6986 {
6987 insns_since_last_label = 1;
6988
6989 if (group_barrier_needed (insn))
6990 {
6991 if (last_label)
6992 {
6993 if (dump)
6994 fprintf (dump, "Emitting stop before label %d\n",
6995 INSN_UID (last_label));
6996 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
6997 insn = last_label;
6998
6999 init_insn_group_barriers ();
7000 last_label = 0;
7001 }
7002 }
7003 }
7004 }
7005 }
7006
7007 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
7008 This function has to emit all necessary group barriers. */
7009
7010 static void
7011 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
7012 {
7013 rtx_insn *insn;
7014
7015 init_insn_group_barriers ();
7016
7017 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7018 {
7019 if (BARRIER_P (insn))
7020 {
7021 rtx_insn *last = prev_active_insn (insn);
7022
7023 if (! last)
7024 continue;
7025 if (JUMP_TABLE_DATA_P (last))
7026 last = prev_active_insn (last);
7027 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
7028 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
7029
7030 init_insn_group_barriers ();
7031 }
7032 else if (NONDEBUG_INSN_P (insn))
7033 {
7034 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
7035 init_insn_group_barriers ();
7036 else if (group_barrier_needed (insn))
7037 {
7038 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
7039 init_insn_group_barriers ();
7040 group_barrier_needed (insn);
7041 }
7042 }
7043 }
7044 }
7045
7046 \f
7047
7048 /* Instruction scheduling support. */
7049
7050 #define NR_BUNDLES 10
7051
7052 /* A list of names of all available bundles. */
7053
7054 static const char *bundle_name [NR_BUNDLES] =
7055 {
7056 ".mii",
7057 ".mmi",
7058 ".mfi",
7059 ".mmf",
7060 #if NR_BUNDLES == 10
7061 ".bbb",
7062 ".mbb",
7063 #endif
7064 ".mib",
7065 ".mmb",
7066 ".mfb",
7067 ".mlx"
7068 };
7069
7070 /* Nonzero if we should insert stop bits into the schedule. */
7071
7072 int ia64_final_schedule = 0;
7073
7074 /* Codes of the corresponding queried units: */
7075
7076 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
7077 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
7078
7079 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
7080 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
7081
7082 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
7083
7084 /* The following variable value is an insn group barrier. */
7085
7086 static rtx_insn *dfa_stop_insn;
7087
7088 /* The following variable value is the last issued insn. */
7089
7090 static rtx last_scheduled_insn;
7091
7092 /* The following variable value is pointer to a DFA state used as
7093 temporary variable. */
7094
7095 static state_t temp_dfa_state = NULL;
7096
7097 /* The following variable value is DFA state after issuing the last
7098 insn. */
7099
7100 static state_t prev_cycle_state = NULL;
7101
7102 /* The following array element values are TRUE if the corresponding
7103 insn requires to add stop bits before it. */
7104
7105 static char *stops_p = NULL;
7106
7107 /* The following variable is used to set up the mentioned above array. */
7108
7109 static int stop_before_p = 0;
7110
7111 /* The following variable value is length of the arrays `clocks' and
7112 `add_cycles'. */
7113
7114 static int clocks_length;
7115
7116 /* The following variable value is number of data speculations in progress. */
7117 static int pending_data_specs = 0;
7118
7119 /* Number of memory references on current and three future processor cycles. */
7120 static char mem_ops_in_group[4];
7121
7122 /* Number of current processor cycle (from scheduler's point of view). */
7123 static int current_cycle;
7124
7125 static rtx ia64_single_set (rtx);
7126 static void ia64_emit_insn_before (rtx, rtx);
7127
7128 /* Map a bundle number to its pseudo-op. */
7129
7130 const char *
7131 get_bundle_name (int b)
7132 {
7133 return bundle_name[b];
7134 }
7135
7136
7137 /* Return the maximum number of instructions a cpu can issue. */
7138
7139 static int
7140 ia64_issue_rate (void)
7141 {
7142 return 6;
7143 }
7144
7145 /* Helper function - like single_set, but look inside COND_EXEC. */
7146
7147 static rtx
7148 ia64_single_set (rtx insn)
7149 {
7150 rtx x = PATTERN (insn), ret;
7151 if (GET_CODE (x) == COND_EXEC)
7152 x = COND_EXEC_CODE (x);
7153 if (GET_CODE (x) == SET)
7154 return x;
7155
7156 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
7157 Although they are not classical single set, the second set is there just
7158 to protect it from moving past FP-relative stack accesses. */
7159 switch (recog_memoized (insn))
7160 {
7161 case CODE_FOR_prologue_allocate_stack:
7162 case CODE_FOR_prologue_allocate_stack_pr:
7163 case CODE_FOR_epilogue_deallocate_stack:
7164 case CODE_FOR_epilogue_deallocate_stack_pr:
7165 ret = XVECEXP (x, 0, 0);
7166 break;
7167
7168 default:
7169 ret = single_set_2 (insn, x);
7170 break;
7171 }
7172
7173 return ret;
7174 }
7175
7176 /* Adjust the cost of a scheduling dependency.
7177 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
7178 COST is the current cost, DW is dependency weakness. */
7179 static int
7180 ia64_adjust_cost_2 (rtx_insn *insn, int dep_type1, rtx_insn *dep_insn,
7181 int cost, dw_t dw)
7182 {
7183 enum reg_note dep_type = (enum reg_note) dep_type1;
7184 enum attr_itanium_class dep_class;
7185 enum attr_itanium_class insn_class;
7186
7187 insn_class = ia64_safe_itanium_class (insn);
7188 dep_class = ia64_safe_itanium_class (dep_insn);
7189
7190 /* Treat true memory dependencies separately. Ignore apparent true
7191 dependence between store and call (call has a MEM inside a SYMBOL_REF). */
7192 if (dep_type == REG_DEP_TRUE
7193 && (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF)
7194 && (insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL))
7195 return 0;
7196
7197 if (dw == MIN_DEP_WEAK)
7198 /* Store and load are likely to alias, use higher cost to avoid stall. */
7199 return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST);
7200 else if (dw > MIN_DEP_WEAK)
7201 {
7202 /* Store and load are less likely to alias. */
7203 if (mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF)
7204 /* Assume there will be no cache conflict for floating-point data.
7205 For integer data, L1 conflict penalty is huge (17 cycles), so we
7206 never assume it will not cause a conflict. */
7207 return 0;
7208 else
7209 return cost;
7210 }
7211
7212 if (dep_type != REG_DEP_OUTPUT)
7213 return cost;
7214
7215 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
7216 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
7217 return 0;
7218
7219 return cost;
7220 }
7221
7222 /* Like emit_insn_before, but skip cycle_display notes.
7223 ??? When cycle display notes are implemented, update this. */
7224
7225 static void
7226 ia64_emit_insn_before (rtx insn, rtx before)
7227 {
7228 emit_insn_before (insn, before);
7229 }
7230
7231 /* The following function marks insns who produce addresses for load
7232 and store insns. Such insns will be placed into M slots because it
7233 decrease latency time for Itanium1 (see function
7234 `ia64_produce_address_p' and the DFA descriptions). */
7235
7236 static void
7237 ia64_dependencies_evaluation_hook (rtx_insn *head, rtx_insn *tail)
7238 {
7239 rtx_insn *insn, *next, *next_tail;
7240
7241 /* Before reload, which_alternative is not set, which means that
7242 ia64_safe_itanium_class will produce wrong results for (at least)
7243 move instructions. */
7244 if (!reload_completed)
7245 return;
7246
7247 next_tail = NEXT_INSN (tail);
7248 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
7249 if (INSN_P (insn))
7250 insn->call = 0;
7251 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
7252 if (INSN_P (insn)
7253 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
7254 {
7255 sd_iterator_def sd_it;
7256 dep_t dep;
7257 bool has_mem_op_consumer_p = false;
7258
7259 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
7260 {
7261 enum attr_itanium_class c;
7262
7263 if (DEP_TYPE (dep) != REG_DEP_TRUE)
7264 continue;
7265
7266 next = DEP_CON (dep);
7267 c = ia64_safe_itanium_class (next);
7268 if ((c == ITANIUM_CLASS_ST
7269 || c == ITANIUM_CLASS_STF)
7270 && ia64_st_address_bypass_p (insn, next))
7271 {
7272 has_mem_op_consumer_p = true;
7273 break;
7274 }
7275 else if ((c == ITANIUM_CLASS_LD
7276 || c == ITANIUM_CLASS_FLD
7277 || c == ITANIUM_CLASS_FLDP)
7278 && ia64_ld_address_bypass_p (insn, next))
7279 {
7280 has_mem_op_consumer_p = true;
7281 break;
7282 }
7283 }
7284
7285 insn->call = has_mem_op_consumer_p;
7286 }
7287 }
7288
7289 /* We're beginning a new block. Initialize data structures as necessary. */
7290
7291 static void
7292 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7293 int sched_verbose ATTRIBUTE_UNUSED,
7294 int max_ready ATTRIBUTE_UNUSED)
7295 {
7296 #ifdef ENABLE_CHECKING
7297 rtx insn;
7298
7299 if (!sel_sched_p () && reload_completed)
7300 for (insn = NEXT_INSN (current_sched_info->prev_head);
7301 insn != current_sched_info->next_tail;
7302 insn = NEXT_INSN (insn))
7303 gcc_assert (!SCHED_GROUP_P (insn));
7304 #endif
7305 last_scheduled_insn = NULL_RTX;
7306 init_insn_group_barriers ();
7307
7308 current_cycle = 0;
7309 memset (mem_ops_in_group, 0, sizeof (mem_ops_in_group));
7310 }
7311
7312 /* We're beginning a scheduling pass. Check assertion. */
7313
7314 static void
7315 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
7316 int sched_verbose ATTRIBUTE_UNUSED,
7317 int max_ready ATTRIBUTE_UNUSED)
7318 {
7319 gcc_assert (pending_data_specs == 0);
7320 }
7321
7322 /* Scheduling pass is now finished. Free/reset static variable. */
7323 static void
7324 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED,
7325 int sched_verbose ATTRIBUTE_UNUSED)
7326 {
7327 gcc_assert (pending_data_specs == 0);
7328 }
7329
7330 /* Return TRUE if INSN is a load (either normal or speculative, but not a
7331 speculation check), FALSE otherwise. */
7332 static bool
7333 is_load_p (rtx insn)
7334 {
7335 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
7336
7337 return
7338 ((insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD)
7339 && get_attr_check_load (insn) == CHECK_LOAD_NO);
7340 }
7341
7342 /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array
7343 (taking account for 3-cycle cache reference postponing for stores: Intel
7344 Itanium 2 Reference Manual for Software Development and Optimization,
7345 6.7.3.1). */
7346 static void
7347 record_memory_reference (rtx insn)
7348 {
7349 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
7350
7351 switch (insn_class) {
7352 case ITANIUM_CLASS_FLD:
7353 case ITANIUM_CLASS_LD:
7354 mem_ops_in_group[current_cycle % 4]++;
7355 break;
7356 case ITANIUM_CLASS_STF:
7357 case ITANIUM_CLASS_ST:
7358 mem_ops_in_group[(current_cycle + 3) % 4]++;
7359 break;
7360 default:;
7361 }
7362 }
7363
7364 /* We are about to being issuing insns for this clock cycle.
7365 Override the default sort algorithm to better slot instructions. */
7366
7367 static int
7368 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx_insn **ready,
7369 int *pn_ready, int clock_var,
7370 int reorder_type)
7371 {
7372 int n_asms;
7373 int n_ready = *pn_ready;
7374 rtx_insn **e_ready = ready + n_ready;
7375 rtx_insn **insnp;
7376
7377 if (sched_verbose)
7378 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
7379
7380 if (reorder_type == 0)
7381 {
7382 /* First, move all USEs, CLOBBERs and other crud out of the way. */
7383 n_asms = 0;
7384 for (insnp = ready; insnp < e_ready; insnp++)
7385 if (insnp < e_ready)
7386 {
7387 rtx_insn *insn = *insnp;
7388 enum attr_type t = ia64_safe_type (insn);
7389 if (t == TYPE_UNKNOWN)
7390 {
7391 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
7392 || asm_noperands (PATTERN (insn)) >= 0)
7393 {
7394 rtx_insn *lowest = ready[n_asms];
7395 ready[n_asms] = insn;
7396 *insnp = lowest;
7397 n_asms++;
7398 }
7399 else
7400 {
7401 rtx_insn *highest = ready[n_ready - 1];
7402 ready[n_ready - 1] = insn;
7403 *insnp = highest;
7404 return 1;
7405 }
7406 }
7407 }
7408
7409 if (n_asms < n_ready)
7410 {
7411 /* Some normal insns to process. Skip the asms. */
7412 ready += n_asms;
7413 n_ready -= n_asms;
7414 }
7415 else if (n_ready > 0)
7416 return 1;
7417 }
7418
7419 if (ia64_final_schedule)
7420 {
7421 int deleted = 0;
7422 int nr_need_stop = 0;
7423
7424 for (insnp = ready; insnp < e_ready; insnp++)
7425 if (safe_group_barrier_needed (*insnp))
7426 nr_need_stop++;
7427
7428 if (reorder_type == 1 && n_ready == nr_need_stop)
7429 return 0;
7430 if (reorder_type == 0)
7431 return 1;
7432 insnp = e_ready;
7433 /* Move down everything that needs a stop bit, preserving
7434 relative order. */
7435 while (insnp-- > ready + deleted)
7436 while (insnp >= ready + deleted)
7437 {
7438 rtx_insn *insn = *insnp;
7439 if (! safe_group_barrier_needed (insn))
7440 break;
7441 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
7442 *ready = insn;
7443 deleted++;
7444 }
7445 n_ready -= deleted;
7446 ready += deleted;
7447 }
7448
7449 current_cycle = clock_var;
7450 if (reload_completed && mem_ops_in_group[clock_var % 4] >= ia64_max_memory_insns)
7451 {
7452 int moved = 0;
7453
7454 insnp = e_ready;
7455 /* Move down loads/stores, preserving relative order. */
7456 while (insnp-- > ready + moved)
7457 while (insnp >= ready + moved)
7458 {
7459 rtx_insn *insn = *insnp;
7460 if (! is_load_p (insn))
7461 break;
7462 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
7463 *ready = insn;
7464 moved++;
7465 }
7466 n_ready -= moved;
7467 ready += moved;
7468 }
7469
7470 return 1;
7471 }
7472
7473 /* We are about to being issuing insns for this clock cycle. Override
7474 the default sort algorithm to better slot instructions. */
7475
7476 static int
7477 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx_insn **ready,
7478 int *pn_ready, int clock_var)
7479 {
7480 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
7481 pn_ready, clock_var, 0);
7482 }
7483
7484 /* Like ia64_sched_reorder, but called after issuing each insn.
7485 Override the default sort algorithm to better slot instructions. */
7486
7487 static int
7488 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
7489 int sched_verbose ATTRIBUTE_UNUSED, rtx_insn **ready,
7490 int *pn_ready, int clock_var)
7491 {
7492 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
7493 clock_var, 1);
7494 }
7495
7496 /* We are about to issue INSN. Return the number of insns left on the
7497 ready queue that can be issued this cycle. */
7498
7499 static int
7500 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
7501 int sched_verbose ATTRIBUTE_UNUSED,
7502 rtx_insn *insn,
7503 int can_issue_more ATTRIBUTE_UNUSED)
7504 {
7505 if (sched_deps_info->generate_spec_deps && !sel_sched_p ())
7506 /* Modulo scheduling does not extend h_i_d when emitting
7507 new instructions. Don't use h_i_d, if we don't have to. */
7508 {
7509 if (DONE_SPEC (insn) & BEGIN_DATA)
7510 pending_data_specs++;
7511 if (CHECK_SPEC (insn) & BEGIN_DATA)
7512 pending_data_specs--;
7513 }
7514
7515 if (DEBUG_INSN_P (insn))
7516 return 1;
7517
7518 last_scheduled_insn = insn;
7519 memcpy (prev_cycle_state, curr_state, dfa_state_size);
7520 if (reload_completed)
7521 {
7522 int needed = group_barrier_needed (insn);
7523
7524 gcc_assert (!needed);
7525 if (CALL_P (insn))
7526 init_insn_group_barriers ();
7527 stops_p [INSN_UID (insn)] = stop_before_p;
7528 stop_before_p = 0;
7529
7530 record_memory_reference (insn);
7531 }
7532 return 1;
7533 }
7534
7535 /* We are choosing insn from the ready queue. Return zero if INSN
7536 can be chosen. */
7537
7538 static int
7539 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx_insn *insn, int ready_index)
7540 {
7541 gcc_assert (insn && INSN_P (insn));
7542
7543 /* Size of ALAT is 32. As far as we perform conservative
7544 data speculation, we keep ALAT half-empty. */
7545 if (pending_data_specs >= 16 && (TODO_SPEC (insn) & BEGIN_DATA))
7546 return ready_index == 0 ? -1 : 1;
7547
7548 if (ready_index == 0)
7549 return 0;
7550
7551 if ((!reload_completed
7552 || !safe_group_barrier_needed (insn))
7553 && (!mflag_sched_mem_insns_hard_limit
7554 || !is_load_p (insn)
7555 || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns))
7556 return 0;
7557
7558 return 1;
7559 }
7560
7561 /* The following variable value is pseudo-insn used by the DFA insn
7562 scheduler to change the DFA state when the simulated clock is
7563 increased. */
7564
7565 static rtx_insn *dfa_pre_cycle_insn;
7566
7567 /* Returns 1 when a meaningful insn was scheduled between the last group
7568 barrier and LAST. */
7569 static int
7570 scheduled_good_insn (rtx last)
7571 {
7572 if (last && recog_memoized (last) >= 0)
7573 return 1;
7574
7575 for ( ;
7576 last != NULL && !NOTE_INSN_BASIC_BLOCK_P (last)
7577 && !stops_p[INSN_UID (last)];
7578 last = PREV_INSN (last))
7579 /* We could hit a NOTE_INSN_DELETED here which is actually outside
7580 the ebb we're scheduling. */
7581 if (INSN_P (last) && recog_memoized (last) >= 0)
7582 return 1;
7583
7584 return 0;
7585 }
7586
7587 /* We are about to being issuing INSN. Return nonzero if we cannot
7588 issue it on given cycle CLOCK and return zero if we should not sort
7589 the ready queue on the next clock start. */
7590
7591 static int
7592 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx_insn *insn, int last_clock,
7593 int clock, int *sort_p)
7594 {
7595 gcc_assert (insn && INSN_P (insn));
7596
7597 if (DEBUG_INSN_P (insn))
7598 return 0;
7599
7600 /* When a group barrier is needed for insn, last_scheduled_insn
7601 should be set. */
7602 gcc_assert (!(reload_completed && safe_group_barrier_needed (insn))
7603 || last_scheduled_insn);
7604
7605 if ((reload_completed
7606 && (safe_group_barrier_needed (insn)
7607 || (mflag_sched_stop_bits_after_every_cycle
7608 && last_clock != clock
7609 && last_scheduled_insn
7610 && scheduled_good_insn (last_scheduled_insn))))
7611 || (last_scheduled_insn
7612 && (CALL_P (last_scheduled_insn)
7613 || unknown_for_bundling_p (last_scheduled_insn))))
7614 {
7615 init_insn_group_barriers ();
7616
7617 if (verbose && dump)
7618 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
7619 last_clock == clock ? " + cycle advance" : "");
7620
7621 stop_before_p = 1;
7622 current_cycle = clock;
7623 mem_ops_in_group[current_cycle % 4] = 0;
7624
7625 if (last_clock == clock)
7626 {
7627 state_transition (curr_state, dfa_stop_insn);
7628 if (TARGET_EARLY_STOP_BITS)
7629 *sort_p = (last_scheduled_insn == NULL_RTX
7630 || ! CALL_P (last_scheduled_insn));
7631 else
7632 *sort_p = 0;
7633 return 1;
7634 }
7635
7636 if (last_scheduled_insn)
7637 {
7638 if (unknown_for_bundling_p (last_scheduled_insn))
7639 state_reset (curr_state);
7640 else
7641 {
7642 memcpy (curr_state, prev_cycle_state, dfa_state_size);
7643 state_transition (curr_state, dfa_stop_insn);
7644 state_transition (curr_state, dfa_pre_cycle_insn);
7645 state_transition (curr_state, NULL);
7646 }
7647 }
7648 }
7649 return 0;
7650 }
7651
7652 /* Implement targetm.sched.h_i_d_extended hook.
7653 Extend internal data structures. */
7654 static void
7655 ia64_h_i_d_extended (void)
7656 {
7657 if (stops_p != NULL)
7658 {
7659 int new_clocks_length = get_max_uid () * 3 / 2;
7660 stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1);
7661 clocks_length = new_clocks_length;
7662 }
7663 }
7664 \f
7665
7666 /* This structure describes the data used by the backend to guide scheduling.
7667 When the current scheduling point is switched, this data should be saved
7668 and restored later, if the scheduler returns to this point. */
7669 struct _ia64_sched_context
7670 {
7671 state_t prev_cycle_state;
7672 rtx last_scheduled_insn;
7673 struct reg_write_state rws_sum[NUM_REGS];
7674 struct reg_write_state rws_insn[NUM_REGS];
7675 int first_instruction;
7676 int pending_data_specs;
7677 int current_cycle;
7678 char mem_ops_in_group[4];
7679 };
7680 typedef struct _ia64_sched_context *ia64_sched_context_t;
7681
7682 /* Allocates a scheduling context. */
7683 static void *
7684 ia64_alloc_sched_context (void)
7685 {
7686 return xmalloc (sizeof (struct _ia64_sched_context));
7687 }
7688
7689 /* Initializes the _SC context with clean data, if CLEAN_P, and from
7690 the global context otherwise. */
7691 static void
7692 ia64_init_sched_context (void *_sc, bool clean_p)
7693 {
7694 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7695
7696 sc->prev_cycle_state = xmalloc (dfa_state_size);
7697 if (clean_p)
7698 {
7699 state_reset (sc->prev_cycle_state);
7700 sc->last_scheduled_insn = NULL_RTX;
7701 memset (sc->rws_sum, 0, sizeof (rws_sum));
7702 memset (sc->rws_insn, 0, sizeof (rws_insn));
7703 sc->first_instruction = 1;
7704 sc->pending_data_specs = 0;
7705 sc->current_cycle = 0;
7706 memset (sc->mem_ops_in_group, 0, sizeof (mem_ops_in_group));
7707 }
7708 else
7709 {
7710 memcpy (sc->prev_cycle_state, prev_cycle_state, dfa_state_size);
7711 sc->last_scheduled_insn = last_scheduled_insn;
7712 memcpy (sc->rws_sum, rws_sum, sizeof (rws_sum));
7713 memcpy (sc->rws_insn, rws_insn, sizeof (rws_insn));
7714 sc->first_instruction = first_instruction;
7715 sc->pending_data_specs = pending_data_specs;
7716 sc->current_cycle = current_cycle;
7717 memcpy (sc->mem_ops_in_group, mem_ops_in_group, sizeof (mem_ops_in_group));
7718 }
7719 }
7720
7721 /* Sets the global scheduling context to the one pointed to by _SC. */
7722 static void
7723 ia64_set_sched_context (void *_sc)
7724 {
7725 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7726
7727 gcc_assert (sc != NULL);
7728
7729 memcpy (prev_cycle_state, sc->prev_cycle_state, dfa_state_size);
7730 last_scheduled_insn = sc->last_scheduled_insn;
7731 memcpy (rws_sum, sc->rws_sum, sizeof (rws_sum));
7732 memcpy (rws_insn, sc->rws_insn, sizeof (rws_insn));
7733 first_instruction = sc->first_instruction;
7734 pending_data_specs = sc->pending_data_specs;
7735 current_cycle = sc->current_cycle;
7736 memcpy (mem_ops_in_group, sc->mem_ops_in_group, sizeof (mem_ops_in_group));
7737 }
7738
7739 /* Clears the data in the _SC scheduling context. */
7740 static void
7741 ia64_clear_sched_context (void *_sc)
7742 {
7743 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7744
7745 free (sc->prev_cycle_state);
7746 sc->prev_cycle_state = NULL;
7747 }
7748
7749 /* Frees the _SC scheduling context. */
7750 static void
7751 ia64_free_sched_context (void *_sc)
7752 {
7753 gcc_assert (_sc != NULL);
7754
7755 free (_sc);
7756 }
7757
7758 typedef rtx (* gen_func_t) (rtx, rtx);
7759
7760 /* Return a function that will generate a load of mode MODE_NO
7761 with speculation types TS. */
7762 static gen_func_t
7763 get_spec_load_gen_function (ds_t ts, int mode_no)
7764 {
7765 static gen_func_t gen_ld_[] = {
7766 gen_movbi,
7767 gen_movqi_internal,
7768 gen_movhi_internal,
7769 gen_movsi_internal,
7770 gen_movdi_internal,
7771 gen_movsf_internal,
7772 gen_movdf_internal,
7773 gen_movxf_internal,
7774 gen_movti_internal,
7775 gen_zero_extendqidi2,
7776 gen_zero_extendhidi2,
7777 gen_zero_extendsidi2,
7778 };
7779
7780 static gen_func_t gen_ld_a[] = {
7781 gen_movbi_advanced,
7782 gen_movqi_advanced,
7783 gen_movhi_advanced,
7784 gen_movsi_advanced,
7785 gen_movdi_advanced,
7786 gen_movsf_advanced,
7787 gen_movdf_advanced,
7788 gen_movxf_advanced,
7789 gen_movti_advanced,
7790 gen_zero_extendqidi2_advanced,
7791 gen_zero_extendhidi2_advanced,
7792 gen_zero_extendsidi2_advanced,
7793 };
7794 static gen_func_t gen_ld_s[] = {
7795 gen_movbi_speculative,
7796 gen_movqi_speculative,
7797 gen_movhi_speculative,
7798 gen_movsi_speculative,
7799 gen_movdi_speculative,
7800 gen_movsf_speculative,
7801 gen_movdf_speculative,
7802 gen_movxf_speculative,
7803 gen_movti_speculative,
7804 gen_zero_extendqidi2_speculative,
7805 gen_zero_extendhidi2_speculative,
7806 gen_zero_extendsidi2_speculative,
7807 };
7808 static gen_func_t gen_ld_sa[] = {
7809 gen_movbi_speculative_advanced,
7810 gen_movqi_speculative_advanced,
7811 gen_movhi_speculative_advanced,
7812 gen_movsi_speculative_advanced,
7813 gen_movdi_speculative_advanced,
7814 gen_movsf_speculative_advanced,
7815 gen_movdf_speculative_advanced,
7816 gen_movxf_speculative_advanced,
7817 gen_movti_speculative_advanced,
7818 gen_zero_extendqidi2_speculative_advanced,
7819 gen_zero_extendhidi2_speculative_advanced,
7820 gen_zero_extendsidi2_speculative_advanced,
7821 };
7822 static gen_func_t gen_ld_s_a[] = {
7823 gen_movbi_speculative_a,
7824 gen_movqi_speculative_a,
7825 gen_movhi_speculative_a,
7826 gen_movsi_speculative_a,
7827 gen_movdi_speculative_a,
7828 gen_movsf_speculative_a,
7829 gen_movdf_speculative_a,
7830 gen_movxf_speculative_a,
7831 gen_movti_speculative_a,
7832 gen_zero_extendqidi2_speculative_a,
7833 gen_zero_extendhidi2_speculative_a,
7834 gen_zero_extendsidi2_speculative_a,
7835 };
7836
7837 gen_func_t *gen_ld;
7838
7839 if (ts & BEGIN_DATA)
7840 {
7841 if (ts & BEGIN_CONTROL)
7842 gen_ld = gen_ld_sa;
7843 else
7844 gen_ld = gen_ld_a;
7845 }
7846 else if (ts & BEGIN_CONTROL)
7847 {
7848 if ((spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL)
7849 || ia64_needs_block_p (ts))
7850 gen_ld = gen_ld_s;
7851 else
7852 gen_ld = gen_ld_s_a;
7853 }
7854 else if (ts == 0)
7855 gen_ld = gen_ld_;
7856 else
7857 gcc_unreachable ();
7858
7859 return gen_ld[mode_no];
7860 }
7861
7862 /* Constants that help mapping 'enum machine_mode' to int. */
7863 enum SPEC_MODES
7864 {
7865 SPEC_MODE_INVALID = -1,
7866 SPEC_MODE_FIRST = 0,
7867 SPEC_MODE_FOR_EXTEND_FIRST = 1,
7868 SPEC_MODE_FOR_EXTEND_LAST = 3,
7869 SPEC_MODE_LAST = 8
7870 };
7871
7872 enum
7873 {
7874 /* Offset to reach ZERO_EXTEND patterns. */
7875 SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1
7876 };
7877
7878 /* Return index of the MODE. */
7879 static int
7880 ia64_mode_to_int (enum machine_mode mode)
7881 {
7882 switch (mode)
7883 {
7884 case BImode: return 0; /* SPEC_MODE_FIRST */
7885 case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
7886 case HImode: return 2;
7887 case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
7888 case DImode: return 4;
7889 case SFmode: return 5;
7890 case DFmode: return 6;
7891 case XFmode: return 7;
7892 case TImode:
7893 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
7894 mentioned in itanium[12].md. Predicate fp_register_operand also
7895 needs to be defined. Bottom line: better disable for now. */
7896 return SPEC_MODE_INVALID;
7897 default: return SPEC_MODE_INVALID;
7898 }
7899 }
7900
7901 /* Provide information about speculation capabilities. */
7902 static void
7903 ia64_set_sched_flags (spec_info_t spec_info)
7904 {
7905 unsigned int *flags = &(current_sched_info->flags);
7906
7907 if (*flags & SCHED_RGN
7908 || *flags & SCHED_EBB
7909 || *flags & SEL_SCHED)
7910 {
7911 int mask = 0;
7912
7913 if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0)
7914 || (mflag_sched_ar_data_spec && reload_completed))
7915 {
7916 mask |= BEGIN_DATA;
7917
7918 if (!sel_sched_p ()
7919 && ((mflag_sched_br_in_data_spec && !reload_completed)
7920 || (mflag_sched_ar_in_data_spec && reload_completed)))
7921 mask |= BE_IN_DATA;
7922 }
7923
7924 if (mflag_sched_control_spec
7925 && (!sel_sched_p ()
7926 || reload_completed))
7927 {
7928 mask |= BEGIN_CONTROL;
7929
7930 if (!sel_sched_p () && mflag_sched_in_control_spec)
7931 mask |= BE_IN_CONTROL;
7932 }
7933
7934 spec_info->mask = mask;
7935
7936 if (mask)
7937 {
7938 *flags |= USE_DEPS_LIST | DO_SPECULATION;
7939
7940 if (mask & BE_IN_SPEC)
7941 *flags |= NEW_BBS;
7942
7943 spec_info->flags = 0;
7944
7945 if ((mask & CONTROL_SPEC)
7946 && sel_sched_p () && mflag_sel_sched_dont_check_control_spec)
7947 spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL;
7948
7949 if (sched_verbose >= 1)
7950 spec_info->dump = sched_dump;
7951 else
7952 spec_info->dump = 0;
7953
7954 if (mflag_sched_count_spec_in_critical_path)
7955 spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH;
7956 }
7957 }
7958 else
7959 spec_info->mask = 0;
7960 }
7961
7962 /* If INSN is an appropriate load return its mode.
7963 Return -1 otherwise. */
7964 static int
7965 get_mode_no_for_insn (rtx insn)
7966 {
7967 rtx reg, mem, mode_rtx;
7968 int mode_no;
7969 bool extend_p;
7970
7971 extract_insn_cached (insn);
7972
7973 /* We use WHICH_ALTERNATIVE only after reload. This will
7974 guarantee that reload won't touch a speculative insn. */
7975
7976 if (recog_data.n_operands != 2)
7977 return -1;
7978
7979 reg = recog_data.operand[0];
7980 mem = recog_data.operand[1];
7981
7982 /* We should use MEM's mode since REG's mode in presence of
7983 ZERO_EXTEND will always be DImode. */
7984 if (get_attr_speculable1 (insn) == SPECULABLE1_YES)
7985 /* Process non-speculative ld. */
7986 {
7987 if (!reload_completed)
7988 {
7989 /* Do not speculate into regs like ar.lc. */
7990 if (!REG_P (reg) || AR_REGNO_P (REGNO (reg)))
7991 return -1;
7992
7993 if (!MEM_P (mem))
7994 return -1;
7995
7996 {
7997 rtx mem_reg = XEXP (mem, 0);
7998
7999 if (!REG_P (mem_reg))
8000 return -1;
8001 }
8002
8003 mode_rtx = mem;
8004 }
8005 else if (get_attr_speculable2 (insn) == SPECULABLE2_YES)
8006 {
8007 gcc_assert (REG_P (reg) && MEM_P (mem));
8008 mode_rtx = mem;
8009 }
8010 else
8011 return -1;
8012 }
8013 else if (get_attr_data_speculative (insn) == DATA_SPECULATIVE_YES
8014 || get_attr_control_speculative (insn) == CONTROL_SPECULATIVE_YES
8015 || get_attr_check_load (insn) == CHECK_LOAD_YES)
8016 /* Process speculative ld or ld.c. */
8017 {
8018 gcc_assert (REG_P (reg) && MEM_P (mem));
8019 mode_rtx = mem;
8020 }
8021 else
8022 {
8023 enum attr_itanium_class attr_class = get_attr_itanium_class (insn);
8024
8025 if (attr_class == ITANIUM_CLASS_CHK_A
8026 || attr_class == ITANIUM_CLASS_CHK_S_I
8027 || attr_class == ITANIUM_CLASS_CHK_S_F)
8028 /* Process chk. */
8029 mode_rtx = reg;
8030 else
8031 return -1;
8032 }
8033
8034 mode_no = ia64_mode_to_int (GET_MODE (mode_rtx));
8035
8036 if (mode_no == SPEC_MODE_INVALID)
8037 return -1;
8038
8039 extend_p = (GET_MODE (reg) != GET_MODE (mode_rtx));
8040
8041 if (extend_p)
8042 {
8043 if (!(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no
8044 && mode_no <= SPEC_MODE_FOR_EXTEND_LAST))
8045 return -1;
8046
8047 mode_no += SPEC_GEN_EXTEND_OFFSET;
8048 }
8049
8050 return mode_no;
8051 }
8052
8053 /* If X is an unspec part of a speculative load, return its code.
8054 Return -1 otherwise. */
8055 static int
8056 get_spec_unspec_code (const_rtx x)
8057 {
8058 if (GET_CODE (x) != UNSPEC)
8059 return -1;
8060
8061 {
8062 int code;
8063
8064 code = XINT (x, 1);
8065
8066 switch (code)
8067 {
8068 case UNSPEC_LDA:
8069 case UNSPEC_LDS:
8070 case UNSPEC_LDS_A:
8071 case UNSPEC_LDSA:
8072 return code;
8073
8074 default:
8075 return -1;
8076 }
8077 }
8078 }
8079
8080 /* Implement skip_rtx_p hook. */
8081 static bool
8082 ia64_skip_rtx_p (const_rtx x)
8083 {
8084 return get_spec_unspec_code (x) != -1;
8085 }
8086
8087 /* If INSN is a speculative load, return its UNSPEC code.
8088 Return -1 otherwise. */
8089 static int
8090 get_insn_spec_code (const_rtx insn)
8091 {
8092 rtx pat, reg, mem;
8093
8094 pat = PATTERN (insn);
8095
8096 if (GET_CODE (pat) == COND_EXEC)
8097 pat = COND_EXEC_CODE (pat);
8098
8099 if (GET_CODE (pat) != SET)
8100 return -1;
8101
8102 reg = SET_DEST (pat);
8103 if (!REG_P (reg))
8104 return -1;
8105
8106 mem = SET_SRC (pat);
8107 if (GET_CODE (mem) == ZERO_EXTEND)
8108 mem = XEXP (mem, 0);
8109
8110 return get_spec_unspec_code (mem);
8111 }
8112
8113 /* If INSN is a speculative load, return a ds with the speculation types.
8114 Otherwise [if INSN is a normal instruction] return 0. */
8115 static ds_t
8116 ia64_get_insn_spec_ds (rtx_insn *insn)
8117 {
8118 int code = get_insn_spec_code (insn);
8119
8120 switch (code)
8121 {
8122 case UNSPEC_LDA:
8123 return BEGIN_DATA;
8124
8125 case UNSPEC_LDS:
8126 case UNSPEC_LDS_A:
8127 return BEGIN_CONTROL;
8128
8129 case UNSPEC_LDSA:
8130 return BEGIN_DATA | BEGIN_CONTROL;
8131
8132 default:
8133 return 0;
8134 }
8135 }
8136
8137 /* If INSN is a speculative load return a ds with the speculation types that
8138 will be checked.
8139 Otherwise [if INSN is a normal instruction] return 0. */
8140 static ds_t
8141 ia64_get_insn_checked_ds (rtx_insn *insn)
8142 {
8143 int code = get_insn_spec_code (insn);
8144
8145 switch (code)
8146 {
8147 case UNSPEC_LDA:
8148 return BEGIN_DATA | BEGIN_CONTROL;
8149
8150 case UNSPEC_LDS:
8151 return BEGIN_CONTROL;
8152
8153 case UNSPEC_LDS_A:
8154 case UNSPEC_LDSA:
8155 return BEGIN_DATA | BEGIN_CONTROL;
8156
8157 default:
8158 return 0;
8159 }
8160 }
8161
8162 /* If GEN_P is true, calculate the index of needed speculation check and return
8163 speculative pattern for INSN with speculative mode TS, machine mode
8164 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
8165 If GEN_P is false, just calculate the index of needed speculation check. */
8166 static rtx
8167 ia64_gen_spec_load (rtx insn, ds_t ts, int mode_no)
8168 {
8169 rtx pat, new_pat;
8170 gen_func_t gen_load;
8171
8172 gen_load = get_spec_load_gen_function (ts, mode_no);
8173
8174 new_pat = gen_load (copy_rtx (recog_data.operand[0]),
8175 copy_rtx (recog_data.operand[1]));
8176
8177 pat = PATTERN (insn);
8178 if (GET_CODE (pat) == COND_EXEC)
8179 new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
8180 new_pat);
8181
8182 return new_pat;
8183 }
8184
8185 static bool
8186 insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED,
8187 ds_t ds ATTRIBUTE_UNUSED)
8188 {
8189 return false;
8190 }
8191
8192 /* Implement targetm.sched.speculate_insn hook.
8193 Check if the INSN can be TS speculative.
8194 If 'no' - return -1.
8195 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
8196 If current pattern of the INSN already provides TS speculation,
8197 return 0. */
8198 static int
8199 ia64_speculate_insn (rtx_insn *insn, ds_t ts, rtx *new_pat)
8200 {
8201 int mode_no;
8202 int res;
8203
8204 gcc_assert (!(ts & ~SPECULATIVE));
8205
8206 if (ia64_spec_check_p (insn))
8207 return -1;
8208
8209 if ((ts & BE_IN_SPEC)
8210 && !insn_can_be_in_speculative_p (insn, ts))
8211 return -1;
8212
8213 mode_no = get_mode_no_for_insn (insn);
8214
8215 if (mode_no != SPEC_MODE_INVALID)
8216 {
8217 if (ia64_get_insn_spec_ds (insn) == ds_get_speculation_types (ts))
8218 res = 0;
8219 else
8220 {
8221 res = 1;
8222 *new_pat = ia64_gen_spec_load (insn, ts, mode_no);
8223 }
8224 }
8225 else
8226 res = -1;
8227
8228 return res;
8229 }
8230
8231 /* Return a function that will generate a check for speculation TS with mode
8232 MODE_NO.
8233 If simple check is needed, pass true for SIMPLE_CHECK_P.
8234 If clearing check is needed, pass true for CLEARING_CHECK_P. */
8235 static gen_func_t
8236 get_spec_check_gen_function (ds_t ts, int mode_no,
8237 bool simple_check_p, bool clearing_check_p)
8238 {
8239 static gen_func_t gen_ld_c_clr[] = {
8240 gen_movbi_clr,
8241 gen_movqi_clr,
8242 gen_movhi_clr,
8243 gen_movsi_clr,
8244 gen_movdi_clr,
8245 gen_movsf_clr,
8246 gen_movdf_clr,
8247 gen_movxf_clr,
8248 gen_movti_clr,
8249 gen_zero_extendqidi2_clr,
8250 gen_zero_extendhidi2_clr,
8251 gen_zero_extendsidi2_clr,
8252 };
8253 static gen_func_t gen_ld_c_nc[] = {
8254 gen_movbi_nc,
8255 gen_movqi_nc,
8256 gen_movhi_nc,
8257 gen_movsi_nc,
8258 gen_movdi_nc,
8259 gen_movsf_nc,
8260 gen_movdf_nc,
8261 gen_movxf_nc,
8262 gen_movti_nc,
8263 gen_zero_extendqidi2_nc,
8264 gen_zero_extendhidi2_nc,
8265 gen_zero_extendsidi2_nc,
8266 };
8267 static gen_func_t gen_chk_a_clr[] = {
8268 gen_advanced_load_check_clr_bi,
8269 gen_advanced_load_check_clr_qi,
8270 gen_advanced_load_check_clr_hi,
8271 gen_advanced_load_check_clr_si,
8272 gen_advanced_load_check_clr_di,
8273 gen_advanced_load_check_clr_sf,
8274 gen_advanced_load_check_clr_df,
8275 gen_advanced_load_check_clr_xf,
8276 gen_advanced_load_check_clr_ti,
8277 gen_advanced_load_check_clr_di,
8278 gen_advanced_load_check_clr_di,
8279 gen_advanced_load_check_clr_di,
8280 };
8281 static gen_func_t gen_chk_a_nc[] = {
8282 gen_advanced_load_check_nc_bi,
8283 gen_advanced_load_check_nc_qi,
8284 gen_advanced_load_check_nc_hi,
8285 gen_advanced_load_check_nc_si,
8286 gen_advanced_load_check_nc_di,
8287 gen_advanced_load_check_nc_sf,
8288 gen_advanced_load_check_nc_df,
8289 gen_advanced_load_check_nc_xf,
8290 gen_advanced_load_check_nc_ti,
8291 gen_advanced_load_check_nc_di,
8292 gen_advanced_load_check_nc_di,
8293 gen_advanced_load_check_nc_di,
8294 };
8295 static gen_func_t gen_chk_s[] = {
8296 gen_speculation_check_bi,
8297 gen_speculation_check_qi,
8298 gen_speculation_check_hi,
8299 gen_speculation_check_si,
8300 gen_speculation_check_di,
8301 gen_speculation_check_sf,
8302 gen_speculation_check_df,
8303 gen_speculation_check_xf,
8304 gen_speculation_check_ti,
8305 gen_speculation_check_di,
8306 gen_speculation_check_di,
8307 gen_speculation_check_di,
8308 };
8309
8310 gen_func_t *gen_check;
8311
8312 if (ts & BEGIN_DATA)
8313 {
8314 /* We don't need recovery because even if this is ld.sa
8315 ALAT entry will be allocated only if NAT bit is set to zero.
8316 So it is enough to use ld.c here. */
8317
8318 if (simple_check_p)
8319 {
8320 gcc_assert (mflag_sched_spec_ldc);
8321
8322 if (clearing_check_p)
8323 gen_check = gen_ld_c_clr;
8324 else
8325 gen_check = gen_ld_c_nc;
8326 }
8327 else
8328 {
8329 if (clearing_check_p)
8330 gen_check = gen_chk_a_clr;
8331 else
8332 gen_check = gen_chk_a_nc;
8333 }
8334 }
8335 else if (ts & BEGIN_CONTROL)
8336 {
8337 if (simple_check_p)
8338 /* We might want to use ld.sa -> ld.c instead of
8339 ld.s -> chk.s. */
8340 {
8341 gcc_assert (!ia64_needs_block_p (ts));
8342
8343 if (clearing_check_p)
8344 gen_check = gen_ld_c_clr;
8345 else
8346 gen_check = gen_ld_c_nc;
8347 }
8348 else
8349 {
8350 gen_check = gen_chk_s;
8351 }
8352 }
8353 else
8354 gcc_unreachable ();
8355
8356 gcc_assert (mode_no >= 0);
8357 return gen_check[mode_no];
8358 }
8359
8360 /* Return nonzero, if INSN needs branchy recovery check. */
8361 static bool
8362 ia64_needs_block_p (ds_t ts)
8363 {
8364 if (ts & BEGIN_DATA)
8365 return !mflag_sched_spec_ldc;
8366
8367 gcc_assert ((ts & BEGIN_CONTROL) != 0);
8368
8369 return !(mflag_sched_spec_control_ldc && mflag_sched_spec_ldc);
8370 }
8371
8372 /* Generate (or regenerate) a recovery check for INSN. */
8373 static rtx
8374 ia64_gen_spec_check (rtx_insn *insn, rtx_insn *label, ds_t ds)
8375 {
8376 rtx op1, pat, check_pat;
8377 gen_func_t gen_check;
8378 int mode_no;
8379
8380 mode_no = get_mode_no_for_insn (insn);
8381 gcc_assert (mode_no >= 0);
8382
8383 if (label)
8384 op1 = label;
8385 else
8386 {
8387 gcc_assert (!ia64_needs_block_p (ds));
8388 op1 = copy_rtx (recog_data.operand[1]);
8389 }
8390
8391 gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX,
8392 true);
8393
8394 check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1);
8395
8396 pat = PATTERN (insn);
8397 if (GET_CODE (pat) == COND_EXEC)
8398 check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
8399 check_pat);
8400
8401 return check_pat;
8402 }
8403
8404 /* Return nonzero, if X is branchy recovery check. */
8405 static int
8406 ia64_spec_check_p (rtx x)
8407 {
8408 x = PATTERN (x);
8409 if (GET_CODE (x) == COND_EXEC)
8410 x = COND_EXEC_CODE (x);
8411 if (GET_CODE (x) == SET)
8412 return ia64_spec_check_src_p (SET_SRC (x));
8413 return 0;
8414 }
8415
8416 /* Return nonzero, if SRC belongs to recovery check. */
8417 static int
8418 ia64_spec_check_src_p (rtx src)
8419 {
8420 if (GET_CODE (src) == IF_THEN_ELSE)
8421 {
8422 rtx t;
8423
8424 t = XEXP (src, 0);
8425 if (GET_CODE (t) == NE)
8426 {
8427 t = XEXP (t, 0);
8428
8429 if (GET_CODE (t) == UNSPEC)
8430 {
8431 int code;
8432
8433 code = XINT (t, 1);
8434
8435 if (code == UNSPEC_LDCCLR
8436 || code == UNSPEC_LDCNC
8437 || code == UNSPEC_CHKACLR
8438 || code == UNSPEC_CHKANC
8439 || code == UNSPEC_CHKS)
8440 {
8441 gcc_assert (code != 0);
8442 return code;
8443 }
8444 }
8445 }
8446 }
8447 return 0;
8448 }
8449 \f
8450
8451 /* The following page contains abstract data `bundle states' which are
8452 used for bundling insns (inserting nops and template generation). */
8453
8454 /* The following describes state of insn bundling. */
8455
8456 struct bundle_state
8457 {
8458 /* Unique bundle state number to identify them in the debugging
8459 output */
8460 int unique_num;
8461 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
8462 /* number nops before and after the insn */
8463 short before_nops_num, after_nops_num;
8464 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
8465 insn */
8466 int cost; /* cost of the state in cycles */
8467 int accumulated_insns_num; /* number of all previous insns including
8468 nops. L is considered as 2 insns */
8469 int branch_deviation; /* deviation of previous branches from 3rd slots */
8470 int middle_bundle_stops; /* number of stop bits in the middle of bundles */
8471 struct bundle_state *next; /* next state with the same insn_num */
8472 struct bundle_state *originator; /* originator (previous insn state) */
8473 /* All bundle states are in the following chain. */
8474 struct bundle_state *allocated_states_chain;
8475 /* The DFA State after issuing the insn and the nops. */
8476 state_t dfa_state;
8477 };
8478
8479 /* The following is map insn number to the corresponding bundle state. */
8480
8481 static struct bundle_state **index_to_bundle_states;
8482
8483 /* The unique number of next bundle state. */
8484
8485 static int bundle_states_num;
8486
8487 /* All allocated bundle states are in the following chain. */
8488
8489 static struct bundle_state *allocated_bundle_states_chain;
8490
8491 /* All allocated but not used bundle states are in the following
8492 chain. */
8493
8494 static struct bundle_state *free_bundle_state_chain;
8495
8496
8497 /* The following function returns a free bundle state. */
8498
8499 static struct bundle_state *
8500 get_free_bundle_state (void)
8501 {
8502 struct bundle_state *result;
8503
8504 if (free_bundle_state_chain != NULL)
8505 {
8506 result = free_bundle_state_chain;
8507 free_bundle_state_chain = result->next;
8508 }
8509 else
8510 {
8511 result = XNEW (struct bundle_state);
8512 result->dfa_state = xmalloc (dfa_state_size);
8513 result->allocated_states_chain = allocated_bundle_states_chain;
8514 allocated_bundle_states_chain = result;
8515 }
8516 result->unique_num = bundle_states_num++;
8517 return result;
8518
8519 }
8520
8521 /* The following function frees given bundle state. */
8522
8523 static void
8524 free_bundle_state (struct bundle_state *state)
8525 {
8526 state->next = free_bundle_state_chain;
8527 free_bundle_state_chain = state;
8528 }
8529
8530 /* Start work with abstract data `bundle states'. */
8531
8532 static void
8533 initiate_bundle_states (void)
8534 {
8535 bundle_states_num = 0;
8536 free_bundle_state_chain = NULL;
8537 allocated_bundle_states_chain = NULL;
8538 }
8539
8540 /* Finish work with abstract data `bundle states'. */
8541
8542 static void
8543 finish_bundle_states (void)
8544 {
8545 struct bundle_state *curr_state, *next_state;
8546
8547 for (curr_state = allocated_bundle_states_chain;
8548 curr_state != NULL;
8549 curr_state = next_state)
8550 {
8551 next_state = curr_state->allocated_states_chain;
8552 free (curr_state->dfa_state);
8553 free (curr_state);
8554 }
8555 }
8556
8557 /* Hashtable helpers. */
8558
8559 struct bundle_state_hasher : typed_noop_remove <bundle_state>
8560 {
8561 typedef bundle_state value_type;
8562 typedef bundle_state compare_type;
8563 static inline hashval_t hash (const value_type *);
8564 static inline bool equal (const value_type *, const compare_type *);
8565 };
8566
8567 /* The function returns hash of BUNDLE_STATE. */
8568
8569 inline hashval_t
8570 bundle_state_hasher::hash (const value_type *state)
8571 {
8572 unsigned result, i;
8573
8574 for (result = i = 0; i < dfa_state_size; i++)
8575 result += (((unsigned char *) state->dfa_state) [i]
8576 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
8577 return result + state->insn_num;
8578 }
8579
8580 /* The function returns nonzero if the bundle state keys are equal. */
8581
8582 inline bool
8583 bundle_state_hasher::equal (const value_type *state1,
8584 const compare_type *state2)
8585 {
8586 return (state1->insn_num == state2->insn_num
8587 && memcmp (state1->dfa_state, state2->dfa_state,
8588 dfa_state_size) == 0);
8589 }
8590
8591 /* Hash table of the bundle states. The key is dfa_state and insn_num
8592 of the bundle states. */
8593
8594 static hash_table<bundle_state_hasher> *bundle_state_table;
8595
8596 /* The function inserts the BUNDLE_STATE into the hash table. The
8597 function returns nonzero if the bundle has been inserted into the
8598 table. The table contains the best bundle state with given key. */
8599
8600 static int
8601 insert_bundle_state (struct bundle_state *bundle_state)
8602 {
8603 struct bundle_state **entry_ptr;
8604
8605 entry_ptr = bundle_state_table->find_slot (bundle_state, INSERT);
8606 if (*entry_ptr == NULL)
8607 {
8608 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
8609 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
8610 *entry_ptr = bundle_state;
8611 return TRUE;
8612 }
8613 else if (bundle_state->cost < (*entry_ptr)->cost
8614 || (bundle_state->cost == (*entry_ptr)->cost
8615 && ((*entry_ptr)->accumulated_insns_num
8616 > bundle_state->accumulated_insns_num
8617 || ((*entry_ptr)->accumulated_insns_num
8618 == bundle_state->accumulated_insns_num
8619 && ((*entry_ptr)->branch_deviation
8620 > bundle_state->branch_deviation
8621 || ((*entry_ptr)->branch_deviation
8622 == bundle_state->branch_deviation
8623 && (*entry_ptr)->middle_bundle_stops
8624 > bundle_state->middle_bundle_stops))))))
8625
8626 {
8627 struct bundle_state temp;
8628
8629 temp = **entry_ptr;
8630 **entry_ptr = *bundle_state;
8631 (*entry_ptr)->next = temp.next;
8632 *bundle_state = temp;
8633 }
8634 return FALSE;
8635 }
8636
8637 /* Start work with the hash table. */
8638
8639 static void
8640 initiate_bundle_state_table (void)
8641 {
8642 bundle_state_table = new hash_table<bundle_state_hasher> (50);
8643 }
8644
8645 /* Finish work with the hash table. */
8646
8647 static void
8648 finish_bundle_state_table (void)
8649 {
8650 delete bundle_state_table;
8651 bundle_state_table = NULL;
8652 }
8653
8654 \f
8655
8656 /* The following variable is a insn `nop' used to check bundle states
8657 with different number of inserted nops. */
8658
8659 static rtx_insn *ia64_nop;
8660
8661 /* The following function tries to issue NOPS_NUM nops for the current
8662 state without advancing processor cycle. If it failed, the
8663 function returns FALSE and frees the current state. */
8664
8665 static int
8666 try_issue_nops (struct bundle_state *curr_state, int nops_num)
8667 {
8668 int i;
8669
8670 for (i = 0; i < nops_num; i++)
8671 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
8672 {
8673 free_bundle_state (curr_state);
8674 return FALSE;
8675 }
8676 return TRUE;
8677 }
8678
8679 /* The following function tries to issue INSN for the current
8680 state without advancing processor cycle. If it failed, the
8681 function returns FALSE and frees the current state. */
8682
8683 static int
8684 try_issue_insn (struct bundle_state *curr_state, rtx insn)
8685 {
8686 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
8687 {
8688 free_bundle_state (curr_state);
8689 return FALSE;
8690 }
8691 return TRUE;
8692 }
8693
8694 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
8695 starting with ORIGINATOR without advancing processor cycle. If
8696 TRY_BUNDLE_END_P is TRUE, the function also/only (if
8697 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
8698 If it was successful, the function creates new bundle state and
8699 insert into the hash table and into `index_to_bundle_states'. */
8700
8701 static void
8702 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
8703 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
8704 {
8705 struct bundle_state *curr_state;
8706
8707 curr_state = get_free_bundle_state ();
8708 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
8709 curr_state->insn = insn;
8710 curr_state->insn_num = originator->insn_num + 1;
8711 curr_state->cost = originator->cost;
8712 curr_state->originator = originator;
8713 curr_state->before_nops_num = before_nops_num;
8714 curr_state->after_nops_num = 0;
8715 curr_state->accumulated_insns_num
8716 = originator->accumulated_insns_num + before_nops_num;
8717 curr_state->branch_deviation = originator->branch_deviation;
8718 curr_state->middle_bundle_stops = originator->middle_bundle_stops;
8719 gcc_assert (insn);
8720 if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
8721 {
8722 gcc_assert (GET_MODE (insn) != TImode);
8723 if (!try_issue_nops (curr_state, before_nops_num))
8724 return;
8725 if (!try_issue_insn (curr_state, insn))
8726 return;
8727 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
8728 if (curr_state->accumulated_insns_num % 3 != 0)
8729 curr_state->middle_bundle_stops++;
8730 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
8731 && curr_state->accumulated_insns_num % 3 != 0)
8732 {
8733 free_bundle_state (curr_state);
8734 return;
8735 }
8736 }
8737 else if (GET_MODE (insn) != TImode)
8738 {
8739 if (!try_issue_nops (curr_state, before_nops_num))
8740 return;
8741 if (!try_issue_insn (curr_state, insn))
8742 return;
8743 curr_state->accumulated_insns_num++;
8744 gcc_assert (!unknown_for_bundling_p (insn));
8745
8746 if (ia64_safe_type (insn) == TYPE_L)
8747 curr_state->accumulated_insns_num++;
8748 }
8749 else
8750 {
8751 /* If this is an insn that must be first in a group, then don't allow
8752 nops to be emitted before it. Currently, alloc is the only such
8753 supported instruction. */
8754 /* ??? The bundling automatons should handle this for us, but they do
8755 not yet have support for the first_insn attribute. */
8756 if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES)
8757 {
8758 free_bundle_state (curr_state);
8759 return;
8760 }
8761
8762 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
8763 state_transition (curr_state->dfa_state, NULL);
8764 curr_state->cost++;
8765 if (!try_issue_nops (curr_state, before_nops_num))
8766 return;
8767 if (!try_issue_insn (curr_state, insn))
8768 return;
8769 curr_state->accumulated_insns_num++;
8770 if (unknown_for_bundling_p (insn))
8771 {
8772 /* Finish bundle containing asm insn. */
8773 curr_state->after_nops_num
8774 = 3 - curr_state->accumulated_insns_num % 3;
8775 curr_state->accumulated_insns_num
8776 += 3 - curr_state->accumulated_insns_num % 3;
8777 }
8778 else if (ia64_safe_type (insn) == TYPE_L)
8779 curr_state->accumulated_insns_num++;
8780 }
8781 if (ia64_safe_type (insn) == TYPE_B)
8782 curr_state->branch_deviation
8783 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
8784 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
8785 {
8786 if (!only_bundle_end_p && insert_bundle_state (curr_state))
8787 {
8788 state_t dfa_state;
8789 struct bundle_state *curr_state1;
8790 struct bundle_state *allocated_states_chain;
8791
8792 curr_state1 = get_free_bundle_state ();
8793 dfa_state = curr_state1->dfa_state;
8794 allocated_states_chain = curr_state1->allocated_states_chain;
8795 *curr_state1 = *curr_state;
8796 curr_state1->dfa_state = dfa_state;
8797 curr_state1->allocated_states_chain = allocated_states_chain;
8798 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
8799 dfa_state_size);
8800 curr_state = curr_state1;
8801 }
8802 if (!try_issue_nops (curr_state,
8803 3 - curr_state->accumulated_insns_num % 3))
8804 return;
8805 curr_state->after_nops_num
8806 = 3 - curr_state->accumulated_insns_num % 3;
8807 curr_state->accumulated_insns_num
8808 += 3 - curr_state->accumulated_insns_num % 3;
8809 }
8810 if (!insert_bundle_state (curr_state))
8811 free_bundle_state (curr_state);
8812 return;
8813 }
8814
8815 /* The following function returns position in the two window bundle
8816 for given STATE. */
8817
8818 static int
8819 get_max_pos (state_t state)
8820 {
8821 if (cpu_unit_reservation_p (state, pos_6))
8822 return 6;
8823 else if (cpu_unit_reservation_p (state, pos_5))
8824 return 5;
8825 else if (cpu_unit_reservation_p (state, pos_4))
8826 return 4;
8827 else if (cpu_unit_reservation_p (state, pos_3))
8828 return 3;
8829 else if (cpu_unit_reservation_p (state, pos_2))
8830 return 2;
8831 else if (cpu_unit_reservation_p (state, pos_1))
8832 return 1;
8833 else
8834 return 0;
8835 }
8836
8837 /* The function returns code of a possible template for given position
8838 and state. The function should be called only with 2 values of
8839 position equal to 3 or 6. We avoid generating F NOPs by putting
8840 templates containing F insns at the end of the template search
8841 because undocumented anomaly in McKinley derived cores which can
8842 cause stalls if an F-unit insn (including a NOP) is issued within a
8843 six-cycle window after reading certain application registers (such
8844 as ar.bsp). Furthermore, power-considerations also argue against
8845 the use of F-unit instructions unless they're really needed. */
8846
8847 static int
8848 get_template (state_t state, int pos)
8849 {
8850 switch (pos)
8851 {
8852 case 3:
8853 if (cpu_unit_reservation_p (state, _0mmi_))
8854 return 1;
8855 else if (cpu_unit_reservation_p (state, _0mii_))
8856 return 0;
8857 else if (cpu_unit_reservation_p (state, _0mmb_))
8858 return 7;
8859 else if (cpu_unit_reservation_p (state, _0mib_))
8860 return 6;
8861 else if (cpu_unit_reservation_p (state, _0mbb_))
8862 return 5;
8863 else if (cpu_unit_reservation_p (state, _0bbb_))
8864 return 4;
8865 else if (cpu_unit_reservation_p (state, _0mmf_))
8866 return 3;
8867 else if (cpu_unit_reservation_p (state, _0mfi_))
8868 return 2;
8869 else if (cpu_unit_reservation_p (state, _0mfb_))
8870 return 8;
8871 else if (cpu_unit_reservation_p (state, _0mlx_))
8872 return 9;
8873 else
8874 gcc_unreachable ();
8875 case 6:
8876 if (cpu_unit_reservation_p (state, _1mmi_))
8877 return 1;
8878 else if (cpu_unit_reservation_p (state, _1mii_))
8879 return 0;
8880 else if (cpu_unit_reservation_p (state, _1mmb_))
8881 return 7;
8882 else if (cpu_unit_reservation_p (state, _1mib_))
8883 return 6;
8884 else if (cpu_unit_reservation_p (state, _1mbb_))
8885 return 5;
8886 else if (cpu_unit_reservation_p (state, _1bbb_))
8887 return 4;
8888 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
8889 return 3;
8890 else if (cpu_unit_reservation_p (state, _1mfi_))
8891 return 2;
8892 else if (cpu_unit_reservation_p (state, _1mfb_))
8893 return 8;
8894 else if (cpu_unit_reservation_p (state, _1mlx_))
8895 return 9;
8896 else
8897 gcc_unreachable ();
8898 default:
8899 gcc_unreachable ();
8900 }
8901 }
8902
8903 /* True when INSN is important for bundling. */
8904
8905 static bool
8906 important_for_bundling_p (rtx insn)
8907 {
8908 return (INSN_P (insn)
8909 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8910 && GET_CODE (PATTERN (insn)) != USE
8911 && GET_CODE (PATTERN (insn)) != CLOBBER);
8912 }
8913
8914 /* The following function returns an insn important for insn bundling
8915 followed by INSN and before TAIL. */
8916
8917 static rtx
8918 get_next_important_insn (rtx insn, rtx tail)
8919 {
8920 for (; insn && insn != tail; insn = NEXT_INSN (insn))
8921 if (important_for_bundling_p (insn))
8922 return insn;
8923 return NULL_RTX;
8924 }
8925
8926 /* True when INSN is unknown, but important, for bundling. */
8927
8928 static bool
8929 unknown_for_bundling_p (rtx insn)
8930 {
8931 return (INSN_P (insn)
8932 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_UNKNOWN
8933 && GET_CODE (PATTERN (insn)) != USE
8934 && GET_CODE (PATTERN (insn)) != CLOBBER);
8935 }
8936
8937 /* Add a bundle selector TEMPLATE0 before INSN. */
8938
8939 static void
8940 ia64_add_bundle_selector_before (int template0, rtx insn)
8941 {
8942 rtx b = gen_bundle_selector (GEN_INT (template0));
8943
8944 ia64_emit_insn_before (b, insn);
8945 #if NR_BUNDLES == 10
8946 if ((template0 == 4 || template0 == 5)
8947 && ia64_except_unwind_info (&global_options) == UI_TARGET)
8948 {
8949 int i;
8950 rtx note = NULL_RTX;
8951
8952 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
8953 first or second slot. If it is and has REG_EH_NOTE set, copy it
8954 to following nops, as br.call sets rp to the address of following
8955 bundle and therefore an EH region end must be on a bundle
8956 boundary. */
8957 insn = PREV_INSN (insn);
8958 for (i = 0; i < 3; i++)
8959 {
8960 do
8961 insn = next_active_insn (insn);
8962 while (NONJUMP_INSN_P (insn)
8963 && get_attr_empty (insn) == EMPTY_YES);
8964 if (CALL_P (insn))
8965 note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8966 else if (note)
8967 {
8968 int code;
8969
8970 gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop
8971 || code == CODE_FOR_nop_b);
8972 if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
8973 note = NULL_RTX;
8974 else
8975 add_reg_note (insn, REG_EH_REGION, XEXP (note, 0));
8976 }
8977 }
8978 }
8979 #endif
8980 }
8981
8982 /* The following function does insn bundling. Bundling means
8983 inserting templates and nop insns to fit insn groups into permitted
8984 templates. Instruction scheduling uses NDFA (non-deterministic
8985 finite automata) encoding informations about the templates and the
8986 inserted nops. Nondeterminism of the automata permits follows
8987 all possible insn sequences very fast.
8988
8989 Unfortunately it is not possible to get information about inserting
8990 nop insns and used templates from the automata states. The
8991 automata only says that we can issue an insn possibly inserting
8992 some nops before it and using some template. Therefore insn
8993 bundling in this function is implemented by using DFA
8994 (deterministic finite automata). We follow all possible insn
8995 sequences by inserting 0-2 nops (that is what the NDFA describe for
8996 insn scheduling) before/after each insn being bundled. We know the
8997 start of simulated processor cycle from insn scheduling (insn
8998 starting a new cycle has TImode).
8999
9000 Simple implementation of insn bundling would create enormous
9001 number of possible insn sequences satisfying information about new
9002 cycle ticks taken from the insn scheduling. To make the algorithm
9003 practical we use dynamic programming. Each decision (about
9004 inserting nops and implicitly about previous decisions) is described
9005 by structure bundle_state (see above). If we generate the same
9006 bundle state (key is automaton state after issuing the insns and
9007 nops for it), we reuse already generated one. As consequence we
9008 reject some decisions which cannot improve the solution and
9009 reduce memory for the algorithm.
9010
9011 When we reach the end of EBB (extended basic block), we choose the
9012 best sequence and then, moving back in EBB, insert templates for
9013 the best alternative. The templates are taken from querying
9014 automaton state for each insn in chosen bundle states.
9015
9016 So the algorithm makes two (forward and backward) passes through
9017 EBB. */
9018
9019 static void
9020 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
9021 {
9022 struct bundle_state *curr_state, *next_state, *best_state;
9023 rtx insn, next_insn;
9024 int insn_num;
9025 int i, bundle_end_p, only_bundle_end_p, asm_p;
9026 int pos = 0, max_pos, template0, template1;
9027 rtx b;
9028 rtx nop;
9029 enum attr_type type;
9030
9031 insn_num = 0;
9032 /* Count insns in the EBB. */
9033 for (insn = NEXT_INSN (prev_head_insn);
9034 insn && insn != tail;
9035 insn = NEXT_INSN (insn))
9036 if (INSN_P (insn))
9037 insn_num++;
9038 if (insn_num == 0)
9039 return;
9040 bundling_p = 1;
9041 dfa_clean_insn_cache ();
9042 initiate_bundle_state_table ();
9043 index_to_bundle_states = XNEWVEC (struct bundle_state *, insn_num + 2);
9044 /* First (forward) pass -- generation of bundle states. */
9045 curr_state = get_free_bundle_state ();
9046 curr_state->insn = NULL;
9047 curr_state->before_nops_num = 0;
9048 curr_state->after_nops_num = 0;
9049 curr_state->insn_num = 0;
9050 curr_state->cost = 0;
9051 curr_state->accumulated_insns_num = 0;
9052 curr_state->branch_deviation = 0;
9053 curr_state->middle_bundle_stops = 0;
9054 curr_state->next = NULL;
9055 curr_state->originator = NULL;
9056 state_reset (curr_state->dfa_state);
9057 index_to_bundle_states [0] = curr_state;
9058 insn_num = 0;
9059 /* Shift cycle mark if it is put on insn which could be ignored. */
9060 for (insn = NEXT_INSN (prev_head_insn);
9061 insn != tail;
9062 insn = NEXT_INSN (insn))
9063 if (INSN_P (insn)
9064 && !important_for_bundling_p (insn)
9065 && GET_MODE (insn) == TImode)
9066 {
9067 PUT_MODE (insn, VOIDmode);
9068 for (next_insn = NEXT_INSN (insn);
9069 next_insn != tail;
9070 next_insn = NEXT_INSN (next_insn))
9071 if (important_for_bundling_p (next_insn)
9072 && INSN_CODE (next_insn) != CODE_FOR_insn_group_barrier)
9073 {
9074 PUT_MODE (next_insn, TImode);
9075 break;
9076 }
9077 }
9078 /* Forward pass: generation of bundle states. */
9079 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
9080 insn != NULL_RTX;
9081 insn = next_insn)
9082 {
9083 gcc_assert (important_for_bundling_p (insn));
9084 type = ia64_safe_type (insn);
9085 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
9086 insn_num++;
9087 index_to_bundle_states [insn_num] = NULL;
9088 for (curr_state = index_to_bundle_states [insn_num - 1];
9089 curr_state != NULL;
9090 curr_state = next_state)
9091 {
9092 pos = curr_state->accumulated_insns_num % 3;
9093 next_state = curr_state->next;
9094 /* We must fill up the current bundle in order to start a
9095 subsequent asm insn in a new bundle. Asm insn is always
9096 placed in a separate bundle. */
9097 only_bundle_end_p
9098 = (next_insn != NULL_RTX
9099 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
9100 && unknown_for_bundling_p (next_insn));
9101 /* We may fill up the current bundle if it is the cycle end
9102 without a group barrier. */
9103 bundle_end_p
9104 = (only_bundle_end_p || next_insn == NULL_RTX
9105 || (GET_MODE (next_insn) == TImode
9106 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
9107 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
9108 || type == TYPE_S)
9109 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
9110 only_bundle_end_p);
9111 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
9112 only_bundle_end_p);
9113 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
9114 only_bundle_end_p);
9115 }
9116 gcc_assert (index_to_bundle_states [insn_num]);
9117 for (curr_state = index_to_bundle_states [insn_num];
9118 curr_state != NULL;
9119 curr_state = curr_state->next)
9120 if (verbose >= 2 && dump)
9121 {
9122 /* This structure is taken from generated code of the
9123 pipeline hazard recognizer (see file insn-attrtab.c).
9124 Please don't forget to change the structure if a new
9125 automaton is added to .md file. */
9126 struct DFA_chip
9127 {
9128 unsigned short one_automaton_state;
9129 unsigned short oneb_automaton_state;
9130 unsigned short two_automaton_state;
9131 unsigned short twob_automaton_state;
9132 };
9133
9134 fprintf
9135 (dump,
9136 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n",
9137 curr_state->unique_num,
9138 (curr_state->originator == NULL
9139 ? -1 : curr_state->originator->unique_num),
9140 curr_state->cost,
9141 curr_state->before_nops_num, curr_state->after_nops_num,
9142 curr_state->accumulated_insns_num, curr_state->branch_deviation,
9143 curr_state->middle_bundle_stops,
9144 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
9145 INSN_UID (insn));
9146 }
9147 }
9148
9149 /* We should find a solution because the 2nd insn scheduling has
9150 found one. */
9151 gcc_assert (index_to_bundle_states [insn_num]);
9152 /* Find a state corresponding to the best insn sequence. */
9153 best_state = NULL;
9154 for (curr_state = index_to_bundle_states [insn_num];
9155 curr_state != NULL;
9156 curr_state = curr_state->next)
9157 /* We are just looking at the states with fully filled up last
9158 bundle. The first we prefer insn sequences with minimal cost
9159 then with minimal inserted nops and finally with branch insns
9160 placed in the 3rd slots. */
9161 if (curr_state->accumulated_insns_num % 3 == 0
9162 && (best_state == NULL || best_state->cost > curr_state->cost
9163 || (best_state->cost == curr_state->cost
9164 && (curr_state->accumulated_insns_num
9165 < best_state->accumulated_insns_num
9166 || (curr_state->accumulated_insns_num
9167 == best_state->accumulated_insns_num
9168 && (curr_state->branch_deviation
9169 < best_state->branch_deviation
9170 || (curr_state->branch_deviation
9171 == best_state->branch_deviation
9172 && curr_state->middle_bundle_stops
9173 < best_state->middle_bundle_stops)))))))
9174 best_state = curr_state;
9175 /* Second (backward) pass: adding nops and templates. */
9176 gcc_assert (best_state);
9177 insn_num = best_state->before_nops_num;
9178 template0 = template1 = -1;
9179 for (curr_state = best_state;
9180 curr_state->originator != NULL;
9181 curr_state = curr_state->originator)
9182 {
9183 insn = curr_state->insn;
9184 asm_p = unknown_for_bundling_p (insn);
9185 insn_num++;
9186 if (verbose >= 2 && dump)
9187 {
9188 struct DFA_chip
9189 {
9190 unsigned short one_automaton_state;
9191 unsigned short oneb_automaton_state;
9192 unsigned short two_automaton_state;
9193 unsigned short twob_automaton_state;
9194 };
9195
9196 fprintf
9197 (dump,
9198 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n",
9199 curr_state->unique_num,
9200 (curr_state->originator == NULL
9201 ? -1 : curr_state->originator->unique_num),
9202 curr_state->cost,
9203 curr_state->before_nops_num, curr_state->after_nops_num,
9204 curr_state->accumulated_insns_num, curr_state->branch_deviation,
9205 curr_state->middle_bundle_stops,
9206 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
9207 INSN_UID (insn));
9208 }
9209 /* Find the position in the current bundle window. The window can
9210 contain at most two bundles. Two bundle window means that
9211 the processor will make two bundle rotation. */
9212 max_pos = get_max_pos (curr_state->dfa_state);
9213 if (max_pos == 6
9214 /* The following (negative template number) means that the
9215 processor did one bundle rotation. */
9216 || (max_pos == 3 && template0 < 0))
9217 {
9218 /* We are at the end of the window -- find template(s) for
9219 its bundle(s). */
9220 pos = max_pos;
9221 if (max_pos == 3)
9222 template0 = get_template (curr_state->dfa_state, 3);
9223 else
9224 {
9225 template1 = get_template (curr_state->dfa_state, 3);
9226 template0 = get_template (curr_state->dfa_state, 6);
9227 }
9228 }
9229 if (max_pos > 3 && template1 < 0)
9230 /* It may happen when we have the stop inside a bundle. */
9231 {
9232 gcc_assert (pos <= 3);
9233 template1 = get_template (curr_state->dfa_state, 3);
9234 pos += 3;
9235 }
9236 if (!asm_p)
9237 /* Emit nops after the current insn. */
9238 for (i = 0; i < curr_state->after_nops_num; i++)
9239 {
9240 nop = gen_nop ();
9241 emit_insn_after (nop, insn);
9242 pos--;
9243 gcc_assert (pos >= 0);
9244 if (pos % 3 == 0)
9245 {
9246 /* We are at the start of a bundle: emit the template
9247 (it should be defined). */
9248 gcc_assert (template0 >= 0);
9249 ia64_add_bundle_selector_before (template0, nop);
9250 /* If we have two bundle window, we make one bundle
9251 rotation. Otherwise template0 will be undefined
9252 (negative value). */
9253 template0 = template1;
9254 template1 = -1;
9255 }
9256 }
9257 /* Move the position backward in the window. Group barrier has
9258 no slot. Asm insn takes all bundle. */
9259 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
9260 && !unknown_for_bundling_p (insn))
9261 pos--;
9262 /* Long insn takes 2 slots. */
9263 if (ia64_safe_type (insn) == TYPE_L)
9264 pos--;
9265 gcc_assert (pos >= 0);
9266 if (pos % 3 == 0
9267 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
9268 && !unknown_for_bundling_p (insn))
9269 {
9270 /* The current insn is at the bundle start: emit the
9271 template. */
9272 gcc_assert (template0 >= 0);
9273 ia64_add_bundle_selector_before (template0, insn);
9274 b = PREV_INSN (insn);
9275 insn = b;
9276 /* See comment above in analogous place for emitting nops
9277 after the insn. */
9278 template0 = template1;
9279 template1 = -1;
9280 }
9281 /* Emit nops after the current insn. */
9282 for (i = 0; i < curr_state->before_nops_num; i++)
9283 {
9284 nop = gen_nop ();
9285 ia64_emit_insn_before (nop, insn);
9286 nop = PREV_INSN (insn);
9287 insn = nop;
9288 pos--;
9289 gcc_assert (pos >= 0);
9290 if (pos % 3 == 0)
9291 {
9292 /* See comment above in analogous place for emitting nops
9293 after the insn. */
9294 gcc_assert (template0 >= 0);
9295 ia64_add_bundle_selector_before (template0, insn);
9296 b = PREV_INSN (insn);
9297 insn = b;
9298 template0 = template1;
9299 template1 = -1;
9300 }
9301 }
9302 }
9303
9304 #ifdef ENABLE_CHECKING
9305 {
9306 /* Assert right calculation of middle_bundle_stops. */
9307 int num = best_state->middle_bundle_stops;
9308 bool start_bundle = true, end_bundle = false;
9309
9310 for (insn = NEXT_INSN (prev_head_insn);
9311 insn && insn != tail;
9312 insn = NEXT_INSN (insn))
9313 {
9314 if (!INSN_P (insn))
9315 continue;
9316 if (recog_memoized (insn) == CODE_FOR_bundle_selector)
9317 start_bundle = true;
9318 else
9319 {
9320 rtx next_insn;
9321
9322 for (next_insn = NEXT_INSN (insn);
9323 next_insn && next_insn != tail;
9324 next_insn = NEXT_INSN (next_insn))
9325 if (INSN_P (next_insn)
9326 && (ia64_safe_itanium_class (next_insn)
9327 != ITANIUM_CLASS_IGNORE
9328 || recog_memoized (next_insn)
9329 == CODE_FOR_bundle_selector)
9330 && GET_CODE (PATTERN (next_insn)) != USE
9331 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
9332 break;
9333
9334 end_bundle = next_insn == NULL_RTX
9335 || next_insn == tail
9336 || (INSN_P (next_insn)
9337 && recog_memoized (next_insn)
9338 == CODE_FOR_bundle_selector);
9339 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier
9340 && !start_bundle && !end_bundle
9341 && next_insn
9342 && !unknown_for_bundling_p (next_insn))
9343 num--;
9344
9345 start_bundle = false;
9346 }
9347 }
9348
9349 gcc_assert (num == 0);
9350 }
9351 #endif
9352
9353 free (index_to_bundle_states);
9354 finish_bundle_state_table ();
9355 bundling_p = 0;
9356 dfa_clean_insn_cache ();
9357 }
9358
9359 /* The following function is called at the end of scheduling BB or
9360 EBB. After reload, it inserts stop bits and does insn bundling. */
9361
9362 static void
9363 ia64_sched_finish (FILE *dump, int sched_verbose)
9364 {
9365 if (sched_verbose)
9366 fprintf (dump, "// Finishing schedule.\n");
9367 if (!reload_completed)
9368 return;
9369 if (reload_completed)
9370 {
9371 final_emit_insn_group_barriers (dump);
9372 bundling (dump, sched_verbose, current_sched_info->prev_head,
9373 current_sched_info->next_tail);
9374 if (sched_verbose && dump)
9375 fprintf (dump, "// finishing %d-%d\n",
9376 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
9377 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
9378
9379 return;
9380 }
9381 }
9382
9383 /* The following function inserts stop bits in scheduled BB or EBB. */
9384
9385 static void
9386 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
9387 {
9388 rtx_insn *insn;
9389 int need_barrier_p = 0;
9390 int seen_good_insn = 0;
9391
9392 init_insn_group_barriers ();
9393
9394 for (insn = NEXT_INSN (current_sched_info->prev_head);
9395 insn != current_sched_info->next_tail;
9396 insn = NEXT_INSN (insn))
9397 {
9398 if (BARRIER_P (insn))
9399 {
9400 rtx_insn *last = prev_active_insn (insn);
9401
9402 if (! last)
9403 continue;
9404 if (JUMP_TABLE_DATA_P (last))
9405 last = prev_active_insn (last);
9406 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
9407 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
9408
9409 init_insn_group_barriers ();
9410 seen_good_insn = 0;
9411 need_barrier_p = 0;
9412 }
9413 else if (NONDEBUG_INSN_P (insn))
9414 {
9415 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
9416 {
9417 init_insn_group_barriers ();
9418 seen_good_insn = 0;
9419 need_barrier_p = 0;
9420 }
9421 else if (need_barrier_p || group_barrier_needed (insn)
9422 || (mflag_sched_stop_bits_after_every_cycle
9423 && GET_MODE (insn) == TImode
9424 && seen_good_insn))
9425 {
9426 if (TARGET_EARLY_STOP_BITS)
9427 {
9428 rtx_insn *last;
9429
9430 for (last = insn;
9431 last != current_sched_info->prev_head;
9432 last = PREV_INSN (last))
9433 if (INSN_P (last) && GET_MODE (last) == TImode
9434 && stops_p [INSN_UID (last)])
9435 break;
9436 if (last == current_sched_info->prev_head)
9437 last = insn;
9438 last = prev_active_insn (last);
9439 if (last
9440 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
9441 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
9442 last);
9443 init_insn_group_barriers ();
9444 for (last = NEXT_INSN (last);
9445 last != insn;
9446 last = NEXT_INSN (last))
9447 if (INSN_P (last))
9448 {
9449 group_barrier_needed (last);
9450 if (recog_memoized (last) >= 0
9451 && important_for_bundling_p (last))
9452 seen_good_insn = 1;
9453 }
9454 }
9455 else
9456 {
9457 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
9458 insn);
9459 init_insn_group_barriers ();
9460 seen_good_insn = 0;
9461 }
9462 group_barrier_needed (insn);
9463 if (recog_memoized (insn) >= 0
9464 && important_for_bundling_p (insn))
9465 seen_good_insn = 1;
9466 }
9467 else if (recog_memoized (insn) >= 0
9468 && important_for_bundling_p (insn))
9469 seen_good_insn = 1;
9470 need_barrier_p = (CALL_P (insn) || unknown_for_bundling_p (insn));
9471 }
9472 }
9473 }
9474
9475 \f
9476
9477 /* If the following function returns TRUE, we will use the DFA
9478 insn scheduler. */
9479
9480 static int
9481 ia64_first_cycle_multipass_dfa_lookahead (void)
9482 {
9483 return (reload_completed ? 6 : 4);
9484 }
9485
9486 /* The following function initiates variable `dfa_pre_cycle_insn'. */
9487
9488 static void
9489 ia64_init_dfa_pre_cycle_insn (void)
9490 {
9491 if (temp_dfa_state == NULL)
9492 {
9493 dfa_state_size = state_size ();
9494 temp_dfa_state = xmalloc (dfa_state_size);
9495 prev_cycle_state = xmalloc (dfa_state_size);
9496 }
9497 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
9498 SET_PREV_INSN (dfa_pre_cycle_insn) = SET_NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
9499 recog_memoized (dfa_pre_cycle_insn);
9500 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
9501 SET_PREV_INSN (dfa_stop_insn) = SET_NEXT_INSN (dfa_stop_insn) = NULL_RTX;
9502 recog_memoized (dfa_stop_insn);
9503 }
9504
9505 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
9506 used by the DFA insn scheduler. */
9507
9508 static rtx
9509 ia64_dfa_pre_cycle_insn (void)
9510 {
9511 return dfa_pre_cycle_insn;
9512 }
9513
9514 /* The following function returns TRUE if PRODUCER (of type ilog or
9515 ld) produces address for CONSUMER (of type st or stf). */
9516
9517 int
9518 ia64_st_address_bypass_p (rtx producer, rtx consumer)
9519 {
9520 rtx dest, reg, mem;
9521
9522 gcc_assert (producer && consumer);
9523 dest = ia64_single_set (producer);
9524 gcc_assert (dest);
9525 reg = SET_DEST (dest);
9526 gcc_assert (reg);
9527 if (GET_CODE (reg) == SUBREG)
9528 reg = SUBREG_REG (reg);
9529 gcc_assert (GET_CODE (reg) == REG);
9530
9531 dest = ia64_single_set (consumer);
9532 gcc_assert (dest);
9533 mem = SET_DEST (dest);
9534 gcc_assert (mem && GET_CODE (mem) == MEM);
9535 return reg_mentioned_p (reg, mem);
9536 }
9537
9538 /* The following function returns TRUE if PRODUCER (of type ilog or
9539 ld) produces address for CONSUMER (of type ld or fld). */
9540
9541 int
9542 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
9543 {
9544 rtx dest, src, reg, mem;
9545
9546 gcc_assert (producer && consumer);
9547 dest = ia64_single_set (producer);
9548 gcc_assert (dest);
9549 reg = SET_DEST (dest);
9550 gcc_assert (reg);
9551 if (GET_CODE (reg) == SUBREG)
9552 reg = SUBREG_REG (reg);
9553 gcc_assert (GET_CODE (reg) == REG);
9554
9555 src = ia64_single_set (consumer);
9556 gcc_assert (src);
9557 mem = SET_SRC (src);
9558 gcc_assert (mem);
9559
9560 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
9561 mem = XVECEXP (mem, 0, 0);
9562 else if (GET_CODE (mem) == IF_THEN_ELSE)
9563 /* ??? Is this bypass necessary for ld.c? */
9564 {
9565 gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR);
9566 mem = XEXP (mem, 1);
9567 }
9568
9569 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
9570 mem = XEXP (mem, 0);
9571
9572 if (GET_CODE (mem) == UNSPEC)
9573 {
9574 int c = XINT (mem, 1);
9575
9576 gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A
9577 || c == UNSPEC_LDSA);
9578 mem = XVECEXP (mem, 0, 0);
9579 }
9580
9581 /* Note that LO_SUM is used for GOT loads. */
9582 gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
9583
9584 return reg_mentioned_p (reg, mem);
9585 }
9586
9587 /* The following function returns TRUE if INSN produces address for a
9588 load/store insn. We will place such insns into M slot because it
9589 decreases its latency time. */
9590
9591 int
9592 ia64_produce_address_p (rtx insn)
9593 {
9594 return insn->call;
9595 }
9596
9597 \f
9598 /* Emit pseudo-ops for the assembler to describe predicate relations.
9599 At present this assumes that we only consider predicate pairs to
9600 be mutex, and that the assembler can deduce proper values from
9601 straight-line code. */
9602
9603 static void
9604 emit_predicate_relation_info (void)
9605 {
9606 basic_block bb;
9607
9608 FOR_EACH_BB_REVERSE_FN (bb, cfun)
9609 {
9610 int r;
9611 rtx_insn *head = BB_HEAD (bb);
9612
9613 /* We only need such notes at code labels. */
9614 if (! LABEL_P (head))
9615 continue;
9616 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head)))
9617 head = NEXT_INSN (head);
9618
9619 /* Skip p0, which may be thought to be live due to (reg:DI p0)
9620 grabbing the entire block of predicate registers. */
9621 for (r = PR_REG (2); r < PR_REG (64); r += 2)
9622 if (REGNO_REG_SET_P (df_get_live_in (bb), r))
9623 {
9624 rtx p = gen_rtx_REG (BImode, r);
9625 rtx_insn *n = emit_insn_after (gen_pred_rel_mutex (p), head);
9626 if (head == BB_END (bb))
9627 BB_END (bb) = n;
9628 head = n;
9629 }
9630 }
9631
9632 /* Look for conditional calls that do not return, and protect predicate
9633 relations around them. Otherwise the assembler will assume the call
9634 returns, and complain about uses of call-clobbered predicates after
9635 the call. */
9636 FOR_EACH_BB_REVERSE_FN (bb, cfun)
9637 {
9638 rtx_insn *insn = BB_HEAD (bb);
9639
9640 while (1)
9641 {
9642 if (CALL_P (insn)
9643 && GET_CODE (PATTERN (insn)) == COND_EXEC
9644 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
9645 {
9646 rtx_insn *b =
9647 emit_insn_before (gen_safe_across_calls_all (), insn);
9648 rtx_insn *a = emit_insn_after (gen_safe_across_calls_normal (), insn);
9649 if (BB_HEAD (bb) == insn)
9650 BB_HEAD (bb) = b;
9651 if (BB_END (bb) == insn)
9652 BB_END (bb) = a;
9653 }
9654
9655 if (insn == BB_END (bb))
9656 break;
9657 insn = NEXT_INSN (insn);
9658 }
9659 }
9660 }
9661
9662 /* Perform machine dependent operations on the rtl chain INSNS. */
9663
9664 static void
9665 ia64_reorg (void)
9666 {
9667 /* We are freeing block_for_insn in the toplev to keep compatibility
9668 with old MDEP_REORGS that are not CFG based. Recompute it now. */
9669 compute_bb_for_insn ();
9670
9671 /* If optimizing, we'll have split before scheduling. */
9672 if (optimize == 0)
9673 split_all_insns ();
9674
9675 if (optimize && flag_schedule_insns_after_reload
9676 && dbg_cnt (ia64_sched2))
9677 {
9678 basic_block bb;
9679 timevar_push (TV_SCHED2);
9680 ia64_final_schedule = 1;
9681
9682 /* We can't let modulo-sched prevent us from scheduling any bbs,
9683 since we need the final schedule to produce bundle information. */
9684 FOR_EACH_BB_FN (bb, cfun)
9685 bb->flags &= ~BB_DISABLE_SCHEDULE;
9686
9687 initiate_bundle_states ();
9688 ia64_nop = make_insn_raw (gen_nop ());
9689 SET_PREV_INSN (ia64_nop) = SET_NEXT_INSN (ia64_nop) = NULL_RTX;
9690 recog_memoized (ia64_nop);
9691 clocks_length = get_max_uid () + 1;
9692 stops_p = XCNEWVEC (char, clocks_length);
9693
9694 if (ia64_tune == PROCESSOR_ITANIUM2)
9695 {
9696 pos_1 = get_cpu_unit_code ("2_1");
9697 pos_2 = get_cpu_unit_code ("2_2");
9698 pos_3 = get_cpu_unit_code ("2_3");
9699 pos_4 = get_cpu_unit_code ("2_4");
9700 pos_5 = get_cpu_unit_code ("2_5");
9701 pos_6 = get_cpu_unit_code ("2_6");
9702 _0mii_ = get_cpu_unit_code ("2b_0mii.");
9703 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
9704 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
9705 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
9706 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
9707 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
9708 _0mib_ = get_cpu_unit_code ("2b_0mib.");
9709 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
9710 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
9711 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
9712 _1mii_ = get_cpu_unit_code ("2b_1mii.");
9713 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
9714 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
9715 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
9716 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
9717 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
9718 _1mib_ = get_cpu_unit_code ("2b_1mib.");
9719 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
9720 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
9721 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
9722 }
9723 else
9724 {
9725 pos_1 = get_cpu_unit_code ("1_1");
9726 pos_2 = get_cpu_unit_code ("1_2");
9727 pos_3 = get_cpu_unit_code ("1_3");
9728 pos_4 = get_cpu_unit_code ("1_4");
9729 pos_5 = get_cpu_unit_code ("1_5");
9730 pos_6 = get_cpu_unit_code ("1_6");
9731 _0mii_ = get_cpu_unit_code ("1b_0mii.");
9732 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
9733 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
9734 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
9735 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
9736 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
9737 _0mib_ = get_cpu_unit_code ("1b_0mib.");
9738 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
9739 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
9740 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
9741 _1mii_ = get_cpu_unit_code ("1b_1mii.");
9742 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
9743 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
9744 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
9745 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
9746 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
9747 _1mib_ = get_cpu_unit_code ("1b_1mib.");
9748 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
9749 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
9750 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
9751 }
9752
9753 if (flag_selective_scheduling2
9754 && !maybe_skip_selective_scheduling ())
9755 run_selective_scheduling ();
9756 else
9757 schedule_ebbs ();
9758
9759 /* Redo alignment computation, as it might gone wrong. */
9760 compute_alignments ();
9761
9762 /* We cannot reuse this one because it has been corrupted by the
9763 evil glat. */
9764 finish_bundle_states ();
9765 free (stops_p);
9766 stops_p = NULL;
9767 emit_insn_group_barriers (dump_file);
9768
9769 ia64_final_schedule = 0;
9770 timevar_pop (TV_SCHED2);
9771 }
9772 else
9773 emit_all_insn_group_barriers (dump_file);
9774
9775 df_analyze ();
9776
9777 /* A call must not be the last instruction in a function, so that the
9778 return address is still within the function, so that unwinding works
9779 properly. Note that IA-64 differs from dwarf2 on this point. */
9780 if (ia64_except_unwind_info (&global_options) == UI_TARGET)
9781 {
9782 rtx_insn *insn;
9783 int saw_stop = 0;
9784
9785 insn = get_last_insn ();
9786 if (! INSN_P (insn))
9787 insn = prev_active_insn (insn);
9788 if (insn)
9789 {
9790 /* Skip over insns that expand to nothing. */
9791 while (NONJUMP_INSN_P (insn)
9792 && get_attr_empty (insn) == EMPTY_YES)
9793 {
9794 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
9795 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
9796 saw_stop = 1;
9797 insn = prev_active_insn (insn);
9798 }
9799 if (CALL_P (insn))
9800 {
9801 if (! saw_stop)
9802 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9803 emit_insn (gen_break_f ());
9804 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9805 }
9806 }
9807 }
9808
9809 emit_predicate_relation_info ();
9810
9811 if (flag_var_tracking)
9812 {
9813 timevar_push (TV_VAR_TRACKING);
9814 variable_tracking_main ();
9815 timevar_pop (TV_VAR_TRACKING);
9816 }
9817 df_finish_pass (false);
9818 }
9819 \f
9820 /* Return true if REGNO is used by the epilogue. */
9821
9822 int
9823 ia64_epilogue_uses (int regno)
9824 {
9825 switch (regno)
9826 {
9827 case R_GR (1):
9828 /* With a call to a function in another module, we will write a new
9829 value to "gp". After returning from such a call, we need to make
9830 sure the function restores the original gp-value, even if the
9831 function itself does not use the gp anymore. */
9832 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
9833
9834 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
9835 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
9836 /* For functions defined with the syscall_linkage attribute, all
9837 input registers are marked as live at all function exits. This
9838 prevents the register allocator from using the input registers,
9839 which in turn makes it possible to restart a system call after
9840 an interrupt without having to save/restore the input registers.
9841 This also prevents kernel data from leaking to application code. */
9842 return lookup_attribute ("syscall_linkage",
9843 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
9844
9845 case R_BR (0):
9846 /* Conditional return patterns can't represent the use of `b0' as
9847 the return address, so we force the value live this way. */
9848 return 1;
9849
9850 case AR_PFS_REGNUM:
9851 /* Likewise for ar.pfs, which is used by br.ret. */
9852 return 1;
9853
9854 default:
9855 return 0;
9856 }
9857 }
9858
9859 /* Return true if REGNO is used by the frame unwinder. */
9860
9861 int
9862 ia64_eh_uses (int regno)
9863 {
9864 unsigned int r;
9865
9866 if (! reload_completed)
9867 return 0;
9868
9869 if (regno == 0)
9870 return 0;
9871
9872 for (r = reg_save_b0; r <= reg_save_ar_lc; r++)
9873 if (regno == current_frame_info.r[r]
9874 || regno == emitted_frame_related_regs[r])
9875 return 1;
9876
9877 return 0;
9878 }
9879 \f
9880 /* Return true if this goes in small data/bss. */
9881
9882 /* ??? We could also support own long data here. Generating movl/add/ld8
9883 instead of addl,ld8/ld8. This makes the code bigger, but should make the
9884 code faster because there is one less load. This also includes incomplete
9885 types which can't go in sdata/sbss. */
9886
9887 static bool
9888 ia64_in_small_data_p (const_tree exp)
9889 {
9890 if (TARGET_NO_SDATA)
9891 return false;
9892
9893 /* We want to merge strings, so we never consider them small data. */
9894 if (TREE_CODE (exp) == STRING_CST)
9895 return false;
9896
9897 /* Functions are never small data. */
9898 if (TREE_CODE (exp) == FUNCTION_DECL)
9899 return false;
9900
9901 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
9902 {
9903 const char *section = DECL_SECTION_NAME (exp);
9904
9905 if (strcmp (section, ".sdata") == 0
9906 || strncmp (section, ".sdata.", 7) == 0
9907 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9908 || strcmp (section, ".sbss") == 0
9909 || strncmp (section, ".sbss.", 6) == 0
9910 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9911 return true;
9912 }
9913 else
9914 {
9915 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
9916
9917 /* If this is an incomplete type with size 0, then we can't put it
9918 in sdata because it might be too big when completed. */
9919 if (size > 0 && size <= ia64_section_threshold)
9920 return true;
9921 }
9922
9923 return false;
9924 }
9925 \f
9926 /* Output assembly directives for prologue regions. */
9927
9928 /* The current basic block number. */
9929
9930 static bool last_block;
9931
9932 /* True if we need a copy_state command at the start of the next block. */
9933
9934 static bool need_copy_state;
9935
9936 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
9937 # define MAX_ARTIFICIAL_LABEL_BYTES 30
9938 #endif
9939
9940 /* The function emits unwind directives for the start of an epilogue. */
9941
9942 static void
9943 process_epilogue (FILE *asm_out_file, rtx insn ATTRIBUTE_UNUSED,
9944 bool unwind, bool frame ATTRIBUTE_UNUSED)
9945 {
9946 /* If this isn't the last block of the function, then we need to label the
9947 current state, and copy it back in at the start of the next block. */
9948
9949 if (!last_block)
9950 {
9951 if (unwind)
9952 fprintf (asm_out_file, "\t.label_state %d\n",
9953 ++cfun->machine->state_num);
9954 need_copy_state = true;
9955 }
9956
9957 if (unwind)
9958 fprintf (asm_out_file, "\t.restore sp\n");
9959 }
9960
9961 /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */
9962
9963 static void
9964 process_cfa_adjust_cfa (FILE *asm_out_file, rtx pat, rtx insn,
9965 bool unwind, bool frame)
9966 {
9967 rtx dest = SET_DEST (pat);
9968 rtx src = SET_SRC (pat);
9969
9970 if (dest == stack_pointer_rtx)
9971 {
9972 if (GET_CODE (src) == PLUS)
9973 {
9974 rtx op0 = XEXP (src, 0);
9975 rtx op1 = XEXP (src, 1);
9976
9977 gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
9978
9979 if (INTVAL (op1) < 0)
9980 {
9981 gcc_assert (!frame_pointer_needed);
9982 if (unwind)
9983 fprintf (asm_out_file,
9984 "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
9985 -INTVAL (op1));
9986 }
9987 else
9988 process_epilogue (asm_out_file, insn, unwind, frame);
9989 }
9990 else
9991 {
9992 gcc_assert (src == hard_frame_pointer_rtx);
9993 process_epilogue (asm_out_file, insn, unwind, frame);
9994 }
9995 }
9996 else if (dest == hard_frame_pointer_rtx)
9997 {
9998 gcc_assert (src == stack_pointer_rtx);
9999 gcc_assert (frame_pointer_needed);
10000
10001 if (unwind)
10002 fprintf (asm_out_file, "\t.vframe r%d\n",
10003 ia64_dbx_register_number (REGNO (dest)));
10004 }
10005 else
10006 gcc_unreachable ();
10007 }
10008
10009 /* This function processes a SET pattern for REG_CFA_REGISTER. */
10010
10011 static void
10012 process_cfa_register (FILE *asm_out_file, rtx pat, bool unwind)
10013 {
10014 rtx dest = SET_DEST (pat);
10015 rtx src = SET_SRC (pat);
10016 int dest_regno = REGNO (dest);
10017 int src_regno;
10018
10019 if (src == pc_rtx)
10020 {
10021 /* Saving return address pointer. */
10022 if (unwind)
10023 fprintf (asm_out_file, "\t.save rp, r%d\n",
10024 ia64_dbx_register_number (dest_regno));
10025 return;
10026 }
10027
10028 src_regno = REGNO (src);
10029
10030 switch (src_regno)
10031 {
10032 case PR_REG (0):
10033 gcc_assert (dest_regno == current_frame_info.r[reg_save_pr]);
10034 if (unwind)
10035 fprintf (asm_out_file, "\t.save pr, r%d\n",
10036 ia64_dbx_register_number (dest_regno));
10037 break;
10038
10039 case AR_UNAT_REGNUM:
10040 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_unat]);
10041 if (unwind)
10042 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
10043 ia64_dbx_register_number (dest_regno));
10044 break;
10045
10046 case AR_LC_REGNUM:
10047 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_lc]);
10048 if (unwind)
10049 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
10050 ia64_dbx_register_number (dest_regno));
10051 break;
10052
10053 default:
10054 /* Everything else should indicate being stored to memory. */
10055 gcc_unreachable ();
10056 }
10057 }
10058
10059 /* This function processes a SET pattern for REG_CFA_OFFSET. */
10060
10061 static void
10062 process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind)
10063 {
10064 rtx dest = SET_DEST (pat);
10065 rtx src = SET_SRC (pat);
10066 int src_regno = REGNO (src);
10067 const char *saveop;
10068 HOST_WIDE_INT off;
10069 rtx base;
10070
10071 gcc_assert (MEM_P (dest));
10072 if (GET_CODE (XEXP (dest, 0)) == REG)
10073 {
10074 base = XEXP (dest, 0);
10075 off = 0;
10076 }
10077 else
10078 {
10079 gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
10080 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
10081 base = XEXP (XEXP (dest, 0), 0);
10082 off = INTVAL (XEXP (XEXP (dest, 0), 1));
10083 }
10084
10085 if (base == hard_frame_pointer_rtx)
10086 {
10087 saveop = ".savepsp";
10088 off = - off;
10089 }
10090 else
10091 {
10092 gcc_assert (base == stack_pointer_rtx);
10093 saveop = ".savesp";
10094 }
10095
10096 src_regno = REGNO (src);
10097 switch (src_regno)
10098 {
10099 case BR_REG (0):
10100 gcc_assert (!current_frame_info.r[reg_save_b0]);
10101 if (unwind)
10102 fprintf (asm_out_file, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC "\n",
10103 saveop, off);
10104 break;
10105
10106 case PR_REG (0):
10107 gcc_assert (!current_frame_info.r[reg_save_pr]);
10108 if (unwind)
10109 fprintf (asm_out_file, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC "\n",
10110 saveop, off);
10111 break;
10112
10113 case AR_LC_REGNUM:
10114 gcc_assert (!current_frame_info.r[reg_save_ar_lc]);
10115 if (unwind)
10116 fprintf (asm_out_file, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC "\n",
10117 saveop, off);
10118 break;
10119
10120 case AR_PFS_REGNUM:
10121 gcc_assert (!current_frame_info.r[reg_save_ar_pfs]);
10122 if (unwind)
10123 fprintf (asm_out_file, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC "\n",
10124 saveop, off);
10125 break;
10126
10127 case AR_UNAT_REGNUM:
10128 gcc_assert (!current_frame_info.r[reg_save_ar_unat]);
10129 if (unwind)
10130 fprintf (asm_out_file, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC "\n",
10131 saveop, off);
10132 break;
10133
10134 case GR_REG (4):
10135 case GR_REG (5):
10136 case GR_REG (6):
10137 case GR_REG (7):
10138 if (unwind)
10139 fprintf (asm_out_file, "\t.save.g 0x%x\n",
10140 1 << (src_regno - GR_REG (4)));
10141 break;
10142
10143 case BR_REG (1):
10144 case BR_REG (2):
10145 case BR_REG (3):
10146 case BR_REG (4):
10147 case BR_REG (5):
10148 if (unwind)
10149 fprintf (asm_out_file, "\t.save.b 0x%x\n",
10150 1 << (src_regno - BR_REG (1)));
10151 break;
10152
10153 case FR_REG (2):
10154 case FR_REG (3):
10155 case FR_REG (4):
10156 case FR_REG (5):
10157 if (unwind)
10158 fprintf (asm_out_file, "\t.save.f 0x%x\n",
10159 1 << (src_regno - FR_REG (2)));
10160 break;
10161
10162 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
10163 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
10164 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
10165 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
10166 if (unwind)
10167 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
10168 1 << (src_regno - FR_REG (12)));
10169 break;
10170
10171 default:
10172 /* ??? For some reason we mark other general registers, even those
10173 we can't represent in the unwind info. Ignore them. */
10174 break;
10175 }
10176 }
10177
10178 /* This function looks at a single insn and emits any directives
10179 required to unwind this insn. */
10180
10181 static void
10182 ia64_asm_unwind_emit (FILE *asm_out_file, rtx_insn *insn)
10183 {
10184 bool unwind = ia64_except_unwind_info (&global_options) == UI_TARGET;
10185 bool frame = dwarf2out_do_frame ();
10186 rtx note, pat;
10187 bool handled_one;
10188
10189 if (!unwind && !frame)
10190 return;
10191
10192 if (NOTE_INSN_BASIC_BLOCK_P (insn))
10193 {
10194 last_block = NOTE_BASIC_BLOCK (insn)->next_bb
10195 == EXIT_BLOCK_PTR_FOR_FN (cfun);
10196
10197 /* Restore unwind state from immediately before the epilogue. */
10198 if (need_copy_state)
10199 {
10200 if (unwind)
10201 {
10202 fprintf (asm_out_file, "\t.body\n");
10203 fprintf (asm_out_file, "\t.copy_state %d\n",
10204 cfun->machine->state_num);
10205 }
10206 need_copy_state = false;
10207 }
10208 }
10209
10210 if (NOTE_P (insn) || ! RTX_FRAME_RELATED_P (insn))
10211 return;
10212
10213 /* Look for the ALLOC insn. */
10214 if (INSN_CODE (insn) == CODE_FOR_alloc)
10215 {
10216 rtx dest = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
10217 int dest_regno = REGNO (dest);
10218
10219 /* If this is the final destination for ar.pfs, then this must
10220 be the alloc in the prologue. */
10221 if (dest_regno == current_frame_info.r[reg_save_ar_pfs])
10222 {
10223 if (unwind)
10224 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
10225 ia64_dbx_register_number (dest_regno));
10226 }
10227 else
10228 {
10229 /* This must be an alloc before a sibcall. We must drop the
10230 old frame info. The easiest way to drop the old frame
10231 info is to ensure we had a ".restore sp" directive
10232 followed by a new prologue. If the procedure doesn't
10233 have a memory-stack frame, we'll issue a dummy ".restore
10234 sp" now. */
10235 if (current_frame_info.total_size == 0 && !frame_pointer_needed)
10236 /* if haven't done process_epilogue() yet, do it now */
10237 process_epilogue (asm_out_file, insn, unwind, frame);
10238 if (unwind)
10239 fprintf (asm_out_file, "\t.prologue\n");
10240 }
10241 return;
10242 }
10243
10244 handled_one = false;
10245 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
10246 switch (REG_NOTE_KIND (note))
10247 {
10248 case REG_CFA_ADJUST_CFA:
10249 pat = XEXP (note, 0);
10250 if (pat == NULL)
10251 pat = PATTERN (insn);
10252 process_cfa_adjust_cfa (asm_out_file, pat, insn, unwind, frame);
10253 handled_one = true;
10254 break;
10255
10256 case REG_CFA_OFFSET:
10257 pat = XEXP (note, 0);
10258 if (pat == NULL)
10259 pat = PATTERN (insn);
10260 process_cfa_offset (asm_out_file, pat, unwind);
10261 handled_one = true;
10262 break;
10263
10264 case REG_CFA_REGISTER:
10265 pat = XEXP (note, 0);
10266 if (pat == NULL)
10267 pat = PATTERN (insn);
10268 process_cfa_register (asm_out_file, pat, unwind);
10269 handled_one = true;
10270 break;
10271
10272 case REG_FRAME_RELATED_EXPR:
10273 case REG_CFA_DEF_CFA:
10274 case REG_CFA_EXPRESSION:
10275 case REG_CFA_RESTORE:
10276 case REG_CFA_SET_VDRAP:
10277 /* Not used in the ia64 port. */
10278 gcc_unreachable ();
10279
10280 default:
10281 /* Not a frame-related note. */
10282 break;
10283 }
10284
10285 /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the
10286 explicit action to take. No guessing required. */
10287 gcc_assert (handled_one);
10288 }
10289
10290 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
10291
10292 static void
10293 ia64_asm_emit_except_personality (rtx personality)
10294 {
10295 fputs ("\t.personality\t", asm_out_file);
10296 output_addr_const (asm_out_file, personality);
10297 fputc ('\n', asm_out_file);
10298 }
10299
10300 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
10301
10302 static void
10303 ia64_asm_init_sections (void)
10304 {
10305 exception_section = get_unnamed_section (0, output_section_asm_op,
10306 "\t.handlerdata");
10307 }
10308
10309 /* Implement TARGET_DEBUG_UNWIND_INFO. */
10310
10311 static enum unwind_info_type
10312 ia64_debug_unwind_info (void)
10313 {
10314 return UI_TARGET;
10315 }
10316 \f
10317 enum ia64_builtins
10318 {
10319 IA64_BUILTIN_BSP,
10320 IA64_BUILTIN_COPYSIGNQ,
10321 IA64_BUILTIN_FABSQ,
10322 IA64_BUILTIN_FLUSHRS,
10323 IA64_BUILTIN_INFQ,
10324 IA64_BUILTIN_HUGE_VALQ,
10325 IA64_BUILTIN_max
10326 };
10327
10328 static GTY(()) tree ia64_builtins[(int) IA64_BUILTIN_max];
10329
10330 void
10331 ia64_init_builtins (void)
10332 {
10333 tree fpreg_type;
10334 tree float80_type;
10335 tree decl;
10336
10337 /* The __fpreg type. */
10338 fpreg_type = make_node (REAL_TYPE);
10339 TYPE_PRECISION (fpreg_type) = 82;
10340 layout_type (fpreg_type);
10341 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
10342
10343 /* The __float80 type. */
10344 float80_type = make_node (REAL_TYPE);
10345 TYPE_PRECISION (float80_type) = 80;
10346 layout_type (float80_type);
10347 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
10348
10349 /* The __float128 type. */
10350 if (!TARGET_HPUX)
10351 {
10352 tree ftype;
10353 tree float128_type = make_node (REAL_TYPE);
10354
10355 TYPE_PRECISION (float128_type) = 128;
10356 layout_type (float128_type);
10357 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
10358
10359 /* TFmode support builtins. */
10360 ftype = build_function_type_list (float128_type, NULL_TREE);
10361 decl = add_builtin_function ("__builtin_infq", ftype,
10362 IA64_BUILTIN_INFQ, BUILT_IN_MD,
10363 NULL, NULL_TREE);
10364 ia64_builtins[IA64_BUILTIN_INFQ] = decl;
10365
10366 decl = add_builtin_function ("__builtin_huge_valq", ftype,
10367 IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
10368 NULL, NULL_TREE);
10369 ia64_builtins[IA64_BUILTIN_HUGE_VALQ] = decl;
10370
10371 ftype = build_function_type_list (float128_type,
10372 float128_type,
10373 NULL_TREE);
10374 decl = add_builtin_function ("__builtin_fabsq", ftype,
10375 IA64_BUILTIN_FABSQ, BUILT_IN_MD,
10376 "__fabstf2", NULL_TREE);
10377 TREE_READONLY (decl) = 1;
10378 ia64_builtins[IA64_BUILTIN_FABSQ] = decl;
10379
10380 ftype = build_function_type_list (float128_type,
10381 float128_type,
10382 float128_type,
10383 NULL_TREE);
10384 decl = add_builtin_function ("__builtin_copysignq", ftype,
10385 IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
10386 "__copysigntf3", NULL_TREE);
10387 TREE_READONLY (decl) = 1;
10388 ia64_builtins[IA64_BUILTIN_COPYSIGNQ] = decl;
10389 }
10390 else
10391 /* Under HPUX, this is a synonym for "long double". */
10392 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
10393 "__float128");
10394
10395 /* Fwrite on VMS is non-standard. */
10396 #if TARGET_ABI_OPEN_VMS
10397 vms_patch_builtins ();
10398 #endif
10399
10400 #define def_builtin(name, type, code) \
10401 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
10402 NULL, NULL_TREE)
10403
10404 decl = def_builtin ("__builtin_ia64_bsp",
10405 build_function_type_list (ptr_type_node, NULL_TREE),
10406 IA64_BUILTIN_BSP);
10407 ia64_builtins[IA64_BUILTIN_BSP] = decl;
10408
10409 decl = def_builtin ("__builtin_ia64_flushrs",
10410 build_function_type_list (void_type_node, NULL_TREE),
10411 IA64_BUILTIN_FLUSHRS);
10412 ia64_builtins[IA64_BUILTIN_FLUSHRS] = decl;
10413
10414 #undef def_builtin
10415
10416 if (TARGET_HPUX)
10417 {
10418 if ((decl = builtin_decl_explicit (BUILT_IN_FINITE)) != NULL_TREE)
10419 set_user_assembler_name (decl, "_Isfinite");
10420 if ((decl = builtin_decl_explicit (BUILT_IN_FINITEF)) != NULL_TREE)
10421 set_user_assembler_name (decl, "_Isfinitef");
10422 if ((decl = builtin_decl_explicit (BUILT_IN_FINITEL)) != NULL_TREE)
10423 set_user_assembler_name (decl, "_Isfinitef128");
10424 }
10425 }
10426
10427 rtx
10428 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10429 enum machine_mode mode ATTRIBUTE_UNUSED,
10430 int ignore ATTRIBUTE_UNUSED)
10431 {
10432 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10433 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10434
10435 switch (fcode)
10436 {
10437 case IA64_BUILTIN_BSP:
10438 if (! target || ! register_operand (target, DImode))
10439 target = gen_reg_rtx (DImode);
10440 emit_insn (gen_bsp_value (target));
10441 #ifdef POINTERS_EXTEND_UNSIGNED
10442 target = convert_memory_address (ptr_mode, target);
10443 #endif
10444 return target;
10445
10446 case IA64_BUILTIN_FLUSHRS:
10447 emit_insn (gen_flushrs ());
10448 return const0_rtx;
10449
10450 case IA64_BUILTIN_INFQ:
10451 case IA64_BUILTIN_HUGE_VALQ:
10452 {
10453 enum machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp));
10454 REAL_VALUE_TYPE inf;
10455 rtx tmp;
10456
10457 real_inf (&inf);
10458 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode);
10459
10460 tmp = validize_mem (force_const_mem (target_mode, tmp));
10461
10462 if (target == 0)
10463 target = gen_reg_rtx (target_mode);
10464
10465 emit_move_insn (target, tmp);
10466 return target;
10467 }
10468
10469 case IA64_BUILTIN_FABSQ:
10470 case IA64_BUILTIN_COPYSIGNQ:
10471 return expand_call (exp, target, ignore);
10472
10473 default:
10474 gcc_unreachable ();
10475 }
10476
10477 return NULL_RTX;
10478 }
10479
10480 /* Return the ia64 builtin for CODE. */
10481
10482 static tree
10483 ia64_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
10484 {
10485 if (code >= IA64_BUILTIN_max)
10486 return error_mark_node;
10487
10488 return ia64_builtins[code];
10489 }
10490
10491 /* For the HP-UX IA64 aggregate parameters are passed stored in the
10492 most significant bits of the stack slot. */
10493
10494 enum direction
10495 ia64_hpux_function_arg_padding (enum machine_mode mode, const_tree type)
10496 {
10497 /* Exception to normal case for structures/unions/etc. */
10498
10499 if (type && AGGREGATE_TYPE_P (type)
10500 && int_size_in_bytes (type) < UNITS_PER_WORD)
10501 return upward;
10502
10503 /* Fall back to the default. */
10504 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
10505 }
10506
10507 /* Emit text to declare externally defined variables and functions, because
10508 the Intel assembler does not support undefined externals. */
10509
10510 void
10511 ia64_asm_output_external (FILE *file, tree decl, const char *name)
10512 {
10513 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
10514 set in order to avoid putting out names that are never really
10515 used. */
10516 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
10517 {
10518 /* maybe_assemble_visibility will return 1 if the assembler
10519 visibility directive is output. */
10520 int need_visibility = ((*targetm.binds_local_p) (decl)
10521 && maybe_assemble_visibility (decl));
10522
10523 /* GNU as does not need anything here, but the HP linker does
10524 need something for external functions. */
10525 if ((TARGET_HPUX_LD || !TARGET_GNU_AS)
10526 && TREE_CODE (decl) == FUNCTION_DECL)
10527 (*targetm.asm_out.globalize_decl_name) (file, decl);
10528 else if (need_visibility && !TARGET_GNU_AS)
10529 (*targetm.asm_out.globalize_label) (file, name);
10530 }
10531 }
10532
10533 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
10534 modes of word_mode and larger. Rename the TFmode libfuncs using the
10535 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
10536 backward compatibility. */
10537
10538 static void
10539 ia64_init_libfuncs (void)
10540 {
10541 set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
10542 set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
10543 set_optab_libfunc (smod_optab, SImode, "__modsi3");
10544 set_optab_libfunc (umod_optab, SImode, "__umodsi3");
10545
10546 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
10547 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
10548 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
10549 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
10550 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
10551
10552 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
10553 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
10554 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
10555 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
10556 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
10557 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
10558
10559 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
10560 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
10561 set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad");
10562 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
10563 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
10564
10565 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
10566 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
10567 set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad");
10568 /* HP-UX 11.23 libc does not have a function for unsigned
10569 SImode-to-TFmode conversion. */
10570 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad");
10571 }
10572
10573 /* Rename all the TFmode libfuncs using the HPUX conventions. */
10574
10575 static void
10576 ia64_hpux_init_libfuncs (void)
10577 {
10578 ia64_init_libfuncs ();
10579
10580 /* The HP SI millicode division and mod functions expect DI arguments.
10581 By turning them off completely we avoid using both libgcc and the
10582 non-standard millicode routines and use the HP DI millicode routines
10583 instead. */
10584
10585 set_optab_libfunc (sdiv_optab, SImode, 0);
10586 set_optab_libfunc (udiv_optab, SImode, 0);
10587 set_optab_libfunc (smod_optab, SImode, 0);
10588 set_optab_libfunc (umod_optab, SImode, 0);
10589
10590 set_optab_libfunc (sdiv_optab, DImode, "__milli_divI");
10591 set_optab_libfunc (udiv_optab, DImode, "__milli_divU");
10592 set_optab_libfunc (smod_optab, DImode, "__milli_remI");
10593 set_optab_libfunc (umod_optab, DImode, "__milli_remU");
10594
10595 /* HP-UX libc has TF min/max/abs routines in it. */
10596 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
10597 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
10598 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
10599
10600 /* ia64_expand_compare uses this. */
10601 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
10602
10603 /* These should never be used. */
10604 set_optab_libfunc (eq_optab, TFmode, 0);
10605 set_optab_libfunc (ne_optab, TFmode, 0);
10606 set_optab_libfunc (gt_optab, TFmode, 0);
10607 set_optab_libfunc (ge_optab, TFmode, 0);
10608 set_optab_libfunc (lt_optab, TFmode, 0);
10609 set_optab_libfunc (le_optab, TFmode, 0);
10610 }
10611
10612 /* Rename the division and modulus functions in VMS. */
10613
10614 static void
10615 ia64_vms_init_libfuncs (void)
10616 {
10617 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10618 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10619 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10620 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10621 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10622 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10623 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10624 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10625 abort_libfunc = init_one_libfunc ("decc$abort");
10626 memcmp_libfunc = init_one_libfunc ("decc$memcmp");
10627 #ifdef MEM_LIBFUNCS_INIT
10628 MEM_LIBFUNCS_INIT;
10629 #endif
10630 }
10631
10632 /* Rename the TFmode libfuncs available from soft-fp in glibc using
10633 the HPUX conventions. */
10634
10635 static void
10636 ia64_sysv4_init_libfuncs (void)
10637 {
10638 ia64_init_libfuncs ();
10639
10640 /* These functions are not part of the HPUX TFmode interface. We
10641 use them instead of _U_Qfcmp, which doesn't work the way we
10642 expect. */
10643 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
10644 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
10645 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
10646 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
10647 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
10648 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
10649
10650 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
10651 glibc doesn't have them. */
10652 }
10653
10654 /* Use soft-fp. */
10655
10656 static void
10657 ia64_soft_fp_init_libfuncs (void)
10658 {
10659 }
10660
10661 static bool
10662 ia64_vms_valid_pointer_mode (enum machine_mode mode)
10663 {
10664 return (mode == SImode || mode == DImode);
10665 }
10666 \f
10667 /* For HPUX, it is illegal to have relocations in shared segments. */
10668
10669 static int
10670 ia64_hpux_reloc_rw_mask (void)
10671 {
10672 return 3;
10673 }
10674
10675 /* For others, relax this so that relocations to local data goes in
10676 read-only segments, but we still cannot allow global relocations
10677 in read-only segments. */
10678
10679 static int
10680 ia64_reloc_rw_mask (void)
10681 {
10682 return flag_pic ? 3 : 2;
10683 }
10684
10685 /* Return the section to use for X. The only special thing we do here
10686 is to honor small data. */
10687
10688 static section *
10689 ia64_select_rtx_section (enum machine_mode mode, rtx x,
10690 unsigned HOST_WIDE_INT align)
10691 {
10692 if (GET_MODE_SIZE (mode) > 0
10693 && GET_MODE_SIZE (mode) <= ia64_section_threshold
10694 && !TARGET_NO_SDATA)
10695 return sdata_section;
10696 else
10697 return default_elf_select_rtx_section (mode, x, align);
10698 }
10699
10700 static unsigned int
10701 ia64_section_type_flags (tree decl, const char *name, int reloc)
10702 {
10703 unsigned int flags = 0;
10704
10705 if (strcmp (name, ".sdata") == 0
10706 || strncmp (name, ".sdata.", 7) == 0
10707 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
10708 || strncmp (name, ".sdata2.", 8) == 0
10709 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
10710 || strcmp (name, ".sbss") == 0
10711 || strncmp (name, ".sbss.", 6) == 0
10712 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
10713 flags = SECTION_SMALL;
10714
10715 flags |= default_section_type_flags (decl, name, reloc);
10716 return flags;
10717 }
10718
10719 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
10720 structure type and that the address of that type should be passed
10721 in out0, rather than in r8. */
10722
10723 static bool
10724 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
10725 {
10726 tree ret_type = TREE_TYPE (fntype);
10727
10728 /* The Itanium C++ ABI requires that out0, rather than r8, be used
10729 as the structure return address parameter, if the return value
10730 type has a non-trivial copy constructor or destructor. It is not
10731 clear if this same convention should be used for other
10732 programming languages. Until G++ 3.4, we incorrectly used r8 for
10733 these return values. */
10734 return (abi_version_at_least (2)
10735 && ret_type
10736 && TYPE_MODE (ret_type) == BLKmode
10737 && TREE_ADDRESSABLE (ret_type)
10738 && strcmp (lang_hooks.name, "GNU C++") == 0);
10739 }
10740
10741 /* Output the assembler code for a thunk function. THUNK_DECL is the
10742 declaration for the thunk function itself, FUNCTION is the decl for
10743 the target function. DELTA is an immediate constant offset to be
10744 added to THIS. If VCALL_OFFSET is nonzero, the word at
10745 *(*this + vcall_offset) should be added to THIS. */
10746
10747 static void
10748 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10749 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10750 tree function)
10751 {
10752 rtx this_rtx, funexp;
10753 rtx_insn *insn;
10754 unsigned int this_parmno;
10755 unsigned int this_regno;
10756 rtx delta_rtx;
10757
10758 reload_completed = 1;
10759 epilogue_completed = 1;
10760
10761 /* Set things up as ia64_expand_prologue might. */
10762 last_scratch_gr_reg = 15;
10763
10764 memset (&current_frame_info, 0, sizeof (current_frame_info));
10765 current_frame_info.spill_cfa_off = -16;
10766 current_frame_info.n_input_regs = 1;
10767 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
10768
10769 /* Mark the end of the (empty) prologue. */
10770 emit_note (NOTE_INSN_PROLOGUE_END);
10771
10772 /* Figure out whether "this" will be the first parameter (the
10773 typical case) or the second parameter (as happens when the
10774 virtual function returns certain class objects). */
10775 this_parmno
10776 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
10777 ? 1 : 0);
10778 this_regno = IN_REG (this_parmno);
10779 if (!TARGET_REG_NAMES)
10780 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
10781
10782 this_rtx = gen_rtx_REG (Pmode, this_regno);
10783
10784 /* Apply the constant offset, if required. */
10785 delta_rtx = GEN_INT (delta);
10786 if (TARGET_ILP32)
10787 {
10788 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
10789 REG_POINTER (tmp) = 1;
10790 if (delta && satisfies_constraint_I (delta_rtx))
10791 {
10792 emit_insn (gen_ptr_extend_plus_imm (this_rtx, tmp, delta_rtx));
10793 delta = 0;
10794 }
10795 else
10796 emit_insn (gen_ptr_extend (this_rtx, tmp));
10797 }
10798 if (delta)
10799 {
10800 if (!satisfies_constraint_I (delta_rtx))
10801 {
10802 rtx tmp = gen_rtx_REG (Pmode, 2);
10803 emit_move_insn (tmp, delta_rtx);
10804 delta_rtx = tmp;
10805 }
10806 emit_insn (gen_adddi3 (this_rtx, this_rtx, delta_rtx));
10807 }
10808
10809 /* Apply the offset from the vtable, if required. */
10810 if (vcall_offset)
10811 {
10812 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
10813 rtx tmp = gen_rtx_REG (Pmode, 2);
10814
10815 if (TARGET_ILP32)
10816 {
10817 rtx t = gen_rtx_REG (ptr_mode, 2);
10818 REG_POINTER (t) = 1;
10819 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this_rtx));
10820 if (satisfies_constraint_I (vcall_offset_rtx))
10821 {
10822 emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx));
10823 vcall_offset = 0;
10824 }
10825 else
10826 emit_insn (gen_ptr_extend (tmp, t));
10827 }
10828 else
10829 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
10830
10831 if (vcall_offset)
10832 {
10833 if (!satisfies_constraint_J (vcall_offset_rtx))
10834 {
10835 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
10836 emit_move_insn (tmp2, vcall_offset_rtx);
10837 vcall_offset_rtx = tmp2;
10838 }
10839 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
10840 }
10841
10842 if (TARGET_ILP32)
10843 emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp)));
10844 else
10845 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
10846
10847 emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
10848 }
10849
10850 /* Generate a tail call to the target function. */
10851 if (! TREE_USED (function))
10852 {
10853 assemble_external (function);
10854 TREE_USED (function) = 1;
10855 }
10856 funexp = XEXP (DECL_RTL (function), 0);
10857 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
10858 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
10859 insn = get_last_insn ();
10860 SIBLING_CALL_P (insn) = 1;
10861
10862 /* Code generation for calls relies on splitting. */
10863 reload_completed = 1;
10864 epilogue_completed = 1;
10865 try_split (PATTERN (insn), insn, 0);
10866
10867 emit_barrier ();
10868
10869 /* Run just enough of rest_of_compilation to get the insns emitted.
10870 There's not really enough bulk here to make other passes such as
10871 instruction scheduling worth while. Note that use_thunk calls
10872 assemble_start_function and assemble_end_function. */
10873
10874 emit_all_insn_group_barriers (NULL);
10875 insn = get_insns ();
10876 shorten_branches (insn);
10877 final_start_function (insn, file, 1);
10878 final (insn, file, 1);
10879 final_end_function ();
10880
10881 reload_completed = 0;
10882 epilogue_completed = 0;
10883 }
10884
10885 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10886
10887 static rtx
10888 ia64_struct_value_rtx (tree fntype,
10889 int incoming ATTRIBUTE_UNUSED)
10890 {
10891 if (TARGET_ABI_OPEN_VMS ||
10892 (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype)))
10893 return NULL_RTX;
10894 return gen_rtx_REG (Pmode, GR_REG (8));
10895 }
10896
10897 static bool
10898 ia64_scalar_mode_supported_p (enum machine_mode mode)
10899 {
10900 switch (mode)
10901 {
10902 case QImode:
10903 case HImode:
10904 case SImode:
10905 case DImode:
10906 case TImode:
10907 return true;
10908
10909 case SFmode:
10910 case DFmode:
10911 case XFmode:
10912 case RFmode:
10913 return true;
10914
10915 case TFmode:
10916 return true;
10917
10918 default:
10919 return false;
10920 }
10921 }
10922
10923 static bool
10924 ia64_vector_mode_supported_p (enum machine_mode mode)
10925 {
10926 switch (mode)
10927 {
10928 case V8QImode:
10929 case V4HImode:
10930 case V2SImode:
10931 return true;
10932
10933 case V2SFmode:
10934 return true;
10935
10936 default:
10937 return false;
10938 }
10939 }
10940
10941 /* Implement the FUNCTION_PROFILER macro. */
10942
10943 void
10944 ia64_output_function_profiler (FILE *file, int labelno)
10945 {
10946 bool indirect_call;
10947
10948 /* If the function needs a static chain and the static chain
10949 register is r15, we use an indirect call so as to bypass
10950 the PLT stub in case the executable is dynamically linked,
10951 because the stub clobbers r15 as per 5.3.6 of the psABI.
10952 We don't need to do that in non canonical PIC mode. */
10953
10954 if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC)
10955 {
10956 gcc_assert (STATIC_CHAIN_REGNUM == 15);
10957 indirect_call = true;
10958 }
10959 else
10960 indirect_call = false;
10961
10962 if (TARGET_GNU_AS)
10963 fputs ("\t.prologue 4, r40\n", file);
10964 else
10965 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file);
10966 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file);
10967
10968 if (NO_PROFILE_COUNTERS)
10969 fputs ("\tmov out3 = r0\n", file);
10970 else
10971 {
10972 char buf[20];
10973 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10974
10975 if (TARGET_AUTO_PIC)
10976 fputs ("\tmovl out3 = @gprel(", file);
10977 else
10978 fputs ("\taddl out3 = @ltoff(", file);
10979 assemble_name (file, buf);
10980 if (TARGET_AUTO_PIC)
10981 fputs (")\n", file);
10982 else
10983 fputs ("), r1\n", file);
10984 }
10985
10986 if (indirect_call)
10987 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file);
10988 fputs ("\t;;\n", file);
10989
10990 fputs ("\t.save rp, r42\n", file);
10991 fputs ("\tmov out2 = b0\n", file);
10992 if (indirect_call)
10993 fputs ("\tld8 r14 = [r14]\n\t;;\n", file);
10994 fputs ("\t.body\n", file);
10995 fputs ("\tmov out1 = r1\n", file);
10996 if (indirect_call)
10997 {
10998 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file);
10999 fputs ("\tmov b6 = r16\n", file);
11000 fputs ("\tld8 r1 = [r14]\n", file);
11001 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file);
11002 }
11003 else
11004 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file);
11005 }
11006
11007 static GTY(()) rtx mcount_func_rtx;
11008 static rtx
11009 gen_mcount_func_rtx (void)
11010 {
11011 if (!mcount_func_rtx)
11012 mcount_func_rtx = init_one_libfunc ("_mcount");
11013 return mcount_func_rtx;
11014 }
11015
11016 void
11017 ia64_profile_hook (int labelno)
11018 {
11019 rtx label, ip;
11020
11021 if (NO_PROFILE_COUNTERS)
11022 label = const0_rtx;
11023 else
11024 {
11025 char buf[30];
11026 const char *label_name;
11027 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
11028 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
11029 label = gen_rtx_SYMBOL_REF (Pmode, label_name);
11030 SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL;
11031 }
11032 ip = gen_reg_rtx (Pmode);
11033 emit_insn (gen_ip_value (ip));
11034 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL,
11035 VOIDmode, 3,
11036 gen_rtx_REG (Pmode, BR_REG (0)), Pmode,
11037 ip, Pmode,
11038 label, Pmode);
11039 }
11040
11041 /* Return the mangling of TYPE if it is an extended fundamental type. */
11042
11043 static const char *
11044 ia64_mangle_type (const_tree type)
11045 {
11046 type = TYPE_MAIN_VARIANT (type);
11047
11048 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
11049 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
11050 return NULL;
11051
11052 /* On HP-UX, "long double" is mangled as "e" so __float128 is
11053 mangled as "e". */
11054 if (!TARGET_HPUX && TYPE_MODE (type) == TFmode)
11055 return "g";
11056 /* On HP-UX, "e" is not available as a mangling of __float80 so use
11057 an extended mangling. Elsewhere, "e" is available since long
11058 double is 80 bits. */
11059 if (TYPE_MODE (type) == XFmode)
11060 return TARGET_HPUX ? "u9__float80" : "e";
11061 if (TYPE_MODE (type) == RFmode)
11062 return "u7__fpreg";
11063 return NULL;
11064 }
11065
11066 /* Return the diagnostic message string if conversion from FROMTYPE to
11067 TOTYPE is not allowed, NULL otherwise. */
11068 static const char *
11069 ia64_invalid_conversion (const_tree fromtype, const_tree totype)
11070 {
11071 /* Reject nontrivial conversion to or from __fpreg. */
11072 if (TYPE_MODE (fromtype) == RFmode
11073 && TYPE_MODE (totype) != RFmode
11074 && TYPE_MODE (totype) != VOIDmode)
11075 return N_("invalid conversion from %<__fpreg%>");
11076 if (TYPE_MODE (totype) == RFmode
11077 && TYPE_MODE (fromtype) != RFmode)
11078 return N_("invalid conversion to %<__fpreg%>");
11079 return NULL;
11080 }
11081
11082 /* Return the diagnostic message string if the unary operation OP is
11083 not permitted on TYPE, NULL otherwise. */
11084 static const char *
11085 ia64_invalid_unary_op (int op, const_tree type)
11086 {
11087 /* Reject operations on __fpreg other than unary + or &. */
11088 if (TYPE_MODE (type) == RFmode
11089 && op != CONVERT_EXPR
11090 && op != ADDR_EXPR)
11091 return N_("invalid operation on %<__fpreg%>");
11092 return NULL;
11093 }
11094
11095 /* Return the diagnostic message string if the binary operation OP is
11096 not permitted on TYPE1 and TYPE2, NULL otherwise. */
11097 static const char *
11098 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2)
11099 {
11100 /* Reject operations on __fpreg. */
11101 if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode)
11102 return N_("invalid operation on %<__fpreg%>");
11103 return NULL;
11104 }
11105
11106 /* HP-UX version_id attribute.
11107 For object foo, if the version_id is set to 1234 put out an alias
11108 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
11109 other than an alias statement because it is an illegal symbol name. */
11110
11111 static tree
11112 ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED,
11113 tree name ATTRIBUTE_UNUSED,
11114 tree args,
11115 int flags ATTRIBUTE_UNUSED,
11116 bool *no_add_attrs)
11117 {
11118 tree arg = TREE_VALUE (args);
11119
11120 if (TREE_CODE (arg) != STRING_CST)
11121 {
11122 error("version attribute is not a string");
11123 *no_add_attrs = true;
11124 return NULL_TREE;
11125 }
11126 return NULL_TREE;
11127 }
11128
11129 /* Target hook for c_mode_for_suffix. */
11130
11131 static enum machine_mode
11132 ia64_c_mode_for_suffix (char suffix)
11133 {
11134 if (suffix == 'q')
11135 return TFmode;
11136 if (suffix == 'w')
11137 return XFmode;
11138
11139 return VOIDmode;
11140 }
11141
11142 static GTY(()) rtx ia64_dconst_0_5_rtx;
11143
11144 rtx
11145 ia64_dconst_0_5 (void)
11146 {
11147 if (! ia64_dconst_0_5_rtx)
11148 {
11149 REAL_VALUE_TYPE rv;
11150 real_from_string (&rv, "0.5");
11151 ia64_dconst_0_5_rtx = const_double_from_real_value (rv, DFmode);
11152 }
11153 return ia64_dconst_0_5_rtx;
11154 }
11155
11156 static GTY(()) rtx ia64_dconst_0_375_rtx;
11157
11158 rtx
11159 ia64_dconst_0_375 (void)
11160 {
11161 if (! ia64_dconst_0_375_rtx)
11162 {
11163 REAL_VALUE_TYPE rv;
11164 real_from_string (&rv, "0.375");
11165 ia64_dconst_0_375_rtx = const_double_from_real_value (rv, DFmode);
11166 }
11167 return ia64_dconst_0_375_rtx;
11168 }
11169
11170 static enum machine_mode
11171 ia64_get_reg_raw_mode (int regno)
11172 {
11173 if (FR_REGNO_P (regno))
11174 return XFmode;
11175 return default_get_reg_raw_mode(regno);
11176 }
11177
11178 /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. ??? Might not be needed
11179 anymore. */
11180
11181 bool
11182 ia64_member_type_forces_blk (const_tree, enum machine_mode mode)
11183 {
11184 return TARGET_HPUX && mode == TFmode;
11185 }
11186
11187 /* Always default to .text section until HP-UX linker is fixed. */
11188
11189 ATTRIBUTE_UNUSED static section *
11190 ia64_hpux_function_section (tree decl ATTRIBUTE_UNUSED,
11191 enum node_frequency freq ATTRIBUTE_UNUSED,
11192 bool startup ATTRIBUTE_UNUSED,
11193 bool exit ATTRIBUTE_UNUSED)
11194 {
11195 return NULL;
11196 }
11197 \f
11198 /* Construct (set target (vec_select op0 (parallel perm))) and
11199 return true if that's a valid instruction in the active ISA. */
11200
11201 static bool
11202 expand_vselect (rtx target, rtx op0, const unsigned char *perm, unsigned nelt)
11203 {
11204 rtx rperm[MAX_VECT_LEN], x;
11205 unsigned i;
11206
11207 for (i = 0; i < nelt; ++i)
11208 rperm[i] = GEN_INT (perm[i]);
11209
11210 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
11211 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
11212 x = gen_rtx_SET (VOIDmode, target, x);
11213
11214 x = emit_insn (x);
11215 if (recog_memoized (x) < 0)
11216 {
11217 remove_insn (x);
11218 return false;
11219 }
11220 return true;
11221 }
11222
11223 /* Similar, but generate a vec_concat from op0 and op1 as well. */
11224
11225 static bool
11226 expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
11227 const unsigned char *perm, unsigned nelt)
11228 {
11229 enum machine_mode v2mode;
11230 rtx x;
11231
11232 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
11233 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
11234 return expand_vselect (target, x, perm, nelt);
11235 }
11236
11237 /* Try to expand a no-op permutation. */
11238
11239 static bool
11240 expand_vec_perm_identity (struct expand_vec_perm_d *d)
11241 {
11242 unsigned i, nelt = d->nelt;
11243
11244 for (i = 0; i < nelt; ++i)
11245 if (d->perm[i] != i)
11246 return false;
11247
11248 if (!d->testing_p)
11249 emit_move_insn (d->target, d->op0);
11250
11251 return true;
11252 }
11253
11254 /* Try to expand D via a shrp instruction. */
11255
11256 static bool
11257 expand_vec_perm_shrp (struct expand_vec_perm_d *d)
11258 {
11259 unsigned i, nelt = d->nelt, shift, mask;
11260 rtx tmp, hi, lo;
11261
11262 /* ??? Don't force V2SFmode into the integer registers. */
11263 if (d->vmode == V2SFmode)
11264 return false;
11265
11266 mask = (d->one_operand_p ? nelt - 1 : 2 * nelt - 1);
11267
11268 shift = d->perm[0];
11269 if (BYTES_BIG_ENDIAN && shift > nelt)
11270 return false;
11271
11272 for (i = 1; i < nelt; ++i)
11273 if (d->perm[i] != ((shift + i) & mask))
11274 return false;
11275
11276 if (d->testing_p)
11277 return true;
11278
11279 hi = shift < nelt ? d->op1 : d->op0;
11280 lo = shift < nelt ? d->op0 : d->op1;
11281
11282 shift %= nelt;
11283
11284 shift *= GET_MODE_UNIT_SIZE (d->vmode) * BITS_PER_UNIT;
11285
11286 /* We've eliminated the shift 0 case via expand_vec_perm_identity. */
11287 gcc_assert (IN_RANGE (shift, 1, 63));
11288
11289 /* Recall that big-endian elements are numbered starting at the top of
11290 the register. Ideally we'd have a shift-left-pair. But since we
11291 don't, convert to a shift the other direction. */
11292 if (BYTES_BIG_ENDIAN)
11293 shift = 64 - shift;
11294
11295 tmp = gen_reg_rtx (DImode);
11296 hi = gen_lowpart (DImode, hi);
11297 lo = gen_lowpart (DImode, lo);
11298 emit_insn (gen_shrp (tmp, hi, lo, GEN_INT (shift)));
11299
11300 emit_move_insn (d->target, gen_lowpart (d->vmode, tmp));
11301 return true;
11302 }
11303
11304 /* Try to instantiate D in a single instruction. */
11305
11306 static bool
11307 expand_vec_perm_1 (struct expand_vec_perm_d *d)
11308 {
11309 unsigned i, nelt = d->nelt;
11310 unsigned char perm2[MAX_VECT_LEN];
11311
11312 /* Try single-operand selections. */
11313 if (d->one_operand_p)
11314 {
11315 if (expand_vec_perm_identity (d))
11316 return true;
11317 if (expand_vselect (d->target, d->op0, d->perm, nelt))
11318 return true;
11319 }
11320
11321 /* Try two operand selections. */
11322 if (expand_vselect_vconcat (d->target, d->op0, d->op1, d->perm, nelt))
11323 return true;
11324
11325 /* Recognize interleave style patterns with reversed operands. */
11326 if (!d->one_operand_p)
11327 {
11328 for (i = 0; i < nelt; ++i)
11329 {
11330 unsigned e = d->perm[i];
11331 if (e >= nelt)
11332 e -= nelt;
11333 else
11334 e += nelt;
11335 perm2[i] = e;
11336 }
11337
11338 if (expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
11339 return true;
11340 }
11341
11342 if (expand_vec_perm_shrp (d))
11343 return true;
11344
11345 /* ??? Look for deposit-like permutations where most of the result
11346 comes from one vector unchanged and the rest comes from a
11347 sequential hunk of the other vector. */
11348
11349 return false;
11350 }
11351
11352 /* Pattern match broadcast permutations. */
11353
11354 static bool
11355 expand_vec_perm_broadcast (struct expand_vec_perm_d *d)
11356 {
11357 unsigned i, elt, nelt = d->nelt;
11358 unsigned char perm2[2];
11359 rtx temp;
11360 bool ok;
11361
11362 if (!d->one_operand_p)
11363 return false;
11364
11365 elt = d->perm[0];
11366 for (i = 1; i < nelt; ++i)
11367 if (d->perm[i] != elt)
11368 return false;
11369
11370 switch (d->vmode)
11371 {
11372 case V2SImode:
11373 case V2SFmode:
11374 /* Implementable by interleave. */
11375 perm2[0] = elt;
11376 perm2[1] = elt + 2;
11377 ok = expand_vselect_vconcat (d->target, d->op0, d->op0, perm2, 2);
11378 gcc_assert (ok);
11379 break;
11380
11381 case V8QImode:
11382 /* Implementable by extract + broadcast. */
11383 if (BYTES_BIG_ENDIAN)
11384 elt = 7 - elt;
11385 elt *= BITS_PER_UNIT;
11386 temp = gen_reg_rtx (DImode);
11387 emit_insn (gen_extzv (temp, gen_lowpart (DImode, d->op0),
11388 GEN_INT (8), GEN_INT (elt)));
11389 emit_insn (gen_mux1_brcst_qi (d->target, gen_lowpart (QImode, temp)));
11390 break;
11391
11392 case V4HImode:
11393 /* Should have been matched directly by vec_select. */
11394 default:
11395 gcc_unreachable ();
11396 }
11397
11398 return true;
11399 }
11400
11401 /* A subroutine of ia64_expand_vec_perm_const_1. Try to simplify a
11402 two vector permutation into a single vector permutation by using
11403 an interleave operation to merge the vectors. */
11404
11405 static bool
11406 expand_vec_perm_interleave_2 (struct expand_vec_perm_d *d)
11407 {
11408 struct expand_vec_perm_d dremap, dfinal;
11409 unsigned char remap[2 * MAX_VECT_LEN];
11410 unsigned contents, i, nelt, nelt2;
11411 unsigned h0, h1, h2, h3;
11412 rtx_insn *seq;
11413 bool ok;
11414
11415 if (d->one_operand_p)
11416 return false;
11417
11418 nelt = d->nelt;
11419 nelt2 = nelt / 2;
11420
11421 /* Examine from whence the elements come. */
11422 contents = 0;
11423 for (i = 0; i < nelt; ++i)
11424 contents |= 1u << d->perm[i];
11425
11426 memset (remap, 0xff, sizeof (remap));
11427 dremap = *d;
11428
11429 h0 = (1u << nelt2) - 1;
11430 h1 = h0 << nelt2;
11431 h2 = h0 << nelt;
11432 h3 = h0 << (nelt + nelt2);
11433
11434 if ((contents & (h0 | h2)) == contents) /* punpck even halves */
11435 {
11436 for (i = 0; i < nelt; ++i)
11437 {
11438 unsigned which = i / 2 + (i & 1 ? nelt : 0);
11439 remap[which] = i;
11440 dremap.perm[i] = which;
11441 }
11442 }
11443 else if ((contents & (h1 | h3)) == contents) /* punpck odd halves */
11444 {
11445 for (i = 0; i < nelt; ++i)
11446 {
11447 unsigned which = i / 2 + nelt2 + (i & 1 ? nelt : 0);
11448 remap[which] = i;
11449 dremap.perm[i] = which;
11450 }
11451 }
11452 else if ((contents & 0x5555) == contents) /* mix even elements */
11453 {
11454 for (i = 0; i < nelt; ++i)
11455 {
11456 unsigned which = (i & ~1) + (i & 1 ? nelt : 0);
11457 remap[which] = i;
11458 dremap.perm[i] = which;
11459 }
11460 }
11461 else if ((contents & 0xaaaa) == contents) /* mix odd elements */
11462 {
11463 for (i = 0; i < nelt; ++i)
11464 {
11465 unsigned which = (i | 1) + (i & 1 ? nelt : 0);
11466 remap[which] = i;
11467 dremap.perm[i] = which;
11468 }
11469 }
11470 else if (floor_log2 (contents) - ctz_hwi (contents) < (int)nelt) /* shrp */
11471 {
11472 unsigned shift = ctz_hwi (contents);
11473 for (i = 0; i < nelt; ++i)
11474 {
11475 unsigned which = (i + shift) & (2 * nelt - 1);
11476 remap[which] = i;
11477 dremap.perm[i] = which;
11478 }
11479 }
11480 else
11481 return false;
11482
11483 /* Use the remapping array set up above to move the elements from their
11484 swizzled locations into their final destinations. */
11485 dfinal = *d;
11486 for (i = 0; i < nelt; ++i)
11487 {
11488 unsigned e = remap[d->perm[i]];
11489 gcc_assert (e < nelt);
11490 dfinal.perm[i] = e;
11491 }
11492 dfinal.op0 = gen_reg_rtx (dfinal.vmode);
11493 dfinal.op1 = dfinal.op0;
11494 dfinal.one_operand_p = true;
11495 dremap.target = dfinal.op0;
11496
11497 /* Test if the final remap can be done with a single insn. For V4HImode
11498 this *will* succeed. For V8QImode or V2SImode it may not. */
11499 start_sequence ();
11500 ok = expand_vec_perm_1 (&dfinal);
11501 seq = get_insns ();
11502 end_sequence ();
11503 if (!ok)
11504 return false;
11505 if (d->testing_p)
11506 return true;
11507
11508 ok = expand_vec_perm_1 (&dremap);
11509 gcc_assert (ok);
11510
11511 emit_insn (seq);
11512 return true;
11513 }
11514
11515 /* A subroutine of ia64_expand_vec_perm_const_1. Emit a full V4HImode
11516 constant permutation via two mux2 and a merge. */
11517
11518 static bool
11519 expand_vec_perm_v4hi_5 (struct expand_vec_perm_d *d)
11520 {
11521 unsigned char perm2[4];
11522 rtx rmask[4];
11523 unsigned i;
11524 rtx t0, t1, mask, x;
11525 bool ok;
11526
11527 if (d->vmode != V4HImode || d->one_operand_p)
11528 return false;
11529 if (d->testing_p)
11530 return true;
11531
11532 for (i = 0; i < 4; ++i)
11533 {
11534 perm2[i] = d->perm[i] & 3;
11535 rmask[i] = (d->perm[i] & 4 ? const0_rtx : constm1_rtx);
11536 }
11537 mask = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmask));
11538 mask = force_reg (V4HImode, mask);
11539
11540 t0 = gen_reg_rtx (V4HImode);
11541 t1 = gen_reg_rtx (V4HImode);
11542
11543 ok = expand_vselect (t0, d->op0, perm2, 4);
11544 gcc_assert (ok);
11545 ok = expand_vselect (t1, d->op1, perm2, 4);
11546 gcc_assert (ok);
11547
11548 x = gen_rtx_AND (V4HImode, mask, t0);
11549 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
11550
11551 x = gen_rtx_NOT (V4HImode, mask);
11552 x = gen_rtx_AND (V4HImode, x, t1);
11553 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
11554
11555 x = gen_rtx_IOR (V4HImode, t0, t1);
11556 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
11557
11558 return true;
11559 }
11560
11561 /* The guts of ia64_expand_vec_perm_const, also used by the ok hook.
11562 With all of the interface bits taken care of, perform the expansion
11563 in D and return true on success. */
11564
11565 static bool
11566 ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
11567 {
11568 if (expand_vec_perm_1 (d))
11569 return true;
11570 if (expand_vec_perm_broadcast (d))
11571 return true;
11572 if (expand_vec_perm_interleave_2 (d))
11573 return true;
11574 if (expand_vec_perm_v4hi_5 (d))
11575 return true;
11576 return false;
11577 }
11578
11579 bool
11580 ia64_expand_vec_perm_const (rtx operands[4])
11581 {
11582 struct expand_vec_perm_d d;
11583 unsigned char perm[MAX_VECT_LEN];
11584 int i, nelt, which;
11585 rtx sel;
11586
11587 d.target = operands[0];
11588 d.op0 = operands[1];
11589 d.op1 = operands[2];
11590 sel = operands[3];
11591
11592 d.vmode = GET_MODE (d.target);
11593 gcc_assert (VECTOR_MODE_P (d.vmode));
11594 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
11595 d.testing_p = false;
11596
11597 gcc_assert (GET_CODE (sel) == CONST_VECTOR);
11598 gcc_assert (XVECLEN (sel, 0) == nelt);
11599 gcc_checking_assert (sizeof (d.perm) == sizeof (perm));
11600
11601 for (i = which = 0; i < nelt; ++i)
11602 {
11603 rtx e = XVECEXP (sel, 0, i);
11604 int ei = INTVAL (e) & (2 * nelt - 1);
11605
11606 which |= (ei < nelt ? 1 : 2);
11607 d.perm[i] = ei;
11608 perm[i] = ei;
11609 }
11610
11611 switch (which)
11612 {
11613 default:
11614 gcc_unreachable();
11615
11616 case 3:
11617 if (!rtx_equal_p (d.op0, d.op1))
11618 {
11619 d.one_operand_p = false;
11620 break;
11621 }
11622
11623 /* The elements of PERM do not suggest that only the first operand
11624 is used, but both operands are identical. Allow easier matching
11625 of the permutation by folding the permutation into the single
11626 input vector. */
11627 for (i = 0; i < nelt; ++i)
11628 if (d.perm[i] >= nelt)
11629 d.perm[i] -= nelt;
11630 /* FALLTHRU */
11631
11632 case 1:
11633 d.op1 = d.op0;
11634 d.one_operand_p = true;
11635 break;
11636
11637 case 2:
11638 for (i = 0; i < nelt; ++i)
11639 d.perm[i] -= nelt;
11640 d.op0 = d.op1;
11641 d.one_operand_p = true;
11642 break;
11643 }
11644
11645 if (ia64_expand_vec_perm_const_1 (&d))
11646 return true;
11647
11648 /* If the mask says both arguments are needed, but they are the same,
11649 the above tried to expand with one_operand_p true. If that didn't
11650 work, retry with one_operand_p false, as that's what we used in _ok. */
11651 if (which == 3 && d.one_operand_p)
11652 {
11653 memcpy (d.perm, perm, sizeof (perm));
11654 d.one_operand_p = false;
11655 return ia64_expand_vec_perm_const_1 (&d);
11656 }
11657
11658 return false;
11659 }
11660
11661 /* Implement targetm.vectorize.vec_perm_const_ok. */
11662
11663 static bool
11664 ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
11665 const unsigned char *sel)
11666 {
11667 struct expand_vec_perm_d d;
11668 unsigned int i, nelt, which;
11669 bool ret;
11670
11671 d.vmode = vmode;
11672 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
11673 d.testing_p = true;
11674
11675 /* Extract the values from the vector CST into the permutation
11676 array in D. */
11677 memcpy (d.perm, sel, nelt);
11678 for (i = which = 0; i < nelt; ++i)
11679 {
11680 unsigned char e = d.perm[i];
11681 gcc_assert (e < 2 * nelt);
11682 which |= (e < nelt ? 1 : 2);
11683 }
11684
11685 /* For all elements from second vector, fold the elements to first. */
11686 if (which == 2)
11687 for (i = 0; i < nelt; ++i)
11688 d.perm[i] -= nelt;
11689
11690 /* Check whether the mask can be applied to the vector type. */
11691 d.one_operand_p = (which != 3);
11692
11693 /* Otherwise we have to go through the motions and see if we can
11694 figure out how to generate the requested permutation. */
11695 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
11696 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
11697 if (!d.one_operand_p)
11698 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
11699
11700 start_sequence ();
11701 ret = ia64_expand_vec_perm_const_1 (&d);
11702 end_sequence ();
11703
11704 return ret;
11705 }
11706
11707 void
11708 ia64_expand_vec_setv2sf (rtx operands[3])
11709 {
11710 struct expand_vec_perm_d d;
11711 unsigned int which;
11712 bool ok;
11713
11714 d.target = operands[0];
11715 d.op0 = operands[0];
11716 d.op1 = gen_reg_rtx (V2SFmode);
11717 d.vmode = V2SFmode;
11718 d.nelt = 2;
11719 d.one_operand_p = false;
11720 d.testing_p = false;
11721
11722 which = INTVAL (operands[2]);
11723 gcc_assert (which <= 1);
11724 d.perm[0] = 1 - which;
11725 d.perm[1] = which + 2;
11726
11727 emit_insn (gen_fpack (d.op1, operands[1], CONST0_RTX (SFmode)));
11728
11729 ok = ia64_expand_vec_perm_const_1 (&d);
11730 gcc_assert (ok);
11731 }
11732
11733 void
11734 ia64_expand_vec_perm_even_odd (rtx target, rtx op0, rtx op1, int odd)
11735 {
11736 struct expand_vec_perm_d d;
11737 enum machine_mode vmode = GET_MODE (target);
11738 unsigned int i, nelt = GET_MODE_NUNITS (vmode);
11739 bool ok;
11740
11741 d.target = target;
11742 d.op0 = op0;
11743 d.op1 = op1;
11744 d.vmode = vmode;
11745 d.nelt = nelt;
11746 d.one_operand_p = false;
11747 d.testing_p = false;
11748
11749 for (i = 0; i < nelt; ++i)
11750 d.perm[i] = i * 2 + odd;
11751
11752 ok = ia64_expand_vec_perm_const_1 (&d);
11753 gcc_assert (ok);
11754 }
11755
11756 #include "gt-ia64.h"
Mirror of https://gcc.gnu.org/git/gcc.git